diff options
| author | John Keeping <john@metanate.com> | 2016-05-09 13:24:30 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-05-10 19:56:01 +0200 |
| commit | 57e41f3fb32a359753a3b2679c2502b2750bf6af (patch) | |
| tree | 97a44660539d2f62589856e9cd3232de4cdd0856 /sound/soc/codecs/es8328.h | |
| parent | ASoC: es8328: Move clock setup to hw_params (diff) | |
| download | linux-57e41f3fb32a359753a3b2679c2502b2750bf6af.tar.xz linux-57e41f3fb32a359753a3b2679c2502b2750bf6af.zip | |
ASoC: es8328: Fix ADC format setup
The ADCCONTROL4 and DACCONTROL1 registers are similar but not identical,
with the DACCONTROL1 having each field starting one bit higher than
ADCCONTROL4.
Instead of introducing a magic shift, add new constants for the values
in ADCCONTROL4 and use a second variable to setup the ADC.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/es8328.h')
| -rw-r--r-- | sound/soc/codecs/es8328.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sound/soc/codecs/es8328.h b/sound/soc/codecs/es8328.h index 156c748c89c7..5a4af014e516 100644 --- a/sound/soc/codecs/es8328.h +++ b/sound/soc/codecs/es8328.h @@ -84,7 +84,22 @@ int es8328_probe(struct device *dev, struct regmap *regmap); #define ES8328_ADCCONTROL1 0x09 #define ES8328_ADCCONTROL2 0x0a #define ES8328_ADCCONTROL3 0x0b + #define ES8328_ADCCONTROL4 0x0c +#define ES8328_ADCCONTROL4_ADCFORMAT_I2S (0 << 0) +#define ES8328_ADCCONTROL4_ADCFORMAT_LJUST (1 << 0) +#define ES8328_ADCCONTROL4_ADCFORMAT_RJUST (2 << 0) +#define ES8328_ADCCONTROL4_ADCFORMAT_PCM (3 << 0) +#define ES8328_ADCCONTROL4_ADCWL_24 (0 << 2) +#define ES8328_ADCCONTROL4_ADCWL_20 (1 << 2) +#define ES8328_ADCCONTROL4_ADCWL_18 (2 << 2) +#define ES8328_ADCCONTROL4_ADCWL_16 (3 << 2) +#define ES8328_ADCCONTROL4_ADCWL_32 (4 << 2) +#define ES8328_ADCCONTROL4_ADCLRP_I2S_POL_NORMAL (0 << 5) +#define ES8328_ADCCONTROL4_ADCLRP_I2S_POL_INV (1 << 5) +#define ES8328_ADCCONTROL4_ADCLRP_PCM_MSB_CLK2 (0 << 5) +#define ES8328_ADCCONTROL4_ADCLRP_PCM_MSB_CLK1 (1 << 5) + #define ES8328_ADCCONTROL5 0x0d #define ES8328_ADCCONTROL5_RATEMASK (0x1f << 0) |