diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2023-02-09 13:28:04 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-02-09 15:03:31 +0100 |
| commit | e7621434378c40b62ef858c14ae6415fb6469a8e (patch) | |
| tree | e14768707abca0b12346dcbc41e4d7631fd4ae5c /sound/soc/codecs/lpass-rx-macro.c | |
| parent | ASoC: codecs: lpass: register mclk after runtime pm (diff) | |
| download | linux-e7621434378c40b62ef858c14ae6415fb6469a8e.tar.xz linux-e7621434378c40b62ef858c14ae6415fb6469a8e.zip | |
ASoC: codecs: lpass: fix incorrect mclk rate
For some reason we ended up with incorrect mclk rate which should be
1920000 instead of 96000, So far we were getting lucky as the same clk
is set to 192000 by wsa and va macro. This issue is discovered when there
is no wsa macro active and only rx or tx path is tested.
Fix this by setting correct rate.
Fixes: c39667ddcfc5 ("ASoC: codecs: lpass-tx-macro: add support for lpass tx macro")
Fixes: af3d54b99764 ("ASoC: codecs: lpass-rx-macro: add support for lpass rx macro")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20230209122806.18923-7-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/lpass-rx-macro.c')
| -rw-r--r-- | sound/soc/codecs/lpass-rx-macro.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c index dd6970d5eb8d..8621cfabcf5b 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -366,7 +366,7 @@ #define CDC_RX_DSD1_CFG2 (0x0F8C) #define RX_MAX_OFFSET (0x0F8C) -#define MCLK_FREQ 9600000 +#define MCLK_FREQ 19200000 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ @@ -3579,7 +3579,7 @@ static int rx_macro_probe(struct platform_device *pdev) /* set MCLK and NPL rates */ clk_set_rate(rx->mclk, MCLK_FREQ); - clk_set_rate(rx->npl, 2 * MCLK_FREQ); + clk_set_rate(rx->npl, MCLK_FREQ); ret = clk_prepare_enable(rx->macro); if (ret) |