diff options
| author | David Lin <CTLIN0@nuvoton.com> | 2022-11-22 08:38:56 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-11-22 13:23:14 +0100 |
| commit | 7a37265046618b890adf7d7a1f9f1f5fbae908a7 (patch) | |
| tree | fb00305e81d93a63a8b17f2899f5c112af044b67 /sound/soc/codecs/nau8825.h | |
| parent | ASoC: nau8825: Adjust internal clock during jack detection (diff) | |
| download | linux-7a37265046618b890adf7d7a1f9f1f5fbae908a7.tar.xz linux-7a37265046618b890adf7d7a1f9f1f5fbae908a7.zip | |
ASoC: nau8825: Add a manually mechanism for detection failure
This patch is to use saradc to check the jack type when auto
detection is still failure.
Signed-off-by: David Lin <CTLIN0@nuvoton.com>
Link: https://lore.kernel.org/r/20221122073855.43024-2-CTLIN0@nuvoton.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/nau8825.h')
| -rw-r--r-- | sound/soc/codecs/nau8825.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index d84191a7beb2..0c3a446e0e1a 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -155,6 +155,8 @@ /* HSD_CTRL (0xc) */ #define NAU8825_HSD_AUTO_MODE (1 << 6) /* 0 - open, 1 - short to GND */ +#define NAU8825_SPKR_ENGND1 (1 << 3) +#define NAU8825_SPKR_ENGND2 (1 << 2) #define NAU8825_SPKR_DWN1R (1 << 1) #define NAU8825_SPKR_DWN1L (1 << 0) @@ -207,6 +209,17 @@ #define NAU8825_SAR_INPUT_JKR2 (0 << 11) #define NAU8825_SAR_TRACKING_GAIN_SFT 8 #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) +#define NAU8825_SAR_HV_SEL_SFT 7 +#define NAU8825_SAR_HV_SEL_MASK (1 << NAU8825_SAR_HV_SEL_SFT) +#define NAU8825_SAR_HV_SEL_MICBIAS (0 << NAU8825_SAR_HV_SEL_SFT) +#define NAU8825_SAR_HV_SEL_VDDMIC (1 << NAU8825_SAR_HV_SEL_SFT) +#define NAU8825_SAR_RES_SEL_SFT 4 +#define NAU8825_SAR_RES_SEL_MASK (0x7 << NAU8825_SAR_RES_SEL_SFT) +#define NAU8825_SAR_RES_SEL_35K (0 << NAU8825_SAR_RES_SEL_SFT) +#define NAU8825_SAR_RES_SEL_70K (1 << NAU8825_SAR_RES_SEL_SFT) +#define NAU8825_SAR_RES_SEL_170K (2 << NAU8825_SAR_RES_SEL_SFT) +#define NAU8825_SAR_RES_SEL_360K (3 << NAU8825_SAR_RES_SEL_SFT) +#define NAU8825_SAR_RES_SEL_SHORTED (4 << NAU8825_SAR_RES_SEL_SFT) #define NAU8825_SAR_COMPARE_TIME_SFT 2 #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) #define NAU8825_SAR_SAMPLING_TIME_SFT 0 @@ -385,6 +398,13 @@ #define NAU8825_BIAS_VMID_SEL_SFT 4 #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) +/* ANALOG_CONTROL_1 (0x69) */ +#define NAU8825_TESTDACIN_SFT 14 +#define NAU8825_TESTDACIN_MASK (0x3 << NAU8825_TESTDACIN_SFT) +#define NAU8825_TESTDACIN_HIGH (1 << NAU8825_TESTDACIN_SFT) +#define NAU8825_TESTDACIN_LOW (2 << NAU8825_TESTDACIN_SFT) +#define NAU8825_TESTDACIN_GND (3 << NAU8825_TESTDACIN_SFT) + /* ANALOG_CONTROL_2 (0x6a) */ #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) #define NAU8825_DAC_CAPACITOR_MSB (1 << 1) @@ -412,6 +432,9 @@ /* MIC_BIAS (0x74) */ #define NAU8825_MICBIAS_JKSLV (1 << 14) #define NAU8825_MICBIAS_JKR2 (1 << 12) +#define NAU8825_MICBIAS_LOWNOISE_SFT 10 +#define NAU8825_MICBIAS_LOWNOISE_MASK (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT) +#define NAU8825_MICBIAS_LOWNOISE_EN (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT) #define NAU8825_MICBIAS_POWERUP_SFT 8 #define NAU8825_MICBIAS_VOLTAGE_SFT 0 #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 |