diff options
| author | Curtis Malainey <cujomalainey@chromium.org> | 2019-11-06 02:13:35 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-11-11 14:02:06 +0100 |
| commit | ba0b3a977ecf525231d36f2d9f3a6ea05c35090a (patch) | |
| tree | 341e7425717c32d3e09685b9a54b07732efbb925 /sound/soc/codecs/rt5677.h | |
| parent | ASoC: bdw-rt5677: Turn on MCLK1 for DSP via DAPM (diff) | |
| download | linux-ba0b3a977ecf525231d36f2d9f3a6ea05c35090a.tar.xz linux-ba0b3a977ecf525231d36f2d9f3a6ea05c35090a.zip | |
ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/rt5677.h')
| -rw-r--r-- | sound/soc/codecs/rt5677.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index f8ada967fdbc..944ae02aafc2 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1336,6 +1336,8 @@ #define RT5677_PLL_M_SFT 12 #define RT5677_PLL_M_BP (0x1 << 11) #define RT5677_PLL_M_BP_SFT 11 +#define RT5677_PLL_UPDATE_PLL1 (0x1 << 1) +#define RT5677_PLL_UPDATE_PLL1_SFT 1 /* Global Clock Control 1 (0x80) */ #define RT5677_SCLK_SRC_MASK (0x3 << 14) |