diff options
| author | Annaliese McDermond <nh6z@nh6z.net> | 2019-03-22 01:58:46 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-25 16:53:33 +0100 |
| commit | fd2df3aeafa4b4cc468d58e147e0822967034b71 (patch) | |
| tree | 75362499653e967335f69916f994934bcb38f83f /sound/soc/codecs/tlv320aic32x4.c | |
| parent | ASoC: tlv320aic32x4: Model PLL in CCF (diff) | |
| download | linux-fd2df3aeafa4b4cc468d58e147e0822967034b71.tar.xz linux-fd2df3aeafa4b4cc468d58e147e0822967034b71.zip | |
ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF
Model and manage codec clock input as a component in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/tlv320aic32x4.c')
| -rw-r--r-- | sound/soc/codecs/tlv320aic32x4.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 7cf8c7cedfe1..5496e4e080f4 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -735,12 +735,9 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component, aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); - /* PLL as CODEC_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_CLKMUX, - AIC32X4_CODEC_CLKIN_MASK, - AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); /* DAC_MOD_CLK as BDIV_CLKIN */ - snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK, + snd_soc_component_update_bits(component, AIC32X4_IFACE3, + AIC32X4_BDIVCLK_MASK, AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); /* NDAC divider value */ @@ -987,6 +984,15 @@ static int aic32x4_component_probe(struct snd_soc_component *component) { struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); u32 tmp_reg; + int ret; + + struct clk_bulk_data clocks[] = { + { .id = "codec_clkin" }, + }; + + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); + if (ret) + return ret; if (gpio_is_valid(aic32x4->rstn_gpio)) { ndelay(10); @@ -999,6 +1005,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component) if (aic32x4->setup) aic32x4_setup_gpios(component); + clk_set_parent(clocks[0].clk, clocks[1].clk); + /* Power platform configuration */ if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { snd_soc_component_write(component, AIC32X4_MICBIAS, |