diff options
| author | Jiri Prchal <jiri.prchal@aksignal.cz> | 2012-07-10 14:36:58 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-07-10 15:41:48 +0200 |
| commit | a1f34af0ec35e3131d65e0ae4cec6b048cba3e88 (patch) | |
| tree | ac552fc41c81fb54a5755c5920feb9dc194bab85 /sound/soc/codecs/tlv320aic3x.c | |
| parent | ASoC: tlv320aic3x: add AGC settings (diff) | |
| download | linux-a1f34af0ec35e3131d65e0ae4cec6b048cba3e88.tar.xz linux-a1f34af0ec35e3131d65e0ae4cec6b048cba3e88.zip | |
ASoC: tlv320aic3x: add input clock selection
This patch adds input selection of main codec clock - from what pin.
Both registers set same value since codec uses clock divider or pll at one time.
Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.c')
| -rw-r--r-- | sound/soc/codecs/tlv320aic3x.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 0d2f8c44999d..b94f81ffed34 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1002,6 +1002,12 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, struct snd_soc_codec *codec = codec_dai->codec; struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); + /* set clock on MCLK or GPIO2 or BCLK */ + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, + clk_id << PLLCLK_IN_SHIFT); + snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, + clk_id << CLKDIV_IN_SHIFT); + aic3x->sysclk = freq; return 0; } |