diff options
| author | Jose Abreu <Jose.Abreu@synopsys.com> | 2016-04-07 18:53:57 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-04-07 19:41:36 +0200 |
| commit | 3fafd14d9422c46f5c2a142298384dc15dbf88b2 (patch) | |
| tree | 2e39c0013c93acacb6a44c0e51c055df8637d08f /sound/soc/dwc | |
| parent | ASoC: dwc: Unmask I2S interrupts only for enabled channels (diff) | |
| download | linux-3fafd14d9422c46f5c2a142298384dc15dbf88b2.tar.xz linux-3fafd14d9422c46f5c2a142298384dc15dbf88b2.zip | |
ASoC: dwc: Use fifo depth to program FCR
This patch makes Designware I2S driver use the fifo
depth value to program the fifo configuration register
instead of using hardcoded values.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/dwc')
| -rw-r--r-- | sound/soc/dwc/designware_i2s.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index 3effcd1a7df8..0db69b7e9617 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -100,6 +100,7 @@ struct dw_i2s_dev { struct device *dev; u32 ccr; u32 xfer_resolution; + u32 fifo_th; /* data related to DMA transfers b/w i2s and DMAC */ union dw_i2s_snd_dma_data play_dma_data; @@ -232,14 +233,16 @@ static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) if (stream == SNDRV_PCM_STREAM_PLAYBACK) { i2s_write_reg(dev->i2s_base, TCR(ch_reg), dev->xfer_resolution); - i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); + i2s_write_reg(dev->i2s_base, TFCR(ch_reg), + dev->fifo_th - 1); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); } else { i2s_write_reg(dev->i2s_base, RCR(ch_reg), dev->xfer_resolution); - i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); + i2s_write_reg(dev->i2s_base, RFCR(ch_reg), + dev->fifo_th - 1); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); @@ -499,6 +502,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, */ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); + u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); u32 idx; if (dev->capability & DWC_I2S_RECORD && @@ -537,6 +541,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, dev->capability |= DW_I2S_SLAVE; } + dev->fifo_th = fifo_depth / 2; return 0; } |