diff options
| author | Xiubo Li <lixiubo@cmss.chinamobile.com> | 2015-08-12 08:38:18 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-08-12 14:36:58 +0200 |
| commit | dcfcf2c2cd71906073beef32aadb1989e8996951 (patch) | |
| tree | 62645c5ac4fb8b7c9afb067b976e0ee3837d6400 /sound/soc/fsl/fsl_sai.h | |
| parent | ASoC: fsl: Add dedicated DMA buffer size for each cpu dai (diff) | |
| download | linux-dcfcf2c2cd71906073beef32aadb1989e8996951.tar.xz linux-dcfcf2c2cd71906073beef32aadb1989e8996951.zip | |
ASoC: fsl: fix typos for sound/soc/fsl/*
There are too much noise about the typos for fsl's drivers. So I fix
all the typos here in this patch in almost every file I touched.
Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl/fsl_sai.h')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 066280953c85..b4666fd79f6e 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -45,7 +45,7 @@ #define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) -/* SAI Transmit/Recieve Control Register */ +/* SAI Transmit/Receive Control Register */ #define FSL_SAI_CSR_TERE BIT(31) #define FSL_SAI_CSR_FR BIT(25) #define FSL_SAI_CSR_SR BIT(24) @@ -67,10 +67,10 @@ #define FSL_SAI_CSR_FRIE BIT(8) #define FSL_SAI_CSR_FRDE BIT(0) -/* SAI Transmit and Recieve Configuration 1 Register */ +/* SAI Transmit and Receive Configuration 1 Register */ #define FSL_SAI_CR1_RFW_MASK 0x1f -/* SAI Transmit and Recieve Configuration 2 Register */ +/* SAI Transmit and Receive Configuration 2 Register */ #define FSL_SAI_CR2_SYNC BIT(30) #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) #define FSL_SAI_CR2_MSEL_BUS 0 @@ -82,12 +82,12 @@ #define FSL_SAI_CR2_BCD_MSTR BIT(24) #define FSL_SAI_CR2_DIV_MASK 0xff -/* SAI Transmit and Recieve Configuration 3 Register */ +/* SAI Transmit and Receive Configuration 3 Register */ #define FSL_SAI_CR3_TRCE BIT(16) #define FSL_SAI_CR3_WDFL(x) (x) #define FSL_SAI_CR3_WDFL_MASK 0x1f -/* SAI Transmit and Recieve Configuration 4 Register */ +/* SAI Transmit and Receive Configuration 4 Register */ #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) @@ -97,7 +97,7 @@ #define FSL_SAI_CR4_FSP BIT(1) #define FSL_SAI_CR4_FSD_MSTR BIT(0) -/* SAI Transmit and Recieve Configuration 5 Register */ +/* SAI Transmit and Receive Configuration 5 Register */ #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) |