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| author | Jaroslav Kysela <perex@suse.cz> | 2006-02-15 13:31:23 +0100 |
|---|---|---|
| committer | Jaroslav Kysela <perex@suse.cz> | 2006-03-22 10:29:29 +0100 |
| commit | 253b999f5a620be81db4cfa31f76873b639ec9a2 (patch) | |
| tree | 9e329b3739d520989e5ca121bc100bdb7a7cce44 /sound | |
| parent | [ALSA] ice1712 - Delta 1010LT S/PDIF fixes (diff) | |
| download | linux-253b999f5a620be81db4cfa31f76873b639ec9a2.tar.xz linux-253b999f5a620be81db4cfa31f76873b639ec9a2.zip | |
[ALSA] intel8x0 - wait for ICH_RESETREGS
Modules: Intel8x0 driver
It seems that hardware requires some time to reset bus master registers.
We need to wait until ICH_RESETREGS bit is not released.
The suggestion and symptom was described by Mike Gorchak <lestat@i.com.ua>.
Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/pci/intel8x0.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c index da024ffe96c2..ebbf2cf4ca0f 100644 --- a/sound/pci/intel8x0.c +++ b/sound/pci/intel8x0.c @@ -2351,7 +2351,7 @@ static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) { - unsigned int i; + unsigned int i, timeout; int err; if (chip->device_type != DEVICE_ALI) { @@ -2369,6 +2369,15 @@ static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) /* reset channels */ for (i = 0; i < chip->bdbars_count; i++) iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); + for (i = 0; i < chip->bdbars_count; i++) { + timeout = 100000; + while (--timeout != 0) { + if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) + break; + } + if (timeout == 0) + printk(KERN_ERR "intel8x0: reset of registers failed?\n"); + } /* initialize Buffer Descriptor Lists */ for (i = 0; i < chip->bdbars_count; i++) iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, |