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| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2019-07-25 10:34:23 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-07-26 14:09:09 +0200 |
| commit | 34a2a80ff30b5d2330abfa8980c7f0cc15a8158a (patch) | |
| tree | 211576006c6214dc3f415b23f2fa1c85f8c3e18f /sound | |
| parent | ASoC: Fail card instantiation if DAI format setup fails (diff) | |
| download | linux-34a2a80ff30b5d2330abfa8980c7f0cc15a8158a.tar.xz linux-34a2a80ff30b5d2330abfa8980c7f0cc15a8158a.zip | |
ASoC: ti: davinci-mcasp: Fix clk PDIR handling for i2s master mode
When running McASP as master capture alone will not record any audio unless
a parallel playback stream is running. As soon as the playback stops the
captured data is going to be silent again.
In McASP master mode we need to set the PDIR for the clock pins and fix
the mcasp_set_axr_pdir() to skip the bits in the PDIR registers above
AMUTE.
This went unnoticed as most of the boards uses McASP as slave and neither
of these issues are visible (audible) in those setups.
Fixes: ca3d9433349e ("ASoC: davinci-mcasp: Update PDIR (pin direction) register handling")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Link: https://lore.kernel.org/r/20190725083423.7321-1-peter.ujfalusi@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/ti/davinci-mcasp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/sound/soc/ti/davinci-mcasp.c b/sound/soc/ti/davinci-mcasp.c index 2c518088b64d..4d611565375b 100644 --- a/sound/soc/ti/davinci-mcasp.c +++ b/sound/soc/ti/davinci-mcasp.c @@ -195,7 +195,7 @@ static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) { u32 bit; - for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { + for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { if (enable) mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); else @@ -223,6 +223,7 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp) if (mcasp_is_synchronous(mcasp)) { mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); + mcasp_set_clk_pdir(mcasp, true); } /* Activate serializer(s) */ |