diff options
| author | Chen Yu <yu.c.chen@intel.com> | 2021-04-28 04:51:57 +0200 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2021-05-05 01:09:00 +0200 |
| commit | 8c69da293041352d15a2b6e8010c141822a416c5 (patch) | |
| tree | 706505f8c5f4ff450297073735073966161b660e /tools/power/x86 | |
| parent | tools/power turbostat: unmark non-kernel-doc comment (diff) | |
| download | linux-8c69da293041352d15a2b6e8010c141822a416c5.tar.xz linux-8c69da293041352d15a2b6e8010c141822a416c5.zip | |
tools/power turbostat: Enable tsc_tweak for Elkhart Lake and Jasper Lake
It was found that on Elkhart Lake the TSC frequency is driven by
a separate crystal-clock domain, which is different from the
BCLK domain which includes mperf. This has result in small different
speed thus inconsistence between TSC and the mperf, which caused the
Busy% to be higher than 100%. On this platform it seems that the mperf
runs faster than tsc when the CPU is 100% utilized:
delta tsc(18815473183) < delta mperf(18958403680) for 10 seconds.
To align TSC with mperf, leverage the tsc_tweak mechanism introduced for
cores newer than Skylake, so that TSC and mperf would be calculated in
the same domain.
Reported-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Chen Yu <yu.c.chen@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power/x86')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 407e80e72546..9ec13f06c0f3 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -5440,7 +5440,7 @@ void process_cpuid() if (!quiet) dump_sysfs_pstate_config(); - if (has_skl_msrs(family, model)) + if (has_skl_msrs(family, model) || is_ehl(family, model)) calculate_tsc_tweak(); if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) |