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| author | Len Brown <len.brown@intel.com> | 2017-04-13 01:44:51 +0200 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-04-13 02:03:50 +0200 |
| commit | 95149369c1c28b10f7318dfde54018ab107277d0 (patch) | |
| tree | 8d220525609dcb1589167c8446731b316a84b67e /tools/power | |
| parent | tools/power turbostat: turbostat.8 add missing column definitions (diff) | |
| download | linux-95149369c1c28b10f7318dfde54018ab107277d0.tar.xz linux-95149369c1c28b10f7318dfde54018ab107277d0.zip | |
tools/power turbostat: fix impossibly large CPU%c1 value
Most CPUs do not have a hardware c1 counter,
and so turbostat derives c1 residency:
c1 = TSC - MPERF - other_core_cstate_counters
As it is not possible to atomically read these coutners,
measurement jitter can case this calcuation to "go negative"
when very close to 0. Turbostat detect that case and
simply prints c1 = 0.00%
But that check neglected to account for systems where the TSC
crystal clock domain and the MPERF BCLK domain are differ by
a small amount. That allowed very small negative c1 numbers
to escape this check and be printed as huge positve numbers.
This code begs for a bit of cleanup, but this patch
is the minimal change to fix the issue.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index b0591d0da801..0ad966114e58 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -1142,7 +1142,7 @@ delta_thread(struct thread_data *new, struct thread_data *old, * it is possible for mperf's non-halted cycles + idle states * to exceed TSC's all cycles: show c1 = 0% in that case. */ - if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) + if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) old->c1 = 0; else { /* normal case, derive c1 */ |