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authorDave Jiang <dave.jiang@intel.com>2024-04-03 17:47:14 +0200
committerDave Jiang <dave.jiang@intel.com>2024-04-08 17:25:21 +0200
commit51293c565cf4b8d57c154efadb57b17866c74bcb (patch)
tree4a6077b21e18243623b49b98ce91931909d840a7 /tools/testing/cxl
parentcxl: Fix retrieving of access_coordinates in PCIe path (diff)
downloadlinux-51293c565cf4b8d57c154efadb57b17866c74bcb.tar.xz
linux-51293c565cf4b8d57c154efadb57b17866c74bcb.zip
cxl: Fix incorrect region perf data calculation
Current math in cxl_region_perf_data_calculate divides the latency by 1000 every time the function gets called. This causes the region latency to be divided by 1000 per memory device and the math is incorrect. This is user visible as the latency access_coordinate exposed via sysfs will show incorrect latency data. Normalize values from CDAT to nanoseconds. Adjust sub-nanoseconds latency to at least 1. Remove adjustment of perf numbers from the generic target since hmat handling code has already normalized those numbers. Now all computation and stored numbers should be in nanoseconds. cxl_hb_get_perf_coordinates() is removed and HB coords are calculated in the port access_coordinate calculation path since it no longer need to be treated special. Fixes: 3d9f4a197230 ("cxl/region: Calculate performance data for a region") Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20240403154844.3403859-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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