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| author | Paweł Jarosz <paweljarosz3691@gmail.com> | 2016-11-04 14:10:56 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-11-05 23:11:01 +0100 |
| commit | 82e56393a80b99cf8986616447d71cbcff90e9d1 (patch) | |
| tree | 3ff176f7fa80fb65d008cd8816709b7bedc89368 /tools/usb/Makefile | |
| parent | clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 (diff) | |
| download | linux-82e56393a80b99cf8986616447d71cbcff90e9d1.tar.xz linux-82e56393a80b99cf8986616447d71cbcff90e9d1.zip | |
clk: rockchip: add 400MHz to rk3066 clock rates table
We need this to init PLL_CPLL to 400MHz at boot.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/usb/Makefile')
0 files changed, 0 insertions, 0 deletions