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authorZhang Rui <rui.zhang@intel.com>2024-03-12 04:19:15 +0100
committerLen Brown <len.brown@intel.com>2024-04-09 20:04:23 +0200
commitbb5db22c13125b38b0740e19c18ae94f8e5a0eb6 (patch)
treefdeefc75ff626bc11c10f5afcc62bec827e0fa7f /tools
parenttools/power turbostat: Add selftests (diff)
downloadlinux-bb5db22c13125b38b0740e19c18ae94f8e5a0eb6.tar.xz
linux-bb5db22c13125b38b0740e19c18ae94f8e5a0eb6.zip
tools/power/turbostat: Enable MSR_CORE_C1_RES support for ICX
Enable Core C1 hardware residency counter (MSR_CORE_C1_RES) on ICX. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools')
-rw-r--r--tools/power/x86/turbostat/turbostat.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 283dffb987b5..372f67a70d8a 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -664,6 +664,7 @@ static const struct platform_features icx_features = {
.bclk_freq = BCLK_100MHZ,
.supported_cstates = CC1 | CC6 | PC2 | PC6,
.cst_limit = CST_LIMIT_ICX,
+ .has_msr_core_c1_res = 1,
.has_irtl_msrs = 1,
.has_cst_prewake_bit = 1,
.trl_msrs = TRL_BASE | TRL_CORECOUNT,