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| author | Sean Christopherson <seanjc@google.com> | 2024-07-20 01:51:06 +0200 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2024-08-30 01:25:06 +0200 |
| commit | 0cb26ec320851f685280ff061f84855d0e97bf86 (patch) | |
| tree | 087a57b05ab0dc716024acbc5229c6294525b49a /tools | |
| parent | KVM: selftests: Test x2APIC ICR reserved bits (diff) | |
| download | linux-0cb26ec320851f685280ff061f84855d0e97bf86.tar.xz linux-0cb26ec320851f685280ff061f84855d0e97bf86.zip | |
KVM: selftests: Verify the guest can read back the x2APIC ICR it wrote
Now that the BUSY bit mess is gone (for x2APIC), verify that the *guest*
can read back the ICR value that it wrote. Due to the divergent
behavior between AMD and Intel with respect to the backing storage of the
ICR in the vAPIC page, emulating a seemingly simple MSR write is quite
complex.
Link: https://lore.kernel.org/r/20240719235107.3023592-10-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/testing/selftests/kvm/x86_64/xapic_state_test.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tools/testing/selftests/kvm/x86_64/xapic_state_test.c b/tools/testing/selftests/kvm/x86_64/xapic_state_test.c index a17b75fb2506..dbd4f23ce92e 100644 --- a/tools/testing/selftests/kvm/x86_64/xapic_state_test.c +++ b/tools/testing/selftests/kvm/x86_64/xapic_state_test.c @@ -45,10 +45,12 @@ static void x2apic_guest_code(void) uint64_t val = x2apic_read_reg(APIC_IRR) | x2apic_read_reg(APIC_IRR + 0x10) << 32; - if (val & X2APIC_RSVD_BITS_MASK) + if (val & X2APIC_RSVD_BITS_MASK) { x2apic_write_reg_fault(APIC_ICR, val); - else + } else { x2apic_write_reg(APIC_ICR, val); + GUEST_ASSERT_EQ(x2apic_read_reg(APIC_ICR), val); + } GUEST_SYNC(val); } while (1); } |