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authorIan Rogers <irogers@google.com>2022-12-15 07:54:57 +0100
committerArnaldo Carvalho de Melo <acme@redhat.com>2022-12-21 18:52:41 +0100
commit2c3fd22bb3ff166a072c083e6b7468259c37e46a (patch)
tree0fe5cf65b2a210b4d7872afb9578cad80914b6ba /tools
parentperf vendor events intel: Refresh jaketown metrics and events (diff)
downloadlinux-2c3fd22bb3ff166a072c083e6b7468259c37e46a.tar.xz
linux-2c3fd22bb3ff166a072c083e6b7468259c37e46a.zip
perf vendor events intel: Refresh knightslanding events
Update the knightslanding events using the new tooling from: https://github.com/intel/perfmon The events are unchanged but unused json values are removed. This increases consistency across the json files. Signed-off-by: Ian Rogers <irogers@google.com> Acked-by: Kan Liang <kan.liang@linux.intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20221215065510.1621979-11-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools')
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/cache.json411
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json3
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/frontend.json7
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/memory.json201
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json44
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json1016
-rw-r--r--tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json7
7 files changed, 287 insertions, 1402 deletions
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
index 5e10eabda300..01aea3d2832e 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json
@@ -1,14 +1,12 @@
[
{
"BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path.",
- "Counter": "0,1",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses.",
- "Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Counts the number of L2 cache misses",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_REQUESTS.MISS",
"SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "Counts the total number of L2 cache references.",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_REQUESTS.REFERENCE",
"SampleAfterValue": "200003",
@@ -33,14 +29,12 @@
},
{
"BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
- "Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REQUESTS_REJECT.ALL",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts all the load micro-ops retired",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "This event counts the number of load micro-ops retired.",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Counts all the store micro-ops retired",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "This event counts the number of store micro-ops retired.",
@@ -58,7 +51,6 @@
},
{
"BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.HITM",
@@ -68,7 +60,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
@@ -77,7 +68,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
@@ -87,7 +77,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
@@ -97,7 +86,6 @@
},
{
"BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss",
- "Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS",
"SampleAfterValue": "200003",
@@ -105,7 +93,6 @@
},
{
"BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100007",
@@ -113,2190 +100,1792 @@
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000013091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800183091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800083091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000083091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00000132f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x08004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18001832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x08000832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000832f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00040032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00100032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00020032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00080032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x40000032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800188000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800088000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000088000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010800",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000014000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000010100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a7",
"MSRValue": "0x1800400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0800400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x1000400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a7",
"MSRValue": "0x1800180100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0800080100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x1000080100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a7",
"MSRValue": "0x0004000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a7",
"MSRValue": "0x0010000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a7",
"MSRValue": "0x0002000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a7",
"MSRValue": "0x0008000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000012000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800182000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800082000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000082000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000020020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000011000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800181000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800081000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000081000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
"MSRIndex": "0x1a7",
"MSRValue": "0x0000014800",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for any response",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1800180200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0800080200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0004000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0010000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0002000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0008000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
index ff5db600e420..ecc96f32f167 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of floating operations retired that required microcode assists",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.PACKED_SIMD",
"PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.SCALAR_SIMD",
"PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
index 63343a0d1e86..9001f5019848 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
@@ -17,7 +15,6 @@
},
{
"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
- "Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
@@ -33,7 +29,6 @@
},
{
"BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
@@ -41,7 +36,6 @@
},
{
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
- "Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
@@ -49,7 +43,6 @@
},
{
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
- "Counter": "0,1",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
index 2611defaeaa2..b0361f6f0dd9 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
@@ -9,1101 +8,901 @@
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200044",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181803091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101003091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080803091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180603091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100403091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080203091",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200070",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01818032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01010032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00808032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01806032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01004032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x00802032f7",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181808000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101008000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080808000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180608000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100408000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080208000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200022",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200400",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200004",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200001",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200002",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020080",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0101000100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080800100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
"MSRIndex": "0x1a7",
"MSRValue": "0x0180600100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0100400100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
"MSRIndex": "0x1a7",
"MSRValue": "0x0080200100",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181802000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101002000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080802000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100402000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080202000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200040",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000020020",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181801000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101001000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080801000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180601000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100401000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080201000",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0181800200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0101000200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080800200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0180600200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0100400200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.",
- "Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080200200",
- "Offcore": "1",
"SampleAfterValue": "100007",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
index 1f13bc2686cb..1b803fa38641 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
@@ -18,7 +16,6 @@
},
{
"BriefDescription": "Counts the number of far branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -27,7 +24,6 @@
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
@@ -45,7 +40,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -54,7 +48,6 @@
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
@@ -63,7 +56,6 @@
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
@@ -72,7 +64,6 @@
},
{
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.",
- "Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
@@ -89,7 +79,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CALL",
"PEBS": "1",
@@ -98,7 +87,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted far branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.FAR_BRANCH",
"PEBS": "1",
@@ -107,7 +95,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
@@ -116,7 +103,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
@@ -125,7 +111,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
@@ -134,7 +119,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.REL_CALL",
"PEBS": "1",
@@ -143,7 +127,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
@@ -152,7 +135,6 @@
},
{
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.",
- "Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
@@ -161,7 +143,6 @@
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
@@ -169,14 +150,12 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
- "Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter",
"SampleAfterValue": "2000003",
@@ -184,14 +163,12 @@
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles",
- "Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.",
- "Counter": "0,1",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
"PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.",
@@ -200,7 +177,6 @@
},
{
"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
- "Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",
"SampleAfterValue": "2000003",
@@ -208,14 +184,12 @@
},
{
"BriefDescription": "Counts the total number of instructions retired",
- "Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts all nukes",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
"SampleAfterValue": "200003",
@@ -223,7 +197,6 @@
},
{
"BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page",
- "Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200003",
@@ -231,7 +204,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ALL",
"SampleAfterValue": "200003",
@@ -239,7 +211,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
"PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
@@ -248,7 +219,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
"PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.",
@@ -257,7 +227,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.RAT_STALL",
"SampleAfterValue": "200003",
@@ -265,7 +234,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full",
- "Counter": "0,1",
"EventCode": "0xCA",
"EventName": "NO_ALLOC_CYCLES.ROB_FULL",
"SampleAfterValue": "200003",
@@ -273,7 +241,6 @@
},
{
"BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ANY_LD",
"SampleAfterValue": "200003",
@@ -281,7 +248,6 @@
},
{
"BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ANY_ST",
"SampleAfterValue": "200003",
@@ -289,7 +255,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY",
"SampleAfterValue": "200003",
@@ -297,7 +262,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
@@ -307,7 +271,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LD_SPLITS",
@@ -317,7 +280,6 @@
},
{
"BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.LOCK",
"SampleAfterValue": "200003",
@@ -325,7 +287,6 @@
},
{
"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.STA_FULL",
"SampleAfterValue": "200003",
@@ -333,7 +294,6 @@
},
{
"BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.",
- "Counter": "0,1",
"EventCode": "0x03",
"EventName": "RECYCLEQ.ST_SPLITS",
"PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
@@ -342,7 +302,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.ALL",
"SampleAfterValue": "200003",
@@ -350,7 +309,6 @@
},
{
"BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.",
- "Counter": "0,1",
"EventCode": "0xCB",
"EventName": "RS_FULL_STALL.MEC",
"SampleAfterValue": "200003",
@@ -358,7 +316,6 @@
},
{
"BriefDescription": "Counts the number of micro-ops retired",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.",
@@ -367,7 +324,6 @@
},
{
"BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).",
- "Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
index a5e1a9a47e73..3abd9c3fdc48 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
@@ -10,7 +9,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
@@ -19,7 +17,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
"PerPkg": "1",
@@ -27,8 +24,7 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
"PerPkg": "1",
@@ -37,7 +33,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
@@ -46,7 +41,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
"PerPkg": "1",
@@ -55,7 +49,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
"PerPkg": "1",
@@ -64,43 +57,38 @@
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_UCLK"
},
{
- "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Number of EDC Hits or Misses. Miss I",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
"PerPkg": "1",
@@ -109,75 +97,66 @@
},
{
"BriefDescription": "ECLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_E_E_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_ECLK"
},
{
- "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
"EventCode": "0x01",
"EventName": "UNC_E_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "UCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_E_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
- "Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_WPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -186,7 +165,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -195,7 +173,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -204,7 +181,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -213,61 +189,54 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -276,7 +245,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -285,7 +253,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -294,7 +261,6 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -303,61 +269,54 @@
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -366,7 +325,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -375,7 +333,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -384,7 +341,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -393,61 +349,54 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -456,7 +405,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -465,7 +413,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -474,7 +421,6 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -483,61 +429,54 @@
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
"PerPkg": "1",
@@ -546,7 +485,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
"PerPkg": "1",
@@ -555,7 +493,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
"PerPkg": "1",
@@ -564,7 +501,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
"PerPkg": "1",
@@ -573,61 +509,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
"PerPkg": "1",
@@ -636,7 +565,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
"PerPkg": "1",
@@ -645,7 +573,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
"PerPkg": "1",
@@ -654,7 +581,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
"PerPkg": "1",
@@ -663,61 +589,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -726,7 +645,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -735,7 +653,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -744,7 +661,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -753,61 +669,54 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -816,7 +725,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -825,7 +733,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -834,7 +741,6 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -843,61 +749,54 @@
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
@@ -906,7 +805,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
@@ -915,7 +813,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6",
"PerPkg": "1",
@@ -924,7 +821,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7",
"PerPkg": "1",
@@ -933,61 +829,54 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
@@ -996,7 +885,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
@@ -1005,7 +893,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6",
"PerPkg": "1",
@@ -1014,7 +901,6 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7",
"PerPkg": "1",
@@ -1023,61 +909,54 @@
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4",
"PerPkg": "1",
@@ -1086,7 +965,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5",
"PerPkg": "1",
@@ -1095,7 +973,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6",
"PerPkg": "1",
@@ -1104,7 +981,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7",
"PerPkg": "1",
@@ -1113,61 +989,54 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 1",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 2",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 3",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 4",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4",
"PerPkg": "1",
@@ -1176,7 +1045,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 5",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5",
"PerPkg": "1",
@@ -1185,7 +1053,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 6",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6",
"PerPkg": "1",
@@ -1194,7 +1061,6 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 7",
- "Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7",
"PerPkg": "1",
@@ -1203,43 +1069,38 @@
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Stall on No AD Transgress Credits For Transgress 8",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL",
"PerPkg": "1",
@@ -1248,16 +1109,14 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Lines Victimized that Does Not Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE",
"PerPkg": "1",
@@ -1266,16 +1125,14 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_H_CLOCK",
"PerPkg": "1",
@@ -1283,313 +1140,278 @@
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Bypass. IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
"EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AD",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AK",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty BL",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty IV",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts AD",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts AK",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts BL",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts IV",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_H_EGRESS_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy AD",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy AK",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy BL",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy IV",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_H_EGRESS_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
- "Counter": "0,1,2,3",
"EventCode": "0xAE",
"EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
@@ -1598,16 +1420,14 @@
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
@@ -1616,16 +1436,14 @@
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
@@ -1634,16 +1452,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
@@ -1652,16 +1468,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
@@ -1670,16 +1484,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
@@ -1688,25 +1500,22 @@
},
{
"BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_H_EGRESS_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
@@ -1715,16 +1524,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
@@ -1733,16 +1540,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
@@ -1751,25 +1556,22 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
@@ -1778,16 +1580,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
@@ -1796,16 +1596,14 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
@@ -1814,25 +1612,22 @@
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
@@ -1841,16 +1636,14 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
@@ -1859,16 +1652,14 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
@@ -1877,25 +1668,22 @@
},
{
"BriefDescription": "CMS Vert Egress Allocations IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1",
"PerPkg": "1",
@@ -1904,16 +1692,14 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1",
"PerPkg": "1",
@@ -1922,16 +1708,14 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1",
"PerPkg": "1",
@@ -1940,25 +1724,22 @@
},
{
"BriefDescription": "CMS Vertical Egress NACKs",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
@@ -1967,16 +1748,14 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
@@ -1985,16 +1764,14 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
@@ -2003,25 +1780,22 @@
},
{
"BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1",
"PerPkg": "1",
@@ -2030,16 +1804,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1",
"PerPkg": "1",
@@ -2048,16 +1820,14 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1",
"PerPkg": "1",
@@ -2066,25 +1836,22 @@
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles source throttling is adderted - horizontal",
- "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_H_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles source throttling is adderted - vertical",
- "Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_H_FAST_ASSERTED.VERT",
"PerPkg": "1",
@@ -2092,160 +1859,142 @@
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA9",
"EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left",
- "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right",
- "Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.PRQ",
"PerPkg": "1",
@@ -2254,7 +2003,6 @@
},
{
"BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ",
"PerPkg": "1",
@@ -2263,34 +2011,30 @@
},
{
"BriefDescription": "Cycles with the IPQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles with the IRQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Cycles with the ISMQ in Internal Starvation.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue.",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_INGRESS_INT_STARVED.PRQ",
"PerPkg": "1",
@@ -2302,7 +2046,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
@@ -2310,7 +2054,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
@@ -2318,7 +2062,7 @@
"EventCode": "0x11",
"EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
@@ -2339,25 +2083,22 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2366,7 +2107,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2375,7 +2115,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2384,25 +2123,22 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2411,7 +2147,6 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2420,16 +2155,14 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2438,16 +2171,14 @@
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Probe Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2456,25 +2187,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2483,7 +2211,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2492,7 +2219,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2501,25 +2227,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2528,7 +2251,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2537,16 +2259,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2555,16 +2275,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2573,25 +2291,22 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2600,7 +2315,6 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2609,7 +2323,6 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2618,25 +2331,22 @@
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2645,25 +2355,22 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2672,7 +2379,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2681,7 +2387,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2690,25 +2395,22 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -2717,25 +2419,22 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2744,7 +2443,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2753,7 +2451,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2762,25 +2459,22 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -2789,7 +2483,6 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
@@ -2798,16 +2491,14 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
@@ -2816,16 +2507,14 @@
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Other Queue Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY",
"PerPkg": "1",
@@ -2834,25 +2523,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
@@ -2861,7 +2547,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
@@ -2870,7 +2555,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
@@ -2879,25 +2563,22 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
@@ -2906,7 +2587,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
@@ -2915,16 +2595,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
@@ -2933,16 +2611,14 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY",
"PerPkg": "1",
@@ -2951,25 +2627,22 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI",
"PerPkg": "1",
@@ -2978,7 +2651,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
@@ -2987,7 +2659,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
@@ -2996,25 +2667,22 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
@@ -3023,7 +2691,6 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
@@ -3032,16 +2699,14 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
@@ -3050,16 +2715,14 @@
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY",
"PerPkg": "1",
@@ -3068,7 +2731,6 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.CV0_PREF_MISS",
"PerPkg": "1",
@@ -3077,7 +2739,6 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.CV0_PREF_VIC",
"PerPkg": "1",
@@ -3086,178 +2747,158 @@
},
{
"BriefDescription": "Miscellaneous events in the Cbo. RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop Eviction",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Miscellaneous events in the Cbo. Write Combining Aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_H_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_H_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Horizontal ring sink starvation count - IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - AD ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - AK ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - BL ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Vertical ring sink starvation count - IV ring",
- "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts cycles in throttle mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_H_RING_SRC_THRTL",
"PerPkg": "1",
@@ -3265,7 +2906,6 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.ANY",
"PerPkg": "1",
@@ -3274,43 +2914,38 @@
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x03",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "UMask": "0x09",
+ "UMask": "0x9",
"Unit": "CHA"
},
{
"BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_H_SF_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x05",
+ "UMask": "0x5",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
@@ -3319,16 +2954,14 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
@@ -3337,16 +2970,14 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD",
"PerPkg": "1",
@@ -3355,25 +2986,22 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD",
"PerPkg": "1",
@@ -3382,25 +3010,22 @@
},
{
"BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD",
"PerPkg": "1",
@@ -3409,25 +3034,22 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD",
"PerPkg": "1",
@@ -3436,7 +3058,6 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV",
"PerPkg": "1",
@@ -3445,25 +3066,22 @@
},
{
"BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD",
"PerPkg": "1",
@@ -3472,25 +3090,22 @@
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD",
"PerPkg": "1",
@@ -3499,25 +3114,22 @@
},
{
"BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD",
"PerPkg": "1",
@@ -3526,25 +3138,22 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD",
"PerPkg": "1",
@@ -3553,16 +3162,14 @@
},
{
"BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.EVICT",
"PerPkg": "1",
@@ -3571,16 +3178,14 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.HIT",
"PerPkg": "1",
- "UMask": "0x1F",
+ "UMask": "0x1f",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.IPQ",
"PerPkg": "1",
@@ -3589,7 +3194,6 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.IRQ",
"PerPkg": "1",
@@ -3598,16 +3202,14 @@
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x2F",
+ "UMask": "0x2f",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TOR_INSERTS.PRQ",
"PerPkg": "1",
@@ -3627,7 +3229,7 @@
"EventCode": "0x36",
"EventName": "UNC_H_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x1F",
+ "UMask": "0x1f",
"Unit": "CHA"
},
{
@@ -3683,7 +3285,7 @@
"EventCode": "0x36",
"EventName": "UNC_H_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x2F",
+ "UMask": "0x2f",
"Unit": "CHA"
},
{
@@ -3712,167 +3314,148 @@
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
"EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
"PerPkg": "1",
@@ -3881,16 +3464,14 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
"PerPkg": "1",
@@ -3899,34 +3480,30 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
"PerPkg": "1",
@@ -3935,16 +3512,14 @@
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1",
- "Counter": "0,1",
"EventCode": "0x23",
"EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
"PerPkg": "1",
@@ -3953,16 +3528,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
"PerPkg": "1",
@@ -3971,16 +3544,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
"PerPkg": "1",
@@ -3989,16 +3560,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
"PerPkg": "1",
@@ -4007,16 +3576,14 @@
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
"PerPkg": "1",
@@ -4025,7 +3592,6 @@
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -4034,68 +3600,60 @@
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CAS All",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x03",
+ "UMask": "0x3",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "DCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_D_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "UCLK count",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_UCLK"
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
index 821cdd44a12f..99a8fa8f19cc 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
- "Counter": "0,1",
"Data_LA": "1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.CYCLES",
"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.",
@@ -20,7 +18,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
@@ -28,7 +25,6 @@
},
{
"BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
@@ -37,7 +33,6 @@
},
{
"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.",
- "Counter": "0,1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress.",
@@ -46,7 +41,6 @@
},
{
"BriefDescription": "Counts the total I-side page walks that are completed.",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
@@ -55,7 +49,6 @@
},
{
"BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
- "Counter": "0,1",
"EdgeDetect": "1",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.WALKS",
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 12:02:06 +0100