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| author | Marc Zyngier <marc.zyngier@arm.com> | 2016-02-18 20:15:45 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-02-18 20:15:45 +0100 |
| commit | 8f318526a292c5e7cebb82f3f766b83c22343293 (patch) | |
| tree | 59295989b94241595716d5174f2ba1b670c8616b /tools | |
| parent | irqchip/gicv3-its: Avoid cache flush beyond ITS_BASERn memory size (diff) | |
| download | linux-8f318526a292c5e7cebb82f3f766b83c22343293.tar.xz linux-8f318526a292c5e7cebb82f3f766b83c22343293.zip | |
irqchip/gic-v3: Add missing barrier to 32bit version of gic_read_iar()
Commit 1a1ebd5 ("irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is
visible on redestributor") fixed the missing barrier on arm64, but
forgot to update the 32bit counterpart, which has the same requirements.
Let's fix it.
Fixes: 1a1ebd5 ("irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions