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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-11-19 16:43:16 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-19 20:50:56 +0100 |
| commit | 7a110b9107ed8fe27277988cdb4d18e7043b7252 (patch) | |
| tree | 8e4d7d7bc4f460dd7e8510d08dccd567d849cd6f /virt | |
| parent | clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz (diff) | |
| download | linux-7a110b9107ed8fe27277988cdb4d18e7043b7252.tar.xz linux-7a110b9107ed8fe27277988cdb4d18e7043b7252.zip | |
clk: at91: clk-master: re-factor master clock
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions