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authorChristoffer Dall <christoffer.dall@linaro.org>2016-05-25 16:26:33 +0200
committerChristoffer Dall <christoffer.dall@linaro.org>2016-05-31 16:09:28 +0200
commit4d3afc9bad2b67b118a0cc204dc94703f7a44e74 (patch)
tree5ea0fcc6170249ccd1e69aa9eccb8f644de52f7a /virt
parentLinux 4.7-rc1 (diff)
downloadlinux-4d3afc9bad2b67b118a0cc204dc94703f7a44e74.tar.xz
linux-4d3afc9bad2b67b118a0cc204dc94703f7a44e74.zip
KVM: arm/arm64: vgic-v2: Clear all dirty LRs
When saving the state of the list registers, it is critical to reset them zero, as we could otherwise leave unexpected EOI interrupts pending for virtual level interrupts. Cc: stable@vger.kernel.org # v4.6+ Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'virt')
-rw-r--r--virt/kvm/arm/hyp/vgic-v2-sr.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c
index a3f12b3b277b..3a3a699b7489 100644
--- a/virt/kvm/arm/hyp/vgic-v2-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v2-sr.c
@@ -100,12 +100,11 @@ static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
continue;
- if (cpu_if->vgic_elrsr & (1UL << i)) {
+ if (cpu_if->vgic_elrsr & (1UL << i))
cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
- continue;
- }
+ else
+ cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
- cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
writel_relaxed(0, base + GICH_LR0 + (i * 4));
}
}