diff options
58 files changed, 7052 insertions, 1247 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index cb91507ffb1e..3868458a5feb 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -2,7 +2,10 @@ Allwinner Clock Control Unit Binding ------------------------------------ Required properties : -- compatible: must contain one of the following compatible: +- compatible: must contain one of the following compatibles: + - "allwinner,sun6i-a31-ccu" + - "allwinner,sun8i-a23-ccu" + - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" - reg: Must contain the registers base address and length diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..7b6bda3b4189 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -98,6 +98,7 @@ ezchip EZchip Semiconductor fcs Fairchild Semiconductor firefly Firefly focaltech FocalTech Systems Co.,Ltd +friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd fsl Freescale Semiconductor ge General Electric Company geekbuying GeekBuying diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..5b54f992ee28 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -719,6 +719,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-pcduino2.dtb \ sun4i-a10-pov-protab2-ips9.dtb dtb-$(CONFIG_MACH_SUN5I) += \ + ntc-gr8-evb.dtb \ sun5i-a10s-auxtek-t003.dtb \ sun5i-a10s-auxtek-t004.dtb \ sun5i-a10s-mk802.dtb \ @@ -727,6 +728,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-wobo-i5.dtb \ sun5i-a13-difrnce-dit4350.dtb \ sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-98v-rev2.dtb \ sun5i-a13-olinuxino.dtb \ @@ -743,6 +745,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-mele-a1000g-quad.dtb \ sun6i-a31s-colorfly-e708-q1.dtb \ sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ sun6i-a31s-primo81.dtb \ sun6i-a31s-sina31s.dtb \ sun6i-a31s-sinovoip-bpi-m2.dtb \ @@ -782,16 +785,22 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-q8-tablet.dtb \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index afbe89c01df5..675bb0f30825 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -53,6 +53,12 @@ interrupt-controller; #interrupt-cells = <1>; + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; diff --git a/arch/arm/boot/dts/ntc-gr8-evb.dts b/arch/arm/boot/dts/ntc-gr8-evb.dts new file mode 100644 index 000000000000..4b622f3b5220 --- /dev/null +++ b/arch/arm/boot/dts/ntc-gr8-evb.dts @@ -0,0 +1,342 @@ +/* + * Copyright 2016 Free Electrons + * Copyright 2016 NextThing Co + * + * Mylène Josserand <mylene.josserand@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "ntc-gr8.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "NextThing GR8-EVB"; + compatible = "nextthing,gr8-evb", "nextthing,gr8"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 10000 0>; + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; +}; + +&be0 { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + + /* + * The interrupt is routed through the "External Fast + * Interrupt Request" pin (ball G13 of the module) + * directly to the main interrupt controller, without + * any other controller interfering. + */ + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + wm8978: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@190 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <190000>; + }; + + button@390 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <390000>; + }; + + button@600 { + label = "Menu"; + linux,code = <KEY_MENU>; + channel = <0>; + voltage = <600000>; + }; + + button@800 { + label = "Search"; + linux,code = <KEY_SEARCH>; + channel = <0>; + voltage = <800000>; + }; + + button@980 { + label = "Home"; + linux,code = <KEY_HOMEPAGE>; + channel = <0>; + voltage = <980000>; + }; + + button@1180 { + label = "Esc"; + linux,code = <KEY_ESC>; + channel = <0>; + voltage = <1180000>; + }; + + button@1400 { + label = "Enter"; + linux,code = <KEY_ENTER>; + channel = <0>; + voltage = <1400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + + /* MLC Support sucks for now */ + status = "disabled"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_pin_gr8_evb: usb0-id-pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +®_dcdc2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; + regulator-always-on; +}; + +®_dcdc3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; + regulator-always-on; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; + regulator-always-on; +}; + +®_usb1_vbus { + pinctrl-0 = <&usb1_vbus_pin_gr8_evb>; + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&rtp { + allwinner,ts-attached; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; + +&tve0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>; + status = "okay"; +}; + +&usb_otg { + /* + * The GR8-EVB has a somewhat interesting design. There's a + * pin supposed to control VBUS, an ID pin, a VBUS detect pin, + * so everything should work just fine. + * + * Except that the pin supposed to control VBUS is not + * connected to any controllable output, neither to the SoC + * through a GPIO or to the PMIC, and it is pulled down, + * meaning that we will never be able to enable VBUS on this + * board. + */ + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/arm/boot/dts/ntc-gr8.dtsi new file mode 100644 index 000000000000..ca54e03ef366 --- /dev/null +++ b/arch/arm/boot/dts/ntc-gr8.dtsi @@ -0,0 +1,1087 @@ +/* + * Copyright 2016 Mylène Josserand + * + * Mylène Josserand <mylene.josserand@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/sun4i-a10-pll2.h> +#include <dt-bindings/dma/sun4i-a10.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&cpu>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc24M: clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-osc-clk"; + reg = <0x01c20050 0x4>; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc3M: osc3M-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + + osc32k: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-pll2-clk"; + reg = <0x01c20008 0x8>; + clocks = <&osc24M>; + clock-output-names = "pll2-1x", "pll2-2x", + "pll2-4x", "pll2-8x"; + }; + + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2-clk { + compatible = "allwinner,sun4i-a10-pll3-2x-clk"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + + pll4: clk@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll5: clk@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2-clk { + compatible = "allwinner,sun4i-a10-pll3-2x-clk"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + + /* dummy is 200M */ + cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; + clock-output-names = "cpu"; + }; + + axi: axi@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20054 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb: ahb@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&axi>, <&cpu>, <&pll6 1>; + clock-output-names = "ahb"; + /* + * Use PLL6 as parent, instead of CPU/AXI + * which has rate changes due to cpufreq + */ + assigned-clocks = <&ahb>; + assigned-clock-parents = <&pll6 1>; + }; + + apb0: apb0@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb>; + clock-output-names = "apb0"; + }; + + apb1: clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1"; + }; + + axi_gates: clk@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-indices = <0>; + clock-output-names = "axi_dram"; + }; + + ahb_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-indices = <0>, <1>, + <2>, <5>, <6>, + <7>, <8>, <9>, + <10>, <13>, + <14>, <17>, <20>, + <21>, <22>, + <28>, <32>, <34>, + <36>, <40>, <44>, + <46>, <51>, + <52>; + clock-output-names = "ahb_usbotg", "ahb_ehci", + "ahb_ohci", "ahb_ss", "ahb_dma", + "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_nand", + "ahb_sdram", "ahb_emac", "ahb_spi0", + "ahb_spi1", "ahb_spi2", + "ahb_hstimer", "ahb_ve", "ahb_tve", + "ahb_lcd", "ahb_csi", "ahb_de_be", + "ahb_de_fe", "ahb_iep", + "ahb_mali400"; + }; + + apb0_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-indices = <0>, <3>, + <5>, <6>; + clock-output-names = "apb0_codec", "apb0_i2s0", + "apb0_pio", "apb0_ir"; + }; + + apb1_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-indices = <0>, <1>, + <2>, <17>, + <18>, <19>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_uart1", + "apb1_uart2", "apb1_uart3"; + }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s0"; + }; + + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_phy"; + }; + + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "nextthing,gr8-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; + + de_be_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + + de_fe_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe"; + }; + + tcon_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + tcon_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; + + codec_clk: clk@01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "codec"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun5i-a13-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@01c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_a: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + }; + + sram_d: sram@00010000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0000 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 3>; + dma-names = "rxtx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 27>, + <&dma SUN4I_DMA_DEDICATED 26>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 9>, + <&dma SUN4I_DMA_DEDICATED 8>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + tve0: tv-encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + }; + }; + }; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <32>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <33>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + interrupts = <34>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c13000 { + compatible = "allwinner,sun4i-a10-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ahb_gates 0>; + interrupts = <38>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + + dr_mode = "otg"; + }; + + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun5i-a13-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4>; + reg-names = "phy_ctrl", "pmu1"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 0>, <&usb_clk 1>; + reset-names = "usb0_reset", "usb1_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <39>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <40>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <12>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + dmas = <&dma SUN4I_DMA_DEDICATED 29>, + <&dma SUN4I_DMA_DEDICATED 28>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-a10-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@01c20800 { + compatible = "nextthing,gr8-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2s0_data_pins_a: i2s0-data@0 { + allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,function = "i2s0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2s0_mclk_pins_a: i2s0-mclk@0 { + allwinner,pins = "PB6", "PB7", "PB8", "PB9"; + allwinner,function = "i2s0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + ir0_rx_pins_a: ir0@0 { + allwinner,pins = "PB4"; + allwinner,function = "ir0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + lcd_rgb666_pins: lcd-rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_pins_a: nand-base0@0 { + allwinner,pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_cs0_pins_a: nand-cs@0 { + allwinner,pins = "PC4"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + nand_rb0_pins_a: nand-rb@0 { + allwinner,pins = "PC6"; + allwinner,function = "nand0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB10"; + allwinner,function = "spdif"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + uart1_pins_a: uart1@1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart1_cts_rts_pins_a: uart1-cts-rts@0 { + allwinner,pins = "PG5", "PG6"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun5i-a10s-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <22>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + i2s0: i2s@01c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <16>; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lradc: lradc@01c22800 { + compatible = "allwinner,sun4i-a10-lradc-keys"; + reg = <0x01c22800 0x100>; + interrupts = <31>; + status = "disabled"; + }; + + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-codec"; + reg = <0x01c22c00 0x40>; + interrupts = <30>; + clocks = <&apb0_gates 0>, <&codec_clk>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 19>, + <&dma SUN4I_DMA_NORMAL 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + rtp: rtp@01c25000 { + compatible = "allwinner,sun5i-a13-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + #thermal-sensor-cells = <0>; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun4i-a10-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + timer@01c60000 { + compatible = "allwinner,sun5i-a13-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <82>, <83>; + clocks = <&ahb_gates 28>; + }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + status = "disabled"; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index f3cb297fd1db..5f98582232d6 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -121,10 +121,6 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - &otg_sram { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts new file mode 100644 index 000000000000..b1e2afd9de52 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Empire Electronix M712 tablet"; + compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts index 1b11ec95ae53..439ae3b537df 100644 --- a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts +++ b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts @@ -42,171 +42,9 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun5i-reference-design-tablet.dtsi" / { model = "INet-98V Rev 02"; compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index f694482bdeb6..b68a12374b35 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -64,6 +64,16 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + status { + label = "chip:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; }; &be0 { diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 1867af24ff52..6a84fe7e9ab2 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -47,7 +47,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/clock/sun6i-a31-ccu.h> #include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun6i-a31-ccu.h> / { interrupt-parent = <&gic>; @@ -65,7 +67,10 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, + <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, + <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; status = "disabled"; }; @@ -73,7 +78,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, + <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, + <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; status = "disabled"; }; }; @@ -97,7 +104,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - clocks = <&cpu>; + clocks = <&ccu CLK_CPU>; clock-latency = <244144>; /* 8 32k periods */ operating-points = < /* kHz uV */ @@ -192,235 +199,6 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - - /* - * Clock AHB1 from PLL6, instead of CPU/AXI which - * has rate changes due to cpufreq. Also the DMA - * controller requires AHB1 clocked from PLL6. - */ - assigned-clocks = <&ahb1>; - assigned-clock-parents = <&pll6 0>; - }; - - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <11>, <12>, - <13>, <14>, - <17>, <18>, <19>, - <20>, <21>, <22>, - <23>, <24>, <26>, - <27>, <29>, - <30>, <31>, <32>, - <36>, <37>, <40>, - <43>, <44>, <45>, - <46>, <47>, <50>, - <52>, <55>, <56>, - <57>, <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", - "ahb1_nand0", "ahb1_sdram", - "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", - "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", - "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", - "ahb1_ehci1", "ahb1_ohci0", - "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", - "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", - "ahb1_hdmi", "ahb1_de0", "ahb1_de1", - "ahb1_fe0", "ahb1_fe1", "ahb1_mp", - "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", - "ahb1_drc0", "ahb1_drc1"; - }; - - apb1: apb1@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <4>, - <5>, <12>, - <13>; - clock-output-names = "apb1_codec", "apb1_digital_mic", - "apb1_pio", "apb1_daudio0", - "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <3>, <16>, - <17>, <18>, <19>, - <20>, <21>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_i2c3", - "apb2_uart0", "apb2_uart1", - "apb2_uart2", "apb2_uart3", - "apb2_uart4", "apb2_uart5"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@01c20094 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc3", - "mmc3_output", - "mmc3_sample"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; - - spi0_clk: clk@01c200a0 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi0"; - }; - - spi1_clk: clk@01c200a4 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi1"; - }; - - spi2_clk: clk@01c200a8 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi2"; - }; - - spi3_clk: clk@01c200ac { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "spi3"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-indices = <8>, <9>, <10>, - <16>, <17>, - <18>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", - "usb_ohci0", "usb_ohci1", - "usb_ohci2"; - }; - /* * The following two are dummy clocks, placeholders * used in the gmac_tx clock. The gmac driver will @@ -463,23 +241,23 @@ compatible = "allwinner,sun6i-a31-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_AHB1_DMA>; + resets = <&ccu RST_AHB1_DMA>; #dma-cells = <1>; }; mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_AHB1_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_AHB1_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -490,15 +268,15 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_AHB1_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_AHB1_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -509,15 +287,15 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_AHB1_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_AHB1_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -528,15 +306,15 @@ mmc3: mmc@01c12000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&ahb1_gates 11>, - <&mmc3_clk 0>, - <&mmc3_clk 1>, - <&mmc3_clk 2>; + clocks = <&ccu CLK_AHB1_MMC3>, + <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 11>; + resets = <&ccu RST_AHB1_MMC3>; reset-names = "ahb"; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -547,8 +325,8 @@ usb_otg: usb@01c19000 { compatible = "allwinner,sun6i-a31-musb"; reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; + clocks = <&ccu CLK_AHB1_OTG>; + resets = <&ccu RST_AHB1_OTG>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; phys = <&usbphy 0>; @@ -565,15 +343,15 @@ reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&usb_clk 8>, - <&usb_clk 9>, - <&usb_clk 10>; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; clock-names = "usb0_phy", "usb1_phy", "usb2_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>, - <&usb_clk 2>; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; @@ -585,8 +363,8 @@ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_AHB1_EHCI0>; + resets = <&ccu RST_AHB1_EHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -596,8 +374,8 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_AHB1_OHCI0>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -607,8 +385,8 @@ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 27>; - resets = <&ahb1_rst 27>; + clocks = <&ccu CLK_AHB1_EHCI1>; + resets = <&ccu RST_AHB1_EHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -618,8 +396,8 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1b400 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 30>, <&usb_clk 17>; - resets = <&ahb1_rst 30>; + clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_AHB1_OHCI1>; phys = <&usbphy 2>; phy-names = "usb"; status = "disabled"; @@ -629,11 +407,20 @@ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; reg = <0x01c1c400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 31>, <&usb_clk 18>; - resets = <&ahb1_rst 31>; + clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_AHB1_OHCI2>; status = "disabled"; }; + ccu: clock@01c20000 { + compatible = "allwinner,sun6i-a31-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -641,7 +428,7 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_APB1_PIO>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -762,24 +549,6 @@ }; }; - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; - }; - timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; @@ -816,8 +585,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_APB2_UART0>; + resets = <&ccu RST_APB2_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; @@ -829,8 +598,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_APB2_UART1>; + resets = <&ccu RST_APB2_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; @@ -842,8 +611,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_APB2_UART2>; + resets = <&ccu RST_APB2_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -855,8 +624,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_APB2_UART3>; + resets = <&ccu RST_APB2_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -868,8 +637,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_APB2_UART4>; + resets = <&ccu RST_APB2_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -881,8 +650,8 @@ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 21>; - resets = <&apb2_rst 21>; + clocks = <&ccu CLK_APB2_UART5>; + resets = <&ccu RST_APB2_UART5>; dmas = <&dma 22>, <&dma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -892,8 +661,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_APB2_I2C0>; + resets = <&ccu RST_APB2_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -903,8 +672,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_APB2_I2C1>; + resets = <&ccu RST_APB2_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -914,8 +683,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_APB2_I2C2>; + resets = <&ccu RST_APB2_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -925,8 +694,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 3>; - resets = <&apb2_rst 3>; + clocks = <&ccu CLK_APB2_I2C3>; + resets = <&ccu RST_APB2_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -937,9 +706,9 @@ reg = <0x01c30000 0x1054>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; + clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ahb1_rst 17>; + resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; @@ -953,9 +722,9 @@ compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_AHB1_SS>; reset-names = "ahb"; }; @@ -967,19 +736,19 @@ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 19>; - resets = <&ahb1_rst 19>; + clocks = <&ccu CLK_AHB1_HSTIMER>; + resets = <&ccu RST_AHB1_HSTIMER>; }; spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 20>, <&spi0_clk>; + clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; dmas = <&dma 23>, <&dma 23>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 20>; + resets = <&ccu RST_AHB1_SPI0>; status = "disabled"; }; @@ -987,11 +756,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c69000 0x1000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 21>, <&spi1_clk>; + clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; dmas = <&dma 24>, <&dma 24>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 21>; + resets = <&ccu RST_AHB1_SPI1>; status = "disabled"; }; @@ -999,11 +768,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6a000 0x1000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 22>, <&spi2_clk>; + clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; clock-names = "ahb", "mod"; dmas = <&dma 25>, <&dma 25>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 22>; + resets = <&ccu RST_AHB1_SPI2>; status = "disabled"; }; @@ -1011,11 +780,11 @@ compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c6b000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 23>, <&spi3_clk>; + clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; clock-names = "ahb", "mod"; dmas = <&dma 26>, <&dma 26>; dma-names = "rx", "tx"; - resets = <&ahb1_rst 23>; + resets = <&ccu RST_AHB1_SPI3>; status = "disabled"; }; @@ -1052,8 +821,9 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, - <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, + <&ccu CLK_PLL_PERIPH>, + <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts index e182eec6d878..882a4d89fa22 100644 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -42,32 +42,11 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include "sun6i-reference-design-tablet.dtsi" / { model = "Colorfly E708 Q1 tablet"; compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; }; &lradc { @@ -82,103 +61,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&pio { - mma8452_int_e708_q1: mma8452_int_pin@0 { - allwinner,pins = "PA9"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - ®_dldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -186,23 +68,5 @@ }; &simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; vcc-pg-supply = <®_dldo2>; }; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp221 pmic on the board. - * - * Once we have axp221 power-supply and vbus-usb support we should switch - * to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts new file mode 100644 index 000000000000..e584e6b186a7 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts @@ -0,0 +1,100 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sun6i-reference-design-tablet.dtsi" + +/ { + model = "iNet Q972 tablet"; + compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button@200 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <200000>; + }; + + button@900 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <900000>; + }; + + button@1200 { + label = "Back"; + linux,code = <KEY_BACK>; + channel = <0>; + voltage = <1200000>; + }; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi new file mode 100644 index 000000000000..0c434304e040 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -0,0 +1,193 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + /* Wifi is connected here */ + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 7e05e09e61c7..01d8bbf08749 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -46,7 +46,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> / { interrupt-parent = <&gic>; @@ -60,7 +62,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, + <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; status = "disabled"; }; }; @@ -111,143 +115,6 @@ clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - /* dummy clock until actually implemented */ - pll5: pll5_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll5"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - }; - - apb1: apb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <5>, - <12>, <13>; - clock-output-names = "apb1_codec", "apb1_pio", - "apb1_daudio0", "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <16>, - <17>, <18>, - <19>, <20>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_uart0", - "apb2_uart1", "apb2_uart2", - "apb2_uart3", "apb2_uart4"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun8i-a23-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", - "usb_hsic_12M", "usb_ohci0"; - }; }; soc@01c00000 { @@ -260,23 +127,23 @@ compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; #dma-cells = <1>; }; mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -287,15 +154,15 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -306,15 +173,15 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -322,12 +189,55 @@ #size-cells = <0>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c19000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + /* + * compatible and address regions get set in + * SoC specific dtsi file + */ + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + ehci0: usb@01c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_BUS_EHCI>; + resets = <&ccu RST_BUS_EHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -337,18 +247,26 @@ compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; + resets = <&ccu RST_BUS_OHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; + ccu: clock@01c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_BUS_PIO>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; @@ -414,24 +332,16 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - }; - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202c0 0xc>; - }; - - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; + lcd_rgb666_pins: lcd-rgb666@0 { + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; timer@01c20c00 { @@ -469,8 +379,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; @@ -482,8 +392,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; @@ -495,8 +405,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -508,8 +418,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -521,8 +431,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -532,8 +442,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -543,8 +453,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -554,8 +464,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts index b2ce284a65a2..f27ebbbeac09 100644 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts @@ -42,70 +42,18 @@ /dts-v1/; #include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> -#include <dt-bindings/pwm/pwm.h> +#include "sun8i-reference-design-tablet.dtsi" / { model = "Allwinner GT90H Dual Core Tablet (v4)"; compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; - - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_gt90h>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; &ehci0 { status = "okay"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - &lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; - button@600 { label = "Back"; linux,code = <KEY_BACK>; @@ -114,144 +62,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>; - vmmc-supply = <®_aldo1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin_gt90h: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_cd_pin_gt90h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - &usbphy { usb1_vbus-supply = <®_dldo1>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index e3004428e7a7..4789aac89955 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -47,4 +47,46 @@ / { model = "Polaroid MID2407PXE03 tablet"; compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2407>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 6d06e24d446b..c9213caf7424 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -47,4 +47,46 @@ / { model = "Polaroid MID2809PXE04 tablet"; compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2809>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 92e6616979ea..54d045dab825 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -48,74 +48,10 @@ memory { reg = <0x40000000 0x40000000>; }; +}; - clocks { - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <6>, - <8>, <9>, <10>, - <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>; - clock-output-names = "ahb1_mipidsi", "ahb1_dma", - "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", - "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>; - clock-output-names = "mbus"; - }; - }; - - soc@01c00000 { - usb_otg: usb@01c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - }; +&ccu { + compatible = "allwinner,sun8i-a23-ccu"; }; &pio { @@ -124,3 +60,13 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; }; + +&usb_otg { + compatible = "allwinner,sun6i-a31-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index 65660324005c..de6269dcac3a 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -47,6 +47,11 @@ / { model = "Allwinner GA10H Quad Core Tablet (v1.1)"; compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; + + aliases { + /* Make u-boot set mac-address for rtl8703as (no eeprom) */ + ethernet0 = &rtl8703as; + }; }; &ehci0 { @@ -62,6 +67,19 @@ }; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8703as: sdio_wifi@1 { + reg = <1>; + }; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts new file mode 100644 index 000000000000..0f52cd9dfa41 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -0,0 +1,88 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * Copyright 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-D978 Rev 02"; + compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_d978>; + + home { + label = "d978:blue:home"; + gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + led_pin_d978: led_pin_d978@0 { + allwinner,pins = "PL5"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts new file mode 100644 index 000000000000..9ea637e82b2d --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 - Stefan Mavrodiev <stefan.mavrodiev@gmail.com> + * Olimex LTD. <support@olimex.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Olimex A33-OLinuXino"; + compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_olinuxino>; + + green { + label = "a33-olinuxino:green:usr"; + gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + led_pin_olinuxino: led_pins@0 { + allwinner,pins = "PB7"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PB3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 001d8402ca18..fd1e1cddd4a8 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -59,107 +59,179 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-a33-display-engine"; + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + memory { reg = <0x40000000 0x80000000>; }; - clocks { - /* Dummy clock for pll11 (DDR1) until actually implemented */ - pll11: pll11_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll11"; - }; + soc@01c00000 { + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun8i-a33-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_LCD>; + reset-names = "lcd"; + status = "disabled"; - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a33-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>, - <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma","ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc", - "ahb1_sat"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>; - clock-output-names = "mbus"; + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; }; - }; - soc@01c00000 { crypto: crypto-engine@01c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_BUS_SS>; reset-names = "ahb"; }; - usb_otg: usb@01c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun8i-a33-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; }; - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; + be0: display-backend@01e60000 { + compatible = "allwinner,sun8i-a33-display-backend"; + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@01e70000 { + compatible = "allwinner,sun8i-a33-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + assigned-clocks = <&ccu CLK_DRC>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; }; }; }; +&ccu { + compatible = "allwinner,sun8i-a33-ccu"; +}; + &pio { compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, @@ -173,3 +245,13 @@ }; }; + +&usb_otg { + compatible = "allwinner,sun8i-a33-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts new file mode 100644 index 000000000000..3d64cafc1e90 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 James Pettigrew <james@innovum.com.au> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index f93f5d1695c4..f89fe00ddec5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189; }; chosen { @@ -131,6 +133,14 @@ bus-width = <4>; non-removable; status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189: sdio_wifi@1 { + reg = <1>; + }; }; &pio { diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts new file mode 100644 index 000000000000..1550fee1ec68 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Lite"; + compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; + + aliases { + /* The H3 emac is not used so the wifi is ethernet0 */ + ethernet0 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts new file mode 100644 index 000000000000..851fd2c2cc8c --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" + +/ { + model = "Xunlong Orange Pi PC Plus"; + compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; + + aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index b0cb41787e09..bb585918cf54 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -44,7 +44,7 @@ #include "sun8i-h3-orangepi-2.dts" / { - model = "Xunlong Orange Pi Plus"; + model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; reg_usb3_vbus: usb3-vbus { diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts new file mode 100644 index 000000000000..5851a47a3089 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, + * with 2G RAM and an external gbit ethernet phy. + */ + +#include "sun8i-h3-orangepi-pc-plus.dts" + +/ { + model = "Xunlong Orange Pi Plus 2E"; + compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index fdf9fdbda267..6d83b8674201 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -389,6 +389,14 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; }; + pwm: pwm@01c21400 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 60fa9585022b..29f837a47771 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -42,10 +42,59 @@ #include "sunxi-reference-design-tablet.dtsi" #include "sun8i-reference-design-tablet.dtsi" +/ { + aliases { + serial0 = &r_uart; + /* Make u-boot set mac-address for wifi without an eeprom */ + ethernet0 = &sdio_wifi; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + /* + * Q8 boards use various PL# pins as wifi-en. On other boards + * these may be connected to a wifi module output pin. To avoid + * short-circuits we configure these as inputs with pull-ups via + * pinctrl, instead of listing them as active-low reset-gpios. + */ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_q8>; + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + &ehci0 { status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&r_pio { + wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6", "PL7", "PL11"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 9d9036140511..08cd00143635 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -63,6 +63,25 @@ }; }; +&i2c0 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * The gsl1680 is the only device on this bus. + */ + clock-frequency = <400000>; + + touchscreen: touchscreen@0 { + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + /* Tablet dts must provide reg and compatible */ + status = "disabled"; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; @@ -88,6 +107,13 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + ts_power_pin: ts_power_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH8"; allwinner,function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 1526b41c70f1..04b014603659 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -103,6 +103,11 @@ allwinner,drive = <SUN4I_PINCTRL_40_MA>; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_cubieboard4: led-pins@0 { allwinner,pins = "PH6", "PH17"; @@ -250,6 +255,30 @@ }; }; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; #include "axp809.dtsi" diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 7fd22e888602..fd874ded890e 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -152,6 +152,11 @@ status = "okay"; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; @@ -322,6 +327,30 @@ }; }; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; #include "axp809.dtsi" diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f68b3242b33a..3c5214cbe4e6 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -148,15 +148,14 @@ /* * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This clock is by default enabled - * and clocked at 32768 Hz, from the oscillator connected - * to the AC100. It is configurable, but no such driver or - * bindings exist yet. + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. */ osc32k: osc32k_clk { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; clock-output-names = "osc32k"; }; @@ -899,8 +898,7 @@ resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; r_ir_pins: r_ir { diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 2afcbd39e41e..254d9526c018 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -1,5 +1,6 @@ config SUNXI_CCU bool "Clock support for Allwinner SoCs" + depends on ARCH_SUNXI || COMPILE_TEST default ARCH_SUNXI if SUNXI_CCU @@ -19,6 +20,10 @@ config SUNXI_CCU_GATE config SUNXI_CCU_MUX bool +config SUNXI_CCU_MULT + bool + select SUNXI_CCU_MUX + config SUNXI_CCU_PHASE bool @@ -51,6 +56,40 @@ config SUNXI_CCU_MP # SoC Drivers +config SUN6I_A31_CCU + bool "Support for the Allwinner A31/A31s CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default MACH_SUN6I + +config SUN8I_A23_CCU + bool "Support for the Allwinner A23 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_MULT + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default MACH_SUN8I + +config SUN8I_A33_CCU + bool "Support for the Allwinner A33 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_MULT + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default MACH_SUN8I + config SUN8I_H3_CCU bool "Support for the Allwinner H3 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 633ce642ffae..106cba27c331 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SUNXI_CCU_DIV) += ccu_div.o obj-$(CONFIG_SUNXI_CCU_FRAC) += ccu_frac.o obj-$(CONFIG_SUNXI_CCU_GATE) += ccu_gate.o obj-$(CONFIG_SUNXI_CCU_MUX) += ccu_mux.o +obj-$(CONFIG_SUNXI_CCU_MULT) += ccu_mult.o obj-$(CONFIG_SUNXI_CCU_PHASE) += ccu_phase.o # Multi-factor clocks @@ -17,4 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM) += ccu_nm.o obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o # SoC support +obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o +obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o +obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c new file mode 100644 index 000000000000..f1d61faa5bd9 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -0,0 +1,1235 @@ +/* + * Copyright (c) 2016 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * Based on ccu-sun8i-h3.c by Maxime Ripard. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_mux.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun6i-a31.h" + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", + "osc24M", 0x000, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN6I_A31_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", + "osc24M", 0x028, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", + "osc24M", 0x038, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +/* + * The MIPI PLL has 2 modes: "MIPI" and "HDMI". + * + * The MIPI mode is a standard NKM-style clock. The HDMI mode is an + * integer / fractional clock with switchable multipliers and dividers. + * This is not supported here. We hardcode the PLL to MIPI mode. + */ +#define SUN6I_A31_PLL_MIPI_REG 0x040 + +static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" }; +static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi", + pll_mipi_parents, 0x040, + 8, 4, /* N */ + 4, 2, /* K */ + 0, 4, /* M */ + 21, 0, /* mux */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9", + "osc24M", 0x044, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpu", "pll-cpu" }; +static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents, + 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); + +static struct clk_div_table axi_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 3 }, + { .val = 3, .div = 4 }, + { .val = 4, .div = 4 }, + { .val = 5, .div = 4 }, + { .val = 6, .div = 4 }, + { .val = 7, .div = 4 }, + { /* Sentinel */ }, +}; + +static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", + 0x050, 0, 3, axi_div_table, 0); + +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi", "pll-periph" }; + +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .variable_prediv = { + .index = 3, + .shift = 6, + .width = 2, + }, + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; + +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-periph", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1", + 0x060, BIT(1), 0); +static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1", + 0x060, BIT(5), 0); +static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1", + 0x060, BIT(12), 0); +static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1", + 0x060, BIT(17), 0); +static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1", + 0x060, BIT(18), 0); +static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1", + 0x060, BIT(19), 0); +static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1", + 0x060, BIT(22), 0); +static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1", + 0x060, BIT(23), 0); +static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1", + 0x060, BIT(26), 0); +static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1", + 0x060, BIT(27), 0); +static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1", + 0x060, BIT(29), 0); +static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1", + 0x060, BIT(30), 0); +static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1", + 0x060, BIT(31), 0); + +static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1", + 0x064, BIT(5), 0); +static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1", + 0x064, BIT(11), 0); +static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1", + 0x064, BIT(13), 0); +static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1", + 0x064, BIT(14), 0); +static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1", + 0x064, BIT(15), 0); +static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1", + 0x064, BIT(18), 0); +static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1", + 0x064, BIT(20), 0); +static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1", + 0x064, BIT(23), 0); +static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1", + 0x064, BIT(24), 0); +static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1", + 0x064, BIT(25), 0); +static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1", + 0x064, BIT(26), 0); + +static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1", + 0x068, BIT(4), 0); +static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1", + 0x068, BIT(13), 0); + +static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2", + 0x06c, BIT(3), 0); +static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2", + 0x06c, BIT(20), 0); +static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2", + 0x06c, BIT(21), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents, + 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents, + 0x084, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, + 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, + 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, + 0x090, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", + 0x090, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", + 0x090, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, + 0x094, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3", + 0x094, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3", + 0x094, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents, + 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents, + 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", + 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", + 0x0cc, BIT(9), 0); +static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", + 0x0cc, BIT(10), 0); +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", + 0x0cc, BIT(16), 0); +static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M", + 0x0cc, BIT(17), 0); +static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", + 0x0cc, BIT(18), 0); + +/* TODO emac clk not supported yet */ + +static const char * const dram_parents[] = { "pll-ddr", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL); + +static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents, + 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL); +static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents, + 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs", + 0x100, BIT(3), 0); +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs", + 0x100, BIT(16), 0); +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs", + 0x100, BIT(17), 0); +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs", + 0x100, BIT(18), 0); +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs", + 0x100, BIT(19), 0); +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs", + 0x100, BIT(25), 0); +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs", + 0x100, BIT(26), 0); +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs", + 0x100, BIT(27), 0); +static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs", + 0x100, BIT(28), 0); + +static const char * const de_parents[] = { "pll-video0", "pll-video1", + "pll-periph-2x", "pll-gpu", + "pll9", "pll10" }; +static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents, + 0x104, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents, + 0x108, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents, + 0x10c, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents, + 0x110, 0, 4, 24, 3, BIT(31), 0); + +static const char * const mp_parents[] = { "pll-video0", "pll-video1", + "pll9", "pll10" }; +static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents, + 0x114, 0, 4, 24, 3, BIT(31), 0); + +static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1", + "pll-video0-2x", + "pll-video1-2x", "pll-mipi" }; +static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents, + 0x118, 24, 2, BIT(31), 0); +static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents, + 0x11c, 24, 2, BIT(31), 0); + +static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1", + "pll-video0-2x", + "pll-video1-2x" }; +static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, + 0x12c, 0, 4, 24, 3, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents, + 0x12c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1", + "pll9", "pll10", "pll-mipi", + "pll-ve" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents, + 0x134, 16, 4, 24, 3, BIT(31), 0); + +static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1", + "osc24M" }; +static const u8 csi_mclk_table[] = { 0, 1, 5 }; +static struct ccu_div csi0_mclk_clk = { + .enable = BIT(15), + .div = _SUNXI_CCU_DIV(0, 4), + .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table), + .common = { + .reg = 0x134, + .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk", + csi_mclk_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div csi1_mclk_clk = { + .enable = BIT(15), + .div = _SUNXI_CCU_DIV(0, 4), + .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table), + .common = { + .reg = 0x138, + .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk", + csi_mclk_parents, + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", + 0x13c, 16, 3, BIT(31), 0); + +static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", + 0x140, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", + 0x144, BIT(31), 0); +static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio", + 0x148, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, + 0x150, 0, 4, 24, 2, BIT(31), 0); + +static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0); + +static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); + +static const char * const mbus_parents[] = { "osc24M", "pll-periph", + "pll-ddr" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c, + 0, 3, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160, + 0, 3, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL); + +static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents, + 0x168, 16, 3, 24, 2, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy", + lcd_ch1_parents, 0x168, 0, 3, 8, 2, + BIT(15), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy", + lcd_ch1_parents, 0x168, 0, 3, 8, 2, + BIT(15), 0); + +static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents, + 0x180, 0, 3, 24, 2, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents, + 0x184, 0, 3, 24, 2, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents, + 0x188, 0, 3, 24, 2, BIT(31), 0); +static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents, + 0x18c, 0, 3, 24, 2, BIT(31), 0); + +static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x", + "pll-video0", "pll-video1", + "pll9", "pll10" }; +static const struct ccu_mux_fixed_prediv gpu_predivs[] = { + { .index = 1, .div = 3, }, +}; + +static struct ccu_div gpu_core_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV(0, 3), + .mux = { + .shift = 24, + .width = 3, + .fixed_predivs = gpu_predivs, + .n_predivs = ARRAY_SIZE(gpu_predivs), + }, + .common = { + .reg = 0x1a0, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("gpu-core", + gpu_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div gpu_memory_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV(0, 3), + .mux = { + .shift = 24, + .width = 3, + .fixed_predivs = gpu_predivs, + .n_predivs = ARRAY_SIZE(gpu_predivs), + }, + .common = { + .reg = 0x1a4, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("gpu-memory", + gpu_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div gpu_hyd_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV(0, 3), + .mux = { + .shift = 24, + .width = 3, + .fixed_predivs = gpu_predivs, + .n_predivs = ARRAY_SIZE(gpu_predivs), + }, + .common = { + .reg = 0x1a8, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd", + gpu_parents, + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0, + 0, 3, /* M */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents, + 0x1b0, + 0, 3, /* M */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M", + "axi", "ahb1" }; +static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 }; + +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = { + { .index = 0, .div = 750, }, + { .index = 3, .div = 4, }, + { .index = 4, .div = 4, }, +}; + +static struct ccu_mp out_a_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(8, 5), + .p = _SUNXI_CCU_DIV(20, 2), + .mux = { + .shift = 24, + .width = 4, + .table = clk_out_table, + .fixed_predivs = clk_out_predivs, + .n_predivs = ARRAY_SIZE(clk_out_predivs), + }, + .common = { + .reg = 0x300, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("out-a", + clk_out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_mp out_b_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(8, 5), + .p = _SUNXI_CCU_DIV(20, 2), + .mux = { + .shift = 24, + .width = 4, + .table = clk_out_table, + .fixed_predivs = clk_out_predivs, + .n_predivs = ARRAY_SIZE(clk_out_predivs), + }, + .common = { + .reg = 0x304, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("out-b", + clk_out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_mp out_c_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(8, 5), + .p = _SUNXI_CCU_DIV(20, 2), + .mux = { + .shift = 24, + .width = 4, + .table = clk_out_table, + .fixed_predivs = clk_out_predivs, + .n_predivs = ARRAY_SIZE(clk_out_predivs), + }, + .common = { + .reg = 0x308, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("out-c", + clk_out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_common *sun6i_a31_ccu_clks[] = { + &pll_cpu_clk.common, + &pll_audio_base_clk.common, + &pll_video0_clk.common, + &pll_ve_clk.common, + &pll_ddr_clk.common, + &pll_periph_clk.common, + &pll_video1_clk.common, + &pll_gpu_clk.common, + &pll_mipi_clk.common, + &pll9_clk.common, + &pll10_clk.common, + &cpu_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &ahb1_mipidsi_clk.common, + &ahb1_ss_clk.common, + &ahb1_dma_clk.common, + &ahb1_mmc0_clk.common, + &ahb1_mmc1_clk.common, + &ahb1_mmc2_clk.common, + &ahb1_mmc3_clk.common, + &ahb1_nand1_clk.common, + &ahb1_nand0_clk.common, + &ahb1_sdram_clk.common, + &ahb1_emac_clk.common, + &ahb1_ts_clk.common, + &ahb1_hstimer_clk.common, + &ahb1_spi0_clk.common, + &ahb1_spi1_clk.common, + &ahb1_spi2_clk.common, + &ahb1_spi3_clk.common, + &ahb1_otg_clk.common, + &ahb1_ehci0_clk.common, + &ahb1_ehci1_clk.common, + &ahb1_ohci0_clk.common, + &ahb1_ohci1_clk.common, + &ahb1_ohci2_clk.common, + &ahb1_ve_clk.common, + &ahb1_lcd0_clk.common, + &ahb1_lcd1_clk.common, + &ahb1_csi_clk.common, + &ahb1_hdmi_clk.common, + &ahb1_be0_clk.common, + &ahb1_be1_clk.common, + &ahb1_fe0_clk.common, + &ahb1_fe1_clk.common, + &ahb1_mp_clk.common, + &ahb1_gpu_clk.common, + &ahb1_deu0_clk.common, + &ahb1_deu1_clk.common, + &ahb1_drc0_clk.common, + &ahb1_drc1_clk.common, + &apb1_codec_clk.common, + &apb1_spdif_clk.common, + &apb1_digital_mic_clk.common, + &apb1_pio_clk.common, + &apb1_daudio0_clk.common, + &apb1_daudio1_clk.common, + &apb2_i2c0_clk.common, + &apb2_i2c1_clk.common, + &apb2_i2c2_clk.common, + &apb2_i2c3_clk.common, + &apb2_uart0_clk.common, + &apb2_uart1_clk.common, + &apb2_uart2_clk.common, + &apb2_uart3_clk.common, + &apb2_uart4_clk.common, + &apb2_uart5_clk.common, + &nand0_clk.common, + &nand1_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc2_sample_clk.common, + &mmc2_output_clk.common, + &mmc3_clk.common, + &mmc3_sample_clk.common, + &mmc3_output_clk.common, + &ts_clk.common, + &ss_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spi3_clk.common, + &daudio0_clk.common, + &daudio1_clk.common, + &spdif_clk.common, + &usb_phy0_clk.common, + &usb_phy1_clk.common, + &usb_phy2_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &usb_ohci2_clk.common, + &mdfs_clk.common, + &sdram0_clk.common, + &sdram1_clk.common, + &dram_ve_clk.common, + &dram_csi_isp_clk.common, + &dram_ts_clk.common, + &dram_drc0_clk.common, + &dram_drc1_clk.common, + &dram_deu0_clk.common, + &dram_deu1_clk.common, + &dram_fe0_clk.common, + &dram_fe1_clk.common, + &dram_be0_clk.common, + &dram_be1_clk.common, + &dram_mp_clk.common, + &be0_clk.common, + &be1_clk.common, + &fe0_clk.common, + &fe1_clk.common, + &mp_clk.common, + &lcd0_ch0_clk.common, + &lcd1_ch0_clk.common, + &lcd0_ch1_clk.common, + &lcd1_ch1_clk.common, + &csi0_sclk_clk.common, + &csi0_mclk_clk.common, + &csi1_mclk_clk.common, + &ve_clk.common, + &codec_clk.common, + &avs_clk.common, + &digital_mic_clk.common, + &hdmi_clk.common, + &hdmi_ddc_clk.common, + &ps_clk.common, + &mbus0_clk.common, + &mbus1_clk.common, + &mipi_dsi_clk.common, + &mipi_dsi_dphy_clk.common, + &mipi_csi_dphy_clk.common, + &iep_drc0_clk.common, + &iep_drc1_clk.common, + &iep_deu0_clk.common, + &iep_deu1_clk.common, + &gpu_core_clk.common, + &gpu_memory_clk.common, + &gpu_hyd_clk.common, + &ats_clk.common, + &trace_clk.common, + &out_a_clk.common, + &out_b_clk.common, + &out_c_clk.common, +}; + +/* We hardcode the divider to 4 for now */ +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", + "pll-periph", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", + "pll-video0", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", + "pll-video1", 1, 2, 0); + +static struct clk_hw_onecell_data sun6i_a31_hw_clks = { + .hws = { + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, + [CLK_PLL9] = &pll9_clk.common.hw, + [CLK_PLL10] = &pll10_clk.common.hw, + [CLK_CPU] = &cpu_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw, + [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw, + [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw, + [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw, + [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw, + [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw, + [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw, + [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw, + [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw, + [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw, + [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw, + [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw, + [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw, + [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw, + [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw, + [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw, + [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw, + [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw, + [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw, + [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw, + [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw, + [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw, + [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw, + [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw, + [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw, + [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw, + [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw, + [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw, + [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw, + [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw, + [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw, + [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw, + [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw, + [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw, + [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw, + [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw, + [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw, + [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw, + [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw, + [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw, + [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw, + [CLK_APB1_PIO] = &apb1_pio_clk.common.hw, + [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw, + [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw, + [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw, + [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw, + [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw, + [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw, + [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw, + [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw, + [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw, + [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw, + [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw, + [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw, + [CLK_NAND0] = &nand0_clk.common.hw, + [CLK_NAND1] = &nand1_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, + [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw, + [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw, + [CLK_TS] = &ts_clk.common.hw, + [CLK_SS] = &ss_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_DAUDIO0] = &daudio0_clk.common.hw, + [CLK_DAUDIO1] = &daudio1_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, + [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, + [CLK_MDFS] = &mdfs_clk.common.hw, + [CLK_SDRAM0] = &sdram0_clk.common.hw, + [CLK_SDRAM1] = &sdram1_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw, + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, + [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw, + [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw, + [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw, + [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw, + [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw, + [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw, + [CLK_DRAM_BE0] = &dram_be0_clk.common.hw, + [CLK_DRAM_BE1] = &dram_be1_clk.common.hw, + [CLK_DRAM_MP] = &dram_mp_clk.common.hw, + [CLK_BE0] = &be0_clk.common.hw, + [CLK_BE1] = &be1_clk.common.hw, + [CLK_FE0] = &fe0_clk.common.hw, + [CLK_FE1] = &fe1_clk.common.hw, + [CLK_MP] = &mp_clk.common.hw, + [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw, + [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw, + [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw, + [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw, + [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw, + [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, + [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_CODEC] = &codec_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw, + [CLK_HDMI] = &hdmi_clk.common.hw, + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, + [CLK_PS] = &ps_clk.common.hw, + [CLK_MBUS0] = &mbus0_clk.common.hw, + [CLK_MBUS1] = &mbus1_clk.common.hw, + [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw, + [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw, + [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw, + [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw, + [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw, + [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw, + [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw, + [CLK_GPU_CORE] = &gpu_core_clk.common.hw, + [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw, + [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw, + [CLK_ATS] = &ats_clk.common.hw, + [CLK_TRACE] = &trace_clk.common.hw, + [CLK_OUT_A] = &out_a_clk.common.hw, + [CLK_OUT_B] = &out_b_clk.common.hw, + [CLK_OUT_C] = &out_c_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun6i_a31_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, + + [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) }, + [RST_AHB1_SS] = { 0x2c0, BIT(5) }, + [RST_AHB1_DMA] = { 0x2c0, BIT(6) }, + [RST_AHB1_MMC0] = { 0x2c0, BIT(8) }, + [RST_AHB1_MMC1] = { 0x2c0, BIT(9) }, + [RST_AHB1_MMC2] = { 0x2c0, BIT(10) }, + [RST_AHB1_MMC3] = { 0x2c0, BIT(11) }, + [RST_AHB1_NAND1] = { 0x2c0, BIT(12) }, + [RST_AHB1_NAND0] = { 0x2c0, BIT(13) }, + [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) }, + [RST_AHB1_EMAC] = { 0x2c0, BIT(17) }, + [RST_AHB1_TS] = { 0x2c0, BIT(18) }, + [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_AHB1_SPI0] = { 0x2c0, BIT(20) }, + [RST_AHB1_SPI1] = { 0x2c0, BIT(21) }, + [RST_AHB1_SPI2] = { 0x2c0, BIT(22) }, + [RST_AHB1_SPI3] = { 0x2c0, BIT(23) }, + [RST_AHB1_OTG] = { 0x2c0, BIT(24) }, + [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) }, + [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) }, + [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) }, + [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) }, + [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) }, + + [RST_AHB1_VE] = { 0x2c4, BIT(0) }, + [RST_AHB1_LCD0] = { 0x2c4, BIT(4) }, + [RST_AHB1_LCD1] = { 0x2c4, BIT(5) }, + [RST_AHB1_CSI] = { 0x2c4, BIT(8) }, + [RST_AHB1_HDMI] = { 0x2c4, BIT(11) }, + [RST_AHB1_BE0] = { 0x2c4, BIT(12) }, + [RST_AHB1_BE1] = { 0x2c4, BIT(13) }, + [RST_AHB1_FE0] = { 0x2c4, BIT(14) }, + [RST_AHB1_FE1] = { 0x2c4, BIT(15) }, + [RST_AHB1_MP] = { 0x2c4, BIT(18) }, + [RST_AHB1_GPU] = { 0x2c4, BIT(20) }, + [RST_AHB1_DEU0] = { 0x2c4, BIT(23) }, + [RST_AHB1_DEU1] = { 0x2c4, BIT(24) }, + [RST_AHB1_DRC0] = { 0x2c4, BIT(25) }, + [RST_AHB1_DRC1] = { 0x2c4, BIT(26) }, + [RST_AHB1_LVDS] = { 0x2c8, BIT(0) }, + + [RST_APB1_CODEC] = { 0x2d0, BIT(0) }, + [RST_APB1_SPDIF] = { 0x2d0, BIT(1) }, + [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) }, + [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) }, + [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) }, + + [RST_APB2_I2C0] = { 0x2d8, BIT(0) }, + [RST_APB2_I2C1] = { 0x2d8, BIT(1) }, + [RST_APB2_I2C2] = { 0x2d8, BIT(2) }, + [RST_APB2_I2C3] = { 0x2d8, BIT(3) }, + [RST_APB2_UART0] = { 0x2d8, BIT(16) }, + [RST_APB2_UART1] = { 0x2d8, BIT(17) }, + [RST_APB2_UART2] = { 0x2d8, BIT(18) }, + [RST_APB2_UART3] = { 0x2d8, BIT(19) }, + [RST_APB2_UART4] = { 0x2d8, BIT(20) }, + [RST_APB2_UART5] = { 0x2d8, BIT(21) }, +}; + +static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = { + .ccu_clks = sun6i_a31_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks), + + .hw_clks = &sun6i_a31_hw_clks, + + .resets = sun6i_a31_ccu_resets, + .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets), +}; + +static struct ccu_mux_nb sun6i_a31_cpu_nb = { + .common = &cpu_clk.common, + .cm = &cpu_clk.mux, + .delay_us = 1, /* > 8 clock cycles at 24 MHz */ + .bypass_index = 1, /* index of 24 MHz oscillator */ +}; + +static void __init sun6i_a31_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUN6I_A31_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); + + /* Force PLL-MIPI to MIPI mode */ + val = readl(reg + SUN6I_A31_PLL_MIPI_REG); + val &= BIT(16); + writel(val, reg + SUN6I_A31_PLL_MIPI_REG); + + sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc); + + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, + &sun6i_a31_cpu_nb); +} +CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", + sun6i_a31_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h new file mode 100644 index 000000000000..4e434011e9e7 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN6I_A31_H_ +#define _CCU_SUN6I_A31_H_ + +#include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/reset/sun6i-a31-ccu.h> + +#define CLK_PLL_CPU 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO0 6 +#define CLK_PLL_VIDEO0_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR 9 + +/* The PLL_PERIPH clock is exported */ + +#define CLK_PLL_PERIPH_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VIDEO1_2X 13 +#define CLK_PLL_GPU 14 +#define CLK_PLL_MIPI 15 +#define CLK_PLL9 16 +#define CLK_PLL10 17 + +/* The CPUX clock is exported */ + +#define CLK_AXI 19 +#define CLK_AHB1 20 +#define CLK_APB1 21 +#define CLK_APB2 22 + +/* All the bus gates are exported */ + +/* The first bunch of module clocks are exported */ + +/* EMAC clock is not implemented */ + +#define CLK_MDFS 107 +#define CLK_SDRAM0 108 +#define CLK_SDRAM1 109 + +/* All the DRAM gates are exported */ + +/* Some more module clocks are exported */ + +#define CLK_MBUS0 141 +#define CLK_MBUS1 142 + +/* Some more module clocks and external clock outputs are exported */ + +#define CLK_NUMBER (CLK_OUT_C + 1) + +#endif /* _CCU_SUN6I_A31_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h b/drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h new file mode 100644 index 000000000000..62c0f8d49ef8 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h @@ -0,0 +1,63 @@ +/* + * Copyright 2016 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN8I_A23_A33_H_ +#define _CCU_SUN8I_A23_A33_H_ + +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO 6 +#define CLK_PLL_VIDEO_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR0 9 +#define CLK_PLL_PERIPH 10 +#define CLK_PLL_PERIPH_2X 11 +#define CLK_PLL_GPU 12 +#define CLK_PLL_MIPI 13 +#define CLK_PLL_HSIC 14 +#define CLK_PLL_DE 15 +#define CLK_PLL_DDR1 16 +#define CLK_PLL_DDR 17 + +/* The CPUX clock is exported */ + +#define CLK_AXI 19 +#define CLK_AHB1 20 +#define CLK_APB1 21 +#define CLK_APB2 22 + +/* All the bus gates are exported */ + +/* The first part of the mod clocks is exported */ + +#define CLK_DRAM 79 + +/* Some more module clocks are exported */ + +#define CLK_MBUS 95 + +/* And the last module clocks are exported */ + +#define CLK_NUMBER (CLK_ATS + 1) + +#endif /* _CCU_SUN8I_A23_A33_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c new file mode 100644 index 000000000000..11e624ab28b1 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-a23-a33.h" + + +static struct ccu_nkmp pll_cpux_clk = { + .enable = BIT(31), + .lock = BIT(28), + + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", + &ccu_nkmp_ops, + 0), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_A23_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", + "osc24M", 0x028, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", + "osc24M", 0x038, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* + * The MIPI PLL has 2 modes: "MIPI" and "HDMI". + * + * The MIPI mode is a standard NKM-style clock. The HDMI mode is an + * integer / fractional clock with switchable multipliers and dividers. + * This is not supported here. We hardcode the PLL to MIPI mode. + */ +#define SUN8I_A23_PLL_MIPI_REG 0x040 +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", + "pll-video", 0x040, + 8, 4, /* N */ + 4, 2, /* K */ + 0, 4, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", + "osc24M", 0x044, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpux" , "pll-cpux" }; +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, + 0x050, 16, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); + +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi" , "pll-periph" }; +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .variable_prediv = { + .index = 3, + .shift = 6, + .width = 2, + }, + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-periph" , "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", + 0x060, BIT(1), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", + 0x060, BIT(19), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1", + 0x060, BIT(26), 0); +static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1", + 0x060, BIT(29), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1", + 0x064, BIT(14), 0); +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", + 0x064, BIT(20), 0); +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", + 0x064, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", + 0x064, BIT(22), 0); +static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1", + 0x064, BIT(25), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", + 0x068, BIT(13), 0); + +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", + 0x06c, BIT(20), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", + 0x090, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", + 0x090, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, + 0x0b4, 16, 2, BIT(31), 0); + +/* TODO: the parent for most of the USB clocks is not known */ +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", + 0x0cc, BIT(9), 0); +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", + 0x0cc, BIT(10), 0); +static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M", + 0x0cc, BIT(11), 0); +static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M", + 0x0cc, BIT(16), 0); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr", + 0x100, BIT(16), 0); +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", + 0x100, BIT(26), 0); + +static const char * const de_parents[] = { "pll-video", "pll-periph-2x", + "pll-gpu", "pll-de" }; +static const u8 de_table[] = { 0, 2, 3, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", + de_parents, de_table, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", + de_parents, de_table, + 0x10c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x", + "pll-mipi" }; +static const u8 lcd_ch0_table[] = { 0, 2, 4 }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0", + lcd_ch0_parents, lcd_ch0_table, + 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + +static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 lcd_ch1_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1", + lcd_ch1_parents, lcd_ch1_table, + 0x12c, 0, 4, 24, 2, BIT(31), 0); + +static const char * const csi_sclk_parents[] = { "pll-video", "pll-de", + "pll-mipi", "pll-ve" }; +static const u8 csi_sclk_table[] = { 0, 3, 4, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", + csi_sclk_parents, csi_sclk_table, + 0x134, 16, 4, 24, 3, BIT(31), 0); + +static const char * const csi_mclk_parents[] = { "pll-video", "pll-de", + "osc24M" }; +static const u8 csi_mclk_table[] = { 0, 3, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", + csi_mclk_parents, csi_mclk_table, + 0x134, 0, 5, 8, 3, BIT(15), 0); + +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", + 0x140, BIT(31), 0); +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", + 0x144, BIT(31), 0); + +static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x", + "pll-ddr" }; +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + +static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 dsi_sclk_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk", + dsi_sclk_parents, dsi_sclk_table, + 0x168, 16, 4, 24, 2, BIT(31), 0); + +static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" }; +static const u8 dsi_dphy_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", + dsi_dphy_parents, dsi_dphy_table, + 0x168, 0, 4, 8, 2, BIT(15), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc", + de_parents, de_table, + 0x180, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", + 0x1a0, 0, 3, BIT(31), 0); + +static const char * const ats_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents, + 0x1b0, 0, 3, 24, 2, BIT(31), 0); + +static struct ccu_common *sun8i_a23_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr_clk.common, + &pll_periph_clk.common, + &pll_gpu_clk.common, + &pll_mipi_clk.common, + &pll_hsic_clk.common, + &pll_de_clk.common, + &cpux_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &bus_mipi_dsi_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_nand_clk.common, + &bus_dram_clk.common, + &bus_hstimer_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ehci_clk.common, + &bus_ohci_clk.common, + &bus_ve_clk.common, + &bus_lcd_clk.common, + &bus_csi_clk.common, + &bus_de_fe_clk.common, + &bus_de_be_clk.common, + &bus_gpu_clk.common, + &bus_msgbox_clk.common, + &bus_spinlock_clk.common, + &bus_drc_clk.common, + &bus_codec_clk.common, + &bus_pio_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &nand_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc2_sample_clk.common, + &mmc2_output_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &usb_phy0_clk.common, + &usb_phy1_clk.common, + &usb_hsic_clk.common, + &usb_hsic_12M_clk.common, + &usb_ohci_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_drc_clk.common, + &dram_de_fe_clk.common, + &dram_de_be_clk.common, + &de_be_clk.common, + &de_fe_clk.common, + &lcd_ch0_clk.common, + &lcd_ch1_clk.common, + &csi_sclk_clk.common, + &csi_mclk_clk.common, + &ve_clk.common, + &ac_dig_clk.common, + &avs_clk.common, + &mbus_clk.common, + &dsi_sclk_clk.common, + &dsi_dphy_clk.common, + &drc_clk.common, + &gpu_clk.common, + &ats_clk.common, +}; + +/* We hardcode the divider to 4 for now */ +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", + "pll-periph", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", + "pll-video", 1, 2, 0); + +static struct clk_hw_onecell_data sun8i_a23_hw_clks = { + .hws = { + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_CPUX] = &cpux_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw, + [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, + [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_DRC] = &bus_drc_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_I2S1] = &i2s1_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, + [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw, + [CLK_USB_OHCI] = &usb_ohci_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DRC] = &dram_drc_clk.common.hw, + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, + [CLK_DE_BE] = &de_be_clk.common.hw, + [CLK_DE_FE] = &de_fe_clk.common.hw, + [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw, + [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AC_DIG] = &ac_dig_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw, + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, + [CLK_DRC] = &drc_clk.common.hw, + [CLK_GPU] = &gpu_clk.common.hw, + [CLK_ATS] = &ats_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_a23_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, + + [RST_MBUS] = { 0x0fc, BIT(31) }, + + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, + [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, + + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_LCD] = { 0x2c4, BIT(4) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, + [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, + [RST_BUS_DRC] = { 0x2c4, BIT(25) }, + + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, + + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, + + [RST_BUS_I2C0] = { 0x2d4, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d4, BIT(1) }, + [RST_BUS_I2C2] = { 0x2d4, BIT(2) }, + [RST_BUS_UART0] = { 0x2d4, BIT(16) }, + [RST_BUS_UART1] = { 0x2d4, BIT(17) }, + [RST_BUS_UART2] = { 0x2d4, BIT(18) }, + [RST_BUS_UART3] = { 0x2d4, BIT(19) }, + [RST_BUS_UART4] = { 0x2d4, BIT(20) }, +}; + +static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = { + .ccu_clks = sun8i_a23_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks), + + .hw_clks = &sun8i_a23_hw_clks, + + .resets = sun8i_a23_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets), +}; + +static void __init sun8i_a23_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUN8I_A23_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); + + /* Force PLL-MIPI to MIPI mode */ + val = readl(reg + SUN8I_A23_PLL_MIPI_REG); + val &= ~BIT(16); + writel(val, reg + SUN8I_A23_PLL_MIPI_REG); + + sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc); +} +CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu", + sun8i_a23_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c new file mode 100644 index 000000000000..fc00892906d8 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -0,0 +1,780 @@ +/* + * Copyright (c) 2016 Maxime Ripard. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-a23-a33.h" + +static struct ccu_nkmp pll_cpux_clk = { + .enable = BIT(31), + .lock = BIT(28), + + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", + &ccu_nkmp_ops, + 0), + }, +}; + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_A33_PLL_AUDIO_REG 0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", + "osc24M", 0x018, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", + "osc24M", 0x020, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", + "osc24M", 0x028, + 8, 5, /* N */ + 4, 2, /* K */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 2, /* post-div */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", + "osc24M", 0x038, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* + * The MIPI PLL has 2 modes: "MIPI" and "HDMI". + * + * The MIPI mode is a standard NKM-style clock. The HDMI mode is an + * integer / fractional clock with switchable multipliers and dividers. + * This is not supported here. We hardcode the PLL to MIPI mode. + */ +#define SUN8I_A33_PLL_MIPI_REG 0x040 +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", + "pll-video", 0x040, + 8, 4, /* N */ + 4, 2, /* K */ + 0, 4, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", + "osc24M", 0x044, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* TODO: Fix N */ +static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 6, /* N */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpux" , "pll-cpux" }; +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, + 0x050, 16, 2, CLK_IS_CRITICAL); + +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); + +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi" , "pll-periph" }; +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .variable_prediv = { + .index = 3, + .shift = 6, + .width = 2, + }, + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-periph" , "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", + 0x060, BIT(1), 0); +static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1", + 0x060, BIT(5), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", + 0x060, BIT(19), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1", + 0x060, BIT(26), 0); +static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1", + 0x060, BIT(29), 0); + +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", + 0x064, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1", + 0x064, BIT(14), 0); +static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", + 0x064, BIT(20), 0); +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", + 0x064, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", + 0x064, BIT(22), 0); +static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1", + 0x064, BIT(25), 0); +static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1", + 0x064, BIT(26), 0); + +static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", + 0x068, BIT(13), 0); + +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", + 0x06c, BIT(20), 0); + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", + 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", + 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", + 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", + 0x08c, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", + 0x090, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", + 0x090, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, + 0x0b0, 16, 2, BIT(31), 0); + +static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, + 0x0b4, 16, 2, BIT(31), 0); + +/* TODO: the parent for most of the USB clocks is not known */ +static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", + 0x0cc, BIT(8), 0); +static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", + 0x0cc, BIT(9), 0); +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", + 0x0cc, BIT(10), 0); +static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M", + 0x0cc, BIT(11), 0); +static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M", + 0x0cc, BIT(16), 0); + +static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", + 0x0f4, 0, 4, CLK_IS_CRITICAL); + +static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents, + 0x0f8, 16, 1, 0); + +static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", + 0x100, BIT(0), 0); +static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", + 0x100, BIT(1), 0); +static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram", + 0x100, BIT(16), 0); +static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram", + 0x100, BIT(24), 0); +static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram", + 0x100, BIT(26), 0); + +static const char * const de_parents[] = { "pll-video", "pll-periph-2x", + "pll-gpu", "pll-de" }; +static const u8 de_table[] = { 0, 2, 3, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", + de_parents, de_table, + 0x104, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", + de_parents, de_table, + 0x10c, 0, 4, 24, 3, BIT(31), 0); + +static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x", + "pll-mipi" }; +static const u8 lcd_ch0_table[] = { 0, 2, 4 }; +static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0", + lcd_ch0_parents, lcd_ch0_table, + 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); + +static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 lcd_ch1_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1", + lcd_ch1_parents, lcd_ch1_table, + 0x12c, 0, 4, 24, 2, BIT(31), 0); + +static const char * const csi_sclk_parents[] = { "pll-video", "pll-de", + "pll-mipi", "pll-ve" }; +static const u8 csi_sclk_table[] = { 0, 3, 4, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", + csi_sclk_parents, csi_sclk_table, + 0x134, 16, 4, 24, 3, BIT(31), 0); + +static const char * const csi_mclk_parents[] = { "pll-video", "pll-de", + "osc24M" }; +static const u8 csi_mclk_table[] = { 0, 3, 5 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", + csi_mclk_parents, csi_mclk_table, + 0x134, 0, 5, 8, 3, BIT(15), 0); + +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", + 0x140, BIT(31), 0); +static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", + 0x140, BIT(30), 0); +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", + 0x144, BIT(31), 0); + +static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x", + "pll-ddr0", "pll-ddr1" }; +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, + 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + +static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" }; +static const u8 dsi_sclk_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk", + dsi_sclk_parents, dsi_sclk_table, + 0x168, 16, 4, 24, 2, BIT(31), 0); + +static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" }; +static const u8 dsi_dphy_table[] = { 0, 2 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", + dsi_dphy_parents, dsi_dphy_table, + 0x168, 0, 4, 8, 2, BIT(15), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc", + de_parents, de_table, + 0x180, 0, 4, 24, 3, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", + 0x1a0, 0, 3, BIT(31), 0); + +static const char * const ats_parents[] = { "osc24M", "pll-periph" }; +static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents, + 0x1b0, 0, 3, 24, 2, BIT(31), 0); + +static struct ccu_common *sun8i_a33_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph_clk.common, + &pll_gpu_clk.common, + &pll_mipi_clk.common, + &pll_hsic_clk.common, + &pll_de_clk.common, + &pll_ddr1_clk.common, + &pll_ddr_clk.common, + &cpux_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &bus_mipi_dsi_clk.common, + &bus_ss_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_nand_clk.common, + &bus_dram_clk.common, + &bus_hstimer_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_otg_clk.common, + &bus_ehci_clk.common, + &bus_ohci_clk.common, + &bus_ve_clk.common, + &bus_lcd_clk.common, + &bus_csi_clk.common, + &bus_de_fe_clk.common, + &bus_de_be_clk.common, + &bus_gpu_clk.common, + &bus_msgbox_clk.common, + &bus_spinlock_clk.common, + &bus_drc_clk.common, + &bus_sat_clk.common, + &bus_codec_clk.common, + &bus_pio_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &nand_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc2_sample_clk.common, + &mmc2_output_clk.common, + &ss_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &usb_phy0_clk.common, + &usb_phy1_clk.common, + &usb_hsic_clk.common, + &usb_hsic_12M_clk.common, + &usb_ohci_clk.common, + &dram_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_drc_clk.common, + &dram_de_fe_clk.common, + &dram_de_be_clk.common, + &de_be_clk.common, + &de_fe_clk.common, + &lcd_ch0_clk.common, + &lcd_ch1_clk.common, + &csi_sclk_clk.common, + &csi_mclk_clk.common, + &ve_clk.common, + &ac_dig_clk.common, + &ac_dig_4x_clk.common, + &avs_clk.common, + &mbus_clk.common, + &dsi_sclk_clk.common, + &dsi_dphy_clk.common, + &drc_clk.common, + &gpu_clk.common, + &ats_clk.common, +}; + +/* We hardcode the divider to 4 for now */ +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", + "pll-periph", 1, 2, 0); +static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", + "pll-video", 1, 2, 0); + +static struct clk_hw_onecell_data sun8i_a33_hw_clks = { + .hws = { + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, + [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, + [CLK_CPUX] = &cpux_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, + [CLK_BUS_SS] = &bus_ss_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw, + [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, + [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_DRC] = &bus_drc_clk.common.hw, + [CLK_BUS_SAT] = &bus_sat_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, + [CLK_SS] = &ss_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_I2S1] = &i2s1_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, + [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw, + [CLK_USB_OHCI] = &usb_ohci_clk.common.hw, + [CLK_DRAM] = &dram_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_DRC] = &dram_drc_clk.common.hw, + [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, + [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, + [CLK_DE_BE] = &de_be_clk.common.hw, + [CLK_DE_FE] = &de_fe_clk.common.hw, + [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw, + [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AC_DIG] = &ac_dig_clk.common.hw, + [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw, + [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, + [CLK_DRC] = &drc_clk.common.hw, + [CLK_GPU] = &gpu_clk.common.hw, + [CLK_ATS] = &ats_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_a33_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, + + [RST_MBUS] = { 0x0fc, BIT(31) }, + + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, + [RST_BUS_SS] = { 0x2c0, BIT(5) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, + [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, + + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_LCD] = { 0x2c4, BIT(4) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, + [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, + [RST_BUS_GPU] = { 0x2c4, BIT(20) }, + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, + [RST_BUS_DRC] = { 0x2c4, BIT(25) }, + [RST_BUS_SAT] = { 0x2c4, BIT(26) }, + + [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, + + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, + + [RST_BUS_I2C0] = { 0x2d4, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d4, BIT(1) }, + [RST_BUS_I2C2] = { 0x2d4, BIT(2) }, + [RST_BUS_UART0] = { 0x2d4, BIT(16) }, + [RST_BUS_UART1] = { 0x2d4, BIT(17) }, + [RST_BUS_UART2] = { 0x2d4, BIT(18) }, + [RST_BUS_UART3] = { 0x2d4, BIT(19) }, + [RST_BUS_UART4] = { 0x2d4, BIT(20) }, +}; + +static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = { + .ccu_clks = sun8i_a33_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks), + + .hw_clks = &sun8i_a33_hw_clks, + + .resets = sun8i_a33_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets), +}; + +static void __init sun8i_a33_ccu_setup(struct device_node *node) +{ + void __iomem *reg; + u32 val; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + /* Force the PLL-Audio-1x divider to 4 */ + val = readl(reg + SUN8I_A33_PLL_AUDIO_REG); + val &= ~GENMASK(19, 16); + writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG); + + /* Force PLL-MIPI to MIPI mode */ + val = readl(reg + SUN8I_A33_PLL_MIPI_REG); + val &= ~BIT(16); + writel(val, reg + SUN8I_A33_PLL_MIPI_REG); + + sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc); +} +CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu", + sun8i_a33_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 9af359544110..4fa9374c2959 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -184,15 +184,15 @@ static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 0); static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" }; +static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { + { .index = 1, .div = 2 }, +}; static struct ccu_mux ahb2_clk = { .mux = { .shift = 0, .width = 1, - - .fixed_prediv = { - .index = 1, - .div = 2, - }, + .fixed_predivs = ahb2_fixed_predivs, + .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), }, .common = { diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 653ade5769b3..34c338832c0d 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -19,10 +19,29 @@ #include "ccu_common.h" #include "ccu_mux.h" +/** + * struct _ccu_div - Internal divider description + * @shift: Bit offset of the divider in its register + * @width: Width of the divider field in its register + * @max: Maximum value allowed for that divider. This is the + * arithmetic value, not the maximum value to be set in the + * register. + * @flags: clk_divider flags to apply on this divider + * @table: Divider table pointer (if applicable) + * + * That structure represents a single divider, and is meant to be + * embedded in other structures representing the various clock + * classes. + * + * It is basically a wrapper around the clk_divider functions + * arguments. + */ struct _ccu_div { u8 shift; u8 width; + u32 max; + u32 flags; struct clk_div_table *table; @@ -36,14 +55,25 @@ struct _ccu_div { .table = _table, \ } -#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ - _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, _flags) - #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0) +#define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ + { \ + .shift = _shift, \ + .width = _width, \ + .flags = _flags, \ + .max = _max, \ + } + +#define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ + _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags) + +#define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \ + _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0) + #define _SUNXI_CCU_DIV(_shift, _width) \ - _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, NULL, 0) + _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0) struct ccu_div { u32 enable; @@ -77,13 +107,16 @@ struct ccu_div { _shift, _width, _table, 0, \ _flags) -#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ - _mshift, _mwidth, _muxshift, _muxwidth, \ - _gate, _flags) \ +#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ + _parents, _table, \ + _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ struct ccu_div _struct = { \ .enable = _gate, \ .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \ - .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \ .common = { \ .reg = _reg, \ .hw.init = CLK_HW_INIT_PARENTS(_name, \ @@ -93,12 +126,23 @@ struct ccu_div { }, \ } +#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, _muxshift, _muxwidth, \ + _gate, _flags) \ + SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ + _parents, NULL, \ + _reg, _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) + #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ _mshift, _mwidth, _muxshift, _muxwidth, \ _flags) \ - SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ - _mshift, _mwidth, _muxshift, _muxwidth, \ - 0, _flags) + SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ + _parents, NULL, \ + _reg, _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + 0, _flags) #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c index cbf33ef5faa9..ebb1b31568a5 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.c +++ b/drivers/clk/sunxi-ng/ccu_mp.c @@ -21,9 +21,9 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate, unsigned int best_m = 0, best_p = 0; unsigned int _m, _p; - for (_p = 0; _p <= max_p; _p++) { + for (_p = 1; _p <= max_p; _p <<= 1) { for (_m = 1; _m <= max_m; _m++) { - unsigned long tmp_rate = (parent >> _p) / _m; + unsigned long tmp_rate = parent / _p / _m; if (tmp_rate > rate) continue; @@ -46,13 +46,15 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux, void *data) { struct ccu_mp *cmp = data; + unsigned int max_m, max_p; unsigned int m, p; - ccu_mp_find_best(parent_rate, rate, - 1 << cmp->m.width, (1 << cmp->p.width) - 1, - &m, &p); + max_m = cmp->m.max ?: 1 << cmp->m.width; + max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); - return (parent_rate >> p) / m; + ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p); + + return parent_rate / p / m; } static void ccu_mp_disable(struct clk_hw *hw) @@ -108,13 +110,14 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, { struct ccu_mp *cmp = hw_to_ccu_mp(hw); unsigned long flags; + unsigned int max_m, max_p; unsigned int m, p; u32 reg; - ccu_mp_find_best(parent_rate, rate, - 1 << cmp->m.width, (1 << cmp->p.width) - 1, - &m, &p); + max_m = cmp->m.max ?: 1 << cmp->m.width; + max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); + ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p); spin_lock_irqsave(cmp->common.lock, flags); @@ -122,7 +125,7 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); - writel(reg | (p << cmp->p.shift) | ((m - 1) << cmp->m.shift), + writel(reg | (ilog2(p) << cmp->p.shift) | ((m - 1) << cmp->m.shift), cmp->common.base + cmp->common.reg); spin_unlock_irqrestore(cmp->common.lock, flags); diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h index 3cf12bf95962..edf9215ea8cc 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.h +++ b/drivers/clk/sunxi-ng/ccu_mp.h @@ -44,7 +44,7 @@ struct ccu_mp { .enable = _gate, \ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \ - .mux = SUNXI_CLK_MUX(_muxshift, _muxwidth), \ + .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ .common = { \ .reg = _reg, \ .hw.init = CLK_HW_INIT_PARENTS(_name, \ diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c new file mode 100644 index 000000000000..010e9424691d --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_mult.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/clk-provider.h> + +#include "ccu_gate.h" +#include "ccu_mult.h" + +static void ccu_mult_find_best(unsigned long parent, unsigned long rate, + unsigned int max_n, unsigned int *n) +{ + *n = rate / parent; +} + +static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux, + unsigned long parent_rate, + unsigned long rate, + void *data) +{ + struct ccu_mult *cm = data; + unsigned int n; + + ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n); + + return parent_rate * n; +} + +static void ccu_mult_disable(struct clk_hw *hw) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_gate_helper_disable(&cm->common, cm->enable); +} + +static int ccu_mult_enable(struct clk_hw *hw) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_gate_helper_enable(&cm->common, cm->enable); +} + +static int ccu_mult_is_enabled(struct clk_hw *hw) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_gate_helper_is_enabled(&cm->common, cm->enable); +} + +static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + unsigned long val; + u32 reg; + + reg = readl(cm->common.base + cm->common.reg); + val = reg >> cm->mult.shift; + val &= (1 << cm->mult.width) - 1; + + ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1, + &parent_rate); + + return parent_rate * (val + 1); +} + +static int ccu_mult_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_mux_helper_determine_rate(&cm->common, &cm->mux, + req, ccu_mult_round_rate, cm); +} + +static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + unsigned long flags; + unsigned int n; + u32 reg; + + ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1, + &parent_rate); + + ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n); + + spin_lock_irqsave(cm->common.lock, flags); + + reg = readl(cm->common.base + cm->common.reg); + reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift); + + writel(reg | ((n - 1) << cm->mult.shift), + cm->common.base + cm->common.reg); + + spin_unlock_irqrestore(cm->common.lock, flags); + + return 0; +} + +static u8 ccu_mult_get_parent(struct clk_hw *hw) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_mux_helper_get_parent(&cm->common, &cm->mux); +} + +static int ccu_mult_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_mult *cm = hw_to_ccu_mult(hw); + + return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); +} + +const struct clk_ops ccu_mult_ops = { + .disable = ccu_mult_disable, + .enable = ccu_mult_enable, + .is_enabled = ccu_mult_is_enabled, + + .get_parent = ccu_mult_get_parent, + .set_parent = ccu_mult_set_parent, + + .determine_rate = ccu_mult_determine_rate, + .recalc_rate = ccu_mult_recalc_rate, + .set_rate = ccu_mult_set_rate, +}; diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h index 609db6610880..5d2c8dc14073 100644 --- a/drivers/clk/sunxi-ng/ccu_mult.h +++ b/drivers/clk/sunxi-ng/ccu_mult.h @@ -1,6 +1,9 @@ #ifndef _CCU_MULT_H_ #define _CCU_MULT_H_ +#include "ccu_common.h" +#include "ccu_mux.h" + struct _ccu_mult { u8 shift; u8 width; @@ -12,4 +15,36 @@ struct _ccu_mult { .width = _width, \ } +struct ccu_mult { + u32 enable; + + struct _ccu_mult mult; + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ + _mshift, _mwidth, _gate, _lock, \ + _flags) \ + struct ccu_mult _struct = { \ + .enable = _gate, \ + .mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT(_name, \ + _parent, \ + &ccu_mult_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_mult *hw_to_ccu_mult(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mult, common); +} + +extern const struct clk_ops ccu_mult_ops; + #endif /* _CCU_MULT_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 58fc36e7dcce..a43ad52a957d 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -8,7 +8,9 @@ * the License, or (at your option) any later version. */ +#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/delay.h> #include "ccu_gate.h" #include "ccu_mux.h" @@ -18,8 +20,9 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common, int parent_index, unsigned long *parent_rate) { - u8 prediv = 1; + u16 prediv = 1; u32 reg; + int i; if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || (common->features & CCU_FEATURE_VARIABLE_PREDIV))) @@ -32,8 +35,9 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common, } if (common->features & CCU_FEATURE_FIXED_PREDIV) - if (parent_index == cm->fixed_prediv.index) - prediv = cm->fixed_prediv.div; + for (i = 0; i < cm->n_predivs; i++) + if (parent_index == cm->fixed_predivs[i].index) + prediv = cm->fixed_predivs[i].div; if (common->features & CCU_FEATURE_VARIABLE_PREDIV) if (parent_index == cm->variable_prediv.index) { @@ -107,6 +111,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common, parent = reg >> cm->shift; parent &= (1 << cm->width) - 1; + if (cm->table) { + int num_parents = clk_hw_get_num_parents(&common->hw); + int i; + + for (i = 0; i < num_parents; i++) + if (cm->table[i] == parent) + return i; + } + return parent; } @@ -117,6 +130,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, unsigned long flags; u32 reg; + if (cm->table) + index = cm->table[index]; + spin_lock_irqsave(common->lock, flags); reg = readl(common->base + common->reg); @@ -185,3 +201,37 @@ const struct clk_ops ccu_mux_ops = { .determine_rate = __clk_mux_determine_rate, .recalc_rate = ccu_mux_recalc_rate, }; + +/* + * This clock notifier is called when the frequency of the of the parent + * PLL clock is to be changed. The idea is to switch the parent to a + * stable clock, such as the main oscillator, while the PLL frequency + * stabilizes. + */ +static int ccu_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct ccu_mux_nb *mux = to_ccu_mux_nb(nb); + int ret = 0; + + if (event == PRE_RATE_CHANGE) { + mux->original_index = ccu_mux_helper_get_parent(mux->common, + mux->cm); + ret = ccu_mux_helper_set_parent(mux->common, mux->cm, + mux->bypass_index); + } else if (event == POST_RATE_CHANGE) { + ret = ccu_mux_helper_set_parent(mux->common, mux->cm, + mux->original_index); + } + + udelay(mux->delay_us); + + return notifier_from_errno(ret); +} + +int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb) +{ + mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb; + + return clk_notifier_register(clk, &mux_nb->clk_nb); +} diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index 945082631e7d..47aba3a48245 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -5,14 +5,18 @@ #include "ccu_common.h" +struct ccu_mux_fixed_prediv { + u8 index; + u16 div; +}; + struct ccu_mux_internal { - u8 shift; - u8 width; + u8 shift; + u8 width; + const u8 *table; - struct { - u8 index; - u8 div; - } fixed_prediv; + const struct ccu_mux_fixed_prediv *fixed_predivs; + u8 n_predivs; struct { u8 index; @@ -21,12 +25,16 @@ struct ccu_mux_internal { } variable_prediv; }; -#define SUNXI_CLK_MUX(_shift, _width) \ - { \ - .shift = _shift, \ - .width = _width, \ +#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ + { \ + .shift = _shift, \ + .width = _width, \ + .table = _table, \ } +#define _SUNXI_CCU_MUX(_shift, _width) \ + _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL) + struct ccu_mux { u16 reg; u32 enable; @@ -35,9 +43,12 @@ struct ccu_mux { struct ccu_common common; }; -#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, _flags) \ +#define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ + _reg, _shift, _width, _gate, \ + _flags) \ struct ccu_mux _struct = { \ - .mux = SUNXI_CLK_MUX(_shift, _width), \ + .enable = _gate, \ + .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \ .common = { \ .reg = _reg, \ .hw.init = CLK_HW_INIT_PARENTS(_name, \ @@ -49,17 +60,14 @@ struct ccu_mux { #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ _shift, _width, _gate, _flags) \ - struct ccu_mux _struct = { \ - .enable = _gate, \ - .mux = SUNXI_CLK_MUX(_shift, _width), \ - .common = { \ - .reg = _reg, \ - .hw.init = CLK_HW_INIT_PARENTS(_name, \ - _parents, \ - &ccu_mux_ops, \ - _flags), \ - } \ - } + SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \ + _reg, _shift, _width, _gate, \ + _flags) + +#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ + _flags) \ + SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \ + _reg, _shift, _width, 0, _flags) static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) { @@ -88,4 +96,18 @@ int ccu_mux_helper_set_parent(struct ccu_common *common, struct ccu_mux_internal *cm, u8 index); +struct ccu_mux_nb { + struct notifier_block clk_nb; + struct ccu_common *common; + struct ccu_mux_internal *cm; + + u32 delay_us; /* How many us to wait after reparenting */ + u8 bypass_index; /* Which parent to temporarily use */ + u8 original_index; /* This is set by the notifier callback */ +}; + +#define to_ccu_mux_nb(_nb) container_of(_nb, struct ccu_mux_nb, clk_nb) + +int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb); + #endif /* _CCU_MUX_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c index 2071822b1e9c..059fdc3b4f96 100644 --- a/drivers/clk/sunxi-ng/ccu_nkm.c +++ b/drivers/clk/sunxi-ng/ccu_nkm.c @@ -93,19 +93,30 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw, return parent_rate * (n + 1) * (k + 1) / (m + 1); } -static long ccu_nkm_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux, + unsigned long parent_rate, + unsigned long rate, + void *data) { - struct ccu_nkm *nkm = hw_to_ccu_nkm(hw); + struct ccu_nkm *nkm = data; struct _ccu_nkm _nkm; _nkm.max_n = 1 << nkm->n.width; _nkm.max_k = 1 << nkm->k.width; - _nkm.max_m = 1 << nkm->m.width; + _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; - ccu_nkm_find_best(*parent_rate, rate, &_nkm); + ccu_nkm_find_best(parent_rate, rate, &_nkm); - return *parent_rate * _nkm.n * _nkm.k / _nkm.m; + return parent_rate * _nkm.n * _nkm.k / _nkm.m; +} + +static int ccu_nkm_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_nkm *nkm = hw_to_ccu_nkm(hw); + + return ccu_mux_helper_determine_rate(&nkm->common, &nkm->mux, + req, ccu_nkm_round_rate, nkm); } static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate, @@ -118,7 +129,7 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate, _nkm.max_n = 1 << nkm->n.width; _nkm.max_k = 1 << nkm->k.width; - _nkm.max_m = 1 << nkm->m.width; + _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; ccu_nkm_find_best(parent_rate, rate, &_nkm); @@ -142,12 +153,29 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static u8 ccu_nkm_get_parent(struct clk_hw *hw) +{ + struct ccu_nkm *nkm = hw_to_ccu_nkm(hw); + + return ccu_mux_helper_get_parent(&nkm->common, &nkm->mux); +} + +static int ccu_nkm_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_nkm *nkm = hw_to_ccu_nkm(hw); + + return ccu_mux_helper_set_parent(&nkm->common, &nkm->mux, index); +} + const struct clk_ops ccu_nkm_ops = { .disable = ccu_nkm_disable, .enable = ccu_nkm_enable, .is_enabled = ccu_nkm_is_enabled, + .get_parent = ccu_nkm_get_parent, + .set_parent = ccu_nkm_set_parent, + + .determine_rate = ccu_nkm_determine_rate, .recalc_rate = ccu_nkm_recalc_rate, - .round_rate = ccu_nkm_round_rate, .set_rate = ccu_nkm_set_rate, }; diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h index 1936ac1c6b37..35493fddd8ab 100644 --- a/drivers/clk/sunxi-ng/ccu_nkm.h +++ b/drivers/clk/sunxi-ng/ccu_nkm.h @@ -32,10 +32,33 @@ struct ccu_nkm { struct _ccu_mult n; struct _ccu_mult k; struct _ccu_div m; + struct ccu_mux_internal mux; struct ccu_common common; }; +#define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ + _nshift, _nwidth, \ + _kshift, _kwidth, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _lock, _flags) \ + struct ccu_nkm _struct = { \ + .enable = _gate, \ + .lock = _lock, \ + .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \ + .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ + .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ + .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_nkm_ops, \ + _flags), \ + }, \ + } + #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _nshift, _nwidth, \ _kshift, _kwidth, \ diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c index 9f2b98e19dc9..9769dee99511 100644 --- a/drivers/clk/sunxi-ng/ccu_nkmp.c +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c @@ -29,14 +29,14 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate, unsigned long _n, _k, _m, _p; for (_k = 1; _k <= nkmp->max_k; _k++) { - for (_p = 0; _p <= nkmp->max_p; _p++) { + for (_p = 1; _p <= nkmp->max_p; _p <<= 1) { unsigned long tmp_rate; - rational_best_approximation(rate / _k, parent >> _p, + rational_best_approximation(rate / _k, parent / _p, nkmp->max_n, nkmp->max_m, &_n, &_m); - tmp_rate = (parent * _n * _k >> _p) / _m; + tmp_rate = parent * _n * _k / (_m * _p); if (tmp_rate > rate) continue; @@ -110,13 +110,12 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate, _nkmp.max_n = 1 << nkmp->n.width; _nkmp.max_k = 1 << nkmp->k.width; - _nkmp.max_m = 1 << nkmp->m.width; - _nkmp.max_p = (1 << nkmp->p.width) - 1; + _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width; + _nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1); - ccu_nkmp_find_best(*parent_rate, rate, - &_nkmp); + ccu_nkmp_find_best(*parent_rate, rate, &_nkmp); - return (*parent_rate * _nkmp.n * _nkmp.k >> _nkmp.p) / _nkmp.m; + return *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p); } static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, @@ -129,8 +128,8 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, _nkmp.max_n = 1 << nkmp->n.width; _nkmp.max_k = 1 << nkmp->k.width; - _nkmp.max_m = 1 << nkmp->m.width; - _nkmp.max_p = (1 << nkmp->p.width) - 1; + _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width; + _nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1); ccu_nkmp_find_best(parent_rate, rate, &_nkmp); @@ -145,7 +144,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, reg |= (_nkmp.n - 1) << nkmp->n.shift; reg |= (_nkmp.k - 1) << nkmp->k.shift; reg |= (_nkmp.m - 1) << nkmp->m.shift; - reg |= _nkmp.p << nkmp->p.shift; + reg |= ilog2(_nkmp.p) << nkmp->p.shift; writel(reg, nkmp->common.base + nkmp->common.reg); diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index e35ddd8eec8b..b61bdd8c7a7f 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -61,11 +61,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct ccu_nm *nm = hw_to_ccu_nm(hw); + unsigned long max_n, max_m; unsigned long n, m; - rational_best_approximation(rate, *parent_rate, - 1 << nm->n.width, 1 << nm->m.width, - &n, &m); + max_n = 1 << nm->n.width; + max_m = nm->m.max ?: 1 << nm->m.width; + + rational_best_approximation(rate, *parent_rate, max_n, max_m, &n, &m); return *parent_rate * n / m; } @@ -75,6 +77,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, { struct ccu_nm *nm = hw_to_ccu_nm(hw); unsigned long flags; + unsigned long max_n, max_m; unsigned long n, m; u32 reg; @@ -83,9 +86,10 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, else ccu_frac_helper_disable(&nm->common, &nm->frac); - rational_best_approximation(rate, parent_rate, - 1 << nm->n.width, 1 << nm->m.width, - &n, &m); + max_n = 1 << nm->n.width; + max_m = nm->m.max ?: 1 << nm->m.width; + + rational_best_approximation(rate, parent_rate, max_n, max_m, &n, &m); spin_lock_irqsave(nm->common.lock, flags); diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h new file mode 100644 index 000000000000..4482530fb6f5 --- /dev/null +++ b/include/dt-bindings/clock/sun6i-a31-ccu.h @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ +#define _DT_BINDINGS_CLK_SUN6I_A31_H_ + +#define CLK_PLL_PERIPH 10 + +#define CLK_CPU 18 + +#define CLK_AHB1_MIPIDSI 23 +#define CLK_AHB1_SS 24 +#define CLK_AHB1_DMA 25 +#define CLK_AHB1_MMC0 26 +#define CLK_AHB1_MMC1 27 +#define CLK_AHB1_MMC2 28 +#define CLK_AHB1_MMC3 29 +#define CLK_AHB1_NAND1 30 +#define CLK_AHB1_NAND0 31 +#define CLK_AHB1_SDRAM 32 +#define CLK_AHB1_EMAC 33 +#define CLK_AHB1_TS 34 +#define CLK_AHB1_HSTIMER 35 +#define CLK_AHB1_SPI0 36 +#define CLK_AHB1_SPI1 37 +#define CLK_AHB1_SPI2 38 +#define CLK_AHB1_SPI3 39 +#define CLK_AHB1_OTG 40 +#define CLK_AHB1_EHCI0 41 +#define CLK_AHB1_EHCI1 42 +#define CLK_AHB1_OHCI0 43 +#define CLK_AHB1_OHCI1 44 +#define CLK_AHB1_OHCI2 45 +#define CLK_AHB1_VE 46 +#define CLK_AHB1_LCD0 47 +#define CLK_AHB1_LCD1 48 +#define CLK_AHB1_CSI 49 +#define CLK_AHB1_HDMI 50 +#define CLK_AHB1_BE0 51 +#define CLK_AHB1_BE1 52 +#define CLK_AHB1_FE0 53 +#define CLK_AHB1_FE1 54 +#define CLK_AHB1_MP 55 +#define CLK_AHB1_GPU 56 +#define CLK_AHB1_DEU0 57 +#define CLK_AHB1_DEU1 58 +#define CLK_AHB1_DRC0 59 +#define CLK_AHB1_DRC1 60 + +#define CLK_APB1_CODEC 61 +#define CLK_APB1_SPDIF 62 +#define CLK_APB1_DIGITAL_MIC 63 +#define CLK_APB1_PIO 64 +#define CLK_APB1_DAUDIO0 65 +#define CLK_APB1_DAUDIO1 66 + +#define CLK_APB2_I2C0 67 +#define CLK_APB2_I2C1 68 +#define CLK_APB2_I2C2 69 +#define CLK_APB2_I2C3 70 +#define CLK_APB2_UART0 71 +#define CLK_APB2_UART1 72 +#define CLK_APB2_UART2 73 +#define CLK_APB2_UART3 74 +#define CLK_APB2_UART4 75 +#define CLK_APB2_UART5 76 + +#define CLK_NAND0 77 +#define CLK_NAND1 78 +#define CLK_MMC0 79 +#define CLK_MMC0_SAMPLE 80 +#define CLK_MMC0_OUTPUT 81 +#define CLK_MMC1 82 +#define CLK_MMC1_SAMPLE 83 +#define CLK_MMC1_OUTPUT 84 +#define CLK_MMC2 85 +#define CLK_MMC2_SAMPLE 86 +#define CLK_MMC2_OUTPUT 87 +#define CLK_MMC3 88 +#define CLK_MMC3_SAMPLE 89 +#define CLK_MMC3_OUTPUT 90 +#define CLK_TS 91 +#define CLK_SS 92 +#define CLK_SPI0 93 +#define CLK_SPI1 94 +#define CLK_SPI2 95 +#define CLK_SPI3 96 +#define CLK_DAUDIO0 97 +#define CLK_DAUDIO1 98 +#define CLK_SPDIF 99 +#define CLK_USB_PHY0 100 +#define CLK_USB_PHY1 101 +#define CLK_USB_PHY2 102 +#define CLK_USB_OHCI0 103 +#define CLK_USB_OHCI1 104 +#define CLK_USB_OHCI2 105 + +#define CLK_DRAM_VE 110 +#define CLK_DRAM_CSI_ISP 111 +#define CLK_DRAM_TS 112 +#define CLK_DRAM_DRC0 113 +#define CLK_DRAM_DRC1 114 +#define CLK_DRAM_DEU0 115 +#define CLK_DRAM_DEU1 116 +#define CLK_DRAM_FE0 117 +#define CLK_DRAM_FE1 118 +#define CLK_DRAM_BE0 119 +#define CLK_DRAM_BE1 120 +#define CLK_DRAM_MP 121 + +#define CLK_BE0 122 +#define CLK_BE1 123 +#define CLK_FE0 124 +#define CLK_FE1 125 +#define CLK_MP 126 +#define CLK_LCD0_CH0 127 +#define CLK_LCD1_CH0 128 +#define CLK_LCD0_CH1 129 +#define CLK_LCD1_CH1 130 +#define CLK_CSI0_SCLK 131 +#define CLK_CSI0_MCLK 132 +#define CLK_CSI1_MCLK 133 +#define CLK_VE 134 +#define CLK_CODEC 135 +#define CLK_AVS 136 +#define CLK_DIGITAL_MIC 137 +#define CLK_HDMI 138 +#define CLK_HDMI_DDC 139 +#define CLK_PS 140 + +#define CLK_MIPI_DSI 143 +#define CLK_MIPI_DSI_DPHY 144 +#define CLK_MIPI_CSI_DPHY 145 +#define CLK_IEP_DRC0 146 +#define CLK_IEP_DRC1 147 +#define CLK_IEP_DEU0 148 +#define CLK_IEP_DEU1 149 +#define CLK_GPU_CORE 150 +#define CLK_GPU_MEMORY 151 +#define CLK_GPU_HYD 152 +#define CLK_ATS 153 +#define CLK_TRACE 154 + +#define CLK_OUT_A 155 +#define CLK_OUT_B 156 +#define CLK_OUT_C 157 + +#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h new file mode 100644 index 000000000000..f8222b6b2cc3 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ +#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ + +#define CLK_CPUX 18 + +#define CLK_BUS_MIPI_DSI 23 +#define CLK_BUS_SS 24 +#define CLK_BUS_DMA 25 +#define CLK_BUS_MMC0 26 +#define CLK_BUS_MMC1 27 +#define CLK_BUS_MMC2 28 +#define CLK_BUS_NAND 29 +#define CLK_BUS_DRAM 30 +#define CLK_BUS_HSTIMER 31 +#define CLK_BUS_SPI0 32 +#define CLK_BUS_SPI1 33 +#define CLK_BUS_OTG 34 +#define CLK_BUS_EHCI 35 +#define CLK_BUS_OHCI 36 +#define CLK_BUS_VE 37 +#define CLK_BUS_LCD 38 +#define CLK_BUS_CSI 39 +#define CLK_BUS_DE_BE 40 +#define CLK_BUS_DE_FE 41 +#define CLK_BUS_GPU 42 +#define CLK_BUS_MSGBOX 43 +#define CLK_BUS_SPINLOCK 44 +#define CLK_BUS_DRC 45 +#define CLK_BUS_SAT 46 +#define CLK_BUS_CODEC 47 +#define CLK_BUS_PIO 48 +#define CLK_BUS_I2S0 49 +#define CLK_BUS_I2S1 50 +#define CLK_BUS_I2C0 51 +#define CLK_BUS_I2C1 52 +#define CLK_BUS_I2C2 53 +#define CLK_BUS_UART0 54 +#define CLK_BUS_UART1 55 +#define CLK_BUS_UART2 56 +#define CLK_BUS_UART3 57 +#define CLK_BUS_UART4 58 +#define CLK_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC0_SAMPLE 61 +#define CLK_MMC0_OUTPUT 62 +#define CLK_MMC1 63 +#define CLK_MMC1_SAMPLE 64 +#define CLK_MMC1_OUTPUT 65 +#define CLK_MMC2 66 +#define CLK_MMC2_SAMPLE 67 +#define CLK_MMC2_OUTPUT 68 +#define CLK_SS 69 +#define CLK_SPI0 70 +#define CLK_SPI1 71 +#define CLK_I2S0 72 +#define CLK_I2S1 73 +#define CLK_USB_PHY0 74 +#define CLK_USB_PHY1 75 +#define CLK_USB_HSIC 76 +#define CLK_USB_HSIC_12M 77 +#define CLK_USB_OHCI 78 + +#define CLK_DRAM_VE 80 +#define CLK_DRAM_CSI 81 +#define CLK_DRAM_DRC 82 +#define CLK_DRAM_DE_FE 83 +#define CLK_DRAM_DE_BE 84 +#define CLK_DE_BE 85 +#define CLK_DE_FE 86 +#define CLK_LCD_CH0 87 +#define CLK_LCD_CH1 88 +#define CLK_CSI_SCLK 89 +#define CLK_CSI_MCLK 90 +#define CLK_VE 91 +#define CLK_AC_DIG 92 +#define CLK_AC_DIG_4X 93 +#define CLK_AVS 94 + +#define CLK_DSI_SCLK 96 +#define CLK_DSI_DPHY 97 +#define CLK_DRC 98 +#define CLK_GPU 99 +#define CLK_ATS 100 + +#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h new file mode 100644 index 000000000000..fbff365ed6e1 --- /dev/null +++ b/include/dt-bindings/reset/sun6i-a31-ccu.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ +#define _DT_BINDINGS_RST_SUN6I_A31_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_PHY2 2 + +#define RST_AHB1_MIPI_DSI 3 +#define RST_AHB1_SS 4 +#define RST_AHB1_DMA 5 +#define RST_AHB1_MMC0 6 +#define RST_AHB1_MMC1 7 +#define RST_AHB1_MMC2 8 +#define RST_AHB1_MMC3 9 +#define RST_AHB1_NAND1 10 +#define RST_AHB1_NAND0 11 +#define RST_AHB1_SDRAM 12 +#define RST_AHB1_EMAC 13 +#define RST_AHB1_TS 14 +#define RST_AHB1_HSTIMER 15 +#define RST_AHB1_SPI0 16 +#define RST_AHB1_SPI1 17 +#define RST_AHB1_SPI2 18 +#define RST_AHB1_SPI3 19 +#define RST_AHB1_OTG 20 +#define RST_AHB1_EHCI0 21 +#define RST_AHB1_EHCI1 22 +#define RST_AHB1_OHCI0 23 +#define RST_AHB1_OHCI1 24 +#define RST_AHB1_OHCI2 25 +#define RST_AHB1_VE 26 +#define RST_AHB1_LCD0 27 +#define RST_AHB1_LCD1 28 +#define RST_AHB1_CSI 29 +#define RST_AHB1_HDMI 30 +#define RST_AHB1_BE0 31 +#define RST_AHB1_BE1 32 +#define RST_AHB1_FE0 33 +#define RST_AHB1_FE1 34 +#define RST_AHB1_MP 35 +#define RST_AHB1_GPU 36 +#define RST_AHB1_DEU0 37 +#define RST_AHB1_DEU1 38 +#define RST_AHB1_DRC0 39 +#define RST_AHB1_DRC1 40 +#define RST_AHB1_LVDS 41 + +#define RST_APB1_CODEC 42 +#define RST_APB1_SPDIF 43 +#define RST_APB1_DIGITAL_MIC 44 +#define RST_APB1_DAUDIO0 45 +#define RST_APB1_DAUDIO1 46 +#define RST_APB2_I2C0 47 +#define RST_APB2_I2C1 48 +#define RST_APB2_I2C2 49 +#define RST_APB2_I2C3 50 +#define RST_APB2_UART0 51 +#define RST_APB2_UART1 52 +#define RST_APB2_UART2 53 +#define RST_APB2_UART3 54 +#define RST_APB2_UART4 55 +#define RST_APB2_UART5 56 + +#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h new file mode 100644 index 000000000000..6121f2b0cd0a --- /dev/null +++ b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ +#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 +#define RST_MBUS 3 +#define RST_BUS_MIPI_DSI 4 +#define RST_BUS_SS 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MMC0 7 +#define RST_BUS_MMC1 8 +#define RST_BUS_MMC2 9 +#define RST_BUS_NAND 10 +#define RST_BUS_DRAM 11 +#define RST_BUS_HSTIMER 12 +#define RST_BUS_SPI0 13 +#define RST_BUS_SPI1 14 +#define RST_BUS_OTG 15 +#define RST_BUS_EHCI 16 +#define RST_BUS_OHCI 17 +#define RST_BUS_VE 18 +#define RST_BUS_LCD 19 +#define RST_BUS_CSI 20 +#define RST_BUS_DE_BE 21 +#define RST_BUS_DE_FE 22 +#define RST_BUS_GPU 23 +#define RST_BUS_MSGBOX 24 +#define RST_BUS_SPINLOCK 25 +#define RST_BUS_DRC 26 +#define RST_BUS_SAT 27 +#define RST_BUS_LVDS 28 +#define RST_BUS_CODEC 29 +#define RST_BUS_I2S0 30 +#define RST_BUS_I2S1 31 +#define RST_BUS_I2C0 32 +#define RST_BUS_I2C1 33 +#define RST_BUS_I2C2 34 +#define RST_BUS_UART0 35 +#define RST_BUS_UART1 36 +#define RST_BUS_UART2 37 +#define RST_BUS_UART3 38 +#define RST_BUS_UART4 39 + +#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ |