diff options
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/nand.txt | 9 | ||||
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 3 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 1 |
3 files changed, 13 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt index 3733300de8dd..b05601600083 100644 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ b/Documentation/devicetree/bindings/mtd/nand.txt @@ -35,6 +35,15 @@ Optional NAND chip properties: - nand-ecc-step-size: integer representing the number of data bytes that are covered by a single ECC step. +- nand-ecc-maximize: boolean used to specify that you want to maximize ECC + strength. The maximum ECC strength is both controller and + chip dependent. The controller side has to select the ECC + config providing the best strength and taking the OOB area + size constraint into account. + This is particularly useful when only the in-band area is + used by the upper layers, and you want to make your NAND + as reliable as possible. + The ECC strength and ECC step size properties define the correction capability of a controller. Together, they say a controller can correct "{strength} bit errors per {size} bytes". diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index f39775b05779..6669dfcf9e79 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -4272,6 +4272,9 @@ static int nand_dt_init(struct nand_chip *chip) if (ecc_step > 0) chip->ecc.size = ecc_step; + if (of_property_read_bool(dn, "nand-ecc-maximize")) + chip->ecc.options |= NAND_ECC_MAXIMIZE; + return 0; } diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index d3e3f8d03336..331caf987b16 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -141,6 +141,7 @@ enum nand_ecc_algo { * pages and you want to rely on the default implementation. */ #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) +#define NAND_ECC_MAXIMIZE BIT(1) /* Bit mask for flags passed to do_nand_read_ecc */ #define NAND_GET_DEVICE 0x80 |