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-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.txt4
-rw-r--r--Documentation/devicetree/bindings/power_supply/qcom_smbb.txt131
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt57
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts48
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts60
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi43
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi78
-rw-r--r--arch/arm/boot/dts/qcom-pm8941.dtsi24
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi1
11 files changed, 434 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 54c23f34f194..152dfaab2575 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -18,10 +18,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 29ebf84d25af..34e7614d5074 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -14,10 +14,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/power_supply/qcom_smbb.txt b/Documentation/devicetree/bindings/power_supply/qcom_smbb.txt
new file mode 100644
index 000000000000..65b88fac854b
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/qcom_smbb.txt
@@ -0,0 +1,131 @@
+Qualcomm Switch-Mode Battery Charger and Boost
+
+PROPERTIES
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Description: Must be one of:
+ - "qcom,pm8941-charger"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Description: Base address of registers for SMBB block
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Description: The format of the specifier is defined by the binding document
+ describing the node's interrupt parent. Must contain one
+ specifier for each of the following interrupts, in order:
+ - charge done
+ - charge fast mode
+ - charge trickle mode
+ - battery temperature ok
+ - battery present
+ - charger disconnected
+ - USB-in valid
+ - DC-in valid
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Description: Must contain the following list, strictly ordered:
+ "chg-done",
+ "chg-fast",
+ "chg-trkl",
+ "bat-temp-ok",
+ "bat-present",
+ "chg-gone",
+ "usb-valid",
+ "dc-valid"
+
+- qcom,fast-charge-current-limit:
+ Usage: optional (default: 1A, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 3A]
+ Description: Maximum charge current; May be clamped to safety limits.
+
+- qcom,fast-charge-low-threshold-voltage:
+ Usage: optional (default: 3.2V, or pre-configured value)
+ Value type: <u32>; uV; range [2.1V : 3.6V]
+ Description: Battery voltage limit above which fast charging may operate;
+ Below this value linear or switch-mode auto-trickle-charging
+ will operate.
+
+- qcom,fast-charge-high-threshold-voltage:
+ Usage: optional (default: 4.2V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Battery voltage limit below which fast charging may operate;
+ The fast charger will attempt to charge the battery to this
+ voltage. May be clamped to safety limits.
+
+- qcom,fast-charge-safe-voltage:
+ Usage: optional (default: 4.2V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Maximum safe battery voltage; May be pre-set by bootloader, in
+ which case, setting this will harmlessly fail. The property
+ 'fast-charge-high-watermark' will be clamped by this value.
+
+- qcom,fast-charge-safe-current:
+ Usage: optional (default: 1A, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 3A]
+ Description: Maximum safe battery charge current; May pre-set by bootloader,
+ in which case, setting this will harmlessly fail. The property
+ 'qcom,fast-charge-current-limit' will be clamped by this value.
+
+- qcom,auto-recharge-threshold-voltage:
+ Usage: optional (default: 4.1V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Battery voltage limit below which auto-recharge functionality
+ will restart charging after end-of-charge; The high cutoff
+ limit for auto-recharge is 5% above this value.
+
+- qcom,minimum-input-voltage:
+ Usage: optional (default: 4.3V, or pre-configured value)
+ Value type: <u32>; uV; range [4.2V : 9.6V]
+ Description: Input voltage level above which charging may operate
+
+- qcom,dc-current-limit:
+ Usage: optional (default: 100mA, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 2.5A]
+ Description: Default DC charge current limit
+
+- qcom,disable-dc:
+ Usage: optional (default: false)
+ Value type: boolean: <u32> or <empty>
+ Description: Disable DC charger
+
+- qcom,jeita-extended-temp-range:
+ Usage: optional (default: false)
+ Value type: boolean: <u32> or <empty>
+ Description: Enable JEITA extended temperature range; This does *not*
+ adjust the maximum charge voltage or current in the extended
+ temperature range. It only allows charging when the battery
+ is in the extended temperature range. Voltage/current
+ regulation must be done externally to fully comply with
+ the JEITA safety guidelines if this flag is set.
+
+EXAMPLE
+charger@1000 {
+ compatible = "qcom,pm8941-charger";
+ reg = <0x1000 0x700>;
+ interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "chg-done",
+ "chg-fast",
+ "chg-trkl",
+ "bat-temp-ok",
+ "bat-present",
+ "chg-gone",
+ "usb-valid",
+ "dc-valid";
+
+ qcom,fast-charge-current-limit = <1000000>;
+ qcom,dc-charge-current-limit = <1000000>;
+};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
new file mode 100644
index 000000000000..9326cdf6e1b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
@@ -0,0 +1,57 @@
+Qualcomm Shared Memory Manager binding
+
+This binding describes the Qualcomm Shared Memory Manager, used to share data
+between various subsystems and OSes in Qualcomm platforms.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be:
+ "qcom,smem"
+
+- memory-region:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: handle to memory reservation for main SMEM memory region.
+
+- qcom,rpm-msg-ram:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: handle to RPM message memory resource
+
+- hwlocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to a hwspinlock used to protect allocations from
+ the shared memory
+
+= EXAMPLE
+The following example shows the SMEM setup for MSM8974, with a main SMEM region
+at 0xfa00000 and the RPM message ram at 0xfc428000:
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem_region: smem@fa00000 {
+ reg = <0xfa00000 0x200000>;
+ no-map;
+ };
+ };
+
+ smem@fa00000 {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc {
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+ };
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index 47c0282bdfca..03784f1366e5 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -1,4 +1,6 @@
#include "qcom-apq8064-v2.0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "CompuLab CM-QS600";
@@ -12,12 +14,27 @@
stdout-path = "serial0:115200n8";
};
+ pwrseq {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ sdcc4_pwrseq: sdcc4_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_gpios>;
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
+ };
+ };
+
soc {
pinctrl@800000 {
- i2c1_pins: i2c1 {
+ card_detect: card_detect {
mux {
- pins = "gpio20", "gpio21";
- function = "gsbi1";
+ pins = "gpio26";
+ function = "gpio";
+ bias-disable;
};
};
};
@@ -96,10 +113,8 @@
i2c@12460000 {
status = "okay";
clock-frequency = <200000>;
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- eeprom: eeprom@50 {
+ eeprom@50 {
compatible = "24c02";
reg = <0x50>;
pagesize = <32>;
@@ -112,6 +127,8 @@
qcom,mode = <GSBI_PROT_I2C_UART>;
serial@16640000 {
status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi7_uart_2pins>;
};
};
@@ -163,6 +180,21 @@
regulator-always-on;
};
+ qcom,ssbi@500000 {
+ pmic@0 {
+ gpio@150 {
+ wlan_default_gpios: wlan-gpios {
+ pios {
+ pins = "gpio43";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
+ };
+ };
+ };
+ };
+ };
+
amba {
/* eMMC */
sdcc1: sdcc@12400000 {
@@ -175,12 +207,16 @@
sdcc3: sdcc@12180000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&card_detect>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
sdcc4: sdcc@121c0000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
vqmmc-supply = <&v3p3_fixed>;
+ mmc-pwrseq = <&sdcc4_pwrseq>;
};
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index f3100da082b2..11ac608b6d50 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,5 +1,6 @@
#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Qualcomm APQ8064/IFC6410";
@@ -14,6 +15,29 @@
stdout-path = "serial0:115200n8";
};
+ pwrseq {
+ compatible = "simple-bus";
+
+ sdcc4_pwrseq: sdcc4_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_gpios>;
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pm8921_gpio 43 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&notify_led>;
+
+ led@1 {
+ label = "apq8064:green:user1";
+ gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
soc {
pinctrl@800000 {
card_detect: card_detect {
@@ -119,8 +143,6 @@
qcom,mode = <GSBI_PROT_I2C>;
i2c3: i2c@16280000 {
status = "okay";
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
};
};
@@ -131,10 +153,8 @@
i2c@12460000 {
status = "okay";
clock-frequency = <200000>;
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
- eeprom: eeprom@52 {
+ eeprom@52 {
compatible = "atmel,24c128";
reg = <0x52>;
pagesize = <32>;
@@ -148,9 +168,8 @@
serial@16540000 {
status = "ok";
-
pinctrl-names = "default";
- pinctrl-0 = <&uart_pins>;
+ pinctrl-0 = <&gsbi6_uart_4pins>;
};
};
@@ -159,6 +178,8 @@
qcom,mode = <GSBI_PROT_I2C_UART>;
serial@16640000 {
status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsbi7_uart_2pins>;
};
};
@@ -210,6 +231,30 @@
status = "okay";
};
+ qcom,ssbi@500000 {
+ pmic@0 {
+ gpio@150 {
+ wlan_default_gpios: wlan-gpios {
+ pios {
+ pins = "gpio43";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
+ };
+ };
+
+ notify_led: nled {
+ pios {
+ pins = "gpio18";
+ function = "normal";
+ bias-disable;
+ power-source = <PM8921_GPIO_S4>;
+ };
+ };
+ };
+ };
+ };
+
amba {
/* eMMC */
sdcc1: sdcc@12400000 {
@@ -231,6 +276,7 @@
status = "okay";
vmmc-supply = <&ext_3p3v>;
vqmmc-supply = <&pm8921_lvs1>;
+ mmc-pwrseq = <&sdcc4_pwrseq>;
};
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d2e94d647c27..a4c1762b53ea 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -127,12 +127,33 @@
};
};
- uart_pins: uart_pins {
+ gsbi6_uart_2pins: gsbi6_uart_2pins {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "gsbi6";
+ };
+ };
+
+ gsbi6_uart_4pins: gsbi6_uart_4pins {
mux {
pins = "gpio14", "gpio15", "gpio16", "gpio17";
function = "gsbi6";
};
};
+
+ gsbi7_uart_2pins: gsbi7_uart_2pins {
+ mux {
+ pins = "gpio82", "gpio83";
+ function = "gsbi7";
+ };
+ };
+
+ gsbi7_uart_4pins: gsbi7_uart_4pins {
+ mux {
+ pins = "gpio82", "gpio83", "gpio84", "gpio85";
+ function = "gsbi7";
+ };
+ };
};
intc: interrupt-controller@2000000 {
@@ -213,6 +234,8 @@
i2c1: i2c@12460000 {
compatible = "qcom,i2c-qup-v1.1.1";
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
reg = <0x12460000 0x1000>;
interrupts = <0 194 IRQ_TYPE_NONE>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
@@ -258,6 +281,8 @@
ranges;
i2c3: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
reg = <0x16280000 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
clocks = <&gcc GSBI3_QUP_CLK>,
@@ -361,6 +386,22 @@
<136 1>, <137 1>, <138 1>, <139 1>;
};
+ rtc@11d {
+ compatible = "qcom,pm8921-rtc";
+ interrupt-parent = <&pmicintc>;
+ interrupts = <39 1>;
+ reg = <0x11d>;
+ allow-set-time;
+ };
+
+ pwrkey@1c {
+ compatible = "qcom,pm8921-pwrkey";
+ reg = <0x1c>;
+ interrupt-parent = <&pmicintc>;
+ interrupts = <50 1>, <51 1>;
+ debounce = <15625>;
+ pull-up;
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 0554fbd72c40..fcffecae3e67 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -221,6 +221,7 @@
compatible = "qcom,gcc-apq8084";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index ab8e57250468..57e6fcab4089 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -114,6 +114,11 @@
<0xf9002000 0x1000>;
};
+ apcs: syscon@f9011000 {
+ compatible = "syscon";
+ reg = <0xf9011000 0x1000>;
+ };
+
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -228,6 +233,7 @@
compatible = "qcom,gcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
@@ -240,6 +246,7 @@
compatible = "qcom,mmcc-msm8974";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0xfd8c0000 0x6000>;
};
@@ -308,7 +315,7 @@
};
blsp_i2c11: i2c@f9967000 {
- status = "disable";
+ status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9967000 0x1000>;
interrupts = <0 105 IRQ_TYPE_NONE>;
@@ -334,4 +341,73 @@
#interrupt-cells = <4>;
};
};
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <0 168 1>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8974";
+ qcom,smd-channels = "rpm_requests";
+
+ pm8841-regulators {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {};
+ pm8841_s2: s2 {};
+ pm8841_s3: s3 {};
+ pm8841_s4: s4 {};
+ pm8841_s5: s5 {};
+ pm8841_s6: s6 {};
+ pm8841_s7: s7 {};
+ pm8841_s8: s8 {};
+ };
+
+ pm8941-regulators {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ pm8941_s1: s1 {};
+ pm8941_s2: s2 {};
+ pm8941_s3: s3 {};
+ pm8941_5v: s4 {};
+
+ pm8941_l1: l1 {};
+ pm8941_l2: l2 {};
+ pm8941_l3: l3 {};
+ pm8941_l4: l4 {};
+ pm8941_l5: l5 {};
+ pm8941_l6: l6 {};
+ pm8941_l7: l7 {};
+ pm8941_l8: l8 {};
+ pm8941_l9: l9 {};
+ pm8941_l10: l10 {};
+ pm8941_l11: l11 {};
+ pm8941_l12: l12 {};
+ pm8941_l13: l13 {};
+ pm8941_l14: l14 {};
+ pm8941_l15: l15 {};
+ pm8941_l16: l16 {};
+ pm8941_l17: l17 {};
+ pm8941_l18: l18 {};
+ pm8941_l19: l19 {};
+ pm8941_l20: l20 {};
+ pm8941_l21: l21 {};
+ pm8941_l22: l22 {};
+ pm8941_l23: l23 {};
+ pm8941_l24: l24 {};
+
+ pm8941_lvs1: lvs1 {};
+ pm8941_lvs2: lvs2 {};
+ pm8941_lvs3: lvs3 {};
+
+ pm8941_5vs1: 5vs1 {};
+ pm8941_5vs2: 5vs2 {};
+ };
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 968f1043d4f5..b0d443999fcc 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -26,6 +26,27 @@
bias-pull-up;
};
+ charger@1000 {
+ compatible = "qcom,pm8941-charger";
+ reg = <0x1000 0x700>;
+ interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "chg-done",
+ "chg-fast",
+ "chg-trkl",
+ "bat-temp-ok",
+ "bat-present",
+ "chg-gone",
+ "usb-valid",
+ "dc-valid";
+ };
+
pm8941_gpios: gpios@c000 {
compatible = "qcom,pm8941-gpio";
reg = <0xc000 0x2400>;
@@ -120,8 +141,7 @@
pm8941_iadc: iadc@3600 {
compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc";
- reg = <0x3600 0x100>,
- <0x12f1 0x1>;
+ reg = <0x3600 0x100>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5911de008dd5..ac006e895e08 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -99,6 +99,7 @@
compatible = "qcom,gcc-msm8916";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
reg = <0x1800000 0x80000>;
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 23:06:10 +0100