diff options
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358767.c | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 40dea1b5e28a..45181e5cb6ca 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -418,10 +418,18 @@ static u32 tc_srcctrl(struct tc_data *tc) return reg; } -static void tc_wait_pll_lock(struct tc_data *tc) +static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) { + int ret; + + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); + if (ret) + return ret; + /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ usleep_range(3000, 6000); + + return 0; } static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) @@ -521,13 +529,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) return ret; /* Force PLL parameter update and disable bypass */ - ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLUPDATE | PLLEN); - if (ret) - return ret; - - tc_wait_pll_lock(tc); - - return 0; + return tc_pllupdate(tc, PXL_PLLCTRL); } static int tc_pxl_pll_dis(struct tc_data *tc) @@ -601,15 +603,13 @@ static int tc_aux_link_setup(struct tc_data *tc) * Initially PLLs are in bypass. Force PLL parameter update, * disable PLL bypass, enable PLL */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP0_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc); - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP1_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc); ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); if (ret == -ETIMEDOUT) { @@ -889,15 +889,13 @@ static int tc_main_link_enable(struct tc_data *tc) return ret; /* PLL setup */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP0_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc); - ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP1_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc); /* Reset/Enable Main Links */ dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; |