diff options
96 files changed, 12611 insertions, 11823 deletions
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index c71d0f0b750a..323983be3c30 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -11,9 +11,7 @@ Required properties: - hpd-gpio: following information about the hotplug gpio pin. a) phandle of the gpio controller node. b) pin number within the gpio controller. - c) pin function mode. - d) optional flags and pull up/down. - e) drive strength. + c) optional flags and pull up/down. Example: @@ -21,5 +19,5 @@ Example: compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x100000>; interrupts = <0 95 0>; - hpd-gpio = <&gpx3 7 0xf 1 3>; + hpd-gpio = <&gpx3 7 1>; }; diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 2dc1a60a867d..95d6f4b6967c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -968,6 +968,9 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) u8 csum = 0; struct edid *edid = (struct edid *)raw_edid; + if (WARN_ON(!raw_edid)) + return false; + if (edid_fixup > 8 || edid_fixup < 0) edid_fixup = 6; @@ -1010,15 +1013,15 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) break; } - return 1; + return true; bad: - if (raw_edid && print_bad_edid) { + if (print_bad_edid) { printk(KERN_ERR "Raw EDID:\n"); print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, raw_edid, EDID_LENGTH, false); } - return 0; + return false; } EXPORT_SYMBOL(drm_edid_block_valid); diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index 429e07d0b0f1..3a24385e0368 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -271,6 +271,11 @@ static int drm_open_helper(struct inode *inode, struct file *filp, priv->uid = current_euid(); priv->pid = get_pid(task_pid(current)); priv->minor = idr_find(&drm_minors_idr, minor_id); + if (!priv->minor) { + ret = -ENODEV; + goto out_put_pid; + } + priv->ioctl_count = 0; /* for compatibility root is always authenticated */ priv->authenticated = capable(CAP_SYS_ADMIN); @@ -292,7 +297,7 @@ static int drm_open_helper(struct inode *inode, struct file *filp, if (dev->driver->open) { ret = dev->driver->open(dev, priv); if (ret < 0) - goto out_free; + goto out_prime_destroy; } @@ -304,7 +309,7 @@ static int drm_open_helper(struct inode *inode, struct file *filp, if (!priv->minor->master) { mutex_unlock(&dev->struct_mutex); ret = -ENOMEM; - goto out_free; + goto out_close; } priv->is_master = 1; @@ -322,7 +327,7 @@ static int drm_open_helper(struct inode *inode, struct file *filp, drm_master_put(&priv->minor->master); drm_master_put(&priv->master); mutex_unlock(&dev->struct_mutex); - goto out_free; + goto out_close; } } mutex_lock(&dev->struct_mutex); @@ -333,7 +338,7 @@ static int drm_open_helper(struct inode *inode, struct file *filp, drm_master_put(&priv->minor->master); drm_master_put(&priv->master); mutex_unlock(&dev->struct_mutex); - goto out_free; + goto out_close; } } mutex_unlock(&dev->struct_mutex); @@ -367,7 +372,17 @@ static int drm_open_helper(struct inode *inode, struct file *filp, #endif return 0; - out_free: + +out_close: + if (dev->driver->postclose) + dev->driver->postclose(dev, priv); +out_prime_destroy: + if (drm_core_check_feature(dev, DRIVER_PRIME)) + drm_prime_destroy_file_private(&priv->prime); + if (dev->driver->driver_features & DRIVER_GEM) + drm_gem_release(dev, priv); +out_put_pid: + put_pid(priv->pid); kfree(priv); filp->private_data = NULL; return ret; diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index bcedaf7b73b9..603f256152ef 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -108,12 +108,8 @@ drm_gem_init(struct drm_device *dev) return -ENOMEM; } - if (drm_mm_init(&mm->offset_manager, DRM_FILE_PAGE_OFFSET_START, - DRM_FILE_PAGE_OFFSET_SIZE)) { - drm_ht_remove(&mm->offset_hash); - kfree(mm); - return -ENOMEM; - } + drm_mm_init(&mm->offset_manager, DRM_FILE_PAGE_OFFSET_START, + DRM_FILE_PAGE_OFFSET_SIZE); return 0; } diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c index ce063970d68c..ece72a8ac245 100644 --- a/drivers/gpu/drm/drm_gem_cma_helper.c +++ b/drivers/gpu/drm/drm_gem_cma_helper.c @@ -317,288 +317,81 @@ void drm_gem_cma_describe(struct drm_gem_cma_object *cma_obj, struct seq_file *m EXPORT_SYMBOL_GPL(drm_gem_cma_describe); #endif -/* ----------------------------------------------------------------------------- - * DMA-BUF - */ - -struct drm_gem_cma_dmabuf_attachment { - struct sg_table sgt; - enum dma_data_direction dir; -}; - -static int drm_gem_cma_dmabuf_attach(struct dma_buf *dmabuf, struct device *dev, - struct dma_buf_attachment *attach) -{ - struct drm_gem_cma_dmabuf_attachment *cma_attach; - - cma_attach = kzalloc(sizeof(*cma_attach), GFP_KERNEL); - if (!cma_attach) - return -ENOMEM; - - cma_attach->dir = DMA_NONE; - attach->priv = cma_attach; - - return 0; -} - -static void drm_gem_cma_dmabuf_detach(struct dma_buf *dmabuf, - struct dma_buf_attachment *attach) +/* low-level interface prime helpers */ +struct sg_table *drm_gem_cma_prime_get_sg_table(struct drm_gem_object *obj) { - struct drm_gem_cma_dmabuf_attachment *cma_attach = attach->priv; - struct sg_table *sgt; - - if (cma_attach == NULL) - return; - - sgt = &cma_attach->sgt; - - if (cma_attach->dir != DMA_NONE) - dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, - cma_attach->dir); - - sg_free_table(sgt); - kfree(cma_attach); - attach->priv = NULL; -} - -static struct sg_table * -drm_gem_cma_dmabuf_map(struct dma_buf_attachment *attach, - enum dma_data_direction dir) -{ - struct drm_gem_cma_dmabuf_attachment *cma_attach = attach->priv; - struct drm_gem_cma_object *cma_obj = attach->dmabuf->priv; - struct drm_device *drm = cma_obj->base.dev; - struct scatterlist *rd, *wr; + struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj); struct sg_table *sgt; - unsigned int i; - int nents, ret; - - DRM_DEBUG_PRIME("\n"); - - if (WARN_ON(dir == DMA_NONE)) - return ERR_PTR(-EINVAL); - - /* Return the cached mapping when possible. */ - if (cma_attach->dir == dir) - return &cma_attach->sgt; - - /* Two mappings with different directions for the same attachment are - * not allowed. - */ - if (WARN_ON(cma_attach->dir != DMA_NONE)) - return ERR_PTR(-EBUSY); - - sgt = &cma_attach->sgt; - - ret = sg_alloc_table(sgt, cma_obj->sgt->orig_nents, GFP_KERNEL); - if (ret) { - DRM_ERROR("failed to alloc sgt.\n"); - return ERR_PTR(-ENOMEM); - } - - mutex_lock(&drm->struct_mutex); - - rd = cma_obj->sgt->sgl; - wr = sgt->sgl; - for (i = 0; i < sgt->orig_nents; ++i) { - sg_set_page(wr, sg_page(rd), rd->length, rd->offset); - rd = sg_next(rd); - wr = sg_next(wr); - } - - nents = dma_map_sg(attach->dev, sgt->sgl, sgt->orig_nents, dir); - if (!nents) { - DRM_ERROR("failed to map sgl with iommu.\n"); - sg_free_table(sgt); - sgt = ERR_PTR(-EIO); - goto done; - } + int ret; - cma_attach->dir = dir; - attach->priv = cma_attach; + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) + return NULL; - DRM_DEBUG_PRIME("buffer size = %zu\n", cma_obj->base.size); + ret = dma_get_sgtable(obj->dev->dev, sgt, cma_obj->vaddr, + cma_obj->paddr, obj->size); + if (ret < 0) + goto out; -done: - mutex_unlock(&drm->struct_mutex); return sgt; -} -static void drm_gem_cma_dmabuf_unmap(struct dma_buf_attachment *attach, - struct sg_table *sgt, - enum dma_data_direction dir) -{ - /* Nothing to do. */ -} - -static void drm_gem_cma_dmabuf_release(struct dma_buf *dmabuf) -{ - struct drm_gem_cma_object *cma_obj = dmabuf->priv; - - DRM_DEBUG_PRIME("%s\n", __FILE__); - - /* - * drm_gem_cma_dmabuf_release() call means that file object's - * f_count is 0 and it calls drm_gem_object_handle_unreference() - * to drop the references that these values had been increased - * at drm_prime_handle_to_fd() - */ - if (cma_obj->base.export_dma_buf == dmabuf) { - cma_obj->base.export_dma_buf = NULL; - - /* - * drop this gem object refcount to release allocated buffer - * and resources. - */ - drm_gem_object_unreference_unlocked(&cma_obj->base); - } +out: + kfree(sgt); + return NULL; } +EXPORT_SYMBOL_GPL(drm_gem_cma_prime_get_sg_table); -static void *drm_gem_cma_dmabuf_kmap_atomic(struct dma_buf *dmabuf, - unsigned long page_num) +struct drm_gem_object * +drm_gem_cma_prime_import_sg_table(struct drm_device *dev, size_t size, + struct sg_table *sgt) { - /* TODO */ + struct drm_gem_cma_object *cma_obj; - return NULL; -} + if (sgt->nents != 1) + return ERR_PTR(-EINVAL); -static void drm_gem_cma_dmabuf_kunmap_atomic(struct dma_buf *dmabuf, - unsigned long page_num, void *addr) -{ - /* TODO */ -} + /* Create a CMA GEM buffer. */ + cma_obj = __drm_gem_cma_create(dev, size); + if (IS_ERR(cma_obj)) + return ERR_PTR(PTR_ERR(cma_obj)); -static void *drm_gem_cma_dmabuf_kmap(struct dma_buf *dmabuf, - unsigned long page_num) -{ - /* TODO */ + cma_obj->paddr = sg_dma_address(sgt->sgl); + cma_obj->sgt = sgt; - return NULL; -} + DRM_DEBUG_PRIME("dma_addr = 0x%x, size = %zu\n", cma_obj->paddr, size); -static void drm_gem_cma_dmabuf_kunmap(struct dma_buf *dmabuf, - unsigned long page_num, void *addr) -{ - /* TODO */ + return &cma_obj->base; } +EXPORT_SYMBOL_GPL(drm_gem_cma_prime_import_sg_table); -static int drm_gem_cma_dmabuf_mmap(struct dma_buf *dmabuf, - struct vm_area_struct *vma) +int drm_gem_cma_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) { - struct drm_gem_cma_object *cma_obj = dmabuf->priv; - struct drm_gem_object *gem_obj = &cma_obj->base; - struct drm_device *dev = gem_obj->dev; + struct drm_gem_cma_object *cma_obj; + struct drm_device *dev = obj->dev; int ret; mutex_lock(&dev->struct_mutex); - ret = drm_gem_mmap_obj(gem_obj, gem_obj->size, vma); + ret = drm_gem_mmap_obj(obj, obj->size, vma); mutex_unlock(&dev->struct_mutex); if (ret < 0) return ret; + cma_obj = to_drm_gem_cma_obj(obj); return drm_gem_cma_mmap_obj(cma_obj, vma); } +EXPORT_SYMBOL_GPL(drm_gem_cma_prime_mmap); -static void *drm_gem_cma_dmabuf_vmap(struct dma_buf *dmabuf) -{ - struct drm_gem_cma_object *cma_obj = dmabuf->priv; - - return cma_obj->vaddr; -} - -static struct dma_buf_ops drm_gem_cma_dmabuf_ops = { - .attach = drm_gem_cma_dmabuf_attach, - .detach = drm_gem_cma_dmabuf_detach, - .map_dma_buf = drm_gem_cma_dmabuf_map, - .unmap_dma_buf = drm_gem_cma_dmabuf_unmap, - .kmap = drm_gem_cma_dmabuf_kmap, - .kmap_atomic = drm_gem_cma_dmabuf_kmap_atomic, - .kunmap = drm_gem_cma_dmabuf_kunmap, - .kunmap_atomic = drm_gem_cma_dmabuf_kunmap_atomic, - .mmap = drm_gem_cma_dmabuf_mmap, - .vmap = drm_gem_cma_dmabuf_vmap, - .release = drm_gem_cma_dmabuf_release, -}; - -struct dma_buf *drm_gem_cma_dmabuf_export(struct drm_device *drm, - struct drm_gem_object *obj, int flags) +void *drm_gem_cma_prime_vmap(struct drm_gem_object *obj) { struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj); - return dma_buf_export(cma_obj, &drm_gem_cma_dmabuf_ops, - cma_obj->base.size, flags); + return cma_obj->vaddr; } -EXPORT_SYMBOL_GPL(drm_gem_cma_dmabuf_export); +EXPORT_SYMBOL_GPL(drm_gem_cma_prime_vmap); -struct drm_gem_object *drm_gem_cma_dmabuf_import(struct drm_device *drm, - struct dma_buf *dma_buf) +void drm_gem_cma_prime_vunmap(struct drm_gem_object *obj, void *vaddr) { - struct drm_gem_cma_object *cma_obj; - struct dma_buf_attachment *attach; - struct sg_table *sgt; - int ret; - - DRM_DEBUG_PRIME("%s\n", __FILE__); - - /* is this one of own objects? */ - if (dma_buf->ops == &drm_gem_cma_dmabuf_ops) { - struct drm_gem_object *obj; - - cma_obj = dma_buf->priv; - obj = &cma_obj->base; - - /* is it from our device? */ - if (obj->dev == drm) { - /* - * Importing dmabuf exported from out own gem increases - * refcount on gem itself instead of f_count of dmabuf. - */ - drm_gem_object_reference(obj); - dma_buf_put(dma_buf); - return obj; - } - } - - /* Create a CMA GEM buffer. */ - cma_obj = __drm_gem_cma_create(drm, dma_buf->size); - if (IS_ERR(cma_obj)) - return ERR_PTR(PTR_ERR(cma_obj)); - - /* Attach to the buffer and map it. Make sure the mapping is contiguous - * on the device memory bus, as that's all we support. - */ - attach = dma_buf_attach(dma_buf, drm->dev); - if (IS_ERR(attach)) { - ret = -EINVAL; - goto error_gem_free; - } - - sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); - if (IS_ERR_OR_NULL(sgt)) { - ret = sgt ? PTR_ERR(sgt) : -ENOMEM; - goto error_buf_detach; - } - - if (sgt->nents != 1) { - ret = -EINVAL; - goto error_buf_unmap; - } - - cma_obj->base.import_attach = attach; - cma_obj->paddr = sg_dma_address(sgt->sgl); - cma_obj->sgt = sgt; - - DRM_DEBUG_PRIME("dma_addr = 0x%x, size = %zu\n", cma_obj->paddr, - dma_buf->size); - - return &cma_obj->base; - -error_buf_unmap: - dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL); -error_buf_detach: - dma_buf_detach(dma_buf, attach); -error_gem_free: - drm_gem_cma_free_object(&cma_obj->base); - return ERR_PTR(ret); + /* Nothing to do */ } -EXPORT_SYMBOL_GPL(drm_gem_cma_dmabuf_import); +EXPORT_SYMBOL_GPL(drm_gem_cma_prime_vunmap); diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 07cf99cc8862..543b9b3171d3 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -669,7 +669,7 @@ int drm_mm_clean(struct drm_mm * mm) } EXPORT_SYMBOL(drm_mm_clean); -int drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size) +void drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size) { INIT_LIST_HEAD(&mm->hole_stack); INIT_LIST_HEAD(&mm->unused_nodes); @@ -690,8 +690,6 @@ int drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size) list_add_tail(&mm->head_node.hole_stack, &mm->hole_stack); mm->color_adjust = NULL; - - return 0; } EXPORT_SYMBOL(drm_mm_init); @@ -699,8 +697,8 @@ void drm_mm_takedown(struct drm_mm * mm) { struct drm_mm_node *entry, *next; - if (!list_empty(&mm->head_node.node_list)) { - DRM_ERROR("Memory manager not clean. Delaying takedown\n"); + if (WARN(!list_empty(&mm->head_node.node_list), + "Memory manager not clean. Delaying takedown\n")) { return; } @@ -716,36 +714,37 @@ void drm_mm_takedown(struct drm_mm * mm) } EXPORT_SYMBOL(drm_mm_takedown); -void drm_mm_debug_table(struct drm_mm *mm, const char *prefix) +static unsigned long drm_mm_debug_hole(struct drm_mm_node *entry, + const char *prefix) { - struct drm_mm_node *entry; - unsigned long total_used = 0, total_free = 0, total = 0; unsigned long hole_start, hole_end, hole_size; - hole_start = drm_mm_hole_node_start(&mm->head_node); - hole_end = drm_mm_hole_node_end(&mm->head_node); - hole_size = hole_end - hole_start; - if (hole_size) + if (entry->hole_follows) { + hole_start = drm_mm_hole_node_start(entry); + hole_end = drm_mm_hole_node_end(entry); + hole_size = hole_end - hole_start; printk(KERN_DEBUG "%s 0x%08lx-0x%08lx: %8lu: free\n", prefix, hole_start, hole_end, hole_size); - total_free += hole_size; + return hole_size; + } + + return 0; +} + +void drm_mm_debug_table(struct drm_mm *mm, const char *prefix) +{ + struct drm_mm_node *entry; + unsigned long total_used = 0, total_free = 0, total = 0; + + total_free += drm_mm_debug_hole(&mm->head_node, prefix); drm_mm_for_each_node(entry, mm) { printk(KERN_DEBUG "%s 0x%08lx-0x%08lx: %8lu: used\n", prefix, entry->start, entry->start + entry->size, entry->size); total_used += entry->size; - - if (entry->hole_follows) { - hole_start = drm_mm_hole_node_start(entry); - hole_end = drm_mm_hole_node_end(entry); - hole_size = hole_end - hole_start; - printk(KERN_DEBUG "%s 0x%08lx-0x%08lx: %8lu: free\n", - prefix, hole_start, hole_end, - hole_size); - total_free += hole_size; - } + total_free += drm_mm_debug_hole(entry, prefix); } total = total_free + total_used; diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 52709f2171fb..85e450e3241c 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -119,12 +119,13 @@ static void drm_gem_map_detach(struct dma_buf *dma_buf, return; sgt = prime_attach->sgt; + if (sgt) { + if (prime_attach->dir != DMA_NONE) + dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, + prime_attach->dir); + sg_free_table(sgt); + } - if (prime_attach->dir != DMA_NONE) - dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, - prime_attach->dir); - - sg_free_table(sgt); kfree(sgt); kfree(prime_attach); attach->priv = NULL; @@ -244,7 +245,13 @@ static void drm_gem_dmabuf_kunmap(struct dma_buf *dma_buf, static int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma) { - return -EINVAL; + struct drm_gem_object *obj = dma_buf->priv; + struct drm_device *dev = obj->dev; + + if (!dev->driver->gem_prime_mmap) + return -ENOSYS; + + return dev->driver->gem_prime_mmap(obj, vma); } static const struct dma_buf_ops drm_gem_prime_dmabuf_ops = { @@ -347,10 +354,13 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, out_have_obj: get_dma_buf(dmabuf); ret = dma_buf_fd(dmabuf, flags); - if (ret < 0) + if (ret < 0) { dma_buf_put(dmabuf); - else + } else { *prime_fd = ret; + ret = 0; + } + goto out; fail_rm_handle: diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 02296653a058..2290b3b73832 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -30,14 +30,14 @@ static struct device_type drm_sysfs_device_minor = { }; /** - * drm_class_suspend - DRM class suspend hook + * __drm_class_suspend - internal DRM class suspend routine * @dev: Linux device to suspend * @state: power state to enter * * Just figures out what the actual struct drm_device associated with * @dev is and calls its suspend hook, if present. */ -static int drm_class_suspend(struct device *dev, pm_message_t state) +static int __drm_class_suspend(struct device *dev, pm_message_t state) { if (dev->type == &drm_sysfs_device_minor) { struct drm_minor *drm_minor = to_drm_minor(dev); @@ -52,6 +52,26 @@ static int drm_class_suspend(struct device *dev, pm_message_t state) } /** + * drm_class_suspend - internal DRM class suspend hook. Simply calls + * __drm_class_suspend() with the correct pm state. + * @dev: Linux device to suspend + */ +static int drm_class_suspend(struct device *dev) +{ + return __drm_class_suspend(dev, PMSG_SUSPEND); +} + +/** + * drm_class_freeze - internal DRM class freeze hook. Simply calls + * __drm_class_suspend() with the correct pm state. + * @dev: Linux device to freeze + */ +static int drm_class_freeze(struct device *dev) +{ + return __drm_class_suspend(dev, PMSG_FREEZE); +} + +/** * drm_class_resume - DRM class resume hook * @dev: Linux device to resume * @@ -72,6 +92,12 @@ static int drm_class_resume(struct device *dev) return 0; } +static const struct dev_pm_ops drm_class_dev_pm_ops = { + .suspend = drm_class_suspend, + .resume = drm_class_resume, + .freeze = drm_class_freeze, +}; + static char *drm_devnode(struct device *dev, umode_t *mode) { return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev)); @@ -106,8 +132,7 @@ struct class *drm_sysfs_create(struct module *owner, char *name) goto err_out; } - class->suspend = drm_class_suspend; - class->resume = drm_class_resume; + class->pm = &drm_class_dev_pm_ops; err = class_create_file(class, &class_attr_version.attr); if (err) diff --git a/drivers/gpu/drm/drm_trace.h b/drivers/gpu/drm/drm_trace.h index 03ea964aa604..27cc95f36381 100644 --- a/drivers/gpu/drm/drm_trace.h +++ b/drivers/gpu/drm/drm_trace.h @@ -21,7 +21,7 @@ TRACE_EVENT(drm_vblank_event, __entry->crtc = crtc; __entry->seq = seq; ), - TP_printk("crtc=%d, seq=%d", __entry->crtc, __entry->seq) + TP_printk("crtc=%d, seq=%u", __entry->crtc, __entry->seq) ); TRACE_EVENT(drm_vblank_event_queued, @@ -37,7 +37,7 @@ TRACE_EVENT(drm_vblank_event_queued, __entry->crtc = crtc; __entry->seq = seq; ), - TP_printk("pid=%d, crtc=%d, seq=%d", __entry->pid, __entry->crtc, \ + TP_printk("pid=%d, crtc=%d, seq=%u", __entry->pid, __entry->crtc, \ __entry->seq) ); @@ -54,7 +54,7 @@ TRACE_EVENT(drm_vblank_event_delivered, __entry->crtc = crtc; __entry->seq = seq; ), - TP_printk("pid=%d, crtc=%d, seq=%d", __entry->pid, __entry->crtc, \ + TP_printk("pid=%d, crtc=%d, seq=%u", __entry->pid, __entry->crtc, \ __entry->seq) ); diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.c b/drivers/gpu/drm/exynos/exynos_drm_buf.c index 22865baa03b1..b8ac06d92fbf 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_buf.c +++ b/drivers/gpu/drm/exynos/exynos_drm_buf.c @@ -57,8 +57,7 @@ static int lowlevel_buffer_allocate(struct drm_device *dev, dma_addr_t start_addr; unsigned int i = 0; - buf->pages = kzalloc(sizeof(struct page) * nr_pages, - GFP_KERNEL); + buf->pages = drm_calloc_large(nr_pages, sizeof(struct page *)); if (!buf->pages) { DRM_ERROR("failed to allocate pages.\n"); return -ENOMEM; @@ -69,8 +68,8 @@ static int lowlevel_buffer_allocate(struct drm_device *dev, &buf->dma_attrs); if (!buf->kvaddr) { DRM_ERROR("failed to allocate buffer.\n"); - kfree(buf->pages); - return -ENOMEM; + ret = -ENOMEM; + goto err_free; } start_addr = buf->dma_addr; @@ -107,9 +106,9 @@ err_free_attrs: dma_free_attrs(dev->dev, buf->size, buf->pages, (dma_addr_t)buf->dma_addr, &buf->dma_attrs); buf->dma_addr = (dma_addr_t)NULL; - +err_free: if (!is_drm_iommu_supported(dev)) - kfree(buf->pages); + drm_free_large(buf->pages); return ret; } @@ -134,7 +133,7 @@ static void lowlevel_buffer_deallocate(struct drm_device *dev, if (!is_drm_iommu_supported(dev)) { dma_free_attrs(dev->dev, buf->size, buf->kvaddr, (dma_addr_t)buf->dma_addr, &buf->dma_attrs); - kfree(buf->pages); + drm_free_large(buf->pages); } else dma_free_attrs(dev->dev, buf->size, buf->pages, (dma_addr_t)buf->dma_addr, &buf->dma_attrs); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 276237348d1e..ca2729a85129 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -155,6 +155,7 @@ static int exynos_drm_unload(struct drm_device *dev) static int exynos_drm_open(struct drm_device *dev, struct drm_file *file) { struct drm_exynos_file_private *file_priv; + int ret; file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); if (!file_priv) @@ -162,7 +163,13 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file) file->driver_priv = file_priv; - return exynos_drm_subdrv_open(dev, file); + ret = exynos_drm_subdrv_open(dev, file); + if (ret) { + kfree(file_priv); + file->driver_priv = NULL; + } + + return ret; } static void exynos_drm_preclose(struct drm_device *dev, diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index af75434ee4d7..42a5a5466075 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -388,12 +388,9 @@ out: sg_free_table(g2d_userptr->sgt); kfree(g2d_userptr->sgt); - g2d_userptr->sgt = NULL; - kfree(g2d_userptr->pages); - g2d_userptr->pages = NULL; + drm_free_large(g2d_userptr->pages); kfree(g2d_userptr); - g2d_userptr = NULL; } static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, @@ -463,11 +460,11 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev, npages = (end - start) >> PAGE_SHIFT; g2d_userptr->npages = npages; - pages = kzalloc(npages * sizeof(struct page *), GFP_KERNEL); + pages = drm_calloc_large(npages, sizeof(struct page *)); if (!pages) { DRM_ERROR("failed to allocate pages.\n"); - kfree(g2d_userptr); - return ERR_PTR(-ENOMEM); + ret = -ENOMEM; + goto err_free; } vma = find_vma(current->mm, userptr); @@ -543,7 +540,6 @@ err_sg_free_table: err_free_sgt: kfree(sgt); - sgt = NULL; err_free_userptr: exynos_gem_put_pages_to_userptr(g2d_userptr->pages, @@ -554,10 +550,10 @@ err_put_vma: exynos_gem_put_vma(g2d_userptr->vma); err_free_pages: - kfree(pages); + drm_free_large(pages); + +err_free: kfree(g2d_userptr); - pages = NULL; - g2d_userptr = NULL; return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index c3f15e7646d5..24c22a8c3364 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -246,13 +246,14 @@ struct exynos_drm_gem_obj *exynos_drm_gem_create(struct drm_device *dev, exynos_gem_obj->flags = flags; ret = exynos_drm_alloc_buf(dev, buf, flags); - if (ret < 0) { - drm_gem_object_release(&exynos_gem_obj->base); - goto err_fini_buf; - } + if (ret < 0) + goto err_gem_fini; return exynos_gem_obj; +err_gem_fini: + drm_gem_object_release(&exynos_gem_obj->base); + kfree(exynos_gem_obj); err_fini_buf: exynos_drm_fini_buf(dev, buf); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 784bbce0741a..41cc74d83e4e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -413,9 +413,6 @@ static int vidi_power_on(struct vidi_context *ctx, bool enable) struct exynos_drm_subdrv *subdrv = &ctx->subdrv; struct device *dev = subdrv->dev; - if (enable != false && enable != true) - return -EINVAL; - if (enable) { ctx->suspended = false; diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index b1280b43931c..42ffb71c63bc 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -379,7 +379,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) unsigned long flags; struct hdmi_win_data *win_data; unsigned int x_ratio, y_ratio; - unsigned int buf_num; + unsigned int buf_num = 1; dma_addr_t luma_addr[2], chroma_addr[2]; bool tiled_mode = false; bool crcb_mode = false; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index d4e78b64ca87..47d6c748057e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -647,41 +647,44 @@ static const char *purgeable_flag(int purgeable) return purgeable ? " purgeable" : ""; } -static void i915_error_vprintf(struct drm_i915_error_state_buf *e, - const char *f, va_list args) +static bool __i915_error_ok(struct drm_i915_error_state_buf *e) { - unsigned len; if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { e->err = -ENOSPC; - return; + return false; } if (e->bytes == e->size - 1 || e->err) - return; + return false; - /* Seek the first printf which is hits start position */ - if (e->pos < e->start) { - len = vsnprintf(NULL, 0, f, args); - if (e->pos + len <= e->start) { - e->pos += len; - return; - } + return true; +} - /* First vsnprintf needs to fit in full for memmove*/ - if (len >= e->size) { - e->err = -EIO; - return; - } +static bool __i915_error_seek(struct drm_i915_error_state_buf *e, + unsigned len) +{ + if (e->pos + len <= e->start) { + e->pos += len; + return false; } - len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); - if (len >= e->size - e->bytes) - len = e->size - e->bytes - 1; + /* First vsnprintf needs to fit in its entirety for memmove */ + if (len >= e->size) { + e->err = -EIO; + return false; + } + return true; +} + +static void __i915_error_advance(struct drm_i915_error_state_buf *e, + unsigned len) +{ /* If this is first printf in this window, adjust it so that * start position matches start of the buffer */ + if (e->pos < e->start) { const size_t off = e->start - e->pos; @@ -701,6 +704,51 @@ static void i915_error_vprintf(struct drm_i915_error_state_buf *e, e->pos += len; } +static void i915_error_vprintf(struct drm_i915_error_state_buf *e, + const char *f, va_list args) +{ + unsigned len; + + if (!__i915_error_ok(e)) + return; + + /* Seek the first printf which is hits start position */ + if (e->pos < e->start) { + len = vsnprintf(NULL, 0, f, args); + if (!__i915_error_seek(e, len)) + return; + } + + len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); + if (len >= e->size - e->bytes) + len = e->size - e->bytes - 1; + + __i915_error_advance(e, len); +} + +static void i915_error_puts(struct drm_i915_error_state_buf *e, + const char *str) +{ + unsigned len; + + if (!__i915_error_ok(e)) + return; + + len = strlen(str); + + /* Seek the first printf which is hits start position */ + if (e->pos < e->start) { + if (!__i915_error_seek(e, len)) + return; + } + + if (len >= e->size - e->bytes) + len = e->size - e->bytes - 1; + memcpy(e->buf + e->bytes, str, len); + + __i915_error_advance(e, len); +} + void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) { va_list args; @@ -711,6 +759,7 @@ void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) } #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) +#define err_puts(e, s) i915_error_puts(e, s) static void print_error_buffers(struct drm_i915_error_state_buf *m, const char *name, @@ -720,26 +769,26 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m, err_printf(m, "%s [%d]:\n", name, count); while (count--) { - err_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s", + err_printf(m, " %08x %8u %02x %02x %x %x", err->gtt_offset, err->size, err->read_domains, err->write_domain, - err->rseqno, err->wseqno, - pin_flag(err->pinned), - tiling_flag(err->tiling), - dirty_flag(err->dirty), - purgeable_flag(err->purgeable), - err->ring != -1 ? " " : "", - ring_str(err->ring), - cache_level_str(err->cache_level)); + err->rseqno, err->wseqno); + err_puts(m, pin_flag(err->pinned)); + err_puts(m, tiling_flag(err->tiling)); + err_puts(m, dirty_flag(err->dirty)); + err_puts(m, purgeable_flag(err->purgeable)); + err_puts(m, err->ring != -1 ? " " : ""); + err_puts(m, ring_str(err->ring)); + err_puts(m, cache_level_str(err->cache_level)); if (err->name) err_printf(m, " (name: %d)", err->name); if (err->fence_reg != I915_FENCE_REG_NONE) err_printf(m, " (fence: %d)", err->fence_reg); - err_printf(m, "\n"); + err_puts(m, "\n"); err++; } } @@ -1483,7 +1532,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (!IS_ULT(dev)) { + if (!HAS_IPS(dev)) { seq_puts(m, "not supported\n"); return 0; } @@ -1862,10 +1911,10 @@ static int i915_dpio_info(struct seq_file *m, void *data) seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); - seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n", - vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_A)); - seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n", - vlv_dpio_read(dev_priv, _DPIO_LFP_COEFF_B)); + seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", + vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); + seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", + vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index deaa32e8113b..062cbda1bf4a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -465,9 +465,15 @@ void intel_detect_pch(struct drm_device *dev) * make graphics device passthrough work easy for VMM, that only * need to expose ISA bridge to let driver know the real hardware * underneath. This is a requirement from virtualization team. + * + * In some virtualized environments (e.g. XEN), there is irrelevant + * ISA bridge in the system. To work reliably, we should scan trhough + * all the ISA bridge devices and check for the first match, instead + * of only checking the first one. */ pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); - if (pch) { + while (pch) { + struct pci_dev *curr = pch; if (pch->vendor == PCI_VENDOR_ID_INTEL) { unsigned short id; id = pch->device & INTEL_PCH_DEVICE_ID_MASK; @@ -496,10 +502,18 @@ void intel_detect_pch(struct drm_device *dev) DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); WARN_ON(!IS_HASWELL(dev)); WARN_ON(!IS_ULT(dev)); + } else { + goto check_next; } + pci_dev_put(pch); + break; } - pci_dev_put(pch); +check_next: + pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr); + pci_dev_put(curr); } + if (!pch) + DRM_DEBUG_KMS("No PCH found?\n"); } bool i915_semaphore_is_enabled(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9e1bf6dcbb2a..cc1d6056ab70 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1474,6 +1474,8 @@ struct drm_i915_file_private { #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) +#define HAS_IPS(dev) (IS_ULT(dev)) + #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a6178baccb56..769f75262feb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1087,6 +1087,25 @@ i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) interruptible, NULL); } +static int +i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, + struct intel_ring_buffer *ring) +{ + i915_gem_retire_requests_ring(ring); + + /* Manually manage the write flush as we may have not yet + * retired the buffer. + * + * Note that the last_write_seqno is always the earlier of + * the two (read/write) seqno, so if we haved successfully waited, + * we know we have passed the last write. + */ + obj->last_write_seqno = 0; + obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; + + return 0; +} + /** * Ensures that all rendering to the object has completed and the object is * safe to unbind from the GTT or access from the CPU. @@ -1107,18 +1126,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, if (ret) return ret; - i915_gem_retire_requests_ring(ring); - - /* Manually manage the write flush as we may have not yet - * retired the buffer. - */ - if (obj->last_write_seqno && - i915_seqno_passed(seqno, obj->last_write_seqno)) { - obj->last_write_seqno = 0; - obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; - } - - return 0; + return i915_gem_object_wait_rendering__tail(obj, ring); } /* A nonblocking variant of the above wait. This is a highly dangerous routine @@ -1154,19 +1162,10 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, mutex_unlock(&dev->struct_mutex); ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); mutex_lock(&dev->struct_mutex); + if (ret) + return ret; - i915_gem_retire_requests_ring(ring); - - /* Manually manage the write flush as we may have not yet - * retired the buffer. - */ - if (obj->last_write_seqno && - i915_seqno_passed(seqno, obj->last_write_seqno)) { - obj->last_write_seqno = 0; - obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; - } - - return ret; + return i915_gem_object_wait_rendering__tail(obj, ring); } /** @@ -1802,7 +1801,14 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; gfp &= ~(__GFP_IO | __GFP_WAIT); } - +#ifdef CONFIG_SWIOTLB + if (swiotlb_nr_tbl()) { + st->nents++; + sg_set_page(sg, page, PAGE_SIZE, 0); + sg = sg_next(sg); + continue; + } +#endif if (!i || page_to_pfn(page) != last_pfn + 1) { if (i) sg = sg_next(sg); @@ -1813,8 +1819,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) } last_pfn = page_to_pfn(page); } - - sg_mark_end(sg); +#ifdef CONFIG_SWIOTLB + if (!swiotlb_nr_tbl()) +#endif + sg_mark_end(sg); obj->pages = st; if (i915_gem_object_needs_bit17_swizzle(obj)) @@ -3103,7 +3111,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, * before evicting everything in a vain attempt to find space. */ if (obj->base.size > gtt_max) { - DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%ld\n", + DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", obj->base.size, map_and_fenceable ? "mappable" : "total", gtt_max); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index ff471454968d..51b7a2171cae 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -113,7 +113,7 @@ static int get_context_size(struct drm_device *dev) case 7: reg = I915_READ(GEN7_CXT_SIZE); if (IS_HASWELL(dev)) - ret = HSW_CXT_TOTAL_SIZE(reg) * 64; + ret = HSW_CXT_TOTAL_SIZE; else ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; break; diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index f713294618fe..982d4732cecf 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -147,7 +147,7 @@ int i915_gem_stolen_setup_compression(struct drm_device *dev, int size) { struct drm_i915_private *dev_priv = dev->dev_private; - if (dev_priv->mm.stolen_base == 0) + if (!drm_mm_initialized(&dev_priv->mm.stolen)) return -ENODEV; if (size < dev_priv->cfb_size) @@ -179,6 +179,9 @@ void i915_gem_cleanup_stolen(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + if (!drm_mm_initialized(&dev_priv->mm.stolen)) + return; + i915_gem_stolen_cleanup_compression(dev); drm_mm_takedown(&dev_priv->mm.stolen); } @@ -300,7 +303,7 @@ i915_gem_object_create_stolen(struct drm_device *dev, u32 size) struct drm_i915_gem_object *obj; struct drm_mm_node *stolen; - if (dev_priv->mm.stolen_base == 0) + if (!drm_mm_initialized(&dev_priv->mm.stolen)) return NULL; DRM_DEBUG_KMS("creating stolen object: size=%x\n", size); @@ -331,7 +334,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, struct drm_i915_gem_object *obj; struct drm_mm_node *stolen; - if (dev_priv->mm.stolen_base == 0) + if (!drm_mm_initialized(&dev_priv->mm.stolen)) return NULL; DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n", diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7857430943ec..3d92a7cef154 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -70,15 +70,6 @@ static const u32 hpd_status_gen4[] = { [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; -static const u32 hpd_status_i965[] = { - [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, - [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965, - [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965, - [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, - [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, - [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS -}; - static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, @@ -88,13 +79,12 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; -static void ibx_hpd_irq_setup(struct drm_device *dev); -static void i915_hpd_irq_setup(struct drm_device *dev); - /* For display hotplug interrupt */ static void ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) { + assert_spin_locked(&dev_priv->irq_lock); + if ((dev_priv->irq_mask & mask) != 0) { dev_priv->irq_mask &= ~mask; I915_WRITE(DEIMR, dev_priv->irq_mask); @@ -105,6 +95,8 @@ ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) static void ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) { + assert_spin_locked(&dev_priv->irq_lock); + if ((dev_priv->irq_mask & mask) != mask) { dev_priv->irq_mask |= mask; I915_WRITE(DEIMR, dev_priv->irq_mask); @@ -118,6 +110,8 @@ static bool ivb_can_enable_err_int(struct drm_device *dev) struct intel_crtc *crtc; enum pipe pipe; + assert_spin_locked(&dev_priv->irq_lock); + for_each_pipe(pipe) { crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); @@ -708,16 +702,24 @@ static void gen6_pm_rps_work(struct work_struct *work) mutex_lock(&dev_priv->rps.hw_lock); - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) + if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { new_delay = dev_priv->rps.cur_delay + 1; - else + + /* + * For better performance, jump directly + * to RPe if we're below it. + */ + if (IS_VALLEYVIEW(dev_priv->dev) && + dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay) + new_delay = dev_priv->rps.rpe_delay; + } else new_delay = dev_priv->rps.cur_delay - 1; /* sysfs frequency interfaces may have snuck in while servicing the * interrupt */ - if (!(new_delay > dev_priv->rps.max_delay || - new_delay < dev_priv->rps.min_delay)) { + if (new_delay >= dev_priv->rps.min_delay && + new_delay <= dev_priv->rps.max_delay) { if (IS_VALLEYVIEW(dev_priv->dev)) valleyview_set_rps(dev_priv->dev, new_delay); else @@ -870,17 +872,18 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, #define HPD_STORM_DETECT_PERIOD 1000 #define HPD_STORM_THRESHOLD 5 -static inline bool hotplug_irq_storm_detect(struct drm_device *dev, - u32 hotplug_trigger, - const u32 *hpd) +static inline void intel_hpd_irq_handler(struct drm_device *dev, + u32 hotplug_trigger, + const u32 *hpd) { drm_i915_private_t *dev_priv = dev->dev_private; - unsigned long irqflags; int i; - bool ret = false; + bool storm_detected = false; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + if (!hotplug_trigger) + return; + spin_lock(&dev_priv->irq_lock); for (i = 1; i < HPD_NUM_PINS; i++) { if (!(hpd[i] & hotplug_trigger) || @@ -897,15 +900,18 @@ static inline bool hotplug_irq_storm_detect(struct drm_device *dev, dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; dev_priv->hpd_event_bits &= ~(1 << i); DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); - ret = true; + storm_detected = true; } else { dev_priv->hpd_stats[i].hpd_cnt++; } } - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + if (storm_detected) + dev_priv->display.hpd_irq_setup(dev); + spin_unlock(&dev_priv->irq_lock); - return ret; + queue_work(dev_priv->wq, + &dev_priv->hotplug_work); } static void gmbus_irq_handler(struct drm_device *dev) @@ -1012,12 +1018,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", hotplug_status); - if (hotplug_trigger) { - if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915)) - i915_hpd_irq_setup(dev); - queue_work(dev_priv->wq, - &dev_priv->hotplug_work); - } + + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_READ(PORT_HOTPLUG_STAT); } @@ -1043,11 +1046,8 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) int pipe; u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; - if (hotplug_trigger) { - if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx)) - ibx_hpd_irq_setup(dev); - queue_work(dev_priv->wq, &dev_priv->hotplug_work); - } + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); + if (pch_iir & SDE_AUDIO_POWER_MASK) { int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> SDE_AUDIO_POWER_SHIFT); @@ -1148,11 +1148,8 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) int pipe; u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; - if (hotplug_trigger) { - if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt)) - ibx_hpd_irq_setup(dev); - queue_work(dev_priv->wq, &dev_priv->hotplug_work); - } + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); + if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> SDE_AUDIO_POWER_SHIFT_CPT); @@ -1218,8 +1215,11 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg) /* On Haswell, also mask ERR_INT because we don't want to risk * generating "unclaimed register" interrupts from inside the interrupt * handler. */ - if (IS_HASWELL(dev)) + if (IS_HASWELL(dev)) { + spin_lock(&dev_priv->irq_lock); ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); + spin_unlock(&dev_priv->irq_lock); + } gt_iir = I915_READ(GTIIR); if (gt_iir) { @@ -1272,8 +1272,12 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg) ret = IRQ_HANDLED; } - if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev)) - ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); + if (IS_HASWELL(dev)) { + spin_lock(&dev_priv->irq_lock); + if (ivb_can_enable_err_int(dev)) + ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); + spin_unlock(&dev_priv->irq_lock); + } I915_WRITE(DEIER, de_ier); POSTING_READ(DEIER); @@ -2698,6 +2702,8 @@ static void ibx_irq_postinstall(struct drm_device *dev) static int ironlake_irq_postinstall(struct drm_device *dev) { + unsigned long irqflags; + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; /* enable kind of interrupts always enabled */ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | @@ -2711,7 +2717,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) /* should always can generate irq */ I915_WRITE(DEIIR, I915_READ(DEIIR)); I915_WRITE(DEIMR, dev_priv->irq_mask); - I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); + I915_WRITE(DEIER, display_mask | + DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT); POSTING_READ(DEIER); dev_priv->gt_irq_mask = ~0; @@ -2733,10 +2740,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev) ibx_irq_postinstall(dev); if (IS_IRONLAKE_M(dev)) { - /* Clear & enable PCU event interrupts */ - I915_WRITE(DEIIR, DE_PCU_EVENT); - I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); + /* Enable PCU event interrupts + * + * spinlocking not required here for correctness since interrupt + * setup is guaranteed to run in single-threaded context. But we + * need it to make the assert_spin_locked happy. */ + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } return 0; @@ -3212,12 +3223,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", hotplug_status); - if (hotplug_trigger) { - if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915)) - i915_hpd_irq_setup(dev); - queue_work(dev_priv->wq, - &dev_priv->hotplug_work); - } + + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); POSTING_READ(PORT_HOTPLUG_STAT); } @@ -3369,6 +3377,8 @@ static void i915_hpd_irq_setup(struct drm_device *dev) struct intel_encoder *intel_encoder; u32 hotplug_en; + assert_spin_locked(&dev_priv->irq_lock); + if (I915_HAS_HOTPLUG(dev)) { hotplug_en = I915_READ(PORT_HOTPLUG_EN); hotplug_en &= ~HOTPLUG_INT_EN_MASK; @@ -3449,17 +3459,14 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? HOTPLUG_INT_STATUS_G4X : - HOTPLUG_INT_STATUS_I965); + HOTPLUG_INT_STATUS_I915); DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", hotplug_status); - if (hotplug_trigger) { - if (hotplug_irq_storm_detect(dev, hotplug_trigger, - IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965)) - i915_hpd_irq_setup(dev); - queue_work(dev_priv->wq, - &dev_priv->hotplug_work); - } + + intel_hpd_irq_handler(dev, hotplug_trigger, + IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); I915_READ(PORT_HOTPLUG_STAT); } @@ -3655,6 +3662,7 @@ void intel_hpd_init(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; + unsigned long irqflags; int i; for (i = 1; i < HPD_NUM_PINS; i++) { @@ -3667,6 +3675,11 @@ void intel_hpd_init(struct drm_device *dev) if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) connector->polled = DRM_CONNECTOR_POLL_HPD; } + + /* Interrupt setup is already guaranteed to be single-threaded, this is + * just to make the assert_spin_locked checks happy. */ + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); if (dev_priv->display.hpd_irq_setup) dev_priv->display.hpd_irq_setup(dev); + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2102ff32ee20..f2326fc60ac9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -448,9 +448,9 @@ #define _DPIO_PLL_CML_B 0x806c #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) -#define _DPIO_LFP_COEFF_A 0x8048 -#define _DPIO_LFP_COEFF_B 0x8068 -#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) +#define _DPIO_LPF_COEFF_A 0x8048 +#define _DPIO_LPF_COEFF_B 0x8068 +#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B) #define DPIO_CALIBRATION 0x80ac @@ -1718,14 +1718,13 @@ GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ GEN7_CXT_GT1_SIZE(ctx_reg) + \ GEN7_CXT_VFSTATE_SIZE(ctx_reg)) -#define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f) -#define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7) -#define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff) -#define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \ - HSW_CXT_RING_SIZE(ctx_reg) + \ - HSW_CXT_RENDER_SIZE(ctx_reg) + \ - GEN7_CXT_VFSTATE_SIZE(ctx_reg)) - +/* Haswell does have the CXT_SIZE register however it does not appear to be + * valid. Now, docs explain in dwords what is in the context object. The full + * size is 70720 bytes, however, the power context and execlist context will + * never be saved (power context is stored elsewhere, and execlists don't work + * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. + */ +#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) /* * Overlay regs @@ -1874,6 +1873,12 @@ /* SDVO is different across gen3/4 */ #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) +/* + * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, + * since reality corrobates that they're the same as on gen3. But keep these + * bits here (and the comment!) to help any other lost wanderers back onto the + * right tracks. + */ #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) @@ -1885,13 +1890,6 @@ PORTC_HOTPLUG_INT_STATUS | \ PORTD_HOTPLUG_INT_STATUS) -#define HOTPLUG_INT_STATUS_I965 (CRT_HOTPLUG_INT_STATUS | \ - SDVOB_HOTPLUG_INT_STATUS_I965 | \ - SDVOC_HOTPLUG_INT_STATUS_I965 | \ - PORTB_HOTPLUG_INT_STATUS | \ - PORTC_HOTPLUG_INT_STATUS | \ - PORTD_HOTPLUG_INT_STATUS) - #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ SDVOB_HOTPLUG_INT_STATUS_I915 | \ SDVOC_HOTPLUG_INT_STATUS_I915 | \ @@ -3488,7 +3486,7 @@ #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) -#define _SPACNTR 0x72180 +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) #define SP_ENABLE (1<<31) #define SP_GEAMMA_ENABLE (1<<30) #define SP_PIXFORMAT_MASK (0xf<<26) @@ -3507,30 +3505,30 @@ #define SP_YUV_ORDER_YVYU (2<<16) #define SP_YUV_ORDER_VYUY (3<<16) #define SP_TILED (1<<10) -#define _SPALINOFF 0x72184 -#define _SPASTRIDE 0x72188 -#define _SPAPOS 0x7218c -#define _SPASIZE 0x72190 -#define _SPAKEYMINVAL 0x72194 -#define _SPAKEYMSK 0x72198 -#define _SPASURF 0x7219c -#define _SPAKEYMAXVAL 0x721a0 -#define _SPATILEOFF 0x721a4 -#define _SPACONSTALPHA 0x721a8 -#define _SPAGAMC 0x721f4 - -#define _SPBCNTR 0x72280 -#define _SPBLINOFF 0x72284 -#define _SPBSTRIDE 0x72288 -#define _SPBPOS 0x7228c -#define _SPBSIZE 0x72290 -#define _SPBKEYMINVAL 0x72294 -#define _SPBKEYMSK 0x72298 -#define _SPBSURF 0x7229c -#define _SPBKEYMAXVAL 0x722a0 -#define _SPBTILEOFF 0x722a4 -#define _SPBCONSTALPHA 0x722a8 -#define _SPBGAMC 0x722f4 +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) +#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) +#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) +#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) +#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) + +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 224ce25129ce..324211ac9c55 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1356,7 +1356,12 @@ void intel_ddi_init(struct drm_device *dev, enum port port) intel_encoder->cloneable = false; intel_encoder->hot_plug = intel_ddi_hot_plug; - intel_dp_init_connector(intel_dig_port, dp_connector); + if (!intel_dp_init_connector(intel_dig_port, dp_connector)) { + drm_encoder_cleanup(encoder); + kfree(intel_dig_port); + kfree(dp_connector); + return; + } if (intel_encoder->type != INTEL_OUTPUT_EDP) { hdmi_connector = kzalloc(sizeof(struct intel_connector), diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b08d1f9ce0de..85f3eb74d2b7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3250,7 +3250,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) /* IPS only exists on ULT machines and is tied to pipe A. */ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) { - return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A; + return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; } static void hsw_enable_ips(struct intel_crtc *crtc) @@ -4069,7 +4069,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, pipe_config->pipe_bpp = 8*3; } - if (IS_HASWELL(dev)) + if (HAS_IPS(dev)) hsw_compute_ips_config(crtc, pipe_config); /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old @@ -4404,11 +4404,12 @@ static void vlv_update_pll(struct intel_crtc *crtc) /* Set HBR and RBR LPF coefficients */ if (crtc->config.port_clock == 162000 || + intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), 0x005f0021); else - vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), + vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe), 0x00d0000f); if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || @@ -8753,8 +8754,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set) } if (ret) { - DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", - set->crtc->base.id, ret); + DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", + set->crtc->base.id, ret); fail: intel_set_config_restore_state(dev, config); @@ -9121,6 +9122,7 @@ int intel_framebuffer_init(struct drm_device *dev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_i915_gem_object *obj) { + int pitch_limit; int ret; if (obj->tiling_mode == I915_TILING_Y) { @@ -9134,10 +9136,26 @@ int intel_framebuffer_init(struct drm_device *dev, return -EINVAL; } - /* FIXME <= Gen4 stride limits are bit unclear */ - if (mode_cmd->pitches[0] > 32768) { - DRM_DEBUG("pitch (%d) must be at less than 32768\n", - mode_cmd->pitches[0]); + if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { + pitch_limit = 32*1024; + } else if (INTEL_INFO(dev)->gen >= 4) { + if (obj->tiling_mode) + pitch_limit = 16*1024; + else + pitch_limit = 32*1024; + } else if (INTEL_INFO(dev)->gen >= 3) { + if (obj->tiling_mode) + pitch_limit = 8*1024; + else + pitch_limit = 16*1024; + } else + /* XXX DSPC is limited to 4k tiled */ + pitch_limit = 8*1024; + + if (mode_cmd->pitches[0] > pitch_limit) { + DRM_DEBUG("%s pitch (%d) must be at less than %d\n", + obj->tiling_mode ? "tiled" : "linear", + mode_cmd->pitches[0], pitch_limit); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 98686005dcf6..b73971234013 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1324,20 +1324,35 @@ static void intel_dp_get_config(struct intel_encoder *encoder, struct intel_crtc_config *pipe_config) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; u32 tmp, flags = 0; + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum port port = dp_to_dig_port(intel_dp)->port; + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - tmp = I915_READ(intel_dp->output_reg); + if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { + tmp = I915_READ(intel_dp->output_reg); + if (tmp & DP_SYNC_HS_HIGH) + flags |= DRM_MODE_FLAG_PHSYNC; + else + flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & DP_SYNC_HS_HIGH) - flags |= DRM_MODE_FLAG_PHSYNC; - else - flags |= DRM_MODE_FLAG_NHSYNC; + if (tmp & DP_SYNC_VS_HIGH) + flags |= DRM_MODE_FLAG_PVSYNC; + else + flags |= DRM_MODE_FLAG_NVSYNC; + } else { + tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) + flags |= DRM_MODE_FLAG_PHSYNC; + else + flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & DP_SYNC_VS_HIGH) - flags |= DRM_MODE_FLAG_PVSYNC; - else - flags |= DRM_MODE_FLAG_NVSYNC; + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) + flags |= DRM_MODE_FLAG_PVSYNC; + else + flags |= DRM_MODE_FLAG_NVSYNC; + } pipe_config->adjusted_mode.flags |= flags; } @@ -2681,15 +2696,16 @@ done: } static void -intel_dp_destroy(struct drm_connector *connector) +intel_dp_connector_destroy(struct drm_connector *connector) { - struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_connector *intel_connector = to_intel_connector(connector); if (!IS_ERR_OR_NULL(intel_connector->edid)) kfree(intel_connector->edid); - if (is_edp(intel_dp)) + /* Can't call is_edp() since the encoder may have been destroyed + * already. */ + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) intel_panel_fini(&intel_connector->panel); drm_sysfs_connector_remove(connector); @@ -2723,7 +2739,7 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = { .detect = intel_dp_detect, .fill_modes = drm_helper_probe_single_connector_modes, .set_property = intel_dp_set_property, - .destroy = intel_dp_destroy, + .destroy = intel_dp_connector_destroy, }; static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { @@ -2954,7 +2970,85 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, I915_READ(pp_div_reg)); } -void +static bool intel_edp_init_connector(struct intel_dp *intel_dp, + struct intel_connector *intel_connector) +{ + struct drm_connector *connector = &intel_connector->base; + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_display_mode *fixed_mode = NULL; + struct edp_power_seq power_seq = { 0 }; + bool has_dpcd; + struct drm_display_mode *scan; + struct edid *edid; + + if (!is_edp(intel_dp)) + return true; + + intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); + + /* Cache DPCD and EDID for edp. */ + ironlake_edp_panel_vdd_on(intel_dp); + has_dpcd = intel_dp_get_dpcd(intel_dp); + ironlake_edp_panel_vdd_off(intel_dp, false); + + if (has_dpcd) { + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) + dev_priv->no_aux_handshake = + intel_dp->dpcd[DP_MAX_DOWNSPREAD] & + DP_NO_AUX_HANDSHAKE_LINK_TRAINING; + } else { + /* if this fails, presume the device is a ghost */ + DRM_INFO("failed to retrieve link info, disabling eDP\n"); + return false; + } + + /* We now know it's not a ghost, init power sequence regs. */ + intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, + &power_seq); + + ironlake_edp_panel_vdd_on(intel_dp); + edid = drm_get_edid(connector, &intel_dp->adapter); + if (edid) { + if (drm_add_edid_modes(connector, edid)) { + drm_mode_connector_update_edid_property(connector, + edid); + drm_edid_to_eld(connector, edid); + } else { + kfree(edid); + edid = ERR_PTR(-EINVAL); + } + } else { + edid = ERR_PTR(-ENOENT); + } + intel_connector->edid = edid; + + /* prefer fixed mode from EDID if available */ + list_for_each_entry(scan, &connector->probed_modes, head) { + if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { + fixed_mode = drm_mode_duplicate(dev, scan); + break; + } + } + + /* fallback to VBT if available for eDP */ + if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { + fixed_mode = drm_mode_duplicate(dev, + dev_priv->vbt.lfp_lvds_vbt_mode); + if (fixed_mode) + fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; + } + + ironlake_edp_panel_vdd_off(intel_dp, false); + + intel_panel_init(&intel_connector->panel, fixed_mode); + intel_panel_setup_backlight(connector); + + return true; +} + +bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector) { @@ -2963,11 +3057,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_encoder *intel_encoder = &intel_dig_port->base; struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_display_mode *fixed_mode = NULL; - struct edp_power_seq power_seq = { 0 }; enum port port = intel_dig_port->port; const char *name = NULL; - int type; + int type, error; /* Preserve the current hw state. */ intel_dp->DP = I915_READ(intel_dp->output_reg); @@ -3065,74 +3157,21 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, BUG(); } - if (is_edp(intel_dp)) - intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); - - intel_dp_i2c_init(intel_dp, intel_connector, name); - - /* Cache DPCD and EDID for edp. */ - if (is_edp(intel_dp)) { - bool ret; - struct drm_display_mode *scan; - struct edid *edid; - - ironlake_edp_panel_vdd_on(intel_dp); - ret = intel_dp_get_dpcd(intel_dp); - ironlake_edp_panel_vdd_off(intel_dp, false); - - if (ret) { - if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) - dev_priv->no_aux_handshake = - intel_dp->dpcd[DP_MAX_DOWNSPREAD] & - DP_NO_AUX_HANDSHAKE_LINK_TRAINING; - } else { - /* if this fails, presume the device is a ghost */ - DRM_INFO("failed to retrieve link info, disabling eDP\n"); - intel_dp_encoder_destroy(&intel_encoder->base); - intel_dp_destroy(connector); - return; - } - - /* We now know it's not a ghost, init power sequence regs. */ - intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, - &power_seq); + error = intel_dp_i2c_init(intel_dp, intel_connector, name); + WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", + error, port_name(port)); - ironlake_edp_panel_vdd_on(intel_dp); - edid = drm_get_edid(connector, &intel_dp->adapter); - if (edid) { - if (drm_add_edid_modes(connector, edid)) { - drm_mode_connector_update_edid_property(connector, edid); - drm_edid_to_eld(connector, edid); - } else { - kfree(edid); - edid = ERR_PTR(-EINVAL); - } - } else { - edid = ERR_PTR(-ENOENT); + if (!intel_edp_init_connector(intel_dp, intel_connector)) { + i2c_del_adapter(&intel_dp->adapter); + if (is_edp(intel_dp)) { + cancel_delayed_work_sync(&intel_dp->panel_vdd_work); + mutex_lock(&dev->mode_config.mutex); + ironlake_panel_vdd_off_sync(intel_dp); + mutex_unlock(&dev->mode_config.mutex); } - intel_connector->edid = edid; - - /* prefer fixed mode from EDID if available */ - list_for_each_entry(scan, &connector->probed_modes, head) { - if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { - fixed_mode = drm_mode_duplicate(dev, scan); - break; - } - } - - /* fallback to VBT if available for eDP */ - if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { - fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); - if (fixed_mode) - fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; - } - - ironlake_edp_panel_vdd_off(intel_dp, false); - } - - if (is_edp(intel_dp)) { - intel_panel_init(&intel_connector->panel, fixed_mode); - intel_panel_setup_backlight(connector); + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + return false; } intel_dp_add_properties(intel_dp, connector); @@ -3145,6 +3184,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, u32 temp = I915_READ(PEG_BAND_GAP_DATA); I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); } + + return true; } void @@ -3190,5 +3231,9 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) intel_encoder->cloneable = false; intel_encoder->hot_plug = intel_dp_hot_plug; - intel_dp_init_connector(intel_dig_port, intel_connector); + if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { + drm_encoder_cleanup(encoder); + kfree(intel_dig_port); + kfree(intel_connector); + } } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ffe9d35b37b4..c8c9b6f48230 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -141,7 +141,8 @@ struct intel_encoder { bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); /* Reconstructs the equivalent mode flags for the current hardware * state. This must be called _after_ display->get_pipe_config has - * pre-filled the pipe config. */ + * pre-filled the pipe config. Note that intel_encoder->base.crtc must + * be set correctly before calling this function. */ void (*get_config)(struct intel_encoder *, struct intel_crtc_config *pipe_config); int crtc_mask; @@ -586,7 +587,7 @@ extern void intel_lvds_init(struct drm_device *dev); extern bool intel_is_dual_link_lvds(struct drm_device *dev); extern void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); -extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, +extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector); extern void intel_dp_init_link_config(struct intel_dp *intel_dp); extern void intel_dp_start_link_train(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index bc12518a21b4..98df2a0c85bd 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder, u32 hdmi_val; hdmi_val = SDVO_ENCODING_HDMI; - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) + if (!HAS_PCH_SPLIT(dev)) hdmi_val |= intel_hdmi->color_range; if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 79be7cfd3152..cfb8fb68f09c 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -311,8 +311,8 @@ static void intel_didl_outputs(struct drm_device *dev) list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) { if (i >= 8) { - dev_printk(KERN_ERR, &dev->pdev->dev, - "More than 8 outputs detected via ACPI\n"); + dev_dbg(&dev->pdev->dev, + "More than 8 outputs detected via ACPI\n"); return; } status = @@ -338,8 +338,8 @@ blind_set: list_for_each_entry(connector, &dev->mode_config.connector_list, head) { int output_type = ACPI_OTHER_OUTPUT; if (i >= 8) { - dev_printk(KERN_ERR, &dev->pdev->dev, - "More than 8 outputs in connector list\n"); + dev_dbg(&dev->pdev->dev, + "More than 8 outputs in connector list\n"); return; } switch (connector->connector_type) { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b27bda07f4ae..ccbdd83f5220 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3069,26 +3069,17 @@ void gen6_set_rps(struct drm_device *dev, u8 val) trace_intel_gpu_freq_change(val * 50); } -void valleyview_set_rps(struct drm_device *dev, u8 val) +/* + * Wait until the previous freq change has completed, + * or the timeout elapsed, and then update our notion + * of the current GPU frequency. + */ +static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = dev->dev_private; unsigned long timeout = jiffies + msecs_to_jiffies(10); - u32 limits = gen6_rps_limits(dev_priv, &val); u32 pval; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); - WARN_ON(val > dev_priv->rps.max_delay); - WARN_ON(val < dev_priv->rps.min_delay); - - DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n", - vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.cur_delay), - vlv_gpu_freq(dev_priv->mem_freq, val)); - - if (val == dev_priv->rps.cur_delay) - return; - - vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); do { pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); @@ -3099,17 +3090,41 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) udelay(10); } while (pval & 1); - pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); - if ((pval >> 8) != val) - DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n", - val, pval >> 8); + pval >>= 8; - /* Make sure we continue to get interrupts - * until we hit the minimum or maximum frequencies. - */ - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); + if (pval != dev_priv->rps.cur_delay) + DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay), + dev_priv->rps.cur_delay, + vlv_gpu_freq(dev_priv->mem_freq, pval), pval); + + dev_priv->rps.cur_delay = pval; +} + +void valleyview_set_rps(struct drm_device *dev, u8 val) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + gen6_rps_limits(dev_priv, &val); - dev_priv->rps.cur_delay = pval >> 8; + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + WARN_ON(val > dev_priv->rps.max_delay); + WARN_ON(val < dev_priv->rps.min_delay); + + vlv_update_rps_cur_delay(dev_priv); + + DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.cur_delay), + dev_priv->rps.cur_delay, + vlv_gpu_freq(dev_priv->mem_freq, val), val); + + if (val == dev_priv->rps.cur_delay) + return; + + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); + + dev_priv->rps.cur_delay = val; trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); } @@ -3446,7 +3461,8 @@ static void vlv_rps_timer_work(struct work_struct *work) * min freq available. */ mutex_lock(&dev_priv->rps.hw_lock); - valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); + if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) + valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); mutex_unlock(&dev_priv->rps.hw_lock); } @@ -3496,7 +3512,7 @@ static void valleyview_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *ring; - u32 gtfifodbg, val, rpe; + u32 gtfifodbg, val; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -3557,31 +3573,39 @@ static void valleyview_enable_rps(struct drm_device *dev) DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); - DRM_DEBUG_DRIVER("current GPU freq: %d\n", - vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff)); dev_priv->rps.cur_delay = (val >> 8) & 0xff; + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.cur_delay), + dev_priv->rps.cur_delay); dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); dev_priv->rps.hw_max = dev_priv->rps.max_delay; - DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq, - dev_priv->rps.max_delay)); + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.max_delay), + dev_priv->rps.max_delay); - rpe = valleyview_rps_rpe_freq(dev_priv); - DRM_DEBUG_DRIVER("RPe GPU freq: %d\n", - vlv_gpu_freq(dev_priv->mem_freq, rpe)); - dev_priv->rps.rpe_delay = rpe; + dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.rpe_delay), + dev_priv->rps.rpe_delay); - val = valleyview_rps_min_freq(dev_priv); - DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq, - val)); - dev_priv->rps.min_delay = val; + dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.min_delay), + dev_priv->rps.min_delay); - DRM_DEBUG_DRIVER("setting GPU freq to %d\n", - vlv_gpu_freq(dev_priv->mem_freq, rpe)); + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", + vlv_gpu_freq(dev_priv->mem_freq, + dev_priv->rps.rpe_delay), + dev_priv->rps.rpe_delay); INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); - valleyview_set_rps(dev_priv->dev, rpe); + valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); /* requires MSI enabled */ I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS); @@ -4834,10 +4858,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - /* WaForceL3Serialization:vlv */ - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); - /* This is required by WaCatErrorRejectionIssue:vlv */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index b59cfd79bd79..d939a1da3203 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile @@ -200,7 +200,13 @@ nouveau-y += core/engine/fifo/nve0.o nouveau-y += core/engine/graph/ctxnv40.o nouveau-y += core/engine/graph/ctxnv50.o nouveau-y += core/engine/graph/ctxnvc0.o -nouveau-y += core/engine/graph/ctxnve0.o +nouveau-y += core/engine/graph/ctxnvc1.o +nouveau-y += core/engine/graph/ctxnvc3.o +nouveau-y += core/engine/graph/ctxnvc8.o +nouveau-y += core/engine/graph/ctxnvd7.o +nouveau-y += core/engine/graph/ctxnvd9.o +nouveau-y += core/engine/graph/ctxnve4.o +nouveau-y += core/engine/graph/ctxnvf0.o nouveau-y += core/engine/graph/nv04.o nouveau-y += core/engine/graph/nv10.o nouveau-y += core/engine/graph/nv20.o @@ -212,7 +218,13 @@ nouveau-y += core/engine/graph/nv35.o nouveau-y += core/engine/graph/nv40.o nouveau-y += core/engine/graph/nv50.o nouveau-y += core/engine/graph/nvc0.o -nouveau-y += core/engine/graph/nve0.o +nouveau-y += core/engine/graph/nvc1.o +nouveau-y += core/engine/graph/nvc3.o +nouveau-y += core/engine/graph/nvc8.o +nouveau-y += core/engine/graph/nvd7.o +nouveau-y += core/engine/graph/nvd9.o +nouveau-y += core/engine/graph/nve4.o +nouveau-y += core/engine/graph/nvf0.o nouveau-y += core/engine/mpeg/nv31.o nouveau-y += core/engine/mpeg/nv40.o nouveau-y += core/engine/mpeg/nv50.o diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c index 1df3578a5315..418f51f50d7a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c @@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -133,7 +133,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -161,7 +161,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -190,7 +190,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; @@ -291,7 +291,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; + device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; @@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c index 4e6ef62e88c8..7aca1877add4 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c @@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; @@ -105,7 +105,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; @@ -135,7 +135,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; + device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; @@ -163,16 +163,14 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; -#if 0 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; -#endif + device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; -#if 0 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +#if 0 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c index f065fc248adf..db8c6fd46278 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c @@ -55,6 +55,10 @@ nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) nv_wr32(priv, 0x61c510 + soff, 0x00000000); nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); + nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + /* ??? */ nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c index 8b42f45c2b1d..7ffe2f309f12 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c @@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 hval, hreg = 0x614200 + (head * 0x800); u32 oval, oreg; + u32 mask; u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp); if (conf != ~0) { if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { @@ -1133,6 +1134,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800; oval = 0x00000000; hval = 0x00000000; + mask = 0xffffffff; } else if (!outp.location) { if (outp.type == DCB_OUTPUT_DP) @@ -1140,14 +1142,16 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800; oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; hval = 0x00000000; + mask = 0x00000707; } else { oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800; oval = 0x00000001; hval = 0x00000001; + mask = 0x00000707; } nv_mask(priv, hreg, 0x0000000f, hval); - nv_mask(priv, oreg, 0x00000707, oval); + nv_mask(priv, oreg, mask, oval); } } diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 0338e66bc620..09644fa9602c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c @@ -221,8 +221,10 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, } } - if (i == FIFO_ENGINE_NR) + if (i == FIFO_ENGINE_NR) { + nv_error(priv, "unsupported engines 0x%08x\n", args->engine); return -ENODEV; + } ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, priv->user.bar.offset, 0x200, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index 3be7b950eece..64dca260912f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -24,3456 +24,1220 @@ #include "nvc0.h" -void -nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data) -{ - nv_wr32(priv, 0x400204, data); - nv_wr32(priv, 0x400200, icmd); - while (nv_rd32(priv, 0x400700) & 2) {} -} +struct nvc0_graph_init +nvc0_grctx_init_icmd[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 1, 0x01, 0x00000001 }, + { 0x000639, 1, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_9097[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x002700, 8, 0x20, 0x00000000 }, + { 0x002704, 8, 0x20, 0x00000000 }, + { 0x002708, 8, 0x20, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 8, 0x20, 0x00014000 }, + { 0x002714, 8, 0x20, 0x00000040 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002200, 5, 0x10, 0x00000022 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00001fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x003fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 1, 0x04, 0x00000000 }, + { 0x001320, 3, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 1, 0x04, 0x003fffff }, + { 0x0002d0, 1, 0x04, 0x00000c48 }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00300008 }, + { 0x001284, 1, 0x04, 0x04000080 }, + { 0x001450, 1, 0x04, 0x00300008 }, + { 0x001454, 1, 0x04, 0x04000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_902d[] = { + { 0x000200, 1, 0x04, 0x000000cf }, + { 0x000204, 1, 0x04, 0x00000001 }, + { 0x000208, 1, 0x04, 0x00000020 }, + { 0x00020c, 1, 0x04, 0x00000001 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000080 }, + { 0x000218, 2, 0x04, 0x00000100 }, + { 0x000220, 2, 0x04, 0x00000000 }, + { 0x000230, 1, 0x04, 0x000000cf }, + { 0x000234, 1, 0x04, 0x00000001 }, + { 0x000238, 1, 0x04, 0x00000020 }, + { 0x00023c, 1, 0x04, 0x00000001 }, + { 0x000244, 1, 0x04, 0x00000080 }, + { 0x000248, 2, 0x04, 0x00000100 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_9039[] = { + { 0x00030c, 3, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000238, 2, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_90c0[] = { + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x000758, 1, 0x04, 0x00000100 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x000204, 3, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000000 }, + { 0x00024c, 1, 0x04, 0x00000000 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_base[] = { + { 0x400204, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk40xx[] = { + { 0x404004, 10, 0x04, 0x00000000 }, + { 0x404044, 1, 0x04, 0x00000000 }, + { 0x404094, 1, 0x04, 0x00000000 }, + { 0x404098, 12, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf0000087 }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 1, 0x04, 0x00000000 }, + { 0x404134, 1, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x404168, 1, 0x04, 0x00000000 }, + { 0x404174, 1, 0x04, 0x00000000 }, + { 0x404178, 2, 0x04, 0x00000000 }, + { 0x404200, 8, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk44xx[] = { + { 0x404404, 14, 0x04, 0x00000000 }, + { 0x404460, 2, 0x04, 0x00000000 }, + { 0x404468, 1, 0x04, 0x00ffffff }, + { 0x40446c, 1, 0x04, 0x00000000 }, + { 0x404480, 1, 0x04, 0x00000001 }, + { 0x404498, 1, 0x04, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk46xx[] = { + { 0x404604, 1, 0x04, 0x00000015 }, + { 0x404608, 1, 0x04, 0x00000000 }, + { 0x40460c, 1, 0x04, 0x00002e00 }, + { 0x404610, 1, 0x04, 0x00000100 }, + { 0x404618, 8, 0x04, 0x00000000 }, + { 0x404638, 1, 0x04, 0x00000004 }, + { 0x40463c, 8, 0x04, 0x00000000 }, + { 0x40465c, 1, 0x04, 0x007f0100 }, + { 0x404660, 7, 0x04, 0x00000000 }, + { 0x40467c, 1, 0x04, 0x00000002 }, + { 0x404680, 8, 0x04, 0x00000000 }, + { 0x4046a0, 1, 0x04, 0x007f0080 }, + { 0x4046a4, 18, 0x04, 0x00000000 }, + { 0x4046f0, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk47xx[] = { + { 0x404700, 13, 0x04, 0x00000000 }, + { 0x404734, 1, 0x04, 0x00000100 }, + { 0x404738, 8, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk58xx[] = { + { 0x405800, 1, 0x04, 0x078000bf }, + { 0x405830, 1, 0x04, 0x02180000 }, + { 0x405834, 2, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk60xx[] = { + { 0x406020, 1, 0x04, 0x000103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk64xx[] = { + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk78xx[] = { + { 0x407804, 1, 0x04, 0x00000023 }, + { 0x40780c, 1, 0x04, 0x0a418820 }, + { 0x407810, 1, 0x04, 0x062080e6 }, + { 0x407814, 1, 0x04, 0x020398a4 }, + { 0x407818, 1, 0x04, 0x0e629062 }, + { 0x40781c, 1, 0x04, 0x0a418820 }, + { 0x407820, 1, 0x04, 0x000000e6 }, + { 0x4078bc, 1, 0x04, 0x00000103 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_unk80xx[] = { + { 0x408000, 2, 0x04, 0x00000000 }, + { 0x408008, 1, 0x04, 0x00000018 }, + { 0x40800c, 2, 0x04, 0x00000000 }, + { 0x408014, 1, 0x04, 0x00000069 }, + { 0x408018, 1, 0x04, 0xe100e100 }, + { 0x408064, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_rop[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x0003e00d }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x02000001 }, + { 0x408908, 1, 0x04, 0x00c80929 }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x00200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 1, 0x04, 0x00000000 }, + { 0x41870c, 1, 0x04, 0x07c80000 }, + { 0x418710, 1, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x0006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x00000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x00100000 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000000 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_gpc_1[] = { + { 0x418a00, 3, 0x04, 0x00000000 }, + { 0x418a0c, 1, 0x04, 0x00010000 }, + { 0x418a10, 3, 0x04, 0x00000000 }, + { 0x418a20, 3, 0x04, 0x00000000 }, + { 0x418a2c, 1, 0x04, 0x00010000 }, + { 0x418a30, 3, 0x04, 0x00000000 }, + { 0x418a40, 3, 0x04, 0x00000000 }, + { 0x418a4c, 1, 0x04, 0x00010000 }, + { 0x418a50, 3, 0x04, 0x00000000 }, + { 0x418a60, 3, 0x04, 0x00000000 }, + { 0x418a6c, 1, 0x04, 0x00010000 }, + { 0x418a70, 3, 0x04, 0x00000000 }, + { 0x418a80, 3, 0x04, 0x00000000 }, + { 0x418a8c, 1, 0x04, 0x00010000 }, + { 0x418a90, 3, 0x04, 0x00000000 }, + { 0x418aa0, 3, 0x04, 0x00000000 }, + { 0x418aac, 1, 0x04, 0x00010000 }, + { 0x418ab0, 3, 0x04, 0x00000000 }, + { 0x418ac0, 3, 0x04, 0x00000000 }, + { 0x418acc, 1, 0x04, 0x00010000 }, + { 0x418ad0, 3, 0x04, 0x00000000 }, + { 0x418ae0, 3, 0x04, 0x00000000 }, + { 0x418aec, 1, 0x04, 0x00010000 }, + { 0x418af0, 3, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_tpc[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x0000012a }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00000001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + { 0x419c00, 1, 0x04, 0x00000002 }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x00060048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419d20, 1, 0x04, 0x02180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419f50, 2, 0x04, 0x00000000 }, + {} +}; -int -nvc0_grctx_init(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +void +nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) { - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_gpuobj *chan; - u32 size = (0x80000 + priv->size + 4095) & ~4095; - int ret, i; - - /* allocate memory to for a "channel", which we'll use to generate - * the default context values - */ - ret = nouveau_gpuobj_new(nv_object(priv), NULL, size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &info->chan); - chan = info->chan; - if (ret) { - nv_error(priv, "failed to allocate channel memory, %d\n", ret); - return ret; - } - - /* PGD pointer */ - nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0208, 0xffffffff); - nv_wo32(chan, 0x020c, 0x000000ff); - - /* PGT[0] pointer */ - nv_wo32(chan, 0x1000, 0x00000000); - nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); - - /* identity-map the whole "channel" into its own vm */ - for (i = 0; i < size / 4096; i++) { - u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; - nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); - nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); - } - - /* context pointer (virt) */ - nv_wo32(chan, 0x0210, 0x00080004); - nv_wo32(chan, 0x0214, 0x00000000); - - bar->flush(bar); + int gpc, tpc; + u32 offset; - nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); - nv_wr32(priv, 0x100cbc, 0x80000001); - nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); - - /* setup default state for mmio list construction */ - info->data = priv->mmio_data; - info->mmio = priv->mmio_list; - info->addr = 0x2000 + (i * 8); - info->priv = priv; - info->buffer_nr = 0; + mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); - if (priv->firmware) { - nv_wr32(priv, 0x409840, 0x00000030); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000003); - if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) - nv_error(priv, "load_ctx timeout\n"); + mmio_list(0x408004, 0x00000000, 8, 0); + mmio_list(0x408008, 0x80000018, 0, 0); + mmio_list(0x40800c, 0x00000000, 8, 1); + mmio_list(0x408010, 0x80000000, 0, 0); + mmio_list(0x418810, 0x80000000, 12, 2); + mmio_list(0x419848, 0x10000000, 12, 2); + mmio_list(0x419004, 0x00000000, 8, 1); + mmio_list(0x419008, 0x00000000, 0, 0); + mmio_list(0x418808, 0x00000000, 8, 0); + mmio_list(0x41880c, 0x80000018, 0, 0); - nv_wo32(chan, 0x8001c, 1); - nv_wo32(chan, 0x80020, 0); - nv_wo32(chan, 0x80028, 0); - nv_wo32(chan, 0x8002c, 0); - bar->flush(bar); - return 0; - } + mmio_list(0x405830, 0x02180000, 0, 0); - /* HUB_FUC(SET_CHAN) */ - nv_wr32(priv, 0x409840, 0x80000000); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000001); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { - nv_error(priv, "HUB_SET_CHAN timeout\n"); - nvc0_graph_ctxctl_debug(priv); - nouveau_gpuobj_ref(NULL, &info->chan); - return -EBUSY; + for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + u32 addr = TPC_UNIT(gpc, tpc, 0x0520); + mmio_list(addr, 0x02180000 | offset, 0, 0); + offset += 0x0324; + } } - - return 0; } void -nvc0_grctx_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) +nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) { - info->buffer[info->buffer_nr] = info->addr; - info->buffer[info->buffer_nr] += (align - 1); - info->buffer[info->buffer_nr] &= ~(align - 1); - info->addr = info->buffer[info->buffer_nr++] + size; - - info->data->size = size; - info->data->align = align; - info->data->access = access; - info->data++; } void -nvc0_grctx_mmio(struct nvc0_grctx *info, u32 addr, u32 data, u32 shift, u32 buf) +nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) { - struct nvc0_graph_priv *priv = info->priv; - - info->mmio->addr = addr; - info->mmio->data = data; - info->mmio->shift = shift; - info->mmio->buffer = buf; - info->mmio++; + int gpc, tpc, id; - if (shift) - data |= info->buffer[buf] >> shift; - nv_wr32(priv, addr, data); -} - -int -nvc0_grctx_fini(struct nvc0_grctx *info) -{ - struct nvc0_graph_priv *priv = info->priv; - int i; - - /* trigger a context unload by unsetting the "next channel valid" bit - * and faking a context switch interrupt - */ - nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); - nv_wr32(priv, 0x409000, 0x00000100); - if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { - nv_error(priv, "grctx template channel unload timeout\n"); - return -EBUSY; - } - - priv->data = kmalloc(priv->size, GFP_KERNEL); - if (priv->data) { - for (i = 0; i < priv->size; i += 4) - priv->data[i / 4] = nv_ro32(info->chan, 0x80000 + i); - } - - nouveau_gpuobj_ref(NULL, &info->chan); - return priv->data ? 0 : -ENOMEM; -} + for (tpc = 0, id = 0; tpc < 4; tpc++) { + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + if (tpc < priv->tpc_nr[gpc]) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + id++; + } -static void -nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) -{ - u32 fermi = nvc0_graph_class(priv); - u32 mthd; - - nv_mthd(priv, 0x9097, 0x0800, 0x00000000); - nv_mthd(priv, 0x9097, 0x0840, 0x00000000); - nv_mthd(priv, 0x9097, 0x0880, 0x00000000); - nv_mthd(priv, 0x9097, 0x08c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0900, 0x00000000); - nv_mthd(priv, 0x9097, 0x0940, 0x00000000); - nv_mthd(priv, 0x9097, 0x0980, 0x00000000); - nv_mthd(priv, 0x9097, 0x09c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0804, 0x00000000); - nv_mthd(priv, 0x9097, 0x0844, 0x00000000); - nv_mthd(priv, 0x9097, 0x0884, 0x00000000); - nv_mthd(priv, 0x9097, 0x08c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0904, 0x00000000); - nv_mthd(priv, 0x9097, 0x0944, 0x00000000); - nv_mthd(priv, 0x9097, 0x0984, 0x00000000); - nv_mthd(priv, 0x9097, 0x09c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0808, 0x00000400); - nv_mthd(priv, 0x9097, 0x0848, 0x00000400); - nv_mthd(priv, 0x9097, 0x0888, 0x00000400); - nv_mthd(priv, 0x9097, 0x08c8, 0x00000400); - nv_mthd(priv, 0x9097, 0x0908, 0x00000400); - nv_mthd(priv, 0x9097, 0x0948, 0x00000400); - nv_mthd(priv, 0x9097, 0x0988, 0x00000400); - nv_mthd(priv, 0x9097, 0x09c8, 0x00000400); - nv_mthd(priv, 0x9097, 0x080c, 0x00000300); - nv_mthd(priv, 0x9097, 0x084c, 0x00000300); - nv_mthd(priv, 0x9097, 0x088c, 0x00000300); - nv_mthd(priv, 0x9097, 0x08cc, 0x00000300); - nv_mthd(priv, 0x9097, 0x090c, 0x00000300); - nv_mthd(priv, 0x9097, 0x094c, 0x00000300); - nv_mthd(priv, 0x9097, 0x098c, 0x00000300); - nv_mthd(priv, 0x9097, 0x09cc, 0x00000300); - nv_mthd(priv, 0x9097, 0x0810, 0x000000cf); - nv_mthd(priv, 0x9097, 0x0850, 0x00000000); - nv_mthd(priv, 0x9097, 0x0890, 0x00000000); - nv_mthd(priv, 0x9097, 0x08d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0910, 0x00000000); - nv_mthd(priv, 0x9097, 0x0950, 0x00000000); - nv_mthd(priv, 0x9097, 0x0990, 0x00000000); - nv_mthd(priv, 0x9097, 0x09d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0814, 0x00000040); - nv_mthd(priv, 0x9097, 0x0854, 0x00000040); - nv_mthd(priv, 0x9097, 0x0894, 0x00000040); - nv_mthd(priv, 0x9097, 0x08d4, 0x00000040); - nv_mthd(priv, 0x9097, 0x0914, 0x00000040); - nv_mthd(priv, 0x9097, 0x0954, 0x00000040); - nv_mthd(priv, 0x9097, 0x0994, 0x00000040); - nv_mthd(priv, 0x9097, 0x09d4, 0x00000040); - nv_mthd(priv, 0x9097, 0x0818, 0x00000001); - nv_mthd(priv, 0x9097, 0x0858, 0x00000001); - nv_mthd(priv, 0x9097, 0x0898, 0x00000001); - nv_mthd(priv, 0x9097, 0x08d8, 0x00000001); - nv_mthd(priv, 0x9097, 0x0918, 0x00000001); - nv_mthd(priv, 0x9097, 0x0958, 0x00000001); - nv_mthd(priv, 0x9097, 0x0998, 0x00000001); - nv_mthd(priv, 0x9097, 0x09d8, 0x00000001); - nv_mthd(priv, 0x9097, 0x081c, 0x00000000); - nv_mthd(priv, 0x9097, 0x085c, 0x00000000); - nv_mthd(priv, 0x9097, 0x089c, 0x00000000); - nv_mthd(priv, 0x9097, 0x08dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x091c, 0x00000000); - nv_mthd(priv, 0x9097, 0x095c, 0x00000000); - nv_mthd(priv, 0x9097, 0x099c, 0x00000000); - nv_mthd(priv, 0x9097, 0x09dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0820, 0x00000000); - nv_mthd(priv, 0x9097, 0x0860, 0x00000000); - nv_mthd(priv, 0x9097, 0x08a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x08e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0920, 0x00000000); - nv_mthd(priv, 0x9097, 0x0960, 0x00000000); - nv_mthd(priv, 0x9097, 0x09a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x09e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x2700, 0x00000000); - nv_mthd(priv, 0x9097, 0x2720, 0x00000000); - nv_mthd(priv, 0x9097, 0x2740, 0x00000000); - nv_mthd(priv, 0x9097, 0x2760, 0x00000000); - nv_mthd(priv, 0x9097, 0x2780, 0x00000000); - nv_mthd(priv, 0x9097, 0x27a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x27c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x27e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x2704, 0x00000000); - nv_mthd(priv, 0x9097, 0x2724, 0x00000000); - nv_mthd(priv, 0x9097, 0x2744, 0x00000000); - nv_mthd(priv, 0x9097, 0x2764, 0x00000000); - nv_mthd(priv, 0x9097, 0x2784, 0x00000000); - nv_mthd(priv, 0x9097, 0x27a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x27c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x27e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x2708, 0x00000000); - nv_mthd(priv, 0x9097, 0x2728, 0x00000000); - nv_mthd(priv, 0x9097, 0x2748, 0x00000000); - nv_mthd(priv, 0x9097, 0x2768, 0x00000000); - nv_mthd(priv, 0x9097, 0x2788, 0x00000000); - nv_mthd(priv, 0x9097, 0x27a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x27c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x27e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x270c, 0x00000000); - nv_mthd(priv, 0x9097, 0x272c, 0x00000000); - nv_mthd(priv, 0x9097, 0x274c, 0x00000000); - nv_mthd(priv, 0x9097, 0x276c, 0x00000000); - nv_mthd(priv, 0x9097, 0x278c, 0x00000000); - nv_mthd(priv, 0x9097, 0x27ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x27cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x27ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x2710, 0x00014000); - nv_mthd(priv, 0x9097, 0x2730, 0x00014000); - nv_mthd(priv, 0x9097, 0x2750, 0x00014000); - nv_mthd(priv, 0x9097, 0x2770, 0x00014000); - nv_mthd(priv, 0x9097, 0x2790, 0x00014000); - nv_mthd(priv, 0x9097, 0x27b0, 0x00014000); - nv_mthd(priv, 0x9097, 0x27d0, 0x00014000); - nv_mthd(priv, 0x9097, 0x27f0, 0x00014000); - nv_mthd(priv, 0x9097, 0x2714, 0x00000040); - nv_mthd(priv, 0x9097, 0x2734, 0x00000040); - nv_mthd(priv, 0x9097, 0x2754, 0x00000040); - nv_mthd(priv, 0x9097, 0x2774, 0x00000040); - nv_mthd(priv, 0x9097, 0x2794, 0x00000040); - nv_mthd(priv, 0x9097, 0x27b4, 0x00000040); - nv_mthd(priv, 0x9097, 0x27d4, 0x00000040); - nv_mthd(priv, 0x9097, 0x27f4, 0x00000040); - nv_mthd(priv, 0x9097, 0x1c00, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c10, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c20, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c30, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c40, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c50, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c60, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c70, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c80, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c90, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ca0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ce0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cf0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c04, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c14, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c24, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c34, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c44, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c54, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c64, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c74, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c84, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c94, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ca4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cb4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cd4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ce4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cf4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c08, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c18, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c28, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c38, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c48, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c58, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c68, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c78, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c88, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c98, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ca8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cb8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cd8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ce8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cf8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c1c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c2c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c3c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c5c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c6c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c7c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1c9c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cac, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cbc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ccc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cdc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cec, 0x00000000); - nv_mthd(priv, 0x9097, 0x1cfc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d00, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d10, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d20, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d30, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d40, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d50, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d60, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d70, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d80, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d90, 0x00000000); - nv_mthd(priv, 0x9097, 0x1da0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1db0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1de0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1df0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d04, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d14, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d24, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d34, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d44, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d54, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d64, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d74, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d84, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d94, 0x00000000); - nv_mthd(priv, 0x9097, 0x1da4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1db4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dd4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1de4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1df4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d08, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d18, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d28, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d38, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d48, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d58, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d68, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d78, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d88, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d98, 0x00000000); - nv_mthd(priv, 0x9097, 0x1da8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1db8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dd8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1de8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1df8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d1c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d2c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d3c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d5c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d6c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d7c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1d9c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dac, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dbc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dcc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ddc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dec, 0x00000000); - nv_mthd(priv, 0x9097, 0x1dfc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f00, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f08, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f10, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f18, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f20, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f28, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f30, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f38, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f40, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f48, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f50, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f58, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f60, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f68, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f70, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f78, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f04, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f14, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f1c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f24, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f2c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f34, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f3c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f44, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f54, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f5c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f64, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f6c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f74, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f7c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f80, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f88, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f90, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f98, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fa0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fa8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fb8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fd8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fe0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fe8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ff0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ff8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f84, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f94, 0x00000000); - nv_mthd(priv, 0x9097, 0x1f9c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fa4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fac, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fb4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fbc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fcc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fd4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fdc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fe4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1fec, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ff4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1ffc, 0x00000000); - nv_mthd(priv, 0x9097, 0x2200, 0x00000022); - nv_mthd(priv, 0x9097, 0x2210, 0x00000022); - nv_mthd(priv, 0x9097, 0x2220, 0x00000022); - nv_mthd(priv, 0x9097, 0x2230, 0x00000022); - nv_mthd(priv, 0x9097, 0x2240, 0x00000022); - nv_mthd(priv, 0x9097, 0x2000, 0x00000000); - nv_mthd(priv, 0x9097, 0x2040, 0x00000011); - nv_mthd(priv, 0x9097, 0x2080, 0x00000020); - nv_mthd(priv, 0x9097, 0x20c0, 0x00000030); - nv_mthd(priv, 0x9097, 0x2100, 0x00000040); - nv_mthd(priv, 0x9097, 0x2140, 0x00000051); - nv_mthd(priv, 0x9097, 0x200c, 0x00000001); - nv_mthd(priv, 0x9097, 0x204c, 0x00000001); - nv_mthd(priv, 0x9097, 0x208c, 0x00000001); - nv_mthd(priv, 0x9097, 0x20cc, 0x00000001); - nv_mthd(priv, 0x9097, 0x210c, 0x00000001); - nv_mthd(priv, 0x9097, 0x214c, 0x00000001); - nv_mthd(priv, 0x9097, 0x2010, 0x00000000); - nv_mthd(priv, 0x9097, 0x2050, 0x00000000); - nv_mthd(priv, 0x9097, 0x2090, 0x00000001); - nv_mthd(priv, 0x9097, 0x20d0, 0x00000002); - nv_mthd(priv, 0x9097, 0x2110, 0x00000003); - nv_mthd(priv, 0x9097, 0x2150, 0x00000004); - nv_mthd(priv, 0x9097, 0x0380, 0x00000000); - nv_mthd(priv, 0x9097, 0x03a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x03c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x03e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0384, 0x00000000); - nv_mthd(priv, 0x9097, 0x03a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x03c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x03e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0388, 0x00000000); - nv_mthd(priv, 0x9097, 0x03a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x03c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x03e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x038c, 0x00000000); - nv_mthd(priv, 0x9097, 0x03ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x03cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x03ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x0700, 0x00000000); - nv_mthd(priv, 0x9097, 0x0710, 0x00000000); - nv_mthd(priv, 0x9097, 0x0720, 0x00000000); - nv_mthd(priv, 0x9097, 0x0730, 0x00000000); - nv_mthd(priv, 0x9097, 0x0704, 0x00000000); - nv_mthd(priv, 0x9097, 0x0714, 0x00000000); - nv_mthd(priv, 0x9097, 0x0724, 0x00000000); - nv_mthd(priv, 0x9097, 0x0734, 0x00000000); - nv_mthd(priv, 0x9097, 0x0708, 0x00000000); - nv_mthd(priv, 0x9097, 0x0718, 0x00000000); - nv_mthd(priv, 0x9097, 0x0728, 0x00000000); - nv_mthd(priv, 0x9097, 0x0738, 0x00000000); - nv_mthd(priv, 0x9097, 0x2800, 0x00000000); - nv_mthd(priv, 0x9097, 0x2804, 0x00000000); - nv_mthd(priv, 0x9097, 0x2808, 0x00000000); - nv_mthd(priv, 0x9097, 0x280c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2810, 0x00000000); - nv_mthd(priv, 0x9097, 0x2814, 0x00000000); - nv_mthd(priv, 0x9097, 0x2818, 0x00000000); - nv_mthd(priv, 0x9097, 0x281c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2820, 0x00000000); - nv_mthd(priv, 0x9097, 0x2824, 0x00000000); - nv_mthd(priv, 0x9097, 0x2828, 0x00000000); - nv_mthd(priv, 0x9097, 0x282c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2830, 0x00000000); - nv_mthd(priv, 0x9097, 0x2834, 0x00000000); - nv_mthd(priv, 0x9097, 0x2838, 0x00000000); - nv_mthd(priv, 0x9097, 0x283c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2840, 0x00000000); - nv_mthd(priv, 0x9097, 0x2844, 0x00000000); - nv_mthd(priv, 0x9097, 0x2848, 0x00000000); - nv_mthd(priv, 0x9097, 0x284c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2850, 0x00000000); - nv_mthd(priv, 0x9097, 0x2854, 0x00000000); - nv_mthd(priv, 0x9097, 0x2858, 0x00000000); - nv_mthd(priv, 0x9097, 0x285c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2860, 0x00000000); - nv_mthd(priv, 0x9097, 0x2864, 0x00000000); - nv_mthd(priv, 0x9097, 0x2868, 0x00000000); - nv_mthd(priv, 0x9097, 0x286c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2870, 0x00000000); - nv_mthd(priv, 0x9097, 0x2874, 0x00000000); - nv_mthd(priv, 0x9097, 0x2878, 0x00000000); - nv_mthd(priv, 0x9097, 0x287c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2880, 0x00000000); - nv_mthd(priv, 0x9097, 0x2884, 0x00000000); - nv_mthd(priv, 0x9097, 0x2888, 0x00000000); - nv_mthd(priv, 0x9097, 0x288c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2890, 0x00000000); - nv_mthd(priv, 0x9097, 0x2894, 0x00000000); - nv_mthd(priv, 0x9097, 0x2898, 0x00000000); - nv_mthd(priv, 0x9097, 0x289c, 0x00000000); - nv_mthd(priv, 0x9097, 0x28a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x28b0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28b4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28b8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x28c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x28d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28d4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28d8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x28e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x28f0, 0x00000000); - nv_mthd(priv, 0x9097, 0x28f4, 0x00000000); - nv_mthd(priv, 0x9097, 0x28f8, 0x00000000); - nv_mthd(priv, 0x9097, 0x28fc, 0x00000000); - nv_mthd(priv, 0x9097, 0x2900, 0x00000000); - nv_mthd(priv, 0x9097, 0x2904, 0x00000000); - nv_mthd(priv, 0x9097, 0x2908, 0x00000000); - nv_mthd(priv, 0x9097, 0x290c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2910, 0x00000000); - nv_mthd(priv, 0x9097, 0x2914, 0x00000000); - nv_mthd(priv, 0x9097, 0x2918, 0x00000000); - nv_mthd(priv, 0x9097, 0x291c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2920, 0x00000000); - nv_mthd(priv, 0x9097, 0x2924, 0x00000000); - nv_mthd(priv, 0x9097, 0x2928, 0x00000000); - nv_mthd(priv, 0x9097, 0x292c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2930, 0x00000000); - nv_mthd(priv, 0x9097, 0x2934, 0x00000000); - nv_mthd(priv, 0x9097, 0x2938, 0x00000000); - nv_mthd(priv, 0x9097, 0x293c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2940, 0x00000000); - nv_mthd(priv, 0x9097, 0x2944, 0x00000000); - nv_mthd(priv, 0x9097, 0x2948, 0x00000000); - nv_mthd(priv, 0x9097, 0x294c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2950, 0x00000000); - nv_mthd(priv, 0x9097, 0x2954, 0x00000000); - nv_mthd(priv, 0x9097, 0x2958, 0x00000000); - nv_mthd(priv, 0x9097, 0x295c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2960, 0x00000000); - nv_mthd(priv, 0x9097, 0x2964, 0x00000000); - nv_mthd(priv, 0x9097, 0x2968, 0x00000000); - nv_mthd(priv, 0x9097, 0x296c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2970, 0x00000000); - nv_mthd(priv, 0x9097, 0x2974, 0x00000000); - nv_mthd(priv, 0x9097, 0x2978, 0x00000000); - nv_mthd(priv, 0x9097, 0x297c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2980, 0x00000000); - nv_mthd(priv, 0x9097, 0x2984, 0x00000000); - nv_mthd(priv, 0x9097, 0x2988, 0x00000000); - nv_mthd(priv, 0x9097, 0x298c, 0x00000000); - nv_mthd(priv, 0x9097, 0x2990, 0x00000000); - nv_mthd(priv, 0x9097, 0x2994, 0x00000000); - nv_mthd(priv, 0x9097, 0x2998, 0x00000000); - nv_mthd(priv, 0x9097, 0x299c, 0x00000000); - nv_mthd(priv, 0x9097, 0x29a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x29b0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29b4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29b8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x29c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x29d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29d4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29d8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x29e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x29f0, 0x00000000); - nv_mthd(priv, 0x9097, 0x29f4, 0x00000000); - nv_mthd(priv, 0x9097, 0x29f8, 0x00000000); - nv_mthd(priv, 0x9097, 0x29fc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a00, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a20, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a40, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a60, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a80, 0x00000000); - nv_mthd(priv, 0x9097, 0x0aa0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ac0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ae0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b00, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b20, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b40, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b60, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b80, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ba0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0be0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a04, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a24, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a44, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a64, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a84, 0x00000000); - nv_mthd(priv, 0x9097, 0x0aa4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ac4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ae4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b04, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b24, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b44, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b64, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b84, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ba4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0be4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a08, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a28, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a48, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a68, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a88, 0x00000000); - nv_mthd(priv, 0x9097, 0x0aa8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ac8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ae8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b08, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b28, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b48, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b68, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b88, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ba8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0be8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a2c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a6c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0aac, 0x00000000); - nv_mthd(priv, 0x9097, 0x0acc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0aec, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b2c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b6c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bac, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bcc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bec, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a10, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a30, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a50, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a70, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a90, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ab0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ad0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0af0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b10, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b30, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b50, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b70, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b90, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bf0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a14, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a34, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a54, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a74, 0x00000000); - nv_mthd(priv, 0x9097, 0x0a94, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ab4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ad4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0af4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b14, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b34, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b54, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b74, 0x00000000); - nv_mthd(priv, 0x9097, 0x0b94, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bb4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bd4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0bf4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c00, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c10, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c20, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c30, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c40, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c50, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c60, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c70, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c80, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c90, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ca0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ce0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cf0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c04, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c14, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c24, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c34, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c44, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c54, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c64, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c74, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c84, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c94, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ca4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cb4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cd4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ce4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cf4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c08, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c18, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c28, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c38, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c48, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c58, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c68, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c78, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c88, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c98, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ca8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cb8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cd8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ce8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0cf8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0c0c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c1c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c2c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c3c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c4c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c5c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c6c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c7c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c8c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0c9c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0cac, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0cbc, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0ccc, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0cdc, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0cec, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0cfc, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0d00, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d08, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d10, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d18, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d20, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d28, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d30, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d38, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d04, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d0c, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d14, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d1c, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d24, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d2c, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d34, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d3c, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e00, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e10, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e20, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e30, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e40, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e50, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e60, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e70, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e80, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e90, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ea0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0eb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ec0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ed0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ee0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ef0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0e04, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e14, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e24, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e34, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e44, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e54, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e64, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e74, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e84, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e94, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ea4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0eb4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ec4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ed4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ee4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ef4, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e08, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e18, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e28, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e38, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e48, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e58, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e68, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e78, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e88, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0e98, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ea8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0eb8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ec8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ed8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ee8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0ef8, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d40, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d48, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d50, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d58, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d44, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d4c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d54, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d5c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1e00, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e20, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e40, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e60, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e80, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ea0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ec0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ee0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e04, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e24, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e44, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e64, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e84, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ea4, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ec4, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ee4, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e08, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e28, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e48, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e68, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e88, 0x00000002); - nv_mthd(priv, 0x9097, 0x1ea8, 0x00000002); - nv_mthd(priv, 0x9097, 0x1ec8, 0x00000002); - nv_mthd(priv, 0x9097, 0x1ee8, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e0c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e2c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e4c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e6c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e8c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1eac, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ecc, 0x00000001); - nv_mthd(priv, 0x9097, 0x1eec, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e10, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e30, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e50, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e70, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e90, 0x00000001); - nv_mthd(priv, 0x9097, 0x1eb0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ed0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ef0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e14, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e34, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e54, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e74, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e94, 0x00000002); - nv_mthd(priv, 0x9097, 0x1eb4, 0x00000002); - nv_mthd(priv, 0x9097, 0x1ed4, 0x00000002); - nv_mthd(priv, 0x9097, 0x1ef4, 0x00000002); - nv_mthd(priv, 0x9097, 0x1e18, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e38, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e58, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e78, 0x00000001); - nv_mthd(priv, 0x9097, 0x1e98, 0x00000001); - nv_mthd(priv, 0x9097, 0x1eb8, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ed8, 0x00000001); - nv_mthd(priv, 0x9097, 0x1ef8, 0x00000001); - if (fermi == 0x9097) { - for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4) - nv_mthd(priv, 0x9097, mthd, 0x00000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); + } } - nv_mthd(priv, 0x9097, 0x030c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1944, 0x00000000); - nv_mthd(priv, 0x9097, 0x1514, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d68, 0x0000ffff); - nv_mthd(priv, 0x9097, 0x121c, 0x0fac6881); - nv_mthd(priv, 0x9097, 0x0fac, 0x00000001); - nv_mthd(priv, 0x9097, 0x1538, 0x00000001); - nv_mthd(priv, 0x9097, 0x0fe0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fe4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fe8, 0x00000014); - nv_mthd(priv, 0x9097, 0x0fec, 0x00000040); - nv_mthd(priv, 0x9097, 0x0ff0, 0x00000000); - nv_mthd(priv, 0x9097, 0x179c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1228, 0x00000400); - nv_mthd(priv, 0x9097, 0x122c, 0x00000300); - nv_mthd(priv, 0x9097, 0x1230, 0x00010001); - nv_mthd(priv, 0x9097, 0x07f8, 0x00000000); - nv_mthd(priv, 0x9097, 0x15b4, 0x00000001); - nv_mthd(priv, 0x9097, 0x15cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1534, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fb0, 0x00000000); - nv_mthd(priv, 0x9097, 0x15d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x153c, 0x00000000); - nv_mthd(priv, 0x9097, 0x16b4, 0x00000003); - nv_mthd(priv, 0x9097, 0x0fbc, 0x0000ffff); - nv_mthd(priv, 0x9097, 0x0fc0, 0x0000ffff); - nv_mthd(priv, 0x9097, 0x0fc4, 0x0000ffff); - nv_mthd(priv, 0x9097, 0x0fc8, 0x0000ffff); - nv_mthd(priv, 0x9097, 0x0df8, 0x00000000); - nv_mthd(priv, 0x9097, 0x0dfc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1948, 0x00000000); - nv_mthd(priv, 0x9097, 0x1970, 0x00000001); - nv_mthd(priv, 0x9097, 0x161c, 0x000009f0); - nv_mthd(priv, 0x9097, 0x0dcc, 0x00000010); - nv_mthd(priv, 0x9097, 0x163c, 0x00000000); - nv_mthd(priv, 0x9097, 0x15e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1160, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1164, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1168, 0x25e00040); - nv_mthd(priv, 0x9097, 0x116c, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1170, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1174, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1178, 0x25e00040); - nv_mthd(priv, 0x9097, 0x117c, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1180, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1184, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1188, 0x25e00040); - nv_mthd(priv, 0x9097, 0x118c, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1190, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1194, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1198, 0x25e00040); - nv_mthd(priv, 0x9097, 0x119c, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11a0, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11a4, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11a8, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11ac, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11b0, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11b4, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11b8, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11bc, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11c0, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11c4, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11c8, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11cc, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11d0, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11d4, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11d8, 0x25e00040); - nv_mthd(priv, 0x9097, 0x11dc, 0x25e00040); - nv_mthd(priv, 0x9097, 0x1880, 0x00000000); - nv_mthd(priv, 0x9097, 0x1884, 0x00000000); - nv_mthd(priv, 0x9097, 0x1888, 0x00000000); - nv_mthd(priv, 0x9097, 0x188c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1890, 0x00000000); - nv_mthd(priv, 0x9097, 0x1894, 0x00000000); - nv_mthd(priv, 0x9097, 0x1898, 0x00000000); - nv_mthd(priv, 0x9097, 0x189c, 0x00000000); - nv_mthd(priv, 0x9097, 0x18a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x18b0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18b4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18b8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x18c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x18d0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18d4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18d8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x18e0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x18f0, 0x00000000); - nv_mthd(priv, 0x9097, 0x18f4, 0x00000000); - nv_mthd(priv, 0x9097, 0x18f8, 0x00000000); - nv_mthd(priv, 0x9097, 0x18fc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f84, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f88, 0x00000000); - nv_mthd(priv, 0x9097, 0x17c8, 0x00000000); - nv_mthd(priv, 0x9097, 0x17cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x17d0, 0x000000ff); - nv_mthd(priv, 0x9097, 0x17d4, 0xffffffff); - nv_mthd(priv, 0x9097, 0x17d8, 0x00000002); - nv_mthd(priv, 0x9097, 0x17dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x15f4, 0x00000000); - nv_mthd(priv, 0x9097, 0x15f8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1434, 0x00000000); - nv_mthd(priv, 0x9097, 0x1438, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d74, 0x00000000); - nv_mthd(priv, 0x9097, 0x0dec, 0x00000001); - nv_mthd(priv, 0x9097, 0x13a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1318, 0x00000001); - nv_mthd(priv, 0x9097, 0x1644, 0x00000000); - nv_mthd(priv, 0x9097, 0x0748, 0x00000000); - nv_mthd(priv, 0x9097, 0x0de8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1648, 0x00000000); - nv_mthd(priv, 0x9097, 0x12a4, 0x00000000); - nv_mthd(priv, 0x9097, 0x1120, 0x00000000); - nv_mthd(priv, 0x9097, 0x1124, 0x00000000); - nv_mthd(priv, 0x9097, 0x1128, 0x00000000); - nv_mthd(priv, 0x9097, 0x112c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1118, 0x00000000); - nv_mthd(priv, 0x9097, 0x164c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1658, 0x00000000); - nv_mthd(priv, 0x9097, 0x1910, 0x00000290); - nv_mthd(priv, 0x9097, 0x1518, 0x00000000); - nv_mthd(priv, 0x9097, 0x165c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1520, 0x00000000); - nv_mthd(priv, 0x9097, 0x1604, 0x00000000); - nv_mthd(priv, 0x9097, 0x1570, 0x00000000); - nv_mthd(priv, 0x9097, 0x13b0, 0x3f800000); - nv_mthd(priv, 0x9097, 0x13b4, 0x3f800000); - nv_mthd(priv, 0x9097, 0x020c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1670, 0x30201000); - nv_mthd(priv, 0x9097, 0x1674, 0x70605040); - nv_mthd(priv, 0x9097, 0x1678, 0xb8a89888); - nv_mthd(priv, 0x9097, 0x167c, 0xf8e8d8c8); - nv_mthd(priv, 0x9097, 0x166c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1680, 0x00ffff00); - nv_mthd(priv, 0x9097, 0x12d0, 0x00000003); - nv_mthd(priv, 0x9097, 0x12d4, 0x00000002); - nv_mthd(priv, 0x9097, 0x1684, 0x00000000); - nv_mthd(priv, 0x9097, 0x1688, 0x00000000); - nv_mthd(priv, 0x9097, 0x0dac, 0x00001b02); - nv_mthd(priv, 0x9097, 0x0db0, 0x00001b02); - nv_mthd(priv, 0x9097, 0x0db4, 0x00000000); - nv_mthd(priv, 0x9097, 0x168c, 0x00000000); - nv_mthd(priv, 0x9097, 0x15bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x156c, 0x00000000); - nv_mthd(priv, 0x9097, 0x187c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1110, 0x00000001); - nv_mthd(priv, 0x9097, 0x0dc0, 0x00000000); - nv_mthd(priv, 0x9097, 0x0dc4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0dc8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1234, 0x00000000); - nv_mthd(priv, 0x9097, 0x1690, 0x00000000); - nv_mthd(priv, 0x9097, 0x12ac, 0x00000001); - nv_mthd(priv, 0x9097, 0x02c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0790, 0x00000000); - nv_mthd(priv, 0x9097, 0x0794, 0x00000000); - nv_mthd(priv, 0x9097, 0x0798, 0x00000000); - nv_mthd(priv, 0x9097, 0x079c, 0x00000000); - nv_mthd(priv, 0x9097, 0x07a0, 0x00000000); - nv_mthd(priv, 0x9097, 0x077c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1000, 0x00000010); - nv_mthd(priv, 0x9097, 0x10fc, 0x00000000); - nv_mthd(priv, 0x9097, 0x1290, 0x00000000); - nv_mthd(priv, 0x9097, 0x0218, 0x00000010); - nv_mthd(priv, 0x9097, 0x12d8, 0x00000000); - nv_mthd(priv, 0x9097, 0x12dc, 0x00000010); - nv_mthd(priv, 0x9097, 0x0d94, 0x00000001); - nv_mthd(priv, 0x9097, 0x155c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1560, 0x00000000); - nv_mthd(priv, 0x9097, 0x1564, 0x00001fff); - nv_mthd(priv, 0x9097, 0x1574, 0x00000000); - nv_mthd(priv, 0x9097, 0x1578, 0x00000000); - nv_mthd(priv, 0x9097, 0x157c, 0x003fffff); - nv_mthd(priv, 0x9097, 0x1354, 0x00000000); - nv_mthd(priv, 0x9097, 0x1664, 0x00000000); - nv_mthd(priv, 0x9097, 0x1610, 0x00000012); - nv_mthd(priv, 0x9097, 0x1608, 0x00000000); - nv_mthd(priv, 0x9097, 0x160c, 0x00000000); - nv_mthd(priv, 0x9097, 0x162c, 0x00000003); - nv_mthd(priv, 0x9097, 0x0210, 0x00000000); - nv_mthd(priv, 0x9097, 0x0320, 0x00000000); - nv_mthd(priv, 0x9097, 0x0324, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0328, 0x3f800000); - nv_mthd(priv, 0x9097, 0x032c, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0330, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0334, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0338, 0x3f800000); - nv_mthd(priv, 0x9097, 0x0750, 0x00000000); - nv_mthd(priv, 0x9097, 0x0760, 0x39291909); - nv_mthd(priv, 0x9097, 0x0764, 0x79695949); - nv_mthd(priv, 0x9097, 0x0768, 0xb9a99989); - nv_mthd(priv, 0x9097, 0x076c, 0xf9e9d9c9); - nv_mthd(priv, 0x9097, 0x0770, 0x30201000); - nv_mthd(priv, 0x9097, 0x0774, 0x70605040); - nv_mthd(priv, 0x9097, 0x0778, 0x00009080); - nv_mthd(priv, 0x9097, 0x0780, 0x39291909); - nv_mthd(priv, 0x9097, 0x0784, 0x79695949); - nv_mthd(priv, 0x9097, 0x0788, 0xb9a99989); - nv_mthd(priv, 0x9097, 0x078c, 0xf9e9d9c9); - nv_mthd(priv, 0x9097, 0x07d0, 0x30201000); - nv_mthd(priv, 0x9097, 0x07d4, 0x70605040); - nv_mthd(priv, 0x9097, 0x07d8, 0x00009080); - nv_mthd(priv, 0x9097, 0x037c, 0x00000001); - nv_mthd(priv, 0x9097, 0x0740, 0x00000000); - nv_mthd(priv, 0x9097, 0x0744, 0x00000000); - nv_mthd(priv, 0x9097, 0x2600, 0x00000000); - nv_mthd(priv, 0x9097, 0x1918, 0x00000000); - nv_mthd(priv, 0x9097, 0x191c, 0x00000900); - nv_mthd(priv, 0x9097, 0x1920, 0x00000405); - nv_mthd(priv, 0x9097, 0x1308, 0x00000001); - nv_mthd(priv, 0x9097, 0x1924, 0x00000000); - nv_mthd(priv, 0x9097, 0x13ac, 0x00000000); - nv_mthd(priv, 0x9097, 0x192c, 0x00000001); - nv_mthd(priv, 0x9097, 0x193c, 0x00002c1c); - nv_mthd(priv, 0x9097, 0x0d7c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x02c0, 0x00000001); - nv_mthd(priv, 0x9097, 0x1510, 0x00000000); - nv_mthd(priv, 0x9097, 0x1940, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ff4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0ff8, 0x00000000); - nv_mthd(priv, 0x9097, 0x194c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1950, 0x00000000); - nv_mthd(priv, 0x9097, 0x1968, 0x00000000); - nv_mthd(priv, 0x9097, 0x1590, 0x0000003f); - nv_mthd(priv, 0x9097, 0x07e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x07ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x07f0, 0x00000000); - nv_mthd(priv, 0x9097, 0x07f4, 0x00000000); - nv_mthd(priv, 0x9097, 0x196c, 0x00000011); - nv_mthd(priv, 0x9097, 0x197c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fcc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fd0, 0x00000000); - nv_mthd(priv, 0x9097, 0x02d8, 0x00000040); - nv_mthd(priv, 0x9097, 0x1980, 0x00000080); - nv_mthd(priv, 0x9097, 0x1504, 0x00000080); - nv_mthd(priv, 0x9097, 0x1984, 0x00000000); - nv_mthd(priv, 0x9097, 0x0300, 0x00000001); - nv_mthd(priv, 0x9097, 0x13a8, 0x00000000); - nv_mthd(priv, 0x9097, 0x12ec, 0x00000000); - nv_mthd(priv, 0x9097, 0x1310, 0x00000000); - nv_mthd(priv, 0x9097, 0x1314, 0x00000001); - nv_mthd(priv, 0x9097, 0x1380, 0x00000000); - nv_mthd(priv, 0x9097, 0x1384, 0x00000001); - nv_mthd(priv, 0x9097, 0x1388, 0x00000001); - nv_mthd(priv, 0x9097, 0x138c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1390, 0x00000001); - nv_mthd(priv, 0x9097, 0x1394, 0x00000000); - nv_mthd(priv, 0x9097, 0x139c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1398, 0x00000000); - nv_mthd(priv, 0x9097, 0x1594, 0x00000000); - nv_mthd(priv, 0x9097, 0x1598, 0x00000001); - nv_mthd(priv, 0x9097, 0x159c, 0x00000001); - nv_mthd(priv, 0x9097, 0x15a0, 0x00000001); - nv_mthd(priv, 0x9097, 0x15a4, 0x00000001); - nv_mthd(priv, 0x9097, 0x0f54, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f58, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f5c, 0x00000000); - nv_mthd(priv, 0x9097, 0x19bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f9c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0fa0, 0x00000000); - nv_mthd(priv, 0x9097, 0x12cc, 0x00000000); - nv_mthd(priv, 0x9097, 0x12e8, 0x00000000); - nv_mthd(priv, 0x9097, 0x130c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1360, 0x00000000); - nv_mthd(priv, 0x9097, 0x1364, 0x00000000); - nv_mthd(priv, 0x9097, 0x1368, 0x00000000); - nv_mthd(priv, 0x9097, 0x136c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1370, 0x00000000); - nv_mthd(priv, 0x9097, 0x1374, 0x00000000); - nv_mthd(priv, 0x9097, 0x1378, 0x00000000); - nv_mthd(priv, 0x9097, 0x137c, 0x00000000); - nv_mthd(priv, 0x9097, 0x133c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1340, 0x00000001); - nv_mthd(priv, 0x9097, 0x1344, 0x00000002); - nv_mthd(priv, 0x9097, 0x1348, 0x00000001); - nv_mthd(priv, 0x9097, 0x134c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1350, 0x00000002); - nv_mthd(priv, 0x9097, 0x1358, 0x00000001); - nv_mthd(priv, 0x9097, 0x12e4, 0x00000000); - nv_mthd(priv, 0x9097, 0x131c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1320, 0x00000000); - nv_mthd(priv, 0x9097, 0x1324, 0x00000000); - nv_mthd(priv, 0x9097, 0x1328, 0x00000000); - nv_mthd(priv, 0x9097, 0x19c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1140, 0x00000000); - nv_mthd(priv, 0x9097, 0x19c4, 0x00000000); - nv_mthd(priv, 0x9097, 0x19c8, 0x00001500); - nv_mthd(priv, 0x9097, 0x135c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f90, 0x00000000); - nv_mthd(priv, 0x9097, 0x19e0, 0x00000001); - nv_mthd(priv, 0x9097, 0x19e4, 0x00000001); - nv_mthd(priv, 0x9097, 0x19e8, 0x00000001); - nv_mthd(priv, 0x9097, 0x19ec, 0x00000001); - nv_mthd(priv, 0x9097, 0x19f0, 0x00000001); - nv_mthd(priv, 0x9097, 0x19f4, 0x00000001); - nv_mthd(priv, 0x9097, 0x19f8, 0x00000001); - nv_mthd(priv, 0x9097, 0x19fc, 0x00000001); - nv_mthd(priv, 0x9097, 0x19cc, 0x00000001); - nv_mthd(priv, 0x9097, 0x15b8, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a00, 0x00001111); - nv_mthd(priv, 0x9097, 0x1a04, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a08, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a0c, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a10, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a14, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a18, 0x00000000); - nv_mthd(priv, 0x9097, 0x1a1c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d6c, 0xffff0000); - nv_mthd(priv, 0x9097, 0x0d70, 0xffff0000); - nv_mthd(priv, 0x9097, 0x10f8, 0x00001010); - nv_mthd(priv, 0x9097, 0x0d80, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d84, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d88, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d8c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0d90, 0x00000000); - nv_mthd(priv, 0x9097, 0x0da0, 0x00000000); - nv_mthd(priv, 0x9097, 0x1508, 0x80000000); - nv_mthd(priv, 0x9097, 0x150c, 0x40000000); - nv_mthd(priv, 0x9097, 0x1668, 0x00000000); - nv_mthd(priv, 0x9097, 0x0318, 0x00000008); - nv_mthd(priv, 0x9097, 0x031c, 0x00000008); - nv_mthd(priv, 0x9097, 0x0d9c, 0x00000001); - nv_mthd(priv, 0x9097, 0x07dc, 0x00000000); - nv_mthd(priv, 0x9097, 0x074c, 0x00000055); - nv_mthd(priv, 0x9097, 0x1420, 0x00000003); - nv_mthd(priv, 0x9097, 0x17bc, 0x00000000); - nv_mthd(priv, 0x9097, 0x17c0, 0x00000000); - nv_mthd(priv, 0x9097, 0x17c4, 0x00000001); - nv_mthd(priv, 0x9097, 0x1008, 0x00000008); - nv_mthd(priv, 0x9097, 0x100c, 0x00000040); - nv_mthd(priv, 0x9097, 0x1010, 0x0000012c); - nv_mthd(priv, 0x9097, 0x0d60, 0x00000040); - nv_mthd(priv, 0x9097, 0x075c, 0x00000003); - nv_mthd(priv, 0x9097, 0x1018, 0x00000020); - nv_mthd(priv, 0x9097, 0x101c, 0x00000001); - nv_mthd(priv, 0x9097, 0x1020, 0x00000020); - nv_mthd(priv, 0x9097, 0x1024, 0x00000001); - nv_mthd(priv, 0x9097, 0x1444, 0x00000000); - nv_mthd(priv, 0x9097, 0x1448, 0x00000000); - nv_mthd(priv, 0x9097, 0x144c, 0x00000000); - nv_mthd(priv, 0x9097, 0x0360, 0x20164010); - nv_mthd(priv, 0x9097, 0x0364, 0x00000020); - nv_mthd(priv, 0x9097, 0x0368, 0x00000000); - nv_mthd(priv, 0x9097, 0x0de4, 0x00000000); - nv_mthd(priv, 0x9097, 0x0204, 0x00000006); - nv_mthd(priv, 0x9097, 0x0208, 0x00000000); - nv_mthd(priv, 0x9097, 0x02cc, 0x003fffff); - nv_mthd(priv, 0x9097, 0x02d0, 0x00000c48); - nv_mthd(priv, 0x9097, 0x1220, 0x00000005); - nv_mthd(priv, 0x9097, 0x0fdc, 0x00000000); - nv_mthd(priv, 0x9097, 0x0f98, 0x00300008); - nv_mthd(priv, 0x9097, 0x1284, 0x04000080); - nv_mthd(priv, 0x9097, 0x1450, 0x00300008); - nv_mthd(priv, 0x9097, 0x1454, 0x04000080); - nv_mthd(priv, 0x9097, 0x0214, 0x00000000); } -static void -nvc0_grctx_generate_9197(struct nvc0_graph_priv *priv) +void +nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv) { - u32 fermi = nvc0_graph_class(priv); - u32 mthd; - - if (fermi == 0x9197) { - for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4) - nv_mthd(priv, 0x9197, mthd, 0x00000000); + u32 tmp[GPC_MAX / 8] = {}, i = 0; + for (i = 0; i < priv->gpc_nr; i++) + tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4); + for (i = 0; i < 4; i++) { + nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); + nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); } - nv_mthd(priv, 0x9197, 0x02e4, 0x0000b001); } -static void -nvc0_grctx_generate_9297(struct nvc0_graph_priv *priv) +void +nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv) { - u32 fermi = nvc0_graph_class(priv); - u32 mthd; - - if (fermi == 0x9297) { - for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4) - nv_mthd(priv, 0x9297, mthd, 0x00000000); + u8 tpcnr[GPC_MAX], data[TPC_MAX]; + int gpc, tpc, i; + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memset(data, 0x1f, sizeof(data)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + data[tpc] = gpc; } - nv_mthd(priv, 0x9297, 0x036c, 0x00000000); - nv_mthd(priv, 0x9297, 0x0370, 0x00000000); - nv_mthd(priv, 0x9297, 0x07a4, 0x00000000); - nv_mthd(priv, 0x9297, 0x07a8, 0x00000000); - nv_mthd(priv, 0x9297, 0x0374, 0x00000000); - nv_mthd(priv, 0x9297, 0x0378, 0x00000020); -} - -static void -nvc0_grctx_generate_902d(struct nvc0_graph_priv *priv) -{ - nv_mthd(priv, 0x902d, 0x0200, 0x000000cf); - nv_mthd(priv, 0x902d, 0x0204, 0x00000001); - nv_mthd(priv, 0x902d, 0x0208, 0x00000020); - nv_mthd(priv, 0x902d, 0x020c, 0x00000001); - nv_mthd(priv, 0x902d, 0x0210, 0x00000000); - nv_mthd(priv, 0x902d, 0x0214, 0x00000080); - nv_mthd(priv, 0x902d, 0x0218, 0x00000100); - nv_mthd(priv, 0x902d, 0x021c, 0x00000100); - nv_mthd(priv, 0x902d, 0x0220, 0x00000000); - nv_mthd(priv, 0x902d, 0x0224, 0x00000000); - nv_mthd(priv, 0x902d, 0x0230, 0x000000cf); - nv_mthd(priv, 0x902d, 0x0234, 0x00000001); - nv_mthd(priv, 0x902d, 0x0238, 0x00000020); - nv_mthd(priv, 0x902d, 0x023c, 0x00000001); - nv_mthd(priv, 0x902d, 0x0244, 0x00000080); - nv_mthd(priv, 0x902d, 0x0248, 0x00000100); - nv_mthd(priv, 0x902d, 0x024c, 0x00000100); -} -static void -nvc0_grctx_generate_9039(struct nvc0_graph_priv *priv) -{ - nv_mthd(priv, 0x9039, 0x030c, 0x00000000); - nv_mthd(priv, 0x9039, 0x0310, 0x00000000); - nv_mthd(priv, 0x9039, 0x0314, 0x00000000); - nv_mthd(priv, 0x9039, 0x0320, 0x00000000); - nv_mthd(priv, 0x9039, 0x0238, 0x00000000); - nv_mthd(priv, 0x9039, 0x023c, 0x00000000); - nv_mthd(priv, 0x9039, 0x0318, 0x00000000); - nv_mthd(priv, 0x9039, 0x031c, 0x00000000); + for (i = 0; i < 4; i++) + nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); } -static void -nvc0_grctx_generate_90c0(struct nvc0_graph_priv *priv) +void +nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) { - int i; - - for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) { - nv_mthd(priv, 0x90c0, 0x2700 + (i * 0x40), 0x00000000); - nv_mthd(priv, 0x90c0, 0x2720 + (i * 0x40), 0x00000000); - nv_mthd(priv, 0x90c0, 0x2704 + (i * 0x40), 0x00000000); - nv_mthd(priv, 0x90c0, 0x2724 + (i * 0x40), 0x00000000); - nv_mthd(priv, 0x90c0, 0x2708 + (i * 0x40), 0x00000000); - nv_mthd(priv, 0x90c0, 0x2728 + (i * 0x40), 0x00000000); - } - nv_mthd(priv, 0x90c0, 0x270c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x272c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x274c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x276c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x278c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x27ac, 0x00000000); - nv_mthd(priv, 0x90c0, 0x27cc, 0x00000000); - nv_mthd(priv, 0x90c0, 0x27ec, 0x00000000); - for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) { - nv_mthd(priv, 0x90c0, 0x2710 + (i * 0x40), 0x00014000); - nv_mthd(priv, 0x90c0, 0x2730 + (i * 0x40), 0x00014000); - } - for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) { - nv_mthd(priv, 0x90c0, 0x2714 + (i * 0x40), 0x00000040); - nv_mthd(priv, 0x90c0, 0x2734 + (i * 0x40), 0x00000040); + u32 data[6] = {}, data2[2] = {}; + u8 tpcnr[GPC_MAX]; + u8 shift, ntpcv; + int gpc, tpc, i; + + /* calculate first set of magics */ + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + + data[tpc / 6] |= gpc << ((tpc % 6) * 5); } - nv_mthd(priv, 0x90c0, 0x030c, 0x00000001); - nv_mthd(priv, 0x90c0, 0x1944, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0758, 0x00000100); - nv_mthd(priv, 0x90c0, 0x02c4, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0790, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0794, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0798, 0x00000000); - nv_mthd(priv, 0x90c0, 0x079c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x07a0, 0x00000000); - nv_mthd(priv, 0x90c0, 0x077c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0204, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0208, 0x00000000); - nv_mthd(priv, 0x90c0, 0x020c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0214, 0x00000000); - nv_mthd(priv, 0x90c0, 0x024c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x0d94, 0x00000001); - nv_mthd(priv, 0x90c0, 0x1608, 0x00000000); - nv_mthd(priv, 0x90c0, 0x160c, 0x00000000); - nv_mthd(priv, 0x90c0, 0x1664, 0x00000000); -} -static void -nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) -{ - int i; + for (; tpc < 32; tpc++) + data[tpc / 6] |= 7 << ((tpc % 6) * 5); - nv_wr32(priv, 0x404004, 0x00000000); - nv_wr32(priv, 0x404008, 0x00000000); - nv_wr32(priv, 0x40400c, 0x00000000); - nv_wr32(priv, 0x404010, 0x00000000); - nv_wr32(priv, 0x404014, 0x00000000); - nv_wr32(priv, 0x404018, 0x00000000); - nv_wr32(priv, 0x40401c, 0x00000000); - nv_wr32(priv, 0x404020, 0x00000000); - nv_wr32(priv, 0x404024, 0x00000000); - nv_wr32(priv, 0x404028, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x40402c, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x404044, 0x00000000); - nv_wr32(priv, 0x404094, 0x00000000); - nv_wr32(priv, 0x404098, 0x00000000); - nv_wr32(priv, 0x40409c, 0x00000000); - nv_wr32(priv, 0x4040a0, 0x00000000); - nv_wr32(priv, 0x4040a4, 0x00000000); - nv_wr32(priv, 0x4040a8, 0x00000000); - nv_wr32(priv, 0x4040ac, 0x00000000); - nv_wr32(priv, 0x4040b0, 0x00000000); - nv_wr32(priv, 0x4040b4, 0x00000000); - nv_wr32(priv, 0x4040b8, 0x00000000); - nv_wr32(priv, 0x4040bc, 0x00000000); - nv_wr32(priv, 0x4040c0, 0x00000000); - nv_wr32(priv, 0x4040c4, 0x00000000); - nv_wr32(priv, 0x4040c8, 0xf0000087); - nv_wr32(priv, 0x4040d0, 0x00000000); - nv_wr32(priv, 0x4040d4, 0x00000000); - nv_wr32(priv, 0x4040d8, 0x00000000); - nv_wr32(priv, 0x4040dc, 0x00000000); - nv_wr32(priv, 0x4040e0, 0x00000000); - nv_wr32(priv, 0x4040e4, 0x00000000); - nv_wr32(priv, 0x4040e8, 0x00001000); - nv_wr32(priv, 0x4040f8, 0x00000000); - nv_wr32(priv, 0x404130, 0x00000000); - nv_wr32(priv, 0x404134, 0x00000000); - nv_wr32(priv, 0x404138, 0x20000040); - nv_wr32(priv, 0x404150, 0x0000002e); - nv_wr32(priv, 0x404154, 0x00000400); - nv_wr32(priv, 0x404158, 0x00000200); - nv_wr32(priv, 0x404164, 0x00000055); - nv_wr32(priv, 0x404168, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x404174, 0x00000000); - break; - default: - BUG_ON(1); - break; + /* and the second... */ + shift = 0; + ntpcv = priv->tpc_total; + while (!(ntpcv & (1 << 4))) { + ntpcv <<= 1; + shift++; } - nv_wr32(priv, 0x404178, 0x00000000); - nv_wr32(priv, 0x40417c, 0x00000000); - for (i = 0; i < 8; i++) - nv_wr32(priv, 0x404200 + (i * 4), 0x00000000); /* subc */ -} -static void -nvc0_grctx_generate_macro(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404404, 0x00000000); - nv_wr32(priv, 0x404408, 0x00000000); - nv_wr32(priv, 0x40440c, 0x00000000); - nv_wr32(priv, 0x404410, 0x00000000); - nv_wr32(priv, 0x404414, 0x00000000); - nv_wr32(priv, 0x404418, 0x00000000); - nv_wr32(priv, 0x40441c, 0x00000000); - nv_wr32(priv, 0x404420, 0x00000000); - nv_wr32(priv, 0x404424, 0x00000000); - nv_wr32(priv, 0x404428, 0x00000000); - nv_wr32(priv, 0x40442c, 0x00000000); - nv_wr32(priv, 0x404430, 0x00000000); - nv_wr32(priv, 0x404434, 0x00000000); - nv_wr32(priv, 0x404438, 0x00000000); - nv_wr32(priv, 0x404460, 0x00000000); - nv_wr32(priv, 0x404464, 0x00000000); - nv_wr32(priv, 0x404468, 0x00ffffff); - nv_wr32(priv, 0x40446c, 0x00000000); - nv_wr32(priv, 0x404480, 0x00000001); - nv_wr32(priv, 0x404498, 0x00000001); -} - -static void -nvc0_grctx_generate_m2mf(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404604, 0x00000015); - nv_wr32(priv, 0x404608, 0x00000000); - nv_wr32(priv, 0x40460c, 0x00002e00); - nv_wr32(priv, 0x404610, 0x00000100); - nv_wr32(priv, 0x404618, 0x00000000); - nv_wr32(priv, 0x40461c, 0x00000000); - nv_wr32(priv, 0x404620, 0x00000000); - nv_wr32(priv, 0x404624, 0x00000000); - nv_wr32(priv, 0x404628, 0x00000000); - nv_wr32(priv, 0x40462c, 0x00000000); - nv_wr32(priv, 0x404630, 0x00000000); - nv_wr32(priv, 0x404634, 0x00000000); - nv_wr32(priv, 0x404638, 0x00000004); - nv_wr32(priv, 0x40463c, 0x00000000); - nv_wr32(priv, 0x404640, 0x00000000); - nv_wr32(priv, 0x404644, 0x00000000); - nv_wr32(priv, 0x404648, 0x00000000); - nv_wr32(priv, 0x40464c, 0x00000000); - nv_wr32(priv, 0x404650, 0x00000000); - nv_wr32(priv, 0x404654, 0x00000000); - nv_wr32(priv, 0x404658, 0x00000000); - nv_wr32(priv, 0x40465c, 0x007f0100); - nv_wr32(priv, 0x404660, 0x00000000); - nv_wr32(priv, 0x404664, 0x00000000); - nv_wr32(priv, 0x404668, 0x00000000); - nv_wr32(priv, 0x40466c, 0x00000000); - nv_wr32(priv, 0x404670, 0x00000000); - nv_wr32(priv, 0x404674, 0x00000000); - nv_wr32(priv, 0x404678, 0x00000000); - nv_wr32(priv, 0x40467c, 0x00000002); - nv_wr32(priv, 0x404680, 0x00000000); - nv_wr32(priv, 0x404684, 0x00000000); - nv_wr32(priv, 0x404688, 0x00000000); - nv_wr32(priv, 0x40468c, 0x00000000); - nv_wr32(priv, 0x404690, 0x00000000); - nv_wr32(priv, 0x404694, 0x00000000); - nv_wr32(priv, 0x404698, 0x00000000); - nv_wr32(priv, 0x40469c, 0x00000000); - nv_wr32(priv, 0x4046a0, 0x007f0080); - nv_wr32(priv, 0x4046a4, 0x00000000); - nv_wr32(priv, 0x4046a8, 0x00000000); - nv_wr32(priv, 0x4046ac, 0x00000000); - nv_wr32(priv, 0x4046b0, 0x00000000); - nv_wr32(priv, 0x4046b4, 0x00000000); - nv_wr32(priv, 0x4046b8, 0x00000000); - nv_wr32(priv, 0x4046bc, 0x00000000); - nv_wr32(priv, 0x4046c0, 0x00000000); - nv_wr32(priv, 0x4046c4, 0x00000000); - nv_wr32(priv, 0x4046c8, 0x00000000); - nv_wr32(priv, 0x4046cc, 0x00000000); - nv_wr32(priv, 0x4046d0, 0x00000000); - nv_wr32(priv, 0x4046d4, 0x00000000); - nv_wr32(priv, 0x4046d8, 0x00000000); - nv_wr32(priv, 0x4046dc, 0x00000000); - nv_wr32(priv, 0x4046e0, 0x00000000); - nv_wr32(priv, 0x4046e4, 0x00000000); - nv_wr32(priv, 0x4046e8, 0x00000000); - nv_wr32(priv, 0x4046f0, 0x00000000); - nv_wr32(priv, 0x4046f4, 0x00000000); -} + data2[0] = (ntpcv << 16); + data2[0] |= (shift << 21); + data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); + for (i = 1; i < 7; i++) + data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); -static void -nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404700, 0x00000000); - nv_wr32(priv, 0x404704, 0x00000000); - nv_wr32(priv, 0x404708, 0x00000000); - nv_wr32(priv, 0x40470c, 0x00000000); - nv_wr32(priv, 0x404710, 0x00000000); - nv_wr32(priv, 0x404714, 0x00000000); - nv_wr32(priv, 0x404718, 0x00000000); - nv_wr32(priv, 0x40471c, 0x00000000); - nv_wr32(priv, 0x404720, 0x00000000); - nv_wr32(priv, 0x404724, 0x00000000); - nv_wr32(priv, 0x404728, 0x00000000); - nv_wr32(priv, 0x40472c, 0x00000000); - nv_wr32(priv, 0x404730, 0x00000000); - nv_wr32(priv, 0x404734, 0x00000100); - nv_wr32(priv, 0x404738, 0x00000000); - nv_wr32(priv, 0x40473c, 0x00000000); - nv_wr32(priv, 0x404740, 0x00000000); - nv_wr32(priv, 0x404744, 0x00000000); - nv_wr32(priv, 0x404748, 0x00000000); - nv_wr32(priv, 0x40474c, 0x00000000); - nv_wr32(priv, 0x404750, 0x00000000); - nv_wr32(priv, 0x404754, 0x00000000); -} + /* GPC_BROADCAST */ + nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x418b08 + (i * 4), data[i]); -static void -nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xc1: - nv_wr32(priv, 0x405800, 0x0f8000bf); - nv_wr32(priv, 0x405830, 0x02180218); - nv_wr32(priv, 0x405834, 0x00000000); - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x405800, 0x0f8000bf); - nv_wr32(priv, 0x405830, 0x02180218); - nv_wr32(priv, 0x405834, 0x08000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x405800, 0x078000bf); - nv_wr32(priv, 0x405830, 0x02180000); - nv_wr32(priv, 0x405834, 0x00000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x405838, 0x00000000); - nv_wr32(priv, 0x405854, 0x00000000); - nv_wr32(priv, 0x405870, 0x00000001); - nv_wr32(priv, 0x405874, 0x00000001); - nv_wr32(priv, 0x405878, 0x00000001); - nv_wr32(priv, 0x40587c, 0x00000001); - nv_wr32(priv, 0x405a00, 0x00000000); - nv_wr32(priv, 0x405a04, 0x00000000); - nv_wr32(priv, 0x405a18, 0x00000000); + /* GPC_BROADCAST.TP_BROADCAST */ + nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | + priv->magic_not_rop_nr | data2[0]); + nv_wr32(priv, 0x419be4, data2[1]); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x419b00 + (i * 4), data[i]); + + /* UNK78xx */ + nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x40780c + (i * 4), data[i]); } -static void -nvc0_grctx_generate_unk60xx(struct nvc0_graph_priv *priv) +void +nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) { - nv_wr32(priv, 0x406020, 0x000103c1); - nv_wr32(priv, 0x406028, 0x00000001); - nv_wr32(priv, 0x40602c, 0x00000001); - nv_wr32(priv, 0x406030, 0x00000001); - nv_wr32(priv, 0x406034, 0x00000001); -} + u64 tpc_mask = 0, tpc_set = 0; + u8 tpcnr[GPC_MAX]; + int gpc, tpc; + int i, a, b; + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (gpc = 0; gpc < priv->gpc_nr; gpc++) + tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8); + + for (i = 0, gpc = -1, b = -1; i < 32; i++) { + a = (i * (priv->tpc_total - 1)) / 32; + if (a != b) { + b = a; + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; -static void -nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) -{ + tpc_set |= 1 << ((gpc * 8) + tpc); + } - nv_wr32(priv, 0x4064a8, 0x00000000); - nv_wr32(priv, 0x4064ac, 0x00003fff); - nv_wr32(priv, 0x4064b4, 0x00000000); - nv_wr32(priv, 0x4064b8, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x4064bc, 0x00000000); - nv_wr32(priv, 0x4064c0, 0x80140078); - nv_wr32(priv, 0x4064c4, 0x0086ffff); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; + nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); + nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); + if (priv->gpc_nr > 4) { + nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); + nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); + } } } -static void -nvc0_grctx_generate_tpbus(struct nvc0_graph_priv *priv) +void +nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) { - nv_wr32(priv, 0x407804, 0x00000023); - nv_wr32(priv, 0x40780c, 0x0a418820); - nv_wr32(priv, 0x407810, 0x062080e6); - nv_wr32(priv, 0x407814, 0x020398a4); - nv_wr32(priv, 0x407818, 0x0e629062); - nv_wr32(priv, 0x40781c, 0x0a418820); - nv_wr32(priv, 0x407820, 0x000000e6); - nv_wr32(priv, 0x4078bc, 0x00000103); -} + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; -static void -nvc0_grctx_generate_ccache(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x408000, 0x00000000); - nv_wr32(priv, 0x408004, 0x00000000); - nv_wr32(priv, 0x408008, 0x00000018); - nv_wr32(priv, 0x40800c, 0x00000000); - nv_wr32(priv, 0x408010, 0x00000000); - nv_wr32(priv, 0x408014, 0x00000069); - nv_wr32(priv, 0x408018, 0xe100e100); - nv_wr32(priv, 0x408064, 0x00000000); -} + nv_mask(priv, 0x000260, 0x00000001, 0x00000000); -static void -nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) -{ - /* ROPC_BROADCAST */ - nv_wr32(priv, 0x408800, 0x02802a3c); - nv_wr32(priv, 0x408804, 0x00000040); - switch (nv_device(priv)->chipset) { - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x408808, 0x0003e00d); - nv_wr32(priv, 0x408900, 0x3080b801); - nv_wr32(priv, 0x408904, 0x02000001); - nv_wr32(priv, 0x408908, 0x00c80929); - break; - case 0xc1: - nv_wr32(priv, 0x408808, 0x1003e005); - nv_wr32(priv, 0x408900, 0x3080b801); - nv_wr32(priv, 0x408904, 0x62000001); - nv_wr32(priv, 0x408908, 0x00c80929); - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x408808, 0x1043e005); - nv_wr32(priv, 0x408900, 0x3080b801); - nv_wr32(priv, 0x408904, 0x1043e005); - nv_wr32(priv, 0x408908, 0x00c8102f); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x408980, 0x0000011d); -} + for (i = 0; oclass->hub[i]; i++) + nvc0_graph_mmio(priv, oclass->hub[i]); + for (i = 0; oclass->gpc[i]; i++) + nvc0_graph_mmio(priv, oclass->gpc[i]); -static void -nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) -{ - int i; + nv_wr32(priv, 0x404154, 0x00000000); - /* GPC_BROADCAST */ - nv_wr32(priv, 0x418380, 0x00000016); - nv_wr32(priv, 0x418400, 0x38004e00); - nv_wr32(priv, 0x418404, 0x71e0ffff); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418408, 0x00000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x41840c, 0x00001008); - nv_wr32(priv, 0x418410, 0x0fff0fff); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418414, 0x02200fff); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418414, 0x00200fff); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418450, 0x00000000); - nv_wr32(priv, 0x418454, 0x00000000); - nv_wr32(priv, 0x418458, 0x00000000); - nv_wr32(priv, 0x41845c, 0x00000000); - nv_wr32(priv, 0x418460, 0x00000000); - nv_wr32(priv, 0x418464, 0x00000000); - nv_wr32(priv, 0x418468, 0x00000001); - nv_wr32(priv, 0x41846c, 0x00000000); - nv_wr32(priv, 0x418470, 0x00000000); - nv_wr32(priv, 0x418600, 0x0000001f); - nv_wr32(priv, 0x418684, 0x0000000f); - nv_wr32(priv, 0x418700, 0x00000002); - nv_wr32(priv, 0x418704, 0x00000080); - nv_wr32(priv, 0x418708, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x41870c, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x41870c, 0x07c80000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418710, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418800, 0x7006860a); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418800, 0x0006860a); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418808, 0x00000000); - nv_wr32(priv, 0x41880c, 0x00000000); - nv_wr32(priv, 0x418810, 0x00000000); - nv_wr32(priv, 0x418828, 0x00008442); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418830, 0x10000001); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418830, 0x00000001); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x4188d8, 0x00000008); - nv_wr32(priv, 0x4188e0, 0x01000000); - nv_wr32(priv, 0x4188e8, 0x00000000); - nv_wr32(priv, 0x4188ec, 0x00000000); - nv_wr32(priv, 0x4188f0, 0x00000000); - nv_wr32(priv, 0x4188f4, 0x00000000); - nv_wr32(priv, 0x4188f8, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc1: - nv_wr32(priv, 0x4188fc, 0x00100018); - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x4188fc, 0x20100008); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x4188fc, 0x00100000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x41891c, 0x00ff00ff); - nv_wr32(priv, 0x418924, 0x00000000); - nv_wr32(priv, 0x418928, 0x00ffff00); - nv_wr32(priv, 0x41892c, 0x0000ff00); - for (i = 0; i < 8; i++) { - nv_wr32(priv, 0x418a00 + (i * 0x20), 0x00000000); - nv_wr32(priv, 0x418a04 + (i * 0x20), 0x00000000); - nv_wr32(priv, 0x418a08 + (i * 0x20), 0x00000000); - nv_wr32(priv, 0x418a0c + (i * 0x20), 0x00010000); - nv_wr32(priv, 0x418a10 + (i * 0x20), 0x00000000); - nv_wr32(priv, 0x418a14 + (i * 0x20), 0x00000000); - nv_wr32(priv, 0x418a18 + (i * 0x20), 0x00000000); - } - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418b00, 0x00000006); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418b00, 0x00000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418b08, 0x0a418820); - nv_wr32(priv, 0x418b0c, 0x062080e6); - nv_wr32(priv, 0x418b10, 0x020398a4); - nv_wr32(priv, 0x418b14, 0x0e629062); - nv_wr32(priv, 0x418b18, 0x0a418820); - nv_wr32(priv, 0x418b1c, 0x000000e6); - nv_wr32(priv, 0x418bb8, 0x00000103); - nv_wr32(priv, 0x418c08, 0x00000001); - nv_wr32(priv, 0x418c10, 0x00000000); - nv_wr32(priv, 0x418c14, 0x00000000); - nv_wr32(priv, 0x418c18, 0x00000000); - nv_wr32(priv, 0x418c1c, 0x00000000); - nv_wr32(priv, 0x418c20, 0x00000000); - nv_wr32(priv, 0x418c24, 0x00000000); - nv_wr32(priv, 0x418c28, 0x00000000); - nv_wr32(priv, 0x418c2c, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418c6c, 0x00000001); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418c80, 0x20200004); - nv_wr32(priv, 0x418c8c, 0x00000001); - nv_wr32(priv, 0x419000, 0x00000780); - nv_wr32(priv, 0x419004, 0x00000000); - nv_wr32(priv, 0x419008, 0x00000000); - nv_wr32(priv, 0x419014, 0x00000004); -} + oclass->mods(priv, info); + oclass->unkn(priv); -static void -nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) -{ - /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x419818, 0x00000000); - nv_wr32(priv, 0x41983c, 0x00038bc7); - nv_wr32(priv, 0x419848, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419864, 0x00000129); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419864, 0x0000012a); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419888, 0x00000000); - nv_wr32(priv, 0x419a00, 0x000001f0); - nv_wr32(priv, 0x419a04, 0x00000001); - nv_wr32(priv, 0x419a08, 0x00000023); - nv_wr32(priv, 0x419a0c, 0x00020000); - nv_wr32(priv, 0x419a10, 0x00000000); - nv_wr32(priv, 0x419a14, 0x00000200); - switch (nv_device(priv)->chipset) { - case 0xc0: - break; - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419a1c, 0x00000000); - nv_wr32(priv, 0x419a20, 0x00000800); - break; - default: - BUG_ON(1); - break; - } - switch (nv_device(priv)->chipset) { - case 0xc0: - case 0xc8: - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x00419ac4, 0x0017f440); - break; - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x00419ac4, 0x0007f440); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419b00, 0x0a418820); - nv_wr32(priv, 0x419b04, 0x062080e6); - nv_wr32(priv, 0x419b08, 0x020398a4); - nv_wr32(priv, 0x419b0c, 0x0e629062); - nv_wr32(priv, 0x419b10, 0x0a418820); - nv_wr32(priv, 0x419b14, 0x000000e6); - nv_wr32(priv, 0x419bd0, 0x00900103); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419be0, 0x00400001); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419be0, 0x00000001); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419be4, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419c00, 0x0000000a); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419c00, 0x00000002); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419c04, 0x00000006); - nv_wr32(priv, 0x419c08, 0x00000002); - nv_wr32(priv, 0x419c20, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419cb0, 0x00020048); - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419c24, 0x00084210); - nv_wr32(priv, 0x419c28, 0x3cf3cf3c); - nv_wr32(priv, 0x419cb0, 0x00020048); - break; - case 0xc0: - case 0xc8: - nv_wr32(priv, 0x419cb0, 0x00060048); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419ce8, 0x00000000); - nv_wr32(priv, 0x419cf4, 0x00000183); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419d20, 0x12180000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419d20, 0x02180000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419d24, 0x00001fff); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419d44, 0x02180218); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419e04, 0x00000000); - nv_wr32(priv, 0x419e08, 0x00000000); - nv_wr32(priv, 0x419e0c, 0x00000000); - nv_wr32(priv, 0x419e10, 0x00000002); - nv_wr32(priv, 0x419e44, 0x001beff2); - nv_wr32(priv, 0x419e48, 0x00000000); - nv_wr32(priv, 0x419e4c, 0x0000000f); - nv_wr32(priv, 0x419e50, 0x00000000); - nv_wr32(priv, 0x419e54, 0x00000000); - nv_wr32(priv, 0x419e58, 0x00000000); - nv_wr32(priv, 0x419e5c, 0x00000000); - nv_wr32(priv, 0x419e60, 0x00000000); - nv_wr32(priv, 0x419e64, 0x00000000); - nv_wr32(priv, 0x419e68, 0x00000000); - nv_wr32(priv, 0x419e6c, 0x00000000); - nv_wr32(priv, 0x419e70, 0x00000000); - nv_wr32(priv, 0x419e74, 0x00000000); - nv_wr32(priv, 0x419e78, 0x00000000); - nv_wr32(priv, 0x419e7c, 0x00000000); - nv_wr32(priv, 0x419e80, 0x00000000); - nv_wr32(priv, 0x419e84, 0x00000000); - nv_wr32(priv, 0x419e88, 0x00000000); - nv_wr32(priv, 0x419e8c, 0x00000000); - nv_wr32(priv, 0x419e90, 0x00000000); - nv_wr32(priv, 0x419e98, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc0: - case 0xc8: - break; - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419ee0, 0x00010110); - break; - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419ee0, 0x00011110); - break; - default: - BUG_ON(1); - break; - } - switch (nv_device(priv)->chipset) { - case 0xc0: - case 0xc8: - nv_wr32(priv, 0x419f50, 0x00000000); - nv_wr32(priv, 0x419f54, 0x00000000); - break; - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419f30, 0x00000000); - nv_wr32(priv, 0x419f34, 0x00000000); - nv_wr32(priv, 0x419f38, 0x00000000); - nv_wr32(priv, 0x419f3c, 0x00000000); - nv_wr32(priv, 0x419f40, 0x00000000); - nv_wr32(priv, 0x419f44, 0x00000000); - nv_wr32(priv, 0x419f48, 0x00000000); - nv_wr32(priv, 0x419f4c, 0x00000000); - nv_wr32(priv, 0x419f50, 0x00000000); - nv_wr32(priv, 0x419f54, 0x00000000); - nv_wr32(priv, 0x419f58, 0x00000000); - break; - break; - default: - BUG_ON(1); - break; - } + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nvc0_grctx_generate_r4060a8(priv); + nvc0_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + nvc0_graph_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_graph_mthd(priv, oclass->mthd); + nv_mask(priv, 0x000260, 0x00000001, 0x00000001); } int nvc0_grctx_generate(struct nvc0_graph_priv *priv) { + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct nouveau_bar *bar = nouveau_bar(priv); + struct nouveau_gpuobj *chan; struct nvc0_grctx info; - int ret, i, gpc, tpc, id; - u32 fermi = nvc0_graph_class(priv); - u32 r000260, tmp; + int ret, i; - ret = nvc0_grctx_init(priv, &info); - if (ret) + /* allocate memory to for a "channel", which we'll use to generate + * the default context values + */ + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); + if (ret) { + nv_error(priv, "failed to allocate channel memory, %d\n", ret); return ret; - - r000260 = nv_rd32(priv, 0x000260); - nv_wr32(priv, 0x000260, r000260 & ~1); - nv_wr32(priv, 0x400208, 0x00000000); - - nvc0_grctx_generate_dispatch(priv); - nvc0_grctx_generate_macro(priv); - nvc0_grctx_generate_m2mf(priv); - nvc0_grctx_generate_unk47xx(priv); - nvc0_grctx_generate_shaders(priv); - nvc0_grctx_generate_unk60xx(priv); - nvc0_grctx_generate_unk64xx(priv); - nvc0_grctx_generate_tpbus(priv); - nvc0_grctx_generate_ccache(priv); - nvc0_grctx_generate_rop(priv); - nvc0_grctx_generate_gpc(priv); - nvc0_grctx_generate_tp(priv); - - nv_wr32(priv, 0x404154, 0x00000000); - - /* generate per-context mmio list data */ - mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); - mmio_list(0x408004, 0x00000000, 8, 0); - mmio_list(0x408008, 0x80000018, 0, 0); - mmio_list(0x40800c, 0x00000000, 8, 1); - mmio_list(0x408010, 0x80000000, 0, 0); - mmio_list(0x418810, 0x80000000, 12, 2); - mmio_list(0x419848, 0x10000000, 12, 2); - mmio_list(0x419004, 0x00000000, 8, 1); - mmio_list(0x419008, 0x00000000, 0, 0); - mmio_list(0x418808, 0x00000000, 8, 0); - mmio_list(0x41880c, 0x80000018, 0, 0); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xd9: - case 0xd7: - tmp = 0x02180000; - mmio_list(0x405830, 0x00000218 | tmp, 0, 0); - mmio_list(0x4064c4, 0x0086ffff, 0, 0); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - u32 reg = TPC_UNIT(gpc, tpc, 0x0520); - mmio_list(reg, 0x10000000 | tmp, 0, 0); - tmp += 0x0324; - } - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - u32 reg = TPC_UNIT(gpc, tpc, 0x0544); - mmio_list(reg, tmp, 0, 0); - tmp += 0x0324; - } - } - break; - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - tmp = 0x02180000; - mmio_list(0x405830, tmp, 0, 0); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - u32 reg = TPC_UNIT(gpc, tpc, 0x0520); - mmio_list(reg, tmp, 0, 0); - tmp += 0x0324; - } - } - break; - default: - BUG_ON(1); - break; - } - - for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); - id++; - } - - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); - } } - tmp = 0; - for (i = 0; i < priv->gpc_nr; i++) - tmp |= priv->tpc_nr[i] << (i * 4); - nv_wr32(priv, 0x406028, tmp); - nv_wr32(priv, 0x405870, tmp); - - nv_wr32(priv, 0x40602c, 0x00000000); - nv_wr32(priv, 0x405874, 0x00000000); - nv_wr32(priv, 0x406030, 0x00000000); - nv_wr32(priv, 0x405878, 0x00000000); - nv_wr32(priv, 0x406034, 0x00000000); - nv_wr32(priv, 0x40587c, 0x00000000); - - if (1) { - u8 tpcnr[GPC_MAX], data[TPC_MAX]; - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - memset(data, 0x1f, sizeof(data)); + /* PGD pointer */ + nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); + nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); + nv_wo32(chan, 0x0208, 0xffffffff); + nv_wo32(chan, 0x020c, 0x000000ff); - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; - data[tpc] = gpc; - } + /* PGT[0] pointer */ + nv_wo32(chan, 0x1000, 0x00000000); + nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); - for (i = 0; i < 4; i++) - nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); + /* identity-map the whole "channel" into its own vm */ + for (i = 0; i < chan->size / 4096; i++) { + u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; + nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); + nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); } - if (1) { - u32 data[6] = {}, data2[2] = {}; - u8 tpcnr[GPC_MAX]; - u8 shift, ntpcv; - - /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + /* context pointer (virt) */ + nv_wo32(chan, 0x0210, 0x00080004); + nv_wo32(chan, 0x0214, 0x00000000); - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; + bar->flush(bar); - data[tpc / 6] |= gpc << ((tpc % 6) * 5); - } + nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); + nv_wr32(priv, 0x100cbc, 0x80000001); + nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); - for (; tpc < 32; tpc++) - data[tpc / 6] |= 7 << ((tpc % 6) * 5); + /* setup default state for mmio list construction */ + info.priv = priv; + info.data = priv->mmio_data; + info.mmio = priv->mmio_list; + info.addr = 0x2000 + (i * 8); + info.buffer_nr = 0; - /* and the second... */ - shift = 0; - ntpcv = priv->tpc_total; - while (!(ntpcv & (1 << 4))) { - ntpcv <<= 1; - shift++; - } + /* make channel current */ + if (priv->firmware) { + nv_wr32(priv, 0x409840, 0x00000030); + nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(priv, 0x409504, 0x00000003); + if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) + nv_error(priv, "load_ctx timeout\n"); - data2[0] = (ntpcv << 16); - data2[0] |= (shift << 21); - data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); - for (i = 1; i < 7; i++) - data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); - - /* GPC_BROADCAST */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); - - /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | - priv->magic_not_rop_nr | - data2[0]); - nv_wr32(priv, 0x419be4, data2[1]); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x419b00 + (i * 4), data[i]); - - /* UNK78xx */ - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); + nv_wo32(chan, 0x8001c, 1); + nv_wo32(chan, 0x80020, 0); + nv_wo32(chan, 0x80028, 0); + nv_wo32(chan, 0x8002c, 0); + bar->flush(bar); + } else { + nv_wr32(priv, 0x409840, 0x80000000); + nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(priv, 0x409504, 0x00000001); + if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) + nv_error(priv, "HUB_SET_CHAN timeout\n"); } - if (1) { - u32 tpc_mask = 0, tpc_set = 0; - u8 tpcnr[GPC_MAX], a, b; - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) - tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8); + oclass->main(priv, &info); - for (i = 0, gpc = -1, b = -1; i < 32; i++) { - a = (i * (priv->tpc_total - 1)) / 32; - if (a != b) { - b = a; - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - tpc_set |= 1 << ((gpc * 8) + tpc); - } - - nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set); - nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask); - } - } - - nv_wr32(priv, 0x400208, 0x80000000); - - nv_icmd(priv, 0x00001000, 0x00000004); - nv_icmd(priv, 0x000000a9, 0x0000ffff); - nv_icmd(priv, 0x00000038, 0x0fac6881); - nv_icmd(priv, 0x0000003d, 0x00000001); - nv_icmd(priv, 0x000000e8, 0x00000400); - nv_icmd(priv, 0x000000e9, 0x00000400); - nv_icmd(priv, 0x000000ea, 0x00000400); - nv_icmd(priv, 0x000000eb, 0x00000400); - nv_icmd(priv, 0x000000ec, 0x00000400); - nv_icmd(priv, 0x000000ed, 0x00000400); - nv_icmd(priv, 0x000000ee, 0x00000400); - nv_icmd(priv, 0x000000ef, 0x00000400); - nv_icmd(priv, 0x00000078, 0x00000300); - nv_icmd(priv, 0x00000079, 0x00000300); - nv_icmd(priv, 0x0000007a, 0x00000300); - nv_icmd(priv, 0x0000007b, 0x00000300); - nv_icmd(priv, 0x0000007c, 0x00000300); - nv_icmd(priv, 0x0000007d, 0x00000300); - nv_icmd(priv, 0x0000007e, 0x00000300); - nv_icmd(priv, 0x0000007f, 0x00000300); - nv_icmd(priv, 0x00000050, 0x00000011); - nv_icmd(priv, 0x00000058, 0x00000008); - nv_icmd(priv, 0x00000059, 0x00000008); - nv_icmd(priv, 0x0000005a, 0x00000008); - nv_icmd(priv, 0x0000005b, 0x00000008); - nv_icmd(priv, 0x0000005c, 0x00000008); - nv_icmd(priv, 0x0000005d, 0x00000008); - nv_icmd(priv, 0x0000005e, 0x00000008); - nv_icmd(priv, 0x0000005f, 0x00000008); - nv_icmd(priv, 0x00000208, 0x00000001); - nv_icmd(priv, 0x00000209, 0x00000001); - nv_icmd(priv, 0x0000020a, 0x00000001); - nv_icmd(priv, 0x0000020b, 0x00000001); - nv_icmd(priv, 0x0000020c, 0x00000001); - nv_icmd(priv, 0x0000020d, 0x00000001); - nv_icmd(priv, 0x0000020e, 0x00000001); - nv_icmd(priv, 0x0000020f, 0x00000001); - nv_icmd(priv, 0x00000081, 0x00000001); - nv_icmd(priv, 0x00000085, 0x00000004); - nv_icmd(priv, 0x00000088, 0x00000400); - nv_icmd(priv, 0x00000090, 0x00000300); - nv_icmd(priv, 0x00000098, 0x00001001); - nv_icmd(priv, 0x000000e3, 0x00000001); - nv_icmd(priv, 0x000000da, 0x00000001); - nv_icmd(priv, 0x000000f8, 0x00000003); - nv_icmd(priv, 0x000000fa, 0x00000001); - nv_icmd(priv, 0x0000009f, 0x0000ffff); - nv_icmd(priv, 0x000000a0, 0x0000ffff); - nv_icmd(priv, 0x000000a1, 0x0000ffff); - nv_icmd(priv, 0x000000a2, 0x0000ffff); - nv_icmd(priv, 0x000000b1, 0x00000001); - nv_icmd(priv, 0x000000b2, 0x00000000); - nv_icmd(priv, 0x000000b3, 0x00000000); - nv_icmd(priv, 0x000000b4, 0x00000000); - nv_icmd(priv, 0x000000b5, 0x00000000); - nv_icmd(priv, 0x000000b6, 0x00000000); - nv_icmd(priv, 0x000000b7, 0x00000000); - nv_icmd(priv, 0x000000b8, 0x00000000); - nv_icmd(priv, 0x000000b9, 0x00000000); - nv_icmd(priv, 0x000000ba, 0x00000000); - nv_icmd(priv, 0x000000bb, 0x00000000); - nv_icmd(priv, 0x000000bc, 0x00000000); - nv_icmd(priv, 0x000000bd, 0x00000000); - nv_icmd(priv, 0x000000be, 0x00000000); - nv_icmd(priv, 0x000000bf, 0x00000000); - nv_icmd(priv, 0x000000c0, 0x00000000); - nv_icmd(priv, 0x000000c1, 0x00000000); - nv_icmd(priv, 0x000000c2, 0x00000000); - nv_icmd(priv, 0x000000c3, 0x00000000); - nv_icmd(priv, 0x000000c4, 0x00000000); - nv_icmd(priv, 0x000000c5, 0x00000000); - nv_icmd(priv, 0x000000c6, 0x00000000); - nv_icmd(priv, 0x000000c7, 0x00000000); - nv_icmd(priv, 0x000000c8, 0x00000000); - nv_icmd(priv, 0x000000c9, 0x00000000); - nv_icmd(priv, 0x000000ca, 0x00000000); - nv_icmd(priv, 0x000000cb, 0x00000000); - nv_icmd(priv, 0x000000cc, 0x00000000); - nv_icmd(priv, 0x000000cd, 0x00000000); - nv_icmd(priv, 0x000000ce, 0x00000000); - nv_icmd(priv, 0x000000cf, 0x00000000); - nv_icmd(priv, 0x000000d0, 0x00000000); - nv_icmd(priv, 0x000000d1, 0x00000000); - nv_icmd(priv, 0x000000d2, 0x00000000); - nv_icmd(priv, 0x000000d3, 0x00000000); - nv_icmd(priv, 0x000000d4, 0x00000000); - nv_icmd(priv, 0x000000d5, 0x00000000); - nv_icmd(priv, 0x000000d6, 0x00000000); - nv_icmd(priv, 0x000000d7, 0x00000000); - nv_icmd(priv, 0x000000d8, 0x00000000); - nv_icmd(priv, 0x000000d9, 0x00000000); - nv_icmd(priv, 0x00000210, 0x00000040); - nv_icmd(priv, 0x00000211, 0x00000040); - nv_icmd(priv, 0x00000212, 0x00000040); - nv_icmd(priv, 0x00000213, 0x00000040); - nv_icmd(priv, 0x00000214, 0x00000040); - nv_icmd(priv, 0x00000215, 0x00000040); - nv_icmd(priv, 0x00000216, 0x00000040); - nv_icmd(priv, 0x00000217, 0x00000040); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - for (i = 0x400; i <= 0x417; i++) - nv_icmd(priv, i, 0x00000040); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_icmd(priv, 0x00000218, 0x0000c080); - nv_icmd(priv, 0x00000219, 0x0000c080); - nv_icmd(priv, 0x0000021a, 0x0000c080); - nv_icmd(priv, 0x0000021b, 0x0000c080); - nv_icmd(priv, 0x0000021c, 0x0000c080); - nv_icmd(priv, 0x0000021d, 0x0000c080); - nv_icmd(priv, 0x0000021e, 0x0000c080); - nv_icmd(priv, 0x0000021f, 0x0000c080); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - for (i = 0x440; i <= 0x457; i++) - nv_icmd(priv, i, 0x0000c080); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_icmd(priv, 0x000000ad, 0x0000013e); - nv_icmd(priv, 0x000000e1, 0x00000010); - nv_icmd(priv, 0x00000290, 0x00000000); - nv_icmd(priv, 0x00000291, 0x00000000); - nv_icmd(priv, 0x00000292, 0x00000000); - nv_icmd(priv, 0x00000293, 0x00000000); - nv_icmd(priv, 0x00000294, 0x00000000); - nv_icmd(priv, 0x00000295, 0x00000000); - nv_icmd(priv, 0x00000296, 0x00000000); - nv_icmd(priv, 0x00000297, 0x00000000); - nv_icmd(priv, 0x00000298, 0x00000000); - nv_icmd(priv, 0x00000299, 0x00000000); - nv_icmd(priv, 0x0000029a, 0x00000000); - nv_icmd(priv, 0x0000029b, 0x00000000); - nv_icmd(priv, 0x0000029c, 0x00000000); - nv_icmd(priv, 0x0000029d, 0x00000000); - nv_icmd(priv, 0x0000029e, 0x00000000); - nv_icmd(priv, 0x0000029f, 0x00000000); - nv_icmd(priv, 0x000003b0, 0x00000000); - nv_icmd(priv, 0x000003b1, 0x00000000); - nv_icmd(priv, 0x000003b2, 0x00000000); - nv_icmd(priv, 0x000003b3, 0x00000000); - nv_icmd(priv, 0x000003b4, 0x00000000); - nv_icmd(priv, 0x000003b5, 0x00000000); - nv_icmd(priv, 0x000003b6, 0x00000000); - nv_icmd(priv, 0x000003b7, 0x00000000); - nv_icmd(priv, 0x000003b8, 0x00000000); - nv_icmd(priv, 0x000003b9, 0x00000000); - nv_icmd(priv, 0x000003ba, 0x00000000); - nv_icmd(priv, 0x000003bb, 0x00000000); - nv_icmd(priv, 0x000003bc, 0x00000000); - nv_icmd(priv, 0x000003bd, 0x00000000); - nv_icmd(priv, 0x000003be, 0x00000000); - nv_icmd(priv, 0x000003bf, 0x00000000); - nv_icmd(priv, 0x000002a0, 0x00000000); - nv_icmd(priv, 0x000002a1, 0x00000000); - nv_icmd(priv, 0x000002a2, 0x00000000); - nv_icmd(priv, 0x000002a3, 0x00000000); - nv_icmd(priv, 0x000002a4, 0x00000000); - nv_icmd(priv, 0x000002a5, 0x00000000); - nv_icmd(priv, 0x000002a6, 0x00000000); - nv_icmd(priv, 0x000002a7, 0x00000000); - nv_icmd(priv, 0x000002a8, 0x00000000); - nv_icmd(priv, 0x000002a9, 0x00000000); - nv_icmd(priv, 0x000002aa, 0x00000000); - nv_icmd(priv, 0x000002ab, 0x00000000); - nv_icmd(priv, 0x000002ac, 0x00000000); - nv_icmd(priv, 0x000002ad, 0x00000000); - nv_icmd(priv, 0x000002ae, 0x00000000); - nv_icmd(priv, 0x000002af, 0x00000000); - nv_icmd(priv, 0x00000420, 0x00000000); - nv_icmd(priv, 0x00000421, 0x00000000); - nv_icmd(priv, 0x00000422, 0x00000000); - nv_icmd(priv, 0x00000423, 0x00000000); - nv_icmd(priv, 0x00000424, 0x00000000); - nv_icmd(priv, 0x00000425, 0x00000000); - nv_icmd(priv, 0x00000426, 0x00000000); - nv_icmd(priv, 0x00000427, 0x00000000); - nv_icmd(priv, 0x00000428, 0x00000000); - nv_icmd(priv, 0x00000429, 0x00000000); - nv_icmd(priv, 0x0000042a, 0x00000000); - nv_icmd(priv, 0x0000042b, 0x00000000); - nv_icmd(priv, 0x0000042c, 0x00000000); - nv_icmd(priv, 0x0000042d, 0x00000000); - nv_icmd(priv, 0x0000042e, 0x00000000); - nv_icmd(priv, 0x0000042f, 0x00000000); - nv_icmd(priv, 0x000002b0, 0x00000000); - nv_icmd(priv, 0x000002b1, 0x00000000); - nv_icmd(priv, 0x000002b2, 0x00000000); - nv_icmd(priv, 0x000002b3, 0x00000000); - nv_icmd(priv, 0x000002b4, 0x00000000); - nv_icmd(priv, 0x000002b5, 0x00000000); - nv_icmd(priv, 0x000002b6, 0x00000000); - nv_icmd(priv, 0x000002b7, 0x00000000); - nv_icmd(priv, 0x000002b8, 0x00000000); - nv_icmd(priv, 0x000002b9, 0x00000000); - nv_icmd(priv, 0x000002ba, 0x00000000); - nv_icmd(priv, 0x000002bb, 0x00000000); - nv_icmd(priv, 0x000002bc, 0x00000000); - nv_icmd(priv, 0x000002bd, 0x00000000); - nv_icmd(priv, 0x000002be, 0x00000000); - nv_icmd(priv, 0x000002bf, 0x00000000); - nv_icmd(priv, 0x00000430, 0x00000000); - nv_icmd(priv, 0x00000431, 0x00000000); - nv_icmd(priv, 0x00000432, 0x00000000); - nv_icmd(priv, 0x00000433, 0x00000000); - nv_icmd(priv, 0x00000434, 0x00000000); - nv_icmd(priv, 0x00000435, 0x00000000); - nv_icmd(priv, 0x00000436, 0x00000000); - nv_icmd(priv, 0x00000437, 0x00000000); - nv_icmd(priv, 0x00000438, 0x00000000); - nv_icmd(priv, 0x00000439, 0x00000000); - nv_icmd(priv, 0x0000043a, 0x00000000); - nv_icmd(priv, 0x0000043b, 0x00000000); - nv_icmd(priv, 0x0000043c, 0x00000000); - nv_icmd(priv, 0x0000043d, 0x00000000); - nv_icmd(priv, 0x0000043e, 0x00000000); - nv_icmd(priv, 0x0000043f, 0x00000000); - nv_icmd(priv, 0x000002c0, 0x00000000); - nv_icmd(priv, 0x000002c1, 0x00000000); - nv_icmd(priv, 0x000002c2, 0x00000000); - nv_icmd(priv, 0x000002c3, 0x00000000); - nv_icmd(priv, 0x000002c4, 0x00000000); - nv_icmd(priv, 0x000002c5, 0x00000000); - nv_icmd(priv, 0x000002c6, 0x00000000); - nv_icmd(priv, 0x000002c7, 0x00000000); - nv_icmd(priv, 0x000002c8, 0x00000000); - nv_icmd(priv, 0x000002c9, 0x00000000); - nv_icmd(priv, 0x000002ca, 0x00000000); - nv_icmd(priv, 0x000002cb, 0x00000000); - nv_icmd(priv, 0x000002cc, 0x00000000); - nv_icmd(priv, 0x000002cd, 0x00000000); - nv_icmd(priv, 0x000002ce, 0x00000000); - nv_icmd(priv, 0x000002cf, 0x00000000); - nv_icmd(priv, 0x000004d0, 0x00000000); - nv_icmd(priv, 0x000004d1, 0x00000000); - nv_icmd(priv, 0x000004d2, 0x00000000); - nv_icmd(priv, 0x000004d3, 0x00000000); - nv_icmd(priv, 0x000004d4, 0x00000000); - nv_icmd(priv, 0x000004d5, 0x00000000); - nv_icmd(priv, 0x000004d6, 0x00000000); - nv_icmd(priv, 0x000004d7, 0x00000000); - nv_icmd(priv, 0x000004d8, 0x00000000); - nv_icmd(priv, 0x000004d9, 0x00000000); - nv_icmd(priv, 0x000004da, 0x00000000); - nv_icmd(priv, 0x000004db, 0x00000000); - nv_icmd(priv, 0x000004dc, 0x00000000); - nv_icmd(priv, 0x000004dd, 0x00000000); - nv_icmd(priv, 0x000004de, 0x00000000); - nv_icmd(priv, 0x000004df, 0x00000000); - nv_icmd(priv, 0x00000720, 0x00000000); - nv_icmd(priv, 0x00000721, 0x00000000); - nv_icmd(priv, 0x00000722, 0x00000000); - nv_icmd(priv, 0x00000723, 0x00000000); - nv_icmd(priv, 0x00000724, 0x00000000); - nv_icmd(priv, 0x00000725, 0x00000000); - nv_icmd(priv, 0x00000726, 0x00000000); - nv_icmd(priv, 0x00000727, 0x00000000); - nv_icmd(priv, 0x00000728, 0x00000000); - nv_icmd(priv, 0x00000729, 0x00000000); - nv_icmd(priv, 0x0000072a, 0x00000000); - nv_icmd(priv, 0x0000072b, 0x00000000); - nv_icmd(priv, 0x0000072c, 0x00000000); - nv_icmd(priv, 0x0000072d, 0x00000000); - nv_icmd(priv, 0x0000072e, 0x00000000); - nv_icmd(priv, 0x0000072f, 0x00000000); - nv_icmd(priv, 0x000008c0, 0x00000000); - nv_icmd(priv, 0x000008c1, 0x00000000); - nv_icmd(priv, 0x000008c2, 0x00000000); - nv_icmd(priv, 0x000008c3, 0x00000000); - nv_icmd(priv, 0x000008c4, 0x00000000); - nv_icmd(priv, 0x000008c5, 0x00000000); - nv_icmd(priv, 0x000008c6, 0x00000000); - nv_icmd(priv, 0x000008c7, 0x00000000); - nv_icmd(priv, 0x000008c8, 0x00000000); - nv_icmd(priv, 0x000008c9, 0x00000000); - nv_icmd(priv, 0x000008ca, 0x00000000); - nv_icmd(priv, 0x000008cb, 0x00000000); - nv_icmd(priv, 0x000008cc, 0x00000000); - nv_icmd(priv, 0x000008cd, 0x00000000); - nv_icmd(priv, 0x000008ce, 0x00000000); - nv_icmd(priv, 0x000008cf, 0x00000000); - nv_icmd(priv, 0x00000890, 0x00000000); - nv_icmd(priv, 0x00000891, 0x00000000); - nv_icmd(priv, 0x00000892, 0x00000000); - nv_icmd(priv, 0x00000893, 0x00000000); - nv_icmd(priv, 0x00000894, 0x00000000); - nv_icmd(priv, 0x00000895, 0x00000000); - nv_icmd(priv, 0x00000896, 0x00000000); - nv_icmd(priv, 0x00000897, 0x00000000); - nv_icmd(priv, 0x00000898, 0x00000000); - nv_icmd(priv, 0x00000899, 0x00000000); - nv_icmd(priv, 0x0000089a, 0x00000000); - nv_icmd(priv, 0x0000089b, 0x00000000); - nv_icmd(priv, 0x0000089c, 0x00000000); - nv_icmd(priv, 0x0000089d, 0x00000000); - nv_icmd(priv, 0x0000089e, 0x00000000); - nv_icmd(priv, 0x0000089f, 0x00000000); - nv_icmd(priv, 0x000008e0, 0x00000000); - nv_icmd(priv, 0x000008e1, 0x00000000); - nv_icmd(priv, 0x000008e2, 0x00000000); - nv_icmd(priv, 0x000008e3, 0x00000000); - nv_icmd(priv, 0x000008e4, 0x00000000); - nv_icmd(priv, 0x000008e5, 0x00000000); - nv_icmd(priv, 0x000008e6, 0x00000000); - nv_icmd(priv, 0x000008e7, 0x00000000); - nv_icmd(priv, 0x000008e8, 0x00000000); - nv_icmd(priv, 0x000008e9, 0x00000000); - nv_icmd(priv, 0x000008ea, 0x00000000); - nv_icmd(priv, 0x000008eb, 0x00000000); - nv_icmd(priv, 0x000008ec, 0x00000000); - nv_icmd(priv, 0x000008ed, 0x00000000); - nv_icmd(priv, 0x000008ee, 0x00000000); - nv_icmd(priv, 0x000008ef, 0x00000000); - nv_icmd(priv, 0x000008a0, 0x00000000); - nv_icmd(priv, 0x000008a1, 0x00000000); - nv_icmd(priv, 0x000008a2, 0x00000000); - nv_icmd(priv, 0x000008a3, 0x00000000); - nv_icmd(priv, 0x000008a4, 0x00000000); - nv_icmd(priv, 0x000008a5, 0x00000000); - nv_icmd(priv, 0x000008a6, 0x00000000); - nv_icmd(priv, 0x000008a7, 0x00000000); - nv_icmd(priv, 0x000008a8, 0x00000000); - nv_icmd(priv, 0x000008a9, 0x00000000); - nv_icmd(priv, 0x000008aa, 0x00000000); - nv_icmd(priv, 0x000008ab, 0x00000000); - nv_icmd(priv, 0x000008ac, 0x00000000); - nv_icmd(priv, 0x000008ad, 0x00000000); - nv_icmd(priv, 0x000008ae, 0x00000000); - nv_icmd(priv, 0x000008af, 0x00000000); - nv_icmd(priv, 0x000008f0, 0x00000000); - nv_icmd(priv, 0x000008f1, 0x00000000); - nv_icmd(priv, 0x000008f2, 0x00000000); - nv_icmd(priv, 0x000008f3, 0x00000000); - nv_icmd(priv, 0x000008f4, 0x00000000); - nv_icmd(priv, 0x000008f5, 0x00000000); - nv_icmd(priv, 0x000008f6, 0x00000000); - nv_icmd(priv, 0x000008f7, 0x00000000); - nv_icmd(priv, 0x000008f8, 0x00000000); - nv_icmd(priv, 0x000008f9, 0x00000000); - nv_icmd(priv, 0x000008fa, 0x00000000); - nv_icmd(priv, 0x000008fb, 0x00000000); - nv_icmd(priv, 0x000008fc, 0x00000000); - nv_icmd(priv, 0x000008fd, 0x00000000); - nv_icmd(priv, 0x000008fe, 0x00000000); - nv_icmd(priv, 0x000008ff, 0x00000000); - nv_icmd(priv, 0x0000094c, 0x000000ff); - nv_icmd(priv, 0x0000094d, 0xffffffff); - nv_icmd(priv, 0x0000094e, 0x00000002); - nv_icmd(priv, 0x000002ec, 0x00000001); - nv_icmd(priv, 0x00000303, 0x00000001); - nv_icmd(priv, 0x000002e6, 0x00000001); - nv_icmd(priv, 0x00000466, 0x00000052); - nv_icmd(priv, 0x00000301, 0x3f800000); - nv_icmd(priv, 0x00000304, 0x30201000); - nv_icmd(priv, 0x00000305, 0x70605040); - nv_icmd(priv, 0x00000306, 0xb8a89888); - nv_icmd(priv, 0x00000307, 0xf8e8d8c8); - nv_icmd(priv, 0x0000030a, 0x00ffff00); - nv_icmd(priv, 0x0000030b, 0x0000001a); - nv_icmd(priv, 0x0000030c, 0x00000001); - nv_icmd(priv, 0x00000318, 0x00000001); - nv_icmd(priv, 0x00000340, 0x00000000); - nv_icmd(priv, 0x00000375, 0x00000001); - nv_icmd(priv, 0x00000351, 0x00000100); - nv_icmd(priv, 0x0000037d, 0x00000006); - nv_icmd(priv, 0x000003a0, 0x00000002); - nv_icmd(priv, 0x000003aa, 0x00000001); - nv_icmd(priv, 0x000003a9, 0x00000001); - nv_icmd(priv, 0x00000380, 0x00000001); - nv_icmd(priv, 0x00000360, 0x00000040); - nv_icmd(priv, 0x00000366, 0x00000000); - nv_icmd(priv, 0x00000367, 0x00000000); - nv_icmd(priv, 0x00000368, 0x00001fff); - nv_icmd(priv, 0x00000370, 0x00000000); - nv_icmd(priv, 0x00000371, 0x00000000); - nv_icmd(priv, 0x00000372, 0x003fffff); - nv_icmd(priv, 0x0000037a, 0x00000012); - nv_icmd(priv, 0x000005e0, 0x00000022); - nv_icmd(priv, 0x000005e1, 0x00000022); - nv_icmd(priv, 0x000005e2, 0x00000022); - nv_icmd(priv, 0x000005e3, 0x00000022); - nv_icmd(priv, 0x000005e4, 0x00000022); - nv_icmd(priv, 0x00000619, 0x00000003); - nv_icmd(priv, 0x00000811, 0x00000003); - nv_icmd(priv, 0x00000812, 0x00000004); - nv_icmd(priv, 0x00000813, 0x00000006); - nv_icmd(priv, 0x00000814, 0x00000008); - nv_icmd(priv, 0x00000815, 0x0000000b); - nv_icmd(priv, 0x00000800, 0x00000001); - nv_icmd(priv, 0x00000801, 0x00000001); - nv_icmd(priv, 0x00000802, 0x00000001); - nv_icmd(priv, 0x00000803, 0x00000001); - nv_icmd(priv, 0x00000804, 0x00000001); - nv_icmd(priv, 0x00000805, 0x00000001); - nv_icmd(priv, 0x00000632, 0x00000001); - nv_icmd(priv, 0x00000633, 0x00000002); - nv_icmd(priv, 0x00000634, 0x00000003); - nv_icmd(priv, 0x00000635, 0x00000004); - nv_icmd(priv, 0x00000654, 0x3f800000); - nv_icmd(priv, 0x00000657, 0x3f800000); - nv_icmd(priv, 0x00000655, 0x3f800000); - nv_icmd(priv, 0x00000656, 0x3f800000); - nv_icmd(priv, 0x000006cd, 0x3f800000); - nv_icmd(priv, 0x000007f5, 0x3f800000); - nv_icmd(priv, 0x000007dc, 0x39291909); - nv_icmd(priv, 0x000007dd, 0x79695949); - nv_icmd(priv, 0x000007de, 0xb9a99989); - nv_icmd(priv, 0x000007df, 0xf9e9d9c9); - nv_icmd(priv, 0x000007e8, 0x00003210); - nv_icmd(priv, 0x000007e9, 0x00007654); - nv_icmd(priv, 0x000007ea, 0x00000098); - nv_icmd(priv, 0x000007ec, 0x39291909); - nv_icmd(priv, 0x000007ed, 0x79695949); - nv_icmd(priv, 0x000007ee, 0xb9a99989); - nv_icmd(priv, 0x000007ef, 0xf9e9d9c9); - nv_icmd(priv, 0x000007f0, 0x00003210); - nv_icmd(priv, 0x000007f1, 0x00007654); - nv_icmd(priv, 0x000007f2, 0x00000098); - nv_icmd(priv, 0x000005a5, 0x00000001); - nv_icmd(priv, 0x00000980, 0x00000000); - nv_icmd(priv, 0x00000981, 0x00000000); - nv_icmd(priv, 0x00000982, 0x00000000); - nv_icmd(priv, 0x00000983, 0x00000000); - nv_icmd(priv, 0x00000984, 0x00000000); - nv_icmd(priv, 0x00000985, 0x00000000); - nv_icmd(priv, 0x00000986, 0x00000000); - nv_icmd(priv, 0x00000987, 0x00000000); - nv_icmd(priv, 0x00000988, 0x00000000); - nv_icmd(priv, 0x00000989, 0x00000000); - nv_icmd(priv, 0x0000098a, 0x00000000); - nv_icmd(priv, 0x0000098b, 0x00000000); - nv_icmd(priv, 0x0000098c, 0x00000000); - nv_icmd(priv, 0x0000098d, 0x00000000); - nv_icmd(priv, 0x0000098e, 0x00000000); - nv_icmd(priv, 0x0000098f, 0x00000000); - nv_icmd(priv, 0x00000990, 0x00000000); - nv_icmd(priv, 0x00000991, 0x00000000); - nv_icmd(priv, 0x00000992, 0x00000000); - nv_icmd(priv, 0x00000993, 0x00000000); - nv_icmd(priv, 0x00000994, 0x00000000); - nv_icmd(priv, 0x00000995, 0x00000000); - nv_icmd(priv, 0x00000996, 0x00000000); - nv_icmd(priv, 0x00000997, 0x00000000); - nv_icmd(priv, 0x00000998, 0x00000000); - nv_icmd(priv, 0x00000999, 0x00000000); - nv_icmd(priv, 0x0000099a, 0x00000000); - nv_icmd(priv, 0x0000099b, 0x00000000); - nv_icmd(priv, 0x0000099c, 0x00000000); - nv_icmd(priv, 0x0000099d, 0x00000000); - nv_icmd(priv, 0x0000099e, 0x00000000); - nv_icmd(priv, 0x0000099f, 0x00000000); - nv_icmd(priv, 0x000009a0, 0x00000000); - nv_icmd(priv, 0x000009a1, 0x00000000); - nv_icmd(priv, 0x000009a2, 0x00000000); - nv_icmd(priv, 0x000009a3, 0x00000000); - nv_icmd(priv, 0x000009a4, 0x00000000); - nv_icmd(priv, 0x000009a5, 0x00000000); - nv_icmd(priv, 0x000009a6, 0x00000000); - nv_icmd(priv, 0x000009a7, 0x00000000); - nv_icmd(priv, 0x000009a8, 0x00000000); - nv_icmd(priv, 0x000009a9, 0x00000000); - nv_icmd(priv, 0x000009aa, 0x00000000); - nv_icmd(priv, 0x000009ab, 0x00000000); - nv_icmd(priv, 0x000009ac, 0x00000000); - nv_icmd(priv, 0x000009ad, 0x00000000); - nv_icmd(priv, 0x000009ae, 0x00000000); - nv_icmd(priv, 0x000009af, 0x00000000); - nv_icmd(priv, 0x000009b0, 0x00000000); - nv_icmd(priv, 0x000009b1, 0x00000000); - nv_icmd(priv, 0x000009b2, 0x00000000); - nv_icmd(priv, 0x000009b3, 0x00000000); - nv_icmd(priv, 0x000009b4, 0x00000000); - nv_icmd(priv, 0x000009b5, 0x00000000); - nv_icmd(priv, 0x000009b6, 0x00000000); - nv_icmd(priv, 0x000009b7, 0x00000000); - nv_icmd(priv, 0x000009b8, 0x00000000); - nv_icmd(priv, 0x000009b9, 0x00000000); - nv_icmd(priv, 0x000009ba, 0x00000000); - nv_icmd(priv, 0x000009bb, 0x00000000); - nv_icmd(priv, 0x000009bc, 0x00000000); - nv_icmd(priv, 0x000009bd, 0x00000000); - nv_icmd(priv, 0x000009be, 0x00000000); - nv_icmd(priv, 0x000009bf, 0x00000000); - nv_icmd(priv, 0x000009c0, 0x00000000); - nv_icmd(priv, 0x000009c1, 0x00000000); - nv_icmd(priv, 0x000009c2, 0x00000000); - nv_icmd(priv, 0x000009c3, 0x00000000); - nv_icmd(priv, 0x000009c4, 0x00000000); - nv_icmd(priv, 0x000009c5, 0x00000000); - nv_icmd(priv, 0x000009c6, 0x00000000); - nv_icmd(priv, 0x000009c7, 0x00000000); - nv_icmd(priv, 0x000009c8, 0x00000000); - nv_icmd(priv, 0x000009c9, 0x00000000); - nv_icmd(priv, 0x000009ca, 0x00000000); - nv_icmd(priv, 0x000009cb, 0x00000000); - nv_icmd(priv, 0x000009cc, 0x00000000); - nv_icmd(priv, 0x000009cd, 0x00000000); - nv_icmd(priv, 0x000009ce, 0x00000000); - nv_icmd(priv, 0x000009cf, 0x00000000); - nv_icmd(priv, 0x000009d0, 0x00000000); - nv_icmd(priv, 0x000009d1, 0x00000000); - nv_icmd(priv, 0x000009d2, 0x00000000); - nv_icmd(priv, 0x000009d3, 0x00000000); - nv_icmd(priv, 0x000009d4, 0x00000000); - nv_icmd(priv, 0x000009d5, 0x00000000); - nv_icmd(priv, 0x000009d6, 0x00000000); - nv_icmd(priv, 0x000009d7, 0x00000000); - nv_icmd(priv, 0x000009d8, 0x00000000); - nv_icmd(priv, 0x000009d9, 0x00000000); - nv_icmd(priv, 0x000009da, 0x00000000); - nv_icmd(priv, 0x000009db, 0x00000000); - nv_icmd(priv, 0x000009dc, 0x00000000); - nv_icmd(priv, 0x000009dd, 0x00000000); - nv_icmd(priv, 0x000009de, 0x00000000); - nv_icmd(priv, 0x000009df, 0x00000000); - nv_icmd(priv, 0x000009e0, 0x00000000); - nv_icmd(priv, 0x000009e1, 0x00000000); - nv_icmd(priv, 0x000009e2, 0x00000000); - nv_icmd(priv, 0x000009e3, 0x00000000); - nv_icmd(priv, 0x000009e4, 0x00000000); - nv_icmd(priv, 0x000009e5, 0x00000000); - nv_icmd(priv, 0x000009e6, 0x00000000); - nv_icmd(priv, 0x000009e7, 0x00000000); - nv_icmd(priv, 0x000009e8, 0x00000000); - nv_icmd(priv, 0x000009e9, 0x00000000); - nv_icmd(priv, 0x000009ea, 0x00000000); - nv_icmd(priv, 0x000009eb, 0x00000000); - nv_icmd(priv, 0x000009ec, 0x00000000); - nv_icmd(priv, 0x000009ed, 0x00000000); - nv_icmd(priv, 0x000009ee, 0x00000000); - nv_icmd(priv, 0x000009ef, 0x00000000); - nv_icmd(priv, 0x000009f0, 0x00000000); - nv_icmd(priv, 0x000009f1, 0x00000000); - nv_icmd(priv, 0x000009f2, 0x00000000); - nv_icmd(priv, 0x000009f3, 0x00000000); - nv_icmd(priv, 0x000009f4, 0x00000000); - nv_icmd(priv, 0x000009f5, 0x00000000); - nv_icmd(priv, 0x000009f6, 0x00000000); - nv_icmd(priv, 0x000009f7, 0x00000000); - nv_icmd(priv, 0x000009f8, 0x00000000); - nv_icmd(priv, 0x000009f9, 0x00000000); - nv_icmd(priv, 0x000009fa, 0x00000000); - nv_icmd(priv, 0x000009fb, 0x00000000); - nv_icmd(priv, 0x000009fc, 0x00000000); - nv_icmd(priv, 0x000009fd, 0x00000000); - nv_icmd(priv, 0x000009fe, 0x00000000); - nv_icmd(priv, 0x000009ff, 0x00000000); - nv_icmd(priv, 0x00000468, 0x00000004); - nv_icmd(priv, 0x0000046c, 0x00000001); - nv_icmd(priv, 0x00000470, 0x00000000); - nv_icmd(priv, 0x00000471, 0x00000000); - nv_icmd(priv, 0x00000472, 0x00000000); - nv_icmd(priv, 0x00000473, 0x00000000); - nv_icmd(priv, 0x00000474, 0x00000000); - nv_icmd(priv, 0x00000475, 0x00000000); - nv_icmd(priv, 0x00000476, 0x00000000); - nv_icmd(priv, 0x00000477, 0x00000000); - nv_icmd(priv, 0x00000478, 0x00000000); - nv_icmd(priv, 0x00000479, 0x00000000); - nv_icmd(priv, 0x0000047a, 0x00000000); - nv_icmd(priv, 0x0000047b, 0x00000000); - nv_icmd(priv, 0x0000047c, 0x00000000); - nv_icmd(priv, 0x0000047d, 0x00000000); - nv_icmd(priv, 0x0000047e, 0x00000000); - nv_icmd(priv, 0x0000047f, 0x00000000); - nv_icmd(priv, 0x00000480, 0x00000000); - nv_icmd(priv, 0x00000481, 0x00000000); - nv_icmd(priv, 0x00000482, 0x00000000); - nv_icmd(priv, 0x00000483, 0x00000000); - nv_icmd(priv, 0x00000484, 0x00000000); - nv_icmd(priv, 0x00000485, 0x00000000); - nv_icmd(priv, 0x00000486, 0x00000000); - nv_icmd(priv, 0x00000487, 0x00000000); - nv_icmd(priv, 0x00000488, 0x00000000); - nv_icmd(priv, 0x00000489, 0x00000000); - nv_icmd(priv, 0x0000048a, 0x00000000); - nv_icmd(priv, 0x0000048b, 0x00000000); - nv_icmd(priv, 0x0000048c, 0x00000000); - nv_icmd(priv, 0x0000048d, 0x00000000); - nv_icmd(priv, 0x0000048e, 0x00000000); - nv_icmd(priv, 0x0000048f, 0x00000000); - nv_icmd(priv, 0x00000490, 0x00000000); - nv_icmd(priv, 0x00000491, 0x00000000); - nv_icmd(priv, 0x00000492, 0x00000000); - nv_icmd(priv, 0x00000493, 0x00000000); - nv_icmd(priv, 0x00000494, 0x00000000); - nv_icmd(priv, 0x00000495, 0x00000000); - nv_icmd(priv, 0x00000496, 0x00000000); - nv_icmd(priv, 0x00000497, 0x00000000); - nv_icmd(priv, 0x00000498, 0x00000000); - nv_icmd(priv, 0x00000499, 0x00000000); - nv_icmd(priv, 0x0000049a, 0x00000000); - nv_icmd(priv, 0x0000049b, 0x00000000); - nv_icmd(priv, 0x0000049c, 0x00000000); - nv_icmd(priv, 0x0000049d, 0x00000000); - nv_icmd(priv, 0x0000049e, 0x00000000); - nv_icmd(priv, 0x0000049f, 0x00000000); - nv_icmd(priv, 0x000004a0, 0x00000000); - nv_icmd(priv, 0x000004a1, 0x00000000); - nv_icmd(priv, 0x000004a2, 0x00000000); - nv_icmd(priv, 0x000004a3, 0x00000000); - nv_icmd(priv, 0x000004a4, 0x00000000); - nv_icmd(priv, 0x000004a5, 0x00000000); - nv_icmd(priv, 0x000004a6, 0x00000000); - nv_icmd(priv, 0x000004a7, 0x00000000); - nv_icmd(priv, 0x000004a8, 0x00000000); - nv_icmd(priv, 0x000004a9, 0x00000000); - nv_icmd(priv, 0x000004aa, 0x00000000); - nv_icmd(priv, 0x000004ab, 0x00000000); - nv_icmd(priv, 0x000004ac, 0x00000000); - nv_icmd(priv, 0x000004ad, 0x00000000); - nv_icmd(priv, 0x000004ae, 0x00000000); - nv_icmd(priv, 0x000004af, 0x00000000); - nv_icmd(priv, 0x000004b0, 0x00000000); - nv_icmd(priv, 0x000004b1, 0x00000000); - nv_icmd(priv, 0x000004b2, 0x00000000); - nv_icmd(priv, 0x000004b3, 0x00000000); - nv_icmd(priv, 0x000004b4, 0x00000000); - nv_icmd(priv, 0x000004b5, 0x00000000); - nv_icmd(priv, 0x000004b6, 0x00000000); - nv_icmd(priv, 0x000004b7, 0x00000000); - nv_icmd(priv, 0x000004b8, 0x00000000); - nv_icmd(priv, 0x000004b9, 0x00000000); - nv_icmd(priv, 0x000004ba, 0x00000000); - nv_icmd(priv, 0x000004bb, 0x00000000); - nv_icmd(priv, 0x000004bc, 0x00000000); - nv_icmd(priv, 0x000004bd, 0x00000000); - nv_icmd(priv, 0x000004be, 0x00000000); - nv_icmd(priv, 0x000004bf, 0x00000000); - nv_icmd(priv, 0x000004c0, 0x00000000); - nv_icmd(priv, 0x000004c1, 0x00000000); - nv_icmd(priv, 0x000004c2, 0x00000000); - nv_icmd(priv, 0x000004c3, 0x00000000); - nv_icmd(priv, 0x000004c4, 0x00000000); - nv_icmd(priv, 0x000004c5, 0x00000000); - nv_icmd(priv, 0x000004c6, 0x00000000); - nv_icmd(priv, 0x000004c7, 0x00000000); - nv_icmd(priv, 0x000004c8, 0x00000000); - nv_icmd(priv, 0x000004c9, 0x00000000); - nv_icmd(priv, 0x000004ca, 0x00000000); - nv_icmd(priv, 0x000004cb, 0x00000000); - nv_icmd(priv, 0x000004cc, 0x00000000); - nv_icmd(priv, 0x000004cd, 0x00000000); - nv_icmd(priv, 0x000004ce, 0x00000000); - nv_icmd(priv, 0x000004cf, 0x00000000); - nv_icmd(priv, 0x00000510, 0x3f800000); - nv_icmd(priv, 0x00000511, 0x3f800000); - nv_icmd(priv, 0x00000512, 0x3f800000); - nv_icmd(priv, 0x00000513, 0x3f800000); - nv_icmd(priv, 0x00000514, 0x3f800000); - nv_icmd(priv, 0x00000515, 0x3f800000); - nv_icmd(priv, 0x00000516, 0x3f800000); - nv_icmd(priv, 0x00000517, 0x3f800000); - nv_icmd(priv, 0x00000518, 0x3f800000); - nv_icmd(priv, 0x00000519, 0x3f800000); - nv_icmd(priv, 0x0000051a, 0x3f800000); - nv_icmd(priv, 0x0000051b, 0x3f800000); - nv_icmd(priv, 0x0000051c, 0x3f800000); - nv_icmd(priv, 0x0000051d, 0x3f800000); - nv_icmd(priv, 0x0000051e, 0x3f800000); - nv_icmd(priv, 0x0000051f, 0x3f800000); - nv_icmd(priv, 0x00000520, 0x000002b6); - nv_icmd(priv, 0x00000529, 0x00000001); - nv_icmd(priv, 0x00000530, 0xffff0000); - nv_icmd(priv, 0x00000531, 0xffff0000); - nv_icmd(priv, 0x00000532, 0xffff0000); - nv_icmd(priv, 0x00000533, 0xffff0000); - nv_icmd(priv, 0x00000534, 0xffff0000); - nv_icmd(priv, 0x00000535, 0xffff0000); - nv_icmd(priv, 0x00000536, 0xffff0000); - nv_icmd(priv, 0x00000537, 0xffff0000); - nv_icmd(priv, 0x00000538, 0xffff0000); - nv_icmd(priv, 0x00000539, 0xffff0000); - nv_icmd(priv, 0x0000053a, 0xffff0000); - nv_icmd(priv, 0x0000053b, 0xffff0000); - nv_icmd(priv, 0x0000053c, 0xffff0000); - nv_icmd(priv, 0x0000053d, 0xffff0000); - nv_icmd(priv, 0x0000053e, 0xffff0000); - nv_icmd(priv, 0x0000053f, 0xffff0000); - nv_icmd(priv, 0x00000585, 0x0000003f); - nv_icmd(priv, 0x00000576, 0x00000003); - switch (nv_device(priv)->chipset) { - case 0xc1: - case 0xc8: - case 0xd9: - case 0xd7: - nv_icmd(priv, 0x0000057b, 0x00000059); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_icmd(priv, 0x00000586, 0x00000040); - nv_icmd(priv, 0x00000582, 0x00000080); - nv_icmd(priv, 0x00000583, 0x00000080); - nv_icmd(priv, 0x000005c2, 0x00000001); - nv_icmd(priv, 0x00000638, 0x00000001); - nv_icmd(priv, 0x00000639, 0x00000001); - nv_icmd(priv, 0x0000063a, 0x00000002); - nv_icmd(priv, 0x0000063b, 0x00000001); - nv_icmd(priv, 0x0000063c, 0x00000001); - nv_icmd(priv, 0x0000063d, 0x00000002); - nv_icmd(priv, 0x0000063e, 0x00000001); - nv_icmd(priv, 0x000008b8, 0x00000001); - nv_icmd(priv, 0x000008b9, 0x00000001); - nv_icmd(priv, 0x000008ba, 0x00000001); - nv_icmd(priv, 0x000008bb, 0x00000001); - nv_icmd(priv, 0x000008bc, 0x00000001); - nv_icmd(priv, 0x000008bd, 0x00000001); - nv_icmd(priv, 0x000008be, 0x00000001); - nv_icmd(priv, 0x000008bf, 0x00000001); - nv_icmd(priv, 0x00000900, 0x00000001); - nv_icmd(priv, 0x00000901, 0x00000001); - nv_icmd(priv, 0x00000902, 0x00000001); - nv_icmd(priv, 0x00000903, 0x00000001); - nv_icmd(priv, 0x00000904, 0x00000001); - nv_icmd(priv, 0x00000905, 0x00000001); - nv_icmd(priv, 0x00000906, 0x00000001); - nv_icmd(priv, 0x00000907, 0x00000001); - nv_icmd(priv, 0x00000908, 0x00000002); - nv_icmd(priv, 0x00000909, 0x00000002); - nv_icmd(priv, 0x0000090a, 0x00000002); - nv_icmd(priv, 0x0000090b, 0x00000002); - nv_icmd(priv, 0x0000090c, 0x00000002); - nv_icmd(priv, 0x0000090d, 0x00000002); - nv_icmd(priv, 0x0000090e, 0x00000002); - nv_icmd(priv, 0x0000090f, 0x00000002); - nv_icmd(priv, 0x00000910, 0x00000001); - nv_icmd(priv, 0x00000911, 0x00000001); - nv_icmd(priv, 0x00000912, 0x00000001); - nv_icmd(priv, 0x00000913, 0x00000001); - nv_icmd(priv, 0x00000914, 0x00000001); - nv_icmd(priv, 0x00000915, 0x00000001); - nv_icmd(priv, 0x00000916, 0x00000001); - nv_icmd(priv, 0x00000917, 0x00000001); - nv_icmd(priv, 0x00000918, 0x00000001); - nv_icmd(priv, 0x00000919, 0x00000001); - nv_icmd(priv, 0x0000091a, 0x00000001); - nv_icmd(priv, 0x0000091b, 0x00000001); - nv_icmd(priv, 0x0000091c, 0x00000001); - nv_icmd(priv, 0x0000091d, 0x00000001); - nv_icmd(priv, 0x0000091e, 0x00000001); - nv_icmd(priv, 0x0000091f, 0x00000001); - nv_icmd(priv, 0x00000920, 0x00000002); - nv_icmd(priv, 0x00000921, 0x00000002); - nv_icmd(priv, 0x00000922, 0x00000002); - nv_icmd(priv, 0x00000923, 0x00000002); - nv_icmd(priv, 0x00000924, 0x00000002); - nv_icmd(priv, 0x00000925, 0x00000002); - nv_icmd(priv, 0x00000926, 0x00000002); - nv_icmd(priv, 0x00000927, 0x00000002); - nv_icmd(priv, 0x00000928, 0x00000001); - nv_icmd(priv, 0x00000929, 0x00000001); - nv_icmd(priv, 0x0000092a, 0x00000001); - nv_icmd(priv, 0x0000092b, 0x00000001); - nv_icmd(priv, 0x0000092c, 0x00000001); - nv_icmd(priv, 0x0000092d, 0x00000001); - nv_icmd(priv, 0x0000092e, 0x00000001); - nv_icmd(priv, 0x0000092f, 0x00000001); - nv_icmd(priv, 0x00000648, 0x00000001); - nv_icmd(priv, 0x00000649, 0x00000001); - nv_icmd(priv, 0x0000064a, 0x00000001); - nv_icmd(priv, 0x0000064b, 0x00000001); - nv_icmd(priv, 0x0000064c, 0x00000001); - nv_icmd(priv, 0x0000064d, 0x00000001); - nv_icmd(priv, 0x0000064e, 0x00000001); - nv_icmd(priv, 0x0000064f, 0x00000001); - nv_icmd(priv, 0x00000650, 0x00000001); - nv_icmd(priv, 0x00000658, 0x0000000f); - nv_icmd(priv, 0x000007ff, 0x0000000a); - nv_icmd(priv, 0x0000066a, 0x40000000); - nv_icmd(priv, 0x0000066b, 0x10000000); - nv_icmd(priv, 0x0000066c, 0xffff0000); - nv_icmd(priv, 0x0000066d, 0xffff0000); - nv_icmd(priv, 0x000007af, 0x00000008); - nv_icmd(priv, 0x000007b0, 0x00000008); - nv_icmd(priv, 0x000007f6, 0x00000001); - nv_icmd(priv, 0x000006b2, 0x00000055); - nv_icmd(priv, 0x000007ad, 0x00000003); - nv_icmd(priv, 0x00000937, 0x00000001); - nv_icmd(priv, 0x00000971, 0x00000008); - nv_icmd(priv, 0x00000972, 0x00000040); - nv_icmd(priv, 0x00000973, 0x0000012c); - nv_icmd(priv, 0x0000097c, 0x00000040); - nv_icmd(priv, 0x00000979, 0x00000003); - nv_icmd(priv, 0x00000975, 0x00000020); - nv_icmd(priv, 0x00000976, 0x00000001); - nv_icmd(priv, 0x00000977, 0x00000020); - nv_icmd(priv, 0x00000978, 0x00000001); - nv_icmd(priv, 0x00000957, 0x00000003); - nv_icmd(priv, 0x0000095e, 0x20164010); - nv_icmd(priv, 0x0000095f, 0x00000020); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - case 0xc8: - nv_icmd(priv, 0x0000097d, 0x00000020); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; + /* trigger a context unload by unsetting the "next channel valid" bit + * and faking a context switch interrupt + */ + nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); + nv_wr32(priv, 0x409000, 0x00000100); + if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { + nv_error(priv, "grctx template channel unload timeout\n"); + ret = -EBUSY; + goto done; } - nv_icmd(priv, 0x00000683, 0x00000006); - nv_icmd(priv, 0x00000685, 0x003fffff); - nv_icmd(priv, 0x00000687, 0x00000c48); - nv_icmd(priv, 0x000006a0, 0x00000005); - nv_icmd(priv, 0x00000840, 0x00300008); - nv_icmd(priv, 0x00000841, 0x04000080); - nv_icmd(priv, 0x00000842, 0x00300008); - nv_icmd(priv, 0x00000843, 0x04000080); - nv_icmd(priv, 0x00000818, 0x00000000); - nv_icmd(priv, 0x00000819, 0x00000000); - nv_icmd(priv, 0x0000081a, 0x00000000); - nv_icmd(priv, 0x0000081b, 0x00000000); - nv_icmd(priv, 0x0000081c, 0x00000000); - nv_icmd(priv, 0x0000081d, 0x00000000); - nv_icmd(priv, 0x0000081e, 0x00000000); - nv_icmd(priv, 0x0000081f, 0x00000000); - nv_icmd(priv, 0x00000848, 0x00000000); - nv_icmd(priv, 0x00000849, 0x00000000); - nv_icmd(priv, 0x0000084a, 0x00000000); - nv_icmd(priv, 0x0000084b, 0x00000000); - nv_icmd(priv, 0x0000084c, 0x00000000); - nv_icmd(priv, 0x0000084d, 0x00000000); - nv_icmd(priv, 0x0000084e, 0x00000000); - nv_icmd(priv, 0x0000084f, 0x00000000); - nv_icmd(priv, 0x00000850, 0x00000000); - nv_icmd(priv, 0x00000851, 0x00000000); - nv_icmd(priv, 0x00000852, 0x00000000); - nv_icmd(priv, 0x00000853, 0x00000000); - nv_icmd(priv, 0x00000854, 0x00000000); - nv_icmd(priv, 0x00000855, 0x00000000); - nv_icmd(priv, 0x00000856, 0x00000000); - nv_icmd(priv, 0x00000857, 0x00000000); - nv_icmd(priv, 0x00000738, 0x00000000); - nv_icmd(priv, 0x000006aa, 0x00000001); - nv_icmd(priv, 0x000006ab, 0x00000002); - nv_icmd(priv, 0x000006ac, 0x00000080); - nv_icmd(priv, 0x000006ad, 0x00000100); - nv_icmd(priv, 0x000006ae, 0x00000100); - nv_icmd(priv, 0x000006b1, 0x00000011); - nv_icmd(priv, 0x000006bb, 0x000000cf); - nv_icmd(priv, 0x000006ce, 0x2a712488); - nv_icmd(priv, 0x00000739, 0x4085c000); - nv_icmd(priv, 0x0000073a, 0x00000080); - nv_icmd(priv, 0x00000786, 0x80000100); - nv_icmd(priv, 0x0000073c, 0x00010100); - nv_icmd(priv, 0x0000073d, 0x02800000); - nv_icmd(priv, 0x00000787, 0x000000cf); - nv_icmd(priv, 0x0000078c, 0x00000008); - nv_icmd(priv, 0x00000792, 0x00000001); - nv_icmd(priv, 0x00000794, 0x00000001); - nv_icmd(priv, 0x00000795, 0x00000001); - nv_icmd(priv, 0x00000796, 0x00000001); - nv_icmd(priv, 0x00000797, 0x000000cf); - nv_icmd(priv, 0x00000836, 0x00000001); - nv_icmd(priv, 0x0000079a, 0x00000002); - nv_icmd(priv, 0x00000833, 0x04444480); - nv_icmd(priv, 0x000007a1, 0x00000001); - nv_icmd(priv, 0x000007a3, 0x00000001); - nv_icmd(priv, 0x000007a4, 0x00000001); - nv_icmd(priv, 0x000007a5, 0x00000001); - nv_icmd(priv, 0x00000831, 0x00000004); - nv_icmd(priv, 0x0000080c, 0x00000002); - nv_icmd(priv, 0x0000080d, 0x00000100); - nv_icmd(priv, 0x0000080e, 0x00000100); - nv_icmd(priv, 0x0000080f, 0x00000001); - nv_icmd(priv, 0x00000823, 0x00000002); - nv_icmd(priv, 0x00000824, 0x00000100); - nv_icmd(priv, 0x00000825, 0x00000100); - nv_icmd(priv, 0x00000826, 0x00000001); - nv_icmd(priv, 0x0000095d, 0x00000001); - nv_icmd(priv, 0x0000082b, 0x00000004); - nv_icmd(priv, 0x00000942, 0x00010001); - nv_icmd(priv, 0x00000943, 0x00000001); - nv_icmd(priv, 0x00000944, 0x00000022); - nv_icmd(priv, 0x000007c5, 0x00010001); - nv_icmd(priv, 0x00000834, 0x00000001); - nv_icmd(priv, 0x000007c7, 0x00000001); - nv_icmd(priv, 0x0000c1b0, 0x0000000f); - nv_icmd(priv, 0x0000c1b1, 0x0000000f); - nv_icmd(priv, 0x0000c1b2, 0x0000000f); - nv_icmd(priv, 0x0000c1b3, 0x0000000f); - nv_icmd(priv, 0x0000c1b4, 0x0000000f); - nv_icmd(priv, 0x0000c1b5, 0x0000000f); - nv_icmd(priv, 0x0000c1b6, 0x0000000f); - nv_icmd(priv, 0x0000c1b7, 0x0000000f); - nv_icmd(priv, 0x0000c1b8, 0x0fac6881); - nv_icmd(priv, 0x0000c1b9, 0x00fac688); - nv_icmd(priv, 0x0001e100, 0x00000001); - nv_icmd(priv, 0x00001000, 0x00000002); - nv_icmd(priv, 0x000006aa, 0x00000001); - nv_icmd(priv, 0x000006ad, 0x00000100); - nv_icmd(priv, 0x000006ae, 0x00000100); - nv_icmd(priv, 0x000006b1, 0x00000011); - nv_icmd(priv, 0x0000078c, 0x00000008); - nv_icmd(priv, 0x00000792, 0x00000001); - nv_icmd(priv, 0x00000794, 0x00000001); - nv_icmd(priv, 0x00000795, 0x00000001); - nv_icmd(priv, 0x00000796, 0x00000001); - nv_icmd(priv, 0x00000797, 0x000000cf); - nv_icmd(priv, 0x0000079a, 0x00000002); - nv_icmd(priv, 0x00000833, 0x04444480); - nv_icmd(priv, 0x000007a1, 0x00000001); - nv_icmd(priv, 0x000007a3, 0x00000001); - nv_icmd(priv, 0x000007a4, 0x00000001); - nv_icmd(priv, 0x000007a5, 0x00000001); - nv_icmd(priv, 0x00000831, 0x00000004); - nv_icmd(priv, 0x0001e100, 0x00000001); - nv_icmd(priv, 0x00001000, 0x00000014); - nv_icmd(priv, 0x00000351, 0x00000100); - nv_icmd(priv, 0x00000957, 0x00000003); - nv_icmd(priv, 0x0000095d, 0x00000001); - nv_icmd(priv, 0x0000082b, 0x00000004); - nv_icmd(priv, 0x00000942, 0x00010001); - nv_icmd(priv, 0x00000943, 0x00000001); - nv_icmd(priv, 0x000007c5, 0x00010001); - nv_icmd(priv, 0x00000834, 0x00000001); - nv_icmd(priv, 0x000007c7, 0x00000001); - nv_icmd(priv, 0x0001e100, 0x00000001); - nv_icmd(priv, 0x00001000, 0x00000001); - nv_icmd(priv, 0x0000080c, 0x00000002); - nv_icmd(priv, 0x0000080d, 0x00000100); - nv_icmd(priv, 0x0000080e, 0x00000100); - nv_icmd(priv, 0x0000080f, 0x00000001); - nv_icmd(priv, 0x00000823, 0x00000002); - nv_icmd(priv, 0x00000824, 0x00000100); - nv_icmd(priv, 0x00000825, 0x00000100); - nv_icmd(priv, 0x00000826, 0x00000001); - nv_icmd(priv, 0x0001e100, 0x00000001); - - - nv_wr32(priv, 0x400208, 0x00000000); - nv_wr32(priv, 0x404154, 0x00000400); - nvc0_grctx_generate_9097(priv); - if (fermi >= 0x9197) - nvc0_grctx_generate_9197(priv); - if (fermi >= 0x9297) - nvc0_grctx_generate_9297(priv); - nvc0_grctx_generate_902d(priv); - nvc0_grctx_generate_9039(priv); - nvc0_grctx_generate_90c0(priv); - - switch (nv_device(priv)->chipset) { - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_mthd(priv, 0x902d, 0x3410, 0x00000000); - break; - case 0xd9: - case 0xd7: - nv_mthd(priv, 0x902d, 0x3410, 0x80002006); - break; - default: - BUG_ON(1); - break; + priv->data = kmalloc(priv->size, GFP_KERNEL); + if (priv->data) { + for (i = 0; i < priv->size; i += 4) + priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); + ret = 0; + } else { + ret = -ENOMEM; } - nv_wr32(priv, 0x000260, r000260); - - return nvc0_grctx_fini(&info); +done: + nouveau_gpuobj_ref(NULL, &chan); + return ret; } + +struct nvc0_graph_init * +nvc0_grctx_init_hub[] = { + nvc0_grctx_init_base, + nvc0_grctx_init_unk40xx, + nvc0_grctx_init_unk44xx, + nvc0_grctx_init_unk46xx, + nvc0_grctx_init_unk47xx, + nvc0_grctx_init_unk58xx, + nvc0_grctx_init_unk60xx, + nvc0_grctx_init_unk64xx, + nvc0_grctx_init_unk78xx, + nvc0_grctx_init_unk80xx, + nvc0_grctx_init_rop, + NULL +}; + +static struct nvc0_graph_init * +nvc0_grctx_init_gpc[] = { + nvc0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvc0_grctx_init_tpc, + NULL +}; + +struct nvc0_graph_init +nvc0_grctx_init_mthd_magic[] = { + { 0x3410, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_mthd +nvc0_grctx_init_mthd[] = { + { 0x9097, nvc0_grctx_init_9097, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x9039, nvc0_grctx_init_9039, }, + { 0x90c0, nvc0_grctx_init_90c0, }, + { 0x902d, nvc0_grctx_init_mthd_magic, }, + {} +}; + +struct nouveau_oclass * +nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .mods = nvc0_grctx_generate_mods, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_init_hub, + .gpc = nvc0_grctx_init_gpc, + .icmd = nvc0_grctx_init_icmd, + .mthd = nvc0_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c new file mode 100644 index 000000000000..e5be3ee7f172 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c @@ -0,0 +1,823 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +static struct nvc0_graph_init +nvc1_grctx_init_icmd[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 1, 0x01, 0x00000001 }, + { 0x000639, 1, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nvc1_grctx_init_9097[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x002700, 8, 0x20, 0x00000000 }, + { 0x002704, 8, 0x20, 0x00000000 }, + { 0x002708, 8, 0x20, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 8, 0x20, 0x00014000 }, + { 0x002714, 8, 0x20, 0x00000040 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002200, 5, 0x10, 0x00000022 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00001fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x003fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 1, 0x04, 0x00000000 }, + { 0x001320, 3, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 1, 0x04, 0x003fffff }, + { 0x0002d0, 1, 0x04, 0x00000c48 }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00300008 }, + { 0x001284, 1, 0x04, 0x04000080 }, + { 0x001450, 1, 0x04, 0x00300008 }, + { 0x001454, 1, 0x04, 0x04000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvc1_grctx_init_9197[] = { + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + {} +}; + +static struct nvc0_graph_init +nvc1_grctx_init_unk58xx[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180218 }, + { 0x405834, 2, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, +}; + +static struct nvc0_graph_init +nvc1_grctx_init_rop[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c80929 }, + { 0x408980, 1, 0x04, 0x0000011d }, +}; + +static struct nvc0_graph_init +nvc1_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x00200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 1, 0x04, 0x00000000 }, + { 0x41870c, 1, 0x04, 0x07c80000 }, + { 0x418710, 1, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x0006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x00100018 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418a00, 3, 0x04, 0x00000000 }, + { 0x418a0c, 1, 0x04, 0x00010000 }, + { 0x418a10, 3, 0x04, 0x00000000 }, + { 0x418a20, 3, 0x04, 0x00000000 }, + { 0x418a2c, 1, 0x04, 0x00010000 }, + { 0x418a30, 3, 0x04, 0x00000000 }, + { 0x418a40, 3, 0x04, 0x00000000 }, + { 0x418a4c, 1, 0x04, 0x00010000 }, + { 0x418a50, 3, 0x04, 0x00000000 }, + { 0x418a60, 3, 0x04, 0x00000000 }, + { 0x418a6c, 1, 0x04, 0x00010000 }, + { 0x418a70, 3, 0x04, 0x00000000 }, + { 0x418a80, 3, 0x04, 0x00000000 }, + { 0x418a8c, 1, 0x04, 0x00010000 }, + { 0x418a90, 3, 0x04, 0x00000000 }, + { 0x418aa0, 3, 0x04, 0x00000000 }, + { 0x418aac, 1, 0x04, 0x00010000 }, + { 0x418ab0, 3, 0x04, 0x00000000 }, + { 0x418ac0, 3, 0x04, 0x00000000 }, + { 0x418acc, 1, 0x04, 0x00010000 }, + { 0x418ad0, 3, 0x04, 0x00000000 }, + { 0x418ae0, 3, 0x04, 0x00000000 }, + { 0x418aec, 1, 0x04, 0x00010000 }, + { 0x418af0, 3, 0x04, 0x00000000 }, + { 0x418b00, 1, 0x04, 0x00000000 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, +}; + +static struct nvc0_graph_init +nvc1_grctx_init_tpc[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0007f440 }, + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00400001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + { 0x419c00, 1, 0x04, 0x00000002 }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x00020048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419d20, 1, 0x04, 0x12180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419d44, 1, 0x04, 0x02180218 }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00011110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, +}; + +void +nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + int gpc, tpc; + u32 offset; + + mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_list(0x408004, 0x00000000, 8, 0); + mmio_list(0x408008, 0x80000018, 0, 0); + mmio_list(0x40800c, 0x00000000, 8, 1); + mmio_list(0x408010, 0x80000000, 0, 0); + mmio_list(0x418810, 0x80000000, 12, 2); + mmio_list(0x419848, 0x10000000, 12, 2); + mmio_list(0x419004, 0x00000000, 8, 1); + mmio_list(0x419008, 0x00000000, 0, 0); + mmio_list(0x418808, 0x00000000, 8, 0); + mmio_list(0x41880c, 0x80000018, 0, 0); + + mmio_list(0x405830, 0x02180218, 0, 0); + mmio_list(0x4064c4, 0x0086ffff, 0, 0); + + for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + u32 addr = TPC_UNIT(gpc, tpc, 0x0520); + mmio_list(addr, 0x12180000 | offset, 0, 0); + offset += 0x0324; + } + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + u32 addr = TPC_UNIT(gpc, tpc, 0x0544); + mmio_list(addr, 0x02180000 | offset, 0, 0); + offset += 0x0324; + } + } +} + +void +nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) +{ + nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); + nv_mask(priv, 0x419814, 0x00000004, 0x00000004); + nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(priv, 0x405800, 0x08000000, 0x08000000); + nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +} + +static struct nvc0_graph_init * +nvc1_grctx_init_hub[] = { + nvc0_grctx_init_base, + nvc0_grctx_init_unk40xx, + nvc0_grctx_init_unk44xx, + nvc0_grctx_init_unk46xx, + nvc0_grctx_init_unk47xx, + nvc1_grctx_init_unk58xx, + nvc0_grctx_init_unk60xx, + nvc0_grctx_init_unk64xx, + nvc0_grctx_init_unk78xx, + nvc0_grctx_init_unk80xx, + nvc1_grctx_init_rop, + NULL +}; + +struct nvc0_graph_init * +nvc1_grctx_init_gpc[] = { + nvc1_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvc1_grctx_init_tpc, + NULL +}; + +static struct nvc0_graph_mthd +nvc1_grctx_init_mthd[] = { + { 0x9097, nvc1_grctx_init_9097, }, + { 0x9197, nvc1_grctx_init_9197, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x9039, nvc0_grctx_init_9039, }, + { 0x90c0, nvc0_grctx_init_90c0, }, + { 0x902d, nvc0_grctx_init_mthd_magic, }, + {} +}; + +struct nouveau_oclass * +nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .mods = nvc1_grctx_generate_mods, + .unkn = nvc1_grctx_generate_unkn, + .hub = nvc1_grctx_init_hub, + .gpc = nvc1_grctx_init_gpc, + .icmd = nvc1_grctx_init_icmd, + .mthd = nvc1_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c new file mode 100644 index 000000000000..8f237b3bd8c6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c @@ -0,0 +1,99 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +static struct nvc0_graph_init +nvc3_grctx_init_tpc[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x0000012a }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0007f440 }, + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00000001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + { 0x419c00, 1, 0x04, 0x00000002 }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x00020048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419d20, 1, 0x04, 0x02180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00011110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init * +nvc3_grctx_init_gpc[] = { + nvc0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvc3_grctx_init_tpc, + NULL +}; + +struct nouveau_oclass * +nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .mods = nvc0_grctx_generate_mods, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_init_hub, + .gpc = nvc3_grctx_init_gpc, + .icmd = nvc0_grctx_init_icmd, + .mthd = nvc0_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c new file mode 100644 index 000000000000..d0d4ce3c4892 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c @@ -0,0 +1,370 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +static struct nvc0_graph_init +nvc8_grctx_init_icmd[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 1, 0x01, 0x00000001 }, + { 0x000639, 1, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +static struct nvc0_graph_init +nvc8_grctx_init_tpc[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x0000012a }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00000001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + { 0x419c00, 1, 0x04, 0x00000002 }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x00060048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419d20, 1, 0x04, 0x02180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419f50, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc8_grctx_init_9197[] = { + { 0x0002e4, 1, 0x04, 0x0000b001 }, + {} +}; + +struct nvc0_graph_init +nvc8_grctx_init_9297[] = { + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x00000020 }, + {} +}; + +static struct nvc0_graph_mthd +nvc8_grctx_init_mthd[] = { + { 0x9097, nvc1_grctx_init_9097, }, + { 0x9197, nvc8_grctx_init_9197, }, + { 0x9297, nvc8_grctx_init_9297, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x9039, nvc0_grctx_init_9039, }, + { 0x90c0, nvc0_grctx_init_90c0, }, + { 0x902d, nvc0_grctx_init_mthd_magic, }, + {} +}; + +static struct nvc0_graph_init * +nvc8_grctx_init_gpc[] = { + nvc0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvc8_grctx_init_tpc, + NULL +}; + +struct nouveau_oclass * +nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xc8), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .mods = nvc0_grctx_generate_mods, + .unkn = nvc0_grctx_generate_unkn, + .hub = nvc0_grctx_init_hub, + .gpc = nvc8_grctx_init_gpc, + .icmd = nvc8_grctx_init_icmd, + .mthd = nvc8_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c new file mode 100644 index 000000000000..438e78410808 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c @@ -0,0 +1,290 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +struct nvc0_graph_init +nvd7_grctx_init_unk40xx[] = { + { 0x404004, 10, 0x04, 0x00000000 }, + { 0x404044, 1, 0x04, 0x00000000 }, + { 0x404094, 1, 0x04, 0x00000000 }, + { 0x404098, 12, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf0000087 }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 1, 0x04, 0x00000000 }, + { 0x404134, 1, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x404168, 1, 0x04, 0x00000000 }, + { 0x404178, 2, 0x04, 0x00000000 }, + { 0x404200, 8, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_grctx_init_unk58xx[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180324 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_grctx_init_unk64xx[] = { + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x801a0078 }, + { 0x4064c4, 1, 0x04, 0x00c9ffff }, + { 0x4064d0, 8, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 3, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000006 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +static struct nvc0_graph_init +nvd7_grctx_init_tpc[] = { + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00008000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0017f440 }, + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + { 0x419cb0, 1, 0x04, 0x00020048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00010110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_grctx_init_unk[] = { + { 0x41be24, 1, 0x04, 0x00000002 }, + { 0x41bec0, 1, 0x04, 0x12180000 }, + { 0x41bec4, 1, 0x04, 0x00003fff }, + { 0x41bee4, 1, 0x04, 0x03240218 }, + { 0x41bf00, 1, 0x04, 0x0a418820 }, + { 0x41bf04, 1, 0x04, 0x062080e6 }, + { 0x41bf08, 1, 0x04, 0x020398a4 }, + { 0x41bf0c, 1, 0x04, 0x0e629062 }, + { 0x41bf10, 1, 0x04, 0x0a418820 }, + { 0x41bf14, 1, 0x04, 0x000000e6 }, + { 0x41bfd0, 1, 0x04, 0x00900103 }, + { 0x41bfe0, 1, 0x04, 0x00400001 }, + { 0x41bfe4, 1, 0x04, 0x00000000 }, + {} +}; + +static void +nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + u32 magic[GPC_MAX][2]; + u32 offset; + int gpc; + + mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_list(0x40800c, 0x00000000, 8, 1); + mmio_list(0x408010, 0x80000000, 0, 0); + mmio_list(0x419004, 0x00000000, 8, 1); + mmio_list(0x419008, 0x00000000, 0, 0); + mmio_list(0x408004, 0x00000000, 8, 0); + mmio_list(0x408008, 0x80000018, 0, 0); + mmio_list(0x418808, 0x00000000, 8, 0); + mmio_list(0x41880c, 0x80000018, 0, 0); + mmio_list(0x418810, 0x80000000, 12, 2); + mmio_list(0x419848, 0x10000000, 12, 2); + + mmio_list(0x405830, 0x02180324, 0, 0); + mmio_list(0x4064c4, 0x00c9ffff, 0, 0); + + for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { + u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; + u16 magic1 = 0x0324 * priv->tpc_nr[gpc]; + magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; + magic[gpc][1] = 0x00000000 | (magic1 << 16); + offset += 0x0324 * priv->tpc_nr[gpc]; + } + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); + mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); + offset += 0x07ff * priv->tpc_nr[gpc]; + } + mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */ +} + +void +nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; + + nv_mask(priv, 0x000260, 0x00000001, 0x00000000); + + for (i = 0; oclass->hub[i]; i++) + nvc0_graph_mmio(priv, oclass->hub[i]); + for (i = 0; oclass->gpc[i]; i++) + nvc0_graph_mmio(priv, oclass->gpc[i]); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->mods(priv, info); + oclass->unkn(priv); + + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nvc0_grctx_generate_r4060a8(priv); + nve4_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nvc0_graph_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_graph_mthd(priv, oclass->mthd); + nv_mask(priv, 0x000260, 0x00000001, 0x00000001); +} + + +static struct nvc0_graph_init * +nvd7_grctx_init_hub[] = { + nvc0_grctx_init_base, + nvd7_grctx_init_unk40xx, + nvc0_grctx_init_unk44xx, + nvc0_grctx_init_unk46xx, + nvc0_grctx_init_unk47xx, + nvd7_grctx_init_unk58xx, + nvc0_grctx_init_unk60xx, + nvd7_grctx_init_unk64xx, + nvc0_grctx_init_unk78xx, + nvc0_grctx_init_unk80xx, + nvd9_grctx_init_rop, +}; + +struct nvc0_graph_init * +nvd7_grctx_init_gpc[] = { + nvd7_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvd7_grctx_init_tpc, + nvd7_grctx_init_unk, + NULL +}; + +struct nouveau_oclass * +nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xd7), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvd7_grctx_generate_main, + .mods = nvd7_grctx_generate_mods, + .unkn = nve4_grctx_generate_unkn, + .hub = nvd7_grctx_init_hub, + .gpc = nvd7_grctx_init_gpc, + .icmd = nvd9_grctx_init_icmd, + .mthd = nvd9_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c new file mode 100644 index 000000000000..818a4751df46 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c @@ -0,0 +1,515 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +struct nvc0_graph_init +nvd9_grctx_init_90c0[] = { + { 0x002700, 4, 0x40, 0x00000000 }, + { 0x002720, 4, 0x40, 0x00000000 }, + { 0x002704, 4, 0x40, 0x00000000 }, + { 0x002724, 4, 0x40, 0x00000000 }, + { 0x002708, 4, 0x40, 0x00000000 }, + { 0x002728, 4, 0x40, 0x00000000 }, + { 0x00270c, 8, 0x20, 0x00000000 }, + { 0x002710, 4, 0x40, 0x00014000 }, + { 0x002730, 4, 0x40, 0x00014000 }, + { 0x002714, 4, 0x40, 0x00000040 }, + { 0x002734, 4, 0x40, 0x00000040 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x000758, 1, 0x04, 0x00000100 }, + { 0x0002c4, 1, 0x04, 0x00000000 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x000204, 3, 0x04, 0x00000000 }, + { 0x000214, 1, 0x04, 0x00000000 }, + { 0x00024c, 1, 0x04, 0x00000000 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x001664, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvd9_grctx_init_icmd[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000b2, 40, 0x01, 0x00000000 }, + { 0x000210, 8, 0x01, 0x00000040 }, + { 0x000400, 24, 0x01, 0x00000040 }, + { 0x000218, 8, 0x01, 0x0000c080 }, + { 0x000440, 24, 0x01, 0x0000c080 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00001fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x003fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x0005e0, 5, 0x01, 0x00000022 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 1, 0x01, 0x00000001 }, + { 0x000639, 1, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x00000c48 }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00300008 }, + { 0x000841, 1, 0x01, 0x04000080 }, + { 0x000842, 1, 0x01, 0x00300008 }, + { 0x000843, 1, 0x01, 0x04000080 }, + { 0x000818, 8, 0x01, 0x00000000 }, + { 0x000848, 16, 0x01, 0x00000000 }, + { 0x000738, 1, 0x01, 0x00000000 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x000944, 1, 0x01, 0x00000022 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000014 }, + { 0x000351, 1, 0x01, 0x00000100 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095d, 1, 0x01, 0x00000001 }, + { 0x00082b, 1, 0x01, 0x00000004 }, + { 0x000942, 1, 0x01, 0x00010001 }, + { 0x000943, 1, 0x01, 0x00000001 }, + { 0x0007c5, 1, 0x01, 0x00010001 }, + { 0x000834, 1, 0x01, 0x00000001 }, + { 0x0007c7, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x00080c, 1, 0x01, 0x00000002 }, + { 0x00080d, 2, 0x01, 0x00000100 }, + { 0x00080f, 1, 0x01, 0x00000001 }, + { 0x000823, 1, 0x01, 0x00000002 }, + { 0x000824, 2, 0x01, 0x00000100 }, + { 0x000826, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nvd9_grctx_init_unk40xx[] = { + { 0x404004, 11, 0x04, 0x00000000 }, + { 0x404044, 1, 0x04, 0x00000000 }, + { 0x404094, 1, 0x04, 0x00000000 }, + { 0x404098, 12, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf0000087 }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 1, 0x04, 0x00000000 }, + { 0x404134, 1, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x404168, 1, 0x04, 0x00000000 }, + { 0x404178, 2, 0x04, 0x00000000 }, + { 0x404200, 8, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd9_grctx_init_unk58xx[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180218 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd9_grctx_init_unk64xx[] = { + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x80140078 }, + { 0x4064c4, 1, 0x04, 0x0086ffff }, + {} +}; + +struct nvc0_graph_init +nvd9_grctx_init_rop[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1043e005 }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x1043e005 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static struct nvc0_graph_init +nvd9_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 3, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00008442 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100008 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000006 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +static struct nvc0_graph_init +nvd9_grctx_init_tpc[] = { + { 0x419818, 1, 0x04, 0x00000000 }, + { 0x41983c, 1, 0x04, 0x00038bc7 }, + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000001f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000023 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x00000000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419ac4, 1, 0x04, 0x0017f440 }, + { 0x419b00, 1, 0x04, 0x0a418820 }, + { 0x419b04, 1, 0x04, 0x062080e6 }, + { 0x419b08, 1, 0x04, 0x020398a4 }, + { 0x419b0c, 1, 0x04, 0x0e629062 }, + { 0x419b10, 1, 0x04, 0x0a418820 }, + { 0x419b14, 1, 0x04, 0x000000e6 }, + { 0x419bd0, 1, 0x04, 0x00900103 }, + { 0x419be0, 1, 0x04, 0x00400001 }, + { 0x419be4, 1, 0x04, 0x00000000 }, + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x00000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3cf3cf3c }, + { 0x419cb0, 1, 0x04, 0x00020048 }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000183 }, + { 0x419d20, 1, 0x04, 0x12180000 }, + { 0x419d24, 1, 0x04, 0x00001fff }, + { 0x419d44, 1, 0x04, 0x02180218 }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000002 }, + { 0x419e44, 1, 0x04, 0x001beff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000000f }, + { 0x419e50, 17, 0x04, 0x00000000 }, + { 0x419e98, 1, 0x04, 0x00000000 }, + { 0x419ee0, 1, 0x04, 0x00010110 }, + { 0x419f30, 11, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init * +nvd9_grctx_init_hub[] = { + nvc0_grctx_init_base, + nvd9_grctx_init_unk40xx, + nvc0_grctx_init_unk44xx, + nvc0_grctx_init_unk46xx, + nvc0_grctx_init_unk47xx, + nvd9_grctx_init_unk58xx, + nvc0_grctx_init_unk60xx, + nvd9_grctx_init_unk64xx, + nvc0_grctx_init_unk78xx, + nvc0_grctx_init_unk80xx, + nvd9_grctx_init_rop, +}; + +struct nvc0_graph_init * +nvd9_grctx_init_gpc[] = { + nvd9_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvd9_grctx_init_tpc, + NULL +}; + +struct nvc0_graph_init +nvd9_grctx_init_mthd_magic[] = { + { 0x3410, 1, 0x04, 0x80002006 }, + {} +}; + +struct nvc0_graph_mthd +nvd9_grctx_init_mthd[] = { + { 0x9097, nvc1_grctx_init_9097, }, + { 0x9197, nvc8_grctx_init_9197, }, + { 0x9297, nvc8_grctx_init_9297, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x9039, nvc0_grctx_init_9039, }, + { 0x90c0, nvd9_grctx_init_90c0, }, + { 0x902d, nvd9_grctx_init_mthd_magic, }, + {} +}; + +struct nouveau_oclass * +nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xd9), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nvc0_grctx_generate_main, + .mods = nvc1_grctx_generate_mods, + .unkn = nvc1_grctx_generate_unkn, + .hub = nvd9_grctx_init_hub, + .gpc = nvd9_grctx_init_gpc, + .icmd = nvd9_grctx_init_icmd, + .mthd = nvd9_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c deleted file mode 100644 index 848570b4c519..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c +++ /dev/null @@ -1,2924 +0,0 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" - -static void -nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x400208, 0x80000000); - nv_icmd(priv, 0x001000, 0x00000004); - nv_icmd(priv, 0x000039, 0x00000000); - nv_icmd(priv, 0x00003a, 0x00000000); - nv_icmd(priv, 0x00003b, 0x00000000); - nv_icmd(priv, 0x0000a9, 0x0000ffff); - nv_icmd(priv, 0x000038, 0x0fac6881); - nv_icmd(priv, 0x00003d, 0x00000001); - nv_icmd(priv, 0x0000e8, 0x00000400); - nv_icmd(priv, 0x0000e9, 0x00000400); - nv_icmd(priv, 0x0000ea, 0x00000400); - nv_icmd(priv, 0x0000eb, 0x00000400); - nv_icmd(priv, 0x0000ec, 0x00000400); - nv_icmd(priv, 0x0000ed, 0x00000400); - nv_icmd(priv, 0x0000ee, 0x00000400); - nv_icmd(priv, 0x0000ef, 0x00000400); - nv_icmd(priv, 0x000078, 0x00000300); - nv_icmd(priv, 0x000079, 0x00000300); - nv_icmd(priv, 0x00007a, 0x00000300); - nv_icmd(priv, 0x00007b, 0x00000300); - nv_icmd(priv, 0x00007c, 0x00000300); - nv_icmd(priv, 0x00007d, 0x00000300); - nv_icmd(priv, 0x00007e, 0x00000300); - nv_icmd(priv, 0x00007f, 0x00000300); - nv_icmd(priv, 0x000050, 0x00000011); - nv_icmd(priv, 0x000058, 0x00000008); - nv_icmd(priv, 0x000059, 0x00000008); - nv_icmd(priv, 0x00005a, 0x00000008); - nv_icmd(priv, 0x00005b, 0x00000008); - nv_icmd(priv, 0x00005c, 0x00000008); - nv_icmd(priv, 0x00005d, 0x00000008); - nv_icmd(priv, 0x00005e, 0x00000008); - nv_icmd(priv, 0x00005f, 0x00000008); - nv_icmd(priv, 0x000208, 0x00000001); - nv_icmd(priv, 0x000209, 0x00000001); - nv_icmd(priv, 0x00020a, 0x00000001); - nv_icmd(priv, 0x00020b, 0x00000001); - nv_icmd(priv, 0x00020c, 0x00000001); - nv_icmd(priv, 0x00020d, 0x00000001); - nv_icmd(priv, 0x00020e, 0x00000001); - nv_icmd(priv, 0x00020f, 0x00000001); - nv_icmd(priv, 0x000081, 0x00000001); - nv_icmd(priv, 0x000085, 0x00000004); - nv_icmd(priv, 0x000088, 0x00000400); - nv_icmd(priv, 0x000090, 0x00000300); - nv_icmd(priv, 0x000098, 0x00001001); - nv_icmd(priv, 0x0000e3, 0x00000001); - nv_icmd(priv, 0x0000da, 0x00000001); - nv_icmd(priv, 0x0000f8, 0x00000003); - nv_icmd(priv, 0x0000fa, 0x00000001); - nv_icmd(priv, 0x00009f, 0x0000ffff); - nv_icmd(priv, 0x0000a0, 0x0000ffff); - nv_icmd(priv, 0x0000a1, 0x0000ffff); - nv_icmd(priv, 0x0000a2, 0x0000ffff); - nv_icmd(priv, 0x0000b1, 0x00000001); - nv_icmd(priv, 0x0000ad, 0x0000013e); - nv_icmd(priv, 0x0000e1, 0x00000010); - nv_icmd(priv, 0x000290, 0x00000000); - nv_icmd(priv, 0x000291, 0x00000000); - nv_icmd(priv, 0x000292, 0x00000000); - nv_icmd(priv, 0x000293, 0x00000000); - nv_icmd(priv, 0x000294, 0x00000000); - nv_icmd(priv, 0x000295, 0x00000000); - nv_icmd(priv, 0x000296, 0x00000000); - nv_icmd(priv, 0x000297, 0x00000000); - nv_icmd(priv, 0x000298, 0x00000000); - nv_icmd(priv, 0x000299, 0x00000000); - nv_icmd(priv, 0x00029a, 0x00000000); - nv_icmd(priv, 0x00029b, 0x00000000); - nv_icmd(priv, 0x00029c, 0x00000000); - nv_icmd(priv, 0x00029d, 0x00000000); - nv_icmd(priv, 0x00029e, 0x00000000); - nv_icmd(priv, 0x00029f, 0x00000000); - nv_icmd(priv, 0x0003b0, 0x00000000); - nv_icmd(priv, 0x0003b1, 0x00000000); - nv_icmd(priv, 0x0003b2, 0x00000000); - nv_icmd(priv, 0x0003b3, 0x00000000); - nv_icmd(priv, 0x0003b4, 0x00000000); - nv_icmd(priv, 0x0003b5, 0x00000000); - nv_icmd(priv, 0x0003b6, 0x00000000); - nv_icmd(priv, 0x0003b7, 0x00000000); - nv_icmd(priv, 0x0003b8, 0x00000000); - nv_icmd(priv, 0x0003b9, 0x00000000); - nv_icmd(priv, 0x0003ba, 0x00000000); - nv_icmd(priv, 0x0003bb, 0x00000000); - nv_icmd(priv, 0x0003bc, 0x00000000); - nv_icmd(priv, 0x0003bd, 0x00000000); - nv_icmd(priv, 0x0003be, 0x00000000); - nv_icmd(priv, 0x0003bf, 0x00000000); - nv_icmd(priv, 0x0002a0, 0x00000000); - nv_icmd(priv, 0x0002a1, 0x00000000); - nv_icmd(priv, 0x0002a2, 0x00000000); - nv_icmd(priv, 0x0002a3, 0x00000000); - nv_icmd(priv, 0x0002a4, 0x00000000); - nv_icmd(priv, 0x0002a5, 0x00000000); - nv_icmd(priv, 0x0002a6, 0x00000000); - nv_icmd(priv, 0x0002a7, 0x00000000); - nv_icmd(priv, 0x0002a8, 0x00000000); - nv_icmd(priv, 0x0002a9, 0x00000000); - nv_icmd(priv, 0x0002aa, 0x00000000); - nv_icmd(priv, 0x0002ab, 0x00000000); - nv_icmd(priv, 0x0002ac, 0x00000000); - nv_icmd(priv, 0x0002ad, 0x00000000); - nv_icmd(priv, 0x0002ae, 0x00000000); - nv_icmd(priv, 0x0002af, 0x00000000); - nv_icmd(priv, 0x000420, 0x00000000); - nv_icmd(priv, 0x000421, 0x00000000); - nv_icmd(priv, 0x000422, 0x00000000); - nv_icmd(priv, 0x000423, 0x00000000); - nv_icmd(priv, 0x000424, 0x00000000); - nv_icmd(priv, 0x000425, 0x00000000); - nv_icmd(priv, 0x000426, 0x00000000); - nv_icmd(priv, 0x000427, 0x00000000); - nv_icmd(priv, 0x000428, 0x00000000); - nv_icmd(priv, 0x000429, 0x00000000); - nv_icmd(priv, 0x00042a, 0x00000000); - nv_icmd(priv, 0x00042b, 0x00000000); - nv_icmd(priv, 0x00042c, 0x00000000); - nv_icmd(priv, 0x00042d, 0x00000000); - nv_icmd(priv, 0x00042e, 0x00000000); - nv_icmd(priv, 0x00042f, 0x00000000); - nv_icmd(priv, 0x0002b0, 0x00000000); - nv_icmd(priv, 0x0002b1, 0x00000000); - nv_icmd(priv, 0x0002b2, 0x00000000); - nv_icmd(priv, 0x0002b3, 0x00000000); - nv_icmd(priv, 0x0002b4, 0x00000000); - nv_icmd(priv, 0x0002b5, 0x00000000); - nv_icmd(priv, 0x0002b6, 0x00000000); - nv_icmd(priv, 0x0002b7, 0x00000000); - nv_icmd(priv, 0x0002b8, 0x00000000); - nv_icmd(priv, 0x0002b9, 0x00000000); - nv_icmd(priv, 0x0002ba, 0x00000000); - nv_icmd(priv, 0x0002bb, 0x00000000); - nv_icmd(priv, 0x0002bc, 0x00000000); - nv_icmd(priv, 0x0002bd, 0x00000000); - nv_icmd(priv, 0x0002be, 0x00000000); - nv_icmd(priv, 0x0002bf, 0x00000000); - nv_icmd(priv, 0x000430, 0x00000000); - nv_icmd(priv, 0x000431, 0x00000000); - nv_icmd(priv, 0x000432, 0x00000000); - nv_icmd(priv, 0x000433, 0x00000000); - nv_icmd(priv, 0x000434, 0x00000000); - nv_icmd(priv, 0x000435, 0x00000000); - nv_icmd(priv, 0x000436, 0x00000000); - nv_icmd(priv, 0x000437, 0x00000000); - nv_icmd(priv, 0x000438, 0x00000000); - nv_icmd(priv, 0x000439, 0x00000000); - nv_icmd(priv, 0x00043a, 0x00000000); - nv_icmd(priv, 0x00043b, 0x00000000); - nv_icmd(priv, 0x00043c, 0x00000000); - nv_icmd(priv, 0x00043d, 0x00000000); - nv_icmd(priv, 0x00043e, 0x00000000); - nv_icmd(priv, 0x00043f, 0x00000000); - nv_icmd(priv, 0x0002c0, 0x00000000); - nv_icmd(priv, 0x0002c1, 0x00000000); - nv_icmd(priv, 0x0002c2, 0x00000000); - nv_icmd(priv, 0x0002c3, 0x00000000); - nv_icmd(priv, 0x0002c4, 0x00000000); - nv_icmd(priv, 0x0002c5, 0x00000000); - nv_icmd(priv, 0x0002c6, 0x00000000); - nv_icmd(priv, 0x0002c7, 0x00000000); - nv_icmd(priv, 0x0002c8, 0x00000000); - nv_icmd(priv, 0x0002c9, 0x00000000); - nv_icmd(priv, 0x0002ca, 0x00000000); - nv_icmd(priv, 0x0002cb, 0x00000000); - nv_icmd(priv, 0x0002cc, 0x00000000); - nv_icmd(priv, 0x0002cd, 0x00000000); - nv_icmd(priv, 0x0002ce, 0x00000000); - nv_icmd(priv, 0x0002cf, 0x00000000); - nv_icmd(priv, 0x0004d0, 0x00000000); - nv_icmd(priv, 0x0004d1, 0x00000000); - nv_icmd(priv, 0x0004d2, 0x00000000); - nv_icmd(priv, 0x0004d3, 0x00000000); - nv_icmd(priv, 0x0004d4, 0x00000000); - nv_icmd(priv, 0x0004d5, 0x00000000); - nv_icmd(priv, 0x0004d6, 0x00000000); - nv_icmd(priv, 0x0004d7, 0x00000000); - nv_icmd(priv, 0x0004d8, 0x00000000); - nv_icmd(priv, 0x0004d9, 0x00000000); - nv_icmd(priv, 0x0004da, 0x00000000); - nv_icmd(priv, 0x0004db, 0x00000000); - nv_icmd(priv, 0x0004dc, 0x00000000); - nv_icmd(priv, 0x0004dd, 0x00000000); - nv_icmd(priv, 0x0004de, 0x00000000); - nv_icmd(priv, 0x0004df, 0x00000000); - nv_icmd(priv, 0x000720, 0x00000000); - nv_icmd(priv, 0x000721, 0x00000000); - nv_icmd(priv, 0x000722, 0x00000000); - nv_icmd(priv, 0x000723, 0x00000000); - nv_icmd(priv, 0x000724, 0x00000000); - nv_icmd(priv, 0x000725, 0x00000000); - nv_icmd(priv, 0x000726, 0x00000000); - nv_icmd(priv, 0x000727, 0x00000000); - nv_icmd(priv, 0x000728, 0x00000000); - nv_icmd(priv, 0x000729, 0x00000000); - nv_icmd(priv, 0x00072a, 0x00000000); - nv_icmd(priv, 0x00072b, 0x00000000); - nv_icmd(priv, 0x00072c, 0x00000000); - nv_icmd(priv, 0x00072d, 0x00000000); - nv_icmd(priv, 0x00072e, 0x00000000); - nv_icmd(priv, 0x00072f, 0x00000000); - nv_icmd(priv, 0x0008c0, 0x00000000); - nv_icmd(priv, 0x0008c1, 0x00000000); - nv_icmd(priv, 0x0008c2, 0x00000000); - nv_icmd(priv, 0x0008c3, 0x00000000); - nv_icmd(priv, 0x0008c4, 0x00000000); - nv_icmd(priv, 0x0008c5, 0x00000000); - nv_icmd(priv, 0x0008c6, 0x00000000); - nv_icmd(priv, 0x0008c7, 0x00000000); - nv_icmd(priv, 0x0008c8, 0x00000000); - nv_icmd(priv, 0x0008c9, 0x00000000); - nv_icmd(priv, 0x0008ca, 0x00000000); - nv_icmd(priv, 0x0008cb, 0x00000000); - nv_icmd(priv, 0x0008cc, 0x00000000); - nv_icmd(priv, 0x0008cd, 0x00000000); - nv_icmd(priv, 0x0008ce, 0x00000000); - nv_icmd(priv, 0x0008cf, 0x00000000); - nv_icmd(priv, 0x000890, 0x00000000); - nv_icmd(priv, 0x000891, 0x00000000); - nv_icmd(priv, 0x000892, 0x00000000); - nv_icmd(priv, 0x000893, 0x00000000); - nv_icmd(priv, 0x000894, 0x00000000); - nv_icmd(priv, 0x000895, 0x00000000); - nv_icmd(priv, 0x000896, 0x00000000); - nv_icmd(priv, 0x000897, 0x00000000); - nv_icmd(priv, 0x000898, 0x00000000); - nv_icmd(priv, 0x000899, 0x00000000); - nv_icmd(priv, 0x00089a, 0x00000000); - nv_icmd(priv, 0x00089b, 0x00000000); - nv_icmd(priv, 0x00089c, 0x00000000); - nv_icmd(priv, 0x00089d, 0x00000000); - nv_icmd(priv, 0x00089e, 0x00000000); - nv_icmd(priv, 0x00089f, 0x00000000); - nv_icmd(priv, 0x0008e0, 0x00000000); - nv_icmd(priv, 0x0008e1, 0x00000000); - nv_icmd(priv, 0x0008e2, 0x00000000); - nv_icmd(priv, 0x0008e3, 0x00000000); - nv_icmd(priv, 0x0008e4, 0x00000000); - nv_icmd(priv, 0x0008e5, 0x00000000); - nv_icmd(priv, 0x0008e6, 0x00000000); - nv_icmd(priv, 0x0008e7, 0x00000000); - nv_icmd(priv, 0x0008e8, 0x00000000); - nv_icmd(priv, 0x0008e9, 0x00000000); - nv_icmd(priv, 0x0008ea, 0x00000000); - nv_icmd(priv, 0x0008eb, 0x00000000); - nv_icmd(priv, 0x0008ec, 0x00000000); - nv_icmd(priv, 0x0008ed, 0x00000000); - nv_icmd(priv, 0x0008ee, 0x00000000); - nv_icmd(priv, 0x0008ef, 0x00000000); - nv_icmd(priv, 0x0008a0, 0x00000000); - nv_icmd(priv, 0x0008a1, 0x00000000); - nv_icmd(priv, 0x0008a2, 0x00000000); - nv_icmd(priv, 0x0008a3, 0x00000000); - nv_icmd(priv, 0x0008a4, 0x00000000); - nv_icmd(priv, 0x0008a5, 0x00000000); - nv_icmd(priv, 0x0008a6, 0x00000000); - nv_icmd(priv, 0x0008a7, 0x00000000); - nv_icmd(priv, 0x0008a8, 0x00000000); - nv_icmd(priv, 0x0008a9, 0x00000000); - nv_icmd(priv, 0x0008aa, 0x00000000); - nv_icmd(priv, 0x0008ab, 0x00000000); - nv_icmd(priv, 0x0008ac, 0x00000000); - nv_icmd(priv, 0x0008ad, 0x00000000); - nv_icmd(priv, 0x0008ae, 0x00000000); - nv_icmd(priv, 0x0008af, 0x00000000); - nv_icmd(priv, 0x0008f0, 0x00000000); - nv_icmd(priv, 0x0008f1, 0x00000000); - nv_icmd(priv, 0x0008f2, 0x00000000); - nv_icmd(priv, 0x0008f3, 0x00000000); - nv_icmd(priv, 0x0008f4, 0x00000000); - nv_icmd(priv, 0x0008f5, 0x00000000); - nv_icmd(priv, 0x0008f6, 0x00000000); - nv_icmd(priv, 0x0008f7, 0x00000000); - nv_icmd(priv, 0x0008f8, 0x00000000); - nv_icmd(priv, 0x0008f9, 0x00000000); - nv_icmd(priv, 0x0008fa, 0x00000000); - nv_icmd(priv, 0x0008fb, 0x00000000); - nv_icmd(priv, 0x0008fc, 0x00000000); - nv_icmd(priv, 0x0008fd, 0x00000000); - nv_icmd(priv, 0x0008fe, 0x00000000); - nv_icmd(priv, 0x0008ff, 0x00000000); - nv_icmd(priv, 0x00094c, 0x000000ff); - nv_icmd(priv, 0x00094d, 0xffffffff); - nv_icmd(priv, 0x00094e, 0x00000002); - nv_icmd(priv, 0x0002ec, 0x00000001); - nv_icmd(priv, 0x000303, 0x00000001); - nv_icmd(priv, 0x0002e6, 0x00000001); - nv_icmd(priv, 0x000466, 0x00000052); - nv_icmd(priv, 0x000301, 0x3f800000); - nv_icmd(priv, 0x000304, 0x30201000); - nv_icmd(priv, 0x000305, 0x70605040); - nv_icmd(priv, 0x000306, 0xb8a89888); - nv_icmd(priv, 0x000307, 0xf8e8d8c8); - nv_icmd(priv, 0x00030a, 0x00ffff00); - nv_icmd(priv, 0x00030b, 0x0000001a); - nv_icmd(priv, 0x00030c, 0x00000001); - nv_icmd(priv, 0x000318, 0x00000001); - nv_icmd(priv, 0x000340, 0x00000000); - nv_icmd(priv, 0x000375, 0x00000001); - nv_icmd(priv, 0x00037d, 0x00000006); - nv_icmd(priv, 0x0003a0, 0x00000002); - nv_icmd(priv, 0x0003aa, 0x00000001); - nv_icmd(priv, 0x0003a9, 0x00000001); - nv_icmd(priv, 0x000380, 0x00000001); - nv_icmd(priv, 0x000383, 0x00000011); - nv_icmd(priv, 0x000360, 0x00000040); - nv_icmd(priv, 0x000366, 0x00000000); - nv_icmd(priv, 0x000367, 0x00000000); - nv_icmd(priv, 0x000368, 0x00000fff); - nv_icmd(priv, 0x000370, 0x00000000); - nv_icmd(priv, 0x000371, 0x00000000); - nv_icmd(priv, 0x000372, 0x000fffff); - nv_icmd(priv, 0x00037a, 0x00000012); - nv_icmd(priv, 0x000619, 0x00000003); - nv_icmd(priv, 0x000811, 0x00000003); - nv_icmd(priv, 0x000812, 0x00000004); - nv_icmd(priv, 0x000813, 0x00000006); - nv_icmd(priv, 0x000814, 0x00000008); - nv_icmd(priv, 0x000815, 0x0000000b); - nv_icmd(priv, 0x000800, 0x00000001); - nv_icmd(priv, 0x000801, 0x00000001); - nv_icmd(priv, 0x000802, 0x00000001); - nv_icmd(priv, 0x000803, 0x00000001); - nv_icmd(priv, 0x000804, 0x00000001); - nv_icmd(priv, 0x000805, 0x00000001); - nv_icmd(priv, 0x000632, 0x00000001); - nv_icmd(priv, 0x000633, 0x00000002); - nv_icmd(priv, 0x000634, 0x00000003); - nv_icmd(priv, 0x000635, 0x00000004); - nv_icmd(priv, 0x000654, 0x3f800000); - nv_icmd(priv, 0x000657, 0x3f800000); - nv_icmd(priv, 0x000655, 0x3f800000); - nv_icmd(priv, 0x000656, 0x3f800000); - nv_icmd(priv, 0x0006cd, 0x3f800000); - nv_icmd(priv, 0x0007f5, 0x3f800000); - nv_icmd(priv, 0x0007dc, 0x39291909); - nv_icmd(priv, 0x0007dd, 0x79695949); - nv_icmd(priv, 0x0007de, 0xb9a99989); - nv_icmd(priv, 0x0007df, 0xf9e9d9c9); - nv_icmd(priv, 0x0007e8, 0x00003210); - nv_icmd(priv, 0x0007e9, 0x00007654); - nv_icmd(priv, 0x0007ea, 0x00000098); - nv_icmd(priv, 0x0007ec, 0x39291909); - nv_icmd(priv, 0x0007ed, 0x79695949); - nv_icmd(priv, 0x0007ee, 0xb9a99989); - nv_icmd(priv, 0x0007ef, 0xf9e9d9c9); - nv_icmd(priv, 0x0007f0, 0x00003210); - nv_icmd(priv, 0x0007f1, 0x00007654); - nv_icmd(priv, 0x0007f2, 0x00000098); - nv_icmd(priv, 0x0005a5, 0x00000001); - nv_icmd(priv, 0x000980, 0x00000000); - nv_icmd(priv, 0x000981, 0x00000000); - nv_icmd(priv, 0x000982, 0x00000000); - nv_icmd(priv, 0x000983, 0x00000000); - nv_icmd(priv, 0x000984, 0x00000000); - nv_icmd(priv, 0x000985, 0x00000000); - nv_icmd(priv, 0x000986, 0x00000000); - nv_icmd(priv, 0x000987, 0x00000000); - nv_icmd(priv, 0x000988, 0x00000000); - nv_icmd(priv, 0x000989, 0x00000000); - nv_icmd(priv, 0x00098a, 0x00000000); - nv_icmd(priv, 0x00098b, 0x00000000); - nv_icmd(priv, 0x00098c, 0x00000000); - nv_icmd(priv, 0x00098d, 0x00000000); - nv_icmd(priv, 0x00098e, 0x00000000); - nv_icmd(priv, 0x00098f, 0x00000000); - nv_icmd(priv, 0x000990, 0x00000000); - nv_icmd(priv, 0x000991, 0x00000000); - nv_icmd(priv, 0x000992, 0x00000000); - nv_icmd(priv, 0x000993, 0x00000000); - nv_icmd(priv, 0x000994, 0x00000000); - nv_icmd(priv, 0x000995, 0x00000000); - nv_icmd(priv, 0x000996, 0x00000000); - nv_icmd(priv, 0x000997, 0x00000000); - nv_icmd(priv, 0x000998, 0x00000000); - nv_icmd(priv, 0x000999, 0x00000000); - nv_icmd(priv, 0x00099a, 0x00000000); - nv_icmd(priv, 0x00099b, 0x00000000); - nv_icmd(priv, 0x00099c, 0x00000000); - nv_icmd(priv, 0x00099d, 0x00000000); - nv_icmd(priv, 0x00099e, 0x00000000); - nv_icmd(priv, 0x00099f, 0x00000000); - nv_icmd(priv, 0x0009a0, 0x00000000); - nv_icmd(priv, 0x0009a1, 0x00000000); - nv_icmd(priv, 0x0009a2, 0x00000000); - nv_icmd(priv, 0x0009a3, 0x00000000); - nv_icmd(priv, 0x0009a4, 0x00000000); - nv_icmd(priv, 0x0009a5, 0x00000000); - nv_icmd(priv, 0x0009a6, 0x00000000); - nv_icmd(priv, 0x0009a7, 0x00000000); - nv_icmd(priv, 0x0009a8, 0x00000000); - nv_icmd(priv, 0x0009a9, 0x00000000); - nv_icmd(priv, 0x0009aa, 0x00000000); - nv_icmd(priv, 0x0009ab, 0x00000000); - nv_icmd(priv, 0x0009ac, 0x00000000); - nv_icmd(priv, 0x0009ad, 0x00000000); - nv_icmd(priv, 0x0009ae, 0x00000000); - nv_icmd(priv, 0x0009af, 0x00000000); - nv_icmd(priv, 0x0009b0, 0x00000000); - nv_icmd(priv, 0x0009b1, 0x00000000); - nv_icmd(priv, 0x0009b2, 0x00000000); - nv_icmd(priv, 0x0009b3, 0x00000000); - nv_icmd(priv, 0x0009b4, 0x00000000); - nv_icmd(priv, 0x0009b5, 0x00000000); - nv_icmd(priv, 0x0009b6, 0x00000000); - nv_icmd(priv, 0x0009b7, 0x00000000); - nv_icmd(priv, 0x0009b8, 0x00000000); - nv_icmd(priv, 0x0009b9, 0x00000000); - nv_icmd(priv, 0x0009ba, 0x00000000); - nv_icmd(priv, 0x0009bb, 0x00000000); - nv_icmd(priv, 0x0009bc, 0x00000000); - nv_icmd(priv, 0x0009bd, 0x00000000); - nv_icmd(priv, 0x0009be, 0x00000000); - nv_icmd(priv, 0x0009bf, 0x00000000); - nv_icmd(priv, 0x0009c0, 0x00000000); - nv_icmd(priv, 0x0009c1, 0x00000000); - nv_icmd(priv, 0x0009c2, 0x00000000); - nv_icmd(priv, 0x0009c3, 0x00000000); - nv_icmd(priv, 0x0009c4, 0x00000000); - nv_icmd(priv, 0x0009c5, 0x00000000); - nv_icmd(priv, 0x0009c6, 0x00000000); - nv_icmd(priv, 0x0009c7, 0x00000000); - nv_icmd(priv, 0x0009c8, 0x00000000); - nv_icmd(priv, 0x0009c9, 0x00000000); - nv_icmd(priv, 0x0009ca, 0x00000000); - nv_icmd(priv, 0x0009cb, 0x00000000); - nv_icmd(priv, 0x0009cc, 0x00000000); - nv_icmd(priv, 0x0009cd, 0x00000000); - nv_icmd(priv, 0x0009ce, 0x00000000); - nv_icmd(priv, 0x0009cf, 0x00000000); - nv_icmd(priv, 0x0009d0, 0x00000000); - nv_icmd(priv, 0x0009d1, 0x00000000); - nv_icmd(priv, 0x0009d2, 0x00000000); - nv_icmd(priv, 0x0009d3, 0x00000000); - nv_icmd(priv, 0x0009d4, 0x00000000); - nv_icmd(priv, 0x0009d5, 0x00000000); - nv_icmd(priv, 0x0009d6, 0x00000000); - nv_icmd(priv, 0x0009d7, 0x00000000); - nv_icmd(priv, 0x0009d8, 0x00000000); - nv_icmd(priv, 0x0009d9, 0x00000000); - nv_icmd(priv, 0x0009da, 0x00000000); - nv_icmd(priv, 0x0009db, 0x00000000); - nv_icmd(priv, 0x0009dc, 0x00000000); - nv_icmd(priv, 0x0009dd, 0x00000000); - nv_icmd(priv, 0x0009de, 0x00000000); - nv_icmd(priv, 0x0009df, 0x00000000); - nv_icmd(priv, 0x0009e0, 0x00000000); - nv_icmd(priv, 0x0009e1, 0x00000000); - nv_icmd(priv, 0x0009e2, 0x00000000); - nv_icmd(priv, 0x0009e3, 0x00000000); - nv_icmd(priv, 0x0009e4, 0x00000000); - nv_icmd(priv, 0x0009e5, 0x00000000); - nv_icmd(priv, 0x0009e6, 0x00000000); - nv_icmd(priv, 0x0009e7, 0x00000000); - nv_icmd(priv, 0x0009e8, 0x00000000); - nv_icmd(priv, 0x0009e9, 0x00000000); - nv_icmd(priv, 0x0009ea, 0x00000000); - nv_icmd(priv, 0x0009eb, 0x00000000); - nv_icmd(priv, 0x0009ec, 0x00000000); - nv_icmd(priv, 0x0009ed, 0x00000000); - nv_icmd(priv, 0x0009ee, 0x00000000); - nv_icmd(priv, 0x0009ef, 0x00000000); - nv_icmd(priv, 0x0009f0, 0x00000000); - nv_icmd(priv, 0x0009f1, 0x00000000); - nv_icmd(priv, 0x0009f2, 0x00000000); - nv_icmd(priv, 0x0009f3, 0x00000000); - nv_icmd(priv, 0x0009f4, 0x00000000); - nv_icmd(priv, 0x0009f5, 0x00000000); - nv_icmd(priv, 0x0009f6, 0x00000000); - nv_icmd(priv, 0x0009f7, 0x00000000); - nv_icmd(priv, 0x0009f8, 0x00000000); - nv_icmd(priv, 0x0009f9, 0x00000000); - nv_icmd(priv, 0x0009fa, 0x00000000); - nv_icmd(priv, 0x0009fb, 0x00000000); - nv_icmd(priv, 0x0009fc, 0x00000000); - nv_icmd(priv, 0x0009fd, 0x00000000); - nv_icmd(priv, 0x0009fe, 0x00000000); - nv_icmd(priv, 0x0009ff, 0x00000000); - nv_icmd(priv, 0x000468, 0x00000004); - nv_icmd(priv, 0x00046c, 0x00000001); - nv_icmd(priv, 0x000470, 0x00000000); - nv_icmd(priv, 0x000471, 0x00000000); - nv_icmd(priv, 0x000472, 0x00000000); - nv_icmd(priv, 0x000473, 0x00000000); - nv_icmd(priv, 0x000474, 0x00000000); - nv_icmd(priv, 0x000475, 0x00000000); - nv_icmd(priv, 0x000476, 0x00000000); - nv_icmd(priv, 0x000477, 0x00000000); - nv_icmd(priv, 0x000478, 0x00000000); - nv_icmd(priv, 0x000479, 0x00000000); - nv_icmd(priv, 0x00047a, 0x00000000); - nv_icmd(priv, 0x00047b, 0x00000000); - nv_icmd(priv, 0x00047c, 0x00000000); - nv_icmd(priv, 0x00047d, 0x00000000); - nv_icmd(priv, 0x00047e, 0x00000000); - nv_icmd(priv, 0x00047f, 0x00000000); - nv_icmd(priv, 0x000480, 0x00000000); - nv_icmd(priv, 0x000481, 0x00000000); - nv_icmd(priv, 0x000482, 0x00000000); - nv_icmd(priv, 0x000483, 0x00000000); - nv_icmd(priv, 0x000484, 0x00000000); - nv_icmd(priv, 0x000485, 0x00000000); - nv_icmd(priv, 0x000486, 0x00000000); - nv_icmd(priv, 0x000487, 0x00000000); - nv_icmd(priv, 0x000488, 0x00000000); - nv_icmd(priv, 0x000489, 0x00000000); - nv_icmd(priv, 0x00048a, 0x00000000); - nv_icmd(priv, 0x00048b, 0x00000000); - nv_icmd(priv, 0x00048c, 0x00000000); - nv_icmd(priv, 0x00048d, 0x00000000); - nv_icmd(priv, 0x00048e, 0x00000000); - nv_icmd(priv, 0x00048f, 0x00000000); - nv_icmd(priv, 0x000490, 0x00000000); - nv_icmd(priv, 0x000491, 0x00000000); - nv_icmd(priv, 0x000492, 0x00000000); - nv_icmd(priv, 0x000493, 0x00000000); - nv_icmd(priv, 0x000494, 0x00000000); - nv_icmd(priv, 0x000495, 0x00000000); - nv_icmd(priv, 0x000496, 0x00000000); - nv_icmd(priv, 0x000497, 0x00000000); - nv_icmd(priv, 0x000498, 0x00000000); - nv_icmd(priv, 0x000499, 0x00000000); - nv_icmd(priv, 0x00049a, 0x00000000); - nv_icmd(priv, 0x00049b, 0x00000000); - nv_icmd(priv, 0x00049c, 0x00000000); - nv_icmd(priv, 0x00049d, 0x00000000); - nv_icmd(priv, 0x00049e, 0x00000000); - nv_icmd(priv, 0x00049f, 0x00000000); - nv_icmd(priv, 0x0004a0, 0x00000000); - nv_icmd(priv, 0x0004a1, 0x00000000); - nv_icmd(priv, 0x0004a2, 0x00000000); - nv_icmd(priv, 0x0004a3, 0x00000000); - nv_icmd(priv, 0x0004a4, 0x00000000); - nv_icmd(priv, 0x0004a5, 0x00000000); - nv_icmd(priv, 0x0004a6, 0x00000000); - nv_icmd(priv, 0x0004a7, 0x00000000); - nv_icmd(priv, 0x0004a8, 0x00000000); - nv_icmd(priv, 0x0004a9, 0x00000000); - nv_icmd(priv, 0x0004aa, 0x00000000); - nv_icmd(priv, 0x0004ab, 0x00000000); - nv_icmd(priv, 0x0004ac, 0x00000000); - nv_icmd(priv, 0x0004ad, 0x00000000); - nv_icmd(priv, 0x0004ae, 0x00000000); - nv_icmd(priv, 0x0004af, 0x00000000); - nv_icmd(priv, 0x0004b0, 0x00000000); - nv_icmd(priv, 0x0004b1, 0x00000000); - nv_icmd(priv, 0x0004b2, 0x00000000); - nv_icmd(priv, 0x0004b3, 0x00000000); - nv_icmd(priv, 0x0004b4, 0x00000000); - nv_icmd(priv, 0x0004b5, 0x00000000); - nv_icmd(priv, 0x0004b6, 0x00000000); - nv_icmd(priv, 0x0004b7, 0x00000000); - nv_icmd(priv, 0x0004b8, 0x00000000); - nv_icmd(priv, 0x0004b9, 0x00000000); - nv_icmd(priv, 0x0004ba, 0x00000000); - nv_icmd(priv, 0x0004bb, 0x00000000); - nv_icmd(priv, 0x0004bc, 0x00000000); - nv_icmd(priv, 0x0004bd, 0x00000000); - nv_icmd(priv, 0x0004be, 0x00000000); - nv_icmd(priv, 0x0004bf, 0x00000000); - nv_icmd(priv, 0x0004c0, 0x00000000); - nv_icmd(priv, 0x0004c1, 0x00000000); - nv_icmd(priv, 0x0004c2, 0x00000000); - nv_icmd(priv, 0x0004c3, 0x00000000); - nv_icmd(priv, 0x0004c4, 0x00000000); - nv_icmd(priv, 0x0004c5, 0x00000000); - nv_icmd(priv, 0x0004c6, 0x00000000); - nv_icmd(priv, 0x0004c7, 0x00000000); - nv_icmd(priv, 0x0004c8, 0x00000000); - nv_icmd(priv, 0x0004c9, 0x00000000); - nv_icmd(priv, 0x0004ca, 0x00000000); - nv_icmd(priv, 0x0004cb, 0x00000000); - nv_icmd(priv, 0x0004cc, 0x00000000); - nv_icmd(priv, 0x0004cd, 0x00000000); - nv_icmd(priv, 0x0004ce, 0x00000000); - nv_icmd(priv, 0x0004cf, 0x00000000); - nv_icmd(priv, 0x000510, 0x3f800000); - nv_icmd(priv, 0x000511, 0x3f800000); - nv_icmd(priv, 0x000512, 0x3f800000); - nv_icmd(priv, 0x000513, 0x3f800000); - nv_icmd(priv, 0x000514, 0x3f800000); - nv_icmd(priv, 0x000515, 0x3f800000); - nv_icmd(priv, 0x000516, 0x3f800000); - nv_icmd(priv, 0x000517, 0x3f800000); - nv_icmd(priv, 0x000518, 0x3f800000); - nv_icmd(priv, 0x000519, 0x3f800000); - nv_icmd(priv, 0x00051a, 0x3f800000); - nv_icmd(priv, 0x00051b, 0x3f800000); - nv_icmd(priv, 0x00051c, 0x3f800000); - nv_icmd(priv, 0x00051d, 0x3f800000); - nv_icmd(priv, 0x00051e, 0x3f800000); - nv_icmd(priv, 0x00051f, 0x3f800000); - nv_icmd(priv, 0x000520, 0x000002b6); - nv_icmd(priv, 0x000529, 0x00000001); - nv_icmd(priv, 0x000530, 0xffff0000); - nv_icmd(priv, 0x000531, 0xffff0000); - nv_icmd(priv, 0x000532, 0xffff0000); - nv_icmd(priv, 0x000533, 0xffff0000); - nv_icmd(priv, 0x000534, 0xffff0000); - nv_icmd(priv, 0x000535, 0xffff0000); - nv_icmd(priv, 0x000536, 0xffff0000); - nv_icmd(priv, 0x000537, 0xffff0000); - nv_icmd(priv, 0x000538, 0xffff0000); - nv_icmd(priv, 0x000539, 0xffff0000); - nv_icmd(priv, 0x00053a, 0xffff0000); - nv_icmd(priv, 0x00053b, 0xffff0000); - nv_icmd(priv, 0x00053c, 0xffff0000); - nv_icmd(priv, 0x00053d, 0xffff0000); - nv_icmd(priv, 0x00053e, 0xffff0000); - nv_icmd(priv, 0x00053f, 0xffff0000); - nv_icmd(priv, 0x000585, 0x0000003f); - nv_icmd(priv, 0x000576, 0x00000003); - nv_icmd(priv, 0x00057b, 0x00000059); - nv_icmd(priv, 0x000586, 0x00000040); - nv_icmd(priv, 0x000582, 0x00000080); - nv_icmd(priv, 0x000583, 0x00000080); - nv_icmd(priv, 0x0005c2, 0x00000001); - nv_icmd(priv, 0x000638, 0x00000001); - nv_icmd(priv, 0x000639, 0x00000001); - nv_icmd(priv, 0x00063a, 0x00000002); - nv_icmd(priv, 0x00063b, 0x00000001); - nv_icmd(priv, 0x00063c, 0x00000001); - nv_icmd(priv, 0x00063d, 0x00000002); - nv_icmd(priv, 0x00063e, 0x00000001); - nv_icmd(priv, 0x0008b8, 0x00000001); - nv_icmd(priv, 0x0008b9, 0x00000001); - nv_icmd(priv, 0x0008ba, 0x00000001); - nv_icmd(priv, 0x0008bb, 0x00000001); - nv_icmd(priv, 0x0008bc, 0x00000001); - nv_icmd(priv, 0x0008bd, 0x00000001); - nv_icmd(priv, 0x0008be, 0x00000001); - nv_icmd(priv, 0x0008bf, 0x00000001); - nv_icmd(priv, 0x000900, 0x00000001); - nv_icmd(priv, 0x000901, 0x00000001); - nv_icmd(priv, 0x000902, 0x00000001); - nv_icmd(priv, 0x000903, 0x00000001); - nv_icmd(priv, 0x000904, 0x00000001); - nv_icmd(priv, 0x000905, 0x00000001); - nv_icmd(priv, 0x000906, 0x00000001); - nv_icmd(priv, 0x000907, 0x00000001); - nv_icmd(priv, 0x000908, 0x00000002); - nv_icmd(priv, 0x000909, 0x00000002); - nv_icmd(priv, 0x00090a, 0x00000002); - nv_icmd(priv, 0x00090b, 0x00000002); - nv_icmd(priv, 0x00090c, 0x00000002); - nv_icmd(priv, 0x00090d, 0x00000002); - nv_icmd(priv, 0x00090e, 0x00000002); - nv_icmd(priv, 0x00090f, 0x00000002); - nv_icmd(priv, 0x000910, 0x00000001); - nv_icmd(priv, 0x000911, 0x00000001); - nv_icmd(priv, 0x000912, 0x00000001); - nv_icmd(priv, 0x000913, 0x00000001); - nv_icmd(priv, 0x000914, 0x00000001); - nv_icmd(priv, 0x000915, 0x00000001); - nv_icmd(priv, 0x000916, 0x00000001); - nv_icmd(priv, 0x000917, 0x00000001); - nv_icmd(priv, 0x000918, 0x00000001); - nv_icmd(priv, 0x000919, 0x00000001); - nv_icmd(priv, 0x00091a, 0x00000001); - nv_icmd(priv, 0x00091b, 0x00000001); - nv_icmd(priv, 0x00091c, 0x00000001); - nv_icmd(priv, 0x00091d, 0x00000001); - nv_icmd(priv, 0x00091e, 0x00000001); - nv_icmd(priv, 0x00091f, 0x00000001); - nv_icmd(priv, 0x000920, 0x00000002); - nv_icmd(priv, 0x000921, 0x00000002); - nv_icmd(priv, 0x000922, 0x00000002); - nv_icmd(priv, 0x000923, 0x00000002); - nv_icmd(priv, 0x000924, 0x00000002); - nv_icmd(priv, 0x000925, 0x00000002); - nv_icmd(priv, 0x000926, 0x00000002); - nv_icmd(priv, 0x000927, 0x00000002); - nv_icmd(priv, 0x000928, 0x00000001); - nv_icmd(priv, 0x000929, 0x00000001); - nv_icmd(priv, 0x00092a, 0x00000001); - nv_icmd(priv, 0x00092b, 0x00000001); - nv_icmd(priv, 0x00092c, 0x00000001); - nv_icmd(priv, 0x00092d, 0x00000001); - nv_icmd(priv, 0x00092e, 0x00000001); - nv_icmd(priv, 0x00092f, 0x00000001); - nv_icmd(priv, 0x000648, 0x00000001); - nv_icmd(priv, 0x000649, 0x00000001); - nv_icmd(priv, 0x00064a, 0x00000001); - nv_icmd(priv, 0x00064b, 0x00000001); - nv_icmd(priv, 0x00064c, 0x00000001); - nv_icmd(priv, 0x00064d, 0x00000001); - nv_icmd(priv, 0x00064e, 0x00000001); - nv_icmd(priv, 0x00064f, 0x00000001); - nv_icmd(priv, 0x000650, 0x00000001); - nv_icmd(priv, 0x000658, 0x0000000f); - nv_icmd(priv, 0x0007ff, 0x0000000a); - nv_icmd(priv, 0x00066a, 0x40000000); - nv_icmd(priv, 0x00066b, 0x10000000); - nv_icmd(priv, 0x00066c, 0xffff0000); - nv_icmd(priv, 0x00066d, 0xffff0000); - nv_icmd(priv, 0x0007af, 0x00000008); - nv_icmd(priv, 0x0007b0, 0x00000008); - nv_icmd(priv, 0x0007f6, 0x00000001); - nv_icmd(priv, 0x0006b2, 0x00000055); - nv_icmd(priv, 0x0007ad, 0x00000003); - nv_icmd(priv, 0x000937, 0x00000001); - nv_icmd(priv, 0x000971, 0x00000008); - nv_icmd(priv, 0x000972, 0x00000040); - nv_icmd(priv, 0x000973, 0x0000012c); - nv_icmd(priv, 0x00097c, 0x00000040); - nv_icmd(priv, 0x000979, 0x00000003); - nv_icmd(priv, 0x000975, 0x00000020); - nv_icmd(priv, 0x000976, 0x00000001); - nv_icmd(priv, 0x000977, 0x00000020); - nv_icmd(priv, 0x000978, 0x00000001); - nv_icmd(priv, 0x000957, 0x00000003); - nv_icmd(priv, 0x00095e, 0x20164010); - nv_icmd(priv, 0x00095f, 0x00000020); - nv_icmd(priv, 0x00097d, 0x00000020); - nv_icmd(priv, 0x000683, 0x00000006); - nv_icmd(priv, 0x000685, 0x003fffff); - nv_icmd(priv, 0x000687, 0x003fffff); - nv_icmd(priv, 0x0006a0, 0x00000005); - nv_icmd(priv, 0x000840, 0x00400008); - nv_icmd(priv, 0x000841, 0x08000080); - nv_icmd(priv, 0x000842, 0x00400008); - nv_icmd(priv, 0x000843, 0x08000080); - nv_icmd(priv, 0x0006aa, 0x00000001); - nv_icmd(priv, 0x0006ab, 0x00000002); - nv_icmd(priv, 0x0006ac, 0x00000080); - nv_icmd(priv, 0x0006ad, 0x00000100); - nv_icmd(priv, 0x0006ae, 0x00000100); - nv_icmd(priv, 0x0006b1, 0x00000011); - nv_icmd(priv, 0x0006bb, 0x000000cf); - nv_icmd(priv, 0x0006ce, 0x2a712488); - nv_icmd(priv, 0x000739, 0x4085c000); - nv_icmd(priv, 0x00073a, 0x00000080); - nv_icmd(priv, 0x000786, 0x80000100); - nv_icmd(priv, 0x00073c, 0x00010100); - nv_icmd(priv, 0x00073d, 0x02800000); - nv_icmd(priv, 0x000787, 0x000000cf); - nv_icmd(priv, 0x00078c, 0x00000008); - nv_icmd(priv, 0x000792, 0x00000001); - nv_icmd(priv, 0x000794, 0x00000001); - nv_icmd(priv, 0x000795, 0x00000001); - nv_icmd(priv, 0x000796, 0x00000001); - nv_icmd(priv, 0x000797, 0x000000cf); - nv_icmd(priv, 0x000836, 0x00000001); - nv_icmd(priv, 0x00079a, 0x00000002); - nv_icmd(priv, 0x000833, 0x04444480); - nv_icmd(priv, 0x0007a1, 0x00000001); - nv_icmd(priv, 0x0007a3, 0x00000001); - nv_icmd(priv, 0x0007a4, 0x00000001); - nv_icmd(priv, 0x0007a5, 0x00000001); - nv_icmd(priv, 0x000831, 0x00000004); - nv_icmd(priv, 0x000b07, 0x00000002); - nv_icmd(priv, 0x000b08, 0x00000100); - nv_icmd(priv, 0x000b09, 0x00000100); - nv_icmd(priv, 0x000b0a, 0x00000001); - nv_icmd(priv, 0x000a04, 0x000000ff); - nv_icmd(priv, 0x000a0b, 0x00000040); - nv_icmd(priv, 0x00097f, 0x00000100); - nv_icmd(priv, 0x000a02, 0x00000001); - nv_icmd(priv, 0x000809, 0x00000007); - nv_icmd(priv, 0x00c221, 0x00000040); - nv_icmd(priv, 0x00c1b0, 0x0000000f); - nv_icmd(priv, 0x00c1b1, 0x0000000f); - nv_icmd(priv, 0x00c1b2, 0x0000000f); - nv_icmd(priv, 0x00c1b3, 0x0000000f); - nv_icmd(priv, 0x00c1b4, 0x0000000f); - nv_icmd(priv, 0x00c1b5, 0x0000000f); - nv_icmd(priv, 0x00c1b6, 0x0000000f); - nv_icmd(priv, 0x00c1b7, 0x0000000f); - nv_icmd(priv, 0x00c1b8, 0x0fac6881); - nv_icmd(priv, 0x00c1b9, 0x00fac688); - nv_icmd(priv, 0x00c401, 0x00000001); - nv_icmd(priv, 0x00c402, 0x00010001); - nv_icmd(priv, 0x00c403, 0x00000001); - nv_icmd(priv, 0x00c404, 0x00000001); - nv_icmd(priv, 0x00c40e, 0x00000020); - nv_icmd(priv, 0x00c500, 0x00000003); - nv_icmd(priv, 0x01e100, 0x00000001); - nv_icmd(priv, 0x001000, 0x00000002); - nv_icmd(priv, 0x0006aa, 0x00000001); - nv_icmd(priv, 0x0006ad, 0x00000100); - nv_icmd(priv, 0x0006ae, 0x00000100); - nv_icmd(priv, 0x0006b1, 0x00000011); - nv_icmd(priv, 0x00078c, 0x00000008); - nv_icmd(priv, 0x000792, 0x00000001); - nv_icmd(priv, 0x000794, 0x00000001); - nv_icmd(priv, 0x000795, 0x00000001); - nv_icmd(priv, 0x000796, 0x00000001); - nv_icmd(priv, 0x000797, 0x000000cf); - nv_icmd(priv, 0x00079a, 0x00000002); - nv_icmd(priv, 0x000833, 0x04444480); - nv_icmd(priv, 0x0007a1, 0x00000001); - nv_icmd(priv, 0x0007a3, 0x00000001); - nv_icmd(priv, 0x0007a4, 0x00000001); - nv_icmd(priv, 0x0007a5, 0x00000001); - nv_icmd(priv, 0x000831, 0x00000004); - nv_icmd(priv, 0x01e100, 0x00000001); - nv_icmd(priv, 0x001000, 0x00000008); - nv_icmd(priv, 0x000039, 0x00000000); - nv_icmd(priv, 0x00003a, 0x00000000); - nv_icmd(priv, 0x00003b, 0x00000000); - nv_icmd(priv, 0x000380, 0x00000001); - nv_icmd(priv, 0x000366, 0x00000000); - nv_icmd(priv, 0x000367, 0x00000000); - nv_icmd(priv, 0x000368, 0x00000fff); - nv_icmd(priv, 0x000370, 0x00000000); - nv_icmd(priv, 0x000371, 0x00000000); - nv_icmd(priv, 0x000372, 0x000fffff); - nv_icmd(priv, 0x000813, 0x00000006); - nv_icmd(priv, 0x000814, 0x00000008); - nv_icmd(priv, 0x000957, 0x00000003); - nv_icmd(priv, 0x000b07, 0x00000002); - nv_icmd(priv, 0x000b08, 0x00000100); - nv_icmd(priv, 0x000b09, 0x00000100); - nv_icmd(priv, 0x000b0a, 0x00000001); - nv_icmd(priv, 0x000a04, 0x000000ff); - nv_icmd(priv, 0x00097f, 0x00000100); - nv_icmd(priv, 0x000a02, 0x00000001); - nv_icmd(priv, 0x000809, 0x00000007); - nv_icmd(priv, 0x00c221, 0x00000040); - nv_icmd(priv, 0x00c401, 0x00000001); - nv_icmd(priv, 0x00c402, 0x00010001); - nv_icmd(priv, 0x00c403, 0x00000001); - nv_icmd(priv, 0x00c404, 0x00000001); - nv_icmd(priv, 0x00c40e, 0x00000020); - nv_icmd(priv, 0x00c500, 0x00000003); - nv_icmd(priv, 0x01e100, 0x00000001); - nv_icmd(priv, 0x001000, 0x00000001); - nv_icmd(priv, 0x000b07, 0x00000002); - nv_icmd(priv, 0x000b08, 0x00000100); - nv_icmd(priv, 0x000b09, 0x00000100); - nv_icmd(priv, 0x000b0a, 0x00000001); - nv_icmd(priv, 0x01e100, 0x00000001); - nv_wr32(priv, 0x400208, 0x00000000); -} - -static void -nve0_grctx_generate_a097(struct nvc0_graph_priv *priv) -{ - nv_mthd(priv, 0xa097, 0x0800, 0x00000000); - nv_mthd(priv, 0xa097, 0x0840, 0x00000000); - nv_mthd(priv, 0xa097, 0x0880, 0x00000000); - nv_mthd(priv, 0xa097, 0x08c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0900, 0x00000000); - nv_mthd(priv, 0xa097, 0x0940, 0x00000000); - nv_mthd(priv, 0xa097, 0x0980, 0x00000000); - nv_mthd(priv, 0xa097, 0x09c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0804, 0x00000000); - nv_mthd(priv, 0xa097, 0x0844, 0x00000000); - nv_mthd(priv, 0xa097, 0x0884, 0x00000000); - nv_mthd(priv, 0xa097, 0x08c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0904, 0x00000000); - nv_mthd(priv, 0xa097, 0x0944, 0x00000000); - nv_mthd(priv, 0xa097, 0x0984, 0x00000000); - nv_mthd(priv, 0xa097, 0x09c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0808, 0x00000400); - nv_mthd(priv, 0xa097, 0x0848, 0x00000400); - nv_mthd(priv, 0xa097, 0x0888, 0x00000400); - nv_mthd(priv, 0xa097, 0x08c8, 0x00000400); - nv_mthd(priv, 0xa097, 0x0908, 0x00000400); - nv_mthd(priv, 0xa097, 0x0948, 0x00000400); - nv_mthd(priv, 0xa097, 0x0988, 0x00000400); - nv_mthd(priv, 0xa097, 0x09c8, 0x00000400); - nv_mthd(priv, 0xa097, 0x080c, 0x00000300); - nv_mthd(priv, 0xa097, 0x084c, 0x00000300); - nv_mthd(priv, 0xa097, 0x088c, 0x00000300); - nv_mthd(priv, 0xa097, 0x08cc, 0x00000300); - nv_mthd(priv, 0xa097, 0x090c, 0x00000300); - nv_mthd(priv, 0xa097, 0x094c, 0x00000300); - nv_mthd(priv, 0xa097, 0x098c, 0x00000300); - nv_mthd(priv, 0xa097, 0x09cc, 0x00000300); - nv_mthd(priv, 0xa097, 0x0810, 0x000000cf); - nv_mthd(priv, 0xa097, 0x0850, 0x00000000); - nv_mthd(priv, 0xa097, 0x0890, 0x00000000); - nv_mthd(priv, 0xa097, 0x08d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0910, 0x00000000); - nv_mthd(priv, 0xa097, 0x0950, 0x00000000); - nv_mthd(priv, 0xa097, 0x0990, 0x00000000); - nv_mthd(priv, 0xa097, 0x09d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0814, 0x00000040); - nv_mthd(priv, 0xa097, 0x0854, 0x00000040); - nv_mthd(priv, 0xa097, 0x0894, 0x00000040); - nv_mthd(priv, 0xa097, 0x08d4, 0x00000040); - nv_mthd(priv, 0xa097, 0x0914, 0x00000040); - nv_mthd(priv, 0xa097, 0x0954, 0x00000040); - nv_mthd(priv, 0xa097, 0x0994, 0x00000040); - nv_mthd(priv, 0xa097, 0x09d4, 0x00000040); - nv_mthd(priv, 0xa097, 0x0818, 0x00000001); - nv_mthd(priv, 0xa097, 0x0858, 0x00000001); - nv_mthd(priv, 0xa097, 0x0898, 0x00000001); - nv_mthd(priv, 0xa097, 0x08d8, 0x00000001); - nv_mthd(priv, 0xa097, 0x0918, 0x00000001); - nv_mthd(priv, 0xa097, 0x0958, 0x00000001); - nv_mthd(priv, 0xa097, 0x0998, 0x00000001); - nv_mthd(priv, 0xa097, 0x09d8, 0x00000001); - nv_mthd(priv, 0xa097, 0x081c, 0x00000000); - nv_mthd(priv, 0xa097, 0x085c, 0x00000000); - nv_mthd(priv, 0xa097, 0x089c, 0x00000000); - nv_mthd(priv, 0xa097, 0x08dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x091c, 0x00000000); - nv_mthd(priv, 0xa097, 0x095c, 0x00000000); - nv_mthd(priv, 0xa097, 0x099c, 0x00000000); - nv_mthd(priv, 0xa097, 0x09dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0820, 0x00000000); - nv_mthd(priv, 0xa097, 0x0860, 0x00000000); - nv_mthd(priv, 0xa097, 0x08a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x08e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0920, 0x00000000); - nv_mthd(priv, 0xa097, 0x0960, 0x00000000); - nv_mthd(priv, 0xa097, 0x09a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x09e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c00, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c10, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c20, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c30, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c40, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c50, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c60, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c70, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c80, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c90, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ca0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ce0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cf0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c04, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c14, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c24, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c34, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c44, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c54, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c64, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c74, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c84, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c94, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ca4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cb4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cd4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ce4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cf4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c08, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c18, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c28, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c38, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c48, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c58, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c68, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c78, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c88, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c98, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ca8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cb8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cd8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ce8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cf8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c1c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c2c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c3c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c5c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c6c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c7c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1c9c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cac, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cbc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ccc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cdc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cec, 0x00000000); - nv_mthd(priv, 0xa097, 0x1cfc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d00, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d10, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d20, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d30, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d40, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d50, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d60, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d70, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d80, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d90, 0x00000000); - nv_mthd(priv, 0xa097, 0x1da0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1db0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1de0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1df0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d04, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d14, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d24, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d34, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d44, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d54, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d64, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d74, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d84, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d94, 0x00000000); - nv_mthd(priv, 0xa097, 0x1da4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1db4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dd4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1de4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1df4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d08, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d18, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d28, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d38, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d48, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d58, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d68, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d78, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d88, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d98, 0x00000000); - nv_mthd(priv, 0xa097, 0x1da8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1db8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dd8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1de8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1df8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d1c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d2c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d3c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d5c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d6c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d7c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1d9c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dac, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dbc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dcc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ddc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dec, 0x00000000); - nv_mthd(priv, 0xa097, 0x1dfc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f00, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f08, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f10, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f18, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f20, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f28, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f30, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f38, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f40, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f48, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f50, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f58, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f60, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f68, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f70, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f78, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f04, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f14, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f1c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f24, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f2c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f34, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f3c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f44, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f54, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f5c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f64, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f6c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f74, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f7c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f80, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f88, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f90, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f98, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fa0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fa8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fb8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fd8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fe0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fe8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ff0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ff8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f84, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f94, 0x00000000); - nv_mthd(priv, 0xa097, 0x1f9c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fa4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fac, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fb4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fbc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fcc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fd4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fdc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fe4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1fec, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ff4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1ffc, 0x00000000); - nv_mthd(priv, 0xa097, 0x2000, 0x00000000); - nv_mthd(priv, 0xa097, 0x2040, 0x00000011); - nv_mthd(priv, 0xa097, 0x2080, 0x00000020); - nv_mthd(priv, 0xa097, 0x20c0, 0x00000030); - nv_mthd(priv, 0xa097, 0x2100, 0x00000040); - nv_mthd(priv, 0xa097, 0x2140, 0x00000051); - nv_mthd(priv, 0xa097, 0x200c, 0x00000001); - nv_mthd(priv, 0xa097, 0x204c, 0x00000001); - nv_mthd(priv, 0xa097, 0x208c, 0x00000001); - nv_mthd(priv, 0xa097, 0x20cc, 0x00000001); - nv_mthd(priv, 0xa097, 0x210c, 0x00000001); - nv_mthd(priv, 0xa097, 0x214c, 0x00000001); - nv_mthd(priv, 0xa097, 0x2010, 0x00000000); - nv_mthd(priv, 0xa097, 0x2050, 0x00000000); - nv_mthd(priv, 0xa097, 0x2090, 0x00000001); - nv_mthd(priv, 0xa097, 0x20d0, 0x00000002); - nv_mthd(priv, 0xa097, 0x2110, 0x00000003); - nv_mthd(priv, 0xa097, 0x2150, 0x00000004); - nv_mthd(priv, 0xa097, 0x0380, 0x00000000); - nv_mthd(priv, 0xa097, 0x03a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x03c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x03e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0384, 0x00000000); - nv_mthd(priv, 0xa097, 0x03a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x03c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x03e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0388, 0x00000000); - nv_mthd(priv, 0xa097, 0x03a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x03c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x03e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x038c, 0x00000000); - nv_mthd(priv, 0xa097, 0x03ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x03cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x03ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x0700, 0x00000000); - nv_mthd(priv, 0xa097, 0x0710, 0x00000000); - nv_mthd(priv, 0xa097, 0x0720, 0x00000000); - nv_mthd(priv, 0xa097, 0x0730, 0x00000000); - nv_mthd(priv, 0xa097, 0x0704, 0x00000000); - nv_mthd(priv, 0xa097, 0x0714, 0x00000000); - nv_mthd(priv, 0xa097, 0x0724, 0x00000000); - nv_mthd(priv, 0xa097, 0x0734, 0x00000000); - nv_mthd(priv, 0xa097, 0x0708, 0x00000000); - nv_mthd(priv, 0xa097, 0x0718, 0x00000000); - nv_mthd(priv, 0xa097, 0x0728, 0x00000000); - nv_mthd(priv, 0xa097, 0x0738, 0x00000000); - nv_mthd(priv, 0xa097, 0x2800, 0x00000000); - nv_mthd(priv, 0xa097, 0x2804, 0x00000000); - nv_mthd(priv, 0xa097, 0x2808, 0x00000000); - nv_mthd(priv, 0xa097, 0x280c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2810, 0x00000000); - nv_mthd(priv, 0xa097, 0x2814, 0x00000000); - nv_mthd(priv, 0xa097, 0x2818, 0x00000000); - nv_mthd(priv, 0xa097, 0x281c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2820, 0x00000000); - nv_mthd(priv, 0xa097, 0x2824, 0x00000000); - nv_mthd(priv, 0xa097, 0x2828, 0x00000000); - nv_mthd(priv, 0xa097, 0x282c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2830, 0x00000000); - nv_mthd(priv, 0xa097, 0x2834, 0x00000000); - nv_mthd(priv, 0xa097, 0x2838, 0x00000000); - nv_mthd(priv, 0xa097, 0x283c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2840, 0x00000000); - nv_mthd(priv, 0xa097, 0x2844, 0x00000000); - nv_mthd(priv, 0xa097, 0x2848, 0x00000000); - nv_mthd(priv, 0xa097, 0x284c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2850, 0x00000000); - nv_mthd(priv, 0xa097, 0x2854, 0x00000000); - nv_mthd(priv, 0xa097, 0x2858, 0x00000000); - nv_mthd(priv, 0xa097, 0x285c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2860, 0x00000000); - nv_mthd(priv, 0xa097, 0x2864, 0x00000000); - nv_mthd(priv, 0xa097, 0x2868, 0x00000000); - nv_mthd(priv, 0xa097, 0x286c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2870, 0x00000000); - nv_mthd(priv, 0xa097, 0x2874, 0x00000000); - nv_mthd(priv, 0xa097, 0x2878, 0x00000000); - nv_mthd(priv, 0xa097, 0x287c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2880, 0x00000000); - nv_mthd(priv, 0xa097, 0x2884, 0x00000000); - nv_mthd(priv, 0xa097, 0x2888, 0x00000000); - nv_mthd(priv, 0xa097, 0x288c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2890, 0x00000000); - nv_mthd(priv, 0xa097, 0x2894, 0x00000000); - nv_mthd(priv, 0xa097, 0x2898, 0x00000000); - nv_mthd(priv, 0xa097, 0x289c, 0x00000000); - nv_mthd(priv, 0xa097, 0x28a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x28b0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28b4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x28c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x28d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28d4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x28e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x28f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x28f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x28f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x28fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x2900, 0x00000000); - nv_mthd(priv, 0xa097, 0x2904, 0x00000000); - nv_mthd(priv, 0xa097, 0x2908, 0x00000000); - nv_mthd(priv, 0xa097, 0x290c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2910, 0x00000000); - nv_mthd(priv, 0xa097, 0x2914, 0x00000000); - nv_mthd(priv, 0xa097, 0x2918, 0x00000000); - nv_mthd(priv, 0xa097, 0x291c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2920, 0x00000000); - nv_mthd(priv, 0xa097, 0x2924, 0x00000000); - nv_mthd(priv, 0xa097, 0x2928, 0x00000000); - nv_mthd(priv, 0xa097, 0x292c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2930, 0x00000000); - nv_mthd(priv, 0xa097, 0x2934, 0x00000000); - nv_mthd(priv, 0xa097, 0x2938, 0x00000000); - nv_mthd(priv, 0xa097, 0x293c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2940, 0x00000000); - nv_mthd(priv, 0xa097, 0x2944, 0x00000000); - nv_mthd(priv, 0xa097, 0x2948, 0x00000000); - nv_mthd(priv, 0xa097, 0x294c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2950, 0x00000000); - nv_mthd(priv, 0xa097, 0x2954, 0x00000000); - nv_mthd(priv, 0xa097, 0x2958, 0x00000000); - nv_mthd(priv, 0xa097, 0x295c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2960, 0x00000000); - nv_mthd(priv, 0xa097, 0x2964, 0x00000000); - nv_mthd(priv, 0xa097, 0x2968, 0x00000000); - nv_mthd(priv, 0xa097, 0x296c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2970, 0x00000000); - nv_mthd(priv, 0xa097, 0x2974, 0x00000000); - nv_mthd(priv, 0xa097, 0x2978, 0x00000000); - nv_mthd(priv, 0xa097, 0x297c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2980, 0x00000000); - nv_mthd(priv, 0xa097, 0x2984, 0x00000000); - nv_mthd(priv, 0xa097, 0x2988, 0x00000000); - nv_mthd(priv, 0xa097, 0x298c, 0x00000000); - nv_mthd(priv, 0xa097, 0x2990, 0x00000000); - nv_mthd(priv, 0xa097, 0x2994, 0x00000000); - nv_mthd(priv, 0xa097, 0x2998, 0x00000000); - nv_mthd(priv, 0xa097, 0x299c, 0x00000000); - nv_mthd(priv, 0xa097, 0x29a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x29b0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29b4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x29c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x29d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29d4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x29e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x29f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x29f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x29f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x29fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a00, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a20, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a40, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a60, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a80, 0x00000000); - nv_mthd(priv, 0xa097, 0x0aa0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ac0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ae0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b00, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b20, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b40, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b60, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b80, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ba0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0be0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a04, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a24, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a44, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a64, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a84, 0x00000000); - nv_mthd(priv, 0xa097, 0x0aa4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ac4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ae4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b04, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b24, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b44, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b64, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b84, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ba4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0be4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a08, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a28, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a48, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a68, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a88, 0x00000000); - nv_mthd(priv, 0xa097, 0x0aa8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ac8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ae8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b08, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b28, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b48, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b68, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b88, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ba8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0be8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a2c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a6c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0aac, 0x00000000); - nv_mthd(priv, 0xa097, 0x0acc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0aec, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b2c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b6c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bac, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bcc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bec, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a10, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a30, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a50, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a70, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a90, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ab0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ad0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0af0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b10, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b30, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b50, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b70, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b90, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bf0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a14, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a34, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a54, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a74, 0x00000000); - nv_mthd(priv, 0xa097, 0x0a94, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ab4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ad4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0af4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b14, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b34, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b54, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b74, 0x00000000); - nv_mthd(priv, 0xa097, 0x0b94, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bb4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bd4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0bf4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c00, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c10, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c20, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c30, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c40, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c50, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c60, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c70, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c80, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c90, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ca0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ce0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cf0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c04, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c14, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c24, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c34, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c44, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c54, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c64, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c74, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c84, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c94, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ca4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cb4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cd4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ce4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cf4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c08, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c18, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c28, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c38, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c48, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c58, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c68, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c78, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c88, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c98, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ca8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cb8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cd8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ce8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0cf8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0c0c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c1c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c2c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c3c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c4c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c5c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c6c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c7c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c8c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0c9c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0cac, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0cbc, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0ccc, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0cdc, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0cec, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0cfc, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0d00, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d08, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d10, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d18, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d20, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d28, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d30, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d38, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d04, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d0c, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d14, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d1c, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d24, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d2c, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d34, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d3c, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e00, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e10, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e20, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e30, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e40, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e50, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e60, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e70, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e80, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e90, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ea0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0eb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ec0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ed0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ee0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ef0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0e04, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e14, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e24, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e34, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e44, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e54, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e64, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e74, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e84, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e94, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ea4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0eb4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ec4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ed4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ee4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ef4, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e08, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e18, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e28, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e38, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e48, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e58, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e68, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e78, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e88, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0e98, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ea8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0eb8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ec8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ed8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ee8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0ef8, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d40, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d48, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d50, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d58, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d44, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d4c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d54, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d5c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1e00, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e20, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e40, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e60, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e80, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ea0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ec0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ee0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e04, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e24, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e44, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e64, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e84, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ea4, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ec4, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ee4, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e08, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e28, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e48, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e68, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e88, 0x00000002); - nv_mthd(priv, 0xa097, 0x1ea8, 0x00000002); - nv_mthd(priv, 0xa097, 0x1ec8, 0x00000002); - nv_mthd(priv, 0xa097, 0x1ee8, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e0c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e2c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e4c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e6c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e8c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1eac, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ecc, 0x00000001); - nv_mthd(priv, 0xa097, 0x1eec, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e10, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e30, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e50, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e70, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e90, 0x00000001); - nv_mthd(priv, 0xa097, 0x1eb0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ed0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ef0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e14, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e34, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e54, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e74, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e94, 0x00000002); - nv_mthd(priv, 0xa097, 0x1eb4, 0x00000002); - nv_mthd(priv, 0xa097, 0x1ed4, 0x00000002); - nv_mthd(priv, 0xa097, 0x1ef4, 0x00000002); - nv_mthd(priv, 0xa097, 0x1e18, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e38, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e58, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e78, 0x00000001); - nv_mthd(priv, 0xa097, 0x1e98, 0x00000001); - nv_mthd(priv, 0xa097, 0x1eb8, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ed8, 0x00000001); - nv_mthd(priv, 0xa097, 0x1ef8, 0x00000001); - nv_mthd(priv, 0xa097, 0x3400, 0x00000000); - nv_mthd(priv, 0xa097, 0x3404, 0x00000000); - nv_mthd(priv, 0xa097, 0x3408, 0x00000000); - nv_mthd(priv, 0xa097, 0x340c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3410, 0x00000000); - nv_mthd(priv, 0xa097, 0x3414, 0x00000000); - nv_mthd(priv, 0xa097, 0x3418, 0x00000000); - nv_mthd(priv, 0xa097, 0x341c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3420, 0x00000000); - nv_mthd(priv, 0xa097, 0x3424, 0x00000000); - nv_mthd(priv, 0xa097, 0x3428, 0x00000000); - nv_mthd(priv, 0xa097, 0x342c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3430, 0x00000000); - nv_mthd(priv, 0xa097, 0x3434, 0x00000000); - nv_mthd(priv, 0xa097, 0x3438, 0x00000000); - nv_mthd(priv, 0xa097, 0x343c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3440, 0x00000000); - nv_mthd(priv, 0xa097, 0x3444, 0x00000000); - nv_mthd(priv, 0xa097, 0x3448, 0x00000000); - nv_mthd(priv, 0xa097, 0x344c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3450, 0x00000000); - nv_mthd(priv, 0xa097, 0x3454, 0x00000000); - nv_mthd(priv, 0xa097, 0x3458, 0x00000000); - nv_mthd(priv, 0xa097, 0x345c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3460, 0x00000000); - nv_mthd(priv, 0xa097, 0x3464, 0x00000000); - nv_mthd(priv, 0xa097, 0x3468, 0x00000000); - nv_mthd(priv, 0xa097, 0x346c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3470, 0x00000000); - nv_mthd(priv, 0xa097, 0x3474, 0x00000000); - nv_mthd(priv, 0xa097, 0x3478, 0x00000000); - nv_mthd(priv, 0xa097, 0x347c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3480, 0x00000000); - nv_mthd(priv, 0xa097, 0x3484, 0x00000000); - nv_mthd(priv, 0xa097, 0x3488, 0x00000000); - nv_mthd(priv, 0xa097, 0x348c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3490, 0x00000000); - nv_mthd(priv, 0xa097, 0x3494, 0x00000000); - nv_mthd(priv, 0xa097, 0x3498, 0x00000000); - nv_mthd(priv, 0xa097, 0x349c, 0x00000000); - nv_mthd(priv, 0xa097, 0x34a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x34b0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34b4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x34c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x34d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34d4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x34e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x34f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x34f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x34f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x34fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x3500, 0x00000000); - nv_mthd(priv, 0xa097, 0x3504, 0x00000000); - nv_mthd(priv, 0xa097, 0x3508, 0x00000000); - nv_mthd(priv, 0xa097, 0x350c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3510, 0x00000000); - nv_mthd(priv, 0xa097, 0x3514, 0x00000000); - nv_mthd(priv, 0xa097, 0x3518, 0x00000000); - nv_mthd(priv, 0xa097, 0x351c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3520, 0x00000000); - nv_mthd(priv, 0xa097, 0x3524, 0x00000000); - nv_mthd(priv, 0xa097, 0x3528, 0x00000000); - nv_mthd(priv, 0xa097, 0x352c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3530, 0x00000000); - nv_mthd(priv, 0xa097, 0x3534, 0x00000000); - nv_mthd(priv, 0xa097, 0x3538, 0x00000000); - nv_mthd(priv, 0xa097, 0x353c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3540, 0x00000000); - nv_mthd(priv, 0xa097, 0x3544, 0x00000000); - nv_mthd(priv, 0xa097, 0x3548, 0x00000000); - nv_mthd(priv, 0xa097, 0x354c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3550, 0x00000000); - nv_mthd(priv, 0xa097, 0x3554, 0x00000000); - nv_mthd(priv, 0xa097, 0x3558, 0x00000000); - nv_mthd(priv, 0xa097, 0x355c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3560, 0x00000000); - nv_mthd(priv, 0xa097, 0x3564, 0x00000000); - nv_mthd(priv, 0xa097, 0x3568, 0x00000000); - nv_mthd(priv, 0xa097, 0x356c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3570, 0x00000000); - nv_mthd(priv, 0xa097, 0x3574, 0x00000000); - nv_mthd(priv, 0xa097, 0x3578, 0x00000000); - nv_mthd(priv, 0xa097, 0x357c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3580, 0x00000000); - nv_mthd(priv, 0xa097, 0x3584, 0x00000000); - nv_mthd(priv, 0xa097, 0x3588, 0x00000000); - nv_mthd(priv, 0xa097, 0x358c, 0x00000000); - nv_mthd(priv, 0xa097, 0x3590, 0x00000000); - nv_mthd(priv, 0xa097, 0x3594, 0x00000000); - nv_mthd(priv, 0xa097, 0x3598, 0x00000000); - nv_mthd(priv, 0xa097, 0x359c, 0x00000000); - nv_mthd(priv, 0xa097, 0x35a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x35b0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35b4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x35c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x35d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35d4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x35e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x35f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x35f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x35f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x35fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x030c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1944, 0x00000000); - nv_mthd(priv, 0xa097, 0x1514, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d68, 0x0000ffff); - nv_mthd(priv, 0xa097, 0x121c, 0x0fac6881); - nv_mthd(priv, 0xa097, 0x0fac, 0x00000001); - nv_mthd(priv, 0xa097, 0x1538, 0x00000001); - nv_mthd(priv, 0xa097, 0x0fe0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fe4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fe8, 0x00000014); - nv_mthd(priv, 0xa097, 0x0fec, 0x00000040); - nv_mthd(priv, 0xa097, 0x0ff0, 0x00000000); - nv_mthd(priv, 0xa097, 0x179c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1228, 0x00000400); - nv_mthd(priv, 0xa097, 0x122c, 0x00000300); - nv_mthd(priv, 0xa097, 0x1230, 0x00010001); - nv_mthd(priv, 0xa097, 0x07f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x15b4, 0x00000001); - nv_mthd(priv, 0xa097, 0x15cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1534, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fb0, 0x00000000); - nv_mthd(priv, 0xa097, 0x15d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x153c, 0x00000000); - nv_mthd(priv, 0xa097, 0x16b4, 0x00000003); - nv_mthd(priv, 0xa097, 0x0fbc, 0x0000ffff); - nv_mthd(priv, 0xa097, 0x0fc0, 0x0000ffff); - nv_mthd(priv, 0xa097, 0x0fc4, 0x0000ffff); - nv_mthd(priv, 0xa097, 0x0fc8, 0x0000ffff); - nv_mthd(priv, 0xa097, 0x0df8, 0x00000000); - nv_mthd(priv, 0xa097, 0x0dfc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1948, 0x00000000); - nv_mthd(priv, 0xa097, 0x1970, 0x00000001); - nv_mthd(priv, 0xa097, 0x161c, 0x000009f0); - nv_mthd(priv, 0xa097, 0x0dcc, 0x00000010); - nv_mthd(priv, 0xa097, 0x163c, 0x00000000); - nv_mthd(priv, 0xa097, 0x15e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1160, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1164, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1168, 0x25e00040); - nv_mthd(priv, 0xa097, 0x116c, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1170, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1174, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1178, 0x25e00040); - nv_mthd(priv, 0xa097, 0x117c, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1180, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1184, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1188, 0x25e00040); - nv_mthd(priv, 0xa097, 0x118c, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1190, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1194, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1198, 0x25e00040); - nv_mthd(priv, 0xa097, 0x119c, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11a0, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11a4, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11a8, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11ac, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11b0, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11b4, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11b8, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11bc, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11c0, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11c4, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11c8, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11cc, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11d0, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11d4, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11d8, 0x25e00040); - nv_mthd(priv, 0xa097, 0x11dc, 0x25e00040); - nv_mthd(priv, 0xa097, 0x1880, 0x00000000); - nv_mthd(priv, 0xa097, 0x1884, 0x00000000); - nv_mthd(priv, 0xa097, 0x1888, 0x00000000); - nv_mthd(priv, 0xa097, 0x188c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1890, 0x00000000); - nv_mthd(priv, 0xa097, 0x1894, 0x00000000); - nv_mthd(priv, 0xa097, 0x1898, 0x00000000); - nv_mthd(priv, 0xa097, 0x189c, 0x00000000); - nv_mthd(priv, 0xa097, 0x18a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x18b0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18b4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x18c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x18d0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18d4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x18e0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x18f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x18f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x18f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x18fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f84, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f88, 0x00000000); - nv_mthd(priv, 0xa097, 0x17c8, 0x00000000); - nv_mthd(priv, 0xa097, 0x17cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x17d0, 0x000000ff); - nv_mthd(priv, 0xa097, 0x17d4, 0xffffffff); - nv_mthd(priv, 0xa097, 0x17d8, 0x00000002); - nv_mthd(priv, 0xa097, 0x17dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x15f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x15f8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1434, 0x00000000); - nv_mthd(priv, 0xa097, 0x1438, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d74, 0x00000000); - nv_mthd(priv, 0xa097, 0x0dec, 0x00000001); - nv_mthd(priv, 0xa097, 0x13a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1318, 0x00000001); - nv_mthd(priv, 0xa097, 0x1644, 0x00000000); - nv_mthd(priv, 0xa097, 0x0748, 0x00000000); - nv_mthd(priv, 0xa097, 0x0de8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1648, 0x00000000); - nv_mthd(priv, 0xa097, 0x12a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x1120, 0x00000000); - nv_mthd(priv, 0xa097, 0x1124, 0x00000000); - nv_mthd(priv, 0xa097, 0x1128, 0x00000000); - nv_mthd(priv, 0xa097, 0x112c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1118, 0x00000000); - nv_mthd(priv, 0xa097, 0x164c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1658, 0x00000000); - nv_mthd(priv, 0xa097, 0x1910, 0x00000290); - nv_mthd(priv, 0xa097, 0x1518, 0x00000000); - nv_mthd(priv, 0xa097, 0x165c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1520, 0x00000000); - nv_mthd(priv, 0xa097, 0x1604, 0x00000000); - nv_mthd(priv, 0xa097, 0x1570, 0x00000000); - nv_mthd(priv, 0xa097, 0x13b0, 0x3f800000); - nv_mthd(priv, 0xa097, 0x13b4, 0x3f800000); - nv_mthd(priv, 0xa097, 0x020c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1670, 0x30201000); - nv_mthd(priv, 0xa097, 0x1674, 0x70605040); - nv_mthd(priv, 0xa097, 0x1678, 0xb8a89888); - nv_mthd(priv, 0xa097, 0x167c, 0xf8e8d8c8); - nv_mthd(priv, 0xa097, 0x166c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1680, 0x00ffff00); - nv_mthd(priv, 0xa097, 0x12d0, 0x00000003); - nv_mthd(priv, 0xa097, 0x12d4, 0x00000002); - nv_mthd(priv, 0xa097, 0x1684, 0x00000000); - nv_mthd(priv, 0xa097, 0x1688, 0x00000000); - nv_mthd(priv, 0xa097, 0x0dac, 0x00001b02); - nv_mthd(priv, 0xa097, 0x0db0, 0x00001b02); - nv_mthd(priv, 0xa097, 0x0db4, 0x00000000); - nv_mthd(priv, 0xa097, 0x168c, 0x00000000); - nv_mthd(priv, 0xa097, 0x15bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x156c, 0x00000000); - nv_mthd(priv, 0xa097, 0x187c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1110, 0x00000001); - nv_mthd(priv, 0xa097, 0x0dc0, 0x00000000); - nv_mthd(priv, 0xa097, 0x0dc4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0dc8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1234, 0x00000000); - nv_mthd(priv, 0xa097, 0x1690, 0x00000000); - nv_mthd(priv, 0xa097, 0x12ac, 0x00000001); - nv_mthd(priv, 0xa097, 0x0790, 0x00000000); - nv_mthd(priv, 0xa097, 0x0794, 0x00000000); - nv_mthd(priv, 0xa097, 0x0798, 0x00000000); - nv_mthd(priv, 0xa097, 0x079c, 0x00000000); - nv_mthd(priv, 0xa097, 0x07a0, 0x00000000); - nv_mthd(priv, 0xa097, 0x077c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1000, 0x00000010); - nv_mthd(priv, 0xa097, 0x10fc, 0x00000000); - nv_mthd(priv, 0xa097, 0x1290, 0x00000000); - nv_mthd(priv, 0xa097, 0x0218, 0x00000010); - nv_mthd(priv, 0xa097, 0x12d8, 0x00000000); - nv_mthd(priv, 0xa097, 0x12dc, 0x00000010); - nv_mthd(priv, 0xa097, 0x0d94, 0x00000001); - nv_mthd(priv, 0xa097, 0x155c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1560, 0x00000000); - nv_mthd(priv, 0xa097, 0x1564, 0x00000fff); - nv_mthd(priv, 0xa097, 0x1574, 0x00000000); - nv_mthd(priv, 0xa097, 0x1578, 0x00000000); - nv_mthd(priv, 0xa097, 0x157c, 0x000fffff); - nv_mthd(priv, 0xa097, 0x1354, 0x00000000); - nv_mthd(priv, 0xa097, 0x1610, 0x00000012); - nv_mthd(priv, 0xa097, 0x1608, 0x00000000); - nv_mthd(priv, 0xa097, 0x160c, 0x00000000); - nv_mthd(priv, 0xa097, 0x260c, 0x00000000); - nv_mthd(priv, 0xa097, 0x07ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x162c, 0x00000003); - nv_mthd(priv, 0xa097, 0x0210, 0x00000000); - nv_mthd(priv, 0xa097, 0x0320, 0x00000000); - nv_mthd(priv, 0xa097, 0x0324, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0328, 0x3f800000); - nv_mthd(priv, 0xa097, 0x032c, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0330, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0334, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0338, 0x3f800000); - nv_mthd(priv, 0xa097, 0x0750, 0x00000000); - nv_mthd(priv, 0xa097, 0x0760, 0x39291909); - nv_mthd(priv, 0xa097, 0x0764, 0x79695949); - nv_mthd(priv, 0xa097, 0x0768, 0xb9a99989); - nv_mthd(priv, 0xa097, 0x076c, 0xf9e9d9c9); - nv_mthd(priv, 0xa097, 0x0770, 0x30201000); - nv_mthd(priv, 0xa097, 0x0774, 0x70605040); - nv_mthd(priv, 0xa097, 0x0778, 0x00009080); - nv_mthd(priv, 0xa097, 0x0780, 0x39291909); - nv_mthd(priv, 0xa097, 0x0784, 0x79695949); - nv_mthd(priv, 0xa097, 0x0788, 0xb9a99989); - nv_mthd(priv, 0xa097, 0x078c, 0xf9e9d9c9); - nv_mthd(priv, 0xa097, 0x07d0, 0x30201000); - nv_mthd(priv, 0xa097, 0x07d4, 0x70605040); - nv_mthd(priv, 0xa097, 0x07d8, 0x00009080); - nv_mthd(priv, 0xa097, 0x037c, 0x00000001); - nv_mthd(priv, 0xa097, 0x0740, 0x00000000); - nv_mthd(priv, 0xa097, 0x0744, 0x00000000); - nv_mthd(priv, 0xa097, 0x2600, 0x00000000); - nv_mthd(priv, 0xa097, 0x1918, 0x00000000); - nv_mthd(priv, 0xa097, 0x191c, 0x00000900); - nv_mthd(priv, 0xa097, 0x1920, 0x00000405); - nv_mthd(priv, 0xa097, 0x1308, 0x00000001); - nv_mthd(priv, 0xa097, 0x1924, 0x00000000); - nv_mthd(priv, 0xa097, 0x13ac, 0x00000000); - nv_mthd(priv, 0xa097, 0x192c, 0x00000001); - nv_mthd(priv, 0xa097, 0x193c, 0x00002c1c); - nv_mthd(priv, 0xa097, 0x0d7c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x02c0, 0x00000001); - nv_mthd(priv, 0xa097, 0x1510, 0x00000000); - nv_mthd(priv, 0xa097, 0x1940, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ff4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0ff8, 0x00000000); - nv_mthd(priv, 0xa097, 0x194c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1950, 0x00000000); - nv_mthd(priv, 0xa097, 0x1968, 0x00000000); - nv_mthd(priv, 0xa097, 0x1590, 0x0000003f); - nv_mthd(priv, 0xa097, 0x07e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x07ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x07f0, 0x00000000); - nv_mthd(priv, 0xa097, 0x07f4, 0x00000000); - nv_mthd(priv, 0xa097, 0x196c, 0x00000011); - nv_mthd(priv, 0xa097, 0x02e4, 0x0000b001); - nv_mthd(priv, 0xa097, 0x036c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0370, 0x00000000); - nv_mthd(priv, 0xa097, 0x197c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fcc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fd0, 0x00000000); - nv_mthd(priv, 0xa097, 0x02d8, 0x00000040); - nv_mthd(priv, 0xa097, 0x1980, 0x00000080); - nv_mthd(priv, 0xa097, 0x1504, 0x00000080); - nv_mthd(priv, 0xa097, 0x1984, 0x00000000); - nv_mthd(priv, 0xa097, 0x0300, 0x00000001); - nv_mthd(priv, 0xa097, 0x13a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x12ec, 0x00000000); - nv_mthd(priv, 0xa097, 0x1310, 0x00000000); - nv_mthd(priv, 0xa097, 0x1314, 0x00000001); - nv_mthd(priv, 0xa097, 0x1380, 0x00000000); - nv_mthd(priv, 0xa097, 0x1384, 0x00000001); - nv_mthd(priv, 0xa097, 0x1388, 0x00000001); - nv_mthd(priv, 0xa097, 0x138c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1390, 0x00000001); - nv_mthd(priv, 0xa097, 0x1394, 0x00000000); - nv_mthd(priv, 0xa097, 0x139c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1398, 0x00000000); - nv_mthd(priv, 0xa097, 0x1594, 0x00000000); - nv_mthd(priv, 0xa097, 0x1598, 0x00000001); - nv_mthd(priv, 0xa097, 0x159c, 0x00000001); - nv_mthd(priv, 0xa097, 0x15a0, 0x00000001); - nv_mthd(priv, 0xa097, 0x15a4, 0x00000001); - nv_mthd(priv, 0xa097, 0x0f54, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f58, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f5c, 0x00000000); - nv_mthd(priv, 0xa097, 0x19bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f9c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0fa0, 0x00000000); - nv_mthd(priv, 0xa097, 0x12cc, 0x00000000); - nv_mthd(priv, 0xa097, 0x12e8, 0x00000000); - nv_mthd(priv, 0xa097, 0x130c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1360, 0x00000000); - nv_mthd(priv, 0xa097, 0x1364, 0x00000000); - nv_mthd(priv, 0xa097, 0x1368, 0x00000000); - nv_mthd(priv, 0xa097, 0x136c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1370, 0x00000000); - nv_mthd(priv, 0xa097, 0x1374, 0x00000000); - nv_mthd(priv, 0xa097, 0x1378, 0x00000000); - nv_mthd(priv, 0xa097, 0x137c, 0x00000000); - nv_mthd(priv, 0xa097, 0x133c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1340, 0x00000001); - nv_mthd(priv, 0xa097, 0x1344, 0x00000002); - nv_mthd(priv, 0xa097, 0x1348, 0x00000001); - nv_mthd(priv, 0xa097, 0x134c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1350, 0x00000002); - nv_mthd(priv, 0xa097, 0x1358, 0x00000001); - nv_mthd(priv, 0xa097, 0x12e4, 0x00000000); - nv_mthd(priv, 0xa097, 0x131c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1320, 0x00000000); - nv_mthd(priv, 0xa097, 0x1324, 0x00000000); - nv_mthd(priv, 0xa097, 0x1328, 0x00000000); - nv_mthd(priv, 0xa097, 0x19c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x1140, 0x00000000); - nv_mthd(priv, 0xa097, 0x19c4, 0x00000000); - nv_mthd(priv, 0xa097, 0x19c8, 0x00001500); - nv_mthd(priv, 0xa097, 0x135c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f90, 0x00000000); - nv_mthd(priv, 0xa097, 0x19e0, 0x00000001); - nv_mthd(priv, 0xa097, 0x19e4, 0x00000001); - nv_mthd(priv, 0xa097, 0x19e8, 0x00000001); - nv_mthd(priv, 0xa097, 0x19ec, 0x00000001); - nv_mthd(priv, 0xa097, 0x19f0, 0x00000001); - nv_mthd(priv, 0xa097, 0x19f4, 0x00000001); - nv_mthd(priv, 0xa097, 0x19f8, 0x00000001); - nv_mthd(priv, 0xa097, 0x19fc, 0x00000001); - nv_mthd(priv, 0xa097, 0x19cc, 0x00000001); - nv_mthd(priv, 0xa097, 0x15b8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a00, 0x00001111); - nv_mthd(priv, 0xa097, 0x1a04, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a08, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a0c, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a10, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a14, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a18, 0x00000000); - nv_mthd(priv, 0xa097, 0x1a1c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d6c, 0xffff0000); - nv_mthd(priv, 0xa097, 0x0d70, 0xffff0000); - nv_mthd(priv, 0xa097, 0x10f8, 0x00001010); - nv_mthd(priv, 0xa097, 0x0d80, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d84, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d88, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d8c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0d90, 0x00000000); - nv_mthd(priv, 0xa097, 0x0da0, 0x00000000); - nv_mthd(priv, 0xa097, 0x07a4, 0x00000000); - nv_mthd(priv, 0xa097, 0x07a8, 0x00000000); - nv_mthd(priv, 0xa097, 0x1508, 0x80000000); - nv_mthd(priv, 0xa097, 0x150c, 0x40000000); - nv_mthd(priv, 0xa097, 0x1668, 0x00000000); - nv_mthd(priv, 0xa097, 0x0318, 0x00000008); - nv_mthd(priv, 0xa097, 0x031c, 0x00000008); - nv_mthd(priv, 0xa097, 0x0d9c, 0x00000001); - nv_mthd(priv, 0xa097, 0x0374, 0x00000000); - nv_mthd(priv, 0xa097, 0x0378, 0x00000020); - nv_mthd(priv, 0xa097, 0x07dc, 0x00000000); - nv_mthd(priv, 0xa097, 0x074c, 0x00000055); - nv_mthd(priv, 0xa097, 0x1420, 0x00000003); - nv_mthd(priv, 0xa097, 0x17bc, 0x00000000); - nv_mthd(priv, 0xa097, 0x17c0, 0x00000000); - nv_mthd(priv, 0xa097, 0x17c4, 0x00000001); - nv_mthd(priv, 0xa097, 0x1008, 0x00000008); - nv_mthd(priv, 0xa097, 0x100c, 0x00000040); - nv_mthd(priv, 0xa097, 0x1010, 0x0000012c); - nv_mthd(priv, 0xa097, 0x0d60, 0x00000040); - nv_mthd(priv, 0xa097, 0x075c, 0x00000003); - nv_mthd(priv, 0xa097, 0x1018, 0x00000020); - nv_mthd(priv, 0xa097, 0x101c, 0x00000001); - nv_mthd(priv, 0xa097, 0x1020, 0x00000020); - nv_mthd(priv, 0xa097, 0x1024, 0x00000001); - nv_mthd(priv, 0xa097, 0x1444, 0x00000000); - nv_mthd(priv, 0xa097, 0x1448, 0x00000000); - nv_mthd(priv, 0xa097, 0x144c, 0x00000000); - nv_mthd(priv, 0xa097, 0x0360, 0x20164010); - nv_mthd(priv, 0xa097, 0x0364, 0x00000020); - nv_mthd(priv, 0xa097, 0x0368, 0x00000000); - nv_mthd(priv, 0xa097, 0x0de4, 0x00000000); - nv_mthd(priv, 0xa097, 0x0204, 0x00000006); - nv_mthd(priv, 0xa097, 0x0208, 0x00000000); - nv_mthd(priv, 0xa097, 0x02cc, 0x003fffff); - nv_mthd(priv, 0xa097, 0x02d0, 0x003fffff); - nv_mthd(priv, 0xa097, 0x1220, 0x00000005); - nv_mthd(priv, 0xa097, 0x0fdc, 0x00000000); - nv_mthd(priv, 0xa097, 0x0f98, 0x00400008); - nv_mthd(priv, 0xa097, 0x1284, 0x08000080); - nv_mthd(priv, 0xa097, 0x1450, 0x00400008); - nv_mthd(priv, 0xa097, 0x1454, 0x08000080); - nv_mthd(priv, 0xa097, 0x0214, 0x00000000); -} - -static void -nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) -{ - nv_mthd(priv, 0x902d, 0x0200, 0x000000cf); - nv_mthd(priv, 0x902d, 0x0204, 0x00000001); - nv_mthd(priv, 0x902d, 0x0208, 0x00000020); - nv_mthd(priv, 0x902d, 0x020c, 0x00000001); - nv_mthd(priv, 0x902d, 0x0210, 0x00000000); - nv_mthd(priv, 0x902d, 0x0214, 0x00000080); - nv_mthd(priv, 0x902d, 0x0218, 0x00000100); - nv_mthd(priv, 0x902d, 0x021c, 0x00000100); - nv_mthd(priv, 0x902d, 0x0220, 0x00000000); - nv_mthd(priv, 0x902d, 0x0224, 0x00000000); - nv_mthd(priv, 0x902d, 0x0230, 0x000000cf); - nv_mthd(priv, 0x902d, 0x0234, 0x00000001); - nv_mthd(priv, 0x902d, 0x0238, 0x00000020); - nv_mthd(priv, 0x902d, 0x023c, 0x00000001); - nv_mthd(priv, 0x902d, 0x0244, 0x00000080); - nv_mthd(priv, 0x902d, 0x0248, 0x00000100); - nv_mthd(priv, 0x902d, 0x024c, 0x00000100); - switch (nv_device(priv)->chipset) { - case 0xe6: - nv_mthd(priv, 0x902d, 0x3410, 0x80002006); - break; - case 0xe4: - case 0xe7: - default: - nv_mthd(priv, 0x902d, 0x3410, 0x00000000); - break; - } -} - -static void -nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x404004, 0x00000000); - nv_wr32(priv, 0x404008, 0x00000000); - nv_wr32(priv, 0x40400c, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x404010, 0x0); - nv_wr32(priv, 0x404014, 0x0); - nv_wr32(priv, 0x404018, 0x0); - nv_wr32(priv, 0x40401c, 0x0); - nv_wr32(priv, 0x404020, 0x0); - nv_wr32(priv, 0x404024, 0xe000); - nv_wr32(priv, 0x404028, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x40402c, 0x00000000); - nv_wr32(priv, 0x404030, 0x00000000); - nv_wr32(priv, 0x404034, 0x00000000); - nv_wr32(priv, 0x404038, 0x00000000); - nv_wr32(priv, 0x40403c, 0x00000000); - nv_wr32(priv, 0x404040, 0x00000000); - nv_wr32(priv, 0x404044, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x4040a8, 0x0); - nv_wr32(priv, 0x4040ac, 0x0); - nv_wr32(priv, 0x4040b0, 0x0); - nv_wr32(priv, 0x4040b4, 0x0); - nv_wr32(priv, 0x4040b8, 0x0); - nv_wr32(priv, 0x4040bc, 0x0); - nv_wr32(priv, 0x4040c0, 0x0); - nv_wr32(priv, 0x4040c4, 0x0); - nv_wr32(priv, 0x4040c8, 0xf800008f); - nv_wr32(priv, 0x4040d0, 0x0); - nv_wr32(priv, 0x4040d4, 0x0); - nv_wr32(priv, 0x4040d8, 0x0); - nv_wr32(priv, 0x4040dc, 0x0); - nv_wr32(priv, 0x4040e0, 0x0); - nv_wr32(priv, 0x4040e4, 0x0); - nv_wr32(priv, 0x4040e8, 0x1000); - nv_wr32(priv, 0x4040f8, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x404100, 0x00000000); - nv_wr32(priv, 0x404104, 0x00000000); - nv_wr32(priv, 0x404108, 0x00000000); - nv_wr32(priv, 0x40410c, 0x00000000); - nv_wr32(priv, 0x404110, 0x00000000); - nv_wr32(priv, 0x404114, 0x00000000); - nv_wr32(priv, 0x404118, 0x00000000); - nv_wr32(priv, 0x40411c, 0x00000000); - nv_wr32(priv, 0x404120, 0x00000000); - nv_wr32(priv, 0x404124, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x404130, 0x0); - nv_wr32(priv, 0x404134, 0x0); - nv_wr32(priv, 0x404138, 0x20000040); - nv_wr32(priv, 0x404150, 0x2e); - nv_wr32(priv, 0x404154, 0x400); - nv_wr32(priv, 0x404158, 0x200); - nv_wr32(priv, 0x404164, 0x55); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x40417c, 0x00000000); - nv_wr32(priv, 0x404180, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x4041a0, 0x0); - nv_wr32(priv, 0x4041a4, 0x0); - nv_wr32(priv, 0x4041a8, 0x0); - nv_wr32(priv, 0x4041ac, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x404200, 0xa197); - nv_wr32(priv, 0x404204, 0xa1c0); - nv_wr32(priv, 0x404208, 0xa140); - nv_wr32(priv, 0x40420c, 0x902d); - break; - default: - nv_wr32(priv, 0x404200, 0x0); - nv_wr32(priv, 0x404204, 0x0); - nv_wr32(priv, 0x404208, 0x0); - nv_wr32(priv, 0x40420c, 0x0); - break; - } -} - -static void -nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404404, 0x0); - nv_wr32(priv, 0x404408, 0x0); - nv_wr32(priv, 0x40440c, 0x0); - nv_wr32(priv, 0x404410, 0x0); - nv_wr32(priv, 0x404414, 0x0); - nv_wr32(priv, 0x404418, 0x0); - nv_wr32(priv, 0x40441c, 0x0); - nv_wr32(priv, 0x404420, 0x0); - nv_wr32(priv, 0x404424, 0x0); - nv_wr32(priv, 0x404428, 0x0); - nv_wr32(priv, 0x40442c, 0x0); - nv_wr32(priv, 0x404430, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - break; - default: - nv_wr32(priv, 0x404434, 0x0); - break; - } - nv_wr32(priv, 0x404438, 0x0); - nv_wr32(priv, 0x404460, 0x0); - nv_wr32(priv, 0x404464, 0x0); - nv_wr32(priv, 0x404468, 0xffffff); - nv_wr32(priv, 0x40446c, 0x0); - nv_wr32(priv, 0x404480, 0x1); - nv_wr32(priv, 0x404498, 0x1); -} - -static void -nve0_graph_generate_unk46xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404604, 0x14); - nv_wr32(priv, 0x404608, 0x0); - nv_wr32(priv, 0x40460c, 0x3fff); - nv_wr32(priv, 0x404610, 0x100); - nv_wr32(priv, 0x404618, 0x0); - nv_wr32(priv, 0x40461c, 0x0); - nv_wr32(priv, 0x404620, 0x0); - nv_wr32(priv, 0x404624, 0x0); - nv_wr32(priv, 0x40462c, 0x0); - nv_wr32(priv, 0x404630, 0x0); - nv_wr32(priv, 0x404640, 0x0); - nv_wr32(priv, 0x404654, 0x0); - nv_wr32(priv, 0x404660, 0x0); - nv_wr32(priv, 0x404678, 0x0); - nv_wr32(priv, 0x40467c, 0x2); - nv_wr32(priv, 0x404680, 0x0); - nv_wr32(priv, 0x404684, 0x0); - nv_wr32(priv, 0x404688, 0x0); - nv_wr32(priv, 0x40468c, 0x0); - nv_wr32(priv, 0x404690, 0x0); - nv_wr32(priv, 0x404694, 0x0); - nv_wr32(priv, 0x404698, 0x0); - nv_wr32(priv, 0x40469c, 0x0); - nv_wr32(priv, 0x4046a0, 0x7f0080); - nv_wr32(priv, 0x4046a4, 0x0); - nv_wr32(priv, 0x4046a8, 0x0); - nv_wr32(priv, 0x4046ac, 0x0); - nv_wr32(priv, 0x4046b0, 0x0); - nv_wr32(priv, 0x4046b4, 0x0); - nv_wr32(priv, 0x4046b8, 0x0); - nv_wr32(priv, 0x4046bc, 0x0); - nv_wr32(priv, 0x4046c0, 0x0); - nv_wr32(priv, 0x4046c8, 0x0); - nv_wr32(priv, 0x4046cc, 0x0); - nv_wr32(priv, 0x4046d0, 0x0); -} - -static void -nve0_graph_generate_unk47xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404700, 0x0); - nv_wr32(priv, 0x404704, 0x0); - nv_wr32(priv, 0x404708, 0x0); - nv_wr32(priv, 0x404718, 0x0); - nv_wr32(priv, 0x40471c, 0x0); - nv_wr32(priv, 0x404720, 0x0); - nv_wr32(priv, 0x404724, 0x0); - nv_wr32(priv, 0x404728, 0x0); - nv_wr32(priv, 0x40472c, 0x0); - nv_wr32(priv, 0x404730, 0x0); - nv_wr32(priv, 0x404734, 0x100); - nv_wr32(priv, 0x404738, 0x0); - nv_wr32(priv, 0x40473c, 0x0); - nv_wr32(priv, 0x404744, 0x0); - nv_wr32(priv, 0x404748, 0x0); - nv_wr32(priv, 0x404754, 0x0); -} - -static void -nve0_graph_generate_unk58xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x405800, 0xf8000bf); - nv_wr32(priv, 0x405830, 0x2180648); - nv_wr32(priv, 0x405834, 0x8000000); - nv_wr32(priv, 0x405838, 0x0); - nv_wr32(priv, 0x405854, 0x0); - nv_wr32(priv, 0x405870, 0x1); - nv_wr32(priv, 0x405874, 0x1); - nv_wr32(priv, 0x405878, 0x1); - nv_wr32(priv, 0x40587c, 0x1); - nv_wr32(priv, 0x405a00, 0x0); - nv_wr32(priv, 0x405a04, 0x0); - nv_wr32(priv, 0x405a18, 0x0); -} - -static void -nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x405b00, 0x0); - nv_wr32(priv, 0x405b10, 0x1000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x405b20, 0x04000000); - break; - default: - break; - } -} - -static void -nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x406020, 0x34103c1); - break; - default: - nv_wr32(priv, 0x406020, 0x4103c1); - break; - } - nv_wr32(priv, 0x406028, 0x1); - nv_wr32(priv, 0x40602c, 0x1); - nv_wr32(priv, 0x406030, 0x1); - nv_wr32(priv, 0x406034, 0x1); -} - -static void -nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x4064a8, 0x0); - nv_wr32(priv, 0x4064ac, 0x3fff); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x4064b0, 0x0); - break; - default: - break; - } - nv_wr32(priv, 0x4064b4, 0x0); - nv_wr32(priv, 0x4064b8, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x4064c0, 0x802000f0); - nv_wr32(priv, 0x4064c4, 0x192ffff); - nv_wr32(priv, 0x4064c8, 0x18007c0); - break; - default: - nv_wr32(priv, 0x4064c0, 0x801a00f0); - nv_wr32(priv, 0x4064c4, 0x192ffff); - nv_wr32(priv, 0x4064c8, 0x1800600); - break; - } - nv_wr32(priv, 0x4064cc, 0x0); - nv_wr32(priv, 0x4064d0, 0x0); - nv_wr32(priv, 0x4064d4, 0x0); - nv_wr32(priv, 0x4064d8, 0x0); - nv_wr32(priv, 0x4064dc, 0x0); - nv_wr32(priv, 0x4064e0, 0x0); - nv_wr32(priv, 0x4064e4, 0x0); - nv_wr32(priv, 0x4064e8, 0x0); - nv_wr32(priv, 0x4064ec, 0x0); - nv_wr32(priv, 0x4064fc, 0x22a); -} - -static void -nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xf0: - break; - default: - nv_wr32(priv, 0x407040, 0x0); - break; - } -} - -static void -nve0_graph_generate_unk78xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x407804, 0x23); - nv_wr32(priv, 0x40780c, 0xa418820); - nv_wr32(priv, 0x407810, 0x62080e6); - nv_wr32(priv, 0x407814, 0x20398a4); - nv_wr32(priv, 0x407818, 0xe629062); - nv_wr32(priv, 0x40781c, 0xa418820); - nv_wr32(priv, 0x407820, 0xe6); - nv_wr32(priv, 0x4078bc, 0x103); -} - -static void -nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x408000, 0x0); - nv_wr32(priv, 0x408004, 0x0); - nv_wr32(priv, 0x408008, 0x30); - nv_wr32(priv, 0x40800c, 0x0); - nv_wr32(priv, 0x408010, 0x0); - nv_wr32(priv, 0x408014, 0x69); - nv_wr32(priv, 0x408018, 0xe100e100); - nv_wr32(priv, 0x408064, 0x0); -} - -static void -nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x408800, 0x12802a3c); - break; - default: - nv_wr32(priv, 0x408800, 0x2802a3c); - break; - } - nv_wr32(priv, 0x408804, 0x40); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x408808, 0x1003e005); - break; - default: - nv_wr32(priv, 0x408808, 0x1043e005); - break; - } - nv_wr32(priv, 0x408840, 0xb); - nv_wr32(priv, 0x408900, 0x3080b801); - nv_wr32(priv, 0x408904, 0x62000001); - nv_wr32(priv, 0x408908, 0xc8102f); - nv_wr32(priv, 0x408980, 0x11d); -} - -static void -nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) -{ - int i; - - nv_wr32(priv, 0x418380, 0x16); - nv_wr32(priv, 0x418400, 0x38004e00); - nv_wr32(priv, 0x418404, 0x71e0ffff); - nv_wr32(priv, 0x41840c, 0x1008); - nv_wr32(priv, 0x418410, 0xfff0fff); - nv_wr32(priv, 0x418414, 0x2200fff); - nv_wr32(priv, 0x418450, 0x0); - nv_wr32(priv, 0x418454, 0x0); - nv_wr32(priv, 0x418458, 0x0); - nv_wr32(priv, 0x41845c, 0x0); - nv_wr32(priv, 0x418460, 0x0); - nv_wr32(priv, 0x418464, 0x0); - nv_wr32(priv, 0x418468, 0x1); - nv_wr32(priv, 0x41846c, 0x0); - nv_wr32(priv, 0x418470, 0x0); - nv_wr32(priv, 0x418600, 0x1f); - nv_wr32(priv, 0x418684, 0xf); - nv_wr32(priv, 0x418700, 0x2); - nv_wr32(priv, 0x418704, 0x80); - nv_wr32(priv, 0x418708, 0x0); - nv_wr32(priv, 0x41870c, 0x0); - nv_wr32(priv, 0x418710, 0x0); - nv_wr32(priv, 0x418800, 0x7006860a); - nv_wr32(priv, 0x418808, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x41880c, 0x30); - break; - default: - nv_wr32(priv, 0x41880c, 0x0); - break; - } - nv_wr32(priv, 0x418810, 0x0); - nv_wr32(priv, 0x418828, 0x44); - nv_wr32(priv, 0x418830, 0x10000001); - nv_wr32(priv, 0x4188d8, 0x8); - nv_wr32(priv, 0x4188e0, 0x1000000); - nv_wr32(priv, 0x4188e8, 0x0); - nv_wr32(priv, 0x4188ec, 0x0); - nv_wr32(priv, 0x4188f0, 0x0); - nv_wr32(priv, 0x4188f4, 0x0); - nv_wr32(priv, 0x4188f8, 0x0); - nv_wr32(priv, 0x4188fc, 0x20100018); - nv_wr32(priv, 0x41891c, 0xff00ff); - nv_wr32(priv, 0x418924, 0x0); - nv_wr32(priv, 0x418928, 0xffff00); - nv_wr32(priv, 0x41892c, 0xff00); - for (i = 0; i < 8; i++) { - nv_wr32(priv, 0x418a00 + (i * 0x20), 0x0); - nv_wr32(priv, 0x418a04 + (i * 0x20), 0x0); - nv_wr32(priv, 0x418a08 + (i * 0x20), 0x0); - nv_wr32(priv, 0x418a0c + (i * 0x20), 0x10000); - nv_wr32(priv, 0x418a10 + (i * 0x20), 0x0); - nv_wr32(priv, 0x418a14 + (i * 0x20), 0x0); - nv_wr32(priv, 0x418a18 + (i * 0x20), 0x0); - } - nv_wr32(priv, 0x418b00, 0x6); - nv_wr32(priv, 0x418b08, 0xa418820); - nv_wr32(priv, 0x418b0c, 0x62080e6); - nv_wr32(priv, 0x418b10, 0x20398a4); - nv_wr32(priv, 0x418b14, 0xe629062); - nv_wr32(priv, 0x418b18, 0xa418820); - nv_wr32(priv, 0x418b1c, 0xe6); - nv_wr32(priv, 0x418bb8, 0x103); - nv_wr32(priv, 0x418c08, 0x1); - nv_wr32(priv, 0x418c10, 0x0); - nv_wr32(priv, 0x418c14, 0x0); - nv_wr32(priv, 0x418c18, 0x0); - nv_wr32(priv, 0x418c1c, 0x0); - nv_wr32(priv, 0x418c20, 0x0); - nv_wr32(priv, 0x418c24, 0x0); - nv_wr32(priv, 0x418c28, 0x0); - nv_wr32(priv, 0x418c2c, 0x0); - nv_wr32(priv, 0x418c40, 0xffffffff); - nv_wr32(priv, 0x418c6c, 0x1); - nv_wr32(priv, 0x418c80, 0x20200004); - nv_wr32(priv, 0x418c8c, 0x1); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x418d24, 0x0); - break; - default: - break; - } - nv_wr32(priv, 0x419000, 0x780); - nv_wr32(priv, 0x419004, 0x0); - nv_wr32(priv, 0x419008, 0x0); - nv_wr32(priv, 0x419014, 0x4); -} - -static void -nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x419848, 0x0); - nv_wr32(priv, 0x419864, 0x129); - nv_wr32(priv, 0x419888, 0x0); - nv_wr32(priv, 0x419a00, 0xf0); - nv_wr32(priv, 0x419a04, 0x1); - nv_wr32(priv, 0x419a08, 0x21); - nv_wr32(priv, 0x419a0c, 0x20000); - nv_wr32(priv, 0x419a10, 0x0); - nv_wr32(priv, 0x419a14, 0x200); - nv_wr32(priv, 0x419a1c, 0xc000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419a20, 0x20800); - break; - default: - nv_wr32(priv, 0x419a20, 0x800); - break; - } - nv_wr32(priv, 0x419a30, 0x1); - nv_wr32(priv, 0x419ac4, 0x37f440); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419c00, 0x1a); - break; - default: - nv_wr32(priv, 0x419c00, 0xa); - break; - } - nv_wr32(priv, 0x419c04, 0x80000006); - nv_wr32(priv, 0x419c08, 0x2); - nv_wr32(priv, 0x419c20, 0x0); - nv_wr32(priv, 0x419c24, 0x84210); - nv_wr32(priv, 0x419c28, 0x3efbefbe); - nv_wr32(priv, 0x419ce8, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419cf4, 0x203); - nv_wr32(priv, 0x419e04, 0x0); - nv_wr32(priv, 0x419e08, 0x1d); - nv_wr32(priv, 0x419e0c, 0x0); - nv_wr32(priv, 0x419e10, 0x1c02); - - break; - default: - nv_wr32(priv, 0x419cf4, 0x3203); - nv_wr32(priv, 0x419e04, 0x0); - nv_wr32(priv, 0x419e08, 0x0); - nv_wr32(priv, 0x419e0c, 0x0); - nv_wr32(priv, 0x419e10, 0x402); - break; - } - nv_wr32(priv, 0x419e44, 0x13eff2); - nv_wr32(priv, 0x419e48, 0x0); - nv_wr32(priv, 0x419e4c, 0x7f); - nv_wr32(priv, 0x419e50, 0x0); - nv_wr32(priv, 0x419e54, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419e58, 0x1); - break; - default: - nv_wr32(priv, 0x419e58, 0x0); - break; - } - nv_wr32(priv, 0x419e5c, 0x0); - nv_wr32(priv, 0x419e60, 0x0); - nv_wr32(priv, 0x419e64, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419e68, 0x2); - break; - default: - nv_wr32(priv, 0x419e68, 0x0); - break; - } - nv_wr32(priv, 0x419e6c, 0x0); - nv_wr32(priv, 0x419e70, 0x0); - nv_wr32(priv, 0x419e74, 0x0); - nv_wr32(priv, 0x419e78, 0x0); - nv_wr32(priv, 0x419e7c, 0x0); - nv_wr32(priv, 0x419e80, 0x0); - nv_wr32(priv, 0x419e84, 0x0); - nv_wr32(priv, 0x419e88, 0x0); - nv_wr32(priv, 0x419e8c, 0x0); - nv_wr32(priv, 0x419e90, 0x0); - nv_wr32(priv, 0x419e94, 0x0); - nv_wr32(priv, 0x419e98, 0x0); - switch (nv_device(priv)->chipset) { - case 0xe4: - case 0xe7: - case 0xe6: - nv_wr32(priv, 0x419eac, 0x1f8f); - nv_wr32(priv, 0x419eb0, 0xd3f); - break; - case 0xf0: - nv_wr32(priv, 0x419eac, 0x1fcf); - nv_wr32(priv, 0x419eb0, 0xdb00da0); - nv_wr32(priv, 0x419eb8, 0x0); - break; - } - nv_wr32(priv, 0x419ec8, 0x1304f); - nv_wr32(priv, 0x419f30, 0x0); - nv_wr32(priv, 0x419f34, 0x0); - nv_wr32(priv, 0x419f38, 0x0); - nv_wr32(priv, 0x419f3c, 0x0); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419f40, 0x18); - break; - default: - nv_wr32(priv, 0x419f40, 0x0); - break; - } - nv_wr32(priv, 0x419f44, 0x0); - nv_wr32(priv, 0x419f48, 0x0); - nv_wr32(priv, 0x419f4c, 0x0); - nv_wr32(priv, 0x419f58, 0x0); - switch (nv_device(priv)->chipset) { - case 0xe4: - case 0xe7: - case 0xe6: - nv_wr32(priv, 0x419f70, 0x0); - nv_wr32(priv, 0x419f78, 0xb); - nv_wr32(priv, 0x419f7c, 0x27a); - break; - case 0xf0: - nv_wr32(priv, 0x419f70, 0x7300); - nv_wr32(priv, 0x419f78, 0xeb); - nv_wr32(priv, 0x419f7c, 0x404); - break; - } -} - -static void -nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x41be24, 0x6); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x41bec0, 0x10000000); - break; - default: - nv_wr32(priv, 0x41bec0, 0x12180000); - break; - } - nv_wr32(priv, 0x41bec4, 0x37f7f); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x41bee4, 0x0); - break; - default: - nv_wr32(priv, 0x41bee4, 0x6480430); - break; - } - nv_wr32(priv, 0x41bf00, 0xa418820); - nv_wr32(priv, 0x41bf04, 0x62080e6); - nv_wr32(priv, 0x41bf08, 0x20398a4); - nv_wr32(priv, 0x41bf0c, 0xe629062); - nv_wr32(priv, 0x41bf10, 0xa418820); - nv_wr32(priv, 0x41bf14, 0xe6); - nv_wr32(priv, 0x41bfd0, 0x900103); - nv_wr32(priv, 0x41bfe0, 0x400001); - nv_wr32(priv, 0x41bfe4, 0x0); -} - -int -nve0_grctx_generate(struct nvc0_graph_priv *priv) -{ - struct nvc0_grctx info; - int ret, i, gpc, tpc, id; - u32 data[6] = {}, data2[2] = {}, tmp; - u32 tpc_set = 0, tpc_mask = 0; - u32 magic[GPC_MAX][2], offset; - u8 tpcnr[GPC_MAX], a, b; - u8 shift, ntpcv; - - ret = nvc0_grctx_init(priv, &info); - if (ret) - return ret; - - nv_mask(priv, 0x000260, 0x00000001, 0x00000000); - nv_wr32(priv, 0x400204, 0x00000000); - nv_wr32(priv, 0x400208, 0x00000000); - - nve0_graph_generate_unk40xx(priv); - nve0_graph_generate_unk44xx(priv); - nve0_graph_generate_unk46xx(priv); - nve0_graph_generate_unk47xx(priv); - nve0_graph_generate_unk58xx(priv); - nve0_graph_generate_unk5bxx(priv); - nve0_graph_generate_unk60xx(priv); - nve0_graph_generate_unk64xx(priv); - nve0_graph_generate_unk70xx(priv); - nve0_graph_generate_unk78xx(priv); - nve0_graph_generate_unk80xx(priv); - nve0_graph_generate_unk88xx(priv); - nve0_graph_generate_gpc(priv); - nve0_graph_generate_tpc(priv); - nve0_graph_generate_tpcunk(priv); - - nv_wr32(priv, 0x404154, 0x0); - - mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); - mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); - mmio_list(0x40800c, 0x00000000, 8, 1); - mmio_list(0x408010, 0x80000000, 0, 0); - mmio_list(0x419004, 0x00000000, 8, 1); - mmio_list(0x419008, 0x00000000, 0, 0); - mmio_list(0x4064cc, 0x80000000, 0, 0); - mmio_list(0x408004, 0x00000000, 8, 0); - mmio_list(0x408008, 0x80000030, 0, 0); - mmio_list(0x418808, 0x00000000, 8, 0); - mmio_list(0x41880c, 0x80000030, 0, 0); - mmio_list(0x4064c8, 0x01800600, 0, 0); - mmio_list(0x418810, 0x80000000, 12, 2); - mmio_list(0x419848, 0x10000000, 12, 2); - mmio_list(0x405830, 0x02180648, 0, 0); - mmio_list(0x4064c4, 0x0192ffff, 0, 0); - for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { - u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; - u16 magic1 = 0x0648 * priv->tpc_nr[gpc]; - magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; - magic[gpc][1] = 0x00000000 | (magic1 << 16); - offset += 0x0324 * priv->tpc_nr[gpc]; - } - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); - mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); - offset += 0x07ff * priv->tpc_nr[gpc]; - } - mmio_list(0x17e91c, 0x06060609, 0, 0); - mmio_list(0x17e920, 0x00090a05, 0, 0); - - nv_wr32(priv, 0x418c6c, 0x1); - nv_wr32(priv, 0x41980c, 0x10); - nv_wr32(priv, 0x41be08, 0x4); - nv_wr32(priv, 0x4064c0, 0x801a00f0); - nv_wr32(priv, 0x405800, 0xf8000bf); - nv_wr32(priv, 0x419c00, 0xa); - - for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0698), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x04e8), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0088), id++); - } - - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); - } - } - - tmp = 0; - for (i = 0; i < priv->gpc_nr; i++) - tmp |= priv->tpc_nr[i] << (i * 4); - nv_wr32(priv, 0x406028, tmp); - nv_wr32(priv, 0x405870, tmp); - - nv_wr32(priv, 0x40602c, 0x0); - nv_wr32(priv, 0x405874, 0x0); - nv_wr32(priv, 0x406030, 0x0); - nv_wr32(priv, 0x405878, 0x0); - nv_wr32(priv, 0x406034, 0x0); - nv_wr32(priv, 0x40587c, 0x0); - - /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - - gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpcnr[gpc]--; - - data[tpc / 6] |= gpc << ((tpc % 6) * 5); - } - - for (; tpc < 32; tpc++) - data[tpc / 6] |= 7 << ((tpc % 6) * 5); - - /* and the second... */ - shift = 0; - ntpcv = priv->tpc_total; - while (!(ntpcv & (1 << 4))) { - ntpcv <<= 1; - shift++; - } - - data2[0] = ntpcv << 16; - data2[0] |= shift << 21; - data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); - data2[0] |= priv->tpc_total << 8; - data2[0] |= priv->magic_not_rop_nr; - for (i = 1; i < 7; i++) - data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); - - /* and write it all the various parts of PGRAPH */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); - - nv_wr32(priv, 0x41bfd0, data2[0]); - nv_wr32(priv, 0x41bfe4, data2[1]); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); - - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | priv->magic_not_rop_nr); - for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); - - - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) - tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8); - - for (i = 0, gpc = -1, b = -1; i < 32; i++) { - a = (i * (priv->tpc_total - 1)) / 32; - if (a != b) { - b = a; - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - tpc_set |= 1 << ((gpc * 8) + tpc); - } - - nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set); - nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask); - } - - for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); - if (priv->gpc_nr == 1) { - nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); - nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); - } else { - nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); - nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); - } - nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); - - nve0_grctx_generate_icmd(priv); - nve0_grctx_generate_a097(priv); - nve0_grctx_generate_902d(priv); - - nv_mask(priv, 0x000260, 0x00000001, 0x00000001); - nv_wr32(priv, 0x418800, 0x7026860a); //XXX - nv_wr32(priv, 0x41be10, 0x00bb8bc7); //XXX - return nvc0_grctx_fini(&info); -} diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c new file mode 100644 index 000000000000..e2de73ee5eee --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -0,0 +1,1018 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +struct nvc0_graph_init +nve4_grctx_init_icmd[] = { + { 0x001000, 1, 0x01, 0x00000004 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x0000a9, 1, 0x01, 0x0000ffff }, + { 0x000038, 1, 0x01, 0x0fac6881 }, + { 0x00003d, 1, 0x01, 0x00000001 }, + { 0x0000e8, 8, 0x01, 0x00000400 }, + { 0x000078, 8, 0x01, 0x00000300 }, + { 0x000050, 1, 0x01, 0x00000011 }, + { 0x000058, 8, 0x01, 0x00000008 }, + { 0x000208, 8, 0x01, 0x00000001 }, + { 0x000081, 1, 0x01, 0x00000001 }, + { 0x000085, 1, 0x01, 0x00000004 }, + { 0x000088, 1, 0x01, 0x00000400 }, + { 0x000090, 1, 0x01, 0x00000300 }, + { 0x000098, 1, 0x01, 0x00001001 }, + { 0x0000e3, 1, 0x01, 0x00000001 }, + { 0x0000da, 1, 0x01, 0x00000001 }, + { 0x0000f8, 1, 0x01, 0x00000003 }, + { 0x0000fa, 1, 0x01, 0x00000001 }, + { 0x00009f, 4, 0x01, 0x0000ffff }, + { 0x0000b1, 1, 0x01, 0x00000001 }, + { 0x0000ad, 1, 0x01, 0x0000013e }, + { 0x0000e1, 1, 0x01, 0x00000010 }, + { 0x000290, 16, 0x01, 0x00000000 }, + { 0x0003b0, 16, 0x01, 0x00000000 }, + { 0x0002a0, 16, 0x01, 0x00000000 }, + { 0x000420, 16, 0x01, 0x00000000 }, + { 0x0002b0, 16, 0x01, 0x00000000 }, + { 0x000430, 16, 0x01, 0x00000000 }, + { 0x0002c0, 16, 0x01, 0x00000000 }, + { 0x0004d0, 16, 0x01, 0x00000000 }, + { 0x000720, 16, 0x01, 0x00000000 }, + { 0x0008c0, 16, 0x01, 0x00000000 }, + { 0x000890, 16, 0x01, 0x00000000 }, + { 0x0008e0, 16, 0x01, 0x00000000 }, + { 0x0008a0, 16, 0x01, 0x00000000 }, + { 0x0008f0, 16, 0x01, 0x00000000 }, + { 0x00094c, 1, 0x01, 0x000000ff }, + { 0x00094d, 1, 0x01, 0xffffffff }, + { 0x00094e, 1, 0x01, 0x00000002 }, + { 0x0002ec, 1, 0x01, 0x00000001 }, + { 0x000303, 1, 0x01, 0x00000001 }, + { 0x0002e6, 1, 0x01, 0x00000001 }, + { 0x000466, 1, 0x01, 0x00000052 }, + { 0x000301, 1, 0x01, 0x3f800000 }, + { 0x000304, 1, 0x01, 0x30201000 }, + { 0x000305, 1, 0x01, 0x70605040 }, + { 0x000306, 1, 0x01, 0xb8a89888 }, + { 0x000307, 1, 0x01, 0xf8e8d8c8 }, + { 0x00030a, 1, 0x01, 0x00ffff00 }, + { 0x00030b, 1, 0x01, 0x0000001a }, + { 0x00030c, 1, 0x01, 0x00000001 }, + { 0x000318, 1, 0x01, 0x00000001 }, + { 0x000340, 1, 0x01, 0x00000000 }, + { 0x000375, 1, 0x01, 0x00000001 }, + { 0x00037d, 1, 0x01, 0x00000006 }, + { 0x0003a0, 1, 0x01, 0x00000002 }, + { 0x0003aa, 1, 0x01, 0x00000001 }, + { 0x0003a9, 1, 0x01, 0x00000001 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000383, 1, 0x01, 0x00000011 }, + { 0x000360, 1, 0x01, 0x00000040 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x00037a, 1, 0x01, 0x00000012 }, + { 0x000619, 1, 0x01, 0x00000003 }, + { 0x000811, 1, 0x01, 0x00000003 }, + { 0x000812, 1, 0x01, 0x00000004 }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000815, 1, 0x01, 0x0000000b }, + { 0x000800, 6, 0x01, 0x00000001 }, + { 0x000632, 1, 0x01, 0x00000001 }, + { 0x000633, 1, 0x01, 0x00000002 }, + { 0x000634, 1, 0x01, 0x00000003 }, + { 0x000635, 1, 0x01, 0x00000004 }, + { 0x000654, 1, 0x01, 0x3f800000 }, + { 0x000657, 1, 0x01, 0x3f800000 }, + { 0x000655, 2, 0x01, 0x3f800000 }, + { 0x0006cd, 1, 0x01, 0x3f800000 }, + { 0x0007f5, 1, 0x01, 0x3f800000 }, + { 0x0007dc, 1, 0x01, 0x39291909 }, + { 0x0007dd, 1, 0x01, 0x79695949 }, + { 0x0007de, 1, 0x01, 0xb9a99989 }, + { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007e8, 1, 0x01, 0x00003210 }, + { 0x0007e9, 1, 0x01, 0x00007654 }, + { 0x0007ea, 1, 0x01, 0x00000098 }, + { 0x0007ec, 1, 0x01, 0x39291909 }, + { 0x0007ed, 1, 0x01, 0x79695949 }, + { 0x0007ee, 1, 0x01, 0xb9a99989 }, + { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, + { 0x0007f0, 1, 0x01, 0x00003210 }, + { 0x0007f1, 1, 0x01, 0x00007654 }, + { 0x0007f2, 1, 0x01, 0x00000098 }, + { 0x0005a5, 1, 0x01, 0x00000001 }, + { 0x000980, 128, 0x01, 0x00000000 }, + { 0x000468, 1, 0x01, 0x00000004 }, + { 0x00046c, 1, 0x01, 0x00000001 }, + { 0x000470, 96, 0x01, 0x00000000 }, + { 0x000510, 16, 0x01, 0x3f800000 }, + { 0x000520, 1, 0x01, 0x000002b6 }, + { 0x000529, 1, 0x01, 0x00000001 }, + { 0x000530, 16, 0x01, 0xffff0000 }, + { 0x000585, 1, 0x01, 0x0000003f }, + { 0x000576, 1, 0x01, 0x00000003 }, + { 0x00057b, 1, 0x01, 0x00000059 }, + { 0x000586, 1, 0x01, 0x00000040 }, + { 0x000582, 2, 0x01, 0x00000080 }, + { 0x0005c2, 1, 0x01, 0x00000001 }, + { 0x000638, 1, 0x01, 0x00000001 }, + { 0x000639, 1, 0x01, 0x00000001 }, + { 0x00063a, 1, 0x01, 0x00000002 }, + { 0x00063b, 2, 0x01, 0x00000001 }, + { 0x00063d, 1, 0x01, 0x00000002 }, + { 0x00063e, 1, 0x01, 0x00000001 }, + { 0x0008b8, 8, 0x01, 0x00000001 }, + { 0x000900, 8, 0x01, 0x00000001 }, + { 0x000908, 8, 0x01, 0x00000002 }, + { 0x000910, 16, 0x01, 0x00000001 }, + { 0x000920, 8, 0x01, 0x00000002 }, + { 0x000928, 8, 0x01, 0x00000001 }, + { 0x000648, 9, 0x01, 0x00000001 }, + { 0x000658, 1, 0x01, 0x0000000f }, + { 0x0007ff, 1, 0x01, 0x0000000a }, + { 0x00066a, 1, 0x01, 0x40000000 }, + { 0x00066b, 1, 0x01, 0x10000000 }, + { 0x00066c, 2, 0x01, 0xffff0000 }, + { 0x0007af, 2, 0x01, 0x00000008 }, + { 0x0007f6, 1, 0x01, 0x00000001 }, + { 0x0006b2, 1, 0x01, 0x00000055 }, + { 0x0007ad, 1, 0x01, 0x00000003 }, + { 0x000937, 1, 0x01, 0x00000001 }, + { 0x000971, 1, 0x01, 0x00000008 }, + { 0x000972, 1, 0x01, 0x00000040 }, + { 0x000973, 1, 0x01, 0x0000012c }, + { 0x00097c, 1, 0x01, 0x00000040 }, + { 0x000979, 1, 0x01, 0x00000003 }, + { 0x000975, 1, 0x01, 0x00000020 }, + { 0x000976, 1, 0x01, 0x00000001 }, + { 0x000977, 1, 0x01, 0x00000020 }, + { 0x000978, 1, 0x01, 0x00000001 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x00095e, 1, 0x01, 0x20164010 }, + { 0x00095f, 1, 0x01, 0x00000020 }, + { 0x00097d, 1, 0x01, 0x00000020 }, + { 0x000683, 1, 0x01, 0x00000006 }, + { 0x000685, 1, 0x01, 0x003fffff }, + { 0x000687, 1, 0x01, 0x003fffff }, + { 0x0006a0, 1, 0x01, 0x00000005 }, + { 0x000840, 1, 0x01, 0x00400008 }, + { 0x000841, 1, 0x01, 0x08000080 }, + { 0x000842, 1, 0x01, 0x00400008 }, + { 0x000843, 1, 0x01, 0x08000080 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ab, 1, 0x01, 0x00000002 }, + { 0x0006ac, 1, 0x01, 0x00000080 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x0006bb, 1, 0x01, 0x000000cf }, + { 0x0006ce, 1, 0x01, 0x2a712488 }, + { 0x000739, 1, 0x01, 0x4085c000 }, + { 0x00073a, 1, 0x01, 0x00000080 }, + { 0x000786, 1, 0x01, 0x80000100 }, + { 0x00073c, 1, 0x01, 0x00010100 }, + { 0x00073d, 1, 0x01, 0x02800000 }, + { 0x000787, 1, 0x01, 0x000000cf }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x000836, 1, 0x01, 0x00000001 }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x000a0b, 1, 0x01, 0x00000040 }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c1b0, 8, 0x01, 0x0000000f }, + { 0x00c1b8, 1, 0x01, 0x0fac6881 }, + { 0x00c1b9, 1, 0x01, 0x00fac688 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000002 }, + { 0x0006aa, 1, 0x01, 0x00000001 }, + { 0x0006ad, 2, 0x01, 0x00000100 }, + { 0x0006b1, 1, 0x01, 0x00000011 }, + { 0x00078c, 1, 0x01, 0x00000008 }, + { 0x000792, 1, 0x01, 0x00000001 }, + { 0x000794, 1, 0x01, 0x00000001 }, + { 0x000795, 2, 0x01, 0x00000001 }, + { 0x000797, 1, 0x01, 0x000000cf }, + { 0x00079a, 1, 0x01, 0x00000002 }, + { 0x000833, 1, 0x01, 0x04444480 }, + { 0x0007a1, 1, 0x01, 0x00000001 }, + { 0x0007a3, 1, 0x01, 0x00000001 }, + { 0x0007a4, 2, 0x01, 0x00000001 }, + { 0x000831, 1, 0x01, 0x00000004 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000008 }, + { 0x000039, 3, 0x01, 0x00000000 }, + { 0x000380, 1, 0x01, 0x00000001 }, + { 0x000366, 2, 0x01, 0x00000000 }, + { 0x000368, 1, 0x01, 0x00000fff }, + { 0x000370, 2, 0x01, 0x00000000 }, + { 0x000372, 1, 0x01, 0x000fffff }, + { 0x000813, 1, 0x01, 0x00000006 }, + { 0x000814, 1, 0x01, 0x00000008 }, + { 0x000957, 1, 0x01, 0x00000003 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x000a04, 1, 0x01, 0x000000ff }, + { 0x00097f, 1, 0x01, 0x00000100 }, + { 0x000a02, 1, 0x01, 0x00000001 }, + { 0x000809, 1, 0x01, 0x00000007 }, + { 0x00c221, 1, 0x01, 0x00000040 }, + { 0x00c401, 1, 0x01, 0x00000001 }, + { 0x00c402, 1, 0x01, 0x00010001 }, + { 0x00c403, 2, 0x01, 0x00000001 }, + { 0x00c40e, 1, 0x01, 0x00000020 }, + { 0x00c500, 1, 0x01, 0x00000003 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + { 0x001000, 1, 0x01, 0x00000001 }, + { 0x000b07, 1, 0x01, 0x00000002 }, + { 0x000b08, 2, 0x01, 0x00000100 }, + { 0x000b0a, 1, 0x01, 0x00000001 }, + { 0x01e100, 1, 0x01, 0x00000001 }, + {} +}; + +struct nvc0_graph_init +nve4_grctx_init_a097[] = { + { 0x000800, 8, 0x40, 0x00000000 }, + { 0x000804, 8, 0x40, 0x00000000 }, + { 0x000808, 8, 0x40, 0x00000400 }, + { 0x00080c, 8, 0x40, 0x00000300 }, + { 0x000810, 1, 0x04, 0x000000cf }, + { 0x000850, 7, 0x40, 0x00000000 }, + { 0x000814, 8, 0x40, 0x00000040 }, + { 0x000818, 8, 0x40, 0x00000001 }, + { 0x00081c, 8, 0x40, 0x00000000 }, + { 0x000820, 8, 0x40, 0x00000000 }, + { 0x001c00, 16, 0x10, 0x00000000 }, + { 0x001c04, 16, 0x10, 0x00000000 }, + { 0x001c08, 16, 0x10, 0x00000000 }, + { 0x001c0c, 16, 0x10, 0x00000000 }, + { 0x001d00, 16, 0x10, 0x00000000 }, + { 0x001d04, 16, 0x10, 0x00000000 }, + { 0x001d08, 16, 0x10, 0x00000000 }, + { 0x001d0c, 16, 0x10, 0x00000000 }, + { 0x001f00, 16, 0x08, 0x00000000 }, + { 0x001f04, 16, 0x08, 0x00000000 }, + { 0x001f80, 16, 0x08, 0x00000000 }, + { 0x001f84, 16, 0x08, 0x00000000 }, + { 0x002000, 1, 0x04, 0x00000000 }, + { 0x002040, 1, 0x04, 0x00000011 }, + { 0x002080, 1, 0x04, 0x00000020 }, + { 0x0020c0, 1, 0x04, 0x00000030 }, + { 0x002100, 1, 0x04, 0x00000040 }, + { 0x002140, 1, 0x04, 0x00000051 }, + { 0x00200c, 6, 0x40, 0x00000001 }, + { 0x002010, 1, 0x04, 0x00000000 }, + { 0x002050, 1, 0x04, 0x00000000 }, + { 0x002090, 1, 0x04, 0x00000001 }, + { 0x0020d0, 1, 0x04, 0x00000002 }, + { 0x002110, 1, 0x04, 0x00000003 }, + { 0x002150, 1, 0x04, 0x00000004 }, + { 0x000380, 4, 0x20, 0x00000000 }, + { 0x000384, 4, 0x20, 0x00000000 }, + { 0x000388, 4, 0x20, 0x00000000 }, + { 0x00038c, 4, 0x20, 0x00000000 }, + { 0x000700, 4, 0x10, 0x00000000 }, + { 0x000704, 4, 0x10, 0x00000000 }, + { 0x000708, 4, 0x10, 0x00000000 }, + { 0x002800, 128, 0x04, 0x00000000 }, + { 0x000a00, 16, 0x20, 0x00000000 }, + { 0x000a04, 16, 0x20, 0x00000000 }, + { 0x000a08, 16, 0x20, 0x00000000 }, + { 0x000a0c, 16, 0x20, 0x00000000 }, + { 0x000a10, 16, 0x20, 0x00000000 }, + { 0x000a14, 16, 0x20, 0x00000000 }, + { 0x000c00, 16, 0x10, 0x00000000 }, + { 0x000c04, 16, 0x10, 0x00000000 }, + { 0x000c08, 16, 0x10, 0x00000000 }, + { 0x000c0c, 16, 0x10, 0x3f800000 }, + { 0x000d00, 8, 0x08, 0xffff0000 }, + { 0x000d04, 8, 0x08, 0xffff0000 }, + { 0x000e00, 16, 0x10, 0x00000000 }, + { 0x000e04, 16, 0x10, 0xffff0000 }, + { 0x000e08, 16, 0x10, 0xffff0000 }, + { 0x000d40, 4, 0x08, 0x00000000 }, + { 0x000d44, 4, 0x08, 0x00000000 }, + { 0x001e00, 8, 0x20, 0x00000001 }, + { 0x001e04, 8, 0x20, 0x00000001 }, + { 0x001e08, 8, 0x20, 0x00000002 }, + { 0x001e0c, 8, 0x20, 0x00000001 }, + { 0x001e10, 8, 0x20, 0x00000001 }, + { 0x001e14, 8, 0x20, 0x00000002 }, + { 0x001e18, 8, 0x20, 0x00000001 }, + { 0x003400, 128, 0x04, 0x00000000 }, + { 0x00030c, 1, 0x04, 0x00000001 }, + { 0x001944, 1, 0x04, 0x00000000 }, + { 0x001514, 1, 0x04, 0x00000000 }, + { 0x000d68, 1, 0x04, 0x0000ffff }, + { 0x00121c, 1, 0x04, 0x0fac6881 }, + { 0x000fac, 1, 0x04, 0x00000001 }, + { 0x001538, 1, 0x04, 0x00000001 }, + { 0x000fe0, 2, 0x04, 0x00000000 }, + { 0x000fe8, 1, 0x04, 0x00000014 }, + { 0x000fec, 1, 0x04, 0x00000040 }, + { 0x000ff0, 1, 0x04, 0x00000000 }, + { 0x00179c, 1, 0x04, 0x00000000 }, + { 0x001228, 1, 0x04, 0x00000400 }, + { 0x00122c, 1, 0x04, 0x00000300 }, + { 0x001230, 1, 0x04, 0x00010001 }, + { 0x0007f8, 1, 0x04, 0x00000000 }, + { 0x0015b4, 1, 0x04, 0x00000001 }, + { 0x0015cc, 1, 0x04, 0x00000000 }, + { 0x001534, 1, 0x04, 0x00000000 }, + { 0x000fb0, 1, 0x04, 0x00000000 }, + { 0x0015d0, 1, 0x04, 0x00000000 }, + { 0x00153c, 1, 0x04, 0x00000000 }, + { 0x0016b4, 1, 0x04, 0x00000003 }, + { 0x000fbc, 4, 0x04, 0x0000ffff }, + { 0x000df8, 2, 0x04, 0x00000000 }, + { 0x001948, 1, 0x04, 0x00000000 }, + { 0x001970, 1, 0x04, 0x00000001 }, + { 0x00161c, 1, 0x04, 0x000009f0 }, + { 0x000dcc, 1, 0x04, 0x00000010 }, + { 0x00163c, 1, 0x04, 0x00000000 }, + { 0x0015e4, 1, 0x04, 0x00000000 }, + { 0x001160, 32, 0x04, 0x25e00040 }, + { 0x001880, 32, 0x04, 0x00000000 }, + { 0x000f84, 2, 0x04, 0x00000000 }, + { 0x0017c8, 2, 0x04, 0x00000000 }, + { 0x0017d0, 1, 0x04, 0x000000ff }, + { 0x0017d4, 1, 0x04, 0xffffffff }, + { 0x0017d8, 1, 0x04, 0x00000002 }, + { 0x0017dc, 1, 0x04, 0x00000000 }, + { 0x0015f4, 2, 0x04, 0x00000000 }, + { 0x001434, 2, 0x04, 0x00000000 }, + { 0x000d74, 1, 0x04, 0x00000000 }, + { 0x000dec, 1, 0x04, 0x00000001 }, + { 0x0013a4, 1, 0x04, 0x00000000 }, + { 0x001318, 1, 0x04, 0x00000001 }, + { 0x001644, 1, 0x04, 0x00000000 }, + { 0x000748, 1, 0x04, 0x00000000 }, + { 0x000de8, 1, 0x04, 0x00000000 }, + { 0x001648, 1, 0x04, 0x00000000 }, + { 0x0012a4, 1, 0x04, 0x00000000 }, + { 0x001120, 4, 0x04, 0x00000000 }, + { 0x001118, 1, 0x04, 0x00000000 }, + { 0x00164c, 1, 0x04, 0x00000000 }, + { 0x001658, 1, 0x04, 0x00000000 }, + { 0x001910, 1, 0x04, 0x00000290 }, + { 0x001518, 1, 0x04, 0x00000000 }, + { 0x00165c, 1, 0x04, 0x00000001 }, + { 0x001520, 1, 0x04, 0x00000000 }, + { 0x001604, 1, 0x04, 0x00000000 }, + { 0x001570, 1, 0x04, 0x00000000 }, + { 0x0013b0, 2, 0x04, 0x3f800000 }, + { 0x00020c, 1, 0x04, 0x00000000 }, + { 0x001670, 1, 0x04, 0x30201000 }, + { 0x001674, 1, 0x04, 0x70605040 }, + { 0x001678, 1, 0x04, 0xb8a89888 }, + { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, + { 0x00166c, 1, 0x04, 0x00000000 }, + { 0x001680, 1, 0x04, 0x00ffff00 }, + { 0x0012d0, 1, 0x04, 0x00000003 }, + { 0x0012d4, 1, 0x04, 0x00000002 }, + { 0x001684, 2, 0x04, 0x00000000 }, + { 0x000dac, 2, 0x04, 0x00001b02 }, + { 0x000db4, 1, 0x04, 0x00000000 }, + { 0x00168c, 1, 0x04, 0x00000000 }, + { 0x0015bc, 1, 0x04, 0x00000000 }, + { 0x00156c, 1, 0x04, 0x00000000 }, + { 0x00187c, 1, 0x04, 0x00000000 }, + { 0x001110, 1, 0x04, 0x00000001 }, + { 0x000dc0, 3, 0x04, 0x00000000 }, + { 0x001234, 1, 0x04, 0x00000000 }, + { 0x001690, 1, 0x04, 0x00000000 }, + { 0x0012ac, 1, 0x04, 0x00000001 }, + { 0x000790, 5, 0x04, 0x00000000 }, + { 0x00077c, 1, 0x04, 0x00000000 }, + { 0x001000, 1, 0x04, 0x00000010 }, + { 0x0010fc, 1, 0x04, 0x00000000 }, + { 0x001290, 1, 0x04, 0x00000000 }, + { 0x000218, 1, 0x04, 0x00000010 }, + { 0x0012d8, 1, 0x04, 0x00000000 }, + { 0x0012dc, 1, 0x04, 0x00000010 }, + { 0x000d94, 1, 0x04, 0x00000001 }, + { 0x00155c, 2, 0x04, 0x00000000 }, + { 0x001564, 1, 0x04, 0x00000fff }, + { 0x001574, 2, 0x04, 0x00000000 }, + { 0x00157c, 1, 0x04, 0x000fffff }, + { 0x001354, 1, 0x04, 0x00000000 }, + { 0x001610, 1, 0x04, 0x00000012 }, + { 0x001608, 2, 0x04, 0x00000000 }, + { 0x00260c, 1, 0x04, 0x00000000 }, + { 0x0007ac, 1, 0x04, 0x00000000 }, + { 0x00162c, 1, 0x04, 0x00000003 }, + { 0x000210, 1, 0x04, 0x00000000 }, + { 0x000320, 1, 0x04, 0x00000000 }, + { 0x000324, 6, 0x04, 0x3f800000 }, + { 0x000750, 1, 0x04, 0x00000000 }, + { 0x000760, 1, 0x04, 0x39291909 }, + { 0x000764, 1, 0x04, 0x79695949 }, + { 0x000768, 1, 0x04, 0xb9a99989 }, + { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, + { 0x000770, 1, 0x04, 0x30201000 }, + { 0x000774, 1, 0x04, 0x70605040 }, + { 0x000778, 1, 0x04, 0x00009080 }, + { 0x000780, 1, 0x04, 0x39291909 }, + { 0x000784, 1, 0x04, 0x79695949 }, + { 0x000788, 1, 0x04, 0xb9a99989 }, + { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, + { 0x0007d0, 1, 0x04, 0x30201000 }, + { 0x0007d4, 1, 0x04, 0x70605040 }, + { 0x0007d8, 1, 0x04, 0x00009080 }, + { 0x00037c, 1, 0x04, 0x00000001 }, + { 0x000740, 2, 0x04, 0x00000000 }, + { 0x002600, 1, 0x04, 0x00000000 }, + { 0x001918, 1, 0x04, 0x00000000 }, + { 0x00191c, 1, 0x04, 0x00000900 }, + { 0x001920, 1, 0x04, 0x00000405 }, + { 0x001308, 1, 0x04, 0x00000001 }, + { 0x001924, 1, 0x04, 0x00000000 }, + { 0x0013ac, 1, 0x04, 0x00000000 }, + { 0x00192c, 1, 0x04, 0x00000001 }, + { 0x00193c, 1, 0x04, 0x00002c1c }, + { 0x000d7c, 1, 0x04, 0x00000000 }, + { 0x000f8c, 1, 0x04, 0x00000000 }, + { 0x0002c0, 1, 0x04, 0x00000001 }, + { 0x001510, 1, 0x04, 0x00000000 }, + { 0x001940, 1, 0x04, 0x00000000 }, + { 0x000ff4, 2, 0x04, 0x00000000 }, + { 0x00194c, 2, 0x04, 0x00000000 }, + { 0x001968, 1, 0x04, 0x00000000 }, + { 0x001590, 1, 0x04, 0x0000003f }, + { 0x0007e8, 4, 0x04, 0x00000000 }, + { 0x00196c, 1, 0x04, 0x00000011 }, + { 0x0002e4, 1, 0x04, 0x0000b001 }, + { 0x00036c, 2, 0x04, 0x00000000 }, + { 0x00197c, 1, 0x04, 0x00000000 }, + { 0x000fcc, 2, 0x04, 0x00000000 }, + { 0x0002d8, 1, 0x04, 0x00000040 }, + { 0x001980, 1, 0x04, 0x00000080 }, + { 0x001504, 1, 0x04, 0x00000080 }, + { 0x001984, 1, 0x04, 0x00000000 }, + { 0x000300, 1, 0x04, 0x00000001 }, + { 0x0013a8, 1, 0x04, 0x00000000 }, + { 0x0012ec, 1, 0x04, 0x00000000 }, + { 0x001310, 1, 0x04, 0x00000000 }, + { 0x001314, 1, 0x04, 0x00000001 }, + { 0x001380, 1, 0x04, 0x00000000 }, + { 0x001384, 4, 0x04, 0x00000001 }, + { 0x001394, 1, 0x04, 0x00000000 }, + { 0x00139c, 1, 0x04, 0x00000000 }, + { 0x001398, 1, 0x04, 0x00000000 }, + { 0x001594, 1, 0x04, 0x00000000 }, + { 0x001598, 4, 0x04, 0x00000001 }, + { 0x000f54, 3, 0x04, 0x00000000 }, + { 0x0019bc, 1, 0x04, 0x00000000 }, + { 0x000f9c, 2, 0x04, 0x00000000 }, + { 0x0012cc, 1, 0x04, 0x00000000 }, + { 0x0012e8, 1, 0x04, 0x00000000 }, + { 0x00130c, 1, 0x04, 0x00000001 }, + { 0x001360, 8, 0x04, 0x00000000 }, + { 0x00133c, 2, 0x04, 0x00000001 }, + { 0x001344, 1, 0x04, 0x00000002 }, + { 0x001348, 2, 0x04, 0x00000001 }, + { 0x001350, 1, 0x04, 0x00000002 }, + { 0x001358, 1, 0x04, 0x00000001 }, + { 0x0012e4, 1, 0x04, 0x00000000 }, + { 0x00131c, 1, 0x04, 0x00000000 }, + { 0x001320, 3, 0x04, 0x00000000 }, + { 0x0019c0, 1, 0x04, 0x00000000 }, + { 0x001140, 1, 0x04, 0x00000000 }, + { 0x0019c4, 1, 0x04, 0x00000000 }, + { 0x0019c8, 1, 0x04, 0x00001500 }, + { 0x00135c, 1, 0x04, 0x00000000 }, + { 0x000f90, 1, 0x04, 0x00000000 }, + { 0x0019e0, 8, 0x04, 0x00000001 }, + { 0x0019cc, 1, 0x04, 0x00000001 }, + { 0x0015b8, 1, 0x04, 0x00000000 }, + { 0x001a00, 1, 0x04, 0x00001111 }, + { 0x001a04, 7, 0x04, 0x00000000 }, + { 0x000d6c, 2, 0x04, 0xffff0000 }, + { 0x0010f8, 1, 0x04, 0x00001010 }, + { 0x000d80, 5, 0x04, 0x00000000 }, + { 0x000da0, 1, 0x04, 0x00000000 }, + { 0x0007a4, 2, 0x04, 0x00000000 }, + { 0x001508, 1, 0x04, 0x80000000 }, + { 0x00150c, 1, 0x04, 0x40000000 }, + { 0x001668, 1, 0x04, 0x00000000 }, + { 0x000318, 2, 0x04, 0x00000008 }, + { 0x000d9c, 1, 0x04, 0x00000001 }, + { 0x000374, 1, 0x04, 0x00000000 }, + { 0x000378, 1, 0x04, 0x00000020 }, + { 0x0007dc, 1, 0x04, 0x00000000 }, + { 0x00074c, 1, 0x04, 0x00000055 }, + { 0x001420, 1, 0x04, 0x00000003 }, + { 0x0017bc, 2, 0x04, 0x00000000 }, + { 0x0017c4, 1, 0x04, 0x00000001 }, + { 0x001008, 1, 0x04, 0x00000008 }, + { 0x00100c, 1, 0x04, 0x00000040 }, + { 0x001010, 1, 0x04, 0x0000012c }, + { 0x000d60, 1, 0x04, 0x00000040 }, + { 0x00075c, 1, 0x04, 0x00000003 }, + { 0x001018, 1, 0x04, 0x00000020 }, + { 0x00101c, 1, 0x04, 0x00000001 }, + { 0x001020, 1, 0x04, 0x00000020 }, + { 0x001024, 1, 0x04, 0x00000001 }, + { 0x001444, 3, 0x04, 0x00000000 }, + { 0x000360, 1, 0x04, 0x20164010 }, + { 0x000364, 1, 0x04, 0x00000020 }, + { 0x000368, 1, 0x04, 0x00000000 }, + { 0x000de4, 1, 0x04, 0x00000000 }, + { 0x000204, 1, 0x04, 0x00000006 }, + { 0x000208, 1, 0x04, 0x00000000 }, + { 0x0002cc, 2, 0x04, 0x003fffff }, + { 0x001220, 1, 0x04, 0x00000005 }, + { 0x000fdc, 1, 0x04, 0x00000000 }, + { 0x000f98, 1, 0x04, 0x00400008 }, + { 0x001284, 1, 0x04, 0x08000080 }, + { 0x001450, 1, 0x04, 0x00400008 }, + { 0x001454, 1, 0x04, 0x08000080 }, + { 0x000214, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk40xx[] = { + { 0x404010, 5, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 1, 0x04, 0x00000000 }, + { 0x4040a8, 1, 0x04, 0x00000000 }, + { 0x4040ac, 7, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404130, 1, 0x04, 0x00000000 }, + { 0x404134, 1, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 4, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_grctx_init_unk46xx[] = { + { 0x404604, 1, 0x04, 0x00000014 }, + { 0x404608, 1, 0x04, 0x00000000 }, + { 0x40460c, 1, 0x04, 0x00003fff }, + { 0x404610, 1, 0x04, 0x00000100 }, + { 0x404618, 4, 0x04, 0x00000000 }, + { 0x40462c, 2, 0x04, 0x00000000 }, + { 0x404640, 1, 0x04, 0x00000000 }, + { 0x404654, 1, 0x04, 0x00000000 }, + { 0x404660, 1, 0x04, 0x00000000 }, + { 0x404678, 1, 0x04, 0x00000000 }, + { 0x40467c, 1, 0x04, 0x00000002 }, + { 0x404680, 8, 0x04, 0x00000000 }, + { 0x4046a0, 1, 0x04, 0x007f0080 }, + { 0x4046a4, 8, 0x04, 0x00000000 }, + { 0x4046c8, 3, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_grctx_init_unk47xx[] = { + { 0x404700, 3, 0x04, 0x00000000 }, + { 0x404718, 7, 0x04, 0x00000000 }, + { 0x404734, 1, 0x04, 0x00000100 }, + { 0x404738, 2, 0x04, 0x00000000 }, + { 0x404744, 2, 0x04, 0x00000000 }, + { 0x404754, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_grctx_init_unk58xx[] = { + { 0x405800, 1, 0x04, 0x0f8000bf }, + { 0x405830, 1, 0x04, 0x02180648 }, + { 0x405834, 1, 0x04, 0x08000000 }, + { 0x405838, 1, 0x04, 0x00000000 }, + { 0x405854, 1, 0x04, 0x00000000 }, + { 0x405870, 4, 0x04, 0x00000001 }, + { 0x405a00, 2, 0x04, 0x00000000 }, + { 0x405a18, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk5bxx[] = { + { 0x405b00, 1, 0x04, 0x00000000 }, + { 0x405b10, 1, 0x04, 0x00001000 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk60xx[] = { + { 0x406020, 1, 0x04, 0x004103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk64xx[] = { + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b4, 2, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x801a00f0 }, + { 0x4064c4, 1, 0x04, 0x0192ffff }, + { 0x4064c8, 1, 0x04, 0x01800600 }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk70xx[] = { + { 0x407040, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_grctx_init_unk80xx[] = { + { 0x408000, 2, 0x04, 0x00000000 }, + { 0x408008, 1, 0x04, 0x00000030 }, + { 0x40800c, 2, 0x04, 0x00000000 }, + { 0x408014, 1, 0x04, 0x00000069 }, + { 0x408018, 1, 0x04, 0xe100e100 }, + { 0x408064, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_rop[] = { + { 0x408800, 1, 0x04, 0x02802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1043e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 3, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 3, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000006 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c40, 1, 0x04, 0xffffffff }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_tpc[] = { + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000000f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000021 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x00000800 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419ac4, 1, 0x04, 0x0037f440 }, + { 0x419c00, 1, 0x04, 0x0000000a }, + { 0x419c04, 1, 0x04, 0x80000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00003203 }, + { 0x419e04, 3, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00000402 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 19, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001f8f }, + { 0x419eb0, 1, 0x04, 0x00000d3f }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 8, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00000000 }, + { 0x419f78, 1, 0x04, 0x0000000b }, + { 0x419f7c, 1, 0x04, 0x0000027a }, + {} +}; + +static struct nvc0_graph_init +nve4_grctx_init_unk[] = { + { 0x41be24, 1, 0x04, 0x00000006 }, + { 0x41bec0, 1, 0x04, 0x12180000 }, + { 0x41bec4, 1, 0x04, 0x00037f7f }, + { 0x41bee4, 1, 0x04, 0x06480430 }, + { 0x41bf00, 1, 0x04, 0x0a418820 }, + { 0x41bf04, 1, 0x04, 0x062080e6 }, + { 0x41bf08, 1, 0x04, 0x020398a4 }, + { 0x41bf0c, 1, 0x04, 0x0e629062 }, + { 0x41bf10, 1, 0x04, 0x0a418820 }, + { 0x41bf14, 1, 0x04, 0x000000e6 }, + { 0x41bfd0, 1, 0x04, 0x00900103 }, + { 0x41bfe0, 1, 0x04, 0x00400001 }, + { 0x41bfe4, 1, 0x04, 0x00000000 }, + {} +}; + +static void +nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + u32 magic[GPC_MAX][2]; + u32 offset; + int gpc; + + mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_list(0x40800c, 0x00000000, 8, 1); + mmio_list(0x408010, 0x80000000, 0, 0); + mmio_list(0x419004, 0x00000000, 8, 1); + mmio_list(0x419008, 0x00000000, 0, 0); + mmio_list(0x4064cc, 0x80000000, 0, 0); + mmio_list(0x408004, 0x00000000, 8, 0); + mmio_list(0x408008, 0x80000030, 0, 0); + mmio_list(0x418808, 0x00000000, 8, 0); + mmio_list(0x41880c, 0x80000030, 0, 0); + mmio_list(0x4064c8, 0x01800600, 0, 0); + mmio_list(0x418810, 0x80000000, 12, 2); + mmio_list(0x419848, 0x10000000, 12, 2); + + mmio_list(0x405830, 0x02180648, 0, 0); + mmio_list(0x4064c4, 0x0192ffff, 0, 0); + + for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { + u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; + u16 magic1 = 0x0648 * priv->tpc_nr[gpc]; + magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; + magic[gpc][1] = 0x00000000 | (magic1 << 16); + offset += 0x0324 * priv->tpc_nr[gpc]; + } + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); + mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); + offset += 0x07ff * priv->tpc_nr[gpc]; + } + + mmio_list(0x17e91c, 0x06060609, 0, 0); + mmio_list(0x17e920, 0x00090a05, 0, 0); +} + +void +nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) +{ + nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); + nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); + nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(priv, 0x405800, 0x08000000, 0x08000000); + nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +} + +void +nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) +{ + u32 data[6] = {}, data2[2] = {}; + u8 tpcnr[GPC_MAX]; + u8 shift, ntpcv; + int gpc, tpc, i; + + /* calculate first set of magics */ + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + + gpc = -1; + for (tpc = 0; tpc < priv->tpc_total; tpc++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpcnr[gpc]--; + + data[tpc / 6] |= gpc << ((tpc % 6) * 5); + } + + for (; tpc < 32; tpc++) + data[tpc / 6] |= 7 << ((tpc % 6) * 5); + + /* and the second... */ + shift = 0; + ntpcv = priv->tpc_total; + while (!(ntpcv & (1 << 4))) { + ntpcv <<= 1; + shift++; + } + + data2[0] = (ntpcv << 16); + data2[0] |= (shift << 21); + data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); + for (i = 1; i < 7; i++) + data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); + + /* GPC_BROADCAST */ + nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x418b08 + (i * 4), data[i]); + + /* GPC_BROADCAST.TP_BROADCAST */ + nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | + priv->magic_not_rop_nr | data2[0]); + nv_wr32(priv, 0x41bfe4, data2[1]); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); + + /* UNK78xx */ + nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | + priv->magic_not_rop_nr); + for (i = 0; i < 6; i++) + nv_wr32(priv, 0x40780c + (i * 4), data[i]); +} + +void +nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int i; + + nv_mask(priv, 0x000260, 0x00000001, 0x00000000); + + for (i = 0; oclass->hub[i]; i++) + nvc0_graph_mmio(priv, oclass->hub[i]); + for (i = 0; oclass->gpc[i]; i++) + nvc0_graph_mmio(priv, oclass->gpc[i]); + + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->mods(priv, info); + oclass->unkn(priv); + + nvc0_grctx_generate_tpcid(priv); + nvc0_grctx_generate_r406028(priv); + nve4_grctx_generate_r418bb8(priv); + nvc0_grctx_generate_r406800(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + if (priv->gpc_nr == 1) { + nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); + nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); + } else { + nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); + nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); + } + nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); + + nvc0_graph_icmd(priv, oclass->icmd); + nv_wr32(priv, 0x404154, 0x00000400); + nvc0_graph_mthd(priv, oclass->mthd); + nv_mask(priv, 0x000260, 0x00000001, 0x00000001); + + nv_mask(priv, 0x418800, 0x00200000, 0x00200000); + nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); +} + +static struct nvc0_graph_init * +nve4_grctx_init_hub[] = { + nvc0_grctx_init_base, + nve4_grctx_init_unk40xx, + nvc0_grctx_init_unk44xx, + nve4_grctx_init_unk46xx, + nve4_grctx_init_unk47xx, + nve4_grctx_init_unk58xx, + nve4_grctx_init_unk5bxx, + nve4_grctx_init_unk60xx, + nve4_grctx_init_unk64xx, + nve4_grctx_init_unk70xx, + nvc0_grctx_init_unk78xx, + nve4_grctx_init_unk80xx, + nve4_grctx_init_rop, + NULL +}; + +struct nvc0_graph_init * +nve4_grctx_init_gpc[] = { + nve4_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nve4_grctx_init_tpc, + nve4_grctx_init_unk, + NULL +}; + +static struct nvc0_graph_mthd +nve4_grctx_init_mthd[] = { + { 0xa097, nve4_grctx_init_a097, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x902d, nvc0_grctx_init_mthd_magic, }, + {} +}; + +struct nouveau_oclass * +nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nve4_grctx_generate_main, + .mods = nve4_grctx_generate_mods, + .unkn = nve4_grctx_generate_unkn, + .hub = nve4_grctx_init_hub, + .gpc = nve4_grctx_init_gpc, + .icmd = nve4_grctx_init_icmd, + .mthd = nve4_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c new file mode 100644 index 000000000000..dcb2ebb8c29d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c @@ -0,0 +1,328 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +static struct nvc0_graph_init +nvf0_grctx_init_unk40xx[] = { + { 0x404004, 8, 0x04, 0x00000000 }, + { 0x404024, 1, 0x04, 0x0000e000 }, + { 0x404028, 8, 0x04, 0x00000000 }, + { 0x4040a8, 8, 0x04, 0x00000000 }, + { 0x4040c8, 1, 0x04, 0xf800008f }, + { 0x4040d0, 6, 0x04, 0x00000000 }, + { 0x4040e8, 1, 0x04, 0x00001000 }, + { 0x4040f8, 1, 0x04, 0x00000000 }, + { 0x404100, 10, 0x04, 0x00000000 }, + { 0x404130, 2, 0x04, 0x00000000 }, + { 0x404138, 1, 0x04, 0x20000040 }, + { 0x404150, 1, 0x04, 0x0000002e }, + { 0x404154, 1, 0x04, 0x00000400 }, + { 0x404158, 1, 0x04, 0x00000200 }, + { 0x404164, 1, 0x04, 0x00000055 }, + { 0x40417c, 2, 0x04, 0x00000000 }, + { 0x4041a0, 4, 0x04, 0x00000000 }, + { 0x404200, 1, 0x04, 0x0000a197 }, + { 0x404204, 1, 0x04, 0x0000a1c0 }, + { 0x404208, 1, 0x04, 0x0000a140 }, + { 0x40420c, 1, 0x04, 0x0000902d }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk44xx[] = { + { 0x404404, 12, 0x04, 0x00000000 }, + { 0x404438, 1, 0x04, 0x00000000 }, + { 0x404460, 2, 0x04, 0x00000000 }, + { 0x404468, 1, 0x04, 0x00ffffff }, + { 0x40446c, 1, 0x04, 0x00000000 }, + { 0x404480, 1, 0x04, 0x00000001 }, + { 0x404498, 1, 0x04, 0x00000001 }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk5bxx[] = { + { 0x405b00, 1, 0x04, 0x00000000 }, + { 0x405b10, 1, 0x04, 0x00001000 }, + { 0x405b20, 1, 0x04, 0x04000000 }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk60xx[] = { + { 0x406020, 1, 0x04, 0x034103c1 }, + { 0x406028, 4, 0x04, 0x00000001 }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk64xx[] = { + { 0x4064a8, 1, 0x04, 0x00000000 }, + { 0x4064ac, 1, 0x04, 0x00003fff }, + { 0x4064b0, 3, 0x04, 0x00000000 }, + { 0x4064c0, 1, 0x04, 0x802000f0 }, + { 0x4064c4, 1, 0x04, 0x0192ffff }, + { 0x4064c8, 1, 0x04, 0x018007c0 }, + { 0x4064cc, 9, 0x04, 0x00000000 }, + { 0x4064fc, 1, 0x04, 0x0000022a }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk88xx[] = { + { 0x408800, 1, 0x04, 0x12802a3c }, + { 0x408804, 1, 0x04, 0x00000040 }, + { 0x408808, 1, 0x04, 0x1003e005 }, + { 0x408840, 1, 0x04, 0x0000000b }, + { 0x408900, 1, 0x04, 0x3080b801 }, + { 0x408904, 1, 0x04, 0x62000001 }, + { 0x408908, 1, 0x04, 0x00c8102f }, + { 0x408980, 1, 0x04, 0x0000011d }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_gpc_0[] = { + { 0x418380, 1, 0x04, 0x00000016 }, + { 0x418400, 1, 0x04, 0x38004e00 }, + { 0x418404, 1, 0x04, 0x71e0ffff }, + { 0x41840c, 1, 0x04, 0x00001008 }, + { 0x418410, 1, 0x04, 0x0fff0fff }, + { 0x418414, 1, 0x04, 0x02200fff }, + { 0x418450, 6, 0x04, 0x00000000 }, + { 0x418468, 1, 0x04, 0x00000001 }, + { 0x41846c, 2, 0x04, 0x00000000 }, + { 0x418600, 1, 0x04, 0x0000001f }, + { 0x418684, 1, 0x04, 0x0000000f }, + { 0x418700, 1, 0x04, 0x00000002 }, + { 0x418704, 1, 0x04, 0x00000080 }, + { 0x418708, 3, 0x04, 0x00000000 }, + { 0x418800, 1, 0x04, 0x7006860a }, + { 0x418808, 1, 0x04, 0x00000000 }, + { 0x41880c, 1, 0x04, 0x00000030 }, + { 0x418810, 1, 0x04, 0x00000000 }, + { 0x418828, 1, 0x04, 0x00000044 }, + { 0x418830, 1, 0x04, 0x10000001 }, + { 0x4188d8, 1, 0x04, 0x00000008 }, + { 0x4188e0, 1, 0x04, 0x01000000 }, + { 0x4188e8, 5, 0x04, 0x00000000 }, + { 0x4188fc, 1, 0x04, 0x20100018 }, + { 0x41891c, 1, 0x04, 0x00ff00ff }, + { 0x418924, 1, 0x04, 0x00000000 }, + { 0x418928, 1, 0x04, 0x00ffff00 }, + { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000006 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c40, 1, 0x04, 0xffffffff }, + { 0x418c6c, 1, 0x04, 0x00000001 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x418d24, 1, 0x04, 0x00000000 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_tpc[] = { + { 0x419848, 1, 0x04, 0x00000000 }, + { 0x419864, 1, 0x04, 0x00000129 }, + { 0x419888, 1, 0x04, 0x00000000 }, + { 0x419a00, 1, 0x04, 0x000000f0 }, + { 0x419a04, 1, 0x04, 0x00000001 }, + { 0x419a08, 1, 0x04, 0x00000021 }, + { 0x419a0c, 1, 0x04, 0x00020000 }, + { 0x419a10, 1, 0x04, 0x00000000 }, + { 0x419a14, 1, 0x04, 0x00000200 }, + { 0x419a1c, 1, 0x04, 0x0000c000 }, + { 0x419a20, 1, 0x04, 0x00020800 }, + { 0x419a30, 1, 0x04, 0x00000001 }, + { 0x419ac4, 1, 0x04, 0x0037f440 }, + { 0x419c00, 1, 0x04, 0x0000001a }, + { 0x419c04, 1, 0x04, 0x80000006 }, + { 0x419c08, 1, 0x04, 0x00000002 }, + { 0x419c20, 1, 0x04, 0x00000000 }, + { 0x419c24, 1, 0x04, 0x00084210 }, + { 0x419c28, 1, 0x04, 0x3efbefbe }, + { 0x419ce8, 1, 0x04, 0x00000000 }, + { 0x419cf4, 1, 0x04, 0x00000203 }, + { 0x419e04, 1, 0x04, 0x00000000 }, + { 0x419e08, 1, 0x04, 0x0000001d }, + { 0x419e0c, 1, 0x04, 0x00000000 }, + { 0x419e10, 1, 0x04, 0x00001c02 }, + { 0x419e44, 1, 0x04, 0x0013eff2 }, + { 0x419e48, 1, 0x04, 0x00000000 }, + { 0x419e4c, 1, 0x04, 0x0000007f }, + { 0x419e50, 2, 0x04, 0x00000000 }, + { 0x419e58, 1, 0x04, 0x00000001 }, + { 0x419e5c, 3, 0x04, 0x00000000 }, + { 0x419e68, 1, 0x04, 0x00000002 }, + { 0x419e6c, 12, 0x04, 0x00000000 }, + { 0x419eac, 1, 0x04, 0x00001fcf }, + { 0x419eb0, 1, 0x04, 0x0db00da0 }, + { 0x419eb8, 1, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0001304f }, + { 0x419f30, 4, 0x04, 0x00000000 }, + { 0x419f40, 1, 0x04, 0x00000018 }, + { 0x419f44, 3, 0x04, 0x00000000 }, + { 0x419f58, 1, 0x04, 0x00000000 }, + { 0x419f70, 1, 0x04, 0x00007300 }, + { 0x419f78, 1, 0x04, 0x000000eb }, + { 0x419f7c, 1, 0x04, 0x00000404 }, + {} +}; + +static struct nvc0_graph_init +nvf0_grctx_init_unk[] = { + { 0x41be24, 1, 0x04, 0x00000006 }, + { 0x41bec0, 1, 0x04, 0x10000000 }, + { 0x41bec4, 1, 0x04, 0x00037f7f }, + { 0x41bee4, 1, 0x04, 0x00000000 }, + { 0x41bf00, 1, 0x04, 0x0a418820 }, + { 0x41bf04, 1, 0x04, 0x062080e6 }, + { 0x41bf08, 1, 0x04, 0x020398a4 }, + { 0x41bf0c, 1, 0x04, 0x0e629062 }, + { 0x41bf10, 1, 0x04, 0x0a418820 }, + { 0x41bf14, 1, 0x04, 0x000000e6 }, + { 0x41bfd0, 1, 0x04, 0x00900103 }, + { 0x41bfe0, 1, 0x04, 0x00400001 }, + { 0x41bfe4, 1, 0x04, 0x00000000 }, + {} +}; + +static void +nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +{ + u32 magic[GPC_MAX][4]; + u32 offset; + int gpc; + + mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); + mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); + mmio_list(0x40800c, 0x00000000, 8, 1); + mmio_list(0x408010, 0x80000000, 0, 0); + mmio_list(0x419004, 0x00000000, 8, 1); + mmio_list(0x419008, 0x00000000, 0, 0); + mmio_list(0x4064cc, 0x80000000, 0, 0); + mmio_list(0x408004, 0x00000000, 8, 0); + mmio_list(0x408008, 0x80000030, 0, 0); + mmio_list(0x418808, 0x00000000, 8, 0); + mmio_list(0x41880c, 0x80000030, 0, 0); + mmio_list(0x4064c8, 0x01800600, 0, 0); + mmio_list(0x418810, 0x80000000, 12, 2); + mmio_list(0x419848, 0x10000000, 12, 2); + + mmio_list(0x405830, 0x02180648, 0, 0); + mmio_list(0x4064c4, 0x0192ffff, 0, 0); + + for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { + u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1); + u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1); + u16 magic2 = 0x0218; + u16 magic3 = 0x0648; + magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; + magic[gpc][1] = 0x00000000 | (magic1 << 16); + offset += 0x0324 * (priv->tpc_nr[gpc] - 1);; + magic[gpc][2] = 0x10000000 | (magic2 << 16) | offset; + magic[gpc][3] = 0x00000000 | (magic3 << 16); + offset += 0x0324; + } + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); + mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); + offset += 0x07ff * (priv->tpc_nr[gpc] - 1); + mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0); + mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0); + offset += 0x07ff; + } + + mmio_list(0x17e91c, 0x06060609, 0, 0); + mmio_list(0x17e920, 0x00090a05, 0, 0); +} + +static struct nvc0_graph_init * +nvf0_grctx_init_hub[] = { + nvc0_grctx_init_base, + nvf0_grctx_init_unk40xx, + nvf0_grctx_init_unk44xx, + nve4_grctx_init_unk46xx, + nve4_grctx_init_unk47xx, + nve4_grctx_init_unk58xx, + nvf0_grctx_init_unk5bxx, + nvf0_grctx_init_unk60xx, + nvf0_grctx_init_unk64xx, + nve4_grctx_init_unk80xx, + nvf0_grctx_init_unk88xx, + nvd9_grctx_init_rop, + NULL +}; + +struct nvc0_graph_init * +nvf0_grctx_init_gpc[] = { + nvf0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + nvf0_grctx_init_tpc, + nvf0_grctx_init_unk, + NULL +}; + +static struct nvc0_graph_mthd +nvf0_grctx_init_mthd[] = { + { 0xa197, nvc1_grctx_init_9097, }, + { 0x902d, nvc0_grctx_init_902d, }, + { 0x902d, nvc0_grctx_init_mthd_magic, }, + {} +}; + +struct nouveau_oclass * +nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0xf0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_context_ctor, + .dtor = nvc0_graph_context_dtor, + .init = _nouveau_graph_context_init, + .fini = _nouveau_graph_context_fini, + .rd32 = _nouveau_graph_context_rd32, + .wr32 = _nouveau_graph_context_wr32, + }, + .main = nve4_grctx_generate_main, + .mods = nvf0_grctx_generate_mods, + .unkn = nve4_grctx_generate_unkn, + .hub = nvf0_grctx_init_hub, + .gpc = nvf0_grctx_init_gpc, + .icmd = nvc0_grctx_init_icmd, + .mthd = nvf0_grctx_init_mthd, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc index da18885c559c..5d24b6de16cc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc @@ -149,13 +149,9 @@ watchdog_clear: // wait_donez: trace_set(T_WAIT); - mov $r8 0x818 - shl b32 $r8 6 - iowr I[$r8 + 0x000] $r10 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) wait_donez_ne: - mov $r8 0x400 - shl b32 $r8 6 - iord $r8 I[$r8 + 0x000] + nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) xbit $r8 $r8 $r10 bra ne #wait_donez_ne trace_clr(T_WAIT) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index 4770e8c99432..5547c1b3f4f2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc @@ -29,16 +29,26 @@ */ #ifdef INCLUDE_DATA +gpc_mmio_list_head: .b32 #mmio_list_base +gpc_mmio_list_tail: +tpc_mmio_list_head: .b32 #mmio_list_base +tpc_mmio_list_tail: +unk_mmio_list_head: .b32 #mmio_list_base +unk_mmio_list_tail: .b32 #mmio_list_base + gpc_id: .b32 0 -gpc_mmio_list_head: .b32 0 -gpc_mmio_list_tail: .b32 0 tpc_count: .b32 0 tpc_mask: .b32 0 -tpc_mmio_list_head: .b32 0 -tpc_mmio_list_tail: .b32 0 + +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +unk_count: .b32 0 +unk_mask: .b32 0 +#endif cmd_queue: queue_init + +mmio_list_base: #endif #ifdef INCLUDE_CODE @@ -61,7 +71,6 @@ error: // fall through to main loop after completion. // // Input: -// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh) // CC_SCRATCH[1]: context base // // Output: @@ -106,26 +115,33 @@ init: iord $r2 I[$r1 + 0x000] // MYINDEX st b32 D[$r0 + #gpc_id] $r2 - // find context data for this chipset - mov $r2 0x800 - shl b32 $r2 6 - iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0] - mov $r1 #chipsets - 12 - init_find_chipset: - add b32 $r1 12 - ld b32 $r3 D[$r1 + 0x00] - cmpu b32 $r3 $r2 - bra e #init_context - cmpu b32 $r3 0 - bra ne #init_find_chipset - // unknown chipset - ret +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // figure out which, and how many, UNKs are actually present + mov $r14 0x0c30 + sethi $r14 0x500000 + clear b32 $r2 + clear b32 $r3 + clear b32 $r4 + init_unk_loop: + call #nv_rd32 + cmp b32 $r15 0 + bra z #init_unk_next + mov $r15 1 + shl b32 $r15 $r2 + or $r4 $r15 + add b32 $r3 1 + init_unk_next: + add b32 $r2 1 + add b32 $r14 4 + cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE + bra ne #init_unk_loop + init_unk_done: + st b32 D[$r0 + #unk_count] $r3 + st b32 D[$r0 + #unk_mask] $r4 +#endif // initialise context base, and size tracking - init_context: - mov $r2 0x800 - shl b32 $r2 6 - iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base + nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0) clear b32 $r3 // track GPC context size here // set mmctx base addresses now so we don't have to do it later, @@ -136,30 +152,33 @@ init: iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE - // calculate GPC mmio context size, store the chipset-specific - // mmio list pointers somewhere we can get at them later without - // re-parsing the chipset list - clear b32 $r14 - clear b32 $r15 - ld b16 $r14 D[$r1 + 4] - ld b16 $r15 D[$r1 + 6] - st b16 D[$r0 + #gpc_mmio_list_head] $r14 - st b16 D[$r0 + #gpc_mmio_list_tail] $r15 + // calculate GPC mmio context size + ld b32 $r14 D[$r0 + #gpc_mmio_list_head] + ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] call #mmctx_size add b32 $r2 $r15 add b32 $r3 $r15 - // calculate per-TPC mmio context size, store the list pointers - ld b16 $r14 D[$r1 + 8] - ld b16 $r15 D[$r1 + 10] - st b16 D[$r0 + #tpc_mmio_list_head] $r14 - st b16 D[$r0 + #tpc_mmio_list_tail] $r15 + // calculate per-TPC mmio context size + ld b32 $r14 D[$r0 + #tpc_mmio_list_head] + ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] call #mmctx_size ld b32 $r14 D[$r0 + #tpc_count] mulu $r14 $r15 add b32 $r2 $r14 add b32 $r3 $r14 +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // calculate per-UNK mmio context size + ld b32 $r14 D[$r0 + #unk_mmio_list_head] + ld b32 $r15 D[$r0 + #unk_mmio_list_tail] + call #mmctx_size + ld b32 $r14 D[$r0 + #unk_count] + mulu $r14 $r15 + add b32 $r2 $r14 + add b32 $r3 $r14 +#endif + // round up base/size to 256 byte boundary (for strand SWBASE) add b32 $r4 0x1300 shr b32 $r3 2 @@ -177,13 +196,10 @@ init: add b32 $r3 $r15 // save context size, and tell HUB we're done - mov $r1 0x800 - shl b32 $r1 6 - iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size - add b32 $r1 0x800 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3) clear b32 $r2 bset $r2 31 - iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 + nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2) // Main program loop, very simple, sleeps until woken up by the interrupt // handler, pulls a command from the queue and executes its handler @@ -228,6 +244,7 @@ ih: push $r13 push $r14 push $r15 + clear b32 $r0 // incoming fifo command? iord $r10 I[$r0 + 0x200] // INTR @@ -335,7 +352,9 @@ ctx_xfer: // per-TPC mmio context xbit $r10 $flags $p1 // direction +#if !NV_PGRAPH_GPCX_UNK__SIZE or $r10 4 // last +#endif mov $r11 0x4000 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 ld b32 $r12 D[$r0 + #gpc_id] @@ -347,6 +366,22 @@ ctx_xfer: mov $r14 0x800 // stride = 0x800 call #mmctx_xfer +#if NV_PGRAPH_GPCX_UNK__SIZE > 0 + // per-UNK mmio context + xbit $r10 $flags $p1 // direction + or $r10 4 // last + mov $r11 0x3000 + sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0 + ld b32 $r12 D[$r0 + #gpc_id] + shl b32 $r12 15 + add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 + ld b32 $r12 D[$r0 + #unk_mmio_list_head] + ld b32 $r13 D[$r0 + #unk_mmio_list_tail] + ld b32 $r15 D[$r0 + #unk_mask] + mov $r14 0x200 // stride = 0x200 + call #mmctx_xfer +#endif + // wait for strands to finish call #strand_wait diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc index c2d9e59bb58f..5ae06a2d64c9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc @@ -22,127 +22,15 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#define NVGF +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000 + +#define CHIPSET GF100 #include "macros.fuc" .section #nvc0_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" - -chipsets: -.b8 0xc0 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc0_tpc_mmio_tail -.b8 0xc1 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc1_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc1_tpc_mmio_tail -.b8 0xc3 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc3_tpc_mmio_tail -.b8 0xc4 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc3_tpc_mmio_tail -.b8 0xc8 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc0_tpc_mmio_tail -.b8 0xce 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc3_tpc_mmio_tail -.b8 0xcf 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc3_tpc_mmio_tail -.b8 0xd9 0 0 0 -.b16 #nvd9_gpc_mmio_head -.b16 #nvc1_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvd9_tpc_mmio_tail -.b8 0xd7 0 0 0 -.b16 #nvd9_gpc_mmio_head -.b16 #nvc1_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvd9_tpc_mmio_tail -.b8 0 0 0 0 - -// GPC mmio lists -nvc0_gpc_mmio_head: -mmctx_data(0x000408, 1) -nvd9_gpc_mmio_head: -mmctx_data(0x000380, 1) -mmctx_data(0x000400, 2); -mmctx_data(0x00040c, 3); -mmctx_data(0x000450, 9) -mmctx_data(0x000600, 1) -mmctx_data(0x000684, 1) -mmctx_data(0x000700, 5) -mmctx_data(0x000800, 1) -mmctx_data(0x000808, 3) -mmctx_data(0x000828, 1) -mmctx_data(0x000830, 1) -mmctx_data(0x0008d8, 1) -mmctx_data(0x0008e0, 1) -mmctx_data(0x0008e8, 6) -mmctx_data(0x00091c, 1) -mmctx_data(0x000924, 3) -mmctx_data(0x000b00, 1) -mmctx_data(0x000b08, 6) -mmctx_data(0x000bb8, 1) -mmctx_data(0x000c08, 1) -mmctx_data(0x000c10, 8) -mmctx_data(0x000c80, 1) -mmctx_data(0x000c8c, 1) -mmctx_data(0x001000, 3) -mmctx_data(0x001014, 1) -nvc0_gpc_mmio_tail: -mmctx_data(0x000c6c, 1); -nvc1_gpc_mmio_tail: - -// TPC mmio lists -nvc0_tpc_mmio_head: -mmctx_data(0x000018, 1) -mmctx_data(0x00003c, 1) -mmctx_data(0x000048, 1) -mmctx_data(0x000064, 1) -mmctx_data(0x000088, 1) -mmctx_data(0x000200, 6) -mmctx_data(0x000300, 6) -mmctx_data(0x0003d0, 1) -mmctx_data(0x0003e0, 2) -mmctx_data(0x000400, 3) -mmctx_data(0x000420, 1) -mmctx_data(0x0004b0, 1) -mmctx_data(0x0004e8, 1) -mmctx_data(0x0004f4, 1) -mmctx_data(0x000520, 2) -mmctx_data(0x000604, 4) -mmctx_data(0x000644, 20) -mmctx_data(0x000698, 1) -mmctx_data(0x000750, 2) -nvc0_tpc_mmio_tail: -mmctx_data(0x00021c, 2) -mmctx_data(0x0002c4, 1) -mmctx_data(0x000730, 8) -mmctx_data(0x000758, 1) -nvc3_tpc_mmio_tail: -mmctx_data(0x000544, 1) -nvc1_tpc_mmio_tail: -mmctx_data(0x000424, 2); -mmctx_data(0x0006e0, 1); -nvd9_tpc_mmio_tail: #undef INCLUDE_DATA .section #nvc0_grgpc_code diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 66ec1acaadee..f2b0dea80116 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h @@ -1,17 +1,19 @@ uint32_t nvc0_grgpc_data[] = { -/* 0x0000: gpc_id */ - 0x00000000, -/* 0x0004: gpc_mmio_list_head */ - 0x00000000, -/* 0x0008: gpc_mmio_list_tail */ - 0x00000000, -/* 0x000c: tpc_count */ - 0x00000000, -/* 0x0010: tpc_mask */ +/* 0x0000: gpc_mmio_list_head */ + 0x00000064, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x00000064, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x00000064, +/* 0x000c: unk_mmio_list_tail */ + 0x00000064, +/* 0x0010: gpc_id */ 0x00000000, -/* 0x0014: tpc_mmio_list_head */ +/* 0x0014: tpc_count */ 0x00000000, -/* 0x0018: tpc_mmio_list_tail */ +/* 0x0018: tpc_mask */ 0x00000000, /* 0x001c: cmd_queue */ 0x00000000, @@ -32,107 +34,17 @@ uint32_t nvc0_grgpc_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0064: chipsets */ - 0x000000c0, - 0x013c00d4, - 0x018c0140, - 0x000000c1, - 0x014000d4, - 0x01a00140, - 0x000000c3, - 0x013c00d4, - 0x019c0140, - 0x000000c4, - 0x013c00d4, - 0x019c0140, - 0x000000c8, - 0x013c00d4, - 0x018c0140, - 0x000000ce, - 0x013c00d4, - 0x019c0140, - 0x000000cf, - 0x013c00d4, - 0x019c0140, - 0x000000d9, - 0x014000d8, - 0x01a80140, - 0x000000d7, - 0x014000d8, - 0x01a80140, - 0x00000000, -/* 0x00d4: nvc0_gpc_mmio_head */ - 0x00000408, -/* 0x00d8: nvd9_gpc_mmio_head */ - 0x00000380, - 0x04000400, - 0x0800040c, - 0x20000450, - 0x00000600, - 0x00000684, - 0x10000700, - 0x00000800, - 0x08000808, - 0x00000828, - 0x00000830, - 0x000008d8, - 0x000008e0, - 0x140008e8, - 0x0000091c, - 0x08000924, - 0x00000b00, - 0x14000b08, - 0x00000bb8, - 0x00000c08, - 0x1c000c10, - 0x00000c80, - 0x00000c8c, - 0x08001000, - 0x00001014, -/* 0x013c: nvc0_gpc_mmio_tail */ - 0x00000c6c, -/* 0x0140: nvc1_gpc_mmio_tail */ -/* 0x0140: nvc0_tpc_mmio_head */ - 0x00000018, - 0x0000003c, - 0x00000048, - 0x00000064, - 0x00000088, - 0x14000200, - 0x14000300, - 0x000003d0, - 0x040003e0, - 0x08000400, - 0x00000420, - 0x000004b0, - 0x000004e8, - 0x000004f4, - 0x04000520, - 0x0c000604, - 0x4c000644, - 0x00000698, - 0x04000750, -/* 0x018c: nvc0_tpc_mmio_tail */ - 0x0400021c, - 0x000002c4, - 0x1c000730, - 0x00000758, -/* 0x019c: nvc3_tpc_mmio_tail */ - 0x00000544, -/* 0x01a0: nvc1_tpc_mmio_tail */ - 0x04000424, - 0x000006e0, }; uint32_t nvc0_grgpc_code[] = { - 0x03060ef5, + 0x03180ef5, /* 0x0004: queue_put */ 0x9800d898, 0x86f001d9, 0x0489b808, 0xf00c1bf4, 0x21f502f7, - 0x00f802ec, + 0x00f802fe, /* 0x001c: queue_put_next */ 0xb60798c4, 0x8dbb0384, @@ -164,7 +76,7 @@ uint32_t nvc0_grgpc_code[] = { 0xc800bccf, 0x1bf41fcc, 0x06a7f0fa, - 0x010321f5, + 0x010921f5, 0xf840bfcf, /* 0x008d: nv_wr32 */ 0x28b7f100, @@ -186,63 +98,66 @@ uint32_t nvc0_grgpc_code[] = { 0x0684b604, 0xf80080d0, /* 0x00c9: wait_donez */ - 0x3c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d000, - 0x081887f1, - 0xd00684b6, -/* 0x00e2: wait_donez_ne */ - 0x87f1008a, - 0x84b60400, - 0x0088cf06, + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, 0xf4888aff, - 0x87f1f31b, - 0x84b6085c, - 0xf094bd06, - 0x89d00099, -/* 0x0103: wait_doneo */ - 0xf100f800, - 0xb6083c87, - 0x94bd0684, - 0xd00099f0, - 0x87f10089, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, 0x84b60818, 0x008ad006, -/* 0x011c: wait_doneo_e */ +/* 0x0124: wait_doneo_e */ 0x040087f1, 0xcf0684b6, 0x8aff0088, 0xf30bf488, - 0x085c87f1, - 0xbd0684b6, - 0x0099f094, - 0xf80089d0, -/* 0x013d: mmctx_size */ -/* 0x013f: nv_mmctx_size_loop */ - 0x9894bd00, - 0x85b600e8, - 0x0180b61a, - 0xbb0284b6, - 0xe0b60098, - 0x04efb804, - 0xb9eb1bf4, - 0x00f8029f, -/* 0x015c: mmctx_xfer */ - 0x083c87f1, - 0xbd0684b6, - 0x0199f094, - 0xf10089d0, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, 0xb6071087, 0x94bd0684, 0xf405bbfd, 0x8bd0090b, 0x0099f000, -/* 0x0180: mmctx_base_disabled */ +/* 0x018c: mmctx_base_disabled */ 0xf405eefd, 0x8ed00c0b, 0xc08fd080, -/* 0x018f: mmctx_multi_disabled */ +/* 0x019b: mmctx_multi_disabled */ 0xb70199f0, 0xc8010080, 0xb4b600ab, @@ -250,8 +165,8 @@ uint32_t nvc0_grgpc_code[] = { 0xb601aec8, 0xbefd11e4, 0x008bd005, -/* 0x01a8: mmctx_exec_loop */ -/* 0x01a8: mmctx_wait_free */ +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ 0xf0008ecf, 0x0bf41fe4, 0x00ce98fa, @@ -260,76 +175,77 @@ uint32_t nvc0_grgpc_code[] = { 0x04cdb804, 0xc8e81bf4, 0x1bf402ab, -/* 0x01c9: mmctx_fini_wait */ +/* 0x01d5: mmctx_fini_wait */ 0x008bcf18, 0xb01fb4f0, 0x1bf410b4, 0x02a7f0f7, 0xf4c921f4, -/* 0x01de: mmctx_stop */ +/* 0x01ea: mmctx_stop */ 0xabc81b0e, 0x10b4b600, 0xf00cb9f0, 0x8bd012b9, -/* 0x01ed: mmctx_stop_wait */ +/* 0x01f9: mmctx_stop_wait */ 0x008bcf00, 0xf412bbc8, -/* 0x01f6: mmctx_done */ - 0x87f1fa1b, - 0x84b6085c, - 0xf094bd06, - 0x89d00199, -/* 0x0207: strand_wait */ - 0xf900f800, - 0x02a7f0a0, - 0xfcc921f4, -/* 0x0213: strand_pre */ - 0xf100f8a0, - 0xf04afc87, - 0x97f00283, - 0x0089d00c, - 0x020721f5, -/* 0x0226: strand_post */ - 0x87f100f8, - 0x83f04afc, - 0x0d97f002, - 0xf50089d0, - 0xf8020721, -/* 0x0239: strand_set */ - 0xfca7f100, - 0x02a3f04f, - 0x0500aba2, - 0xd00fc7f0, - 0xc7f000ac, - 0x00bcd00b, - 0x020721f5, - 0xf000aed0, - 0xbcd00ac7, - 0x0721f500, -/* 0x0263: strand_ctx_init */ - 0xf100f802, - 0xb6083c87, - 0x94bd0684, - 0xd00399f0, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, 0x21f50089, - 0xe7f00213, - 0x3921f503, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, 0xfca7f102, 0x02a3f046, 0x0400aba0, 0xf040a0d0, 0xbcd001c7, - 0x0721f500, + 0x1521f500, 0x010c9202, 0xf000acd0, 0xbcd002c7, - 0x0721f500, - 0x2621f502, + 0x1521f500, + 0x3421f502, 0x8087f102, 0x0684b608, 0xb70089cf, 0x95220080, -/* 0x02ba: ctx_init_strand_loop */ +/* 0x02ca: ctx_init_strand_loop */ 0x8ed008fe, 0x408ed000, 0xb6808acf, @@ -338,86 +254,74 @@ uint32_t nvc0_grgpc_code[] = { 0xb60480b6, 0x1bf40192, 0x08e4b6e8, - 0xf1f2efbc, - 0xb6085c87, - 0x94bd0684, - 0xd00399f0, - 0x00f80089, -/* 0x02ec: error */ - 0xe7f1e0f9, - 0xe3f09814, - 0x8d21f440, - 0x041ce0b7, - 0xf401f7f0, - 0xe0fc8d21, -/* 0x0306: init */ - 0x04bd00f8, - 0xf10004fe, - 0xf0120017, - 0x12d00227, - 0x3e17f100, - 0x0010fe04, - 0x040017f1, - 0xf0c010d0, - 0x12d00427, - 0x1031f400, - 0x060817f1, - 0xcf0614b6, - 0x37f00012, - 0x1f24f001, - 0xb60432bb, - 0x02800132, - 0x04038003, - 0x040010b7, - 0x800012cf, - 0x27f10002, - 0x24b60800, - 0x0022cf06, -/* 0x035f: init_find_chipset */ - 0xb65817f0, - 0x13980c10, - 0x0432b800, - 0xb00b0bf4, - 0x1bf40034, -/* 0x0373: init_context */ - 0xf100f8f1, - 0xb6080027, - 0x22cf0624, - 0xf134bd40, - 0xb6070047, - 0x25950644, - 0x0045d008, - 0xbd4045d0, - 0x58f4bde4, - 0x1f58021e, - 0x020e4003, - 0xf5040f40, - 0xbb013d21, - 0x3fbb002f, - 0x041e5800, - 0x40051f58, - 0x0f400a0e, - 0x3d21f50c, - 0x030e9801, - 0xbb00effd, - 0x3ebb002e, - 0x0040b700, - 0x0235b613, - 0xb60043d0, - 0x35b60825, - 0x0120b606, - 0xb60130b6, - 0x34b60824, - 0x022fb908, - 0x026321f5, - 0xf1003fbb, - 0xb6080017, - 0x13d00614, - 0x0010b740, - 0xf024bd08, - 0x12d01f29, -/* 0x0401: main */ - 0x0031f400, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0xe0f900f8, + 0x9814e7f1, + 0xf440e3f0, + 0xe0b78d21, + 0xf7f0041c, + 0x8d21f401, + 0x00f8e0fc, +/* 0x0318: init */ + 0x04fe04bd, + 0x0017f100, + 0x0227f012, + 0xf10012d0, + 0xfe042617, + 0x17f10010, + 0x10d00400, + 0x0427f0c0, + 0xf40012d0, + 0x17f11031, + 0x14b60608, + 0x0012cf06, + 0xf00137f0, + 0x32bb1f24, + 0x0132b604, + 0x80050280, + 0x10b70603, + 0x12cf0400, + 0x04028000, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0x070047f1, + 0x950644b6, + 0x45d00825, + 0x4045d000, + 0x98000e98, + 0x21f5010f, + 0x2fbb0147, + 0x003fbb00, + 0x98010e98, + 0x21f5020f, + 0x0e980147, + 0x00effd05, + 0xbb002ebb, + 0x40b7003e, + 0x35b61300, + 0x0043d002, + 0xb60825b6, + 0x20b60635, + 0x0130b601, + 0xb60824b6, + 0x2fb90834, + 0x7121f502, + 0x003fbb02, + 0x010007f1, + 0xd00203f0, + 0x04bd0003, + 0x29f024bd, + 0x0007f11f, + 0x0203f008, + 0xbd0002d0, +/* 0x03e9: main */ + 0x0031f404, 0xf00028f4, 0x21f41cd7, 0xf401f439, @@ -428,94 +332,100 @@ uint32_t nvc0_grgpc_code[] = { 0x01e4b604, 0xfe051efd, 0x21f50018, - 0x0ef404c3, -/* 0x0431: main_not_ctx_xfer */ + 0x0ef404ad, +/* 0x0419: main_not_ctx_xfer */ 0x10ef94d3, 0xf501f5f0, - 0xf402ec21, -/* 0x043e: ih */ + 0xf402fe21, +/* 0x0426: ih */ 0x80f9c60e, 0xf90188fe, 0xf990f980, 0xf9b0f9a0, 0xf9e0f9d0, - 0x800acff0, - 0xf404abc4, - 0xb7f11d0b, - 0xd7f01900, - 0x40becf1c, - 0xf400bfcf, - 0xb0b70421, - 0xe7f00400, - 0x00bed001, -/* 0x0474: ih_no_fifo */ - 0xfc400ad0, - 0xfce0fcf0, - 0xfcb0fcd0, - 0xfc90fca0, - 0x0088fe80, - 0x32f480fc, -/* 0x048f: hub_barrier_done */ - 0xf001f800, - 0x0e9801f7, - 0x04febb00, - 0x9418e7f1, - 0xf440e3f0, - 0x00f88d21, -/* 0x04a4: ctx_redswitch */ - 0x0614e7f1, - 0xf006e4b6, - 0xefd020f7, - 0x08f7f000, -/* 0x04b4: ctx_redswitch_delay */ - 0xf401f2b6, - 0xf7f1fd1b, - 0xefd00a20, -/* 0x04c3: ctx_xfer */ - 0xf100f800, - 0xb60a0417, - 0x1fd00614, - 0x0711f400, - 0x04a421f5, -/* 0x04d4: ctx_xfer_not_load */ - 0x4afc17f1, - 0xf00213f0, - 0x12d00c27, - 0x0721f500, - 0xfc27f102, - 0x0223f047, - 0xf00020d0, - 0x20b6012c, - 0x0012d003, + 0xcf04bdf0, + 0xabc4800a, + 0x1d0bf404, + 0x1900b7f1, + 0xcf1cd7f0, + 0xbfcf40be, + 0x0421f400, + 0x0400b0b7, + 0xd001e7f0, +/* 0x045e: ih_no_fifo */ + 0x0ad000be, + 0xfcf0fc40, + 0xfcd0fce0, + 0xfca0fcb0, + 0xfe80fc90, + 0x80fc0088, + 0xf80032f4, +/* 0x0479: hub_barrier_done */ + 0x01f7f001, + 0xbb040e98, + 0xe7f104fe, + 0xe3f09418, + 0x8d21f440, +/* 0x048e: ctx_redswitch */ + 0xe7f100f8, + 0xe4b60614, + 0x20f7f006, + 0xf000efd0, +/* 0x049e: ctx_redswitch_delay */ + 0xf2b608f7, + 0xfd1bf401, + 0x0a20f7f1, + 0xf800efd0, +/* 0x04ad: ctx_xfer */ + 0x0417f100, + 0x0614b60a, + 0xf4001fd0, + 0x21f50711, +/* 0x04be: ctx_xfer_not_load */ + 0x17f1048e, + 0x13f04afc, + 0x0c27f002, + 0xf50012d0, + 0xf1021521, + 0xf047fc27, + 0x20d00223, + 0x012cf000, + 0xd00320b6, + 0xacf00012, + 0x02a5f001, + 0xf000b7f0, + 0x0c9850b3, + 0x0fc4b604, + 0x9800bcbb, + 0x0d98000c, + 0x00e7f001, + 0x016621f5, 0xf001acf0, - 0xb7f002a5, - 0x50b3f000, - 0xb6000c98, - 0xbcbb0fc4, - 0x010c9800, - 0xf0020d98, - 0x21f500e7, - 0xacf0015c, - 0x04a5f001, - 0x4000b7f1, - 0x9850b3f0, - 0xc4b6000c, - 0x00bcbb0f, - 0x98050c98, - 0x0f98060d, - 0x00e7f104, - 0x5c21f508, - 0x0721f501, - 0x0601f402, -/* 0x054b: ctx_xfer_post */ - 0xf11412f4, - 0xf04afc17, - 0x27f00213, - 0x0012d00d, - 0x020721f5, -/* 0x055c: ctx_xfer_done */ - 0x048f21f5, - 0x000000f8, + 0xb7f104a5, + 0xb3f04000, + 0x040c9850, + 0xbb0fc4b6, + 0x0c9800bc, + 0x020d9801, + 0xf1060f98, + 0xf50800e7, + 0xf5016621, + 0xf4021521, + 0x12f40601, +/* 0x0535: ctx_xfer_post */ + 0xfc17f114, + 0x0213f04a, + 0xd00d27f0, + 0x21f50012, +/* 0x0546: ctx_xfer_done */ + 0x21f50215, + 0x00f80479, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc new file mode 100644 index 000000000000..c2f754edbd7d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 + +#define CHIPSET GF117 +#include "macros.fuc" + +.section #nvd7_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nvd7_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h new file mode 100644 index 000000000000..dd346c2a1624 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h @@ -0,0 +1,475 @@ +uint32_t nvd7_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nvd7_grgpc_code[] = { + 0x03180ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f802fe, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0x0728b7f1, + 0xb906b4b6, + 0xc9f002ec, + 0x00bcd01f, +/* 0x0078: nv_rd32_wait */ + 0xc800bccf, + 0x1bf41fcc, + 0x06a7f0fa, + 0x010921f5, + 0xf840bfcf, +/* 0x008d: nv_wr32 */ + 0x28b7f100, + 0x06b4b607, + 0xb980bfd0, + 0xc9f002ec, + 0x1ec9f01f, +/* 0x00a3: nv_wr32_wait */ + 0xcf00bcd0, + 0xccc800bc, + 0xfa1bf41f, +/* 0x00ae: watchdog_reset */ + 0x87f100f8, + 0x84b60430, + 0x1ff9f006, + 0xf8008fd0, +/* 0x00bd: watchdog_clear */ + 0x3087f100, + 0x0684b604, + 0xf80080d0, +/* 0x00c9: wait_donez */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, + 0xf4888aff, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, + 0x84b60818, + 0x008ad006, +/* 0x0124: wait_doneo_e */ + 0x040087f1, + 0xcf0684b6, + 0x8aff0088, + 0xf30bf488, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, + 0xb6071087, + 0x94bd0684, + 0xf405bbfd, + 0x8bd0090b, + 0x0099f000, +/* 0x018c: mmctx_base_disabled */ + 0xf405eefd, + 0x8ed00c0b, + 0xc08fd080, +/* 0x019b: mmctx_multi_disabled */ + 0xb70199f0, + 0xc8010080, + 0xb4b600ab, + 0x0cb9f010, + 0xb601aec8, + 0xbefd11e4, + 0x008bd005, +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ + 0xf0008ecf, + 0x0bf41fe4, + 0x00ce98fa, + 0xd005e9fd, + 0xc0b6c08e, + 0x04cdb804, + 0xc8e81bf4, + 0x1bf402ab, +/* 0x01d5: mmctx_fini_wait */ + 0x008bcf18, + 0xb01fb4f0, + 0x1bf410b4, + 0x02a7f0f7, + 0xf4c921f4, +/* 0x01ea: mmctx_stop */ + 0xabc81b0e, + 0x10b4b600, + 0xf00cb9f0, + 0x8bd012b9, +/* 0x01f9: mmctx_stop_wait */ + 0x008bcf00, + 0xf412bbc8, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, + 0x21f50089, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, + 0xfca7f102, + 0x02a3f046, + 0x0400aba0, + 0xf040a0d0, + 0xbcd001c7, + 0x1521f500, + 0x010c9202, + 0xf000acd0, + 0xbcd002c7, + 0x1521f500, + 0x3421f502, + 0x8087f102, + 0x0684b608, + 0xb70089cf, + 0x95220080, +/* 0x02ca: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0xe0f900f8, + 0x9814e7f1, + 0xf440e3f0, + 0xe0b78d21, + 0xf7f0041c, + 0x8d21f401, + 0x00f8e0fc, +/* 0x0318: init */ + 0x04fe04bd, + 0x0017f100, + 0x0227f012, + 0xf10012d0, + 0xfe047017, + 0x17f10010, + 0x10d00400, + 0x0427f0c0, + 0xf40012d0, + 0x17f11031, + 0x14b60608, + 0x0012cf06, + 0xf00137f0, + 0x32bb1f24, + 0x0132b604, + 0x80050280, + 0x10b70603, + 0x12cf0400, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0371: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0386: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40126b0, +/* 0x0392: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0x070047f1, + 0x950644b6, + 0x45d00825, + 0x4045d000, + 0x98000e98, + 0x21f5010f, + 0x2fbb0147, + 0x003fbb00, + 0x98010e98, + 0x21f5020f, + 0x0e980147, + 0x00effd05, + 0xbb002ebb, + 0x0e98003e, + 0x030f9802, + 0x014721f5, + 0xfd070e98, + 0x2ebb00ef, + 0x003ebb00, + 0x130040b7, + 0xd00235b6, + 0x25b60043, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb027121, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0080007, + 0x02d00203, +/* 0x0433: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x04f721f5, +/* 0x0463: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0xfe21f501, + 0xc60ef402, +/* 0x0470: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x800acf04, + 0xf404abc4, + 0xb7f11d0b, + 0xd7f01900, + 0x40becf24, + 0xf400bfcf, + 0xb0b70421, + 0xe7f00400, + 0x00bed001, +/* 0x04a8: ih_no_fifo */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x04c3: hub_barrier_done */ + 0xf001f800, + 0x0e9801f7, + 0x04febb04, + 0x9418e7f1, + 0xf440e3f0, + 0x00f88d21, +/* 0x04d8: ctx_redswitch */ + 0x0614e7f1, + 0xf006e4b6, + 0xefd020f7, + 0x08f7f000, +/* 0x04e8: ctx_redswitch_delay */ + 0xf401f2b6, + 0xf7f1fd1b, + 0xefd00a20, +/* 0x04f7: ctx_xfer */ + 0xf100f800, + 0xb60a0417, + 0x1fd00614, + 0x0711f400, + 0x04d821f5, +/* 0x0508: ctx_xfer_not_load */ + 0x4afc17f1, + 0xf00213f0, + 0x12d00c27, + 0x1521f500, + 0xfc27f102, + 0x0223f047, + 0xf00020d0, + 0x20b6012c, + 0x0012d003, + 0xf001acf0, + 0xb7f002a5, + 0x50b3f000, + 0xb6040c98, + 0xbcbb0fc4, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xacf00166, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf00166, + 0x04a5f001, + 0x3000b7f1, + 0x9850b3f0, + 0xc4b6040c, + 0x00bcbb0f, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6621f502, + 0x1521f501, + 0x0601f402, +/* 0x05a3: ctx_xfer_post */ + 0xf11412f4, + 0xf04afc17, + 0x27f00213, + 0x0012d00d, + 0x021521f5, +/* 0x05b4: ctx_xfer_done */ + 0x04c321f5, + 0x000000f8, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc index 2fc585eeff95..6b906cd2a31f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc @@ -22,150 +22,15 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#define NVGK +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 + +#define CHIPSET GK100 #include "macros.fuc" .section #nve0_grgpc_data #define INCLUDE_DATA #include "com.fuc" #include "gpc.fuc" - -chipsets: -.b8 0xe4 0 0 0 -.b16 #nve4_gpc_mmio_head -.b16 #nve4_gpc_mmio_tail -.b16 #nve4_tpc_mmio_head -.b16 #nve4_tpc_mmio_tail -.b8 0xe7 0 0 0 -.b16 #nve4_gpc_mmio_head -.b16 #nve4_gpc_mmio_tail -.b16 #nve4_tpc_mmio_head -.b16 #nve4_tpc_mmio_tail -.b8 0xe6 0 0 0 -.b16 #nve4_gpc_mmio_head -.b16 #nve4_gpc_mmio_tail -.b16 #nve4_tpc_mmio_head -.b16 #nve4_tpc_mmio_tail -.b8 0xf0 0 0 0 -.b16 #nvf0_gpc_mmio_head -.b16 #nvf0_gpc_mmio_tail -.b16 #nvf0_tpc_mmio_head -.b16 #nvf0_tpc_mmio_tail -.b8 0 0 0 0 - -// GPC mmio lists -nve4_gpc_mmio_head: -mmctx_data(0x000380, 1) -mmctx_data(0x000400, 2) -mmctx_data(0x00040c, 3) -mmctx_data(0x000450, 9) -mmctx_data(0x000600, 1) -mmctx_data(0x000684, 1) -mmctx_data(0x000700, 5) -mmctx_data(0x000800, 1) -mmctx_data(0x000808, 3) -mmctx_data(0x000828, 1) -mmctx_data(0x000830, 1) -mmctx_data(0x0008d8, 1) -mmctx_data(0x0008e0, 1) -mmctx_data(0x0008e8, 6) -mmctx_data(0x00091c, 1) -mmctx_data(0x000924, 3) -mmctx_data(0x000b00, 1) -mmctx_data(0x000b08, 6) -mmctx_data(0x000bb8, 1) -mmctx_data(0x000c08, 1) -mmctx_data(0x000c10, 8) -mmctx_data(0x000c40, 1) -mmctx_data(0x000c6c, 1) -mmctx_data(0x000c80, 1) -mmctx_data(0x000c8c, 1) -mmctx_data(0x001000, 3) -mmctx_data(0x001014, 1) -mmctx_data(0x003024, 1) -mmctx_data(0x0030c0, 2) -mmctx_data(0x0030e4, 1) -mmctx_data(0x003100, 6) -mmctx_data(0x0031d0, 1) -mmctx_data(0x0031e0, 2) -nve4_gpc_mmio_tail: - -nvf0_gpc_mmio_head: -mmctx_data(0x000380, 1) -mmctx_data(0x000400, 2) -mmctx_data(0x00040c, 3) -mmctx_data(0x000450, 9) -mmctx_data(0x000600, 1) -mmctx_data(0x000684, 1) -mmctx_data(0x000700, 5) -mmctx_data(0x000800, 1) -mmctx_data(0x000808, 3) -mmctx_data(0x000828, 1) -mmctx_data(0x000830, 1) -mmctx_data(0x0008d8, 1) -mmctx_data(0x0008e0, 1) -mmctx_data(0x0008e8, 6) -mmctx_data(0x00091c, 1) -mmctx_data(0x000924, 3) -mmctx_data(0x000b00, 1) -mmctx_data(0x000b08, 6) -mmctx_data(0x000bb8, 1) -mmctx_data(0x000c08, 1) -mmctx_data(0x000c10, 8) -mmctx_data(0x000c40, 1) -mmctx_data(0x000c6c, 1) -mmctx_data(0x000c80, 1) -mmctx_data(0x000c8c, 1) -mmctx_data(0x000d24, 1) -mmctx_data(0x001000, 3) -mmctx_data(0x001014, 1) -nvf0_gpc_mmio_tail: - -// TPC mmio lists -nve4_tpc_mmio_head: -mmctx_data(0x000048, 1) -mmctx_data(0x000064, 1) -mmctx_data(0x000088, 1) -mmctx_data(0x000200, 6) -mmctx_data(0x00021c, 2) -mmctx_data(0x000230, 1) -mmctx_data(0x0002c4, 1) -mmctx_data(0x000400, 3) -mmctx_data(0x000420, 3) -mmctx_data(0x0004e8, 1) -mmctx_data(0x0004f4, 1) -mmctx_data(0x000604, 4) -mmctx_data(0x000644, 22) -mmctx_data(0x0006ac, 2) -mmctx_data(0x0006c8, 1) -mmctx_data(0x000730, 8) -mmctx_data(0x000758, 1) -mmctx_data(0x000770, 1) -mmctx_data(0x000778, 2) -nve4_tpc_mmio_tail: - -nvf0_tpc_mmio_head: -mmctx_data(0x000048, 1) -mmctx_data(0x000064, 1) -mmctx_data(0x000088, 1) -mmctx_data(0x000200, 6) -mmctx_data(0x00021c, 2) -mmctx_data(0x000230, 1) -mmctx_data(0x0002c4, 1) -mmctx_data(0x000400, 3) -mmctx_data(0x000420, 3) -mmctx_data(0x0004e8, 1) -mmctx_data(0x0004f4, 1) -mmctx_data(0x000604, 4) -mmctx_data(0x000644, 22) -mmctx_data(0x0006ac, 2) -mmctx_data(0x0006b8, 1) -mmctx_data(0x0006c8, 1) -mmctx_data(0x000730, 8) -mmctx_data(0x000758, 1) -mmctx_data(0x000770, 1) -mmctx_data(0x000778, 2) -nvf0_tpc_mmio_tail: #undef INCLUDE_DATA .section #nve0_grgpc_code diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h index 504ae96cd3dd..7ff5ef6b0804 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h @@ -1,169 +1,54 @@ uint32_t nve0_grgpc_data[] = { -/* 0x0000: gpc_id */ +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, -/* 0x0004: gpc_mmio_list_head */ 0x00000000, -/* 0x0008: gpc_mmio_list_tail */ 0x00000000, -/* 0x000c: tpc_count */ - 0x00000000, -/* 0x0010: tpc_mask */ - 0x00000000, -/* 0x0014: tpc_mmio_list_head */ - 0x00000000, -/* 0x0018: tpc_mmio_list_tail */ - 0x00000000, -/* 0x001c: cmd_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0064: chipsets */ - 0x000000e4, - 0x011c0098, - 0x01d8018c, - 0x000000e7, - 0x011c0098, - 0x01d8018c, - 0x000000e6, - 0x011c0098, - 0x01d8018c, - 0x000000f0, - 0x018c011c, - 0x022801d8, - 0x00000000, -/* 0x0098: nve4_gpc_mmio_head */ - 0x00000380, - 0x04000400, - 0x0800040c, - 0x20000450, - 0x00000600, - 0x00000684, - 0x10000700, - 0x00000800, - 0x08000808, - 0x00000828, - 0x00000830, - 0x000008d8, - 0x000008e0, - 0x140008e8, - 0x0000091c, - 0x08000924, - 0x00000b00, - 0x14000b08, - 0x00000bb8, - 0x00000c08, - 0x1c000c10, - 0x00000c40, - 0x00000c6c, - 0x00000c80, - 0x00000c8c, - 0x08001000, - 0x00001014, - 0x00003024, - 0x040030c0, - 0x000030e4, - 0x14003100, - 0x000031d0, - 0x040031e0, -/* 0x011c: nve4_gpc_mmio_tail */ -/* 0x011c: nvf0_gpc_mmio_head */ - 0x00000380, - 0x04000400, - 0x0800040c, - 0x20000450, - 0x00000600, - 0x00000684, - 0x10000700, - 0x00000800, - 0x08000808, - 0x00000828, - 0x00000830, - 0x000008d8, - 0x000008e0, - 0x140008e8, - 0x0000091c, - 0x08000924, - 0x00000b00, - 0x14000b08, - 0x00000bb8, - 0x00000c08, - 0x1c000c10, - 0x00000c40, - 0x00000c6c, - 0x00000c80, - 0x00000c8c, - 0x00000d24, - 0x08001000, - 0x00001014, -/* 0x018c: nvf0_gpc_mmio_tail */ -/* 0x018c: nve4_tpc_mmio_head */ - 0x00000048, - 0x00000064, - 0x00000088, - 0x14000200, - 0x0400021c, - 0x00000230, - 0x000002c4, - 0x08000400, - 0x08000420, - 0x000004e8, - 0x000004f4, - 0x0c000604, - 0x54000644, - 0x040006ac, - 0x000006c8, - 0x1c000730, - 0x00000758, - 0x00000770, - 0x04000778, -/* 0x01d8: nve4_tpc_mmio_tail */ -/* 0x01d8: nvf0_tpc_mmio_head */ - 0x00000048, - 0x00000064, - 0x00000088, - 0x14000200, - 0x0400021c, - 0x00000230, - 0x000002c4, - 0x08000400, - 0x08000420, - 0x000004e8, - 0x000004f4, - 0x0c000604, - 0x54000644, - 0x040006ac, - 0x000006b8, - 0x000006c8, - 0x1c000730, - 0x00000758, - 0x00000770, - 0x04000778, }; uint32_t nve0_grgpc_code[] = { - 0x03060ef5, + 0x03180ef5, /* 0x0004: queue_put */ 0x9800d898, 0x86f001d9, 0x0489b808, 0xf00c1bf4, 0x21f502f7, - 0x00f802ec, + 0x00f802fe, /* 0x001c: queue_put_next */ 0xb60798c4, 0x8dbb0384, @@ -195,7 +80,7 @@ uint32_t nve0_grgpc_code[] = { 0xc800bccf, 0x1bf41fcc, 0x06a7f0fa, - 0x010321f5, + 0x010921f5, 0xf840bfcf, /* 0x008d: nv_wr32 */ 0x28b7f100, @@ -217,63 +102,66 @@ uint32_t nve0_grgpc_code[] = { 0x0684b604, 0xf80080d0, /* 0x00c9: wait_donez */ - 0x3c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d000, - 0x081887f1, - 0xd00684b6, -/* 0x00e2: wait_donez_ne */ - 0x87f1008a, - 0x84b60400, - 0x0088cf06, + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, 0xf4888aff, - 0x87f1f31b, - 0x84b6085c, - 0xf094bd06, - 0x89d00099, -/* 0x0103: wait_doneo */ - 0xf100f800, - 0xb6083c87, - 0x94bd0684, - 0xd00099f0, - 0x87f10089, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, 0x84b60818, 0x008ad006, -/* 0x011c: wait_doneo_e */ +/* 0x0124: wait_doneo_e */ 0x040087f1, 0xcf0684b6, 0x8aff0088, 0xf30bf488, - 0x085c87f1, - 0xbd0684b6, - 0x0099f094, - 0xf80089d0, -/* 0x013d: mmctx_size */ -/* 0x013f: nv_mmctx_size_loop */ - 0x9894bd00, - 0x85b600e8, - 0x0180b61a, - 0xbb0284b6, - 0xe0b60098, - 0x04efb804, - 0xb9eb1bf4, - 0x00f8029f, -/* 0x015c: mmctx_xfer */ - 0x083c87f1, - 0xbd0684b6, - 0x0199f094, - 0xf10089d0, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, 0xb6071087, 0x94bd0684, 0xf405bbfd, 0x8bd0090b, 0x0099f000, -/* 0x0180: mmctx_base_disabled */ +/* 0x018c: mmctx_base_disabled */ 0xf405eefd, 0x8ed00c0b, 0xc08fd080, -/* 0x018f: mmctx_multi_disabled */ +/* 0x019b: mmctx_multi_disabled */ 0xb70199f0, 0xc8010080, 0xb4b600ab, @@ -281,8 +169,8 @@ uint32_t nve0_grgpc_code[] = { 0xb601aec8, 0xbefd11e4, 0x008bd005, -/* 0x01a8: mmctx_exec_loop */ -/* 0x01a8: mmctx_wait_free */ +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ 0xf0008ecf, 0x0bf41fe4, 0x00ce98fa, @@ -291,76 +179,77 @@ uint32_t nve0_grgpc_code[] = { 0x04cdb804, 0xc8e81bf4, 0x1bf402ab, -/* 0x01c9: mmctx_fini_wait */ +/* 0x01d5: mmctx_fini_wait */ 0x008bcf18, 0xb01fb4f0, 0x1bf410b4, 0x02a7f0f7, 0xf4c921f4, -/* 0x01de: mmctx_stop */ +/* 0x01ea: mmctx_stop */ 0xabc81b0e, 0x10b4b600, 0xf00cb9f0, 0x8bd012b9, -/* 0x01ed: mmctx_stop_wait */ +/* 0x01f9: mmctx_stop_wait */ 0x008bcf00, 0xf412bbc8, -/* 0x01f6: mmctx_done */ - 0x87f1fa1b, - 0x84b6085c, - 0xf094bd06, - 0x89d00199, -/* 0x0207: strand_wait */ - 0xf900f800, - 0x02a7f0a0, - 0xfcc921f4, -/* 0x0213: strand_pre */ - 0xf100f8a0, - 0xf04afc87, - 0x97f00283, - 0x0089d00c, - 0x020721f5, -/* 0x0226: strand_post */ - 0x87f100f8, - 0x83f04afc, - 0x0d97f002, - 0xf50089d0, - 0xf8020721, -/* 0x0239: strand_set */ - 0xfca7f100, - 0x02a3f04f, - 0x0500aba2, - 0xd00fc7f0, - 0xc7f000ac, - 0x00bcd00b, - 0x020721f5, - 0xf000aed0, - 0xbcd00ac7, - 0x0721f500, -/* 0x0263: strand_ctx_init */ - 0xf100f802, - 0xb6083c87, - 0x94bd0684, - 0xd00399f0, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, 0x21f50089, - 0xe7f00213, - 0x3921f503, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, 0xfca7f102, 0x02a3f046, 0x0400aba0, 0xf040a0d0, 0xbcd001c7, - 0x0721f500, + 0x1521f500, 0x010c9202, 0xf000acd0, 0xbcd002c7, - 0x0721f500, - 0x2621f502, + 0x1521f500, + 0x3421f502, 0x8087f102, 0x0684b608, 0xb70089cf, 0x95220080, -/* 0x02ba: ctx_init_strand_loop */ +/* 0x02ca: ctx_init_strand_loop */ 0x8ed008fe, 0x408ed000, 0xb6808acf, @@ -369,150 +258,160 @@ uint32_t nve0_grgpc_code[] = { 0xb60480b6, 0x1bf40192, 0x08e4b6e8, - 0xf1f2efbc, - 0xb6085c87, - 0x94bd0684, - 0xd00399f0, - 0x00f80089, -/* 0x02ec: error */ - 0xe7f1e0f9, - 0xe3f09814, - 0x8d21f440, - 0x041ce0b7, - 0xf401f7f0, - 0xe0fc8d21, -/* 0x0306: init */ - 0x04bd00f8, - 0xf10004fe, - 0xf0120017, - 0x12d00227, - 0x3e17f100, - 0x0010fe04, - 0x040017f1, - 0xf0c010d0, - 0x12d00427, - 0x1031f400, - 0x060817f1, - 0xcf0614b6, - 0x37f00012, - 0x1f24f001, - 0xb60432bb, - 0x02800132, - 0x04038003, - 0x040010b7, - 0x800012cf, - 0x27f10002, - 0x24b60800, - 0x0022cf06, -/* 0x035f: init_find_chipset */ - 0xb65817f0, - 0x13980c10, - 0x0432b800, - 0xb00b0bf4, - 0x1bf40034, -/* 0x0373: init_context */ - 0xf100f8f1, - 0xb6080027, - 0x22cf0624, - 0xf134bd40, - 0xb6070047, - 0x25950644, - 0x0045d008, - 0xbd4045d0, - 0x58f4bde4, - 0x1f58021e, - 0x020e4003, - 0xf5040f40, - 0xbb013d21, - 0x3fbb002f, - 0x041e5800, - 0x40051f58, - 0x0f400a0e, - 0x3d21f50c, - 0x030e9801, - 0xbb00effd, - 0x3ebb002e, - 0x0040b700, - 0x0235b613, - 0xb60043d0, - 0x35b60825, - 0x0120b606, - 0xb60130b6, - 0x34b60824, - 0x022fb908, - 0x026321f5, - 0xf1003fbb, - 0xb6080017, - 0x13d00614, - 0x0010b740, - 0xf024bd08, - 0x12d01f29, -/* 0x0401: main */ - 0x0031f400, - 0xf00028f4, - 0x21f41cd7, - 0xf401f439, - 0xf404e4b0, - 0x81fe1e18, - 0x0627f001, - 0x12fd20bd, - 0x01e4b604, - 0xfe051efd, - 0x21f50018, - 0x0ef404c3, -/* 0x0431: main_not_ctx_xfer */ - 0x10ef94d3, - 0xf501f5f0, - 0xf402ec21, -/* 0x043e: ih */ - 0x80f9c60e, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0x800acff0, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0xe0f900f8, + 0x9814e7f1, + 0xf440e3f0, + 0xe0b78d21, + 0xf7f0041c, + 0x8d21f401, + 0x00f8e0fc, +/* 0x0318: init */ + 0x04fe04bd, + 0x0017f100, + 0x0227f012, + 0xf10012d0, + 0xfe047017, + 0x17f10010, + 0x10d00400, + 0x0427f0c0, + 0xf40012d0, + 0x17f11031, + 0x14b60608, + 0x0012cf06, + 0xf00137f0, + 0x32bb1f24, + 0x0132b604, + 0x80050280, + 0x10b70603, + 0x12cf0400, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0371: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0386: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40126b0, +/* 0x0392: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0x070047f1, + 0x950644b6, + 0x45d00825, + 0x4045d000, + 0x98000e98, + 0x21f5010f, + 0x2fbb0147, + 0x003fbb00, + 0x98010e98, + 0x21f5020f, + 0x0e980147, + 0x00effd05, + 0xbb002ebb, + 0x0e98003e, + 0x030f9802, + 0x014721f5, + 0xfd070e98, + 0x2ebb00ef, + 0x003ebb00, + 0x130040b7, + 0xd00235b6, + 0x25b60043, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb027121, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0080007, + 0x02d00203, +/* 0x0433: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x04f721f5, +/* 0x0463: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0xfe21f501, + 0xc60ef402, +/* 0x0470: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x800acf04, 0xf404abc4, 0xb7f11d0b, 0xd7f01900, - 0x40becf1c, + 0x40becf24, 0xf400bfcf, 0xb0b70421, 0xe7f00400, 0x00bed001, -/* 0x0474: ih_no_fifo */ +/* 0x04a8: ih_no_fifo */ 0xfc400ad0, 0xfce0fcf0, 0xfcb0fcd0, 0xfc90fca0, 0x0088fe80, 0x32f480fc, -/* 0x048f: hub_barrier_done */ +/* 0x04c3: hub_barrier_done */ 0xf001f800, 0x0e9801f7, - 0x04febb00, + 0x04febb04, 0x9418e7f1, 0xf440e3f0, 0x00f88d21, -/* 0x04a4: ctx_redswitch */ +/* 0x04d8: ctx_redswitch */ 0x0614e7f1, 0xf006e4b6, 0xefd020f7, 0x08f7f000, -/* 0x04b4: ctx_redswitch_delay */ +/* 0x04e8: ctx_redswitch_delay */ 0xf401f2b6, 0xf7f1fd1b, 0xefd00a20, -/* 0x04c3: ctx_xfer */ +/* 0x04f7: ctx_xfer */ 0xf100f800, 0xb60a0417, 0x1fd00614, 0x0711f400, - 0x04a421f5, -/* 0x04d4: ctx_xfer_not_load */ + 0x04d821f5, +/* 0x0508: ctx_xfer_not_load */ 0x4afc17f1, 0xf00213f0, 0x12d00c27, - 0x0721f500, + 0x1521f500, 0xfc27f102, 0x0223f047, 0xf00020d0, @@ -521,31 +420,40 @@ uint32_t nve0_grgpc_code[] = { 0xf001acf0, 0xb7f002a5, 0x50b3f000, - 0xb6000c98, + 0xb6040c98, 0xbcbb0fc4, - 0x010c9800, - 0xf0020d98, + 0x000c9800, + 0xf0010d98, 0x21f500e7, - 0xacf0015c, + 0xacf00166, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf00166, 0x04a5f001, - 0x4000b7f1, + 0x3000b7f1, 0x9850b3f0, - 0xc4b6000c, + 0xc4b6040c, 0x00bcbb0f, - 0x98050c98, - 0x0f98060d, - 0x00e7f104, - 0x5c21f508, - 0x0721f501, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6621f502, + 0x1521f501, 0x0601f402, -/* 0x054b: ctx_xfer_post */ +/* 0x05a3: ctx_xfer_post */ 0xf11412f4, 0xf04afc17, 0x27f00213, 0x0012d00d, - 0x020721f5, -/* 0x055c: ctx_xfer_done */ - 0x048f21f5, + 0x021521f5, +/* 0x05b4: ctx_xfer_done */ + 0x04c321f5, 0x000000f8, 0x00000000, 0x00000000, @@ -564,26 +472,4 @@ uint32_t nve0_grgpc_code[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc new file mode 100644 index 000000000000..90bbe525b626 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc @@ -0,0 +1,42 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 + +#define CHIPSET GK110 +#include "macros.fuc" + +.section #nvf0_grgpc_data +#define INCLUDE_DATA +#include "com.fuc" +#include "gpc.fuc" +#undef INCLUDE_DATA + +.section #nvf0_grgpc_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "gpc.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h new file mode 100644 index 000000000000..f870507be880 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h @@ -0,0 +1,475 @@ +uint32_t nvf0_grgpc_data[] = { +/* 0x0000: gpc_mmio_list_head */ + 0x0000006c, +/* 0x0004: gpc_mmio_list_tail */ +/* 0x0004: tpc_mmio_list_head */ + 0x0000006c, +/* 0x0008: tpc_mmio_list_tail */ +/* 0x0008: unk_mmio_list_head */ + 0x0000006c, +/* 0x000c: unk_mmio_list_tail */ + 0x0000006c, +/* 0x0010: gpc_id */ + 0x00000000, +/* 0x0014: tpc_count */ + 0x00000000, +/* 0x0018: tpc_mask */ + 0x00000000, +/* 0x001c: unk_count */ + 0x00000000, +/* 0x0020: unk_mask */ + 0x00000000, +/* 0x0024: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t nvf0_grgpc_code[] = { + 0x03180ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f802fe, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0x0728b7f1, + 0xb906b4b6, + 0xc9f002ec, + 0x00bcd01f, +/* 0x0078: nv_rd32_wait */ + 0xc800bccf, + 0x1bf41fcc, + 0x06a7f0fa, + 0x010921f5, + 0xf840bfcf, +/* 0x008d: nv_wr32 */ + 0x28b7f100, + 0x06b4b607, + 0xb980bfd0, + 0xc9f002ec, + 0x1ec9f01f, +/* 0x00a3: nv_wr32_wait */ + 0xcf00bcd0, + 0xccc800bc, + 0xfa1bf41f, +/* 0x00ae: watchdog_reset */ + 0x87f100f8, + 0x84b60430, + 0x1ff9f006, + 0xf8008fd0, +/* 0x00bd: watchdog_clear */ + 0x3087f100, + 0x0684b604, + 0xf80080d0, +/* 0x00c9: wait_donez */ + 0xf094bd00, + 0x07f10099, + 0x03f03700, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, + 0xf4888aff, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f03700, + 0x0009d002, + 0x87f104bd, + 0x84b60818, + 0x008ad006, +/* 0x0124: wait_doneo_e */ + 0x040087f1, + 0xcf0684b6, + 0x8aff0088, + 0xf30bf488, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf0370007, + 0x09d00203, + 0xf104bd00, + 0xb6071087, + 0x94bd0684, + 0xf405bbfd, + 0x8bd0090b, + 0x0099f000, +/* 0x018c: mmctx_base_disabled */ + 0xf405eefd, + 0x8ed00c0b, + 0xc08fd080, +/* 0x019b: mmctx_multi_disabled */ + 0xb70199f0, + 0xc8010080, + 0xb4b600ab, + 0x0cb9f010, + 0xb601aec8, + 0xbefd11e4, + 0x008bd005, +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ + 0xf0008ecf, + 0x0bf41fe4, + 0x00ce98fa, + 0xd005e9fd, + 0xc0b6c08e, + 0x04cdb804, + 0xc8e81bf4, + 0x1bf402ab, +/* 0x01d5: mmctx_fini_wait */ + 0x008bcf18, + 0xb01fb4f0, + 0x1bf410b4, + 0x02a7f0f7, + 0xf4c921f4, +/* 0x01ea: mmctx_stop */ + 0xabc81b0e, + 0x10b4b600, + 0xf00cb9f0, + 0x8bd012b9, +/* 0x01f9: mmctx_stop_wait */ + 0x008bcf00, + 0xf412bbc8, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, + 0x21f50089, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f03700, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, + 0xfca7f102, + 0x02a3f046, + 0x0400aba0, + 0xf040a0d0, + 0xbcd001c7, + 0x1521f500, + 0x010c9202, + 0xf000acd0, + 0xbcd002c7, + 0x1521f500, + 0x3421f502, + 0x8087f102, + 0x0684b608, + 0xb70089cf, + 0x95220080, +/* 0x02ca: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0xe0f900f8, + 0x9814e7f1, + 0xf440e3f0, + 0xe0b78d21, + 0xf7f0041c, + 0x8d21f401, + 0x00f8e0fc, +/* 0x0318: init */ + 0x04fe04bd, + 0x0017f100, + 0x0227f012, + 0xf10012d0, + 0xfe047017, + 0x17f10010, + 0x10d00400, + 0x0427f0c0, + 0xf40012d0, + 0x17f11031, + 0x14b60608, + 0x0012cf06, + 0xf00137f0, + 0x32bb1f24, + 0x0132b604, + 0x80050280, + 0x10b70603, + 0x12cf0400, + 0x04028000, + 0x0c30e7f1, + 0xbd50e3f0, + 0xbd34bd24, +/* 0x0371: init_unk_loop */ + 0x6821f444, + 0xf400f6b0, + 0xf7f00f0b, + 0x04f2bb01, + 0xb6054ffd, +/* 0x0386: init_unk_next */ + 0x20b60130, + 0x04e0b601, + 0xf40226b0, +/* 0x0392: init_unk_done */ + 0x0380e21b, + 0x08048007, + 0x010027f1, + 0xcf0223f0, + 0x34bd0022, + 0x070047f1, + 0x950644b6, + 0x45d00825, + 0x4045d000, + 0x98000e98, + 0x21f5010f, + 0x2fbb0147, + 0x003fbb00, + 0x98010e98, + 0x21f5020f, + 0x0e980147, + 0x00effd05, + 0xbb002ebb, + 0x0e98003e, + 0x030f9802, + 0x014721f5, + 0xfd070e98, + 0x2ebb00ef, + 0x003ebb00, + 0x130040b7, + 0xd00235b6, + 0x25b60043, + 0x0635b608, + 0xb60120b6, + 0x24b60130, + 0x0834b608, + 0xf5022fb9, + 0xbb027121, + 0x07f1003f, + 0x03f00100, + 0x0003d002, + 0x24bd04bd, + 0xf11f29f0, + 0xf0300007, + 0x02d00203, +/* 0x0433: main */ + 0xf404bd00, + 0x28f40031, + 0x24d7f000, + 0xf43921f4, + 0xe4b0f401, + 0x1e18f404, + 0xf00181fe, + 0x20bd0627, + 0xb60412fd, + 0x1efd01e4, + 0x0018fe05, + 0x04f721f5, +/* 0x0463: main_not_ctx_xfer */ + 0x94d30ef4, + 0xf5f010ef, + 0xfe21f501, + 0xc60ef402, +/* 0x0470: ih */ + 0x88fe80f9, + 0xf980f901, + 0xf9a0f990, + 0xf9d0f9b0, + 0xbdf0f9e0, + 0x800acf04, + 0xf404abc4, + 0xb7f11d0b, + 0xd7f01900, + 0x40becf24, + 0xf400bfcf, + 0xb0b70421, + 0xe7f00400, + 0x00bed001, +/* 0x04a8: ih_no_fifo */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x04c3: hub_barrier_done */ + 0xf001f800, + 0x0e9801f7, + 0x04febb04, + 0x9418e7f1, + 0xf440e3f0, + 0x00f88d21, +/* 0x04d8: ctx_redswitch */ + 0x0614e7f1, + 0xf006e4b6, + 0xefd020f7, + 0x08f7f000, +/* 0x04e8: ctx_redswitch_delay */ + 0xf401f2b6, + 0xf7f1fd1b, + 0xefd00a20, +/* 0x04f7: ctx_xfer */ + 0xf100f800, + 0xb60a0417, + 0x1fd00614, + 0x0711f400, + 0x04d821f5, +/* 0x0508: ctx_xfer_not_load */ + 0x4afc17f1, + 0xf00213f0, + 0x12d00c27, + 0x1521f500, + 0xfc27f102, + 0x0223f047, + 0xf00020d0, + 0x20b6012c, + 0x0012d003, + 0xf001acf0, + 0xb7f002a5, + 0x50b3f000, + 0xb6040c98, + 0xbcbb0fc4, + 0x000c9800, + 0xf0010d98, + 0x21f500e7, + 0xacf00166, + 0x00b7f101, + 0x50b3f040, + 0xb6040c98, + 0xbcbb0fc4, + 0x010c9800, + 0x98020d98, + 0xe7f1060f, + 0x21f50800, + 0xacf00166, + 0x04a5f001, + 0x3000b7f1, + 0x9850b3f0, + 0xc4b6040c, + 0x00bcbb0f, + 0x98020c98, + 0x0f98030d, + 0x00e7f108, + 0x6621f502, + 0x1521f501, + 0x0601f402, +/* 0x05a3: ctx_xfer_post */ + 0xf11412f4, + 0xf04afc17, + 0x27f00213, + 0x0012d00d, + 0x021521f5, +/* 0x05b4: ctx_xfer_done */ + 0x04c321f5, + 0x000000f8, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc index 5c68bf6d69aa..b82d2ae89917 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc @@ -24,11 +24,12 @@ */ #ifdef INCLUDE_DATA +hub_mmio_list_head: .b32 #hub_mmio_list_base +hub_mmio_list_tail: .b32 #hub_mmio_list_next + gpc_count: .b32 0 rop_count: .b32 0 cmd_queue: queue_init -hub_mmio_list_head: .b32 0 -hub_mmio_list_tail: .b32 0 ctx_current: .b32 0 @@ -40,6 +41,9 @@ chan_mmio_address: .b32 0 .align 256 xfer_data: .skip 256 +hub_mmio_list_base: +.b32 0x0417e91c // 0x17e91c, 2 +hub_mmio_list_next: #endif #ifdef INCLUDE_CODE @@ -48,23 +52,14 @@ xfer_data: .skip 256 // In: $r15 error code (see nvc0.fuc) // error: - push $r14 - mov $r14 0x814 - shl b32 $r14 6 - iowr I[$r14 + 0x000] $r15 // CC_SCRATCH[5] = error code - mov $r14 0xc1c - shl b32 $r14 6 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) mov $r15 1 - iowr I[$r14 + 0x000] $r15 // INTR_UP_SET - pop $r14 + nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15) ret // HUB fuc initialisation, executed by triggering ucode start, will // fall through to main loop after completion. // -// Input: -// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh) -// // Output: // CC_SCRATCH[0]: // 31:31: set to signal completion @@ -141,31 +136,12 @@ init: iowr I[$r2 + 0x000] $r1 iowr I[$r2 + 0x100] $r1 - // find context data for this chipset - mov $r2 0x800 - shl b32 $r2 6 - iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0] - mov $r15 #chipsets - 8 - init_find_chipset: - add b32 $r15 8 - ld b32 $r3 D[$r15 + 0x00] - cmpu b32 $r3 $r2 - bra e #init_context - cmpu b32 $r3 0 - bra ne #init_find_chipset - // unknown chipset - ret - // context size calculation, reserve first 256 bytes for use by fuc - init_context: mov $r1 256 // calculate size of mmio context data - ld b16 $r14 D[$r15 + 4] - ld b16 $r15 D[$r15 + 6] - sethi $r14 0 - st b32 D[$r0 + #hub_mmio_list_head] $r14 - st b32 D[$r0 + #hub_mmio_list_tail] $r15 + ld b32 $r14 D[$r0 + #hub_mmio_list_head] + ld b32 $r15 D[$r0 + #hub_mmio_list_tail] call #mmctx_size // set mmctx base addresses now so we don't have to do it later, @@ -204,9 +180,6 @@ init: add b32 $r14 $r4 0x804 mov b32 $r15 $r1 call #nv_wr32 // CC_SCRATCH[1] = ctx offset - add b32 $r14 $r4 0x800 - mov b32 $r15 $r2 - call #nv_wr32 // CC_SCRATCH[0] = chipset add b32 $r14 $r4 0x10c clear b32 $r15 call #nv_wr32 @@ -232,13 +205,10 @@ init: bra ne #init_gpc // save context size, and tell host we're ready - mov $r2 0x800 - shl b32 $r2 6 - iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size - add b32 $r2 0x800 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) clear b32 $r1 bset $r1 31 - iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1) // Main program loop, very simple, sleeps until woken up by the interrupt // handler, pulls a command from the queue and executes its handler @@ -330,11 +300,9 @@ main: bra #main main_done: - mov $r1 0x820 - shl b32 $r1 6 clear b32 $r2 bset $r2 31 - iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2) bra #main // interrupt handler @@ -348,6 +316,7 @@ ih: push $r13 push $r14 push $r15 + clear b32 $r0 // incoming fifo command? iord $r10 I[$r0 + 0x200] // INTR @@ -398,7 +367,7 @@ ih: bclr $flags $p0 iret -#ifdef NVGF +#if CHIPSET < GK100 // Not real sure, but, MEM_CMD 7 will hang forever if this isn't done ctx_4160s: mov $r14 0x4160 @@ -562,7 +531,7 @@ ctx_load: // In: $r2 channel address // ctx_chan: -#ifdef NVGF +#if CHIPSET < GK100 call #ctx_4160s #endif call #ctx_load @@ -576,7 +545,7 @@ ctx_chan: iord $r2 I[$r1 + 0x000] or $r2 $r2 bra ne #ctx_chan_wait -#ifdef NVGF +#if CHIPSET < GK100 call #ctx_4160c #endif ret @@ -655,7 +624,7 @@ ctx_xfer: ctx_xfer_pre: mov $r15 0x10 call #ctx_86c -#ifdef NVGF +#if CHIPSET < GK100 call #ctx_4160s #endif bra not $p1 #ctx_xfer_exec @@ -746,7 +715,7 @@ ctx_xfer: call #ctx_mmio_exec ctx_xfer_no_post_mmio: -#ifdef NVGF +#if CHIPSET < GK100 call #ctx_4160c #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc index f144f665b807..3ff52badf932 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc @@ -22,92 +22,13 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#define NVGF +#define CHIPSET GF100 #include "macros.fuc" .section #nvc0_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" - -chipsets: -.b8 0xc0 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xc1 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc1_hub_mmio_tail -.b8 0xc3 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xc4 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xc8 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xce 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xcf 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail -.b8 0xd9 0 0 0 -.b16 #nvd9_hub_mmio_head -.b16 #nvd9_hub_mmio_tail -.b8 0xd7 0 0 0 -.b16 #nvd9_hub_mmio_head -.b16 #nvd9_hub_mmio_tail -.b8 0 0 0 0 - -nvc0_hub_mmio_head: -mmctx_data(0x40402c, 1) -mmctx_data(0x404174, 1) -nvd9_hub_mmio_head: -mmctx_data(0x17e91c, 2) -mmctx_data(0x400204, 2) -mmctx_data(0x404004, 10) -mmctx_data(0x404044, 1) -mmctx_data(0x404094, 14) -mmctx_data(0x4040d0, 7) -mmctx_data(0x4040f8, 1) -mmctx_data(0x404130, 3) -mmctx_data(0x404150, 3) -mmctx_data(0x404164, 2) -mmctx_data(0x404178, 2) -mmctx_data(0x404200, 8) -mmctx_data(0x404404, 14) -mmctx_data(0x404460, 4) -mmctx_data(0x404480, 1) -mmctx_data(0x404498, 1) -mmctx_data(0x404604, 4) -mmctx_data(0x404618, 32) -mmctx_data(0x404698, 21) -mmctx_data(0x4046f0, 2) -mmctx_data(0x404700, 22) -mmctx_data(0x405800, 1) -mmctx_data(0x405830, 3) -mmctx_data(0x405854, 1) -mmctx_data(0x405870, 4) -mmctx_data(0x405a00, 2) -mmctx_data(0x405a18, 1) -mmctx_data(0x406020, 1) -mmctx_data(0x406028, 4) -mmctx_data(0x4064a8, 2) -mmctx_data(0x4064b4, 2) -mmctx_data(0x407804, 1) -mmctx_data(0x40780c, 6) -mmctx_data(0x4078bc, 1) -mmctx_data(0x408000, 7) -mmctx_data(0x408064, 1) -mmctx_data(0x408800, 3) -mmctx_data(0x408900, 3) -mmctx_data(0x408980, 1) -nvc0_hub_mmio_tail: -mmctx_data(0x4064c0, 2) -nvc1_hub_mmio_tail: -mmctx_data(0x4064bc, 3) -nvd9_hub_mmio_tail: #undef INCLUDE_DATA .section #nvc0_grhub_code diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index d1bf23001830..b59f694c0423 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h @@ -1,9 +1,13 @@ uint32_t nvc0_grhub_data[] = { -/* 0x0000: gpc_count */ +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ 0x00000000, -/* 0x0004: rop_count */ +/* 0x000c: rop_count */ 0x00000000, -/* 0x0008: cmd_queue */ +/* 0x0010: cmd_queue */ 0x00000000, 0x00000000, 0x00000000, @@ -22,10 +26,6 @@ uint32_t nvc0_grhub_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0050: hub_mmio_list_head */ - 0x00000000, -/* 0x0054: hub_mmio_list_tail */ - 0x00000000, /* 0x0058: ctx_current */ 0x00000000, 0x00000000, @@ -201,84 +201,19 @@ uint32_t nvc0_grhub_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0300: chipsets */ - 0x000000c0, - 0x03f0034c, - 0x000000c1, - 0x03f4034c, - 0x000000c3, - 0x03f0034c, - 0x000000c4, - 0x03f0034c, - 0x000000c8, - 0x03f0034c, - 0x000000ce, - 0x03f0034c, - 0x000000cf, - 0x03f0034c, - 0x000000d9, - 0x03f80354, - 0x000000d7, - 0x03f80354, - 0x00000000, -/* 0x034c: nvc0_hub_mmio_head */ - 0x0040402c, - 0x00404174, -/* 0x0354: nvd9_hub_mmio_head */ +/* 0x0300: hub_mmio_list_base */ 0x0417e91c, - 0x04400204, - 0x24404004, - 0x00404044, - 0x34404094, - 0x184040d0, - 0x004040f8, - 0x08404130, - 0x08404150, - 0x04404164, - 0x04404178, - 0x1c404200, - 0x34404404, - 0x0c404460, - 0x00404480, - 0x00404498, - 0x0c404604, - 0x7c404618, - 0x50404698, - 0x044046f0, - 0x54404700, - 0x00405800, - 0x08405830, - 0x00405854, - 0x0c405870, - 0x04405a00, - 0x00405a18, - 0x00406020, - 0x0c406028, - 0x044064a8, - 0x044064b4, - 0x00407804, - 0x1440780c, - 0x004078bc, - 0x18408000, - 0x00408064, - 0x08408800, - 0x08408900, - 0x00408980, -/* 0x03f0: nvc0_hub_mmio_tail */ - 0x044064c0, -/* 0x03f4: nvc1_hub_mmio_tail */ - 0x084064bc, }; uint32_t nvc0_grhub_code[] = { - 0x03090ef5, + 0x031b0ef5, /* 0x0004: queue_put */ 0x9800d898, 0x86f001d9, 0x0489b808, 0xf00c1bf4, 0x21f502f7, - 0x00f802ec, + 0x00f802fe, /* 0x001c: queue_put_next */ 0xb60798c4, 0x8dbb0384, @@ -310,7 +245,7 @@ uint32_t nvc0_grhub_code[] = { 0xc800bccf, 0x1bf41fcc, 0x06a7f0fa, - 0x010321f5, + 0x010921f5, 0xf840bfcf, /* 0x008d: nv_wr32 */ 0x28b7f100, @@ -332,63 +267,66 @@ uint32_t nvc0_grhub_code[] = { 0x0684b604, 0xf80080d0, /* 0x00c9: wait_donez */ - 0x3c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d000, - 0x081887f1, - 0xd00684b6, -/* 0x00e2: wait_donez_ne */ - 0x87f1008a, - 0x84b60400, - 0x0088cf06, + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, 0xf4888aff, - 0x87f1f31b, - 0x84b6085c, - 0xf094bd06, - 0x89d00099, -/* 0x0103: wait_doneo */ - 0xf100f800, - 0xb6083c87, - 0x94bd0684, - 0xd00099f0, - 0x87f10089, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, 0x84b60818, 0x008ad006, -/* 0x011c: wait_doneo_e */ +/* 0x0124: wait_doneo_e */ 0x040087f1, 0xcf0684b6, 0x8aff0088, 0xf30bf488, - 0x085c87f1, - 0xbd0684b6, - 0x0099f094, - 0xf80089d0, -/* 0x013d: mmctx_size */ -/* 0x013f: nv_mmctx_size_loop */ - 0x9894bd00, - 0x85b600e8, - 0x0180b61a, - 0xbb0284b6, - 0xe0b60098, - 0x04efb804, - 0xb9eb1bf4, - 0x00f8029f, -/* 0x015c: mmctx_xfer */ - 0x083c87f1, - 0xbd0684b6, - 0x0199f094, - 0xf10089d0, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, 0xb6071087, 0x94bd0684, 0xf405bbfd, 0x8bd0090b, 0x0099f000, -/* 0x0180: mmctx_base_disabled */ +/* 0x018c: mmctx_base_disabled */ 0xf405eefd, 0x8ed00c0b, 0xc08fd080, -/* 0x018f: mmctx_multi_disabled */ +/* 0x019b: mmctx_multi_disabled */ 0xb70199f0, 0xc8010080, 0xb4b600ab, @@ -396,8 +334,8 @@ uint32_t nvc0_grhub_code[] = { 0xb601aec8, 0xbefd11e4, 0x008bd005, -/* 0x01a8: mmctx_exec_loop */ -/* 0x01a8: mmctx_wait_free */ +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ 0xf0008ecf, 0x0bf41fe4, 0x00ce98fa, @@ -406,76 +344,77 @@ uint32_t nvc0_grhub_code[] = { 0x04cdb804, 0xc8e81bf4, 0x1bf402ab, -/* 0x01c9: mmctx_fini_wait */ +/* 0x01d5: mmctx_fini_wait */ 0x008bcf18, 0xb01fb4f0, 0x1bf410b4, 0x02a7f0f7, 0xf4c921f4, -/* 0x01de: mmctx_stop */ +/* 0x01ea: mmctx_stop */ 0xabc81b0e, 0x10b4b600, 0xf00cb9f0, 0x8bd012b9, -/* 0x01ed: mmctx_stop_wait */ +/* 0x01f9: mmctx_stop_wait */ 0x008bcf00, 0xf412bbc8, -/* 0x01f6: mmctx_done */ - 0x87f1fa1b, - 0x84b6085c, - 0xf094bd06, - 0x89d00199, -/* 0x0207: strand_wait */ - 0xf900f800, - 0x02a7f0a0, - 0xfcc921f4, -/* 0x0213: strand_pre */ - 0xf100f8a0, - 0xf04afc87, - 0x97f00283, - 0x0089d00c, - 0x020721f5, -/* 0x0226: strand_post */ - 0x87f100f8, - 0x83f04afc, - 0x0d97f002, - 0xf50089d0, - 0xf8020721, -/* 0x0239: strand_set */ - 0xfca7f100, - 0x02a3f04f, - 0x0500aba2, - 0xd00fc7f0, - 0xc7f000ac, - 0x00bcd00b, - 0x020721f5, - 0xf000aed0, - 0xbcd00ac7, - 0x0721f500, -/* 0x0263: strand_ctx_init */ - 0xf100f802, - 0xb6083c87, - 0x94bd0684, - 0xd00399f0, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, 0x21f50089, - 0xe7f00213, - 0x3921f503, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, 0xfca7f102, 0x02a3f046, 0x0400aba0, 0xf040a0d0, 0xbcd001c7, - 0x0721f500, + 0x1521f500, 0x010c9202, 0xf000acd0, 0xbcd002c7, - 0x0721f500, - 0x2621f502, + 0x1521f500, + 0x3421f502, 0x8087f102, 0x0684b608, 0xb70089cf, 0x95220080, -/* 0x02ba: ctx_init_strand_loop */ +/* 0x02ca: ctx_init_strand_loop */ 0x8ed008fe, 0x408ed000, 0xb6808acf, @@ -484,457 +423,451 @@ uint32_t nvc0_grhub_code[] = { 0xb60480b6, 0x1bf40192, 0x08e4b6e8, - 0xf1f2efbc, - 0xb6085c87, - 0x94bd0684, - 0xd00399f0, - 0x00f80089, -/* 0x02ec: error */ - 0xe7f1e0f9, - 0xe4b60814, - 0x00efd006, - 0x0c1ce7f1, - 0xf006e4b6, - 0xefd001f7, - 0xf8e0fc00, -/* 0x0309: init */ - 0xfe04bd00, - 0x07fe0004, - 0x0017f100, - 0x0227f012, - 0xf10012d0, - 0xfe05ba17, - 0x17f10010, - 0x10d00400, - 0x0437f1c0, - 0x0634b604, - 0x200327f1, - 0xf10032d0, - 0xd0200427, - 0x27f10132, - 0x32d0200b, - 0x0c27f102, - 0x0732d020, - 0x0c2427f1, - 0xb90624b6, - 0x23d00003, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x031b: init */ + 0xbd00f804, + 0x0004fe04, + 0xf10007fe, + 0xf0120017, + 0x12d00227, + 0xb117f100, + 0x0010fe05, + 0x040017f1, + 0xf1c010d0, + 0xb6040437, + 0x27f10634, + 0x32d02003, 0x0427f100, - 0x0023f087, - 0xb70012d0, - 0xf0010012, - 0x12d00427, - 0x1031f400, - 0x9604e7f1, - 0xf440e3f0, - 0xf1c76821, - 0x01018090, - 0x801ff4f0, - 0x17f0000f, - 0x041fbb01, - 0xf10112b6, - 0xb6040c27, - 0x21d00624, - 0x4021d000, - 0x080027f1, - 0xcf0624b6, - 0xf7f10022, -/* 0x03aa: init_find_chipset */ - 0xf0b602f8, - 0x00f39808, - 0xf40432b8, - 0x34b00b0b, - 0xf11bf400, -/* 0x03be: init_context */ - 0x17f100f8, - 0xfe580100, - 0x03ff5802, - 0x8000e3f0, - 0x0f80140e, - 0x3d21f515, - 0x0037f101, - 0x0634b607, - 0xd0081495, - 0x34d00034, - 0x0030b740, - 0x001fbb13, - 0xd002f5b6, - 0x15b6003f, - 0x0110b608, - 0xb90814b6, - 0x21f5021f, - 0x1fbb0263, - 0x00039800, - 0x200047f1, -/* 0x040f: init_gpc */ - 0xa05043f0, - 0xb908044e, - 0x21f4021f, - 0x004ea08d, - 0x022fb908, - 0xa08d21f4, - 0xbd010c4e, - 0x8d21f4f4, - 0x01044ea0, - 0xa08d21f4, - 0xf001004e, - 0x21f402f7, - 0x004ea08d, -/* 0x0441: init_gpc_wait */ - 0x6821f408, - 0xf41fffc8, - 0x4ea0fa0b, - 0x21f40804, - 0x001fbb68, - 0x800040b7, - 0xf40132b6, - 0x27f1b41b, - 0x24b60800, - 0x4021d006, - 0x080020b7, - 0x19f014bd, - 0x0021d01f, -/* 0x0474: main */ + 0x0132d020, + 0x200b27f1, + 0xf10232d0, + 0xd0200c27, + 0x27f10732, + 0x24b60c24, + 0x0003b906, + 0xf10023d0, + 0xf0870427, + 0x12d00023, + 0x0012b700, + 0x0427f001, + 0xf40012d0, + 0xe7f11031, + 0xe3f09604, + 0x6821f440, + 0x8090f1c7, + 0xf4f00301, + 0x020f801f, + 0xbb0117f0, + 0x12b6041f, + 0x0c27f101, + 0x0624b604, + 0xd00021d0, + 0x17f14021, + 0x0e980100, + 0x010f9800, + 0x014721f5, + 0x070037f1, + 0x950634b6, + 0x34d00814, + 0x4034d000, + 0x130030b7, + 0xb6001fbb, + 0x3fd002f5, + 0x0815b600, + 0xb60110b6, + 0x1fb90814, + 0x7121f502, + 0x001fbb02, + 0xf1020398, + 0xf0200047, +/* 0x03f6: init_gpc */ + 0x4ea05043, + 0x1fb90804, + 0x8d21f402, + 0x010c4ea0, + 0x21f4f4bd, + 0x044ea08d, + 0x8d21f401, + 0x01004ea0, + 0xf402f7f0, + 0x4ea08d21, +/* 0x041e: init_gpc_wait */ + 0x21f40800, + 0x1fffc868, + 0xa0fa0bf4, + 0xf408044e, + 0x1fbb6821, + 0x0040b700, + 0x0132b680, + 0xf1be1bf4, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0458: main */ 0xf40031f4, 0xd7f00028, - 0x3921f408, + 0x3921f410, 0xb1f401f4, 0xf54001e4, - 0xf100d11b, - 0xb6083c87, - 0x94bd0684, - 0xd00499f0, - 0x17f10089, - 0x14b60b00, - 0x4012cf06, - 0xc80011cf, - 0x0bf41f13, - 0x1f23c87e, - 0xf95a0bf4, - 0x0212b920, - 0x083c87f1, - 0xbd0684b6, - 0x0799f094, - 0xf40089d0, - 0x31f40132, - 0x2a21f502, - 0x5c87f108, - 0x0684b608, - 0x99f094bd, - 0x0089d007, - 0x87f120fc, - 0x84b6083c, - 0xf094bd06, - 0x89d00699, - 0x0131f400, - 0x082a21f5, - 0x085c87f1, - 0xbd0684b6, - 0x0699f094, - 0xf40089d0, -/* 0x050a: chsw_prev_no_next */ - 0x20f9310e, - 0xf40212b9, - 0x32f40132, - 0x2a21f502, - 0xf120fc08, - 0xb60b0017, - 0x12d00614, - 0x130ef400, -/* 0x0528: chsw_no_prev */ + 0xbd00de1b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0b0017f1, + 0xcf0614b6, + 0x11cf4012, + 0x1f13c800, + 0x00870bf5, 0xf41f23c8, - 0x31f40d0b, + 0x20f9620b, + 0xbd0212b9, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50231, + 0x94bd082f, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xfc04bd00, + 0xf094bd20, + 0x07f10699, + 0x03f00f00, + 0x0009d002, + 0x31f404bd, + 0x2f21f501, + 0xf094bd08, + 0x07f10699, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x04f9: chsw_prev_no_next */ + 0xb920f931, + 0x32f40212, 0x0232f401, - 0x082a21f5, -/* 0x0538: chsw_done */ - 0x0b0c17f1, - 0xf00614b6, - 0x12d00127, - 0x5c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d004, - 0xff200ef5, -/* 0x0558: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0xb621f502, - 0x420ef407, -/* 0x0568: main_not_ctx_chan */ - 0xf402e4b0, - 0x87f12e1b, - 0x84b6083c, - 0xf094bd06, - 0x89d00799, - 0x0132f400, + 0x082f21f5, + 0x17f120fc, + 0x14b60b00, + 0x0012d006, +/* 0x0517: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, 0xf50232f4, - 0xf1082a21, - 0xb6085c87, - 0x94bd0684, - 0xd00799f0, - 0x0ef40089, -/* 0x0599: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf502ec21, -/* 0x05a7: main_done */ - 0xf1fed10e, - 0xb6082017, - 0x24bd0614, - 0xd01f29f0, - 0x0ef50012, -/* 0x05ba: ih */ - 0x80f9febe, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0x800acff0, - 0xf404abc4, - 0xb7f11d0b, - 0xd7f01900, - 0x40becf08, - 0xf400bfcf, - 0xb0b70421, - 0xe7f00400, - 0x00bed001, -/* 0x05f0: ih_no_fifo */ - 0x0100abe4, - 0xf00d0bf4, - 0xe7f108d7, - 0x21f44001, -/* 0x0601: ih_no_ctxsw */ - 0x04b7f104, - 0xffb0bd01, - 0x0bf4b4ab, - 0x1ca7f10d, - 0x06a4b60c, -/* 0x0617: ih_no_other */ - 0xd000abd0, - 0xf0fc400a, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0x0032f480, -/* 0x0632: ctx_4160s */ - 0xe7f101f8, - 0xe3f04160, - 0x01f7f040, -/* 0x063f: ctx_4160s_wait */ - 0xf48d21f4, - 0xffc86821, - 0xfa0bf404, -/* 0x064a: ctx_4160c */ - 0xe7f100f8, - 0xe3f04160, - 0xf4f4bd40, +/* 0x0527: chsw_done */ + 0xf1082f21, + 0xb60b0c17, + 0x27f00614, + 0x0012d001, + 0x99f094bd, + 0x0007f104, + 0x0203f017, + 0xbd0009d0, + 0x130ef504, +/* 0x0549: main_not_ctx_switch */ + 0x01e4b0ff, + 0xb90d1bf4, + 0x21f502f2, + 0x0ef407bb, +/* 0x0559: main_not_ctx_chan */ + 0x02e4b046, + 0xbd321bf4, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50232, + 0x94bd082f, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xf404bd00, +/* 0x058e: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x02fe21f5, + 0xfec00ef5, +/* 0x059c: main_done */ + 0x29f024bd, + 0x0007f11f, + 0x0203f008, + 0xbd0002d0, + 0xab0ef504, +/* 0x05b1: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x0acf04bd, + 0x04abc480, + 0xf11d0bf4, + 0xf01900b7, + 0xbecf10d7, + 0x00bfcf40, + 0xb70421f4, + 0xf00400b0, + 0xbed001e7, +/* 0x05e9: ih_no_fifo */ + 0x00abe400, + 0x0d0bf401, + 0xf110d7f0, + 0xf44001e7, +/* 0x05fa: ih_no_ctxsw */ + 0xb7f10421, + 0xb0bd0104, + 0xf4b4abff, + 0xa7f10d0b, + 0xa4b60c1c, + 0x00abd006, +/* 0x0610: ih_no_other */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x062b: ctx_4160s */ + 0xf101f800, + 0xf04160e7, + 0xf7f040e3, + 0x8d21f401, +/* 0x0638: ctx_4160s_wait */ + 0xc86821f4, + 0x0bf404ff, +/* 0x0643: ctx_4160c */ + 0xf100f8fa, + 0xf04160e7, + 0xf4bd40e3, + 0xf88d21f4, +/* 0x0651: ctx_4170s */ + 0x70e7f100, + 0x40e3f041, + 0xf410f5f0, 0x00f88d21, -/* 0x0658: ctx_4170s */ +/* 0x0660: ctx_4170w */ 0x4170e7f1, - 0xf040e3f0, - 0x21f410f5, -/* 0x0667: ctx_4170w */ - 0xf100f88d, - 0xf04170e7, - 0x21f440e3, - 0x10f4f068, - 0xf8f31bf4, -/* 0x0679: ctx_redswitch */ - 0x14e7f100, - 0x06e4b606, - 0x0270f7f1, - 0xf000efd0, -/* 0x068a: ctx_redswitch_delay */ - 0xf2b608f7, - 0xfd1bf401, - 0x0770f7f1, - 0xf800efd0, -/* 0x0699: ctx_86c */ - 0x6ce7f100, - 0x06e4b608, - 0xf100efd0, - 0xf08a14e7, - 0x21f440e3, - 0x6ce7f18d, - 0x41e3f0a8, - 0xf88d21f4, -/* 0x06b9: ctx_load */ - 0x3c87f100, - 0x0684b608, + 0xf440e3f0, + 0xf4f06821, + 0xf31bf410, +/* 0x0672: ctx_redswitch */ + 0xe7f100f8, + 0xe4b60614, + 0x70f7f106, + 0x00efd002, +/* 0x0683: ctx_redswitch_delay */ + 0xb608f7f0, + 0x1bf401f2, + 0x70f7f1fd, + 0x00efd007, +/* 0x0692: ctx_86c */ + 0xe7f100f8, + 0xe4b6086c, + 0x00efd006, + 0x8a14e7f1, + 0xf440e3f0, + 0xe7f18d21, + 0xe3f0a86c, + 0x8d21f441, +/* 0x06b2: ctx_load */ + 0x94bd00f8, + 0xf10599f0, + 0xf00f0007, + 0x09d00203, + 0xf004bd00, + 0x21f40ca7, + 0x2417f1c9, + 0x0614b60a, + 0xf10010d0, + 0xb60b0037, + 0x32d00634, + 0x0c17f140, + 0x0614b60a, + 0xd00747f0, + 0x14d00012, +/* 0x06ed: ctx_chan_wait_0 */ + 0x4014cf40, + 0xf41f44f0, + 0x32d0fa1b, + 0x000bfe00, + 0xb61f2af0, + 0x20b60424, + 0xf094bd02, + 0x07f10899, + 0x03f00f00, + 0x0009d002, + 0x17f104bd, + 0x14b60a04, + 0x0012d006, + 0x0a2017f1, + 0xf00614b6, + 0x23f10227, + 0x12d08000, + 0x1017f000, + 0x020027f1, + 0xfa0223f0, + 0x03f80512, 0x99f094bd, - 0x0089d005, - 0xf40ca7f0, - 0x17f1c921, - 0x14b60a24, - 0x0010d006, - 0x0b0037f1, - 0xd00634b6, - 0x17f14032, - 0x14b60a0c, - 0x0747f006, - 0xd00012d0, -/* 0x06f2: ctx_chan_wait_0 */ - 0x14cf4014, - 0x1f44f040, - 0xd0fa1bf4, - 0x0bfe0032, - 0x1f2af000, - 0xb60424b6, - 0x87f10220, - 0x84b6083c, - 0xf094bd06, - 0x89d00899, - 0x0417f100, + 0x0007f108, + 0x0203f017, + 0xbd0009d0, + 0x81019804, + 0x981814b6, + 0x25b68002, + 0x0512fd08, + 0xbd160180, + 0x0999f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0a0427f1, + 0xd00624b6, + 0x27f00021, + 0x2017f101, 0x0614b60a, 0xf10012d0, - 0xb60a2017, - 0x27f00614, - 0x0023f102, - 0x0012d080, - 0xf11017f0, - 0xf0020027, - 0x12fa0223, - 0xf103f805, - 0xb6085c87, - 0x94bd0684, - 0xd00899f0, - 0x01980089, - 0x1814b681, - 0xb6800298, - 0x12fd0825, - 0x16018005, - 0x083c87f1, - 0xbd0684b6, + 0xf0010017, + 0x01fa0613, + 0xbd03f805, 0x0999f094, - 0xf10089d0, - 0xb60a0427, - 0x21d00624, - 0x0127f000, - 0x0a2017f1, - 0xd00614b6, - 0x17f10012, - 0x13f00100, - 0x0501fa06, - 0x87f103f8, - 0x84b6085c, - 0xf094bd06, - 0x89d00999, - 0x5c87f100, - 0x0684b608, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, 0x99f094bd, - 0x0089d005, -/* 0x07b6: ctx_chan */ - 0x21f500f8, - 0x21f50632, - 0xa7f006b9, - 0xc921f40c, - 0x0a1017f1, - 0xf00614b6, - 0x12d00527, -/* 0x07d1: ctx_chan_wait */ - 0x0012cf00, - 0xf40522fd, - 0x21f5fa1b, - 0x00f8064a, -/* 0x07e0: ctx_mmio_exec */ - 0xf1410398, - 0xb60a0427, - 0x23d00624, -/* 0x07ef: ctx_mmio_loop */ - 0xc434bd00, - 0x1bf4ff34, - 0x0057f10f, - 0x0653f002, - 0xf80535fa, -/* 0x0801: ctx_mmio_pull */ - 0x804e9803, - 0xf4814f98, - 0x30b68d21, - 0x0112b608, -/* 0x0813: ctx_mmio_done */ - 0x98df1bf4, - 0x23d01603, - 0x40008000, - 0x010017f1, - 0xfa0613f0, - 0x03f80601, -/* 0x082a: ctx_xfer */ - 0xf7f100f8, - 0xf4b60c00, - 0x04e7f006, -/* 0x0837: ctx_xfer_idle */ - 0xcf80fed0, - 0xe4f100fe, - 0x1bf42000, - 0x0611f4f9, -/* 0x0847: ctx_xfer_pre */ - 0xf01102f4, - 0x21f510f7, - 0x21f50699, - 0x11f40632, -/* 0x0855: ctx_xfer_pre_load */ - 0x02f7f01c, - 0x065821f5, - 0x066721f5, - 0x067921f5, - 0x21f5f4bd, - 0x21f50658, -/* 0x086e: ctx_xfer_exec */ - 0x019806b9, - 0x1427f116, - 0x0624b604, - 0xf10020d0, - 0xf0a500e7, - 0x1fb941e3, - 0x8d21f402, - 0xf004e0b6, - 0x2cf001fc, - 0x0124b602, - 0xf405f2fd, - 0x17f18d21, - 0x13f04afc, - 0x0c27f002, - 0xf50012d0, - 0xf1020721, - 0xf047fc27, - 0x20d00223, - 0x012cf000, - 0xd00320b6, - 0xacf00012, - 0x06a5f001, - 0x9800b7f0, - 0x0d98140c, - 0x00e7f015, - 0x015c21f5, - 0xf508a7f0, - 0xf5010321, - 0xf4020721, - 0xa7f02201, - 0xc921f40c, - 0x0a1017f1, - 0xf00614b6, - 0x12d00527, -/* 0x08f5: ctx_xfer_post_save_wait */ - 0x0012cf00, - 0xf40522fd, - 0x02f4fa1b, -/* 0x0901: ctx_xfer_post */ - 0x02f7f032, - 0x065821f5, - 0x21f5f4bd, - 0x21f50699, - 0x21f50226, - 0xf4bd0667, - 0x065821f5, - 0x981011f4, - 0x11fd4001, - 0x070bf405, - 0x07e021f5, -/* 0x092c: ctx_xfer_no_post_mmio */ - 0x064a21f5, -/* 0x0930: ctx_xfer_done */ - 0x000000f8, - 0x00000000, + 0x0007f105, + 0x0203f017, + 0xbd0009d0, +/* 0x07bb: ctx_chan */ + 0xf500f804, + 0xf5062b21, + 0xf006b221, + 0x21f40ca7, + 0x1017f1c9, + 0x0614b60a, + 0xd00527f0, +/* 0x07d6: ctx_chan_wait */ + 0x12cf0012, + 0x0522fd00, + 0xf5fa1bf4, + 0xf8064321, +/* 0x07e5: ctx_mmio_exec */ + 0x41039800, + 0x0a0427f1, + 0xd00624b6, + 0x34bd0023, +/* 0x07f4: ctx_mmio_loop */ + 0xf4ff34c4, + 0x57f10f1b, + 0x53f00200, + 0x0535fa06, +/* 0x0806: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0xb68d21f4, + 0x12b60830, + 0xdf1bf401, +/* 0x0818: ctx_mmio_done */ + 0xd0160398, + 0x00800023, + 0x0017f140, + 0x0613f001, + 0xf80601fa, +/* 0x082f: ctx_xfer */ + 0xf100f803, + 0xb60c00f7, + 0xe7f006f4, + 0x80fed004, +/* 0x083c: ctx_xfer_idle */ + 0xf100fecf, + 0xf42000e4, + 0x11f4f91b, + 0x1102f406, +/* 0x084c: ctx_xfer_pre */ + 0xf510f7f0, + 0xf5069221, + 0xf4062b21, +/* 0x085a: ctx_xfer_pre_load */ + 0xf7f01c11, + 0x5121f502, + 0x6021f506, + 0x7221f506, + 0xf5f4bd06, + 0xf5065121, +/* 0x0873: ctx_xfer_exec */ + 0x9806b221, + 0x27f11601, + 0x24b60414, + 0x0020d006, + 0xa500e7f1, + 0xb941e3f0, + 0x21f4021f, + 0x04e0b68d, + 0xf001fcf0, + 0x24b6022c, + 0x05f2fd01, + 0xf18d21f4, + 0xf04afc17, + 0x27f00213, + 0x0012d00c, + 0x021521f5, + 0x47fc27f1, + 0xd00223f0, + 0x2cf00020, + 0x0320b601, + 0xf00012d0, + 0xa5f001ac, + 0x00b7f006, + 0x98000c98, + 0xe7f0010d, + 0x6621f500, + 0x08a7f001, + 0x010921f5, + 0x021521f5, + 0xf02201f4, + 0x21f40ca7, + 0x1017f1c9, + 0x0614b60a, + 0xd00527f0, +/* 0x08fa: ctx_xfer_post_save_wait */ + 0x12cf0012, + 0x0522fd00, + 0xf4fa1bf4, +/* 0x0906: ctx_xfer_post */ + 0xf7f03202, + 0x5121f502, + 0xf5f4bd06, + 0xf5069221, + 0xf5023421, + 0xbd066021, + 0x5121f5f4, + 0x1011f406, + 0xfd400198, + 0x0bf40511, + 0xe521f507, +/* 0x0931: ctx_xfer_no_post_mmio */ + 0x4321f507, +/* 0x0935: ctx_xfer_done */ + 0x0000f806, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc new file mode 100644 index 000000000000..afbe03ac9077 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#define CHIPSET GF117 +#include "macros.fuc" + +.section #nvd7_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nvd7_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h new file mode 100644 index 000000000000..a1b9f763996a --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h @@ -0,0 +1,921 @@ +uint32_t nvd7_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nvd7_grhub_code[] = { + 0x031b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f802fe, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0x0728b7f1, + 0xb906b4b6, + 0xc9f002ec, + 0x00bcd01f, +/* 0x0078: nv_rd32_wait */ + 0xc800bccf, + 0x1bf41fcc, + 0x06a7f0fa, + 0x010921f5, + 0xf840bfcf, +/* 0x008d: nv_wr32 */ + 0x28b7f100, + 0x06b4b607, + 0xb980bfd0, + 0xc9f002ec, + 0x1ec9f01f, +/* 0x00a3: nv_wr32_wait */ + 0xcf00bcd0, + 0xccc800bc, + 0xfa1bf41f, +/* 0x00ae: watchdog_reset */ + 0x87f100f8, + 0x84b60430, + 0x1ff9f006, + 0xf8008fd0, +/* 0x00bd: watchdog_clear */ + 0x3087f100, + 0x0684b604, + 0xf80080d0, +/* 0x00c9: wait_donez */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, + 0xf4888aff, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, + 0x84b60818, + 0x008ad006, +/* 0x0124: wait_doneo_e */ + 0x040087f1, + 0xcf0684b6, + 0x8aff0088, + 0xf30bf488, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, + 0xb6071087, + 0x94bd0684, + 0xf405bbfd, + 0x8bd0090b, + 0x0099f000, +/* 0x018c: mmctx_base_disabled */ + 0xf405eefd, + 0x8ed00c0b, + 0xc08fd080, +/* 0x019b: mmctx_multi_disabled */ + 0xb70199f0, + 0xc8010080, + 0xb4b600ab, + 0x0cb9f010, + 0xb601aec8, + 0xbefd11e4, + 0x008bd005, +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ + 0xf0008ecf, + 0x0bf41fe4, + 0x00ce98fa, + 0xd005e9fd, + 0xc0b6c08e, + 0x04cdb804, + 0xc8e81bf4, + 0x1bf402ab, +/* 0x01d5: mmctx_fini_wait */ + 0x008bcf18, + 0xb01fb4f0, + 0x1bf410b4, + 0x02a7f0f7, + 0xf4c921f4, +/* 0x01ea: mmctx_stop */ + 0xabc81b0e, + 0x10b4b600, + 0xf00cb9f0, + 0x8bd012b9, +/* 0x01f9: mmctx_stop_wait */ + 0x008bcf00, + 0xf412bbc8, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, + 0x21f50089, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, + 0xfca7f102, + 0x02a3f046, + 0x0400aba0, + 0xf040a0d0, + 0xbcd001c7, + 0x1521f500, + 0x010c9202, + 0xf000acd0, + 0xbcd002c7, + 0x1521f500, + 0x3421f502, + 0x8087f102, + 0x0684b608, + 0xb70089cf, + 0x95220080, +/* 0x02ca: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x031b: init */ + 0xbd00f804, + 0x0004fe04, + 0xf10007fe, + 0xf0120017, + 0x12d00227, + 0xb117f100, + 0x0010fe05, + 0x040017f1, + 0xf1c010d0, + 0xb6040437, + 0x27f10634, + 0x32d02003, + 0x0427f100, + 0x0132d020, + 0x200b27f1, + 0xf10232d0, + 0xd0200c27, + 0x27f10732, + 0x24b60c24, + 0x0003b906, + 0xf10023d0, + 0xf0870427, + 0x12d00023, + 0x0012b700, + 0x0427f001, + 0xf40012d0, + 0xe7f11031, + 0xe3f09604, + 0x6821f440, + 0x8090f1c7, + 0xf4f00301, + 0x020f801f, + 0xbb0117f0, + 0x12b6041f, + 0x0c27f101, + 0x0624b604, + 0xd00021d0, + 0x17f14021, + 0x0e980100, + 0x010f9800, + 0x014721f5, + 0x070037f1, + 0x950634b6, + 0x34d00814, + 0x4034d000, + 0x130030b7, + 0xb6001fbb, + 0x3fd002f5, + 0x0815b600, + 0xb60110b6, + 0x1fb90814, + 0x7121f502, + 0x001fbb02, + 0xf1020398, + 0xf0200047, +/* 0x03f6: init_gpc */ + 0x4ea05043, + 0x1fb90804, + 0x8d21f402, + 0x010c4ea0, + 0x21f4f4bd, + 0x044ea08d, + 0x8d21f401, + 0x01004ea0, + 0xf402f7f0, + 0x4ea08d21, +/* 0x041e: init_gpc_wait */ + 0x21f40800, + 0x1fffc868, + 0xa0fa0bf4, + 0xf408044e, + 0x1fbb6821, + 0x0040b700, + 0x0132b680, + 0xf1be1bf4, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0458: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00de1b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0b0017f1, + 0xcf0614b6, + 0x11cf4012, + 0x1f13c800, + 0x00870bf5, + 0xf41f23c8, + 0x20f9620b, + 0xbd0212b9, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50231, + 0x94bd082f, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xfc04bd00, + 0xf094bd20, + 0x07f10699, + 0x03f00f00, + 0x0009d002, + 0x31f404bd, + 0x2f21f501, + 0xf094bd08, + 0x07f10699, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x04f9: chsw_prev_no_next */ + 0xb920f931, + 0x32f40212, + 0x0232f401, + 0x082f21f5, + 0x17f120fc, + 0x14b60b00, + 0x0012d006, +/* 0x0517: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, + 0xf50232f4, +/* 0x0527: chsw_done */ + 0xf1082f21, + 0xb60b0c17, + 0x27f00614, + 0x0012d001, + 0x99f094bd, + 0x0007f104, + 0x0203f017, + 0xbd0009d0, + 0x130ef504, +/* 0x0549: main_not_ctx_switch */ + 0x01e4b0ff, + 0xb90d1bf4, + 0x21f502f2, + 0x0ef407bb, +/* 0x0559: main_not_ctx_chan */ + 0x02e4b046, + 0xbd321bf4, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50232, + 0x94bd082f, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xf404bd00, +/* 0x058e: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x02fe21f5, + 0xfec00ef5, +/* 0x059c: main_done */ + 0x29f024bd, + 0x0007f11f, + 0x0203f008, + 0xbd0002d0, + 0xab0ef504, +/* 0x05b1: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x0acf04bd, + 0x04abc480, + 0xf11d0bf4, + 0xf01900b7, + 0xbecf10d7, + 0x00bfcf40, + 0xb70421f4, + 0xf00400b0, + 0xbed001e7, +/* 0x05e9: ih_no_fifo */ + 0x00abe400, + 0x0d0bf401, + 0xf110d7f0, + 0xf44001e7, +/* 0x05fa: ih_no_ctxsw */ + 0xb7f10421, + 0xb0bd0104, + 0xf4b4abff, + 0xa7f10d0b, + 0xa4b60c1c, + 0x00abd006, +/* 0x0610: ih_no_other */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x062b: ctx_4160s */ + 0xf101f800, + 0xf04160e7, + 0xf7f040e3, + 0x8d21f401, +/* 0x0638: ctx_4160s_wait */ + 0xc86821f4, + 0x0bf404ff, +/* 0x0643: ctx_4160c */ + 0xf100f8fa, + 0xf04160e7, + 0xf4bd40e3, + 0xf88d21f4, +/* 0x0651: ctx_4170s */ + 0x70e7f100, + 0x40e3f041, + 0xf410f5f0, + 0x00f88d21, +/* 0x0660: ctx_4170w */ + 0x4170e7f1, + 0xf440e3f0, + 0xf4f06821, + 0xf31bf410, +/* 0x0672: ctx_redswitch */ + 0xe7f100f8, + 0xe4b60614, + 0x70f7f106, + 0x00efd002, +/* 0x0683: ctx_redswitch_delay */ + 0xb608f7f0, + 0x1bf401f2, + 0x70f7f1fd, + 0x00efd007, +/* 0x0692: ctx_86c */ + 0xe7f100f8, + 0xe4b6086c, + 0x00efd006, + 0x8a14e7f1, + 0xf440e3f0, + 0xe7f18d21, + 0xe3f0a86c, + 0x8d21f441, +/* 0x06b2: ctx_load */ + 0x94bd00f8, + 0xf10599f0, + 0xf00f0007, + 0x09d00203, + 0xf004bd00, + 0x21f40ca7, + 0x2417f1c9, + 0x0614b60a, + 0xf10010d0, + 0xb60b0037, + 0x32d00634, + 0x0c17f140, + 0x0614b60a, + 0xd00747f0, + 0x14d00012, +/* 0x06ed: ctx_chan_wait_0 */ + 0x4014cf40, + 0xf41f44f0, + 0x32d0fa1b, + 0x000bfe00, + 0xb61f2af0, + 0x20b60424, + 0xf094bd02, + 0x07f10899, + 0x03f00f00, + 0x0009d002, + 0x17f104bd, + 0x14b60a04, + 0x0012d006, + 0x0a2017f1, + 0xf00614b6, + 0x23f10227, + 0x12d08000, + 0x1017f000, + 0x020027f1, + 0xfa0223f0, + 0x03f80512, + 0x99f094bd, + 0x0007f108, + 0x0203f017, + 0xbd0009d0, + 0x81019804, + 0x981814b6, + 0x25b68002, + 0x0512fd08, + 0xbd160180, + 0x0999f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0a0427f1, + 0xd00624b6, + 0x27f00021, + 0x2017f101, + 0x0614b60a, + 0xf10012d0, + 0xf0010017, + 0x01fa0613, + 0xbd03f805, + 0x0999f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, + 0x99f094bd, + 0x0007f105, + 0x0203f017, + 0xbd0009d0, +/* 0x07bb: ctx_chan */ + 0xf500f804, + 0xf5062b21, + 0xf006b221, + 0x21f40ca7, + 0x1017f1c9, + 0x0614b60a, + 0xd00527f0, +/* 0x07d6: ctx_chan_wait */ + 0x12cf0012, + 0x0522fd00, + 0xf5fa1bf4, + 0xf8064321, +/* 0x07e5: ctx_mmio_exec */ + 0x41039800, + 0x0a0427f1, + 0xd00624b6, + 0x34bd0023, +/* 0x07f4: ctx_mmio_loop */ + 0xf4ff34c4, + 0x57f10f1b, + 0x53f00200, + 0x0535fa06, +/* 0x0806: ctx_mmio_pull */ + 0x4e9803f8, + 0x814f9880, + 0xb68d21f4, + 0x12b60830, + 0xdf1bf401, +/* 0x0818: ctx_mmio_done */ + 0xd0160398, + 0x00800023, + 0x0017f140, + 0x0613f001, + 0xf80601fa, +/* 0x082f: ctx_xfer */ + 0xf100f803, + 0xb60c00f7, + 0xe7f006f4, + 0x80fed004, +/* 0x083c: ctx_xfer_idle */ + 0xf100fecf, + 0xf42000e4, + 0x11f4f91b, + 0x1102f406, +/* 0x084c: ctx_xfer_pre */ + 0xf510f7f0, + 0xf5069221, + 0xf4062b21, +/* 0x085a: ctx_xfer_pre_load */ + 0xf7f01c11, + 0x5121f502, + 0x6021f506, + 0x7221f506, + 0xf5f4bd06, + 0xf5065121, +/* 0x0873: ctx_xfer_exec */ + 0x9806b221, + 0x27f11601, + 0x24b60414, + 0x0020d006, + 0xa500e7f1, + 0xb941e3f0, + 0x21f4021f, + 0x04e0b68d, + 0xf001fcf0, + 0x24b6022c, + 0x05f2fd01, + 0xf18d21f4, + 0xf04afc17, + 0x27f00213, + 0x0012d00c, + 0x021521f5, + 0x47fc27f1, + 0xd00223f0, + 0x2cf00020, + 0x0320b601, + 0xf00012d0, + 0xa5f001ac, + 0x00b7f006, + 0x98000c98, + 0xe7f0010d, + 0x6621f500, + 0x08a7f001, + 0x010921f5, + 0x021521f5, + 0xf02201f4, + 0x21f40ca7, + 0x1017f1c9, + 0x0614b60a, + 0xd00527f0, +/* 0x08fa: ctx_xfer_post_save_wait */ + 0x12cf0012, + 0x0522fd00, + 0xf4fa1bf4, +/* 0x0906: ctx_xfer_post */ + 0xf7f03202, + 0x5121f502, + 0xf5f4bd06, + 0xf5069221, + 0xf5023421, + 0xbd066021, + 0x5121f5f4, + 0x1011f406, + 0xfd400198, + 0x0bf40511, + 0xe521f507, +/* 0x0931: ctx_xfer_no_post_mmio */ + 0x4321f507, +/* 0x0935: ctx_xfer_done */ + 0x0000f806, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc index c7225db6486c..d4840f1879fd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc @@ -22,138 +22,13 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> */ -#define NVGK +#define CHIPSET GK100 #include "macros.fuc" .section #nve0_grhub_data #define INCLUDE_DATA #include "com.fuc" #include "hub.fuc" - -chipsets: -.b8 0xe4 0 0 0 -.b16 #nve4_hub_mmio_head -.b16 #nve4_hub_mmio_tail -.b8 0xe7 0 0 0 -.b16 #nve4_hub_mmio_head -.b16 #nve4_hub_mmio_tail -.b8 0xe6 0 0 0 -.b16 #nve4_hub_mmio_head -.b16 #nve4_hub_mmio_tail -.b8 0xf0 0 0 0 -.b16 #nvf0_hub_mmio_head -.b16 #nvf0_hub_mmio_tail -.b8 0 0 0 0 - -nve4_hub_mmio_head: -mmctx_data(0x17e91c, 2) -mmctx_data(0x400204, 2) -mmctx_data(0x404010, 7) -mmctx_data(0x4040a8, 9) -mmctx_data(0x4040d0, 7) -mmctx_data(0x4040f8, 1) -mmctx_data(0x404130, 3) -mmctx_data(0x404150, 3) -mmctx_data(0x404164, 1) -mmctx_data(0x4041a0, 4) -mmctx_data(0x404200, 4) -mmctx_data(0x404404, 14) -mmctx_data(0x404460, 4) -mmctx_data(0x404480, 1) -mmctx_data(0x404498, 1) -mmctx_data(0x404604, 4) -mmctx_data(0x404618, 4) -mmctx_data(0x40462c, 2) -mmctx_data(0x404640, 1) -mmctx_data(0x404654, 1) -mmctx_data(0x404660, 1) -mmctx_data(0x404678, 19) -mmctx_data(0x4046c8, 3) -mmctx_data(0x404700, 3) -mmctx_data(0x404718, 10) -mmctx_data(0x404744, 2) -mmctx_data(0x404754, 1) -mmctx_data(0x405800, 1) -mmctx_data(0x405830, 3) -mmctx_data(0x405854, 1) -mmctx_data(0x405870, 4) -mmctx_data(0x405a00, 2) -mmctx_data(0x405a18, 1) -mmctx_data(0x405b00, 1) -mmctx_data(0x405b10, 1) -mmctx_data(0x406020, 1) -mmctx_data(0x406028, 4) -mmctx_data(0x4064a8, 2) -mmctx_data(0x4064b4, 2) -mmctx_data(0x4064c0, 12) -mmctx_data(0x4064fc, 1) -mmctx_data(0x407040, 1) -mmctx_data(0x407804, 1) -mmctx_data(0x40780c, 6) -mmctx_data(0x4078bc, 1) -mmctx_data(0x408000, 7) -mmctx_data(0x408064, 1) -mmctx_data(0x408800, 3) -mmctx_data(0x408840, 1) -mmctx_data(0x408900, 3) -mmctx_data(0x408980, 1) -nve4_hub_mmio_tail: - -nvf0_hub_mmio_head: -mmctx_data(0x17e91c, 2) -mmctx_data(0x400204, 2) -mmctx_data(0x404004, 17) -mmctx_data(0x4040a8, 9) -mmctx_data(0x4040d0, 7) -mmctx_data(0x4040f8, 1) -mmctx_data(0x404100, 10) -mmctx_data(0x404130, 3) -mmctx_data(0x404150, 3) -mmctx_data(0x404164, 1) -mmctx_data(0x40417c, 2) -mmctx_data(0x4041a0, 4) -mmctx_data(0x404200, 4) -mmctx_data(0x404404, 12) -mmctx_data(0x404438, 1) -mmctx_data(0x404460, 4) -mmctx_data(0x404480, 1) -mmctx_data(0x404498, 1) -mmctx_data(0x404604, 4) -mmctx_data(0x404618, 4) -mmctx_data(0x40462c, 2) -mmctx_data(0x404640, 1) -mmctx_data(0x404654, 1) -mmctx_data(0x404660, 1) -mmctx_data(0x404678, 19) -mmctx_data(0x4046c8, 3) -mmctx_data(0x404700, 3) -mmctx_data(0x404718, 10) -mmctx_data(0x404744, 2) -mmctx_data(0x404754, 1) -mmctx_data(0x405800, 1) -mmctx_data(0x405830, 3) -mmctx_data(0x405854, 1) -mmctx_data(0x405870, 4) -mmctx_data(0x405a00, 2) -mmctx_data(0x405a18, 1) -mmctx_data(0x405b00, 1) -mmctx_data(0x405b10, 1) -mmctx_data(0x405b20, 1) -mmctx_data(0x406020, 1) -mmctx_data(0x406028, 4) -mmctx_data(0x4064a8, 5) -mmctx_data(0x4064c0, 12) -mmctx_data(0x4064fc, 1) -mmctx_data(0x407804, 1) -mmctx_data(0x40780c, 6) -mmctx_data(0x4078bc, 1) -mmctx_data(0x408000, 7) -mmctx_data(0x408064, 1) -mmctx_data(0x408800, 3) -mmctx_data(0x408840, 1) -mmctx_data(0x408900, 3) -mmctx_data(0x408980, 1) -nvf0_hub_mmio_tail: #undef INCLUDE_DATA .section #nve0_grhub_code diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h index 623e8698ace1..eb7bc0e9576e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h @@ -1,9 +1,13 @@ uint32_t nve0_grhub_data[] = { -/* 0x0000: gpc_count */ +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ 0x00000000, -/* 0x0004: rop_count */ +/* 0x000c: rop_count */ 0x00000000, -/* 0x0008: cmd_queue */ +/* 0x0010: cmd_queue */ 0x00000000, 0x00000000, 0x00000000, @@ -22,10 +26,6 @@ uint32_t nve0_grhub_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0050: hub_mmio_list_head */ - 0x00000000, -/* 0x0054: hub_mmio_list_tail */ - 0x00000000, /* 0x0058: ctx_current */ 0x00000000, 0x00000000, @@ -201,134 +201,19 @@ uint32_t nve0_grhub_data[] = { 0x00000000, 0x00000000, 0x00000000, -/* 0x0300: chipsets */ - 0x000000e4, - 0x03f00324, - 0x000000e7, - 0x03f00324, - 0x000000e6, - 0x03f00324, - 0x000000f0, - 0x04c403f0, - 0x00000000, -/* 0x0324: nve4_hub_mmio_head */ - 0x0417e91c, - 0x04400204, - 0x18404010, - 0x204040a8, - 0x184040d0, - 0x004040f8, - 0x08404130, - 0x08404150, - 0x00404164, - 0x0c4041a0, - 0x0c404200, - 0x34404404, - 0x0c404460, - 0x00404480, - 0x00404498, - 0x0c404604, - 0x0c404618, - 0x0440462c, - 0x00404640, - 0x00404654, - 0x00404660, - 0x48404678, - 0x084046c8, - 0x08404700, - 0x24404718, - 0x04404744, - 0x00404754, - 0x00405800, - 0x08405830, - 0x00405854, - 0x0c405870, - 0x04405a00, - 0x00405a18, - 0x00405b00, - 0x00405b10, - 0x00406020, - 0x0c406028, - 0x044064a8, - 0x044064b4, - 0x2c4064c0, - 0x004064fc, - 0x00407040, - 0x00407804, - 0x1440780c, - 0x004078bc, - 0x18408000, - 0x00408064, - 0x08408800, - 0x00408840, - 0x08408900, - 0x00408980, -/* 0x03f0: nve4_hub_mmio_tail */ -/* 0x03f0: nvf0_hub_mmio_head */ +/* 0x0300: hub_mmio_list_base */ 0x0417e91c, - 0x04400204, - 0x40404004, - 0x204040a8, - 0x184040d0, - 0x004040f8, - 0x24404100, - 0x08404130, - 0x08404150, - 0x00404164, - 0x0440417c, - 0x0c4041a0, - 0x0c404200, - 0x2c404404, - 0x00404438, - 0x0c404460, - 0x00404480, - 0x00404498, - 0x0c404604, - 0x0c404618, - 0x0440462c, - 0x00404640, - 0x00404654, - 0x00404660, - 0x48404678, - 0x084046c8, - 0x08404700, - 0x24404718, - 0x04404744, - 0x00404754, - 0x00405800, - 0x08405830, - 0x00405854, - 0x0c405870, - 0x04405a00, - 0x00405a18, - 0x00405b00, - 0x00405b10, - 0x00405b20, - 0x00406020, - 0x0c406028, - 0x104064a8, - 0x2c4064c0, - 0x004064fc, - 0x00407804, - 0x1440780c, - 0x004078bc, - 0x18408000, - 0x00408064, - 0x08408800, - 0x00408840, - 0x08408900, - 0x00408980, }; uint32_t nve0_grhub_code[] = { - 0x03090ef5, + 0x031b0ef5, /* 0x0004: queue_put */ 0x9800d898, 0x86f001d9, 0x0489b808, 0xf00c1bf4, 0x21f502f7, - 0x00f802ec, + 0x00f802fe, /* 0x001c: queue_put_next */ 0xb60798c4, 0x8dbb0384, @@ -360,7 +245,7 @@ uint32_t nve0_grhub_code[] = { 0xc800bccf, 0x1bf41fcc, 0x06a7f0fa, - 0x010321f5, + 0x010921f5, 0xf840bfcf, /* 0x008d: nv_wr32 */ 0x28b7f100, @@ -382,63 +267,66 @@ uint32_t nve0_grhub_code[] = { 0x0684b604, 0xf80080d0, /* 0x00c9: wait_donez */ - 0x3c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d000, - 0x081887f1, - 0xd00684b6, -/* 0x00e2: wait_donez_ne */ - 0x87f1008a, - 0x84b60400, - 0x0088cf06, + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, 0xf4888aff, - 0x87f1f31b, - 0x84b6085c, - 0xf094bd06, - 0x89d00099, -/* 0x0103: wait_doneo */ - 0xf100f800, - 0xb6083c87, - 0x94bd0684, - 0xd00099f0, - 0x87f10089, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f00f00, + 0x0009d002, + 0x87f104bd, 0x84b60818, 0x008ad006, -/* 0x011c: wait_doneo_e */ +/* 0x0124: wait_doneo_e */ 0x040087f1, 0xcf0684b6, 0x8aff0088, 0xf30bf488, - 0x085c87f1, - 0xbd0684b6, - 0x0099f094, - 0xf80089d0, -/* 0x013d: mmctx_size */ -/* 0x013f: nv_mmctx_size_loop */ - 0x9894bd00, - 0x85b600e8, - 0x0180b61a, - 0xbb0284b6, - 0xe0b60098, - 0x04efb804, - 0xb9eb1bf4, - 0x00f8029f, -/* 0x015c: mmctx_xfer */ - 0x083c87f1, - 0xbd0684b6, - 0x0199f094, - 0xf10089d0, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf00f0007, + 0x09d00203, + 0xf104bd00, 0xb6071087, 0x94bd0684, 0xf405bbfd, 0x8bd0090b, 0x0099f000, -/* 0x0180: mmctx_base_disabled */ +/* 0x018c: mmctx_base_disabled */ 0xf405eefd, 0x8ed00c0b, 0xc08fd080, -/* 0x018f: mmctx_multi_disabled */ +/* 0x019b: mmctx_multi_disabled */ 0xb70199f0, 0xc8010080, 0xb4b600ab, @@ -446,8 +334,8 @@ uint32_t nve0_grhub_code[] = { 0xb601aec8, 0xbefd11e4, 0x008bd005, -/* 0x01a8: mmctx_exec_loop */ -/* 0x01a8: mmctx_wait_free */ +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ 0xf0008ecf, 0x0bf41fe4, 0x00ce98fa, @@ -456,76 +344,77 @@ uint32_t nve0_grhub_code[] = { 0x04cdb804, 0xc8e81bf4, 0x1bf402ab, -/* 0x01c9: mmctx_fini_wait */ +/* 0x01d5: mmctx_fini_wait */ 0x008bcf18, 0xb01fb4f0, 0x1bf410b4, 0x02a7f0f7, 0xf4c921f4, -/* 0x01de: mmctx_stop */ +/* 0x01ea: mmctx_stop */ 0xabc81b0e, 0x10b4b600, 0xf00cb9f0, 0x8bd012b9, -/* 0x01ed: mmctx_stop_wait */ +/* 0x01f9: mmctx_stop_wait */ 0x008bcf00, 0xf412bbc8, -/* 0x01f6: mmctx_done */ - 0x87f1fa1b, - 0x84b6085c, - 0xf094bd06, - 0x89d00199, -/* 0x0207: strand_wait */ - 0xf900f800, - 0x02a7f0a0, - 0xfcc921f4, -/* 0x0213: strand_pre */ - 0xf100f8a0, - 0xf04afc87, - 0x97f00283, - 0x0089d00c, - 0x020721f5, -/* 0x0226: strand_post */ - 0x87f100f8, - 0x83f04afc, - 0x0d97f002, - 0xf50089d0, - 0xf8020721, -/* 0x0239: strand_set */ - 0xfca7f100, - 0x02a3f04f, - 0x0500aba2, - 0xd00fc7f0, - 0xc7f000ac, - 0x00bcd00b, - 0x020721f5, - 0xf000aed0, - 0xbcd00ac7, - 0x0721f500, -/* 0x0263: strand_ctx_init */ - 0xf100f802, - 0xb6083c87, - 0x94bd0684, - 0xd00399f0, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, 0x21f50089, - 0xe7f00213, - 0x3921f503, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f00f00, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, 0xfca7f102, 0x02a3f046, 0x0400aba0, 0xf040a0d0, 0xbcd001c7, - 0x0721f500, + 0x1521f500, 0x010c9202, 0xf000acd0, 0xbcd002c7, - 0x0721f500, - 0x2621f502, + 0x1521f500, + 0x3421f502, 0x8087f102, 0x0684b608, 0xb70089cf, 0x95220080, -/* 0x02ba: ctx_init_strand_loop */ +/* 0x02ca: ctx_init_strand_loop */ 0x8ed008fe, 0x408ed000, 0xb6808acf, @@ -534,438 +423,496 @@ uint32_t nve0_grhub_code[] = { 0xb60480b6, 0x1bf40192, 0x08e4b6e8, - 0xf1f2efbc, - 0xb6085c87, - 0x94bd0684, - 0xd00399f0, - 0x00f80089, -/* 0x02ec: error */ - 0xe7f1e0f9, - 0xe4b60814, - 0x00efd006, - 0x0c1ce7f1, - 0xf006e4b6, - 0xefd001f7, - 0xf8e0fc00, -/* 0x0309: init */ - 0xfe04bd00, - 0x07fe0004, - 0x0017f100, - 0x0227f012, - 0xf10012d0, - 0xfe05ba17, - 0x17f10010, - 0x10d00400, - 0x0437f1c0, - 0x0634b604, - 0x200327f1, - 0xf10032d0, - 0xd0200427, - 0x27f10132, - 0x32d0200b, - 0x0c27f102, - 0x0732d020, - 0x0c2427f1, - 0xb90624b6, - 0x23d00003, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x031b: init */ + 0xbd00f804, + 0x0004fe04, + 0xf10007fe, + 0xf0120017, + 0x12d00227, + 0xb117f100, + 0x0010fe05, + 0x040017f1, + 0xf1c010d0, + 0xb6040437, + 0x27f10634, + 0x32d02003, 0x0427f100, - 0x0023f087, - 0xb70012d0, - 0xf0010012, - 0x12d00427, - 0x1031f400, - 0x9604e7f1, - 0xf440e3f0, - 0xf1c76821, - 0x01018090, - 0x801ff4f0, - 0x17f0000f, - 0x041fbb01, - 0xf10112b6, - 0xb6040c27, - 0x21d00624, - 0x4021d000, - 0x080027f1, - 0xcf0624b6, - 0xf7f10022, -/* 0x03aa: init_find_chipset */ - 0xf0b602f8, - 0x00f39808, - 0xf40432b8, - 0x34b00b0b, - 0xf11bf400, -/* 0x03be: init_context */ - 0x17f100f8, - 0xfe580100, - 0x03ff5802, - 0x8000e3f0, - 0x0f80140e, - 0x3d21f515, - 0x0037f101, - 0x0634b607, - 0xd0081495, - 0x34d00034, - 0x0030b740, - 0x001fbb13, - 0xd002f5b6, - 0x15b6003f, - 0x0110b608, - 0xb90814b6, - 0x21f5021f, - 0x1fbb0263, - 0x00039800, - 0x200047f1, -/* 0x040f: init_gpc */ - 0xa05043f0, - 0xb908044e, - 0x21f4021f, - 0x004ea08d, - 0x022fb908, - 0xa08d21f4, - 0xbd010c4e, - 0x8d21f4f4, - 0x01044ea0, - 0xa08d21f4, - 0xf001004e, - 0x21f402f7, - 0x004ea08d, -/* 0x0441: init_gpc_wait */ - 0x6821f408, - 0xf41fffc8, - 0x4ea0fa0b, - 0x21f40804, - 0x001fbb68, - 0x800040b7, - 0xf40132b6, - 0x27f1b41b, - 0x24b60800, - 0x4021d006, - 0x080020b7, - 0x19f014bd, - 0x0021d01f, -/* 0x0474: main */ + 0x0132d020, + 0x200b27f1, + 0xf10232d0, + 0xd0200c27, + 0x27f10732, + 0x24b60c24, + 0x0003b906, + 0xf10023d0, + 0xf0870427, + 0x12d00023, + 0x0012b700, + 0x0427f001, + 0xf40012d0, + 0xe7f11031, + 0xe3f09604, + 0x6821f440, + 0x8090f1c7, + 0xf4f00301, + 0x020f801f, + 0xbb0117f0, + 0x12b6041f, + 0x0c27f101, + 0x0624b604, + 0xd00021d0, + 0x17f14021, + 0x0e980100, + 0x010f9800, + 0x014721f5, + 0x070037f1, + 0x950634b6, + 0x34d00814, + 0x4034d000, + 0x130030b7, + 0xb6001fbb, + 0x3fd002f5, + 0x0815b600, + 0xb60110b6, + 0x1fb90814, + 0x7121f502, + 0x001fbb02, + 0xf1020398, + 0xf0200047, +/* 0x03f6: init_gpc */ + 0x4ea05043, + 0x1fb90804, + 0x8d21f402, + 0x010c4ea0, + 0x21f4f4bd, + 0x044ea08d, + 0x8d21f401, + 0x01004ea0, + 0xf402f7f0, + 0x4ea08d21, +/* 0x041e: init_gpc_wait */ + 0x21f40800, + 0x1fffc868, + 0xa0fa0bf4, + 0xf408044e, + 0x1fbb6821, + 0x0040b700, + 0x0132b680, + 0xf1be1bf4, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x080007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0458: main */ 0xf40031f4, 0xd7f00028, - 0x3921f408, + 0x3921f410, 0xb1f401f4, 0xf54001e4, - 0xf100d11b, - 0xb6083c87, - 0x94bd0684, - 0xd00499f0, - 0x17f10089, - 0x14b60b00, - 0x4012cf06, - 0xc80011cf, - 0x0bf41f13, - 0x1f23c87e, - 0xf95a0bf4, - 0x0212b920, - 0x083c87f1, - 0xbd0684b6, - 0x0799f094, - 0xf40089d0, - 0x31f40132, - 0xfc21f502, - 0x5c87f107, - 0x0684b608, - 0x99f094bd, - 0x0089d007, - 0x87f120fc, - 0x84b6083c, - 0xf094bd06, - 0x89d00699, - 0x0131f400, - 0x07fc21f5, - 0x085c87f1, - 0xbd0684b6, - 0x0699f094, - 0xf40089d0, -/* 0x050a: chsw_prev_no_next */ - 0x20f9310e, - 0xf40212b9, - 0x32f40132, - 0xfc21f502, - 0xf120fc07, - 0xb60b0017, - 0x12d00614, - 0x130ef400, -/* 0x0528: chsw_no_prev */ + 0xbd00de1b, + 0x0499f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0b0017f1, + 0xcf0614b6, + 0x11cf4012, + 0x1f13c800, + 0x00870bf5, 0xf41f23c8, - 0x31f40d0b, + 0x20f9620b, + 0xbd0212b9, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50231, + 0x94bd0801, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xfc04bd00, + 0xf094bd20, + 0x07f10699, + 0x03f00f00, + 0x0009d002, + 0x31f404bd, + 0x0121f501, + 0xf094bd08, + 0x07f10699, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x04f9: chsw_prev_no_next */ + 0xb920f931, + 0x32f40212, 0x0232f401, - 0x07fc21f5, -/* 0x0538: chsw_done */ - 0x0b0c17f1, - 0xf00614b6, - 0x12d00127, - 0x5c87f100, - 0x0684b608, - 0x99f094bd, - 0x0089d004, - 0xff200ef5, -/* 0x0558: main_not_ctx_switch */ - 0xf401e4b0, - 0xf2b90d1b, - 0x9021f502, - 0x420ef407, -/* 0x0568: main_not_ctx_chan */ - 0xf402e4b0, - 0x87f12e1b, - 0x84b6083c, - 0xf094bd06, - 0x89d00799, - 0x0132f400, + 0x080121f5, + 0x17f120fc, + 0x14b60b00, + 0x0012d006, +/* 0x0517: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, 0xf50232f4, - 0xf107fc21, - 0xb6085c87, - 0x94bd0684, - 0xd00799f0, - 0x0ef40089, -/* 0x0599: main_not_ctx_save */ - 0x10ef9411, - 0xf501f5f0, - 0xf502ec21, -/* 0x05a7: main_done */ - 0xf1fed10e, - 0xb6082017, - 0x24bd0614, - 0xd01f29f0, - 0x0ef50012, -/* 0x05ba: ih */ - 0x80f9febe, - 0xf90188fe, - 0xf990f980, - 0xf9b0f9a0, - 0xf9e0f9d0, - 0x800acff0, - 0xf404abc4, - 0xb7f11d0b, - 0xd7f01900, - 0x40becf08, - 0xf400bfcf, - 0xb0b70421, - 0xe7f00400, - 0x00bed001, -/* 0x05f0: ih_no_fifo */ - 0x0100abe4, - 0xf00d0bf4, - 0xe7f108d7, - 0x21f44001, -/* 0x0601: ih_no_ctxsw */ - 0x04b7f104, - 0xffb0bd01, - 0x0bf4b4ab, - 0x1ca7f10d, - 0x06a4b60c, -/* 0x0617: ih_no_other */ - 0xd000abd0, - 0xf0fc400a, - 0xd0fce0fc, - 0xa0fcb0fc, - 0x80fc90fc, - 0xfc0088fe, - 0x0032f480, -/* 0x0632: ctx_4170s */ - 0xe7f101f8, +/* 0x0527: chsw_done */ + 0xf1080121, + 0xb60b0c17, + 0x27f00614, + 0x0012d001, + 0x99f094bd, + 0x0007f104, + 0x0203f017, + 0xbd0009d0, + 0x130ef504, +/* 0x0549: main_not_ctx_switch */ + 0x01e4b0ff, + 0xb90d1bf4, + 0x21f502f2, + 0x0ef40795, +/* 0x0559: main_not_ctx_chan */ + 0x02e4b046, + 0xbd321bf4, + 0x0799f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50232, + 0x94bd0801, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xf404bd00, +/* 0x058e: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x02fe21f5, + 0xfec00ef5, +/* 0x059c: main_done */ + 0x29f024bd, + 0x0007f11f, + 0x0203f008, + 0xbd0002d0, + 0xab0ef504, +/* 0x05b1: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x0acf04bd, + 0x04abc480, + 0xf11d0bf4, + 0xf01900b7, + 0xbecf10d7, + 0x00bfcf40, + 0xb70421f4, + 0xf00400b0, + 0xbed001e7, +/* 0x05e9: ih_no_fifo */ + 0x00abe400, + 0x0d0bf401, + 0xf110d7f0, + 0xf44001e7, +/* 0x05fa: ih_no_ctxsw */ + 0xb7f10421, + 0xb0bd0104, + 0xf4b4abff, + 0xa7f10d0b, + 0xa4b60c1c, + 0x00abd006, +/* 0x0610: ih_no_other */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x062b: ctx_4170s */ + 0xf101f800, + 0xf04170e7, + 0xf5f040e3, + 0x8d21f410, +/* 0x063a: ctx_4170w */ + 0xe7f100f8, 0xe3f04170, - 0x10f5f040, - 0xf88d21f4, -/* 0x0641: ctx_4170w */ - 0x70e7f100, - 0x40e3f041, - 0xf06821f4, - 0x1bf410f4, -/* 0x0653: ctx_redswitch */ - 0xf100f8f3, - 0xb60614e7, - 0xf7f106e4, - 0xefd00270, - 0x08f7f000, -/* 0x0664: ctx_redswitch_delay */ - 0xf401f2b6, - 0xf7f1fd1b, - 0xefd00770, -/* 0x0673: ctx_86c */ - 0xf100f800, - 0xb6086ce7, - 0xefd006e4, - 0x14e7f100, - 0x40e3f08a, - 0xf18d21f4, - 0xf0a86ce7, - 0x21f441e3, -/* 0x0693: ctx_load */ - 0xf100f88d, - 0xb6083c87, - 0x94bd0684, - 0xd00599f0, - 0xa7f00089, - 0xc921f40c, - 0x0a2417f1, - 0xd00614b6, - 0x37f10010, - 0x34b60b00, - 0x4032d006, - 0x0a0c17f1, - 0xf00614b6, - 0x12d00747, - 0x4014d000, -/* 0x06cc: ctx_chan_wait_0 */ - 0xf04014cf, - 0x1bf41f44, - 0x0032d0fa, - 0xf0000bfe, - 0x24b61f2a, - 0x0220b604, - 0x083c87f1, - 0xbd0684b6, - 0x0899f094, - 0xf10089d0, - 0xb60a0417, - 0x12d00614, - 0x2017f100, - 0x0614b60a, - 0xf10227f0, - 0xd0800023, - 0x17f00012, - 0x0027f110, - 0x0223f002, - 0xf80512fa, - 0x5c87f103, - 0x0684b608, + 0x6821f440, + 0xf410f4f0, + 0x00f8f31b, +/* 0x064c: ctx_redswitch */ + 0x0614e7f1, + 0xf106e4b6, + 0xd00270f7, + 0xf7f000ef, +/* 0x065d: ctx_redswitch_delay */ + 0x01f2b608, + 0xf1fd1bf4, + 0xd00770f7, + 0x00f800ef, +/* 0x066c: ctx_86c */ + 0x086ce7f1, + 0xd006e4b6, + 0xe7f100ef, + 0xe3f08a14, + 0x8d21f440, + 0xa86ce7f1, + 0xf441e3f0, + 0x00f88d21, +/* 0x068c: ctx_load */ 0x99f094bd, - 0x0089d008, - 0xb6810198, - 0x02981814, - 0x0825b680, - 0x800512fd, - 0x87f11601, - 0x84b6083c, - 0xf094bd06, - 0x89d00999, - 0x0427f100, - 0x0624b60a, - 0xf00021d0, - 0x17f10127, + 0x0007f105, + 0x0203f00f, + 0xbd0009d0, + 0x0ca7f004, + 0xf1c921f4, + 0xb60a2417, + 0x10d00614, + 0x0037f100, + 0x0634b60b, + 0xf14032d0, + 0xb60a0c17, + 0x47f00614, + 0x0012d007, +/* 0x06c7: ctx_chan_wait_0 */ + 0xcf4014d0, + 0x44f04014, + 0xfa1bf41f, + 0xfe0032d0, + 0x2af0000b, + 0x0424b61f, + 0xbd0220b6, + 0x0899f094, + 0x0f0007f1, + 0xd00203f0, + 0x04bd0009, + 0x0a0417f1, + 0xd00614b6, + 0x17f10012, 0x14b60a20, - 0x0012d006, - 0x010017f1, - 0xfa0613f0, - 0x03f80501, - 0x085c87f1, - 0xbd0684b6, - 0x0999f094, - 0xf10089d0, - 0xb6085c87, - 0x94bd0684, - 0xd00599f0, - 0x00f80089, -/* 0x0790: ctx_chan */ - 0x069321f5, - 0xf40ca7f0, - 0x17f1c921, - 0x14b60a10, - 0x0527f006, -/* 0x07a7: ctx_chan_wait */ - 0xcf0012d0, - 0x22fd0012, - 0xfa1bf405, -/* 0x07b2: ctx_mmio_exec */ - 0x039800f8, - 0x0427f141, - 0x0624b60a, - 0xbd0023d0, -/* 0x07c1: ctx_mmio_loop */ - 0xff34c434, - 0xf10f1bf4, - 0xf0020057, - 0x35fa0653, -/* 0x07d3: ctx_mmio_pull */ - 0x9803f805, - 0x4f98804e, - 0x8d21f481, - 0xb60830b6, - 0x1bf40112, -/* 0x07e5: ctx_mmio_done */ - 0x160398df, - 0x800023d0, - 0x17f14000, - 0x13f00100, - 0x0601fa06, - 0x00f803f8, -/* 0x07fc: ctx_xfer */ - 0x0c00f7f1, - 0xf006f4b6, - 0xfed004e7, -/* 0x0809: ctx_xfer_idle */ - 0x00fecf80, - 0x2000e4f1, - 0xf4f91bf4, - 0x02f40611, -/* 0x0819: ctx_xfer_pre */ - 0x10f7f00d, - 0x067321f5, -/* 0x0823: ctx_xfer_pre_load */ - 0xf01c11f4, - 0x21f502f7, - 0x21f50632, - 0x21f50641, - 0xf4bd0653, - 0x063221f5, - 0x069321f5, -/* 0x083c: ctx_xfer_exec */ - 0xf1160198, - 0xb6041427, - 0x20d00624, - 0x00e7f100, - 0x41e3f0a5, - 0xf4021fb9, - 0xe0b68d21, - 0x01fcf004, - 0xb6022cf0, - 0xf2fd0124, - 0x8d21f405, - 0x4afc17f1, - 0xf00213f0, - 0x12d00c27, - 0x0721f500, - 0xfc27f102, - 0x0223f047, - 0xf00020d0, - 0x20b6012c, - 0x0012d003, - 0xf001acf0, - 0xb7f006a5, - 0x140c9800, - 0xf0150d98, - 0x21f500e7, - 0xa7f0015c, - 0x0321f508, - 0x0721f501, - 0x2201f402, - 0xf40ca7f0, - 0x17f1c921, - 0x14b60a10, - 0x0527f006, -/* 0x08c3: ctx_xfer_post_save_wait */ - 0xcf0012d0, - 0x22fd0012, - 0xfa1bf405, -/* 0x08cf: ctx_xfer_post */ - 0xf02e02f4, - 0x21f502f7, - 0xf4bd0632, - 0x067321f5, - 0x022621f5, - 0x064121f5, - 0x21f5f4bd, - 0x11f40632, - 0x40019810, - 0xf40511fd, - 0x21f5070b, -/* 0x08fa: ctx_xfer_no_post_mmio */ -/* 0x08fa: ctx_xfer_done */ - 0x00f807b2, + 0x0227f006, + 0x800023f1, + 0xf00012d0, + 0x27f11017, + 0x23f00200, + 0x0512fa02, + 0x94bd03f8, + 0xf10899f0, + 0xf0170007, + 0x09d00203, + 0x9804bd00, + 0x14b68101, + 0x80029818, + 0xfd0825b6, + 0x01800512, + 0xf094bd16, + 0x07f10999, + 0x03f00f00, + 0x0009d002, + 0x27f104bd, + 0x24b60a04, + 0x0021d006, + 0xf10127f0, + 0xb60a2017, + 0x12d00614, + 0x0017f100, + 0x0613f001, + 0xf80501fa, + 0xf094bd03, + 0x07f10999, + 0x03f01700, + 0x0009d002, + 0x94bd04bd, + 0xf10599f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0795: ctx_chan */ + 0x8c21f500, + 0x0ca7f006, + 0xf1c921f4, + 0xb60a1017, + 0x27f00614, + 0x0012d005, +/* 0x07ac: ctx_chan_wait */ + 0xfd0012cf, + 0x1bf40522, +/* 0x07b7: ctx_mmio_exec */ + 0x9800f8fa, + 0x27f14103, + 0x24b60a04, + 0x0023d006, +/* 0x07c6: ctx_mmio_loop */ + 0x34c434bd, + 0x0f1bf4ff, + 0x020057f1, + 0xfa0653f0, + 0x03f80535, +/* 0x07d8: ctx_mmio_pull */ + 0x98804e98, + 0x21f4814f, + 0x0830b68d, + 0xf40112b6, +/* 0x07ea: ctx_mmio_done */ + 0x0398df1b, + 0x0023d016, + 0xf1400080, + 0xf0010017, + 0x01fa0613, + 0xf803f806, +/* 0x0801: ctx_xfer */ + 0x00f7f100, + 0x06f4b60c, + 0xd004e7f0, +/* 0x080e: ctx_xfer_idle */ + 0xfecf80fe, + 0x00e4f100, + 0xf91bf420, + 0xf40611f4, +/* 0x081e: ctx_xfer_pre */ + 0xf7f00d02, + 0x6c21f510, + 0x1c11f406, +/* 0x0828: ctx_xfer_pre_load */ + 0xf502f7f0, + 0xf5062b21, + 0xf5063a21, + 0xbd064c21, + 0x2b21f5f4, + 0x8c21f506, +/* 0x0841: ctx_xfer_exec */ + 0x16019806, + 0x041427f1, + 0xd00624b6, + 0xe7f10020, + 0xe3f0a500, + 0x021fb941, + 0xb68d21f4, + 0xfcf004e0, + 0x022cf001, + 0xfd0124b6, + 0x21f405f2, + 0xfc17f18d, + 0x0213f04a, + 0xd00c27f0, + 0x21f50012, + 0x27f10215, + 0x23f047fc, + 0x0020d002, + 0xb6012cf0, + 0x12d00320, + 0x01acf000, + 0xf006a5f0, + 0x0c9800b7, + 0x010d9800, + 0xf500e7f0, + 0xf0016621, + 0x21f508a7, + 0x21f50109, + 0x01f40215, + 0x0ca7f022, + 0xf1c921f4, + 0xb60a1017, + 0x27f00614, + 0x0012d005, +/* 0x08c8: ctx_xfer_post_save_wait */ + 0xfd0012cf, + 0x1bf40522, + 0x2e02f4fa, +/* 0x08d4: ctx_xfer_post */ + 0xf502f7f0, + 0xbd062b21, + 0x6c21f5f4, + 0x3421f506, + 0x3a21f502, + 0xf5f4bd06, + 0xf4062b21, + 0x01981011, + 0x0511fd40, + 0xf5070bf4, +/* 0x08ff: ctx_xfer_no_post_mmio */ +/* 0x08ff: ctx_xfer_done */ + 0xf807b721, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, 0x00000000, }; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc new file mode 100644 index 000000000000..ec42ed29b50d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc @@ -0,0 +1,40 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#define CHIPSET GK110 +#include "macros.fuc" + +.section #nvf0_grhub_data +#define INCLUDE_DATA +#include "com.fuc" +#include "hub.fuc" +#undef INCLUDE_DATA + +.section #nvf0_grhub_code +#define INCLUDE_CODE +bra #init +#include "com.fuc" +#include "hub.fuc" +.align 256 +#undef INCLUDE_CODE diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h new file mode 100644 index 000000000000..438506d14749 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h @@ -0,0 +1,918 @@ +uint32_t nvf0_grhub_data[] = { +/* 0x0000: hub_mmio_list_head */ + 0x00000300, +/* 0x0004: hub_mmio_list_tail */ + 0x00000304, +/* 0x0008: gpc_count */ + 0x00000000, +/* 0x000c: rop_count */ + 0x00000000, +/* 0x0010: cmd_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: ctx_current */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0100: chan_data */ +/* 0x0100: chan_mmio_count */ + 0x00000000, +/* 0x0104: chan_mmio_address */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0200: xfer_data */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0300: hub_mmio_list_base */ + 0x0417e91c, +}; + +uint32_t nvf0_grhub_code[] = { + 0x031b0ef5, +/* 0x0004: queue_put */ + 0x9800d898, + 0x86f001d9, + 0x0489b808, + 0xf00c1bf4, + 0x21f502f7, + 0x00f802fe, +/* 0x001c: queue_put_next */ + 0xb60798c4, + 0x8dbb0384, + 0x0880b600, + 0x80008e80, + 0x90b6018f, + 0x0f94f001, + 0xf801d980, +/* 0x0039: queue_get */ + 0x0131f400, + 0x9800d898, + 0x89b801d9, + 0x210bf404, + 0xb60789c4, + 0x9dbb0394, + 0x0890b600, + 0x98009e98, + 0x80b6019f, + 0x0f84f001, + 0xf400d880, +/* 0x0066: queue_get_done */ + 0x00f80132, +/* 0x0068: nv_rd32 */ + 0x0728b7f1, + 0xb906b4b6, + 0xc9f002ec, + 0x00bcd01f, +/* 0x0078: nv_rd32_wait */ + 0xc800bccf, + 0x1bf41fcc, + 0x06a7f0fa, + 0x010921f5, + 0xf840bfcf, +/* 0x008d: nv_wr32 */ + 0x28b7f100, + 0x06b4b607, + 0xb980bfd0, + 0xc9f002ec, + 0x1ec9f01f, +/* 0x00a3: nv_wr32_wait */ + 0xcf00bcd0, + 0xccc800bc, + 0xfa1bf41f, +/* 0x00ae: watchdog_reset */ + 0x87f100f8, + 0x84b60430, + 0x1ff9f006, + 0xf8008fd0, +/* 0x00bd: watchdog_clear */ + 0x3087f100, + 0x0684b604, + 0xf80080d0, +/* 0x00c9: wait_donez */ + 0xf094bd00, + 0x07f10099, + 0x03f03700, + 0x0009d002, + 0x07f104bd, + 0x03f00600, + 0x000ad002, +/* 0x00e6: wait_donez_ne */ + 0x87f104bd, + 0x83f00000, + 0x0088cf01, + 0xf4888aff, + 0x94bdf31b, + 0xf10099f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0109: wait_doneo */ + 0xf094bd00, + 0x07f10099, + 0x03f03700, + 0x0009d002, + 0x87f104bd, + 0x84b60818, + 0x008ad006, +/* 0x0124: wait_doneo_e */ + 0x040087f1, + 0xcf0684b6, + 0x8aff0088, + 0xf30bf488, + 0x99f094bd, + 0x0007f100, + 0x0203f017, + 0xbd0009d0, +/* 0x0147: mmctx_size */ + 0xbd00f804, +/* 0x0149: nv_mmctx_size_loop */ + 0x00e89894, + 0xb61a85b6, + 0x84b60180, + 0x0098bb02, + 0xb804e0b6, + 0x1bf404ef, + 0x029fb9eb, +/* 0x0166: mmctx_xfer */ + 0x94bd00f8, + 0xf10199f0, + 0xf0370007, + 0x09d00203, + 0xf104bd00, + 0xb6071087, + 0x94bd0684, + 0xf405bbfd, + 0x8bd0090b, + 0x0099f000, +/* 0x018c: mmctx_base_disabled */ + 0xf405eefd, + 0x8ed00c0b, + 0xc08fd080, +/* 0x019b: mmctx_multi_disabled */ + 0xb70199f0, + 0xc8010080, + 0xb4b600ab, + 0x0cb9f010, + 0xb601aec8, + 0xbefd11e4, + 0x008bd005, +/* 0x01b4: mmctx_exec_loop */ +/* 0x01b4: mmctx_wait_free */ + 0xf0008ecf, + 0x0bf41fe4, + 0x00ce98fa, + 0xd005e9fd, + 0xc0b6c08e, + 0x04cdb804, + 0xc8e81bf4, + 0x1bf402ab, +/* 0x01d5: mmctx_fini_wait */ + 0x008bcf18, + 0xb01fb4f0, + 0x1bf410b4, + 0x02a7f0f7, + 0xf4c921f4, +/* 0x01ea: mmctx_stop */ + 0xabc81b0e, + 0x10b4b600, + 0xf00cb9f0, + 0x8bd012b9, +/* 0x01f9: mmctx_stop_wait */ + 0x008bcf00, + 0xf412bbc8, +/* 0x0202: mmctx_done */ + 0x94bdfa1b, + 0xf10199f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0215: strand_wait */ + 0xf0a0f900, + 0x21f402a7, + 0xf8a0fcc9, +/* 0x0221: strand_pre */ + 0xfc87f100, + 0x0283f04a, + 0xd00c97f0, + 0x21f50089, + 0x00f80215, +/* 0x0234: strand_post */ + 0x4afc87f1, + 0xf00283f0, + 0x89d00d97, + 0x1521f500, +/* 0x0247: strand_set */ + 0xf100f802, + 0xf04ffca7, + 0xaba202a3, + 0xc7f00500, + 0x00acd00f, + 0xd00bc7f0, + 0x21f500bc, + 0xaed00215, + 0x0ac7f000, + 0xf500bcd0, + 0xf8021521, +/* 0x0271: strand_ctx_init */ + 0xf094bd00, + 0x07f10399, + 0x03f03700, + 0x0009d002, + 0x21f504bd, + 0xe7f00221, + 0x4721f503, + 0xfca7f102, + 0x02a3f046, + 0x0400aba0, + 0xf040a0d0, + 0xbcd001c7, + 0x1521f500, + 0x010c9202, + 0xf000acd0, + 0xbcd002c7, + 0x1521f500, + 0x3421f502, + 0x8087f102, + 0x0684b608, + 0xb70089cf, + 0x95220080, +/* 0x02ca: ctx_init_strand_loop */ + 0x8ed008fe, + 0x408ed000, + 0xb6808acf, + 0xa0b606a5, + 0x00eabb01, + 0xb60480b6, + 0x1bf40192, + 0x08e4b6e8, + 0xbdf2efbc, + 0x0399f094, + 0x170007f1, + 0xd00203f0, + 0x04bd0009, +/* 0x02fe: error */ + 0x07f100f8, + 0x03f00500, + 0x000fd002, + 0xf7f004bd, + 0x0007f101, + 0x0303f007, + 0xbd000fd0, +/* 0x031b: init */ + 0xbd00f804, + 0x0004fe04, + 0xf10007fe, + 0xf0120017, + 0x12d00227, + 0xb117f100, + 0x0010fe05, + 0x040017f1, + 0xf1c010d0, + 0xb6040437, + 0x27f10634, + 0x32d02003, + 0x0427f100, + 0x0132d020, + 0x200b27f1, + 0xf10232d0, + 0xd0200c27, + 0x27f10732, + 0x24b60c24, + 0x0003b906, + 0xf10023d0, + 0xf0870427, + 0x12d00023, + 0x0012b700, + 0x0427f001, + 0xf40012d0, + 0xe7f11031, + 0xe3f09604, + 0x6821f440, + 0x8090f1c7, + 0xf4f00301, + 0x020f801f, + 0xbb0117f0, + 0x12b6041f, + 0x0c27f101, + 0x0624b604, + 0xd00021d0, + 0x17f14021, + 0x0e980100, + 0x010f9800, + 0x014721f5, + 0x070037f1, + 0x950634b6, + 0x34d00814, + 0x4034d000, + 0x130030b7, + 0xb6001fbb, + 0x3fd002f5, + 0x0815b600, + 0xb60110b6, + 0x1fb90814, + 0x7121f502, + 0x001fbb02, + 0xf1020398, + 0xf0200047, +/* 0x03f6: init_gpc */ + 0x4ea05043, + 0x1fb90804, + 0x8d21f402, + 0x010c4ea0, + 0x21f4f4bd, + 0x044ea08d, + 0x8d21f401, + 0x01004ea0, + 0xf402f7f0, + 0x4ea08d21, +/* 0x041e: init_gpc_wait */ + 0x21f40800, + 0x1fffc868, + 0xa0fa0bf4, + 0xf408044e, + 0x1fbb6821, + 0x0040b700, + 0x0132b680, + 0xf1be1bf4, + 0xf0010007, + 0x01d00203, + 0xbd04bd00, + 0x1f19f014, + 0x300007f1, + 0xd00203f0, + 0x04bd0001, +/* 0x0458: main */ + 0xf40031f4, + 0xd7f00028, + 0x3921f410, + 0xb1f401f4, + 0xf54001e4, + 0xbd00de1b, + 0x0499f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0x0b0017f1, + 0xcf0614b6, + 0x11cf4012, + 0x1f13c800, + 0x00870bf5, + 0xf41f23c8, + 0x20f9620b, + 0xbd0212b9, + 0x0799f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50231, + 0x94bd0801, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xfc04bd00, + 0xf094bd20, + 0x07f10699, + 0x03f03700, + 0x0009d002, + 0x31f404bd, + 0x0121f501, + 0xf094bd08, + 0x07f10699, + 0x03f01700, + 0x0009d002, + 0x0ef404bd, +/* 0x04f9: chsw_prev_no_next */ + 0xb920f931, + 0x32f40212, + 0x0232f401, + 0x080121f5, + 0x17f120fc, + 0x14b60b00, + 0x0012d006, +/* 0x0517: chsw_no_prev */ + 0xc8130ef4, + 0x0bf41f23, + 0x0131f40d, + 0xf50232f4, +/* 0x0527: chsw_done */ + 0xf1080121, + 0xb60b0c17, + 0x27f00614, + 0x0012d001, + 0x99f094bd, + 0x0007f104, + 0x0203f017, + 0xbd0009d0, + 0x130ef504, +/* 0x0549: main_not_ctx_switch */ + 0x01e4b0ff, + 0xb90d1bf4, + 0x21f502f2, + 0x0ef40795, +/* 0x0559: main_not_ctx_chan */ + 0x02e4b046, + 0xbd321bf4, + 0x0799f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0xf40132f4, + 0x21f50232, + 0x94bd0801, + 0xf10799f0, + 0xf0170007, + 0x09d00203, + 0xf404bd00, +/* 0x058e: main_not_ctx_save */ + 0xef94110e, + 0x01f5f010, + 0x02fe21f5, + 0xfec00ef5, +/* 0x059c: main_done */ + 0x29f024bd, + 0x0007f11f, + 0x0203f030, + 0xbd0002d0, + 0xab0ef504, +/* 0x05b1: ih */ + 0xfe80f9fe, + 0x80f90188, + 0xa0f990f9, + 0xd0f9b0f9, + 0xf0f9e0f9, + 0x0acf04bd, + 0x04abc480, + 0xf11d0bf4, + 0xf01900b7, + 0xbecf10d7, + 0x00bfcf40, + 0xb70421f4, + 0xf00400b0, + 0xbed001e7, +/* 0x05e9: ih_no_fifo */ + 0x00abe400, + 0x0d0bf401, + 0xf110d7f0, + 0xf44001e7, +/* 0x05fa: ih_no_ctxsw */ + 0xb7f10421, + 0xb0bd0104, + 0xf4b4abff, + 0xa7f10d0b, + 0xa4b60c1c, + 0x00abd006, +/* 0x0610: ih_no_other */ + 0xfc400ad0, + 0xfce0fcf0, + 0xfcb0fcd0, + 0xfc90fca0, + 0x0088fe80, + 0x32f480fc, +/* 0x062b: ctx_4170s */ + 0xf101f800, + 0xf04170e7, + 0xf5f040e3, + 0x8d21f410, +/* 0x063a: ctx_4170w */ + 0xe7f100f8, + 0xe3f04170, + 0x6821f440, + 0xf410f4f0, + 0x00f8f31b, +/* 0x064c: ctx_redswitch */ + 0x0614e7f1, + 0xf106e4b6, + 0xd00270f7, + 0xf7f000ef, +/* 0x065d: ctx_redswitch_delay */ + 0x01f2b608, + 0xf1fd1bf4, + 0xd00770f7, + 0x00f800ef, +/* 0x066c: ctx_86c */ + 0x086ce7f1, + 0xd006e4b6, + 0xe7f100ef, + 0xe3f08a14, + 0x8d21f440, + 0xa86ce7f1, + 0xf441e3f0, + 0x00f88d21, +/* 0x068c: ctx_load */ + 0x99f094bd, + 0x0007f105, + 0x0203f037, + 0xbd0009d0, + 0x0ca7f004, + 0xf1c921f4, + 0xb60a2417, + 0x10d00614, + 0x0037f100, + 0x0634b60b, + 0xf14032d0, + 0xb60a0c17, + 0x47f00614, + 0x0012d007, +/* 0x06c7: ctx_chan_wait_0 */ + 0xcf4014d0, + 0x44f04014, + 0xfa1bf41f, + 0xfe0032d0, + 0x2af0000b, + 0x0424b61f, + 0xbd0220b6, + 0x0899f094, + 0x370007f1, + 0xd00203f0, + 0x04bd0009, + 0x0a0417f1, + 0xd00614b6, + 0x17f10012, + 0x14b60a20, + 0x0227f006, + 0x800023f1, + 0xf00012d0, + 0x27f11017, + 0x23f00200, + 0x0512fa02, + 0x94bd03f8, + 0xf10899f0, + 0xf0170007, + 0x09d00203, + 0x9804bd00, + 0x14b68101, + 0x80029818, + 0xfd0825b6, + 0x01800512, + 0xf094bd16, + 0x07f10999, + 0x03f03700, + 0x0009d002, + 0x27f104bd, + 0x24b60a04, + 0x0021d006, + 0xf10127f0, + 0xb60a2017, + 0x12d00614, + 0x0017f100, + 0x0613f001, + 0xf80501fa, + 0xf094bd03, + 0x07f10999, + 0x03f01700, + 0x0009d002, + 0x94bd04bd, + 0xf10599f0, + 0xf0170007, + 0x09d00203, + 0xf804bd00, +/* 0x0795: ctx_chan */ + 0x8c21f500, + 0x0ca7f006, + 0xf1c921f4, + 0xb60a1017, + 0x27f00614, + 0x0012d005, +/* 0x07ac: ctx_chan_wait */ + 0xfd0012cf, + 0x1bf40522, +/* 0x07b7: ctx_mmio_exec */ + 0x9800f8fa, + 0x27f14103, + 0x24b60a04, + 0x0023d006, +/* 0x07c6: ctx_mmio_loop */ + 0x34c434bd, + 0x0f1bf4ff, + 0x020057f1, + 0xfa0653f0, + 0x03f80535, +/* 0x07d8: ctx_mmio_pull */ + 0x98804e98, + 0x21f4814f, + 0x0830b68d, + 0xf40112b6, +/* 0x07ea: ctx_mmio_done */ + 0x0398df1b, + 0x0023d016, + 0xf1400080, + 0xf0010017, + 0x01fa0613, + 0xf803f806, +/* 0x0801: ctx_xfer */ + 0x00f7f100, + 0x06f4b60c, + 0xd004e7f0, +/* 0x080e: ctx_xfer_idle */ + 0xfecf80fe, + 0x00e4f100, + 0xf91bf420, + 0xf40611f4, +/* 0x081e: ctx_xfer_pre */ + 0xf7f00d02, + 0x6c21f510, + 0x1c11f406, +/* 0x0828: ctx_xfer_pre_load */ + 0xf502f7f0, + 0xf5062b21, + 0xf5063a21, + 0xbd064c21, + 0x2b21f5f4, + 0x8c21f506, +/* 0x0841: ctx_xfer_exec */ + 0x16019806, + 0x041427f1, + 0xd00624b6, + 0xe7f10020, + 0xe3f0a500, + 0x021fb941, + 0xb68d21f4, + 0xfcf004e0, + 0x022cf001, + 0xfd0124b6, + 0x21f405f2, + 0xfc17f18d, + 0x0213f04a, + 0xd00c27f0, + 0x21f50012, + 0x27f10215, + 0x23f047fc, + 0x0020d002, + 0xb6012cf0, + 0x12d00320, + 0x01acf000, + 0xf006a5f0, + 0x0c9800b7, + 0x010d9800, + 0xf500e7f0, + 0xf0016621, + 0x21f508a7, + 0x21f50109, + 0x01f40215, + 0x0ca7f022, + 0xf1c921f4, + 0xb60a1017, + 0x27f00614, + 0x0012d005, +/* 0x08c8: ctx_xfer_post_save_wait */ + 0xfd0012cf, + 0x1bf40522, + 0x2e02f4fa, +/* 0x08d4: ctx_xfer_post */ + 0xf502f7f0, + 0xbd062b21, + 0x6c21f5f4, + 0x3421f506, + 0x3a21f502, + 0xf5f4bd06, + 0xf4062b21, + 0x01981011, + 0x0511fd40, + 0xf5070bf4, +/* 0x08ff: ctx_xfer_no_post_mmio */ +/* 0x08ff: ctx_xfer_done */ + 0xf807b721, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc index 43a0b9476efd..33a5a82eccbd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc @@ -24,6 +24,33 @@ #include "os.h" +#define GF100 0xc0 +#define GF117 0xd7 +#define GK100 0xe0 +#define GK110 0xf0 + +#define NV_PGRAPH_FECS_SIGNAL 0x409400 +#if CHIPSET < GK110 +#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) +#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +#else +#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) +#endif +#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c + +#if CHIPSET < GK110 +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +#else +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) +#endif + #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) @@ -38,16 +65,25 @@ #define T_LCHAN 8 #define T_LCTXH 9 +#define nv_mkmm(rv,r) /* +*/ movw rv ((r) & 0x0000fffc) /* +*/ sethi rv ((r) & 0x00ff0000) +#define nv_mkio(rv,r,i) /* +*/ nv_mkmm(rv, (((r) & 0xffc) << 6) | ((i) << 2)) + +#define nv_iord(rv,r,i) /* +*/ nv_mkio(rv,r,i) /* +*/ iord rv I[rv] +#define nv_iowr(r,i,rv) /* +*/ nv_mkio($r0,r,i) /* +*/ iowr I[$r0] rv /* +*/ clear b32 $r0 + #define trace_set(bit) /* -*/ mov $r8 0x83c /* -*/ shl b32 $r8 6 /* */ clear b32 $r9 /* */ bset $r9 bit /* -*/ iowr I[$r8 + 0x000] $r9 - +*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) #define trace_clr(bit) /* -*/ mov $r8 0x85c /* -*/ shl b32 $r8 6 /* */ clear b32 $r9 /* */ bset $r9 bit /* -*/ iowr I[$r8 + 0x000] $r9 +*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index d61c833be09f..3f4f35cc3848 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -23,14 +23,12 @@ */ #include "nvc0.h" -#include "fuc/hubnvc0.fuc.h" -#include "fuc/gpcnvc0.fuc.h" /******************************************************************************* * Graphics object classes ******************************************************************************/ -static struct nouveau_oclass +struct nouveau_oclass nvc0_graph_sclass[] = { { 0x902d, &nouveau_object_ofuncs }, { 0x9039, &nouveau_object_ofuncs }, @@ -39,40 +37,6 @@ nvc0_graph_sclass[] = { {} }; -static struct nouveau_oclass -nvc1_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { 0x9097, &nouveau_object_ofuncs }, - { 0x90c0, &nouveau_object_ofuncs }, - { 0x9197, &nouveau_object_ofuncs }, - {} -}; - -static struct nouveau_oclass -nvc8_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0x9039, &nouveau_object_ofuncs }, - { 0x9097, &nouveau_object_ofuncs }, - { 0x90c0, &nouveau_object_ofuncs }, - { 0x9197, &nouveau_object_ofuncs }, - { 0x9297, &nouveau_object_ofuncs }, - {} -}; - -u64 -nvc0_graph_units(struct nouveau_graph *graph) -{ - struct nvc0_graph_priv *priv = (void *)graph; - u64 cfg; - - cfg = (u32)priv->gpc_nr; - cfg |= (u32)priv->tpc_total << 8; - cfg |= (u64)priv->rop_nr << 32; - - return cfg; -} - /******************************************************************************* * PGRAPH context ******************************************************************************/ @@ -181,60 +145,271 @@ nvc0_graph_context_dtor(struct nouveau_object *object) nouveau_graph_context_destroy(&chan->base); } -static struct nouveau_oclass -nvc0_graph_cclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ -static void -nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) +struct nvc0_graph_init +nvc0_graph_init_regs[] = { + { 0x400080, 1, 0x04, 0x003083c2 }, + { 0x400088, 1, 0x04, 0x00006fe7 }, + { 0x40008c, 1, 0x04, 0x00000000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x013901f7 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk40xx[] = { + { 0x40415c, 1, 0x04, 0x00000000 }, + { 0x404170, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk44xx[] = { + { 0x404488, 2, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk78xx[] = { + { 0x407808, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk60xx[] = { + { 0x406024, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk58xx[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405908, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk80xx[] = { + { 0x40803c, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_gpc[] = { + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x80000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 1, 0x04, 0x80000000 }, + { 0x4188cc, 1, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000050 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvc0_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x41980c, 3, 0x04, 0x00000000 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x06060618 }, + { 0x419ed0, 1, 0x04, 0x0eff0e38 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_init_unk88xx[] = { + { 0x40880c, 1, 0x04, 0x00000000 }, + { 0x408910, 9, 0x04, 0x00000000 }, + { 0x408950, 1, 0x04, 0x00000000 }, + { 0x408954, 1, 0x04, 0x0000ffff }, + { 0x408984, 1, 0x04, 0x00000000 }, + { 0x408988, 1, 0x04, 0x08040201 }, + { 0x40898c, 1, 0x04, 0x80402010 }, + {} +}; + +struct nvc0_graph_init +nvc0_graph_tpc_0[] = { + { 0x50405c, 1, 0x04, 0x00000001 }, + {} +}; + +void +nvc0_graph_mmio(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init) { - nv_error(priv, "%06x - done 0x%08x\n", base, - nv_rd32(priv, base + 0x400)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), - nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), - nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); + for (; init && init->count; init++) { + u32 addr = init->addr, i; + for (i = 0; i < init->count; i++) { + nv_wr32(priv, addr, init->data); + addr += init->pitch; + } + } } void -nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) +nvc0_graph_icmd(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init) { - u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; - u32 gpc; + u32 addr, data; + int i, j; + + nv_wr32(priv, 0x400208, 0x80000000); + for (i = 0; init->count; init++, i++) { + if (!i || data != init->data) { + nv_wr32(priv, 0x400204, init->data); + data = init->data; + } - nvc0_graph_ctxctl_debug_unit(priv, 0x409000); - for (gpc = 0; gpc < gpcnr; gpc++) - nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); + addr = init->addr; + for (j = 0; j < init->count; j++) { + nv_wr32(priv, 0x400200, addr); + addr += init->pitch; + while (nv_rd32(priv, 0x400700) & 0x00000002) {} + } + } + nv_wr32(priv, 0x400208, 0x00000000); +} + +void +nvc0_graph_mthd(struct nvc0_graph_priv *priv, struct nvc0_graph_mthd *mthds) +{ + struct nvc0_graph_mthd *mthd; + struct nvc0_graph_init *init; + int i = 0, j; + u32 data; + + while ((mthd = &mthds[i++]) && (init = mthd->init)) { + u32 addr = 0x80000000 | mthd->oclass; + for (data = 0; init->count; init++) { + if (data != init->data) { + nv_wr32(priv, 0x40448c, init->data); + data = init->data; + } + + addr = (addr & 0x8000ffff) | (init->addr << 14); + for (j = 0; j < init->count; j++) { + nv_wr32(priv, 0x404488, addr); + addr += init->pitch << 14; + } + } + } +} + +u64 +nvc0_graph_units(struct nouveau_graph *graph) +{ + struct nvc0_graph_priv *priv = (void *)graph; + u64 cfg; + + cfg = (u32)priv->gpc_nr; + cfg |= (u32)priv->tpc_total << 8; + cfg |= (u64)priv->rop_nr << 32; + + return cfg; } +static const struct nouveau_enum nve0_sked_error[] = { + { 7, "CONSTANT_BUFFER_SIZE" }, + { 9, "LOCAL_MEMORY_SIZE_POS" }, + { 10, "LOCAL_MEMORY_SIZE_NEG" }, + { 11, "WARP_CSTACK_SIZE" }, + { 12, "TOTAL_TEMP_SIZE" }, + { 13, "REGISTER_COUNT" }, + { 18, "TOTAL_THREADS" }, + { 20, "PROGRAM_OFFSET" }, + { 21, "SHARED_MEMORY_SIZE" }, + { 25, "SHARED_CONFIG_TOO_SMALL" }, + { 26, "TOTAL_REGISTER_COUNT" }, + {} +}; + +static const struct nouveau_enum nvc0_gpc_rop_error[] = { + { 1, "RT_PITCH_OVERRUN" }, + { 4, "RT_WIDTH_OVERRUN" }, + { 5, "RT_HEIGHT_OVERRUN" }, + { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, + { 8, "RT_STORAGE_TYPE_MISMATCH" }, + { 10, "RT_LINEAR_MISMATCH" }, + {} +}; + static void -nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) +nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) { - u32 ustat = nv_rd32(priv, 0x409c18); + u32 trap[4]; + int i; - if (ustat & 0x00000001) - nv_error(priv, "CTXCTRL ucode error\n"); - if (ustat & 0x00080000) - nv_error(priv, "CTXCTRL watchdog timeout\n"); - if (ustat & ~0x00080001) - nv_error(priv, "CTXCTRL 0x%08x\n", ustat); + trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); + trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); + trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); + trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); - nvc0_graph_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, ustat); + nv_error(priv, "GPC%d/PROP trap:", gpc); + for (i = 0; i <= 29; ++i) { + if (!(trap[0] & (1 << i))) + continue; + pr_cont(" "); + nouveau_enum_print(nvc0_gpc_rop_error, i); + } + pr_cont("\n"); + + nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", + trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, + trap[3] & 0xff); + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); } static const struct nouveau_enum nvc0_mp_warp_error[] = { @@ -283,13 +458,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000001); stat &= ~0x00000001; } if (stat & 0x00000002) { nvc0_graph_trap_mp(priv, gpc, tpc); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000002); stat &= ~0x00000002; } @@ -297,7 +470,6 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000004); stat &= ~0x00000004; } @@ -305,13 +477,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000008); stat &= ~0x00000008; } if (stat) { nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), stat); } } @@ -322,10 +492,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) int tpc; if (stat & 0x00000001) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); - nv_error(priv, "GPC%d/PROP: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000001); + nvc0_graph_trap_gpc_rop(priv, gpc); stat &= ~0x00000001; } @@ -333,7 +500,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000002); stat &= ~0x00000002; } @@ -341,7 +507,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000004); stat &= ~0x00000004; } @@ -349,7 +514,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000008); stat &= ~0x00000009; } @@ -364,7 +528,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) if (stat) { nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), stat); } } @@ -372,7 +535,7 @@ static void nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) { u32 trap = nv_rd32(priv, 0x400108); - int rop, gpc; + int rop, gpc, i; if (trap & 0x00000001) { u32 stat = nv_rd32(priv, 0x404000); @@ -422,6 +585,24 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) trap &= ~0x00000080; } + if (trap & 0x00000100) { + u32 stat = nv_rd32(priv, 0x407020); + + nv_error(priv, "SKED:"); + for (i = 0; i <= 29; ++i) { + if (!(stat & (1 << i))) + continue; + pr_cont(" "); + nouveau_enum_print(nve0_sked_error, i); + } + pr_cont("\n"); + + if (stat & 0x3fffffff) + nv_wr32(priv, 0x407020, 0x40000000); + nv_wr32(priv, 0x400108, 0x00000100); + trap &= ~0x00000100; + } + if (trap & 0x01000000) { u32 stat = nv_rd32(priv, 0x400118); for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { @@ -456,6 +637,46 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) } static void +nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) +{ + nv_error(priv, "%06x - done 0x%08x\n", base, + nv_rd32(priv, base + 0x400)); + nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), + nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); + nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), + nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); +} + +void +nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) +{ + u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; + u32 gpc; + + nvc0_graph_ctxctl_debug_unit(priv, 0x409000); + for (gpc = 0; gpc < gpcnr; gpc++) + nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); +} + +static void +nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) +{ + u32 ustat = nv_rd32(priv, 0x409c18); + + if (ustat & 0x00000001) + nv_error(priv, "CTXCTL ucode error\n"); + if (ustat & 0x00080000) + nv_error(priv, "CTXCTL watchdog timeout\n"); + if (ustat & ~0x00080001) + nv_error(priv, "CTXCTL 0x%08x\n", ustat); + + nvc0_graph_ctxctl_debug(priv); + nv_wr32(priv, 0x409c20, ustat); +} + +static void nvc0_graph_intr(struct nouveau_subdev *subdev) { struct nouveau_fifo *pfifo = nouveau_fifo(subdev); @@ -531,828 +752,6 @@ nvc0_graph_intr(struct nouveau_subdev *subdev) nouveau_engctx_put(engctx); } -int -nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, - struct nvc0_graph_fuc *fuc) -{ - struct nouveau_device *device = nv_device(priv); - const struct firmware *fw; - char f[32]; - int ret; - - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); - ret = request_firmware(&fw, f, &device->pdev->dev); - if (ret) { - snprintf(f, sizeof(f), "nouveau/%s", fwname); - ret = request_firmware(&fw, f, &device->pdev->dev); - if (ret) { - nv_error(priv, "failed to load %s\n", fwname); - return ret; - } - } - - fuc->size = fw->size; - fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); - release_firmware(fw); - return (fuc->data != NULL) ? 0 : -ENOMEM; -} - -static int -nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nvc0_graph_priv *priv; - bool enable = device->chipset != 0xd7; - int ret, i; - - ret = nouveau_graph_create(parent, engine, oclass, enable, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x18001000; - nv_subdev(priv)->intr = nvc0_graph_intr; - nv_engine(priv)->cclass = &nvc0_graph_cclass; - - priv->base.units = nvc0_graph_units; - - if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) { - nv_info(priv, "using external firmware\n"); - if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) - return -EINVAL; - priv->firmware = true; - } - - switch (nvc0_graph_class(priv)) { - case 0x9097: - nv_engine(priv)->sclass = nvc0_graph_sclass; - break; - case 0x9197: - nv_engine(priv)->sclass = nvc1_graph_sclass; - break; - case 0x9297: - nv_engine(priv)->sclass = nvc8_graph_sclass; - break; - } - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b4); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b8); - if (ret) - return ret; - - for (i = 0; i < 0x1000; i += 4) { - nv_wo32(priv->unk4188b4, i, 0x00000010); - nv_wo32(priv->unk4188b8, i, 0x00000010); - } - - priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; - priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; - for (i = 0; i < priv->gpc_nr; i++) { - priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); - priv->tpc_total += priv->tpc_nr[i]; - } - - /*XXX: these need figuring out... though it might not even matter */ - switch (nv_device(priv)->chipset) { - case 0xc0: - if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ - priv->magic_not_rop_nr = 0x07; - } else - if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ - priv->magic_not_rop_nr = 0x05; - } else - if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ - priv->magic_not_rop_nr = 0x06; - } - break; - case 0xc3: /* 450, 4/0/0/0, 2 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xc4: /* 460, 3/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x01; - break; - case 0xc1: /* 2/0/0/0, 1 */ - priv->magic_not_rop_nr = 0x01; - break; - case 0xc8: /* 4/4/3/4, 5 */ - priv->magic_not_rop_nr = 0x06; - break; - case 0xce: /* 4/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xcf: /* 4/0/0/0, 3 */ - priv->magic_not_rop_nr = 0x03; - break; - case 0xd9: /* 1/0/0/0, 1 */ - priv->magic_not_rop_nr = 0x01; - break; - } - - return 0; -} - -static void -nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc) -{ - kfree(fuc->data); - fuc->data = NULL; -} - -void -nvc0_graph_dtor(struct nouveau_object *object) -{ - struct nvc0_graph_priv *priv = (void *)object; - - kfree(priv->data); - - nvc0_graph_dtor_fw(&priv->fuc409c); - nvc0_graph_dtor_fw(&priv->fuc409d); - nvc0_graph_dtor_fw(&priv->fuc41ac); - nvc0_graph_dtor_fw(&priv->fuc41ad); - - nouveau_gpuobj_ref(NULL, &priv->unk4188b8); - nouveau_gpuobj_ref(NULL, &priv->unk4188b4); - - nouveau_graph_destroy(&priv->base); -} - -static void -nvc0_graph_init_obj418880(struct nvc0_graph_priv *priv) -{ - int i; - - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - for (i = 0; i < 4; i++) - nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); -} - -static void -nvc0_graph_init_regs(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x400080, 0x003083c2); - nv_wr32(priv, 0x400088, 0x00006fe7); - nv_wr32(priv, 0x40008c, 0x00000000); - nv_wr32(priv, 0x400090, 0x00000030); - nv_wr32(priv, 0x40013c, 0x013901f7); - nv_wr32(priv, 0x400140, 0x00000100); - nv_wr32(priv, 0x400144, 0x00000000); - nv_wr32(priv, 0x400148, 0x00000110); - nv_wr32(priv, 0x400138, 0x00000000); - nv_wr32(priv, 0x400130, 0x00000000); - nv_wr32(priv, 0x400134, 0x00000000); - nv_wr32(priv, 0x400124, 0x00000002); -} - -static void -nvc0_graph_init_unk40xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40415c, 0x00000000); - nv_wr32(priv, 0x404170, 0x00000000); -} - -static void -nvc0_graph_init_unk44xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404488, 0x00000000); - nv_wr32(priv, 0x40448c, 0x00000000); -} - -static void -nvc0_graph_init_unk78xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x407808, 0x00000000); -} - -static void -nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x406024, 0x00000000); -} - -static void -nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x4064f0, 0x00000000); - nv_wr32(priv, 0x4064f4, 0x00000000); - nv_wr32(priv, 0x4064f8, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } -} - -static void -nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_wr32(priv, 0x405850, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x405900, 0x00002834); - break; - case 0xc0: - case 0xc8: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x405908, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x405928, 0x00000000); - nv_wr32(priv, 0x40592c, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } -} - -static void -nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40803c, 0x00000000); -} - -static void -nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418408, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x4184a0, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x4184a4, 0x00000000); - nv_wr32(priv, 0x4184a8, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418604, 0x00000000); - nv_wr32(priv, 0x418680, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - case 0xc1: - nv_wr32(priv, 0x418714, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418714, 0x80000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418384, 0x00000000); - nv_wr32(priv, 0x418814, 0x00000000); - nv_wr32(priv, 0x418818, 0x00000000); - nv_wr32(priv, 0x41881c, 0x00000000); - nv_wr32(priv, 0x418b04, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - case 0xc1: - case 0xc8: - nv_wr32(priv, 0x4188c8, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x4188c8, 0x80000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x4188cc, 0x00000000); - nv_wr32(priv, 0x4188d0, 0x00010000); - nv_wr32(priv, 0x4188d4, 0x00000001); - nv_wr32(priv, 0x418910, 0x00010001); - nv_wr32(priv, 0x418914, 0x00000301); - nv_wr32(priv, 0x418918, 0x00800000); - nv_wr32(priv, 0x418980, 0x77777770); - nv_wr32(priv, 0x418984, 0x77777777); - nv_wr32(priv, 0x418988, 0x77777777); - nv_wr32(priv, 0x41898c, 0x77777777); - nv_wr32(priv, 0x418c04, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418c64, 0x00000000); - nv_wr32(priv, 0x418c68, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418c88, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418cb4, 0x00000000); - nv_wr32(priv, 0x418cb8, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418d00, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418d28, 0x00000000); - nv_wr32(priv, 0x418d2c, 0x00000000); - nv_wr32(priv, 0x418f00, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418f08, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418f20, 0x00000000); - nv_wr32(priv, 0x418f24, 0x00000000); - /*fall-through*/ - case 0xc1: - nv_wr32(priv, 0x418e00, 0x00000003); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x418e00, 0x00000050); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x418e08, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x418e1c, 0x00000000); - nv_wr32(priv, 0x418e20, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x41900c, 0x00000000); - nv_wr32(priv, 0x419018, 0x00000000); -} - -static void -nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x419d08, 0x00000000); - nv_wr32(priv, 0x419d0c, 0x00000000); - nv_wr32(priv, 0x419d10, 0x00000014); - nv_wr32(priv, 0x419ab0, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419ac8, 0x00000000); - break; - case 0xc0: - case 0xc8: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419ab8, 0x000000e7); - nv_wr32(priv, 0x419abc, 0x00000000); - nv_wr32(priv, 0x419ac0, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419ab4, 0x00000000); - nv_wr32(priv, 0x41980c, 0x00000010); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x41980c, 0x00000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419810, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - case 0xc1: - nv_wr32(priv, 0x419814, 0x00000004); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419814, 0x00000000); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419844, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x41984c, 0x0000a918); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x41984c, 0x00005bc5); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419850, 0x00000000); - nv_wr32(priv, 0x419854, 0x00000000); - nv_wr32(priv, 0x419858, 0x00000000); - nv_wr32(priv, 0x41985c, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419880, 0x00000002); - break; - case 0xc0: - case 0xc8: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419c98, 0x00000000); - nv_wr32(priv, 0x419ca8, 0x80000000); - nv_wr32(priv, 0x419cb4, 0x00000000); - nv_wr32(priv, 0x419cb8, 0x00008bf4); - nv_wr32(priv, 0x419cbc, 0x28137606); - nv_wr32(priv, 0x419cc0, 0x00000000); - nv_wr32(priv, 0x419cc4, 0x00000000); - nv_wr32(priv, 0x419bd4, 0x00800000); - nv_wr32(priv, 0x419bdc, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419bf8, 0x00000000); - nv_wr32(priv, 0x419bfc, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419d2c, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419d48, 0x00000000); - nv_wr32(priv, 0x419d4c, 0x00000000); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419c0c, 0x00000000); - nv_wr32(priv, 0x419e00, 0x00000000); - nv_wr32(priv, 0x419ea0, 0x00000000); - nv_wr32(priv, 0x419ea4, 0x00000100); - switch (nv_device(priv)->chipset) { - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419ea8, 0x02001100); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xc8: - case 0xce: - case 0xcf: - nv_wr32(priv, 0x419ea8, 0x00001100); - break; - default: - BUG_ON(1); - break; - } - - switch (nv_device(priv)->chipset) { - case 0xc8: - nv_wr32(priv, 0x419eac, 0x11100f02); - break; - case 0xc0: - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419eac, 0x11100702); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419eb0, 0x00000003); - nv_wr32(priv, 0x419eb4, 0x00000000); - nv_wr32(priv, 0x419eb8, 0x00000000); - nv_wr32(priv, 0x419ebc, 0x00000000); - nv_wr32(priv, 0x419ec0, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xc3: - case 0xc4: - case 0xc1: - case 0xce: - case 0xcf: - case 0xd9: - case 0xd7: - nv_wr32(priv, 0x419ec8, 0x0e063818); - nv_wr32(priv, 0x419ecc, 0x0e060e06); - nv_wr32(priv, 0x419ed0, 0x00003818); - break; - case 0xc0: - case 0xc8: - nv_wr32(priv, 0x419ec8, 0x06060618); - nv_wr32(priv, 0x419ed0, 0x0eff0e38); - break; - default: - BUG_ON(1); - break; - } - nv_wr32(priv, 0x419ed4, 0x011104f1); - nv_wr32(priv, 0x419edc, 0x00000000); - nv_wr32(priv, 0x419f00, 0x00000000); - nv_wr32(priv, 0x419f2c, 0x00000000); -} - -static void -nvc0_graph_init_unk88xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40880c, 0x00000000); - nv_wr32(priv, 0x408910, 0x00000000); - nv_wr32(priv, 0x408914, 0x00000000); - nv_wr32(priv, 0x408918, 0x00000000); - nv_wr32(priv, 0x40891c, 0x00000000); - nv_wr32(priv, 0x408920, 0x00000000); - nv_wr32(priv, 0x408924, 0x00000000); - nv_wr32(priv, 0x408928, 0x00000000); - nv_wr32(priv, 0x40892c, 0x00000000); - nv_wr32(priv, 0x408930, 0x00000000); - nv_wr32(priv, 0x408950, 0x00000000); - nv_wr32(priv, 0x408954, 0x0000ffff); - nv_wr32(priv, 0x408984, 0x00000000); - nv_wr32(priv, 0x408988, 0x08040201); - nv_wr32(priv, 0x40898c, 0x80402010); -} - -static void -nvc0_graph_init_gpc_0(struct nvc0_graph_priv *priv) -{ - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); - u32 data[TPC_MAX / 8]; - u8 tpcnr[GPC_MAX]; - int i, gpc, tpc; - - nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */ - - /* - * TP ROP UNKVAL(magic_not_rop_nr) - * 450: 4/0/0/0 2 3 - * 460: 3/4/0/0 4 1 - * 465: 3/4/4/0 4 7 - * 470: 3/3/4/4 5 5 - * 480: 3/4/4/4 6 6 - */ - - memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - data[i / 8] |= tpc << ((i % 8) * 4); - } - - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | - priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); - } - - nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); -} - -static void -nvc0_graph_init_units(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x409c24, 0x000f0000); - nv_wr32(priv, 0x404000, 0xc0000000); /* DISPATCH */ - nv_wr32(priv, 0x404600, 0xc0000000); /* M2MF */ - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x40601c, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); /* MACRO */ - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); -} - -static void -nvc0_graph_init_gpc_1(struct nvc0_graph_priv *priv) -{ - int gpc, tpc; - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); - } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); - } -} - -static void -nvc0_graph_init_rop(struct nvc0_graph_priv *priv) -{ - int rop; - - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); - } -} - void nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) @@ -1371,9 +770,46 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, } } -static int +static void +nvc0_graph_init_csdata(struct nvc0_graph_priv *priv, + struct nvc0_graph_init *init, + u32 falcon, u32 starstar, u32 base) +{ + u32 addr = init->addr; + u32 next = addr; + u32 star, temp; + + nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); + star = nv_rd32(priv, falcon + 0x01c4); + temp = nv_rd32(priv, falcon + 0x01c4); + if (temp > star) + star = temp; + nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); + + do { + if (init->addr != next) { + while (addr < next) { + u32 nr = min((int)(next - addr) / 4, 32); + nv_wr32(priv, falcon + 0x01c4, + ((nr - 1) << 26) | (addr - base)); + addr += nr * 4; + star += 4; + } + addr = next = init->addr; + } + next += init->count * 4; + } while ((init++)->count); + + nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); + nv_wr32(priv, falcon + 0x01c4, star); +} + +int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) { + struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; + struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; + struct nvc0_graph_init *init; u32 r000260; int i; @@ -1424,6 +860,38 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) return -EBUSY; } + if (nv_device(priv)->chipset >= 0xe0) { + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000030); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x30 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409810, 0xb00095c8); + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000031); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x31 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409810, 0x00080420); + nv_wr32(priv, 0x409800, 0x00000000); + nv_wr32(priv, 0x409500, 0x00000001); + nv_wr32(priv, 0x409504, 0x00000032); + if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(priv, "fuc09 req 0x32 timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x409614, 0x00000070); + nv_wr32(priv, 0x409614, 0x00000770); + nv_wr32(priv, 0x40802c, 0x00000001); + } + if (priv->data == NULL) { int ret = nvc0_grctx_generate(priv); if (ret) { @@ -1438,31 +906,41 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) /* load HUB microcode */ r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); nv_wr32(priv, 0x4091c0, 0x01000000); - for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++) - nv_wr32(priv, 0x4091c4, nvc0_grhub_data[i]); + for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) + nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); nv_wr32(priv, 0x409180, 0x01000000); - for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) { + for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) nv_wr32(priv, 0x409188, i >> 6); - nv_wr32(priv, 0x409184, nvc0_grhub_code[i]); + nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); + } + + for (i = 0; (init = cclass->hub[i]); i++) { + nvc0_graph_init_csdata(priv, init, 0x409000, 0x000, 0x000000); } /* load GPC microcode */ nv_wr32(priv, 0x41a1c0, 0x01000000); - for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++) - nv_wr32(priv, 0x41a1c4, nvc0_grgpc_data[i]); + for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) + nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); nv_wr32(priv, 0x41a180, 0x01000000); - for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) { + for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) nv_wr32(priv, 0x41a188, i >> 6); - nv_wr32(priv, 0x41a184, nvc0_grgpc_code[i]); + nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); } nv_wr32(priv, 0x000260, r000260); + if ((init = cclass->gpc[0])) + nvc0_graph_init_csdata(priv, init, 0x41a000, 0x000, 0x418000); + if ((init = cclass->gpc[2])) + nvc0_graph_init_csdata(priv, init, 0x41a000, 0x004, 0x419800); + if ((init = cclass->gpc[3])) + nvc0_graph_init_csdata(priv, init, 0x41a000, 0x008, 0x41be00); + /* start HUB ucode running, it'll init the GPCs */ - nv_wr32(priv, 0x409800, nv_device(priv)->chipset); nv_wr32(priv, 0x40910c, 0x00000000); nv_wr32(priv, 0x409100, 0x00000002); if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { @@ -1483,38 +961,104 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) return 0; } -static int +int nvc0_graph_init(struct nouveau_object *object) { + struct nvc0_graph_oclass *oclass = (void *)object->oclass; struct nvc0_graph_priv *priv = (void *)object; - int ret; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc, rop; + int ret, i; ret = nouveau_graph_init(&priv->base); if (ret) return ret; - nvc0_graph_init_obj418880(priv); - nvc0_graph_init_regs(priv); - nvc0_graph_init_unk40xx(priv); - nvc0_graph_init_unk44xx(priv); - nvc0_graph_init_unk78xx(priv); - nvc0_graph_init_unk60xx(priv); - nvc0_graph_init_unk64xx(priv); - nvc0_graph_init_unk58xx(priv); - nvc0_graph_init_unk80xx(priv); - nvc0_graph_init_gpc(priv); - nvc0_graph_init_tpc(priv); - nvc0_graph_init_unk88xx(priv); - nvc0_graph_init_gpc_0(priv); - /*nvc0_graph_init_unitplemented_c242(priv);*/ + nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); + nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + + for (i = 0; oclass->mmio[i]; i++) + nvc0_graph_mmio(priv, oclass->mmio[i]); + + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + if (nv_device(priv)->chipset != 0xd7) + nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); + else + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + + nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, 0x400500, 0x00010001); + nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); - nvc0_graph_init_units(priv); - nvc0_graph_init_gpc_1(priv); - nvc0_graph_init_rop(priv); + nv_wr32(priv, 0x409c24, 0x000f0000); + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x40601c, 0xc0000000); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x406018, 0xc0000000); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x405844, 0x00ffffff); + nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + } + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + } + + for (rop = 0; rop < priv->rop_nr; rop++) { + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); @@ -1522,22 +1066,205 @@ nvc0_graph_init(struct nouveau_object *object) nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(priv, 0x400054, 0x34ce3464); + return nvc0_graph_init_ctxctl(priv); +} + +static void +nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc) +{ + kfree(fuc->data); + fuc->data = NULL; +} + +int +nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, + struct nvc0_graph_fuc *fuc) +{ + struct nouveau_device *device = nv_device(priv); + const struct firmware *fw; + char f[32]; + int ret; + + snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); + ret = request_firmware(&fw, f, &device->pdev->dev); + if (ret) { + snprintf(f, sizeof(f), "nouveau/%s", fwname); + ret = request_firmware(&fw, f, &device->pdev->dev); + if (ret) { + nv_error(priv, "failed to load %s\n", fwname); + return ret; + } + } + + fuc->size = fw->size; + fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); + release_firmware(fw); + return (fuc->data != NULL) ? 0 : -ENOMEM; +} + +void +nvc0_graph_dtor(struct nouveau_object *object) +{ + struct nvc0_graph_priv *priv = (void *)object; + + kfree(priv->data); + + nvc0_graph_dtor_fw(&priv->fuc409c); + nvc0_graph_dtor_fw(&priv->fuc409d); + nvc0_graph_dtor_fw(&priv->fuc41ac); + nvc0_graph_dtor_fw(&priv->fuc41ad); + + nouveau_gpuobj_ref(NULL, &priv->unk4188b8); + nouveau_gpuobj_ref(NULL, &priv->unk4188b4); + + nouveau_graph_destroy(&priv->base); +} + +int +nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, + struct nouveau_oclass *bclass, void *data, u32 size, + struct nouveau_object **pobject) +{ + struct nvc0_graph_oclass *oclass = (void *)bclass; + struct nouveau_device *device = nv_device(parent); + struct nvc0_graph_priv *priv; + int ret, i; + + ret = nouveau_graph_create(parent, engine, bclass, + (oclass->fecs.ucode != NULL), &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x18001000; + nv_subdev(priv)->intr = nvc0_graph_intr; + + priv->base.units = nvc0_graph_units; - ret = nvc0_graph_init_ctxctl(priv); + if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) { + nv_info(priv, "using external firmware\n"); + if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || + nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || + nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || + nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) + return -EINVAL; + priv->firmware = true; + } + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b4); + if (ret) + return ret; + + ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, + &priv->unk4188b8); if (ret) return ret; + for (i = 0; i < 0x1000; i += 4) { + nv_wo32(priv->unk4188b4, i, 0x00000010); + nv_wo32(priv->unk4188b8, i, 0x00000010); + } + + priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; + priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; + for (i = 0; i < priv->gpc_nr; i++) { + priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); + priv->tpc_total += priv->tpc_nr[i]; + } + + /*XXX: these need figuring out... though it might not even matter */ + switch (nv_device(priv)->chipset) { + case 0xc0: + if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ + priv->magic_not_rop_nr = 0x07; + } else + if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ + priv->magic_not_rop_nr = 0x05; + } else + if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ + priv->magic_not_rop_nr = 0x06; + } + break; + case 0xc3: /* 450, 4/0/0/0, 2 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xc4: /* 460, 3/4/0/0, 4 */ + priv->magic_not_rop_nr = 0x01; + break; + case 0xc1: /* 2/0/0/0, 1 */ + priv->magic_not_rop_nr = 0x01; + break; + case 0xc8: /* 4/4/3/4, 5 */ + priv->magic_not_rop_nr = 0x06; + break; + case 0xce: /* 4/4/0/0, 4 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xcf: /* 4/0/0/0, 3 */ + priv->magic_not_rop_nr = 0x03; + break; + case 0xd7: + case 0xd9: /* 1/0/0/0, 1 */ + priv->magic_not_rop_nr = 0x01; + break; + } + + nv_engine(priv)->cclass = *oclass->cclass; + nv_engine(priv)->sclass = oclass->sclass; return 0; } -struct nouveau_oclass -nvc0_graph_oclass = { - .handle = NV_ENGINE(GR, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { +struct nvc0_graph_init * +nvc0_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvc0_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvc0_graph_init_gpc, + nvc0_graph_init_tpc, + nvc0_graph_init_unk88xx, + nvc0_graph_tpc_0, + NULL +}; + +#include "fuc/hubnvc0.fuc.h" + +struct nvc0_graph_ucode +nvc0_graph_fecs_ucode = { + .code.data = nvc0_grhub_code, + .code.size = sizeof(nvc0_grhub_code), + .data.data = nvc0_grhub_data, + .data.size = sizeof(nvc0_grhub_data), +}; + +#include "fuc/gpcnvc0.fuc.h" + +struct nvc0_graph_ucode +nvc0_graph_gpccs_ucode = { + .code.data = nvc0_grgpc_code, + .code.size = sizeof(nvc0_grgpc_code), + .data.data = nvc0_grgpc_data, + .data.size = sizeof(nvc0_grgpc_data), +}; + +struct nouveau_oclass * +nvc0_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xc0), + .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_graph_ctor, .dtor = nvc0_graph_dtor, .init = nvc0_graph_init, .fini = _nouveau_graph_fini, }, -}; + .cclass = &nvc0_grctx_oclass, + .sclass = nvc0_graph_sclass, + .mmio = nvc0_graph_init_mmio, + .fecs.ucode = &nvc0_graph_fecs_ucode, + .gpccs.ucode = &nvc0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h index af7212d96f3f..ea17a80ad7fc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h @@ -102,76 +102,187 @@ struct nvc0_graph_chan { } data[4]; }; -static inline u32 -nvc0_graph_class(void *obj) -{ - struct nouveau_device *device = nv_device(obj); - - switch (device->chipset) { - case 0xc0: - case 0xc3: - case 0xc4: - case 0xce: /* guess, mmio trace shows only 0x9097 state */ - case 0xcf: /* guess, mmio trace shows only 0x9097 state */ - return 0x9097; - case 0xc1: - return 0x9197; - case 0xc8: - case 0xd9: - case 0xd7: - return 0x9297; - case 0xe4: - case 0xe7: - case 0xe6: - return 0xa097; - case 0xf0: - return 0xa197; - default: - return 0; - } -} - -void nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data); - -static inline void -nv_mthd(struct nvc0_graph_priv *priv, u32 class, u32 mthd, u32 data) -{ - nv_wr32(priv, 0x40448c, data); - nv_wr32(priv, 0x404488, 0x80000000 | (mthd << 14) | class); -} +int nvc0_grctx_generate(struct nvc0_graph_priv *); + +int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *, u32, + struct nouveau_object **); +void nvc0_graph_context_dtor(struct nouveau_object *); + +void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); + +u64 nvc0_graph_units(struct nouveau_graph *); +int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *, + struct nouveau_oclass *, void *data, u32 size, + struct nouveau_object **); +void nvc0_graph_dtor(struct nouveau_object *); +int nvc0_graph_init(struct nouveau_object *); +int nve4_graph_init(struct nouveau_object *); + +extern struct nouveau_oclass nvc0_graph_sclass[]; + +extern struct nouveau_oclass nvc8_graph_sclass[]; + +struct nvc0_graph_init { + u32 addr; + u8 count; + u8 pitch; + u32 data; +}; + +struct nvc0_graph_mthd { + u16 oclass; + struct nvc0_graph_init *init; +}; struct nvc0_grctx { struct nvc0_graph_priv *priv; struct nvc0_graph_data *data; struct nvc0_graph_mmio *mmio; - struct nouveau_gpuobj *chan; int buffer_nr; u64 buffer[4]; u64 addr; }; +struct nvc0_grctx_oclass { + struct nouveau_oclass base; + /* main context generation function */ + void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *); + /* context-specific modify-on-first-load list generation function */ + void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *); + void (*unkn)(struct nvc0_graph_priv *); + /* mmio context data */ + struct nvc0_graph_init **hub; + struct nvc0_graph_init **gpc; + /* indirect context data, generated with icmds/mthds */ + struct nvc0_graph_init *icmd; + struct nvc0_graph_mthd *mthd; +}; + +struct nvc0_graph_ucode { + struct nvc0_graph_fuc code; + struct nvc0_graph_fuc data; +}; + +extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode; +extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode; + +struct nvc0_graph_oclass { + struct nouveau_oclass base; + struct nouveau_oclass **cclass; + struct nouveau_oclass *sclass; + struct nvc0_graph_init **mmio; + struct { + struct nvc0_graph_ucode *ucode; + } fecs; + struct { + struct nvc0_graph_ucode *ucode; + } gpccs; +}; + +void nvc0_graph_mmio(struct nvc0_graph_priv *, struct nvc0_graph_init *); +void nvc0_graph_icmd(struct nvc0_graph_priv *, struct nvc0_graph_init *); +void nvc0_graph_mthd(struct nvc0_graph_priv *, struct nvc0_graph_mthd *); +int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *); + +extern struct nvc0_graph_init nvc0_graph_init_regs[]; +extern struct nvc0_graph_init nvc0_graph_init_unk40xx[]; +extern struct nvc0_graph_init nvc0_graph_init_unk44xx[]; +extern struct nvc0_graph_init nvc0_graph_init_unk78xx[]; +extern struct nvc0_graph_init nvc0_graph_init_unk60xx[]; +extern struct nvc0_graph_init nvc0_graph_init_unk58xx[]; +extern struct nvc0_graph_init nvc0_graph_init_unk80xx[]; +extern struct nvc0_graph_init nvc0_graph_init_gpc[]; +extern struct nvc0_graph_init nvc0_graph_init_unk88xx[]; +extern struct nvc0_graph_init nvc0_graph_tpc_0[]; + +extern struct nvc0_graph_init nvc3_graph_init_unk58xx[]; + +extern struct nvc0_graph_init nvd9_graph_init_unk58xx[]; +extern struct nvc0_graph_init nvd9_graph_init_unk64xx[]; + +extern struct nvc0_graph_init nve4_graph_init_regs[]; +extern struct nvc0_graph_init nve4_graph_init_unk[]; +extern struct nvc0_graph_init nve4_graph_init_unk88xx[]; + int nvc0_grctx_generate(struct nvc0_graph_priv *); -int nvc0_grctx_init(struct nvc0_graph_priv *, struct nvc0_grctx *); -void nvc0_grctx_data(struct nvc0_grctx *, u32, u32, u32); -void nvc0_grctx_mmio(struct nvc0_grctx *, u32, u32, u32, u32); -int nvc0_grctx_fini(struct nvc0_grctx *); +void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); +void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); +void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); +void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); +void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *); +void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *); +void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *); +void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); +void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *); -int nve0_grctx_generate(struct nvc0_graph_priv *); +extern struct nouveau_oclass *nvc0_grctx_oclass; +extern struct nvc0_graph_init *nvc0_grctx_init_hub[]; +extern struct nvc0_graph_init nvc0_grctx_init_base[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk40xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk44xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk46xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk47xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[]; +extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[]; +extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[]; +extern struct nvc0_graph_init nvc0_grctx_init_tpc[]; +extern struct nvc0_graph_init nvc0_grctx_init_icmd[]; +extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; // -#define mmio_data(s,a,p) nvc0_grctx_data(&info, (s), (a), (p)) -#define mmio_list(r,d,s,b) nvc0_grctx_mmio(&info, (r), (d), (s), (b)) +extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[]; +extern struct nvc0_graph_init nvc0_grctx_init_902d[]; +extern struct nvc0_graph_init nvc0_grctx_init_9039[]; +extern struct nvc0_graph_init nvc0_grctx_init_90c0[]; +extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[]; -void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); -int nvc0_graph_ctor_fw(struct nvc0_graph_priv *, const char *, - struct nvc0_graph_fuc *); -void nvc0_graph_dtor(struct nouveau_object *); -void nvc0_graph_init_fw(struct nvc0_graph_priv *, u32 base, - struct nvc0_graph_fuc *, struct nvc0_graph_fuc *); -int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_graph_context_dtor(struct nouveau_object *); +void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); +void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); +extern struct nouveau_oclass *nvc1_grctx_oclass; +extern struct nvc0_graph_init nvc1_grctx_init_9097[]; + +extern struct nouveau_oclass *nvc3_grctx_oclass; + +extern struct nouveau_oclass *nvc8_grctx_oclass; +extern struct nvc0_graph_init nvc8_grctx_init_9197[]; +extern struct nvc0_graph_init nvc8_grctx_init_9297[]; + +extern struct nouveau_oclass *nvd7_grctx_oclass; + +extern struct nouveau_oclass *nvd9_grctx_oclass; +extern struct nvc0_graph_init nvd9_grctx_init_rop[]; +extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[]; + +void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); +void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); +extern struct nouveau_oclass *nve4_grctx_oclass; +extern struct nvc0_graph_init nve4_grctx_init_unk46xx[]; +extern struct nvc0_graph_init nve4_grctx_init_unk47xx[]; +extern struct nvc0_graph_init nve4_grctx_init_unk58xx[]; +extern struct nvc0_graph_init nve4_grctx_init_unk80xx[]; +extern struct nvc0_graph_init nve4_grctx_init_unk90xx[]; + +extern struct nouveau_oclass *nvf0_grctx_oclass; + +#define mmio_data(s,a,p) do { \ + info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \ + info->addr = info->buffer[info->buffer_nr++] + (s); \ + info->data->size = (s); \ + info->data->align = (a); \ + info->data->access = (p); \ + info->data++; \ +} while(0) -u64 nvc0_graph_units(struct nouveau_graph *); +#define mmio_list(r,d,s,b) do { \ + info->mmio->addr = (r); \ + info->mmio->data = (d); \ + info->mmio->shift = (s); \ + info->mmio->buffer = (b); \ + info->mmio++; \ + nv_wr32(priv, (r), (d) | ((s) ? (info->buffer[(b)] >> (s)) : 0)); \ +} while(0) #endif diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c new file mode 100644 index 000000000000..bc4a469b86cb --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c @@ -0,0 +1,144 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nvc1_graph_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0x9039, &nouveau_object_ofuncs }, + { 0x9097, &nouveau_object_ofuncs }, + { 0x90c0, &nouveau_object_ofuncs }, + { 0x9197, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static struct nvc0_graph_init +nvc1_graph_init_gpc[] = { + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000003 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvc1_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x41980c, 2, 0x04, 0x00000000 }, + { 0x419814, 1, 0x04, 0x00000004 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init * +nvc1_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvc3_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvc1_graph_init_gpc, + nvc1_graph_init_tpc, + nvc0_graph_init_unk88xx, + nvc0_graph_tpc_0, + NULL +}; + +struct nouveau_oclass * +nvc1_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xc1), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nvc0_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nvc1_grctx_oclass, + .sclass = nvc1_graph_sclass, + .mmio = nvc1_graph_init_mmio, + .fecs.ucode = &nvc0_graph_fecs_ucode, + .gpccs.ucode = &nvc0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c new file mode 100644 index 000000000000..d44b3b3ee800 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c @@ -0,0 +1,110 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nvc0_graph_init +nvc3_graph_init_unk58xx[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00002834 }, + { 0x405908, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvc3_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x41980c, 3, 0x04, 0x00000000 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init * +nvc3_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvc3_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvc0_graph_init_gpc, + nvc3_graph_init_tpc, + nvc0_graph_init_unk88xx, + nvc0_graph_tpc_0, + NULL +}; + +struct nouveau_oclass * +nvc3_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xc3), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nvc0_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nvc3_grctx_oclass, + .sclass = nvc0_graph_sclass, + .mmio = nvc3_graph_init_mmio, + .fecs.ucode = &nvc0_graph_fecs_ucode, + .gpccs.ucode = &nvc0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c new file mode 100644 index 000000000000..02845e567314 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +struct nouveau_oclass +nvc8_graph_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0x9039, &nouveau_object_ofuncs }, + { 0x9097, &nouveau_object_ofuncs }, + { 0x90c0, &nouveau_object_ofuncs }, + { 0x9197, &nouveau_object_ofuncs }, + { 0x9297, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static struct nvc0_graph_init +nvc8_graph_init_gpc[] = { + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x80000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000050 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvc8_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x41980c, 3, 0x04, 0x00000000 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc5 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00001100 }, + { 0x419eac, 1, 0x04, 0x11100f02 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x06060618 }, + { 0x419ed0, 1, 0x04, 0x0eff0e38 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init * +nvc8_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvc0_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvc8_graph_init_gpc, + nvc8_graph_init_tpc, + nvc0_graph_init_unk88xx, + nvc0_graph_tpc_0, + NULL +}; + +struct nouveau_oclass * +nvc8_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xc8), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nvc0_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nvc8_grctx_oclass, + .sclass = nvc8_graph_sclass, + .mmio = nvc8_graph_init_mmio, + .fecs.ucode = &nvc0_graph_fecs_ucode, + .gpccs.ucode = &nvc0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c new file mode 100644 index 000000000000..5052d7ab4d72 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c @@ -0,0 +1,167 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +#include "fuc/hubnvd7.fuc.h" + +struct nvc0_graph_ucode +nvd7_graph_fecs_ucode = { + .code.data = nvd7_grhub_code, + .code.size = sizeof(nvd7_grhub_code), + .data.data = nvd7_grhub_data, + .data.size = sizeof(nvd7_grhub_data), +}; + +#include "fuc/gpcnvd7.fuc.h" + +struct nvc0_graph_ucode +nvd7_graph_gpccs_ucode = { + .code.data = nvd7_grgpc_code, + .code.size = sizeof(nvd7_grgpc_code), + .data.data = nvd7_grgpc_data, + .data.size = sizeof(nvd7_grgpc_data), +}; + +static struct nvc0_graph_init +nvd7_graph_init_gpc[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x4184a4, 2, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c64, 1, 0x04, 0x00000000 }, + { 0x418c68, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418cb4, 2, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 1, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000003 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 1, 0x04, 0x00000000 }, + { 0x418e20, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x00005bc8 }, + { 0x419850, 2, 0x04, 0x00000000 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x02001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd7_graph_init_tpc_0[] = { + { 0x40402c, 1, 0x04, 0x00000000 }, + { 0x4040f0, 1, 0x04, 0x00000000 }, + { 0x404174, 1, 0x04, 0x00000000 }, + { 0x503018, 1, 0x04, 0x00000001 }, + {} +}; + +static struct nvc0_graph_init * +nvd7_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvd9_graph_init_unk64xx, + nvd9_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvd7_graph_init_gpc, + nvd7_graph_init_tpc, + nve4_graph_init_unk, + nvc0_graph_init_unk88xx, + nvd7_graph_init_tpc_0, + NULL +}; + +struct nouveau_oclass * +nvd7_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xd7), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nvc0_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nvd7_grctx_oclass, + .sclass = nvc8_graph_sclass, + .mmio = nvd7_graph_init_mmio, + .fecs.ucode = &nvd7_graph_fecs_ucode, + .gpccs.ucode = &nvd7_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c new file mode 100644 index 000000000000..652098e0df3f --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c @@ -0,0 +1,165 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nvc0_graph_init +nvd9_graph_init_unk64xx[] = { + { 0x4064f0, 3, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nvd9_graph_init_unk58xx[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x00002834 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 1, 0x04, 0x00000000 }, + { 0x40592c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd9_graph_init_gpc[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x4184a4, 2, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c64, 1, 0x04, 0x00000000 }, + { 0x418c68, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418cb4, 2, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 1, 0x04, 0x00000000 }, + { 0x418d2c, 1, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000003 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 1, 0x04, 0x00000000 }, + { 0x418e20, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvd9_graph_init_tpc[] = { + { 0x419d08, 2, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419810, 1, 0x04, 0x00000000 }, + { 0x419814, 1, 0x04, 0x00000004 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x41984c, 1, 0x04, 0x0000a918 }, + { 0x419850, 4, 0x04, 0x00000000 }, + { 0x419880, 1, 0x04, 0x00000002 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x80000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00008bf4 }, + { 0x419cbc, 1, 0x04, 0x28137606 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419bd4, 1, 0x04, 0x00800000 }, + { 0x419bdc, 1, 0x04, 0x00000000 }, + { 0x419bf8, 1, 0x04, 0x00000000 }, + { 0x419bfc, 1, 0x04, 0x00000000 }, + { 0x419d2c, 1, 0x04, 0x00000000 }, + { 0x419d48, 1, 0x04, 0x00000000 }, + { 0x419d4c, 1, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x02001100 }, + { 0x419eac, 1, 0x04, 0x11100702 }, + { 0x419eb0, 1, 0x04, 0x00000003 }, + { 0x419eb4, 4, 0x04, 0x00000000 }, + { 0x419ec8, 1, 0x04, 0x0e063818 }, + { 0x419ecc, 1, 0x04, 0x0e060e06 }, + { 0x419ed0, 1, 0x04, 0x00003818 }, + { 0x419ed4, 1, 0x04, 0x011104f1 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f2c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init * +nvd9_graph_init_mmio[] = { + nvc0_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvd9_graph_init_unk64xx, + nvd9_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvd9_graph_init_gpc, + nvd9_graph_init_tpc, + nvc0_graph_init_unk88xx, + nvc0_graph_tpc_0, + NULL +}; + +struct nouveau_oclass * +nvd9_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xd9), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nvc0_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nvd9_grctx_oclass, + .sclass = nvc8_graph_sclass, + .mmio = nvd9_graph_init_mmio, + .fecs.ucode = &nvc0_graph_fecs_ucode, + .gpccs.ucode = &nvc0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c deleted file mode 100644 index f4685bb66eb8..000000000000 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c +++ /dev/null @@ -1,1105 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#include "nvc0.h" -#include "fuc/hubnve0.fuc.h" -#include "fuc/gpcnve0.fuc.h" - -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nouveau_oclass -nve0_graph_sclass[] = { - { 0x902d, &nouveau_object_ofuncs }, - { 0xa040, &nouveau_object_ofuncs }, - { 0xa097, &nouveau_object_ofuncs }, - { 0xa0c0, &nouveau_object_ofuncs }, - {} -}; - -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - -static struct nouveau_oclass -nve0_graph_cclass = { - .handle = NV_ENGCTX(GR, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_graph_context_ctor, - .dtor = nvc0_graph_context_dtor, - .init = _nouveau_graph_context_init, - .fini = _nouveau_graph_context_fini, - .rd32 = _nouveau_graph_context_rd32, - .wr32 = _nouveau_graph_context_wr32, - }, -}; - -/******************************************************************************* - * PGRAPH engine/subdev functions - ******************************************************************************/ - -static void -nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) -{ - u32 ustat = nv_rd32(priv, 0x409c18); - - if (ustat & 0x00000001) - nv_error(priv, "CTXCTRL ucode error\n"); - if (ustat & 0x00080000) - nv_error(priv, "CTXCTRL watchdog timeout\n"); - if (ustat & ~0x00080001) - nv_error(priv, "CTXCTRL 0x%08x\n", ustat); - - nvc0_graph_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, ustat); -} - -static const struct nouveau_enum nve0_mp_warp_error[] = { - { 0x00, "NO_ERROR" }, - { 0x01, "STACK_MISMATCH" }, - { 0x05, "MISALIGNED_PC" }, - { 0x08, "MISALIGNED_GPR" }, - { 0x09, "INVALID_OPCODE" }, - { 0x0d, "GPR_OUT_OF_BOUNDS" }, - { 0x0e, "MEM_OUT_OF_BOUNDS" }, - { 0x0f, "UNALIGNED_MEM_ACCESS" }, - { 0x11, "INVALID_PARAM" }, - {} -}; - -static const struct nouveau_bitfield nve0_mp_global_error[] = { - { 0x00000004, "MULTIPLE_WARP_ERRORS" }, - { 0x00000008, "OUT_OF_STACK_SPACE" }, - {} -}; - -static const struct nouveau_enum nve0_gpc_rop_error[] = { - { 1, "RT_PITCH_OVERRUN" }, - { 4, "RT_WIDTH_OVERRUN" }, - { 5, "RT_HEIGHT_OVERRUN" }, - { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, - { 8, "RT_STORAGE_TYPE_MISMATCH" }, - { 10, "RT_LINEAR_MISMATCH" }, - {} -}; - -static const struct nouveau_enum nve0_sked_error[] = { - { 7, "CONSTANT_BUFFER_SIZE" }, - { 9, "LOCAL_MEMORY_SIZE_POS" }, - { 10, "LOCAL_MEMORY_SIZE_NEG" }, - { 11, "WARP_CSTACK_SIZE" }, - { 12, "TOTAL_TEMP_SIZE" }, - { 13, "REGISTER_COUNT" }, - { 18, "TOTAL_THREADS" }, - { 20, "PROGRAM_OFFSET" }, - { 21, "SHARED_MEMORY_SIZE" }, - { 25, "SHARED_CONFIG_TOO_SMALL" }, - { 26, "TOTAL_REGISTER_COUNT" }, - {} -}; - -static void -nve0_graph_mp_trap(struct nvc0_graph_priv *priv, int gpc, int tpc) -{ - u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); - u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); - - nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); - nouveau_bitfield_print(nve0_mp_global_error, gerr); - if (werr) { - pr_cont(" "); - nouveau_enum_print(nve0_mp_warp_error, werr & 0xffff); - } - pr_cont("\n"); - - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); -} - -static void -nve0_graph_tpc_trap(struct nvc0_graph_priv *priv, int gpc, int tpc) -{ - u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x508)); - - if (stat & 0x1) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x224)); - nv_error(priv, "GPC%i/TPC%i/TEX trap: %08x\n", - gpc, tpc, trap); - - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - stat &= ~0x1; - } - - if (stat & 0x2) { - nve0_graph_mp_trap(priv, gpc, tpc); - stat &= ~0x2; - } - - if (stat & 0x4) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x084)); - nv_error(priv, "GPC%i/TPC%i/POLY trap: %08x\n", - gpc, tpc, trap); - - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - stat &= ~0x4; - } - - if (stat & 0x8) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x48c)); - nv_error(priv, "GPC%i/TPC%i/L1C trap: %08x\n", - gpc, tpc, trap); - - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - stat &= ~0x8; - } - - if (stat) { - nv_error(priv, "GPC%i/TPC%i: unknown stat %08x\n", - gpc, tpc, stat); - } -} - -static void -nve0_graph_gpc_trap(struct nvc0_graph_priv *priv) -{ - const u32 mask = nv_rd32(priv, 0x400118); - int gpc; - - for (gpc = 0; gpc < 4; ++gpc) { - u32 stat; - int tpc; - - if (!(mask & (1 << gpc))) - continue; - stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); - - if (stat & 0x0001) { - u32 trap[4]; - int i; - - trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); - trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); - trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); - trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); - - nv_error(priv, "GPC%i/PROP trap:", gpc); - for (i = 0; i <= 29; ++i) { - if (!(trap[0] & (1 << i))) - continue; - pr_cont(" "); - nouveau_enum_print(nve0_gpc_rop_error, i); - } - pr_cont("\n"); - - nv_error(priv, "x = %u, y = %u, " - "format = %x, storage type = %x\n", - trap[1] & 0xffff, - trap[1] >> 16, - (trap[2] >> 8) & 0x3f, - trap[3] & 0xff); - - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - stat &= ~0x0001; - } - - if (stat & 0x0002) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); - nv_error(priv, "GPC%i/ZCULL trap: %08x\n", gpc, - trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - stat &= ~0x0002; - } - - if (stat & 0x0004) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); - nv_error(priv, "GPC%i/CCACHE trap: %08x\n", gpc, - trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - stat &= ~0x0004; - } - - if (stat & 0x0008) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); - nv_error(priv, "GPC%i/ESETUP trap %08x\n", gpc, - trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - stat &= ~0x0008; - } - - for (tpc = 0; tpc < 8; ++tpc) { - if (stat & (1 << (16 + tpc))) - nve0_graph_tpc_trap(priv, gpc, tpc); - } - stat &= ~0xff0000; - - if (stat) { - nv_error(priv, "GPC%i: unknown stat %08x\n", - gpc, stat); - } - } -} - - -static void -nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst, - struct nouveau_object *engctx) -{ - u32 trap = nv_rd32(priv, 0x400108); - int i; - int rop; - - if (trap & 0x00000001) { - u32 stat = nv_rd32(priv, 0x404000); - nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n", - chid, inst, nouveau_client_name(engctx), stat); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000001); - trap &= ~0x00000001; - } - - if (trap & 0x00000010) { - u32 stat = nv_rd32(priv, 0x405840); - nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n", - chid, inst, nouveau_client_name(engctx), stat); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000010); - trap &= ~0x00000010; - } - - if (trap & 0x00000100) { - u32 stat = nv_rd32(priv, 0x407020); - nv_error(priv, "SKED ch %d [0x%010llx %s]:", - chid, inst, nouveau_client_name(engctx)); - - for (i = 0; i <= 29; ++i) { - if (!(stat & (1 << i))) - continue; - pr_cont(" "); - nouveau_enum_print(nve0_sked_error, i); - } - pr_cont("\n"); - - if (stat & 0x3fffffff) - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x400108, 0x00000100); - trap &= ~0x00000100; - } - - if (trap & 0x01000000) { - nv_error(priv, "GPC ch %d [0x%010llx %s]:\n", - chid, inst, nouveau_client_name(engctx)); - nve0_graph_gpc_trap(priv); - trap &= ~0x01000000; - } - - if (trap & 0x02000000) { - for (rop = 0; rop < priv->rop_nr; rop++) { - u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); - u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); - nv_error(priv, - "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n", - rop, chid, inst, nouveau_client_name(engctx), - statz, statc); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - } - nv_wr32(priv, 0x400108, 0x02000000); - trap &= ~0x02000000; - } - - if (trap) { - nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n", - chid, inst, nouveau_client_name(engctx), trap); - nv_wr32(priv, 0x400108, trap); - } -} - -static void -nve0_graph_intr(struct nouveau_subdev *subdev) -{ - struct nouveau_fifo *pfifo = nouveau_fifo(subdev); - struct nouveau_engine *engine = nv_engine(subdev); - struct nouveau_object *engctx; - struct nouveau_handle *handle; - struct nvc0_graph_priv *priv = (void *)subdev; - u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; - u32 stat = nv_rd32(priv, 0x400100); - u32 addr = nv_rd32(priv, 0x400704); - u32 mthd = (addr & 0x00003ffc); - u32 subc = (addr & 0x00070000) >> 16; - u32 data = nv_rd32(priv, 0x400708); - u32 code = nv_rd32(priv, 0x400110); - u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); - int chid; - - engctx = nouveau_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); - - if (stat & 0x00000010) { - handle = nouveau_handle_get_class(engctx, class); - if (!handle || nv_call(handle->object, mthd, data)) { - nv_error(priv, - "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst, nouveau_client_name(engctx), subc, - class, mthd, data); - } - nouveau_handle_put(handle); - nv_wr32(priv, 0x400100, 0x00000010); - stat &= ~0x00000010; - } - - if (stat & 0x00000020) { - nv_error(priv, - "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst, nouveau_client_name(engctx), subc, class, - mthd, data); - nv_wr32(priv, 0x400100, 0x00000020); - stat &= ~0x00000020; - } - - if (stat & 0x00100000) { - nv_error(priv, "DATA_ERROR ["); - nouveau_enum_print(nv50_data_error_names, code); - pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst, nouveau_client_name(engctx), subc, class, - mthd, data); - nv_wr32(priv, 0x400100, 0x00100000); - stat &= ~0x00100000; - } - - if (stat & 0x00200000) { - nve0_graph_trap_isr(priv, chid, inst, engctx); - nv_wr32(priv, 0x400100, 0x00200000); - stat &= ~0x00200000; - } - - if (stat & 0x00080000) { - nve0_graph_ctxctl_isr(priv); - nv_wr32(priv, 0x400100, 0x00080000); - stat &= ~0x00080000; - } - - if (stat) { - nv_error(priv, "unknown stat 0x%08x\n", stat); - nv_wr32(priv, 0x400100, stat); - } - - nv_wr32(priv, 0x400500, 0x00010001); - nouveau_engctx_put(engctx); -} - -static int -nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_device *device = nv_device(parent); - struct nvc0_graph_priv *priv; - int ret, i; - - ret = nouveau_graph_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x18001000; - nv_subdev(priv)->intr = nve0_graph_intr; - nv_engine(priv)->cclass = &nve0_graph_cclass; - nv_engine(priv)->sclass = nve0_graph_sclass; - - priv->base.units = nvc0_graph_units; - - if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) { - nv_info(priv, "using external firmware\n"); - if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) - return -EINVAL; - priv->firmware = true; - } - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b4); - if (ret) - return ret; - - ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b8); - if (ret) - return ret; - - for (i = 0; i < 0x1000; i += 4) { - nv_wo32(priv->unk4188b4, i, 0x00000010); - nv_wo32(priv->unk4188b8, i, 0x00000010); - } - - priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; - priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; - for (i = 0; i < priv->gpc_nr; i++) { - priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); - priv->tpc_total += priv->tpc_nr[i]; - } - - switch (nv_device(priv)->chipset) { - case 0xe4: - if (priv->tpc_total == 8) - priv->magic_not_rop_nr = 3; - else - if (priv->tpc_total == 7) - priv->magic_not_rop_nr = 1; - break; - case 0xe7: - case 0xe6: - priv->magic_not_rop_nr = 1; - break; - case 0xf0: - default: - break; - } - - return 0; -} - -static void -nve0_graph_init_obj418880(struct nvc0_graph_priv *priv) -{ - int i; - - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - for (i = 0; i < 4; i++) - nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); -} - -static void -nve0_graph_init_regs(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x400080, 0x003083c2); - nv_wr32(priv, 0x400088, 0x0001ffe7); - nv_wr32(priv, 0x40008c, 0x00000000); - nv_wr32(priv, 0x400090, 0x00000030); - nv_wr32(priv, 0x40013c, 0x003901f7); - nv_wr32(priv, 0x400140, 0x00000100); - nv_wr32(priv, 0x400144, 0x00000000); - nv_wr32(priv, 0x400148, 0x00000110); - nv_wr32(priv, 0x400138, 0x00000000); - nv_wr32(priv, 0x400130, 0x00000000); - nv_wr32(priv, 0x400134, 0x00000000); - nv_wr32(priv, 0x400124, 0x00000002); -} - -static void -nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40415c, 0x00000000); - nv_wr32(priv, 0x404170, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x4041b4, 0x00000000); - break; - default: - break; - } -} - -static void -nve0_graph_init_unk44xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x404488, 0x00000000); - nv_wr32(priv, 0x40448c, 0x00000000); -} - -static void -nve0_graph_init_unk78xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x407808, 0x00000000); -} - -static void -nve0_graph_init_unk60xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x406024, 0x00000000); -} - -static void -nve0_graph_init_unk64xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x4064f0, 0x00000000); - nv_wr32(priv, 0x4064f4, 0x00000000); - nv_wr32(priv, 0x4064f8, 0x00000000); -} - -static void -nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_wr32(priv, 0x405850, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x405900, 0x0000ff00); - break; - default: - nv_wr32(priv, 0x405900, 0x0000ff34); - break; - } - nv_wr32(priv, 0x405908, 0x00000000); - nv_wr32(priv, 0x405928, 0x00000000); - nv_wr32(priv, 0x40592c, 0x00000000); -} - -static void -nve0_graph_init_unk80xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40803c, 0x00000000); -} - -static void -nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x407010, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x407040, 0x80440424); - nv_wr32(priv, 0x407048, 0x0000000a); - break; - default: - break; - } -} - -static void -nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv) -{ - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x505b44, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x405b50, 0x00000000); -} - -static void -nve0_graph_init_gpc(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x418408, 0x00000000); - nv_wr32(priv, 0x4184a0, 0x00000000); - nv_wr32(priv, 0x4184a4, 0x00000000); - nv_wr32(priv, 0x4184a8, 0x00000000); - nv_wr32(priv, 0x418604, 0x00000000); - nv_wr32(priv, 0x418680, 0x00000000); - nv_wr32(priv, 0x418714, 0x00000000); - nv_wr32(priv, 0x418384, 0x00000000); - nv_wr32(priv, 0x418814, 0x00000000); - nv_wr32(priv, 0x418818, 0x00000000); - nv_wr32(priv, 0x41881c, 0x00000000); - nv_wr32(priv, 0x418b04, 0x00000000); - nv_wr32(priv, 0x4188c8, 0x00000000); - nv_wr32(priv, 0x4188cc, 0x00000000); - nv_wr32(priv, 0x4188d0, 0x00010000); - nv_wr32(priv, 0x4188d4, 0x00000001); - nv_wr32(priv, 0x418910, 0x00010001); - nv_wr32(priv, 0x418914, 0x00000301); - nv_wr32(priv, 0x418918, 0x00800000); - nv_wr32(priv, 0x418980, 0x77777770); - nv_wr32(priv, 0x418984, 0x77777777); - nv_wr32(priv, 0x418988, 0x77777777); - nv_wr32(priv, 0x41898c, 0x77777777); - nv_wr32(priv, 0x418c04, 0x00000000); - nv_wr32(priv, 0x418c64, 0x00000000); - nv_wr32(priv, 0x418c68, 0x00000000); - nv_wr32(priv, 0x418c88, 0x00000000); - nv_wr32(priv, 0x418cb4, 0x00000000); - nv_wr32(priv, 0x418cb8, 0x00000000); - nv_wr32(priv, 0x418d00, 0x00000000); - nv_wr32(priv, 0x418d28, 0x00000000); - nv_wr32(priv, 0x418d2c, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x418f00, 0x00000400); - break; - default: - nv_wr32(priv, 0x418f00, 0x00000000); - break; - } - nv_wr32(priv, 0x418f08, 0x00000000); - nv_wr32(priv, 0x418f20, 0x00000000); - nv_wr32(priv, 0x418f24, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x418e00, 0x00000000); - break; - default: - nv_wr32(priv, 0x418e00, 0x00000060); - break; - } - nv_wr32(priv, 0x418e08, 0x00000000); - nv_wr32(priv, 0x418e1c, 0x00000000); - nv_wr32(priv, 0x418e20, 0x00000000); - nv_wr32(priv, 0x41900c, 0x00000000); - nv_wr32(priv, 0x419018, 0x00000000); -} - -static void -nve0_graph_init_tpc(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x419d0c, 0x00000000); - nv_wr32(priv, 0x419d10, 0x00000014); - nv_wr32(priv, 0x419ab0, 0x00000000); - nv_wr32(priv, 0x419ac8, 0x00000000); - nv_wr32(priv, 0x419ab8, 0x000000e7); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419aec, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x419abc, 0x00000000); - nv_wr32(priv, 0x419ac0, 0x00000000); - nv_wr32(priv, 0x419ab4, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419aa8, 0x00000000); - nv_wr32(priv, 0x419aac, 0x00000000); - break; - default: - break; - } - nv_wr32(priv, 0x41980c, 0x00000010); - nv_wr32(priv, 0x419844, 0x00000000); - nv_wr32(priv, 0x419850, 0x00000004); - nv_wr32(priv, 0x419854, 0x00000000); - nv_wr32(priv, 0x419858, 0x00000000); - nv_wr32(priv, 0x419c98, 0x00000000); - nv_wr32(priv, 0x419ca8, 0x00000000); - nv_wr32(priv, 0x419cb0, 0x01000000); - nv_wr32(priv, 0x419cb4, 0x00000000); - nv_wr32(priv, 0x419cb8, 0x00b08bea); - nv_wr32(priv, 0x419c84, 0x00010384); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419cbc, 0x281b3646); - break; - default: - nv_wr32(priv, 0x419cbc, 0x28137646); - break; - } - nv_wr32(priv, 0x419cc0, 0x00000000); - nv_wr32(priv, 0x419cc4, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419c80, 0x00020230); - nv_wr32(priv, 0x419ccc, 0x00000000); - nv_wr32(priv, 0x419cd0, 0x00000000); - nv_wr32(priv, 0x419c0c, 0x00000000); - nv_wr32(priv, 0x419e00, 0x00000080); - break; - default: - nv_wr32(priv, 0x419c80, 0x00020232); - nv_wr32(priv, 0x419c0c, 0x00000000); - nv_wr32(priv, 0x419e00, 0x00000000); - break; - } - nv_wr32(priv, 0x419ea0, 0x00000000); - nv_wr32(priv, 0x419ee4, 0x00000000); - nv_wr32(priv, 0x419ea4, 0x00000100); - nv_wr32(priv, 0x419ea8, 0x00000000); - nv_wr32(priv, 0x419eb4, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - break; - default: - nv_wr32(priv, 0x419eb8, 0x00000000); - break; - } - nv_wr32(priv, 0x419ebc, 0x00000000); - nv_wr32(priv, 0x419ec0, 0x00000000); - nv_wr32(priv, 0x419edc, 0x00000000); - nv_wr32(priv, 0x419f00, 0x00000000); - switch (nv_device(priv)->chipset) { - case 0xf0: - nv_wr32(priv, 0x419ed0, 0x00003234); - nv_wr32(priv, 0x419f74, 0x00015555); - nv_wr32(priv, 0x419f80, 0x00000000); - nv_wr32(priv, 0x419f84, 0x00000000); - nv_wr32(priv, 0x419f88, 0x00000000); - nv_wr32(priv, 0x419f8c, 0x00000000); - break; - default: - nv_wr32(priv, 0x419f74, 0x00000555); - break; - } -} - -static void -nve0_graph_init_tpcunk(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x41be04, 0x00000000); - nv_wr32(priv, 0x41be08, 0x00000004); - nv_wr32(priv, 0x41be0c, 0x00000000); - nv_wr32(priv, 0x41be10, 0x003b8bc7); - nv_wr32(priv, 0x41be14, 0x00000000); - nv_wr32(priv, 0x41be18, 0x00000000); - nv_wr32(priv, 0x41bfd4, 0x00800000); - nv_wr32(priv, 0x41bfdc, 0x00000000); - nv_wr32(priv, 0x41bff8, 0x00000000); - nv_wr32(priv, 0x41bffc, 0x00000000); - nv_wr32(priv, 0x41becc, 0x00000000); - nv_wr32(priv, 0x41bee8, 0x00000000); - nv_wr32(priv, 0x41beec, 0x00000000); -} - -static void -nve0_graph_init_unk88xx(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x40880c, 0x00000000); - nv_wr32(priv, 0x408850, 0x00000004); - nv_wr32(priv, 0x408910, 0x00000000); - nv_wr32(priv, 0x408914, 0x00000000); - nv_wr32(priv, 0x408918, 0x00000000); - nv_wr32(priv, 0x40891c, 0x00000000); - nv_wr32(priv, 0x408920, 0x00000000); - nv_wr32(priv, 0x408924, 0x00000000); - nv_wr32(priv, 0x408928, 0x00000000); - nv_wr32(priv, 0x40892c, 0x00000000); - nv_wr32(priv, 0x408930, 0x00000000); - nv_wr32(priv, 0x408950, 0x00000000); - nv_wr32(priv, 0x408954, 0x0000ffff); - nv_wr32(priv, 0x408958, 0x00000034); - nv_wr32(priv, 0x408984, 0x00000000); - nv_wr32(priv, 0x408988, 0x08040201); - nv_wr32(priv, 0x40898c, 0x80402010); -} - -static void -nve0_graph_init_units(struct nvc0_graph_priv *priv) -{ - nv_wr32(priv, 0x409ffc, 0x00000000); - nv_wr32(priv, 0x409c14, 0x00003e3e); - switch (nv_device(priv)->chipset) { - case 0xe4: - case 0xe7: - case 0xe6: - nv_wr32(priv, 0x409c24, 0x000f0001); - break; - case 0xf0: - nv_wr32(priv, 0x409c24, 0x000f0000); - break; - } - - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); - -} - -static void -nve0_graph_init_gpc_0(struct nvc0_graph_priv *priv) -{ - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); - u32 data[TPC_MAX / 8]; - u8 tpcnr[GPC_MAX]; - int i, gpc, tpc; - - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); - - memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { - do { - gpc = (gpc + 1) % priv->gpc_nr; - } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; - - data[i / 8] |= tpc << ((i % 8) * 4); - } - - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | - priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); - } - - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); -} - -static void -nve0_graph_init_gpc_1(struct nvc0_graph_priv *priv) -{ - int gpc, tpc; - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); - } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); - } -} - -static void -nve0_graph_init_rop(struct nvc0_graph_priv *priv) -{ - int rop; - - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); - } -} - -static int -nve0_graph_init_ctxctl(struct nvc0_graph_priv *priv) -{ - u32 r000260; - int i; - - if (priv->firmware) { - /* load fuc microcode */ - r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); - nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, &priv->fuc409d); - nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, &priv->fuc41ad); - nv_wr32(priv, 0x000260, r000260); - - /* start both of them running */ - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x41a10c, 0x00000000); - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x41a100, 0x00000002); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) - nv_error(priv, "0x409800 wait failed\n"); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x7fffffff); - nv_wr32(priv, 0x409504, 0x00000021); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000010); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x10 timeout\n"); - return -EBUSY; - } - priv->size = nv_rd32(priv, 0x409800); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000016); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x16 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000025); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x25 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000030); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x30 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409810, 0xb00095c8); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000031); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x31 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409810, 0x00080420); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000032); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x32 timeout\n"); - return -EBUSY; - } - - nv_wr32(priv, 0x409614, 0x00000070); - nv_wr32(priv, 0x409614, 0x00000770); - nv_wr32(priv, 0x40802c, 0x00000001); - - if (priv->data == NULL) { - int ret = nve0_grctx_generate(priv); - if (ret) { - nv_error(priv, "failed to construct context\n"); - return ret; - } - } - - return 0; - } - - /* load HUB microcode */ - r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000); - nv_wr32(priv, 0x4091c0, 0x01000000); - for (i = 0; i < sizeof(nve0_grhub_data) / 4; i++) - nv_wr32(priv, 0x4091c4, nve0_grhub_data[i]); - - nv_wr32(priv, 0x409180, 0x01000000); - for (i = 0; i < sizeof(nve0_grhub_code) / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(priv, 0x409188, i >> 6); - nv_wr32(priv, 0x409184, nve0_grhub_code[i]); - } - - /* load GPC microcode */ - nv_wr32(priv, 0x41a1c0, 0x01000000); - for (i = 0; i < sizeof(nve0_grgpc_data) / 4; i++) - nv_wr32(priv, 0x41a1c4, nve0_grgpc_data[i]); - - nv_wr32(priv, 0x41a180, 0x01000000); - for (i = 0; i < sizeof(nve0_grgpc_code) / 4; i++) { - if ((i & 0x3f) == 0) - nv_wr32(priv, 0x41a188, i >> 6); - nv_wr32(priv, 0x41a184, nve0_grgpc_code[i]); - } - nv_wr32(priv, 0x000260, r000260); - - /* start HUB ucode running, it'll init the GPCs */ - nv_wr32(priv, 0x409800, nv_device(priv)->chipset); - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { - nv_error(priv, "HUB_INIT timed out\n"); - nvc0_graph_ctxctl_debug(priv); - return -EBUSY; - } - - priv->size = nv_rd32(priv, 0x409804); - if (priv->data == NULL) { - int ret = nve0_grctx_generate(priv); - if (ret) { - nv_error(priv, "failed to construct context\n"); - return ret; - } - } - - return 0; -} - -static int -nve0_graph_init(struct nouveau_object *object) -{ - struct nvc0_graph_priv *priv = (void *)object; - int ret; - - ret = nouveau_graph_init(&priv->base); - if (ret) - return ret; - - nve0_graph_init_obj418880(priv); - nve0_graph_init_regs(priv); - nve0_graph_init_unk40xx(priv); - nve0_graph_init_unk44xx(priv); - nve0_graph_init_unk78xx(priv); - nve0_graph_init_unk60xx(priv); - nve0_graph_init_unk64xx(priv); - nve0_graph_init_unk58xx(priv); - nve0_graph_init_unk80xx(priv); - nve0_graph_init_unk70xx(priv); - nve0_graph_init_unk5bxx(priv); - nve0_graph_init_gpc(priv); - nve0_graph_init_tpc(priv); - nve0_graph_init_tpcunk(priv); - nve0_graph_init_unk88xx(priv); - nve0_graph_init_gpc_0(priv); - - nv_wr32(priv, 0x400500, 0x00010001); - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - - nve0_graph_init_units(priv); - nve0_graph_init_gpc_1(priv); - nve0_graph_init_rop(priv); - - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); - nv_wr32(priv, 0x400054, 0x34ce3464); - - ret = nve0_graph_init_ctxctl(priv); - if (ret) - return ret; - - return 0; -} - -struct nouveau_oclass -nve0_graph_oclass = { - .handle = NV_ENGINE(GR, 0xe0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_graph_ctor, - .dtor = nvc0_graph_dtor, - .init = nve0_graph_init, - .fini = _nouveau_graph_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c new file mode 100644 index 000000000000..05ec09c88517 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c @@ -0,0 +1,354 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nve4_graph_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa040, &nouveau_object_ofuncs }, + { 0xa097, &nouveau_object_ofuncs }, + { 0xa0c0, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +struct nvc0_graph_init +nve4_graph_init_regs[] = { + { 0x400080, 1, 0x04, 0x003083c2 }, + { 0x400088, 1, 0x04, 0x0001ffe7 }, + { 0x40008c, 1, 0x04, 0x00000000 }, + { 0x400090, 1, 0x04, 0x00000030 }, + { 0x40013c, 1, 0x04, 0x003901f7 }, + { 0x400140, 1, 0x04, 0x00000100 }, + { 0x400144, 1, 0x04, 0x00000000 }, + { 0x400148, 1, 0x04, 0x00000110 }, + { 0x400138, 1, 0x04, 0x00000000 }, + { 0x400130, 2, 0x04, 0x00000000 }, + { 0x400124, 1, 0x04, 0x00000002 }, + {} +}; + +static struct nvc0_graph_init +nve4_graph_init_unk58xx[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x0000ff34 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 1, 0x04, 0x00000000 }, + { 0x40592c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_graph_init_unk70xx[] = { + { 0x407010, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_graph_init_unk5bxx[] = { + { 0x405b50, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_graph_init_gpc[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x4184a4, 2, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c64, 1, 0x04, 0x00000000 }, + { 0x418c68, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418cb4, 2, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 1, 0x04, 0x00000000 }, + { 0x418d2c, 1, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000000 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 2, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000060 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 1, 0x04, 0x00000000 }, + { 0x418e20, 1, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nve4_graph_init_tpc[] = { + { 0x419d0c, 1, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x419850, 1, 0x04, 0x00000004 }, + { 0x419854, 2, 0x04, 0x00000000 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x01000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x28137646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00020232 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000000 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00000000 }, + { 0x419eb4, 1, 0x04, 0x00000000 }, + { 0x419eb8, 3, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419f74, 1, 0x04, 0x00000555 }, + {} +}; + +struct nvc0_graph_init +nve4_graph_init_unk[] = { + { 0x41be04, 1, 0x04, 0x00000000 }, + { 0x41be08, 1, 0x04, 0x00000004 }, + { 0x41be0c, 1, 0x04, 0x00000000 }, + { 0x41be10, 1, 0x04, 0x003b8bc7 }, + { 0x41be14, 2, 0x04, 0x00000000 }, + { 0x41bfd4, 1, 0x04, 0x00800000 }, + { 0x41bfdc, 1, 0x04, 0x00000000 }, + { 0x41bff8, 1, 0x04, 0x00000000 }, + { 0x41bffc, 1, 0x04, 0x00000000 }, + { 0x41becc, 1, 0x04, 0x00000000 }, + { 0x41bee8, 1, 0x04, 0x00000000 }, + { 0x41beec, 1, 0x04, 0x00000000 }, + {} +}; + +struct nvc0_graph_init +nve4_graph_init_unk88xx[] = { + { 0x40880c, 1, 0x04, 0x00000000 }, + { 0x408850, 1, 0x04, 0x00000004 }, + { 0x408910, 9, 0x04, 0x00000000 }, + { 0x408950, 1, 0x04, 0x00000000 }, + { 0x408954, 1, 0x04, 0x0000ffff }, + { 0x408958, 1, 0x04, 0x00000034 }, + { 0x408984, 1, 0x04, 0x00000000 }, + { 0x408988, 1, 0x04, 0x08040201 }, + { 0x40898c, 1, 0x04, 0x80402010 }, + {} +}; + +int +nve4_graph_init(struct nouveau_object *object) +{ + struct nvc0_graph_oclass *oclass = (void *)object->oclass; + struct nvc0_graph_priv *priv = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc, rop; + int ret, i; + + ret = nouveau_graph_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); + nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + + for (i = 0; oclass->mmio[i]; i++) + nvc0_graph_mmio(priv, oclass->mmio[i]); + + nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + + memset(data, 0x00, sizeof(data)); + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); + + nv_wr32(priv, 0x400500, 0x00010001); + + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + + nv_wr32(priv, 0x409ffc, 0x00000000); + nv_wr32(priv, 0x409c14, 0x00003e3e); + nv_wr32(priv, 0x409c24, 0x000f0001); + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(priv, 0x408030, 0xc0000000); + nv_wr32(priv, 0x404490, 0xc0000000); + nv_wr32(priv, 0x406018, 0xc0000000); + nv_wr32(priv, 0x407020, 0x40000000); + nv_wr32(priv, 0x405840, 0xc0000000); + nv_wr32(priv, 0x405844, 0x00ffffff); + nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + } + nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + } + + for (rop = 0; rop < priv->rop_nr; rop++) { + nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + } + + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400118, 0xffffffff); + nv_wr32(priv, 0x400130, 0xffffffff); + nv_wr32(priv, 0x40011c, 0xffffffff); + nv_wr32(priv, 0x400134, 0xffffffff); + + nv_wr32(priv, 0x400054, 0x34ce3464); + return nvc0_graph_init_ctxctl(priv); +} + +static struct nvc0_graph_init * +nve4_graph_init_mmio[] = { + nve4_graph_init_regs, + nvc0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvd9_graph_init_unk64xx, + nve4_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nve4_graph_init_unk70xx, + nve4_graph_init_unk5bxx, + nve4_graph_init_gpc, + nve4_graph_init_tpc, + nve4_graph_init_unk, + nve4_graph_init_unk88xx, + NULL +}; + +#include "fuc/hubnve0.fuc.h" + +static struct nvc0_graph_ucode +nve4_graph_fecs_ucode = { + .code.data = nve0_grhub_code, + .code.size = sizeof(nve0_grhub_code), + .data.data = nve0_grhub_data, + .data.size = sizeof(nve0_grhub_data), +}; + +#include "fuc/gpcnve0.fuc.h" + +static struct nvc0_graph_ucode +nve4_graph_gpccs_ucode = { + .code.data = nve0_grgpc_code, + .code.size = sizeof(nve0_grgpc_code), + .data.data = nve0_grgpc_data, + .data.size = sizeof(nve0_grgpc_data), +}; + +struct nouveau_oclass * +nve4_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xe4), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nve4_graph_init, + .fini = _nouveau_graph_fini, + }, + .cclass = &nve4_grctx_oclass, + .sclass = nve4_graph_sclass, + .mmio = nve4_graph_init_mmio, + .fecs.ucode = &nve4_graph_fecs_ucode, + .gpccs.ucode = &nve4_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c new file mode 100644 index 000000000000..2f0ac7832234 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c @@ -0,0 +1,248 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ + +#include "nvc0.h" + +/******************************************************************************* + * Graphics object classes + ******************************************************************************/ + +static struct nouveau_oclass +nvf0_graph_sclass[] = { + { 0x902d, &nouveau_object_ofuncs }, + { 0xa140, &nouveau_object_ofuncs }, + { 0xa197, &nouveau_object_ofuncs }, + { 0xa1c0, &nouveau_object_ofuncs }, + {} +}; + +/******************************************************************************* + * PGRAPH engine/subdev functions + ******************************************************************************/ + +static struct nvc0_graph_init +nvf0_graph_init_unk40xx[] = { + { 0x40415c, 1, 0x04, 0x00000000 }, + { 0x404170, 1, 0x04, 0x00000000 }, + { 0x4041b4, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvf0_graph_init_unk58xx[] = { + { 0x405844, 1, 0x04, 0x00ffffff }, + { 0x405850, 1, 0x04, 0x00000000 }, + { 0x405900, 1, 0x04, 0x0000ff00 }, + { 0x405908, 1, 0x04, 0x00000000 }, + { 0x405928, 1, 0x04, 0x00000000 }, + { 0x40592c, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvf0_graph_init_unk70xx[] = { + { 0x407010, 1, 0x04, 0x00000000 }, + { 0x407040, 1, 0x04, 0x80440424 }, + { 0x407048, 1, 0x04, 0x0000000a }, + {} +}; + +static struct nvc0_graph_init +nvf0_graph_init_unk5bxx[] = { + { 0x405b44, 1, 0x04, 0x00000000 }, + { 0x405b50, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvf0_graph_init_gpc[] = { + { 0x418408, 1, 0x04, 0x00000000 }, + { 0x4184a0, 1, 0x04, 0x00000000 }, + { 0x4184a4, 2, 0x04, 0x00000000 }, + { 0x418604, 1, 0x04, 0x00000000 }, + { 0x418680, 1, 0x04, 0x00000000 }, + { 0x418714, 1, 0x04, 0x00000000 }, + { 0x418384, 1, 0x04, 0x00000000 }, + { 0x418814, 3, 0x04, 0x00000000 }, + { 0x418b04, 1, 0x04, 0x00000000 }, + { 0x4188c8, 2, 0x04, 0x00000000 }, + { 0x4188d0, 1, 0x04, 0x00010000 }, + { 0x4188d4, 1, 0x04, 0x00000001 }, + { 0x418910, 1, 0x04, 0x00010001 }, + { 0x418914, 1, 0x04, 0x00000301 }, + { 0x418918, 1, 0x04, 0x00800000 }, + { 0x418980, 1, 0x04, 0x77777770 }, + { 0x418984, 3, 0x04, 0x77777777 }, + { 0x418c04, 1, 0x04, 0x00000000 }, + { 0x418c64, 1, 0x04, 0x00000000 }, + { 0x418c68, 1, 0x04, 0x00000000 }, + { 0x418c88, 1, 0x04, 0x00000000 }, + { 0x418cb4, 2, 0x04, 0x00000000 }, + { 0x418d00, 1, 0x04, 0x00000000 }, + { 0x418d28, 1, 0x04, 0x00000000 }, + { 0x418d2c, 1, 0x04, 0x00000000 }, + { 0x418f00, 1, 0x04, 0x00000400 }, + { 0x418f08, 1, 0x04, 0x00000000 }, + { 0x418f20, 1, 0x04, 0x00000000 }, + { 0x418f24, 1, 0x04, 0x00000000 }, + { 0x418e00, 1, 0x04, 0x00000000 }, + { 0x418e08, 1, 0x04, 0x00000000 }, + { 0x418e1c, 2, 0x04, 0x00000000 }, + { 0x41900c, 1, 0x04, 0x00000000 }, + { 0x419018, 1, 0x04, 0x00000000 }, + {} +}; + +static struct nvc0_graph_init +nvf0_graph_init_tpc[] = { + { 0x419d0c, 1, 0x04, 0x00000000 }, + { 0x419d10, 1, 0x04, 0x00000014 }, + { 0x419ab0, 1, 0x04, 0x00000000 }, + { 0x419ac8, 1, 0x04, 0x00000000 }, + { 0x419ab8, 1, 0x04, 0x000000e7 }, + { 0x419aec, 1, 0x04, 0x00000000 }, + { 0x419abc, 2, 0x04, 0x00000000 }, + { 0x419ab4, 1, 0x04, 0x00000000 }, + { 0x419aa8, 2, 0x04, 0x00000000 }, + { 0x41980c, 1, 0x04, 0x00000010 }, + { 0x419844, 1, 0x04, 0x00000000 }, + { 0x419850, 1, 0x04, 0x00000004 }, + { 0x419854, 2, 0x04, 0x00000000 }, + { 0x419c98, 1, 0x04, 0x00000000 }, + { 0x419ca8, 1, 0x04, 0x00000000 }, + { 0x419cb0, 1, 0x04, 0x01000000 }, + { 0x419cb4, 1, 0x04, 0x00000000 }, + { 0x419cb8, 1, 0x04, 0x00b08bea }, + { 0x419c84, 1, 0x04, 0x00010384 }, + { 0x419cbc, 1, 0x04, 0x281b3646 }, + { 0x419cc0, 2, 0x04, 0x00000000 }, + { 0x419c80, 1, 0x04, 0x00020230 }, + { 0x419ccc, 2, 0x04, 0x00000000 }, + { 0x419c0c, 1, 0x04, 0x00000000 }, + { 0x419e00, 1, 0x04, 0x00000080 }, + { 0x419ea0, 1, 0x04, 0x00000000 }, + { 0x419ee4, 1, 0x04, 0x00000000 }, + { 0x419ea4, 1, 0x04, 0x00000100 }, + { 0x419ea8, 1, 0x04, 0x00000000 }, + { 0x419eb4, 1, 0x04, 0x00000000 }, + { 0x419ebc, 2, 0x04, 0x00000000 }, + { 0x419edc, 1, 0x04, 0x00000000 }, + { 0x419f00, 1, 0x04, 0x00000000 }, + { 0x419ed0, 1, 0x04, 0x00003234 }, + { 0x419f74, 1, 0x04, 0x00015555 }, + { 0x419f80, 4, 0x04, 0x00000000 }, + {} +}; + +static int +nvf0_graph_fini(struct nouveau_object *object, bool suspend) +{ + struct nvc0_graph_priv *priv = (void *)object; + static const struct { + u32 addr; + u32 data; + } magic[] = { + { 0x020520, 0xfffffffc }, + { 0x020524, 0xfffffffe }, + { 0x020524, 0xfffffffc }, + { 0x020524, 0xfffffff8 }, + { 0x020524, 0xffffffe0 }, + { 0x020530, 0xfffffffe }, + { 0x02052c, 0xfffffffa }, + { 0x02052c, 0xfffffff0 }, + { 0x02052c, 0xffffffc0 }, + { 0x02052c, 0xffffff00 }, + { 0x02052c, 0xfffffc00 }, + { 0x02052c, 0xfffcfc00 }, + { 0x02052c, 0xfff0fc00 }, + { 0x02052c, 0xff80fc00 }, + { 0x020528, 0xfffffffe }, + { 0x020528, 0xfffffffc }, + }; + int i; + + nv_mask(priv, 0x000200, 0x08001000, 0x00000000); + nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); + for (i = 0; i < ARRAY_SIZE(magic); i++) { + nv_wr32(priv, magic[i].addr, magic[i].data); + nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); + } + + return nouveau_graph_fini(&priv->base, suspend); +} + +static struct nvc0_graph_init * +nvf0_graph_init_mmio[] = { + nve4_graph_init_regs, + nvf0_graph_init_unk40xx, + nvc0_graph_init_unk44xx, + nvc0_graph_init_unk78xx, + nvc0_graph_init_unk60xx, + nvd9_graph_init_unk64xx, + nvf0_graph_init_unk58xx, + nvc0_graph_init_unk80xx, + nvf0_graph_init_unk70xx, + nvf0_graph_init_unk5bxx, + nvf0_graph_init_gpc, + nvf0_graph_init_tpc, + nve4_graph_init_unk, + nve4_graph_init_unk88xx, + NULL +}; + +#include "fuc/hubnvf0.fuc.h" + +static struct nvc0_graph_ucode +nvf0_graph_fecs_ucode = { + .code.data = nvf0_grhub_code, + .code.size = sizeof(nvf0_grhub_code), + .data.data = nvf0_grhub_data, + .data.size = sizeof(nvf0_grhub_data), +}; + +#include "fuc/gpcnvf0.fuc.h" + +static struct nvc0_graph_ucode +nvf0_graph_gpccs_ucode = { + .code.data = nvf0_grgpc_code, + .code.size = sizeof(nvf0_grgpc_code), + .data.data = nvf0_grgpc_data, + .data.size = sizeof(nvf0_grgpc_data), +}; + +struct nouveau_oclass * +nvf0_graph_oclass = &(struct nvc0_graph_oclass) { + .base.handle = NV_ENGINE(GR, 0xf0), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvc0_graph_ctor, + .dtor = nvc0_graph_dtor, + .init = nve4_graph_init, + .fini = nvf0_graph_fini, + }, + .cclass = &nvf0_grctx_oclass, + .sclass = nvf0_graph_sclass, + .mmio = nvf0_graph_init_mmio, + .fecs.ucode = 0 ? &nvf0_graph_fecs_ucode : NULL, + .gpccs.ucode = &nvf0_graph_gpccs_ucode, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h index 5d392439f2ac..8e1b52312ddc 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h @@ -61,8 +61,14 @@ extern struct nouveau_oclass nv34_graph_oclass; extern struct nouveau_oclass nv35_graph_oclass; extern struct nouveau_oclass nv40_graph_oclass; extern struct nouveau_oclass nv50_graph_oclass; -extern struct nouveau_oclass nvc0_graph_oclass; -extern struct nouveau_oclass nve0_graph_oclass; +extern struct nouveau_oclass *nvc0_graph_oclass; +extern struct nouveau_oclass *nvc1_graph_oclass; +extern struct nouveau_oclass *nvc3_graph_oclass; +extern struct nouveau_oclass *nvc8_graph_oclass; +extern struct nouveau_oclass *nvd7_graph_oclass; +extern struct nouveau_oclass *nvd9_graph_oclass; +extern struct nouveau_oclass *nve4_graph_oclass; +extern struct nouveau_oclass *nvf0_graph_oclass; extern const struct nouveau_bitfield nv04_graph_nsource[]; extern struct nouveau_ofuncs nv04_graph_ofuncs; diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c index af407a8637c7..19e265bf4574 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c @@ -80,7 +80,7 @@ nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass nvc0_devinit_oclass = { - .handle = NV_SUBDEV(DEVINIT, 0xa3), + .handle = NV_SUBDEV(DEVINIT, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_devinit_ctor, .dtor = _nouveau_devinit_dtor, diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c index 34d3fbfbd631..67fcb6c852ac 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c @@ -365,7 +365,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, vm->fpde = offset >> (vmm->pgt_bits + 12); vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); - vm->pgt = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); if (!vm->pgt) { kfree(vm); return -ENOMEM; @@ -374,7 +374,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, block >> 12); if (ret) { - kfree(vm->pgt); + vfree(vm->pgt); kfree(vm); return ret; } @@ -450,7 +450,7 @@ nouveau_vm_del(struct nouveau_vm *vm) } nouveau_mm_fini(&vm->mm); - kfree(vm->pgt); + vfree(vm->pgt); kfree(vm); } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index a1cf8255db50..4b1afb131380 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -968,7 +968,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); - struct nouveau_channel *chan = chan = drm->channel; + struct nouveau_channel *chan = chan = drm->ttm.chan; struct nouveau_bo *nvbo = nouveau_bo(bo); struct ttm_mem_reg *old_mem = &bo->mem; int ret; @@ -1052,6 +1052,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm) } drm->ttm.move = mthd->exec; + drm->ttm.chan = chan; name = mthd->name; break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h index f2b30f89dee0..41ff7e0d403a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -96,6 +96,7 @@ struct nouveau_drm { int (*move)(struct nouveau_channel *, struct ttm_buffer_object *, struct ttm_mem_reg *, struct ttm_mem_reg *); + struct nouveau_channel *chan; int mtrr; } ttm; diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index f86771481317..93c2f2cceb51 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -49,6 +49,11 @@ void qxl_ring_free(struct qxl_ring *ring) kfree(ring); } +void qxl_ring_init_hdr(struct qxl_ring *ring) +{ + ring->ring->header.notify_on_prod = ring->n_elements; +} + struct qxl_ring * qxl_ring_create(struct qxl_ring_header *header, int element_size, @@ -69,7 +74,7 @@ qxl_ring_create(struct qxl_ring_header *header, ring->prod_notify = prod_notify; ring->push_event = push_event; if (set_prod_notify) - header->notify_on_prod = ring->n_elements; + qxl_ring_init_hdr(ring); spin_lock_init(&ring->lock); return ring; } @@ -87,7 +92,7 @@ static int qxl_check_header(struct qxl_ring *ring) return ret; } -static int qxl_check_idle(struct qxl_ring *ring) +int qxl_check_idle(struct qxl_ring *ring) { int ret; struct qxl_ring_header *header = &(ring->ring->header); @@ -375,8 +380,8 @@ void qxl_io_destroy_primary(struct qxl_device *qdev) wait_for_io_cmd(qdev, 0, QXL_IO_DESTROY_PRIMARY_ASYNC); } -void qxl_io_create_primary(struct qxl_device *qdev, unsigned width, - unsigned height, unsigned offset, struct qxl_bo *bo) +void qxl_io_create_primary(struct qxl_device *qdev, + unsigned offset, struct qxl_bo *bo) { struct qxl_surface_create *create; @@ -384,8 +389,8 @@ void qxl_io_create_primary(struct qxl_device *qdev, unsigned width, qdev->ram_header); create = &qdev->ram_header->create_surface; create->format = bo->surf.format; - create->width = width; - create->height = height; + create->width = bo->surf.width; + create->height = bo->surf.height; create->stride = bo->surf.stride; create->mem = qxl_bo_physical_address(qdev, bo, offset); diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 686a937675cb..f76f5dd7bfc4 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -30,53 +30,9 @@ #include "qxl_object.h" #include "drm_crtc_helper.h" -static void qxl_crtc_set_to_mode(struct qxl_device *qdev, - struct drm_connector *connector, - struct qxl_head *head) +static bool qxl_head_enabled(struct qxl_head *head) { - struct drm_device *dev = connector->dev; - struct drm_display_mode *mode, *t; - int width = head->width; - int height = head->height; - - if (width < 320 || height < 240) { - qxl_io_log(qdev, "%s: bad head: %dx%d", width, height); - width = 1024; - height = 768; - } - if (width * height * 4 > 16*1024*1024) { - width = 1024; - height = 768; - } - /* TODO: go over regular modes and removed preferred? */ - list_for_each_entry_safe(mode, t, &connector->probed_modes, head) - drm_mode_remove(connector, mode); - mode = drm_cvt_mode(dev, width, height, 60, false, false, false); - mode->type |= DRM_MODE_TYPE_PREFERRED; - mode->status = MODE_OK; - drm_mode_probed_add(connector, mode); - qxl_io_log(qdev, "%s: %d x %d\n", __func__, width, height); -} - -void qxl_crtc_set_from_monitors_config(struct qxl_device *qdev) -{ - struct drm_connector *connector; - int i; - struct drm_device *dev = qdev->ddev; - - i = 0; - qxl_io_log(qdev, "%s: %d, %d\n", __func__, - dev->mode_config.num_connector, - qdev->monitors_config->count); - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - if (i > qdev->monitors_config->count) { - /* crtc will be reported as disabled */ - continue; - } - qxl_crtc_set_to_mode(qdev, connector, - &qdev->monitors_config->heads[i]); - ++i; - } + return head->width && head->height; } void qxl_alloc_client_monitors_config(struct qxl_device *qdev, unsigned count) @@ -106,7 +62,6 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) int num_monitors; uint32_t crc; - BUG_ON(!qdev->monitors_config); num_monitors = qdev->rom->client_monitors_config.count; crc = crc32(0, (const uint8_t *)&qdev->rom->client_monitors_config, sizeof(qdev->rom->client_monitors_config)); @@ -117,8 +72,8 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) return 1; } if (num_monitors > qdev->monitors_config->max_allowed) { - DRM_INFO("client monitors list will be truncated: %d < %d\n", - qdev->monitors_config->max_allowed, num_monitors); + DRM_DEBUG_KMS("client monitors list will be truncated: %d < %d\n", + qdev->monitors_config->max_allowed, num_monitors); num_monitors = qdev->monitors_config->max_allowed; } else { num_monitors = qdev->rom->client_monitors_config.count; @@ -132,18 +87,15 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) &qdev->rom->client_monitors_config.heads[i]; struct qxl_head *client_head = &qdev->client_monitors_config->heads[i]; - struct qxl_head *head = &qdev->monitors_config->heads[i]; - client_head->x = head->x = c_rect->left; - client_head->y = head->y = c_rect->top; - client_head->width = head->width = - c_rect->right - c_rect->left; - client_head->height = head->height = - c_rect->bottom - c_rect->top; - client_head->surface_id = head->surface_id = 0; - client_head->id = head->id = i; - client_head->flags = head->flags = 0; - QXL_DEBUG(qdev, "read %dx%d+%d+%d\n", head->width, head->height, - head->x, head->y); + client_head->x = c_rect->left; + client_head->y = c_rect->top; + client_head->width = c_rect->right - c_rect->left; + client_head->height = c_rect->bottom - c_rect->top; + client_head->surface_id = 0; + client_head->id = i; + client_head->flags = 0; + DRM_DEBUG_KMS("read %dx%d+%d+%d\n", client_head->width, client_head->height, + client_head->x, client_head->y); } return 0; } @@ -155,10 +107,7 @@ void qxl_display_read_client_monitors_config(struct qxl_device *qdev) qxl_io_log(qdev, "failed crc check for client_monitors_config," " retrying\n"); } - qxl_crtc_set_from_monitors_config(qdev); - /* fire off a uevent and let userspace tell us what to do */ - qxl_io_log(qdev, "calling drm_sysfs_hotplug_event\n"); - drm_sysfs_hotplug_event(qdev->ddev); + drm_helper_hpd_irq_event(qdev->ddev); } static int qxl_add_monitors_config_modes(struct drm_connector *connector) @@ -170,9 +119,9 @@ static int qxl_add_monitors_config_modes(struct drm_connector *connector) struct drm_display_mode *mode = NULL; struct qxl_head *head; - if (!qdev->monitors_config) + if (!qdev->client_monitors_config) return 0; - head = &qdev->monitors_config->heads[h]; + head = &qdev->client_monitors_config->heads[h]; mode = drm_cvt_mode(dev, head->width, head->height, 60, false, false, false); @@ -499,7 +448,7 @@ qxl_send_monitors_config(struct qxl_device *qdev) for (i = 0 ; i < qdev->monitors_config->count ; ++i) { struct qxl_head *head = &qdev->monitors_config->heads[i]; - if (head->y > 8192 || head->y < head->x || + if (head->y > 8192 || head->x > 8192 || head->width > 8192 || head->height > 8192) { DRM_ERROR("head %d wrong: %dx%d+%d+%d\n", i, head->width, head->height, @@ -510,16 +459,19 @@ qxl_send_monitors_config(struct qxl_device *qdev) qxl_io_monitors_config(qdev); } -static void qxl_monitors_config_set_single(struct qxl_device *qdev, - unsigned x, unsigned y, - unsigned width, unsigned height) +static void qxl_monitors_config_set(struct qxl_device *qdev, + int index, + unsigned x, unsigned y, + unsigned width, unsigned height, + unsigned surf_id) { - DRM_DEBUG("%dx%d+%d+%d\n", width, height, x, y); - qdev->monitors_config->count = 1; - qdev->monitors_config->heads[0].x = x; - qdev->monitors_config->heads[0].y = y; - qdev->monitors_config->heads[0].width = width; - qdev->monitors_config->heads[0].height = height; + DRM_DEBUG_KMS("%d:%dx%d+%d+%d\n", index, width, height, x, y); + qdev->monitors_config->heads[index].x = x; + qdev->monitors_config->heads[index].y = y; + qdev->monitors_config->heads[index].width = width; + qdev->monitors_config->heads[index].height = height; + qdev->monitors_config->heads[index].surface_id = surf_id; + } static int qxl_crtc_mode_set(struct drm_crtc *crtc, @@ -533,10 +485,11 @@ static int qxl_crtc_mode_set(struct drm_crtc *crtc, struct qxl_mode *m = (void *)mode->private; struct qxl_framebuffer *qfb; struct qxl_bo *bo, *old_bo = NULL; + struct qxl_crtc *qcrtc = to_qxl_crtc(crtc); uint32_t width, height, base_offset; bool recreate_primary = false; int ret; - + int surf_id; if (!crtc->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; @@ -560,7 +513,8 @@ static int qxl_crtc_mode_set(struct drm_crtc *crtc, adjusted_mode->hdisplay, adjusted_mode->vdisplay); - recreate_primary = true; + if (qcrtc->index == 0) + recreate_primary = true; width = mode->hdisplay; height = mode->vdisplay; @@ -581,8 +535,11 @@ static int qxl_crtc_mode_set(struct drm_crtc *crtc, "recreate primary: %dx%d (was %dx%d,%d,%d)\n", width, height, bo->surf.width, bo->surf.height, bo->surf.stride, bo->surf.format); - qxl_io_create_primary(qdev, width, height, base_offset, bo); + qxl_io_create_primary(qdev, base_offset, bo); bo->is_primary = true; + surf_id = 0; + } else { + surf_id = bo->surface_id; } if (old_bo && old_bo != bo) { @@ -592,11 +549,9 @@ static int qxl_crtc_mode_set(struct drm_crtc *crtc, qxl_bo_unreserve(old_bo); } - if (qdev->monitors_config->count == 0) { - qxl_monitors_config_set_single(qdev, x, y, - mode->hdisplay, - mode->vdisplay); - } + qxl_monitors_config_set(qdev, qcrtc->index, x, y, + mode->hdisplay, + mode->vdisplay, surf_id); return 0; } @@ -612,15 +567,36 @@ static void qxl_crtc_commit(struct drm_crtc *crtc) DRM_DEBUG("\n"); } +static void qxl_crtc_disable(struct drm_crtc *crtc) +{ + struct qxl_crtc *qcrtc = to_qxl_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct qxl_device *qdev = dev->dev_private; + if (crtc->fb) { + struct qxl_framebuffer *qfb = to_qxl_framebuffer(crtc->fb); + struct qxl_bo *bo = gem_to_qxl_bo(qfb->obj); + int ret; + ret = qxl_bo_reserve(bo, false); + qxl_bo_unpin(bo); + qxl_bo_unreserve(bo); + crtc->fb = NULL; + } + + qxl_monitors_config_set(qdev, qcrtc->index, 0, 0, 0, 0, 0); + + qxl_send_monitors_config(qdev); +} + static const struct drm_crtc_helper_funcs qxl_crtc_helper_funcs = { .dpms = qxl_crtc_dpms, + .disable = qxl_crtc_disable, .mode_fixup = qxl_crtc_mode_fixup, .mode_set = qxl_crtc_mode_set, .prepare = qxl_crtc_prepare, .commit = qxl_crtc_commit, }; -static int qdev_crtc_init(struct drm_device *dev, int num_crtc) +static int qdev_crtc_init(struct drm_device *dev, int crtc_id) { struct qxl_crtc *qxl_crtc; @@ -629,7 +605,7 @@ static int qdev_crtc_init(struct drm_device *dev, int num_crtc) return -ENOMEM; drm_crtc_init(dev, &qxl_crtc->base, &qxl_crtc_funcs); - + qxl_crtc->index = crtc_id; drm_mode_crtc_set_gamma_size(&qxl_crtc->base, 256); drm_crtc_helper_add(&qxl_crtc->base, &qxl_crtc_helper_funcs); return 0; @@ -657,18 +633,13 @@ static void qxl_write_monitors_config_for_encoder(struct qxl_device *qdev, struct drm_encoder *encoder) { int i; + struct qxl_output *output = drm_encoder_to_qxl_output(encoder); struct qxl_head *head; struct drm_display_mode *mode; BUG_ON(!encoder); /* TODO: ugly, do better */ - for (i = 0 ; (encoder->possible_crtcs != (1 << i)) && i < 32; ++i) - ; - if (encoder->possible_crtcs != (1 << i)) { - DRM_ERROR("encoder has wrong possible_crtcs: %x\n", - encoder->possible_crtcs); - return; - } + i = output->index; if (!qdev->monitors_config || qdev->monitors_config->max_allowed <= i) { DRM_ERROR( @@ -686,7 +657,6 @@ static void qxl_write_monitors_config_for_encoder(struct qxl_device *qdev, DRM_DEBUG("missing for multiple monitors: no head holes\n"); head = &qdev->monitors_config->heads[i]; head->id = i; - head->surface_id = 0; if (encoder->crtc->enabled) { mode = &encoder->crtc->mode; head->width = mode->hdisplay; @@ -701,8 +671,8 @@ static void qxl_write_monitors_config_for_encoder(struct qxl_device *qdev, head->x = 0; head->y = 0; } - DRM_DEBUG("setting head %d to +%d+%d %dx%d\n", - i, head->x, head->y, head->width, head->height); + DRM_DEBUG_KMS("setting head %d to +%d+%d %dx%d out of %d\n", + i, head->x, head->y, head->width, head->height, qdev->monitors_config->count); head->flags = 0; /* TODO - somewhere else to call this for multiple monitors * (config_commit?) */ @@ -797,8 +767,9 @@ static enum drm_connector_status qxl_conn_detect( /* The first monitor is always connected */ connected = (output->index == 0) || - (qdev->monitors_config && - qdev->monitors_config->count > output->index); + (qdev->client_monitors_config && + qdev->client_monitors_config->count > output->index && + qxl_head_enabled(&qdev->client_monitors_config->heads[output->index])); DRM_DEBUG("\n"); return connected ? connector_status_connected @@ -862,6 +833,8 @@ static int qdev_output_init(struct drm_device *dev, int num_output) drm_encoder_init(dev, &qxl_output->enc, &qxl_enc_funcs, DRM_MODE_ENCODER_VIRTUAL); + /* we get HPD via client monitors config */ + connector->polled = DRM_CONNECTOR_POLL_HPD; encoder->possible_crtcs = 1 << num_output; drm_mode_connector_attach_encoder(&qxl_output->base, &qxl_output->enc); @@ -901,16 +874,14 @@ static const struct drm_mode_config_funcs qxl_mode_funcs = { .fb_create = qxl_user_framebuffer_create, }; -int qxl_modeset_init(struct qxl_device *qdev) +int qxl_create_monitors_object(struct qxl_device *qdev) { - int i; int ret; struct drm_gem_object *gobj; - int max_allowed = QXL_NUM_OUTPUTS; + int max_allowed = qxl_num_crtc; int monitors_config_size = sizeof(struct qxl_monitors_config) + - max_allowed * sizeof(struct qxl_head); + max_allowed * sizeof(struct qxl_head); - drm_mode_config_init(qdev->ddev); ret = qxl_gem_object_create(qdev, monitors_config_size, 0, QXL_GEM_DOMAIN_VRAM, false, false, NULL, &gobj); @@ -919,13 +890,59 @@ int qxl_modeset_init(struct qxl_device *qdev) return -ENOMEM; } qdev->monitors_config_bo = gem_to_qxl_bo(gobj); + + ret = qxl_bo_reserve(qdev->monitors_config_bo, false); + if (ret) + return ret; + + ret = qxl_bo_pin(qdev->monitors_config_bo, QXL_GEM_DOMAIN_VRAM, NULL); + if (ret) { + qxl_bo_unreserve(qdev->monitors_config_bo); + return ret; + } + + qxl_bo_unreserve(qdev->monitors_config_bo); + qxl_bo_kmap(qdev->monitors_config_bo, NULL); + qdev->monitors_config = qdev->monitors_config_bo->kptr; qdev->ram_header->monitors_config = qxl_bo_physical_address(qdev, qdev->monitors_config_bo, 0); memset(qdev->monitors_config, 0, monitors_config_size); qdev->monitors_config->max_allowed = max_allowed; + return 0; +} + +int qxl_destroy_monitors_object(struct qxl_device *qdev) +{ + int ret; + + qdev->monitors_config = NULL; + qdev->ram_header->monitors_config = 0; + + qxl_bo_kunmap(qdev->monitors_config_bo); + ret = qxl_bo_reserve(qdev->monitors_config_bo, false); + if (ret) + return ret; + + qxl_bo_unpin(qdev->monitors_config_bo); + qxl_bo_unreserve(qdev->monitors_config_bo); + + qxl_bo_unref(&qdev->monitors_config_bo); + return 0; +} + +int qxl_modeset_init(struct qxl_device *qdev) +{ + int i; + int ret; + + drm_mode_config_init(qdev->ddev); + + ret = qxl_create_monitors_object(qdev); + if (ret) + return ret; qdev->ddev->mode_config.funcs = (void *)&qxl_mode_funcs; @@ -936,7 +953,7 @@ int qxl_modeset_init(struct qxl_device *qdev) qdev->ddev->mode_config.max_height = 8192; qdev->ddev->mode_config.fb_base = qdev->vram_base; - for (i = 0 ; i < QXL_NUM_OUTPUTS; ++i) { + for (i = 0 ; i < qxl_num_crtc; ++i) { qdev_crtc_init(qdev->ddev, i); qdev_output_init(qdev->ddev, i); } @@ -953,6 +970,8 @@ int qxl_modeset_init(struct qxl_device *qdev) void qxl_modeset_fini(struct qxl_device *qdev) { qxl_fbdev_fini(qdev); + + qxl_destroy_monitors_object(qdev); if (qdev->mode_info.mode_config_initialized) { drm_mode_config_cleanup(qdev->ddev); qdev->mode_info.mode_config_initialized = false; diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index aa291d8a98a2..df0b577a6608 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -33,8 +33,9 @@ #include "drmP.h" #include "drm/drm.h" - +#include "drm_crtc_helper.h" #include "qxl_drv.h" +#include "qxl_object.h" extern int qxl_max_ioctls; static DEFINE_PCI_DEVICE_TABLE(pciidlist) = { @@ -47,10 +48,14 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = { MODULE_DEVICE_TABLE(pci, pciidlist); static int qxl_modeset = -1; +int qxl_num_crtc = 4; MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); module_param_named(modeset, qxl_modeset, int, 0400); +MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)"); +module_param_named(num_heads, qxl_num_crtc, int, 0400); + static struct drm_driver qxl_driver; static struct pci_driver qxl_pci_driver; @@ -73,13 +78,6 @@ qxl_pci_remove(struct pci_dev *pdev) drm_put_dev(dev); } -static struct pci_driver qxl_pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - .probe = qxl_pci_probe, - .remove = qxl_pci_remove, -}; - static const struct file_operations qxl_fops = { .owner = THIS_MODULE, .open = drm_open, @@ -90,6 +88,130 @@ static const struct file_operations qxl_fops = { .mmap = qxl_mmap, }; +static int qxl_drm_freeze(struct drm_device *dev) +{ + struct pci_dev *pdev = dev->pdev; + struct qxl_device *qdev = dev->dev_private; + struct drm_crtc *crtc; + + drm_kms_helper_poll_disable(dev); + + console_lock(); + qxl_fbdev_set_suspend(qdev, 1); + console_unlock(); + + /* unpin the front buffers */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + if (crtc->enabled) + (*crtc_funcs->disable)(crtc); + } + + qxl_destroy_monitors_object(qdev); + qxl_surf_evict(qdev); + qxl_vram_evict(qdev); + + while (!qxl_check_idle(qdev->command_ring)); + while (!qxl_check_idle(qdev->release_ring)) + qxl_queue_garbage_collect(qdev, 1); + + pci_save_state(pdev); + + return 0; +} + +static int qxl_drm_resume(struct drm_device *dev, bool thaw) +{ + struct qxl_device *qdev = dev->dev_private; + + qdev->ram_header->int_mask = QXL_INTERRUPT_MASK; + if (!thaw) { + qxl_reinit_memslots(qdev); + qxl_ring_init_hdr(qdev->release_ring); + } + + qxl_create_monitors_object(qdev); + drm_helper_resume_force_mode(dev); + + console_lock(); + qxl_fbdev_set_suspend(qdev, 0); + console_unlock(); + + drm_kms_helper_poll_enable(dev); + return 0; +} + +static int qxl_pm_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + int error; + + error = qxl_drm_freeze(drm_dev); + if (error) + return error; + + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); + return 0; +} + +static int qxl_pm_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + if (pci_enable_device(pdev)) { + return -EIO; + } + + return qxl_drm_resume(drm_dev, false); +} + +static int qxl_pm_thaw(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + return qxl_drm_resume(drm_dev, true); +} + +static int qxl_pm_freeze(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + return qxl_drm_freeze(drm_dev); +} + +static int qxl_pm_restore(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + struct qxl_device *qdev = drm_dev->dev_private; + + qxl_io_reset(qdev); + return qxl_drm_resume(drm_dev, false); +} + +static const struct dev_pm_ops qxl_pm_ops = { + .suspend = qxl_pm_suspend, + .resume = qxl_pm_resume, + .freeze = qxl_pm_freeze, + .thaw = qxl_pm_thaw, + .poweroff = qxl_pm_freeze, + .restore = qxl_pm_restore, +}; +static struct pci_driver qxl_pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = qxl_pci_probe, + .remove = qxl_pci_remove, + .driver.pm = &qxl_pm_ops, +}; + static struct drm_driver qxl_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 43d06ab28a21..aacb791464a3 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -55,11 +55,10 @@ #define DRIVER_MINOR 1 #define DRIVER_PATCHLEVEL 0 -#define QXL_NUM_OUTPUTS 1 - #define QXL_DEBUGFS_MAX_COMPONENTS 32 extern int qxl_log_level; +extern int qxl_num_crtc; enum { QXL_INFO_LEVEL = 1, @@ -139,6 +138,7 @@ struct qxl_reloc_list { struct qxl_crtc { struct drm_crtc base; + int index; int cur_x; int cur_y; }; @@ -156,7 +156,7 @@ struct qxl_framebuffer { #define to_qxl_crtc(x) container_of(x, struct qxl_crtc, base) #define drm_connector_to_qxl_output(x) container_of(x, struct qxl_output, base) -#define drm_encoder_to_qxl_output(x) container_of(x, struct qxl_output, base) +#define drm_encoder_to_qxl_output(x) container_of(x, struct qxl_output, enc) #define to_qxl_framebuffer(x) container_of(x, struct qxl_framebuffer, base) struct qxl_mman { @@ -331,6 +331,10 @@ void qxl_modeset_fini(struct qxl_device *qdev); int qxl_bo_init(struct qxl_device *qdev); void qxl_bo_fini(struct qxl_device *qdev); +void qxl_reinit_memslots(struct qxl_device *qdev); +int qxl_surf_evict(struct qxl_device *qdev); +int qxl_vram_evict(struct qxl_device *qdev); + struct qxl_ring *qxl_ring_create(struct qxl_ring_header *header, int element_size, int n_elements, @@ -338,6 +342,8 @@ struct qxl_ring *qxl_ring_create(struct qxl_ring_header *header, bool set_prod_notify, wait_queue_head_t *push_event); void qxl_ring_free(struct qxl_ring *ring); +void qxl_ring_init_hdr(struct qxl_ring *ring); +int qxl_check_idle(struct qxl_ring *ring); static inline void * qxl_fb_virtual_address(struct qxl_device *qdev, unsigned long physical) @@ -365,6 +371,7 @@ void qxl_fbdev_fini(struct qxl_device *qdev); int qxl_get_handle_for_primary_fb(struct qxl_device *qdev, struct drm_file *file_priv, uint32_t *handle); +void qxl_fbdev_set_suspend(struct qxl_device *qdev, int state); /* qxl_display.c */ int @@ -374,6 +381,8 @@ qxl_framebuffer_init(struct drm_device *dev, struct drm_gem_object *obj); void qxl_display_read_client_monitors_config(struct qxl_device *qdev); void qxl_send_monitors_config(struct qxl_device *qdev); +int qxl_create_monitors_object(struct qxl_device *qdev); +int qxl_destroy_monitors_object(struct qxl_device *qdev); /* used by qxl_debugfs only */ void qxl_crtc_set_from_monitors_config(struct qxl_device *qdev); @@ -435,7 +444,7 @@ void qxl_update_screen(struct qxl_device *qxl); /* qxl io operations (qxl_cmd.c) */ void qxl_io_create_primary(struct qxl_device *qdev, - unsigned width, unsigned height, unsigned offset, + unsigned offset, struct qxl_bo *bo); void qxl_io_destroy_primary(struct qxl_device *qdev); void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id); @@ -528,6 +537,7 @@ irqreturn_t qxl_irq_handler(DRM_IRQ_ARGS); /* qxl_fb.c */ int qxl_fb_init(struct qxl_device *qdev); +bool qxl_fbdev_qobj_is_fb(struct qxl_device *qdev, struct qxl_bo *qobj); int qxl_debugfs_add_files(struct qxl_device *qdev, struct drm_info_list *files, diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c index 4b955b04ce1e..76f39d88d684 100644 --- a/drivers/gpu/drm/qxl/qxl_fb.c +++ b/drivers/gpu/drm/qxl/qxl_fb.c @@ -538,7 +538,7 @@ int qxl_fbdev_init(struct qxl_device *qdev) qfbdev->helper.funcs = &qxl_fb_helper_funcs; ret = drm_fb_helper_init(qdev->ddev, &qfbdev->helper, - 1 /* num_crtc - QXL supports just 1 */, + qxl_num_crtc /* num_crtc - QXL supports just 1 */, QXLFB_CONN_LIMIT); if (ret) { kfree(qfbdev); @@ -560,4 +560,14 @@ void qxl_fbdev_fini(struct qxl_device *qdev) qdev->mode_info.qfbdev = NULL; } +void qxl_fbdev_set_suspend(struct qxl_device *qdev, int state) +{ + fb_set_suspend(qdev->mode_info.qfbdev->helper.fbdev, state); +} +bool qxl_fbdev_qobj_is_fb(struct qxl_device *qdev, struct qxl_bo *qobj) +{ + if (qobj == gem_to_qxl_bo(qdev->mode_info.qfbdev->qfb.obj)) + return true; + return false; +} diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index a4b71b25fa53..6ba49d9922f2 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -183,6 +183,12 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data, /* TODO copy slow path code from i915 */ fb_cmd = qxl_bo_kmap_atomic_page(qdev, cmd_bo, (release->release_offset & PAGE_SIZE)); unwritten = __copy_from_user_inatomic_nocache(fb_cmd + sizeof(union qxl_release_info) + (release->release_offset & ~PAGE_SIZE), (void *)(unsigned long)user_cmd.command, user_cmd.command_size); + + { + struct qxl_drawable *draw = fb_cmd; + + draw->mm_time = qdev->rom->mm_clock; + } qxl_bo_kunmap_atomic_page(qdev, cmd_bo, fb_cmd); if (unwritten) { DRM_ERROR("got unwritten %d\n", unwritten); diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c index e27ce2a907cf..9e8da9ee9731 100644 --- a/drivers/gpu/drm/qxl/qxl_kms.c +++ b/drivers/gpu/drm/qxl/qxl_kms.c @@ -26,6 +26,7 @@ #include "qxl_drv.h" #include "qxl_object.h" +#include <drm/drm_crtc_helper.h> #include <linux/io-mapping.h> int qxl_log_level; @@ -72,21 +73,28 @@ static bool qxl_check_device(struct qxl_device *qdev) return true; } +static void setup_hw_slot(struct qxl_device *qdev, int slot_index, + struct qxl_memslot *slot) +{ + qdev->ram_header->mem_slot.mem_start = slot->start_phys_addr; + qdev->ram_header->mem_slot.mem_end = slot->end_phys_addr; + qxl_io_memslot_add(qdev, slot_index); +} + static uint8_t setup_slot(struct qxl_device *qdev, uint8_t slot_index_offset, unsigned long start_phys_addr, unsigned long end_phys_addr) { uint64_t high_bits; struct qxl_memslot *slot; uint8_t slot_index; - struct qxl_ram_header *ram_header = qdev->ram_header; slot_index = qdev->rom->slots_start + slot_index_offset; slot = &qdev->mem_slots[slot_index]; slot->start_phys_addr = start_phys_addr; slot->end_phys_addr = end_phys_addr; - ram_header->mem_slot.mem_start = slot->start_phys_addr; - ram_header->mem_slot.mem_end = slot->end_phys_addr; - qxl_io_memslot_add(qdev, slot_index); + + setup_hw_slot(qdev, slot_index, slot); + slot->generation = qdev->rom->slot_generation; high_bits = slot_index << qdev->slot_gen_bits; high_bits |= slot->generation; @@ -95,6 +103,12 @@ static uint8_t setup_slot(struct qxl_device *qdev, uint8_t slot_index_offset, return slot_index; } +void qxl_reinit_memslots(struct qxl_device *qdev) +{ + setup_hw_slot(qdev, qdev->main_mem_slot, &qdev->mem_slots[qdev->main_mem_slot]); + setup_hw_slot(qdev, qdev->surfaces_mem_slot, &qdev->mem_slots[qdev->surfaces_mem_slot]); +} + static void qxl_gc_work(struct work_struct *work) { struct qxl_device *qdev = container_of(work, struct qxl_device, gc_work); @@ -294,6 +308,8 @@ int qxl_driver_load(struct drm_device *dev, unsigned long flags) goto out; } + drm_kms_helper_poll_init(qdev->ddev); + return 0; out: kfree(qdev); diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c index d9b12e7bc6e1..1191fe7788c9 100644 --- a/drivers/gpu/drm/qxl/qxl_object.c +++ b/drivers/gpu/drm/qxl/qxl_object.c @@ -363,3 +363,13 @@ int qxl_bo_list_add(struct qxl_reloc_list *reloc_list, struct qxl_bo *bo) return ret; return 0; } + +int qxl_surf_evict(struct qxl_device *qdev) +{ + return ttm_bo_evict_mm(&qdev->mman.bdev, TTM_PL_PRIV0); +} + +int qxl_vram_evict(struct qxl_device *qdev) +{ + return ttm_bo_evict_mm(&qdev->mman.bdev, TTM_PL_VRAM); +} diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 003b34ee38e3..ff82877de876 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -251,7 +251,7 @@ static struct drm_driver rcar_du_driver = { .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = drm_gem_cma_dmabuf_import, .gem_prime_export = drm_gem_cma_dmabuf_export, - .dumb_create = drm_gem_cma_dumb_create, + .dumb_create = rcar_du_dumb_create, .dumb_map_offset = drm_gem_cma_dumb_map_offset, .dumb_destroy = drm_gem_cma_dumb_destroy, .fops = &rcar_du_fops, diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 9c63f39658de..d30c2e29bee2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -138,11 +138,25 @@ void rcar_du_encoder_mode_commit(struct drm_encoder *encoder) * Frame buffer */ +int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); + unsigned int align; + + /* The pitch must be aligned to a 16 pixels boundary. */ + align = 16 * args->bpp / 8; + args->pitch = roundup(max(args->pitch, min_pitch), align); + + return drm_gem_cma_dumb_create(file, dev, args); +} + static struct drm_framebuffer * rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd) { const struct rcar_du_format_info *format; + unsigned int align; format = rcar_du_format_info(mode_cmd->pixel_format); if (format == NULL) { @@ -151,7 +165,10 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, return ERR_PTR(-EINVAL); } - if (mode_cmd->pitches[0] & 15 || mode_cmd->pitches[0] >= 8192) { + align = 16 * format->bpp / 8; + + if (mode_cmd->pitches[0] & (align - 1) || + mode_cmd->pitches[0] >= 8192) { dev_dbg(dev->dev, "invalid pitch value %u\n", mode_cmd->pitches[0]); return ERR_PTR(-EINVAL); @@ -191,8 +208,11 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) if (ret < 0) return ret; - for (i = 0; i < ARRAY_SIZE(rcdu->crtcs); ++i) - rcar_du_crtc_create(rcdu, i); + for (i = 0; i < ARRAY_SIZE(rcdu->crtcs); ++i) { + ret = rcar_du_crtc_create(rcdu, i); + if (ret < 0) + return ret; + } rcdu->used_crtcs = 0; rcdu->num_crtcs = i; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.h b/drivers/gpu/drm/rcar-du/rcar_du_kms.h index e4d8db069a06..dba472263486 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.h @@ -56,4 +56,7 @@ void rcar_du_encoder_mode_commit(struct drm_encoder *encoder); int rcar_du_modeset_init(struct rcar_du_device *rcdu); +int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev, + struct drm_mode_create_dumb *args); + #endif /* __RCAR_DU_KMS_H__ */ diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 6e6975c8596f..cb9dd674670c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1455,9 +1455,7 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev, goto out_no_sys; bdev->addr_space_rb = RB_ROOT; - ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); - if (unlikely(ret != 0)) - goto out_no_addr_mm; + drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000); INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue); INIT_LIST_HEAD(&bdev->ddestroy); @@ -1471,8 +1469,6 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev, mutex_unlock(&glob->device_list_mutex); return 0; -out_no_addr_mm: - ttm_bo_clean_mm(bdev, 0); out_no_sys: return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_manager.c b/drivers/gpu/drm/ttm/ttm_bo_manager.c index 9212494e9072..e4367f91472a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_manager.c +++ b/drivers/gpu/drm/ttm/ttm_bo_manager.c @@ -103,18 +103,12 @@ static int ttm_bo_man_init(struct ttm_mem_type_manager *man, unsigned long p_size) { struct ttm_range_manager *rman; - int ret; rman = kzalloc(sizeof(*rman), GFP_KERNEL); if (!rman) return -ENOMEM; - ret = drm_mm_init(&rman->mm, 0, p_size); - if (ret) { - kfree(rman); - return ret; - } - + drm_mm_init(&rman->mm, 0, p_size); spin_lock_init(&rman->lock); man->priv = rman; return 0; diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 82670ac0d774..12083dc862a9 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -937,6 +937,8 @@ struct drm_driver { struct sg_table *sgt); void *(*gem_prime_vmap)(struct drm_gem_object *obj); void (*gem_prime_vunmap)(struct drm_gem_object *obj, void *vaddr); + int (*gem_prime_mmap)(struct drm_gem_object *obj, + struct vm_area_struct *vma); /* vga arb irq handler */ void (*vgaarb_irq)(struct drm_device *dev, bool state); diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h index 6e17251e9b28..c34f27f80bcc 100644 --- a/include/drm/drm_gem_cma_helper.h +++ b/include/drm/drm_gem_cma_helper.h @@ -48,10 +48,13 @@ extern const struct vm_operations_struct drm_gem_cma_vm_ops; void drm_gem_cma_describe(struct drm_gem_cma_object *obj, struct seq_file *m); #endif -struct dma_buf *drm_gem_cma_dmabuf_export(struct drm_device *drm_dev, - struct drm_gem_object *obj, - int flags); -struct drm_gem_object *drm_gem_cma_dmabuf_import(struct drm_device *drm_dev, - struct dma_buf *dma_buf); +struct sg_table *drm_gem_cma_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object * +drm_gem_cma_prime_import_sg_table(struct drm_device *dev, size_t size, + struct sg_table *sgt); +int drm_gem_cma_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); +void *drm_gem_cma_prime_vmap(struct drm_gem_object *obj); +void drm_gem_cma_prime_vunmap(struct drm_gem_object *obj, void *vaddr); #endif /* __DRM_GEM_CMA_HELPER_H__ */ diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index 88591ef8fa24..4d06edb56d5f 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -177,17 +177,6 @@ static inline struct drm_mm_node *drm_mm_get_block_range( return drm_mm_get_block_range_generic(parent, size, alignment, 0, start, end, 0); } -static inline struct drm_mm_node *drm_mm_get_color_block_range( - struct drm_mm_node *parent, - unsigned long size, - unsigned alignment, - unsigned long color, - unsigned long start, - unsigned long end) -{ - return drm_mm_get_block_range_generic(parent, size, alignment, color, - start, end, 0); -} static inline struct drm_mm_node *drm_mm_get_block_atomic_range( struct drm_mm_node *parent, unsigned long size, @@ -255,29 +244,10 @@ static inline struct drm_mm_node *drm_mm_search_free_in_range( return drm_mm_search_free_in_range_generic(mm, size, alignment, 0, start, end, best_match); } -static inline struct drm_mm_node *drm_mm_search_free_color(const struct drm_mm *mm, - unsigned long size, - unsigned alignment, - unsigned long color, - bool best_match) -{ - return drm_mm_search_free_generic(mm,size, alignment, color, best_match); -} -static inline struct drm_mm_node *drm_mm_search_free_in_range_color( - const struct drm_mm *mm, - unsigned long size, - unsigned alignment, - unsigned long color, - unsigned long start, - unsigned long end, - bool best_match) -{ - return drm_mm_search_free_in_range_generic(mm, size, alignment, color, - start, end, best_match); -} -extern int drm_mm_init(struct drm_mm *mm, - unsigned long start, - unsigned long size); + +extern void drm_mm_init(struct drm_mm *mm, + unsigned long start, + unsigned long size); extern void drm_mm_takedown(struct drm_mm *mm); extern int drm_mm_clean(struct drm_mm *mm); extern int drm_mm_pre_get(struct drm_mm *mm); |