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-rw-r--r--Documentation/devicetree/bindings/arm/cci.txt15
1 files changed, 4 insertions, 11 deletions
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
index 0f2153e8fa7e..9600761f2d5b 100644
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register
space and multiple sets of interface control registers, one per slave
interface.
-Bindings for the CCI node follow the ePAPR standard, available from:
-
-www.power.org/documentation/epapr-version-1-1/
-
-with the addition of the bindings described in this document which are
-specific to ARM.
-
* CCI interconnect node
Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM.
as a tuple of cells, containing child address,
parent address and the size of the region in the
child address space.
- Definition: A standard property. Follow rules in the ePAPR for
- hierarchical bus addressing. CCI interfaces
- addresses refer to the parent node addressing
- scheme to declare their register bases.
+ Definition: A standard property. Follow rules in the Devicetree
+ Specification for hierarchical bus addressing. CCI
+ interfaces addresses refer to the parent node
+ addressing scheme to declare their register bases.
CCI interconnect node can define the following child nodes: