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-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/ste-nomadik.txt5
-rw-r--r--Documentation/devicetree/bindings/bus/imx-weim.txt49
-rw-r--r--Documentation/devicetree/bindings/clock/altr_socfpga.txt7
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt252
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt154
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt211
-rw-r--r--Documentation/devicetree/bindings/clock/st,nomadik.txt104
-rw-r--r--Documentation/devicetree/bindings/gpu/samsung-g2d.txt5
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt16
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt5
-rw-r--r--Documentation/devicetree/bindings/mfd/ab8500.txt2
-rw-r--r--Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt16
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt44
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt34
-rw-r--r--Documentation/devicetree/bindings/video/exynos_dp.txt6
18 files changed, 308 insertions, 610 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index f8288ea1b530..6d498c758b45 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -56,3 +56,6 @@ Boards:
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
+
+- AM43x EPOS EVM
+ compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
index 19bca04b81c9..6256ec31666d 100644
--- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt
+++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
@@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs.
+Required root node property: src
+- Nomadik System and reset controller used for basic chip control, clock
+ and reset line control.
+- compatible: must be "stericsson,nomadik,src"
+
Boards with the Nomadik SoC include:
S8815 "MiniKit" manufactured by Calao Systems:
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 000000000000..cedc2a9c4785
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,49 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+
+The actual devices are instantiated from the child nodes of a WEIM node.
+
+Required properties:
+
+ - compatible: Should be set to "fsl,imx6q-weim"
+ - reg: A resource specifier for the register space
+ (see the example below)
+ - clocks: the clock, see the example below.
+ - #address-cells: Must be set to 2 to allow memory address translation
+ - #size-cells: Must be set to 1 to allow CS address passing
+ - ranges: Must be set up to reflect the memory layout with four
+ integer values for each chip-select line in use:
+
+ <cs-number> 0 <physical address of mapping> <size>
+
+Timing property for child nodes. It is mandatory, not optional.
+
+ - fsl,weim-cs-timing: The timing array, contains 6 timing values for the
+ child node. We can get the CS index from the child
+ node's "reg" property. This property contains the values
+ for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
+ EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+
+ weim: weim@021b8000 {
+ compatible = "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ clocks = <&clks 196>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x08000000>;
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c8416a5c8..0045433eae1f 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
"altr,socfpga-pll-clock" - for a PLL clock
"altr,socfpga-perip-clock" - The peripheral clock divided from the
PLL clock.
+ "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+ can get gated.
+
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+ and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+ and width.
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index ea5e26f16aec..14d5c2af26f4 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
sclk_spi0_isp 174 Exynos4x12
sclk_spi1_isp 175 Exynos4x12
sclk_uart_isp 176 Exynos4x12
+ sclk_fimg2d 177
[Peripheral Clock Gates]
@@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
smmu_mfcl 274
smmu_mfcr 275
g3d 276
- g2d 277 Exynos4210
+ g2d 277
rotator 278 Exynos4210
mdma 279 Exynos4210
smmu_g2d 280 Exynos4210
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index d6cb083b90a2..0c80c2677104 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -12,253 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the CAR.
-
- The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 160 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- above.
-
- 0 unassigned
- 1 unassigned
- 2 unassigned
- 3 unassigned
- 4 rtc
- 5 timer
- 6 uarta
- 7 unassigned (register bit affects uartb and vfir)
- 8 unassigned
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 unassigned
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 unassigned
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 i2s0
- 31 unassigned
-
- 32 unassigned
- 33 unassigned
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 unassigned
- 38 unassigned
- 39 unassigned (register bit affects fuse and fuse_burn)
- 40 kfuse
- 41 sbc1
- 42 nor
- 43 unassigned
- 44 sbc2
- 45 unassigned
- 46 sbc3
- 47 i2c5
- 48 dsia
- 49 unassigned
- 50 mipi
- 51 hdmi
- 52 csi
- 53 unassigned
- 54 i2c2
- 55 uartc
- 56 mipi-cal
- 57 emc
- 58 usb2
- 59 usb3
- 60 msenc
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 unassigned
- 65 uartd
- 66 unassigned
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 unassigned
- 71 owr
- 72 afi
- 73 csite
- 74 unassigned
- 75 unassigned
- 76 la
- 77 trace
- 78 soc_therm
- 79 dtv
- 80 ndspeed
- 81 i2cslow
- 82 dsib
- 83 tsec
- 84 unassigned
- 85 unassigned
- 86 unassigned
- 87 unassigned
- 88 unassigned
- 89 xusb_host
- 90 unassigned
- 91 msenc
- 92 csus
- 93 unassigned
- 94 unassigned
- 95 unassigned (bit affects xusb_dev and xusb_dev_src)
-
- 96 unassigned
- 97 unassigned
- 98 unassigned
- 99 mselect
- 100 tsensor
- 101 i2s3
- 102 i2s4
- 103 i2c4
- 104 sbc5
- 105 sbc6
- 106 d_audio
- 107 apbif
- 108 dam0
- 109 dam1
- 110 dam2
- 111 hda2codec_2x
- 112 unassigned
- 113 audio0_2x
- 114 audio1_2x
- 115 audio2_2x
- 116 audio3_2x
- 117 audio4_2x
- 118 spdif_2x
- 119 actmon
- 120 extern1
- 121 extern2
- 122 extern3
- 123 unassigned
- 124 unassigned
- 125 hda
- 126 unassigned
- 127 se
-
- 128 hda2hdmi
- 129 unassigned
- 130 unassigned
- 131 unassigned
- 132 unassigned
- 133 unassigned
- 134 unassigned
- 135 unassigned
- 136 unassigned
- 137 unassigned
- 138 unassigned
- 139 unassigned
- 140 unassigned
- 141 unassigned
- 142 unassigned
- 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
- xusb_host_src and xusb_ss_src)
- 144 cilab
- 145 cilcd
- 146 cile
- 147 dsialp
- 148 dsiblp
- 149 unassigned
- 150 dds
- 151 unassigned
- 152 dp2
- 153 amx
- 154 adx
- 155 unassigned (bit affects dfll_ref and dfll_soc)
- 156 xusb_ss
-
- 192 uartb
- 193 vfir
- 194 spdif_in
- 195 spdif_out
- 196 vi
- 197 vi_sensor
- 198 fuse
- 199 fuse_burn
- 200 clk_32k
- 201 clk_m
- 202 clk_m_div2
- 203 clk_m_div4
- 204 pll_ref
- 205 pll_c
- 206 pll_c_out1
- 207 pll_c2
- 208 pll_c3
- 209 pll_m
- 210 pll_m_out1
- 211 pll_p
- 212 pll_p_out1
- 213 pll_p_out2
- 214 pll_p_out3
- 215 pll_p_out4
- 216 pll_a
- 217 pll_a_out0
- 218 pll_d
- 219 pll_d_out0
- 220 pll_d2
- 221 pll_d2_out0
- 222 pll_u
- 223 pll_u_480M
- 224 pll_u_60M
- 225 pll_u_48M
- 226 pll_u_12M
- 227 pll_x
- 228 pll_x_out0
- 229 pll_re_vco
- 230 pll_re_out
- 231 pll_e_out0
- 232 spdif_in_sync
- 233 i2s0_sync
- 234 i2s1_sync
- 235 i2s2_sync
- 236 i2s3_sync
- 237 i2s4_sync
- 238 vimclk_sync
- 239 audio0
- 240 audio1
- 241 audio2
- 242 audio3
- 243 audio4
- 244 spdif
- 245 clk_out_1
- 246 clk_out_2
- 247 clk_out_3
- 248 blink
- 252 xusb_host_src
- 253 xusb_falcon_src
- 254 xusb_fs_src
- 255 xusb_ss_src
- 256 xusb_dev_src
- 257 xusb_dev
- 258 xusb_hs_src
- 259 sclk
- 260 hclk
- 261 pclk
- 262 cclk_g
- 263 cclk_lp
- 264 dfll_ref
- 265 dfll_soc
+ In clock consumers, this cell represents the clock ID exposed by the
+ CAR. The assignments may be found in header file
+ <dt-bindings/clock/tegra114-car.h>.
Example SoC include file:
@@ -270,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA114_CLK_USB2>;
};
};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680f6b45..fcfed5bf73fb 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -12,155 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the CAR.
-
- The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 95 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 96 and
- above.
-
- 0 cpu
- 1 unassigned
- 2 unassigned
- 3 ac97
- 4 rtc
- 5 tmr
- 6 uart1
- 7 unassigned (register bit affects uart2 and vfir)
- 8 gpio
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 twc
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 ide
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 unassigned
- 31 cache2
-
- 32 mem
- 33 ahbdma
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 stat_mon
- 38 pmc
- 39 fuse
- 40 kfuse
- 41 sbc1
- 42 snor
- 43 spi1
- 44 sbc2
- 45 xio
- 46 sbc3
- 47 dvc
- 48 dsi
- 49 unassigned (register bit affects tvo and cve)
- 50 mipi
- 51 hdmi
- 52 csi
- 53 tvdac
- 54 i2c2
- 55 uart3
- 56 unassigned
- 57 emc
- 58 usb2
- 59 usb3
- 60 mpe
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 speedo
- 65 uart4
- 66 uart5
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 pcie
- 71 owr
- 72 afi
- 73 csite
- 74 unassigned
- 75 avpucq
- 76 la
- 77 unassigned
- 78 unassigned
- 79 unassigned
- 80 unassigned
- 81 unassigned
- 82 unassigned
- 83 unassigned
- 84 irama
- 85 iramb
- 86 iramc
- 87 iramd
- 88 cram2
- 89 audio_2x a/k/a audio_2x_sync_clk
- 90 clk_d
- 91 unassigned
- 92 sus
- 93 cdev2
- 94 cdev1
- 95 unassigned
-
- 96 uart2
- 97 vfir
- 98 spdif_in
- 99 spdif_out
- 100 vi
- 101 vi_sensor
- 102 tvo
- 103 cve
- 104 osc
- 105 clk_32k a/k/a clk_s
- 106 clk_m
- 107 sclk
- 108 cclk
- 109 hclk
- 110 pclk
- 111 blink
- 112 pll_a
- 113 pll_a_out0
- 114 pll_c
- 115 pll_c_out1
- 116 pll_d
- 117 pll_d_out0
- 118 pll_e
- 119 pll_m
- 120 pll_m_out1
- 121 pll_p
- 122 pll_p_out1
- 123 pll_p_out2
- 124 pll_p_out3
- 125 pll_p_out4
- 126 pll_s
- 127 pll_u
- 128 pll_x
- 129 cop a/k/a avp
- 130 audio a/k/a audio_sync_clk
- 131 pll_ref
- 132 twd
+ In clock consumers, this cell represents the clock ID exposed by the
+ CAR. The assignments may be found in header file
+ <dt-bindings/clock/tegra20-car.h>.
Example SoC include file:
@@ -172,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA20_CLK_USB2>;
};
};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be5fcad..0f714081e986 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -12,212 +12,9 @@ Required properties :
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the CAR.
-
- The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 160 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- above.
-
- 0 cpu
- 1 unassigned
- 2 unassigned
- 3 unassigned
- 4 rtc
- 5 timer
- 6 uarta
- 7 unassigned (register bit affects uartb and vfir)
- 8 gpio
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 unassigned
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 unassigned
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 i2s0
- 31 cop_cache
-
- 32 mc
- 33 ahbdma
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 statmon
- 38 pmc
- 39 unassigned (register bit affects fuse and fuse_burn)
- 40 kfuse
- 41 sbc1
- 42 nor
- 43 unassigned
- 44 sbc2
- 45 unassigned
- 46 sbc3
- 47 i2c5
- 48 dsia
- 49 unassigned (register bit affects cve and tvo)
- 50 mipi
- 51 hdmi
- 52 csi
- 53 tvdac
- 54 i2c2
- 55 uartc
- 56 unassigned
- 57 emc
- 58 usb2
- 59 usb3
- 60 mpe
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 speedo
- 65 uartd
- 66 uarte
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 pcie
- 71 owr
- 72 afi
- 73 csite
- 74 pciex
- 75 avpucq
- 76 la
- 77 unassigned
- 78 unassigned
- 79 dtv
- 80 ndspeed
- 81 i2cslow
- 82 dsib
- 83 unassigned
- 84 irama
- 85 iramb
- 86 iramc
- 87 iramd
- 88 cram2
- 89 unassigned
- 90 audio_2x a/k/a audio_2x_sync_clk
- 91 unassigned
- 92 csus
- 93 cdev2
- 94 cdev1
- 95 unassigned
-
- 96 cpu_g
- 97 cpu_lp
- 98 3d2
- 99 mselect
- 100 tsensor
- 101 i2s3
- 102 i2s4
- 103 i2c4
- 104 sbc5
- 105 sbc6
- 106 d_audio
- 107 apbif
- 108 dam0
- 109 dam1
- 110 dam2
- 111 hda2codec_2x
- 112 atomics
- 113 audio0_2x
- 114 audio1_2x
- 115 audio2_2x
- 116 audio3_2x
- 117 audio4_2x
- 118 audio5_2x
- 119 actmon
- 120 extern1
- 121 extern2
- 122 extern3
- 123 sata_oob
- 124 sata
- 125 hda
- 127 se
- 128 hda2hdmi
- 129 sata_cold
-
- 160 uartb
- 161 vfir
- 162 spdif_in
- 163 spdif_out
- 164 vi
- 165 vi_sensor
- 166 fuse
- 167 fuse_burn
- 168 cve
- 169 tvo
-
- 170 clk_32k
- 171 clk_m
- 172 clk_m_div2
- 173 clk_m_div4
- 174 pll_ref
- 175 pll_c
- 176 pll_c_out1
- 177 pll_m
- 178 pll_m_out1
- 179 pll_p
- 180 pll_p_out1
- 181 pll_p_out2
- 182 pll_p_out3
- 183 pll_p_out4
- 184 pll_a
- 185 pll_a_out0
- 186 pll_d
- 187 pll_d_out0
- 188 pll_d2
- 189 pll_d2_out0
- 190 pll_u
- 191 pll_x
- 192 pll_x_out0
- 193 pll_e
- 194 spdif_in_sync
- 195 i2s0_sync
- 196 i2s1_sync
- 197 i2s2_sync
- 198 i2s3_sync
- 199 i2s4_sync
- 200 vimclk
- 201 audio0
- 202 audio1
- 203 audio2
- 204 audio3
- 205 audio4
- 206 audio5
- 207 clk_out_1 (extern1)
- 208 clk_out_2 (extern2)
- 209 clk_out_3 (extern3)
- 210 sclk
- 211 blink
- 212 cclk_g
- 213 cclk_lp
- 214 twd
- 215 cml0
- 216 cml1
- 217 hclk
- 218 pclk
+ In clock consumers, this cell represents the clock ID exposed by the
+ CAR. The assignments may be found in header file
+ <dt-bindings/clock/tegra30-car.h>.
Example SoC include file:
@@ -229,7 +26,7 @@ Example SoC include file:
};
usb@c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
+ clocks = <&tegra_car TEGRA30_CLK_USB2>;
};
};
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt
new file mode 100644
index 000000000000..7fc09773de46
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt
@@ -0,0 +1,104 @@
+ST Microelectronics Nomadik SRC System Reset and Control
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The Nomadik SRC controller is responsible of controlling chrystals,
+PLLs and clock gates.
+
+Required properties for the SRC node:
+- compatible: must be "stericsson,nomadik-src"
+- reg: must contain the SRC register base and size
+
+Optional properties for the SRC node:
+- disable-sxtalo: if present this will disable the SXTALO
+ i.e. the driver output for the slow 32kHz chrystal, if the
+ board has its own circuitry for providing this oscillator
+- disable-mxtal: if present this will disable the MXTALO,
+ i.e. the driver output for the main (~19.2 MHz) chrystal,
+ if the board has its own circuitry for providing this
+ osciallator
+
+
+PLL nodes: these nodes represent the two PLLs on the system,
+which should both have the main chrystal, represented as a
+fixed frequency clock, as parent.
+
+Required properties for the two PLL nodes:
+- compatible: must be "st,nomadik-pll-clock"
+- clock-cells: must be 0
+- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
+- clocks: this clock will have main chrystal as parent
+
+
+HCLK nodes: these represent the clock gates on individual
+lines from the HCLK clock tree and the gate for individual
+lines from the PCLK clock tree.
+
+Requires properties for the HCLK nodes:
+- compatible: must be "st,nomadik-hclk-clock"
+- clock-cells: must be 0
+- clock-id: must be the clock ID from 0 to 63 according to
+ this table:
+
+ 0: HCLKDMA0
+ 1: HCLKSMC
+ 2: HCLKSDRAM
+ 3: HCLKDMA1
+ 4: HCLKCLCD
+ 5: PCLKIRDA
+ 6: PCLKSSP
+ 7: PCLKUART0
+ 8: PCLKSDI
+ 9: PCLKI2C0
+ 10: PCLKI2C1
+ 11: PCLKUART1
+ 12: PCLMSP0
+ 13: HCLKUSB
+ 14: HCLKDIF
+ 15: HCLKSAA
+ 16: HCLKSVA
+ 17: PCLKHSI
+ 18: PCLKXTI
+ 19: PCLKUART2
+ 20: PCLKMSP1
+ 21: PCLKMSP2
+ 22: PCLKOWM
+ 23: HCLKHPI
+ 24: PCLKSKE
+ 25: PCLKHSEM
+ 26: HCLK3D
+ 27: HCLKHASH
+ 28: HCLKCRYP
+ 29: PCLKMSHC
+ 30: HCLKUSBM
+ 31: HCLKRNG
+ (32, 33, 34, 35 RESERVED)
+ 36: CLDCLK
+ 37: IRDACLK
+ 38: SSPICLK
+ 39: UART0CLK
+ 40: SDICLK
+ 41: I2C0CLK
+ 42: I2C1CLK
+ 43: UART1CLK
+ 44: MSPCLK0
+ 45: USBCLK
+ 46: DIFCLK
+ 47: IPI2CCLK
+ 48: IPBMCCLK
+ 49: HSICLKRX
+ 50: HSICLKTX
+ 51: UART2CLK
+ 52: MSPCLK1
+ 53: MSPCLK2
+ 54: OWMCLK
+ (55 RESERVED)
+ 56: SKECLK
+ (57 RESERVED)
+ 58: 3DCLK
+ 59: PCLKMSP3
+ 60: MSPCLK3
+ 61: MSHCCLK
+ 62: USBMCLK
+ 63: RNGCCLK
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 2b14a940eb75..3f454ffc654a 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -10,11 +10,16 @@ Required properties:
mapped region.
- interrupts : G2D interrupt number to the CPU.
+ - clocks : from common clock binding: handle to G2D clocks.
+ - clock-names : from common clock binding: must contain "sclk_fimg2d" and
+ "fimg2d", corresponding to entries in the clocks property.
Example:
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
+ clocks = <&clock 177>, <&clock 277>;
+ clock-names = "sclk_fimg2d", "fimg2d";
status = "disabled";
};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
new file mode 100644
index 000000000000..1f8b0c507c26
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -0,0 +1,16 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+
+Required properties:
+
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+ interrupts.txt in this directory
+
+Optional properties:
+
+- any properties, listed in interrupts.txt, and any standard resource allocation
+ properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+ if different from the default 4 bits
+- control-parent: disable and enable interrupts on the parent interrupt
+ controller, needed for some broken implementations
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index bf0182d8da25..df37b0230c75 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -15,6 +15,9 @@ Required properties:
mapped region.
- interrupts : MFC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to mfc clocks.
+ - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
+ corresponding to entries in the clocks property.
- samsung,mfc-r : Base address of the first memory bank used by MFC
for DMA contiguous memory allocation and its size.
@@ -34,6 +37,8 @@ mfc: codec@13400000 {
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
+ clocks = <&clock 170>, <&clock 273>;
+ clock-names = "sclk_mfc", "mfc";
};
Board specific DT entry:
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index c3a14e0ad0ad..cd9e90c5d171 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -120,7 +120,7 @@ ab8500 {
"USB_LINK_STATUS",
"USB_ADP_PROBE_PLUG",
"USB_ADP_PROBE_UNPLUG";
- vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+ vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
v-ape-supply = <&db8500_vape_reg>;
musb_1v8-supply = <&db8500_vsmps2_reg>;
};
diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 000000000000..094ae010f2fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI
+
+This file documents differences between the core properties in mmc.txt
+and the properties present in the bcm281xx SDHCI
+
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+
+Example:
+
+sdio2: sdio@0x3f1a0000 {
+ compatible = "bcm,kona-sdhci";
+ reg = <0x3f1a0000 0x10000>;
+ interrupts = <0x0 74 0x4>;
+};
+
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
index bcfdab5d442e..3a7caf7a744a 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
Examples:
usdhc@0219c000 { /* uSDHC4 */
- fsl,card-wired;
+ non-removable;
vmmc-supply = <&reg_3p3v>;
status = "okay";
pinctrl-names = "default";
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index c70fca146e91..e15cfc4bb39e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -21,8 +21,18 @@ Required Properties:
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
- binding is used, the amount of cells must be specified as 2. See generic
- GPIO binding documentation for description of particular cells.
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ Eg: <&gpx2 6 0>
+ <[phandle of the gpio controller node]
+ [pin number within the gpio controller]
+ [flags]>
+
+ Values for gpio specifier:
+ - Pin number: is a value between 0 to 7.
+ - Flags: 0 - Active High
+ 1 - Active Low
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
mode) and pin config (pull up/down, driver strength) settings are represented
@@ -266,3 +276,33 @@ Example 4: Set up the default pin state for uart controller.
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
}
+
+Example 5: A display port client node that supports 'default' pinctrl state
+ and gpio binding.
+
+ display-port-controller {
+ /* ... */
+
+ samsung,hpd-gpio = <&gpx2 6 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_hpd>;
+ };
+
+Example 6: Request the gpio for display port controller
+
+ static int exynos_dp_probe(struct platform_device *pdev)
+ {
+ int hpd_gpio, ret;
+ struct device *dev = &pdev->dev;
+ struct device_node *dp_node = dev->of_node;
+
+ /* ... */
+
+ hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
+
+ /* ... */
+
+ ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
+ "hpd_gpio");
+ /* ... */
+ }
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index b3abde736017..d967ba16de60 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -48,3 +48,37 @@ Example:
clocks = <&clock 285>;
clock-names = "usbhost";
};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
+ controller.
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+ with 'reg' property.
+ - ranges: allows valid 1:1 translation between child's address space and
+ parent's address space
+ - clocks: Clock IDs array as required by the controller.
+ - clock-names: names of clocks correseponding to IDs in the clock property
+
+Sub-nodes:
+The dwc3 core should be added as subnode to Exynos dwc3 glue.
+- dwc3 :
+ The binding details of dwc3 can be found in:
+ Documentation/devicetree/bindings/usb/dwc3.txt
+
+Example:
+ usb@12000000 {
+ compatible = "samsung,exynos5250-dwusb3";
+ clocks = <&clock 286>;
+ clock-names = "usbdrd30";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3 {
+ compatible = "synopsys,dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ usb-phy = <&usb2_phy &usb3_phy>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index c60da67a5d76..84f10c16cb38 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -21,6 +21,10 @@ Required properties for dp-controller:
of memory mapped region.
-interrupts:
interrupt combiner values.
+ -clocks:
+ from common clock binding: handle to dp clock.
+ -clock-names:
+ from common clock binding: Shall be "dp".
-interrupt-parent:
phandle to Interrupt combiner node.
-samsung,color-space:
@@ -61,6 +65,8 @@ SOC specific portion:
reg = <0x145b0000 0x10000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
+ clocks = <&clock 342>;
+ clock-names = "dp";
dptx-phy {
reg = <0x10040720>;