diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6dl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5bcdf3a90bb3..2b3ecd679350 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -18,12 +18,14 @@ cpu@0 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; }; @@ -35,6 +37,27 @@ compatible = "fsl,imx6dl-iomuxc"; reg = <0x020e0000 0x4000>; + audmux { + pinctrl_audmux_2: audmux-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 + MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 + MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 + MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + }; + enet { pinctrl_enet_1: enetgrp-1 { fsl,pins = < @@ -78,6 +101,39 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + }; + uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < @@ -149,6 +205,64 @@ }; }; + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + + }; }; |