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-rw-r--r--arch/arm/boot/dts/qcom-apq8060-dragonboard.dts25
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts24
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts14
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-ifc6410.dts25
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts10
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi162
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi10
-rw-r--r--arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts6
-rw-r--r--arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts7
-rw-r--r--arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts2
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019.dtsi4
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-rb3011.dts6
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi9
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi36
-rw-r--r--arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom-mdm9615.dtsi7
-rw-r--r--arch/arm/boot/dts/qcom-msm8226.dtsi6
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi112
-rw-r--r--arch/arm/boot/dts/qcom-msm8960.dtsi54
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts12
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi10
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi49
-rw-r--r--arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts14
-rw-r--r--arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts20
-rw-r--r--arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts18
-rw-r--r--arch/arm/boot/dts/qcom-pm8841.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-pm8941.dtsi2
-rw-r--r--arch/arm/boot/dts/qcom-pmx55.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-pmx65.dtsi3
-rw-r--r--arch/arm/boot/dts/qcom-sdx55.dtsi8
-rw-r--r--arch/arm/boot/dts/qcom-sdx65-mtp.dts61
-rw-r--r--arch/arm/boot/dts/qcom-sdx65.dtsi271
34 files changed, 682 insertions, 313 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 138d6478ac84..70a1dd629c7a 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include "qcom-msm8660.dtsi"
@@ -273,7 +274,7 @@
};
gpio@150 {
- dragon_ethernet_gpios: ethernet-gpios {
+ dragon_ethernet_gpios: ethernet-state {
pinconf {
pins = "gpio7";
function = "normal";
@@ -282,7 +283,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_bmp085_gpios: bmp085-gpios {
+ dragon_bmp085_gpios: bmp085-state {
pinconf {
pins = "gpio16";
function = "normal";
@@ -291,7 +292,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_mpu3050_gpios: mpu3050-gpios {
+ dragon_mpu3050_gpios: mpu3050-state {
pinconf {
pins = "gpio17";
function = "normal";
@@ -300,7 +301,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_sdcc3_gpios: sdcc3-gpios {
+ dragon_sdcc3_gpios: sdcc3-state {
pinconf {
pins = "gpio22";
function = "normal";
@@ -309,7 +310,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_sdcc5_gpios: sdcc5-gpios {
+ dragon_sdcc5_gpios: sdcc5-state {
pinconf {
pins = "gpio26";
function = "normal";
@@ -319,7 +320,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_ak8975_gpios: ak8975-gpios {
+ dragon_ak8975_gpios: ak8975-state {
pinconf {
pins = "gpio33";
function = "normal";
@@ -328,9 +329,9 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_cm3605_gpios: cm3605-gpios {
+ dragon_cm3605_gpios: cm3605-state {
/* Pin 34 connected to the proxy IRQ */
- pinconf_gpio34 {
+ gpio34-pins {
pins = "gpio34";
function = "normal";
input-enable;
@@ -338,7 +339,7 @@
power-source = <PM8058_GPIO_S3>;
};
/* Pin 35 connected to ASET */
- pinconf_gpio35 {
+ gpio35-pins {
pins = "gpio35";
function = "normal";
output-high;
@@ -346,7 +347,7 @@
power-source = <PM8058_GPIO_S3>;
};
};
- dragon_veth_gpios: veth-gpios {
+ dragon_veth_gpios: veth-state {
pinconf {
pins = "gpio40";
function = "normal";
@@ -416,6 +417,7 @@
compatible = "qcom,pm8058-led";
reg = <0x131>;
label = "pm8058:red";
+ color = <LED_COLOR_ID_RED>;
default-state = "off";
};
led@132 {
@@ -426,6 +428,7 @@
compatible = "qcom,pm8058-led";
reg = <0x132>;
label = "pm8058:yellow";
+ color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
linux,default-trigger = "mmc0";
};
@@ -433,6 +436,8 @@
compatible = "qcom,pm8058-led";
reg = <0x133>;
label = "pm8058:green";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index ca9f73528196..fee278e32cb6 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -24,9 +24,9 @@
ramoops@88d00000{
compatible = "ramoops";
reg = <0x88d00000 0x100000>;
- record-size = <0x00020000>;
- console-size = <0x00020000>;
- ftrace-size = <0x00020000>;
+ record-size = <0x00020000>;
+ console-size = <0x00020000>;
+ ftrace-size = <0x00020000>;
};
};
@@ -44,12 +44,12 @@
gpio-keys {
compatible = "gpio-keys";
- volume_up {
+ key-volume-up {
label = "Volume Up";
gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_VOLUMEUP>;
};
- volume_down {
+ key-volume-down {
label = "Volume Down";
gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -98,8 +98,8 @@
* tabla2x-slim-VDDIO_CDC
*/
s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
regulator-always-on;
};
@@ -341,17 +341,17 @@
};
};
- imem@2a03f000 {
- compatible = "syscon", "simple-mfd";
+ sram@2a03f000 {
+ compatible = "qcom,apq8064-imem", "syscon", "simple-mfd";
reg = <0x2a03f000 0x1000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x65c>;
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
};
};
};
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index e068a8d0adf0..e3bf57cd7423 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -82,8 +82,8 @@
};
s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
@@ -196,8 +196,8 @@
qcom,ssbi@500000 {
pmic@0 {
gpio@150 {
- wlan_default_gpios: wlan-gpios {
- pios {
+ wlan_default_gpios: wlan-gpios-state {
+ pinconf {
pins = "gpio43";
function = "normal";
bias-disable;
@@ -230,9 +230,9 @@
sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
- pinctrl-names = "default";
- pinctrl-0 = <&card_detect>;
- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&card_detect>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
sdcc4: mmc@121c0000 {
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 2638b380be20..0322cb88d448 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
@@ -39,6 +40,7 @@
led@1 {
label = "apq8064:green:user1";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
@@ -108,8 +110,8 @@
};
s4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
@@ -240,8 +242,8 @@
};
sata0: sata@29000000 {
- status = "okay";
- target-supply = <&pm8921_s4>;
+ status = "okay";
+ target-supply = <&pm8921_s4>;
};
/* OTG */
@@ -291,8 +293,8 @@
qcom,ssbi@500000 {
pmic@0 {
gpio@150 {
- wlan_default_gpios: wlan-gpios {
- pios {
+ wlan_default_gpios: wlan-gpios-state {
+ pinconf {
pins = "gpio43";
function = "normal";
bias-disable;
@@ -300,8 +302,8 @@
};
};
- notify_led: nled {
- pios {
+ notify_led: nled-state {
+ pinconf {
pins = "gpio18";
function = "normal";
bias-disable;
@@ -324,9 +326,9 @@
sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&pm8921_l6>;
- pinctrl-names = "default";
- pinctrl-0 = <&card_detect>;
- cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&card_detect>;
+ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
sdcc4: mmc@121c0000 {
@@ -341,7 +343,6 @@
status = "okay";
core-vdda-supply = <&pm8921_hdmi_switch>;
- hdmi-mux-supply = <&ext_3p3v>;
hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts
index 0cee62c7b8b0..c07c5474750d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts
@@ -23,28 +23,28 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- camera-focus {
+ key-camera-focus {
label = "camera_focus";
gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
- camera-snapshot {
+ key-camera-snapshot {
label = "camera_snapshot";
gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA>;
};
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
};
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -334,7 +334,7 @@
qcom,ssbi@500000 {
pmic@0 {
gpio@150 {
- gpio_keys_pin_a: gpio-keys-pin-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio3", "gpio4", "gpio29", "gpio35";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 34c0ba7fa358..cc3882977483 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -315,7 +315,7 @@
firmware {
scm {
- compatible = "qcom,scm-apq8064";
+ compatible = "qcom,scm-apq8064", "qcom,scm";
clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
clock-names = "core";
@@ -430,8 +430,8 @@
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
- compatible = "syscon";
- reg = <0x12100000 0x10000>;
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
};
gsbi1: gsbi@12440000 {
@@ -796,15 +796,15 @@
};
qfprom: qfprom@700000 {
- compatible = "qcom,qfprom";
- reg = <0x00700000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
+ compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
+ reg = <0x00700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
- tsens_calib: calib {
+ tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
- tsens_backup: backup_calib {
+ tsens_backup: backup_calib@414 {
reg = <0x414 0x10>;
};
};
@@ -836,22 +836,22 @@
};
l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
};
rpm@108000 {
- compatible = "qcom,rpm-apq8064";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
+ compatible = "qcom,rpm-apq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
rpmcc: clock-controller {
- compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
+ compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
#clock-cells = <1>;
};
@@ -1004,39 +1004,39 @@
};
sata_phy0: phy@1b400000 {
- compatible = "qcom,apq8064-sata-phy";
- status = "disabled";
- reg = <0x1b400000 0x200>;
- reg-names = "phy_mem";
- clocks = <&gcc SATA_PHY_CFG_CLK>;
- clock-names = "cfg";
- #phy-cells = <0>;
+ compatible = "qcom,apq8064-sata-phy";
+ status = "disabled";
+ reg = <0x1b400000 0x200>;
+ reg-names = "phy_mem";
+ clocks = <&gcc SATA_PHY_CFG_CLK>;
+ clock-names = "cfg";
+ #phy-cells = <0>;
};
sata0: sata@29000000 {
- compatible = "qcom,apq8064-ahci", "generic-ahci";
- status = "disabled";
- reg = <0x29000000 0x180>;
- interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&gcc SFAB_SATA_S_H_CLK>,
- <&gcc SATA_H_CLK>,
- <&gcc SATA_A_CLK>,
- <&gcc SATA_RXOOB_CLK>,
- <&gcc SATA_PMALIVE_CLK>;
- clock-names = "slave_iface",
- "iface",
- "bus",
- "rxoob",
- "core_pmalive";
-
- assigned-clocks = <&gcc SATA_RXOOB_CLK>,
- <&gcc SATA_PMALIVE_CLK>;
- assigned-clock-rates = <100000000>, <100000000>;
-
- phys = <&sata_phy0>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
+ compatible = "qcom,apq8064-ahci", "generic-ahci";
+ status = "disabled";
+ reg = <0x29000000 0x180>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
+ <&gcc SATA_H_CLK>,
+ <&gcc SATA_A_CLK>,
+ <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ clock-names = "slave_iface",
+ "iface",
+ "bus",
+ "rxoob",
+ "core_pmalive";
+
+ assigned-clocks = <&gcc SATA_RXOOB_CLK>,
+ <&gcc SATA_PMALIVE_CLK>;
+ assigned-clock-rates = <100000000>, <100000000>;
+
+ phys = <&sata_phy0>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
};
/* Temporary fixed regulator */
@@ -1076,18 +1076,18 @@
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
- pinctrl-names = "default";
- pinctrl-0 = <&sdcc1_pins>;
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcc1_pins>;
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@@ -1096,36 +1096,36 @@
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <192000000>;
+ max-frequency = <192000000>;
no-1-8-v;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
sdcc4: mmc@121c0000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x121c0000 0x2000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x121c0000 0x2000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <48000000>;
+ max-frequency = <48000000>;
dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
@@ -1271,6 +1271,8 @@
syscon-sfpb = <&mmss_sfpb>;
phys = <&dsi0_phy>;
phy-names = "dsi";
+ status = "disabled";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1299,9 +1301,10 @@
<0x04700300 0x200>,
<0x04700500 0x5c>;
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
- clock-names = "iface_clk", "ref";
+ clock-names = "iface", "ref";
clocks = <&mmcc DSI_M_AHB_CLK>,
<&pxo_board>;
+ status = "disabled";
};
@@ -1420,7 +1423,6 @@
"slave_iface";
phys = <&hdmi_phy>;
- phy-names = "hdmi-phy";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index da50a1a0197f..72f9255855a1 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -95,7 +95,7 @@
firmware {
scm {
- compatible = "qcom,scm";
+ compatible = "qcom,scm-apq8084", "qcom,scm";
clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
@@ -240,10 +240,10 @@
};
qfprom: qfprom@fc4bc000 {
+ compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
+ reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "qcom,qfprom";
- reg = <0xfc4bc000 0x1000>;
tsens_calib: calib@d0 {
reg = <0xd0 0x18>;
};
@@ -419,7 +419,7 @@
status = "disabled";
};
- sdhci@f9824900 {
+ mmc@f9824900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -432,7 +432,7 @@
status = "disabled";
};
- sdhci@f98a4900 {
+ mmc@f98a4900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
index 028ac8e24797..cf7da1ab177c 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"
/ {
@@ -10,17 +11,22 @@
power {
label = "ap120c-ac:green:power";
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "on";
};
wlan {
label = "ap120c-ac:green:wlan";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
support {
label = "ap120c-ac:green:support";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
index b7916fc26d68..c4f89b712fd9 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"
/ {
@@ -8,18 +9,24 @@
status: status {
label = "ap120c-ac:blue:status";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
wlan2g {
label = "ap120c-ac:green:wlan2g";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "ap120c-ac:red:wlan5g";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_RED>;
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
index 1f3b1ce82108..af9a26fb5d4a 100644
--- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi
@@ -11,7 +11,7 @@
keys {
compatible = "gpio-keys";
- reset {
+ key-reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
index faeaa6bf0def..44a9597d8bfd 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -93,7 +93,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
index d596dd1180ae..c7a6e77da272 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -56,7 +56,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <24000000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index c5da723f7674..bb307b8f678c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -156,7 +156,7 @@
firmware {
scm {
- compatible = "qcom,scm-ipq4019";
+ compatible = "qcom,scm-ipq4019", "qcom,scm";
};
};
@@ -221,7 +221,7 @@
status = "disabled";
};
- sdhci: sdhci@7824900 {
+ sdhci: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 596d129d4a95..9034f00f2bd8 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "MikroTik RB3011UiAS-RM";
@@ -187,12 +188,12 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&buttons_pins>;
pinctrl-names = "default";
- button@1 {
+ button {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
@@ -208,6 +209,7 @@
led@7 {
label = "rb3011:green:user";
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index 5c802b99e15f..411c8d63c38e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
@@ -65,19 +66,19 @@
status = "okay";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&buttons_pins>;
pinctrl-names = "default";
- button@1 {
+ button-1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
- button@2 {
+ button-2 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
@@ -107,6 +108,7 @@
led@9 {
label = "status_led_fail";
+ function = LED_FUNCTION_STATUS;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -119,6 +121,7 @@
led@53 {
label = "status_led_pass";
+ function = LED_FUNCTION_STATUS;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 808ea1862283..4b475d98343c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -723,7 +723,7 @@
};
qfprom: qfprom@700000 {
- compatible = "qcom,qfprom";
+ compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -784,7 +784,7 @@
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};
@@ -1184,16 +1184,16 @@
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@@ -1204,18 +1204,18 @@
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <192000000>;
+ max-frequency = <192000000>;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
index 10ad929759ed..49de1821ac3a 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -114,7 +114,7 @@
};
&pmicgpio {
- usb_vbus_5v_pins: usb_vbus_5v_pins {
+ usb_vbus_5v_pins: usb-vbus-5v-state {
pins = "gpio4";
function = "normal";
output-high;
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 8f0752ce1c7b..b47c86412de2 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -321,6 +321,7 @@
pmicgpio: gpio@150 {
compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
+ reg = <0x150>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
@@ -361,7 +362,7 @@
arm,primecell-periphid = <0x00051180>;
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
+ interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
@@ -381,7 +382,7 @@
status = "disabled";
reg = <0x12140000 0x2000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
+ interrupt-names = "cmd_irq";
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
@@ -411,7 +412,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8018-regulators";
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 28eca15b5712..0b5effdb269a 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -134,7 +134,7 @@
reg = <0xf9011000 0x1000>;
};
- sdhc_1: sdhci@f9824900 {
+ sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -150,7 +150,7 @@
status = "disabled";
};
- sdhc_2: sdhci@f98a4900 {
+ sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -166,7 +166,7 @@
status = "disabled";
};
- sdhc_3: sdhci@f9864900 {
+ sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 47b97daecef1..b9cded35b1cc 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -392,24 +392,24 @@
};
l2cc: clock-controller@2082000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x02082000 0x1000>;
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x02082000 0x1000>;
};
rpm: rpm@104000 {
- compatible = "qcom,rpm-msm8660";
- reg = <0x00104000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
-
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ compatible = "qcom,rpm-msm8660";
+ reg = <0x00104000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
+ compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
#clock-cells = <1>;
};
@@ -486,80 +486,80 @@
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x8000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <48000000>;
+ reg = <0x12400000 0x8000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc2: mmc@12140000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12140000 0x8000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <48000000>;
+ reg = <0x12140000 0x8000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x8000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12180000 0x8000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <48000000>;
+ max-frequency = <48000000>;
no-1-8-v;
};
sdcc4: mmc@121c0000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x121c0000 0x8000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
- max-frequency = <48000000>;
+ status = "disabled";
+ reg = <0x121c0000 0x8000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc5: mmc@12200000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12200000 0x8000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12200000 0x8000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <48000000>;
+ max-frequency = <48000000>;
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 4a2d74cf01d2..19554f3b5196 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -148,19 +148,19 @@
};
l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
};
rpm@108000 {
- compatible = "qcom,rpm-msm8960";
- reg = <0x108000 0x1000>;
- qcom,ipc = <&l2cc 0x8 2>;
+ compatible = "qcom,rpm-msm8960";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "ack", "err", "wakeup";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8921-regulators";
@@ -268,16 +268,16 @@
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x8000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
+ reg = <0x12400000 0x8000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@@ -285,18 +285,18 @@
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x8000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <4>;
+ status = "disabled";
+ reg = <0x12180000 0x8000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <192000000>;
+ max-frequency = <192000000>;
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
};
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index 9493886a5c0d..b994474f83e6 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -24,14 +24,14 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
};
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -272,7 +272,7 @@
};
&pm8941_gpios {
- gpio_keys_pin_a: gpio-keys-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio3";
function = "normal";
@@ -280,7 +280,7 @@
power-source = <PM8941_GPIO_S3>;
};
- fuelgauge_pin: fuelgauge-int {
+ fuelgauge_pin: fuelgauge-int-state {
pins = "gpio9";
function = "normal";
@@ -289,7 +289,7 @@
power-source = <PM8941_GPIO_S3>;
};
- wlan_sleep_clk_pin: wl-sleep-clk {
+ wlan_sleep_clk_pin: wl-sleep-clk-state {
pins = "gpio16";
function = "func2";
@@ -297,7 +297,7 @@
power-source = <PM8941_GPIO_S3>;
};
- wlan_regulator_pin: wl-reg-active {
+ wlan_regulator_pin: wl-reg-active-state {
pins = "gpio17";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
index 1d21de46f85c..d42b85bda33a 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
@@ -20,28 +20,28 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
};
- camera-snapshot {
+ key-camera-snapshot {
label = "camera_snapshot";
gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA>;
};
- camera-focus {
+ key-camera-focus {
label = "camera_focus";
gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -163,7 +163,7 @@
};
&pm8941_gpios {
- gpio_keys_pin_a: gpio-keys-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio3", "gpio4", "gpio5";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 814ad0b46232..d944c6272c37 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -96,7 +96,7 @@
firmware {
scm {
- compatible = "qcom,scm";
+ compatible = "qcom,scm-msm8974", "qcom,scm";
clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
@@ -436,7 +436,7 @@
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
- sdhc_1: sdhci@f9824900 {
+ sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -453,7 +453,7 @@
status = "disabled";
};
- sdhc_3: sdhci@f9864900 {
+ sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -472,7 +472,7 @@
status = "disabled";
};
- sdhc_2: sdhci@f98a4900 {
+ sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -578,7 +578,7 @@
blsp2_uart1: serial@f995d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995d000 0x1000>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -1118,10 +1118,10 @@
};
qfprom: qfprom@fc4bc000 {
+ compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
+ reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "qcom,qfprom";
- reg = <0xfc4bc000 0x1000>;
tsens_calib: calib@d0 {
reg = <0xd0 0x18>;
};
@@ -1146,6 +1146,18 @@
#interrupt-cells = <4>;
};
+ bam_dmux_dma: dma-controller@fc834000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xfc834000 0x7000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+
+ num-channels = <6>;
+ qcom,num-ees = <1>;
+ qcom,powered-remotely;
+ };
+
remoteproc_mss: remoteproc@fc880000 {
compatible = "qcom,msm8974-mss-pil";
reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
@@ -1180,6 +1192,20 @@
memory-region = <&mpss_region>;
};
+ bam_dmux: bam-dmux {
+ compatible = "qcom,bam-dmux";
+
+ interrupt-parent = <&modem_smsm>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pc", "pc-ack";
+
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pc", "pc-ack";
+
+ dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
+ dma-names = "tx", "rx";
+ };
+
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
@@ -1586,7 +1612,7 @@
status = "disabled";
- gpu_opp_table: opp_table {
+ gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-320000000 {
@@ -1603,11 +1629,12 @@
};
};
- ocmem@fdd00000 {
+ sram@fdd00000 {
compatible = "qcom,msm8974-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x180000>;
reg-names = "ctrl", "mem";
+ ranges = <0 0xfec00000 0x180000>;
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
<&mmcc OCMEMCX_OCMEMNOC_CLK>;
clock-names = "core", "iface";
@@ -1650,8 +1677,8 @@
};
};
- imem: imem@fe805000 {
- compatible = "syscon", "simple-mfd";
+ imem: sram@fe805000 {
+ compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
reg = <0xfe805000 0x1000>;
reboot-mode {
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
index 58cb2ce1e4df..e1ae99579596 100644
--- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
+++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
@@ -25,7 +25,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- camera-snapshot {
+ key-camera-snapshot {
label = "camera_snapshot";
gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_CAMERA>;
@@ -33,7 +33,7 @@
debounce-interval = <15>;
};
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
@@ -41,7 +41,7 @@
debounce-interval = <15>;
};
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
@@ -78,9 +78,9 @@
&imem {
reboot-mode {
- mode-normal = <0x77665501>;
- mode-bootloader = <0x77665500>;
- mode-recovery = <0x77665502>;
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
};
};
@@ -110,7 +110,7 @@
};
&pm8941_gpios {
- gpio_keys_pin_a: gpio-keys-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio1", "gpio2", "gpio5";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
index d6b2300a8223..aa609312caf9 100644
--- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
+++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
@@ -25,7 +25,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -33,7 +33,7 @@
debounce-interval = <15>;
};
- home-key {
+ key-home {
label = "home_key";
gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -42,7 +42,7 @@
debounce-interval = <15>;
};
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -398,7 +398,7 @@
};
&pma8084_gpios {
- gpio_keys_pin_a: gpio-keys-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio3", "gpio5";
function = "normal";
@@ -406,7 +406,7 @@
power-source = <PMA8084_GPIO_S4>;
};
- touchkey_pin: touchkey-int-pin {
+ touchkey_pin: touchkey-int-state {
pins = "gpio6";
function = "normal";
bias-disable;
@@ -414,7 +414,7 @@
power-source = <PMA8084_GPIO_S4>;
};
- touch_pin: touchscreen-int-pin {
+ touch_pin: touchscreen-int-state {
pins = "gpio8";
function = "normal";
bias-disable;
@@ -422,7 +422,7 @@
power-source = <PMA8084_GPIO_S4>;
};
- panel_en_pin: panel-en-pin {
+ panel_en_pin: panel-en-state {
pins = "gpio14";
function = "normal";
bias-pull-up;
@@ -430,7 +430,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
- wlan_sleep_clk_pin: wlan-sleep-clk-pin {
+ wlan_sleep_clk_pin: wlan-sleep-clk-state {
pins = "gpio16";
function = "func2";
@@ -439,7 +439,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
};
- panel_rst_pin: panel-rst-pin {
+ panel_rst_pin: panel-rst-state {
pins = "gpio17";
function = "normal";
bias-disable;
@@ -447,7 +447,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
- fuelgauge_pin: fuelgauge-int-pin {
+ fuelgauge_pin: fuelgauge-int-state {
pins = "gpio21";
function = "normal";
bias-disable;
diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
index 9bd8faea61a5..9fc696a7399a 100644
--- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
+++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
@@ -24,28 +24,28 @@
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pin_a>;
- volume-down {
+ key-volume-down {
label = "volume_down";
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
};
- camera-snapshot {
+ key-camera-snapshot {
label = "camera_snapshot";
gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA>;
};
- camera-focus {
+ key-camera-focus {
label = "camera_focus";
gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
- volume-up {
+ key-volume-up {
label = "volume_up";
gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
@@ -244,7 +244,7 @@
};
&pm8941_gpios {
- gpio_keys_pin_a: gpio-keys-active {
+ gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio5";
function = "normal";
@@ -252,7 +252,7 @@
power-source = <PM8941_GPIO_S3>;
};
- bt_reg_on_pin: bt-reg-on {
+ bt_reg_on_pin: bt-reg-on-state {
pins = "gpio16";
function = "normal";
@@ -260,7 +260,7 @@
power-source = <PM8941_GPIO_S3>;
};
- wlan_sleep_clk_pin: wl-sleep-clk {
+ wlan_sleep_clk_pin: wl-sleep-clk-state {
pins = "gpio17";
function = "func2";
@@ -268,7 +268,7 @@
power-source = <PM8941_GPIO_S3>;
};
- wlan_regulator_pin: wl-reg-active {
+ wlan_regulator_pin: wl-reg-active-state {
pins = "gpio18";
function = "normal";
@@ -276,7 +276,7 @@
power-source = <PM8941_GPIO_S3>;
};
- lcd_dcdc_en_pin_a: lcd-dcdc-en-active {
+ lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state {
pins = "gpio20";
function = "normal";
diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi
index 2caf71eacb52..b5cdde034d18 100644
--- a/arch/arm/boot/dts/qcom-pm8841.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8841.dtsi
@@ -24,6 +24,7 @@
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
};
};
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index cdd2bdb77b32..a68634397938 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -68,7 +68,7 @@
interrupt-controller;
#interrupt-cells = <2>;
- boost_bypass_n_pin: boost-bypass {
+ boost_bypass_n_pin: boost-bypass-state {
pins = "gpio21";
function = "normal";
};
diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi
index 6571b88d018a..9de7578a4c5f 100644
--- a/arch/arm/boot/dts/qcom-pmx55.dtsi
+++ b/arch/arm/boot/dts/qcom-pmx55.dtsi
@@ -69,6 +69,7 @@
compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
+ gpio-ranges = <&pmx55_gpios 0 0 11>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi
index 5411b833d26e..abf229a8b75a 100644
--- a/arch/arm/boot/dts/qcom-pmx65.dtsi
+++ b/arch/arm/boot/dts/qcom-pmx65.dtsi
@@ -21,9 +21,10 @@
};
pmx65_gpios: pinctrl@8800 {
- compatible = "qcom,pmx65-gpio";
+ compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pmx65_gpios 0 0 16>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 1c2b208a5670..c72540223fa9 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -206,7 +206,7 @@
blsp1_uart3: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x00831000 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc 30>,
<&gcc 9>;
clock-names = "core", "iface";
@@ -388,7 +388,7 @@
reg = <0x01fc0000 0x1000>;
};
- sdhc_1: sdhci@8804000 {
+ sdhc_1: mmc@8804000 {
compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
@@ -561,8 +561,8 @@
#interrupt-cells = <2>;
};
- imem@1468f000 {
- compatible = "simple-mfd";
+ sram@1468f000 {
+ compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
reg = <0x1468f000 0x1000>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 79dc31aa7cd1..85ea02d8362d 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -64,10 +64,6 @@
};
};
-&blsp1_uart3 {
- status = "ok";
-};
-
&apps_rsc {
pmx65-rpmh-regulators {
compatible = "qcom,pmx65-rpmh-regulators";
@@ -123,7 +119,7 @@
regulator-max-microvolt = <1300000>;
};
- ldo1 {
+ vreg_l1b_1p2: ldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -141,13 +137,13 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
- ldo4 {
+ vreg_l4b_0p88: ldo4 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
- ldo5 {
+ vreg_l5b_1p8: ldo5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -177,7 +173,7 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
- ldo10 {
+ vreg_l10b_3p08: ldo10 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -244,3 +240,52 @@
};
};
};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ /* ico and efs2 partitions are secured */
+ secure-regions = /bits/ 64 <0x500000 0x500000
+ 0xa00000 0xb00000>;
+ };
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ memory-region = <&mpss_adsp_mem>;
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+ vdda33-supply = <&vreg_l10b_3p08>;
+ vdda18-supply = <&vreg_l5b_1p8>;
+};
+
+&usb_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l4b_0p88>;
+ vdda-pll-supply = <&vreg_l1b_1p2>;
+};
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index df6f9d6288fe..7a193678b4f5 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -37,6 +37,12 @@
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
+
+ nand_clk_dummy: nand-clk-dummy {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
};
cpus {
@@ -48,9 +54,50 @@
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&apcs>;
+ power-domains = <&rpmhpd SDX65_CX_AO>;
+ power-domain-names = "rpmhpd";
+ operating-points-v2 = <&cpu_opp_table>;
};
};
+ cpu_opp_table: cpu-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-345600000 {
+ opp-hz = /bits/ 64 <345600000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sdx65", "qcom,scm";
+ };
+ };
+
+ mc_virt: interconnect-mc-virt {
+ compatible = "qcom,sdx65-mc-virt";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -87,8 +134,10 @@
};
smem_mem: memory@8fe20000 {
- no-map;
+ compatible = "qcom,smem";
reg = <0x8fe20000 0xc0000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
};
cmd_db: reserved-memory@8fee0000 {
@@ -113,6 +162,37 @@
};
};
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -124,6 +204,7 @@
reg = <0x00100000 0x001f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ #power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -137,13 +218,120 @@
status = "disabled";
};
+ usb_hsphy: phy@ff4000 {
+ compatible = "qcom,usb-snps-hs-7nm-phy";
+ reg = <0xff4000 0x120>;
+ #phy-cells = <0>;
+ status = "disabled";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_BCR>;
+ };
+
+ usb_qmpphy: phy@ff6000 {
+ compatible = "qcom,sdx65-qmp-usb3-uni-phy";
+ reg = <0x00ff6000 0x1c8>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_EN>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB3PHY_PHY_BCR>,
+ <&gcc GCC_USB3_PHY_BCR>;
+ reset-names = "phy", "common";
+
+ usb_ssphy: phy@ff6200 {
+ reg = <0x00ff6e00 0x160>,
+ <0x00ff7000 0x1ec>,
+ <0x00ff6200 0x1e00>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ };
+ };
+
+ system_noc: interconnect@1620000 {
+ compatible = "qcom,sdx65-system-noc";
+ reg = <0x01620000 0x31200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ qpic_bam: dma-controller@1b04000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x01b04000 0x1c000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ status = "disabled";
+ };
+
+ qpic_nand: nand-controller@1b30000 {
+ compatible = "qcom,sdx55-nand";
+ reg = <0x01b30000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>,
+ <&nand_clk_dummy>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;
#hwlock-cells = <1>;
};
- sdhc_1: sdhci@8804000 {
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sdx55-mpss-pas";
+ reg = <0x04080000 0x4040>;
+
+ interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SDX65_CX>,
+ <&rpmhpd SDX65_MSS>;
+ power-domain-names = "cx", "mss";
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
+ label = "mpss";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs 15>;
+ };
+ };
+
+ sdhc_1: mmc@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
@@ -156,6 +344,61 @@
status = "disabled";
};
+ mem_noc: interconnect@9680000 {
+ compatible = "qcom,sdx65-mem-noc";
+ reg = <0x09680000 0x27200>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ usb: usb@a6f8800 {
+ compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
+ reg = <0x0a6f8800 0x400>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_USB30_MSTR_AXI_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 18 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
+ "ss_phy_irq", "dm_hs_phy_irq";
+
+ power-domains = <&gcc USB30_GDSC>;
+
+ resets = <&gcc GCC_USB30_BCR>;
+
+ usb_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x1a0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_hsphy>, <&usb_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0x0c264000 0x1000>;
+ };
+
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
@@ -196,6 +439,19 @@
interrupt-controller;
};
+ imem@1468f000 {
+ compatible = "simple-mfd";
+ reg = <0x1468f000 0x1000>;
+ ranges = <0x0 0x1468f000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
reg = <0x15000000 0x40000>;
@@ -262,6 +518,12 @@
#clock-cells = <0>;
};
+ watchdog@17817000 {
+ compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
+ reg = <0x17817000 0x1000>;
+ clocks = <&sleep_clk>;
+ };
+
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -399,6 +661,11 @@
};
};
};
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
};
};