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-rw-r--r--arch/arm/boot/dts/ste-db8500.dtsi7
-rw-r--r--arch/arm/boot/dts/ste-db8520.dtsi7
-rw-r--r--arch/arm/boot/dts/ste-db9500.dtsi9
-rw-r--r--arch/arm/boot/dts/ste-ux500-samsung-codina.dts12
4 files changed, 22 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/ste-db8500.dtsi
index 344d29853bf7..b5b8ba9be55e 100644
--- a/arch/arm/boot/dts/ste-db8500.dtsi
+++ b/arch/arm/boot/dts/ste-db8500.dtsi
@@ -5,11 +5,10 @@
/ {
cpus {
cpu@300 {
- /* cpufreq controls */
operating-points = <998400 0
- 800000 0
- 400000 0
- 200000 0>;
+ 798720 0
+ 399360 0
+ 199680 0>;
};
};
diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/ste-db8520.dtsi
index 287804e9e183..0c277a6d1914 100644
--- a/arch/arm/boot/dts/ste-db8520.dtsi
+++ b/arch/arm/boot/dts/ste-db8520.dtsi
@@ -5,11 +5,10 @@
/ {
cpus {
cpu@300 {
- /* cpufreq controls */
operating-points = <1152000 0
- 800000 0
- 400000 0
- 200000 0>;
+ 798720 0
+ 399360 0
+ 199680 0>;
};
};
diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/ste-db9500.dtsi
index 0afff703191c..4273d36e881d 100644
--- a/arch/arm/boot/dts/ste-db9500.dtsi
+++ b/arch/arm/boot/dts/ste-db9500.dtsi
@@ -5,11 +5,10 @@
/ {
cpus {
cpu@300 {
- /* cpufreq controls */
- operating-points = <1152000 0
- 800000 0
- 400000 0
- 200000 0>;
+ operating-points = <998400 0
+ 798720 0
+ 399360 0
+ 199680 0>;
};
};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
index ba7986988e87..952606e607ed 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
@@ -27,6 +27,18 @@
model = "Samsung Galaxy Ace 2 (GT-I8160)";
compatible = "samsung,codina", "st-ericsson,u8500";
+ cpus {
+ cpu@300 {
+ /*
+ * This has a frequency cap at ~800 MHz in the firmware.
+ * (Changing this number here will not overclock it.)
+ */
+ operating-points = <798720 0
+ 399360 0
+ 199680 0>;
+ };
+ };
+
chosen {
stdout-path = &serial2;
};