diff options
Diffstat (limited to 'arch/arm/mach-davinci/irq.c')
| -rw-r--r-- | arch/arm/mach-davinci/irq.c | 107 |
1 files changed, 55 insertions, 52 deletions
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index eadbb9d75415..2eb3d9b9f65f 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -19,39 +19,39 @@ #include "irqs.h" -#define FIQ_REG0_OFFSET 0x0000 -#define FIQ_REG1_OFFSET 0x0004 -#define IRQ_REG0_OFFSET 0x0008 -#define IRQ_REG1_OFFSET 0x000C -#define IRQ_IRQENTRY_OFFSET 0x0014 -#define IRQ_ENT_REG0_OFFSET 0x0018 -#define IRQ_ENT_REG1_OFFSET 0x001C -#define IRQ_INCTL_REG_OFFSET 0x0020 -#define IRQ_EABASE_REG_OFFSET 0x0024 -#define IRQ_INTPRI0_REG_OFFSET 0x0030 -#define IRQ_INTPRI7_REG_OFFSET 0x004C - -static void __iomem *davinci_intc_base; -static struct irq_domain *davinci_irq_domain; - -static inline void davinci_irq_writel(unsigned long value, int offset) +#define DAVINCI_AINTC_FIQ_REG0 0x0000 +#define DAVINCI_AINTC_FIQ_REG1 0x0004 +#define DAVINCI_AINTC_IRQ_REG0 0x0008 +#define DAVINCI_AINTC_IRQ_REG1 0x000C +#define DAVINCI_AINTC_IRQ_IRQENTRY 0x0014 +#define DAVINCI_AINTC_IRQ_ENT_REG0 0x0018 +#define DAVINCI_AINTC_IRQ_ENT_REG1 0x001C +#define DAVINCI_AINTC_IRQ_INCTL_REG 0x0020 +#define DAVINCI_AINTC_IRQ_EABASE_REG 0x0024 +#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x0030 +#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x004C + +static void __iomem *davinci_aintc_base; +static struct irq_domain *davinci_aintc_irq_domain; + +static inline void davinci_aintc_writel(unsigned long value, int offset) { - __raw_writel(value, davinci_intc_base + offset); + __raw_writel(value, davinci_aintc_base + offset); } -static inline unsigned long davinci_irq_readl(int offset) +static inline unsigned long davinci_aintc_readl(int offset) { - return readl_relaxed(davinci_intc_base + offset); + return readl_relaxed(davinci_aintc_base + offset); } static __init void -davinci_irq_setup_gc(void __iomem *base, - unsigned int irq_start, unsigned int num) +davinci_aintc_setup_gc(void __iomem *base, + unsigned int irq_start, unsigned int num) { struct irq_chip_generic *gc; struct irq_chip_type *ct; - gc = irq_get_domain_generic_chip(davinci_irq_domain, irq_start); + gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start); gc->reg_base = base; gc->irq_base = irq_start; @@ -60,16 +60,16 @@ davinci_irq_setup_gc(void __iomem *base, ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->regs.ack = IRQ_REG0_OFFSET; - ct->regs.mask = IRQ_ENT_REG0_OFFSET; + ct->regs.ack = DAVINCI_AINTC_IRQ_REG0; + ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0; irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST | IRQ_NOPROBE, 0); } static asmlinkage void __exception_irq_entry -davinci_handle_irq(struct pt_regs *regs) +davinci_aintc_handle_irq(struct pt_regs *regs) { - int irqnr = davinci_irq_readl(IRQ_IRQENTRY_OFFSET); + int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY); /* * Use the formula for entry vector index generation from section @@ -78,70 +78,73 @@ davinci_handle_irq(struct pt_regs *regs) irqnr >>= 2; irqnr -= 1; - handle_domain_irq(davinci_irq_domain, irqnr, regs); + handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs); } /* ARM Interrupt Controller Initialization */ -void __init davinci_irq_init(void) +void __init davinci_aintc_init(void) { unsigned i, j; const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; int ret, irq_base; - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K); - if (WARN_ON(!davinci_intc_base)) + davinci_aintc_base = ioremap(davinci_soc_info.intc_base, SZ_4K); + if (WARN_ON(!davinci_aintc_base)) return; /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1); /* Disable all interrupts */ - davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); - davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0); + davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1); /* Interrupts disabled immediately, IRQ entry reflects all */ - davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG); /* we don't use the hardware vector table, just its entry addresses */ - davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG); /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0); + davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1); - for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + for (i = DAVINCI_AINTC_IRQ_INTPRI0_REG; + i <= DAVINCI_AINTC_IRQ_INTPRI7_REG; i += 4) { u32 pri; for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) pri |= (*davinci_def_priorities & 0x07) << j; - davinci_irq_writel(pri, i); + davinci_aintc_writel(pri, i); } irq_base = irq_alloc_descs(-1, 0, davinci_soc_info.intc_irq_num, 0); if (WARN_ON(irq_base < 0)) return; - davinci_irq_domain = irq_domain_add_legacy(NULL, + davinci_aintc_irq_domain = irq_domain_add_legacy(NULL, davinci_soc_info.intc_irq_num, irq_base, 0, &irq_domain_simple_ops, NULL); - if (WARN_ON(!davinci_irq_domain)) + if (WARN_ON(!davinci_aintc_irq_domain)) return; - ret = irq_alloc_domain_generic_chips(davinci_irq_domain, 32, 1, - "AINTC", handle_edge_irq, - IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0); + ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1, + "AINTC", handle_edge_irq, + IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0); if (WARN_ON(ret)) return; - for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04) - davinci_irq_setup_gc(davinci_intc_base + j, irq_base + i, 32); + for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; + i += 32, j += 0x04) + davinci_aintc_setup_gc(davinci_aintc_base + j, + irq_base + i, 32); irq_set_handler(DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34), handle_level_irq); - set_handle_irq(davinci_handle_irq); + set_handle_irq(davinci_aintc_handle_irq); } |