diff options
Diffstat (limited to 'arch/arm/mach-mx2/devices.c')
| -rw-r--r-- | arch/arm/mach-mx2/devices.c | 676 |
1 files changed, 270 insertions, 406 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 3d398ce09b31..b91e412f7b3e 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -31,6 +31,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/dma-mapping.h> #include <mach/irqs.h> #include <mach/hardware.h> @@ -46,65 +47,31 @@ * - i.MX21: 2 channel * - i.MX27: 3 channel */ -static struct resource mxc_spi_resources0[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource mxc_spi_resources2[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; -#endif - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; +#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_spi_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device mxc_spi_device ## n = { \ + .name = "spi_imx", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ + .resource = mxc_spi_resources ## n, \ + } -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; +DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); +DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); #ifdef CONFIG_MACH_MX27 -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; +DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); #endif /* @@ -112,104 +79,34 @@ struct platform_device mxc_spi_device2 = { * - i.MX21: 3 timers * - i.MX27: 6 timers */ - -/* We use gpt0 as system timer, so do not add a device for this one */ - -static struct resource timer1_resources[] = { - { - .start = GPT2_BASE_ADDR, - .end = GPT2_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT2, - .end = MXC_INT_GPT2, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ + static struct resource timer ## n ##_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_gpt ## n = { \ + .name = "imx_gpt", \ + .id = n, \ + .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ + .resource = timer ## n ## _resources, \ } -}; -struct platform_device mxc_gpt1 = { - .name = "imx_gpt", - .id = 1, - .num_resources = ARRAY_SIZE(timer1_resources), - .resource = timer1_resources, -}; - -static struct resource timer2_resources[] = { - { - .start = GPT3_BASE_ADDR, - .end = GPT3_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT3, - .end = MXC_INT_GPT3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt2 = { - .name = "imx_gpt", - .id = 2, - .num_resources = ARRAY_SIZE(timer2_resources), - .resource = timer2_resources, -}; +/* We use gpt1 as system timer, so do not add a device for this one */ +DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); +DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); #ifdef CONFIG_MACH_MX27 -static struct resource timer3_resources[] = { - { - .start = GPT4_BASE_ADDR, - .end = GPT4_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT4, - .end = MXC_INT_GPT4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt3 = { - .name = "imx_gpt", - .id = 3, - .num_resources = ARRAY_SIZE(timer3_resources), - .resource = timer3_resources, -}; - -static struct resource timer4_resources[] = { - { - .start = GPT5_BASE_ADDR, - .end = GPT5_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT5, - .end = MXC_INT_GPT5, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt4 = { - .name = "imx_gpt", - .id = 4, - .num_resources = ARRAY_SIZE(timer4_resources), - .resource = timer4_resources, -}; - -static struct resource timer5_resources[] = { - { - .start = GPT6_BASE_ADDR, - .end = GPT6_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT6, - .end = MXC_INT_GPT6, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt5 = { - .name = "imx_gpt", - .id = 5, - .num_resources = ARRAY_SIZE(timer5_resources), - .resource = timer5_resources, -}; +DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); +DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); +DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); #endif /* @@ -220,9 +117,9 @@ struct platform_device mxc_gpt5 = { */ static struct resource mxc_wdt_resources[] = { { - .start = WDOG_BASE_ADDR, - .end = WDOG_BASE_ADDR + 0x30, - .flags = IORESOURCE_MEM, + .start = MX2x_WDOG_BASE_ADDR, + .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, }; @@ -235,8 +132,8 @@ struct platform_device mxc_wdt = { static struct resource mxc_w1_master_resources[] = { { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .start = MX2x_OWIRE_BASE_ADDR, + .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -248,24 +145,33 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = NFC_BASE_ADDR, - .end = NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; +#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ + static struct resource pfx ## _nand_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device pfx ## _nand_device = { \ + .name = "mxc_nand", \ + .id = 0, \ + .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ + .resource = pfx ## _nand_resources, \ + } -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); +#endif /* * lcdc: @@ -275,12 +181,12 @@ struct platform_device mxc_nand_device = { */ static struct resource mxc_fb[] = { { - .start = LCDC_BASE_ADDR, - .end = LCDC_BASE_ADDR + 0xFFF, + .start = MX2x_LCDC_BASE_ADDR, + .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_LCDC, - .end = MXC_INT_LCDC, + .start = MX2x_INT_LCDC, + .end = MX2x_INT_LCDC, .flags = IORESOURCE_IRQ, } }; @@ -292,20 +198,20 @@ struct platform_device mxc_fb_device = { .num_resources = ARRAY_SIZE(mxc_fb), .resource = mxc_fb, .dev = { - .coherent_dma_mask = 0xFFFFFFFF, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; #ifdef CONFIG_MACH_MX27 static struct resource mxc_fec_resources[] = { { - .start = FEC_BASE_ADDR, - .end = FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, + .start = MX27_FEC_BASE_ADDR, + .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_FEC, - .end = MXC_INT_FEC, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_FEC, + .end = MX27_INT_FEC, + .flags = IORESOURCE_IRQ, }, }; @@ -317,55 +223,41 @@ struct platform_device mxc_fec_device = { }; #endif -static struct resource mxc_i2c_1_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_i2c_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_i2c_device ## n = { \ + .name = "imx-i2c", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ + .resource = mxc_i2c_resources ## n, \ } -}; -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; +DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); #ifdef CONFIG_MACH_MX27 -static struct resource mxc_i2c_2_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; +DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); #endif static struct resource mxc_pwm_resources[] = { { - .start = PWM_BASE_ADDR, - .end = PWM_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, + .start = MX2x_PWM_BASE_ADDR, + .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_PWM, - .end = MXC_INT_PWM, - .flags = IORESOURCE_IRQ, + .start = MX2x_INT_PWM, + .end = MX2x_INT_PWM, + .flags = IORESOURCE_IRQ, } }; @@ -376,81 +268,53 @@ struct platform_device mxc_pwm_device = { .resource = mxc_pwm_resources, }; -/* - * Resource definition for the MXC SDHC - */ -static struct resource mxc_sdhc1_resources[] = { - { - .start = SDHC1_BASE_ADDR, - .end = SDHC1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC1, - .end = MXC_INT_SDHC1, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC1, - .end = DMA_REQ_SDHC1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 mxc_sdhc1_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .dev = { - .dma_mask = &mxc_sdhc1_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), - .resource = mxc_sdhc1_resources, -}; - -static struct resource mxc_sdhc2_resources[] = { - { - .start = SDHC2_BASE_ADDR, - .end = SDHC2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC2, - .end = MXC_INT_SDHC2, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC2, - .end = DMA_REQ_SDHC2, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ + static struct resource mxc_sdhc_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, { \ + .start = dmareq, \ + .end = dmareq, \ + .flags = IORESOURCE_DMA, \ + }, \ + }; \ + \ + static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ + \ + struct platform_device mxc_sdhc_device ## n = { \ + .name = "mxc-mmc", \ + .id = n, \ + .dev = { \ + .dma_mask = &mxc_sdhc ## n ## _dmamask, \ + .coherent_dma_mask = DMA_BIT_MASK(32), \ + }, \ + .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ + .resource = mxc_sdhc_resources ## n, \ + } -static u64 mxc_sdhc2_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .dev = { - .dma_mask = &mxc_sdhc2_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), - .resource = mxc_sdhc2_resources, -}; +DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); +DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); #ifdef CONFIG_MACH_MX27 static struct resource otg_resources[] = { { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, + .start = MX27_USBOTG_BASE_ADDR, + .end = MX27_USBOTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_USB3, + .end = MX27_INT_USB3, + .flags = IORESOURCE_IRQ, }, }; -static u64 otg_dmamask = 0xffffffffUL; +static u64 otg_dmamask = DMA_BIT_MASK(32); /* OTG gadget device */ struct platform_device mxc_otg_udc_device = { @@ -458,7 +322,7 @@ struct platform_device mxc_otg_udc_device = { .id = -1, .dev = { .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffffUL, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .resource = otg_resources, .num_resources = ARRAY_SIZE(otg_resources), @@ -469,7 +333,7 @@ struct platform_device mxc_otg_host = { .name = "mxc-ehci", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .dma_mask = &otg_dmamask, }, .resource = otg_resources, @@ -478,16 +342,16 @@ struct platform_device mxc_otg_host = { /* USB host 1 */ -static u64 usbh1_dmamask = 0xffffffffUL; +static u64 usbh1_dmamask = DMA_BIT_MASK(32); static struct resource mxc_usbh1_resources[] = { { - .start = OTG_BASE_ADDR + 0x200, - .end = OTG_BASE_ADDR + 0x3ff, + .start = MX27_USBOTG_BASE_ADDR + 0x200, + .end = MX27_USBOTG_BASE_ADDR + 0x3ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, + .start = MX27_INT_USB1, + .end = MX27_INT_USB1, .flags = IORESOURCE_IRQ, }, }; @@ -496,7 +360,7 @@ struct platform_device mxc_usbh1 = { .name = "mxc-ehci", .id = 1, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .dma_mask = &usbh1_dmamask, }, .resource = mxc_usbh1_resources, @@ -504,16 +368,16 @@ struct platform_device mxc_usbh1 = { }; /* USB host 2 */ -static u64 usbh2_dmamask = 0xffffffffUL; +static u64 usbh2_dmamask = DMA_BIT_MASK(32); static struct resource mxc_usbh2_resources[] = { { - .start = OTG_BASE_ADDR + 0x400, - .end = OTG_BASE_ADDR + 0x5ff, + .start = MX27_USBOTG_BASE_ADDR + 0x400, + .end = MX27_USBOTG_BASE_ADDR + 0x5ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, + .start = MX27_INT_USB2, + .end = MX27_INT_USB2, .flags = IORESOURCE_IRQ, }, }; @@ -522,7 +386,7 @@ struct platform_device mxc_usbh2 = { .name = "mxc-ehci", .id = 2, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), .dma_mask = &usbh2_dmamask, }, .resource = mxc_usbh2_resources, @@ -530,115 +394,115 @@ struct platform_device mxc_usbh2 = { }; #endif -static struct resource imx_ssi_resources0[] = { - { - .start = SSI1_BASE_ADDR, - .end = SSI1_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI1, - .end = MXC_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI1_TX0, - .end = DMA_REQ_SSI1_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI1_RX0, - .end = DMA_REQ_SSI1_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI1_TX1, - .end = DMA_REQ_SSI1_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI1_RX1, - .end = DMA_REQ_SSI1_RX1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = SSI2_BASE_ADDR, - .end = SSI2_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI2, - .end = MXC_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI2_TX0, - .end = DMA_REQ_SSI2_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI2_RX0, - .end = DMA_REQ_SSI2_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI2_TX1, - .end = DMA_REQ_SSI2_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI2_RX1, - .end = DMA_REQ_SSI2_RX1, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ + { \ + .name = _name, \ + .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .flags = IORESOURCE_DMA, \ + } -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; +#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ + static struct resource imx_ssi_resources ## n[] = { \ + { \ + .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ + .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = MX2x_INT_SSI1, \ + .end = MX2x_INT_SSI1, \ + .flags = IORESOURCE_IRQ, \ + }, \ + DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ + DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ + DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ + DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ + }; \ + \ + struct platform_device imx_ssi_device ## n = { \ + .name = "imx-ssi", \ + .id = n, \ + .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ + .resource = imx_ssi_resources ## n, \ + } -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; +DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); +DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); /* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .irq = MXC_INT_GPIO, - .base = IO_ADDRESS(GPIO_BASE_ADDR), - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - }, { - .chip.label = "gpio-4", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), - .virtual_irq_start = MXC_GPIO_IRQ_START + 128, - }, { - .chip.label = "gpio-5", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), - .virtual_irq_start = MXC_GPIO_IRQ_START + 160, +#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ + { \ + .chip.label = "gpio-" #n, \ + .irq = _irq, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ } -}; + +#define DEFINE_MXC_GPIO_PORT(SOC, n) \ + { \ + .chip.label = "gpio-" #n, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ + } + +#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ + static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ + DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ + DEFINE_MXC_GPIO_PORT(SOC, 1), \ + DEFINE_MXC_GPIO_PORT(SOC, 2), \ + DEFINE_MXC_GPIO_PORT(SOC, 3), \ + DEFINE_MXC_GPIO_PORT(SOC, 4), \ + DEFINE_MXC_GPIO_PORT(SOC, 5), \ + } + +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_GPIO_PORTS(MX21, imx21); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_GPIO_PORTS(MX27, imx27); +#endif int __init mxc_register_gpios(void) { - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); + else +#endif + return 0; } + +#ifdef CONFIG_MACH_MX21 +static struct resource mx21_usbhc_resources[] = { + { + .start = MX21_BASE_ADDR, + .end = MX21_BASE_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = MX21_INT_USBHOST, + .end = MX21_INT_USBHOST, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx21_usbhc_device = { + .name = "imx21-hcd", + .id = 0, + .dev = { + .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mx21_usbhc_resources), + .resource = mx21_usbhc_resources, +}; +#endif + |