diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock.h')
| -rw-r--r-- | arch/arm/mach-omap2/clock.h | 221 |
1 files changed, 1 insertions, 220 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index baeaff229506..9917f793c3b6 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -20,6 +20,7 @@ #include <linux/list.h> #include <linux/clkdev.h> +#include <linux/clk-provider.h> struct omap_clk { u16 cpu; @@ -52,9 +53,6 @@ struct omap_clk { #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) -#ifdef CONFIG_COMMON_CLK -#include <linux/clk-provider.h> - struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) @@ -134,48 +132,6 @@ struct clockdomain; }; \ DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); - -#else - -struct module; -struct clk; -struct clockdomain; - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - -/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; -#endif - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) @@ -314,7 +270,6 @@ struct dpll_data { #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ #define CLOCK_CLKOUTX2 (1 << 5) -#ifdef CONFIG_COMMON_CLK /** * struct clk_hw_omap - OMAP struct clk * @node: list_head connecting this clock into the full clock list @@ -367,114 +322,6 @@ struct clk_hw_omap_ops { unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, unsigned long parent_rate); -#else -/** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children - * @rate: current clock rate - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @recalc: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled - * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. - */ -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - u8 enable_bit; - s8 usecount; - u8 fixed_div; - u8 flags; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -}; - -extern int mpurate; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); - -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; - -#endif /* CONFIG_COMMON_CLK */ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -505,15 +352,6 @@ extern struct clk dummy_ck; /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -#ifndef CONFIG_COMMON_CLK -int omap2_clk_enable(struct clk *clk); -void omap2_clk_disable(struct clk *clk); -long omap2_clk_round_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* CONFIG_COMMON_CLK */ - -#ifdef CONFIG_COMMON_CLK long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); @@ -534,37 +372,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); -#else -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap3_dpll_recalc(struct clk *clk); -unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); -int omap3_noncore_dpll_enable(struct clk *clk); -void omap3_noncore_dpll_disable(struct clk *clk); -int omap4_dpllmx_gatectrl_read(struct clk *clk); -void omap4_dpllmx_allow_gatectrl(struct clk *clk); -void omap4_dpllmx_deny_gatectrl(struct clk *clk); -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); -#endif -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk); -#else -#define omap2_clk_disable_unused NULL -#endif -#ifdef CONFIG_COMMON_CLK void omap2_init_clk_clkdm(struct clk_hw *clk); -#else -void omap2_init_clk_clkdm(struct clk *clk); -#endif void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ -#ifdef CONFIG_COMMON_CLK u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, unsigned long target_rate, u32 *new_div); @@ -575,29 +387,14 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); -#else -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, - u32 *new_div); -void omap2_init_clksel_parent(struct clk *clk); -unsigned long omap2_clksel_recalc(struct clk *clk); -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); -#endif /* clkt_iclk.c public functions */ extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -#ifdef CONFIG_COMMON_CLK u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -#else -u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); -#endif -#ifdef CONFIG_COMMON_CLK int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); @@ -611,14 +408,6 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); -#else -int omap2_dflt_clk_enable(struct clk *clk); -void omap2_dflt_clk_disable(struct clk *clk); -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val); -#endif int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -665,17 +454,9 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; -#ifndef CONFIG_COMMON_CLK -/* clocks shared between various OMAP SoCs */ -extern struct clk virt_19200000_ck; -extern struct clk virt_26000000_ck; -#endif - extern int am33xx_clk_init(void); -#ifdef CONFIG_COMMON_CLK extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); -#endif #endif |