diff options
Diffstat (limited to 'arch/arm/mach-omap2')
58 files changed, 1844 insertions, 1576 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 8111cd9ff3e5..857b1f097fd8 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS select OMAP_DM_TIMER select PINCTRL select PROC_DEVICETREE if PROC_FS + select SOC_BUS select SPARSE_IRQ select USE_OF help @@ -55,6 +56,7 @@ config SOC_HAS_REALTIME_COUNTER config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V6 default y select CPU_V6 select MULTI_IRQ_HANDLER @@ -64,6 +66,7 @@ config ARCH_OMAP2 config ARCH_OMAP3 bool "TI OMAP3" depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V7 default y select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM @@ -80,6 +83,7 @@ config ARCH_OMAP4 bool "TI OMAP4" default y depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V7 select ARCH_HAS_OPP select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_CPU_SUSPEND if PM @@ -87,6 +91,8 @@ config ARCH_OMAP4 select ARM_GIC select CACHE_L2X0 select CPU_V7 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP select LOCAL_TIMERS if SMP select OMAP_INTERCONNECT @@ -96,9 +102,12 @@ config ARCH_OMAP4 select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT select COMMON_CLK + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 config SOC_OMAP5 bool "TI OMAP5" + depends on ARCH_MULTI_V7 select ARM_CPU_SUSPEND if PM select ARM_GIC select CPU_V7 @@ -135,6 +144,7 @@ config SOC_TI81XX config SOC_AM33XX bool "AM33XX support" + depends on ARCH_MULTI_V7 default y select ARM_CPU_SUSPEND if PM select CPU_V7 @@ -408,7 +418,7 @@ config OMAP3_SDRC_AC_TIMING config OMAP4_ERRATA_I688 bool "OMAP4 errata: Async Bridge Corruption" - depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM + depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM select ARCH_HAS_BARRIERS help If a data is stalled inside asynchronous bridge because of back diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index a3e0aaa4886b..5b86423c89fa 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -38,7 +38,7 @@ #include "gpmc-smc91x.h" #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-data.h> #include "mux.h" #include "hsmmc.h" @@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void) omap_display_init(&sdp2430_dss_data); } -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 5, diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index ce812decfaca..2612eeaa5889 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -35,7 +35,7 @@ #include "common.h" #include <linux/omap-dma.h> #include <video/omapdss.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include "gpmc.h" #include "gpmc-smc91x.h" diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 9fb85908a61e..1d6c28872505 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -35,8 +35,7 @@ #include "common.h" #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include "am35xx-emac.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index af2bb219e214..bccd3e51fecb 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -41,8 +41,7 @@ #include <linux/platform_data/mtd-nand-omap2.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include "common.h" diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 53056c3b0836..12d2126a2382 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -43,8 +43,7 @@ #include "gpmc.h" #include <linux/platform_data/mtd-nand-omap2.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/input/matrix_keypad.h> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 812c829fa46f..69c0acf5aa63 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -34,7 +34,7 @@ #include <asm/mach/map.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-data.h> #include "common.h" #include "mux.h" @@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void) return 0; } -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 1, diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index bf92678a01d0..e979d48270c9 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -31,7 +31,7 @@ #include <asm/mach/arch.h> #include <video/omapdss.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include <linux/platform_data/mtd-onenand-omap2.h> #include "common.h" diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index b12fe966a7b9..8a8e505a0e90 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -41,7 +41,7 @@ #include "gpmc-smsc911x.h" #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> +#include <video/omap-panel-data.h> #include "board-flash.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index c3558f93d42c..fff141330a63 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -43,7 +43,7 @@ #include <asm/mach/flash.h> #include <video/omapdss.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include <linux/platform_data/mtd-nand-omap2.h> #include "common.h" @@ -479,7 +479,7 @@ static int __init beagle_opp_init(void) /* Initialize the omap3 opp table if not already created. */ r = omap3_opp_init(); - if (IS_ERR_VALUE(r) && (r != -EEXIST)) { + if (r < 0 && (r != -EEXIST)) { pr_err("%s: opp default init failed\n", __func__); return r; } diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 48789e0bb915..233a0d528fcf 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -51,7 +51,7 @@ #include "common.h" #include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include "soc.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 95c10b3aa678..495b989f9040 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -44,8 +44,7 @@ #include "gpmc.h" #include <linux/platform_data/mtd-nand-omap2.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include <linux/platform_data/spi-omap2-mcspi.h> diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 86bab51154ee..630833235cbc 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -47,8 +47,7 @@ #include <asm/mach/map.h> #include <video/omapdss.h> -#include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-tfp410.h> +#include <video/omap-panel-data.h> #include "common.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 0f0a97c1fcc0..3662f4d4c8ea 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); static struct omap_clk omap2420_clks[] = { /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), - CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), - CLK(NULL, "osc_ck", &osc_ck, CK_242X), - CLK(NULL, "sys_ck", &sys_ck, CK_242X), - CLK(NULL, "alt_ck", &alt_ck, CK_242X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), + CLK(NULL, "func_32k_ck", &func_32k_ck), + CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "osc_ck", &osc_ck), + CLK(NULL, "sys_ck", &sys_ck), + CLK(NULL, "alt_ck", &alt_ck), + CLK(NULL, "mcbsp_clks", &mcbsp_clks), /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), - CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), - CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), + CLK(NULL, "dpll_ck", &dpll_ck), + CLK(NULL, "apll96_ck", &apll96_ck), + CLK(NULL, "apll54_ck", &apll54_ck), /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), - CLK(NULL, "core_ck", &core_ck, CK_242X), - CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), - CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), - CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), - CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), - CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), - CLK(NULL, "emul_ck", &emul_ck, CK_242X), + CLK(NULL, "func_54m_ck", &func_54m_ck), + CLK(NULL, "core_ck", &core_ck), + CLK(NULL, "func_96m_ck", &func_96m_ck), + CLK(NULL, "func_48m_ck", &func_48m_ck), + CLK(NULL, "func_12m_ck", &func_12m_ck), + CLK(NULL, "sys_clkout_src", &sys_clkout_src), + CLK(NULL, "sys_clkout", &sys_clkout), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src), + CLK(NULL, "sys_clkout2", &sys_clkout2), + CLK(NULL, "emul_ck", &emul_ck), /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), + CLK(NULL, "mpu_ck", &mpu_ck), /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), - CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), - CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + CLK(NULL, "dsp_fck", &dsp_fck), + CLK(NULL, "dsp_ick", &dsp_ick), + CLK(NULL, "iva1_ifck", &iva1_ifck), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck), /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), + CLK(NULL, "gfx_ick", &gfx_ick), /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick, CK_242X), - CLK(NULL, "dss_ick", &dss_ick, CK_242X), - CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), - CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), - CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), + CLK("omapdss_dss", "ick", &dss_ick), + CLK(NULL, "dss_ick", &dss_ick), + CLK(NULL, "dss1_fck", &dss1_fck), + CLK(NULL, "dss2_fck", &dss2_fck), + CLK(NULL, "dss_54m_fck", &dss_54m_fck), /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), + CLK(NULL, "core_l3_ck", &core_l3_ck), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), + CLK(NULL, "usb_l4_ick", &usb_l4_ick), /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck, CK_242X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), + CLK(NULL, "l4_ck", &l4_ck), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), + CLK(NULL, "virt_prcm_set", &virt_prcm_set), /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), - CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), - CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), - CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), - CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), - CLK("omap24xxcam", "fck", &cam_fck, CK_242X), - CLK(NULL, "cam_fck", &cam_fck, CK_242X), - CLK("omap24xxcam", "ick", &cam_ick, CK_242X), - CLK(NULL, "cam_ick", &cam_ick, CK_242X), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), - CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), - CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), - CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), - CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), - CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), - CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), - CLK(NULL, "fac_ick", &fac_ick, CK_242X), - CLK(NULL, "fac_fck", &fac_fck, CK_242X), - CLK(NULL, "eac_ick", &eac_ick, CK_242X), - CLK(NULL, "eac_fck", &eac_fck, CK_242X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), - CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), - CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), - CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), - CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), - CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), - CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), - CLK(NULL, "des_ick", &des_ick, CK_242X), - CLK("omap-sham", "ick", &sha_ick, CK_242X), - CLK(NULL, "sha_ick", &sha_ick, CK_242X), - CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "rng_ick", &rng_ick, CK_242X), - CLK("omap-aes", "ick", &aes_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), - CLK(NULL, "pka_ick", &pka_ick, CK_242X), - CLK(NULL, "usb_fck", &usb_fck, CK_242X), - CLK("musb-hdrc", "fck", &osc_ck, CK_242X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), - CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), + CLK(NULL, "gpt1_ick", &gpt1_ick), + CLK(NULL, "gpt1_fck", &gpt1_fck), + CLK(NULL, "gpt2_ick", &gpt2_ick), + CLK(NULL, "gpt2_fck", &gpt2_fck), + CLK(NULL, "gpt3_ick", &gpt3_ick), + CLK(NULL, "gpt3_fck", &gpt3_fck), + CLK(NULL, "gpt4_ick", &gpt4_ick), + CLK(NULL, "gpt4_fck", &gpt4_fck), + CLK(NULL, "gpt5_ick", &gpt5_ick), + CLK(NULL, "gpt5_fck", &gpt5_fck), + CLK(NULL, "gpt6_ick", &gpt6_ick), + CLK(NULL, "gpt6_fck", &gpt6_fck), + CLK(NULL, "gpt7_ick", &gpt7_ick), + CLK(NULL, "gpt7_fck", &gpt7_fck), + CLK(NULL, "gpt8_ick", &gpt8_ick), + CLK(NULL, "gpt8_fck", &gpt8_fck), + CLK(NULL, "gpt9_ick", &gpt9_ick), + CLK(NULL, "gpt9_fck", &gpt9_fck), + CLK(NULL, "gpt10_ick", &gpt10_ick), + CLK(NULL, "gpt10_fck", &gpt10_fck), + CLK(NULL, "gpt11_ick", &gpt11_ick), + CLK(NULL, "gpt11_fck", &gpt11_fck), + CLK(NULL, "gpt12_ick", &gpt12_ick), + CLK(NULL, "gpt12_fck", &gpt12_fck), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick), + CLK(NULL, "mcspi1_ick", &mcspi1_ick), + CLK(NULL, "mcspi1_fck", &mcspi1_fck), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick), + CLK(NULL, "mcspi2_ick", &mcspi2_ick), + CLK(NULL, "mcspi2_fck", &mcspi2_fck), + CLK(NULL, "uart1_ick", &uart1_ick), + CLK(NULL, "uart1_fck", &uart1_fck), + CLK(NULL, "uart2_ick", &uart2_ick), + CLK(NULL, "uart2_fck", &uart2_fck), + CLK(NULL, "uart3_ick", &uart3_ick), + CLK(NULL, "uart3_fck", &uart3_fck), + CLK(NULL, "gpios_ick", &gpios_ick), + CLK(NULL, "gpios_fck", &gpios_fck), + CLK("omap_wdt", "ick", &mpu_wdt_ick), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), + CLK(NULL, "sync_32k_ick", &sync_32k_ick), + CLK(NULL, "wdt1_ick", &wdt1_ick), + CLK(NULL, "omapctrl_ick", &omapctrl_ick), + CLK("omap24xxcam", "fck", &cam_fck), + CLK(NULL, "cam_fck", &cam_fck), + CLK("omap24xxcam", "ick", &cam_ick), + CLK(NULL, "cam_ick", &cam_ick), + CLK(NULL, "mailboxes_ick", &mailboxes_ick), + CLK(NULL, "wdt4_ick", &wdt4_ick), + CLK(NULL, "wdt4_fck", &wdt4_fck), + CLK(NULL, "wdt3_ick", &wdt3_ick), + CLK(NULL, "wdt3_fck", &wdt3_fck), + CLK(NULL, "mspro_ick", &mspro_ick), + CLK(NULL, "mspro_fck", &mspro_fck), + CLK("mmci-omap.0", "ick", &mmc_ick), + CLK(NULL, "mmc_ick", &mmc_ick), + CLK("mmci-omap.0", "fck", &mmc_fck), + CLK(NULL, "mmc_fck", &mmc_fck), + CLK(NULL, "fac_ick", &fac_ick), + CLK(NULL, "fac_fck", &fac_fck), + CLK(NULL, "eac_ick", &eac_ick), + CLK(NULL, "eac_fck", &eac_fck), + CLK("omap_hdq.0", "ick", &hdq_ick), + CLK(NULL, "hdq_ick", &hdq_ick), + CLK("omap_hdq.0", "fck", &hdq_fck), + CLK(NULL, "hdq_fck", &hdq_fck), + CLK("omap_i2c.1", "ick", &i2c1_ick), + CLK(NULL, "i2c1_ick", &i2c1_ick), + CLK(NULL, "i2c1_fck", &i2c1_fck), + CLK("omap_i2c.2", "ick", &i2c2_ick), + CLK(NULL, "i2c2_ick", &i2c2_ick), + CLK(NULL, "i2c2_fck", &i2c2_fck), + CLK(NULL, "gpmc_fck", &gpmc_fck), + CLK(NULL, "sdma_fck", &sdma_fck), + CLK(NULL, "sdma_ick", &sdma_ick), + CLK(NULL, "sdrc_ick", &sdrc_ick), + CLK(NULL, "vlynq_ick", &vlynq_ick), + CLK(NULL, "vlynq_fck", &vlynq_fck), + CLK(NULL, "des_ick", &des_ick), + CLK("omap-sham", "ick", &sha_ick), + CLK(NULL, "sha_ick", &sha_ick), + CLK("omap_rng", "ick", &rng_ick), + CLK(NULL, "rng_ick", &rng_ick), + CLK("omap-aes", "ick", &aes_ick), + CLK(NULL, "aes_ick", &aes_ick), + CLK(NULL, "pka_ick", &pka_ick), + CLK(NULL, "usb_fck", &usb_fck), + CLK("musb-hdrc", "fck", &osc_ck), + CLK(NULL, "timer_32k_ck", &func_32k_ck), + CLK(NULL, "timer_sys_ck", &sys_ck), + CLK(NULL, "timer_ext_ck", &alt_ck), + CLK(NULL, "cpufreq_ck", &virt_prcm_set), }; @@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = { int __init omap2420_clk_init(void) { - struct omap_clk *c; - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_242X; rate_table = omap2420_rate_table; @@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void) omap2xxx_clkt_vps_check_bootloader_rates(); - for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); - c++) { - clkdev_add(&c->lk); - if (!__clk_init(NULL, c->lk.clk)) - omap2_init_clk_hw_omap_clocks(c->lk.clk); - } + omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks)); omap2xxx_clkt_vps_late_init(); diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index aed8f74ca076..5e4b037bb24c 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -1840,168 +1840,170 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); static struct omap_clk omap2430_clks[] = { /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), - CLK(NULL, "osc_ck", &osc_ck, CK_243X), - CLK("twl", "fck", &osc_ck, CK_243X), - CLK(NULL, "sys_ck", &sys_ck, CK_243X), - CLK(NULL, "alt_ck", &alt_ck, CK_243X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), + CLK(NULL, "func_32k_ck", &func_32k_ck), + CLK(NULL, "secure_32k_ck", &secure_32k_ck), + CLK(NULL, "osc_ck", &osc_ck), + CLK("twl", "fck", &osc_ck), + CLK(NULL, "sys_ck", &sys_ck), + CLK(NULL, "alt_ck", &alt_ck), + CLK(NULL, "mcbsp_clks", &mcbsp_clks), /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), - CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), - CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), + CLK(NULL, "dpll_ck", &dpll_ck), + CLK(NULL, "apll96_ck", &apll96_ck), + CLK(NULL, "apll54_ck", &apll54_ck), /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), - CLK(NULL, "core_ck", &core_ck, CK_243X), - CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), - CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), - CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), - CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), - CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), - CLK(NULL, "emul_ck", &emul_ck, CK_243X), + CLK(NULL, "func_54m_ck", &func_54m_ck), + CLK(NULL, "core_ck", &core_ck), + CLK(NULL, "func_96m_ck", &func_96m_ck), + CLK(NULL, "func_48m_ck", &func_48m_ck), + CLK(NULL, "func_12m_ck", &func_12m_ck), + CLK(NULL, "sys_clkout_src", &sys_clkout_src), + CLK(NULL, "sys_clkout", &sys_clkout), + CLK(NULL, "emul_ck", &emul_ck), /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), + CLK(NULL, "mpu_ck", &mpu_ck), /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), - CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + CLK(NULL, "dsp_fck", &dsp_fck), + CLK(NULL, "iva2_1_ick", &iva2_1_ick), /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck), + CLK(NULL, "gfx_ick", &gfx_ick), /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + CLK(NULL, "mdm_ick", &mdm_ick), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck), /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick, CK_243X), - CLK(NULL, "dss_ick", &dss_ick, CK_243X), - CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), - CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), - CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), + CLK("omapdss_dss", "ick", &dss_ick), + CLK(NULL, "dss_ick", &dss_ick), + CLK(NULL, "dss1_fck", &dss1_fck), + CLK(NULL, "dss2_fck", &dss2_fck), + CLK(NULL, "dss_54m_fck", &dss_54m_fck), /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), + CLK(NULL, "core_l3_ck", &core_l3_ck), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck), + CLK(NULL, "usb_l4_ick", &usb_l4_ick), /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck, CK_243X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), + CLK(NULL, "l4_ck", &l4_ck), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), + CLK(NULL, "virt_prcm_set", &virt_prcm_set), /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), - CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), - CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), - CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), - CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), - CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), - CLK(NULL, "icr_ick", &icr_ick, CK_243X), - CLK("omap24xxcam", "fck", &cam_fck, CK_243X), - CLK(NULL, "cam_fck", &cam_fck, CK_243X), - CLK("omap24xxcam", "ick", &cam_ick, CK_243X), - CLK(NULL, "cam_ick", &cam_ick, CK_243X), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), - CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), - CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), - CLK(NULL, "fac_ick", &fac_ick, CK_243X), - CLK(NULL, "fac_fck", &fac_fck, CK_243X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), - CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), - CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), - CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), - CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), - CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), - CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), - CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), - CLK(NULL, "des_ick", &des_ick, CK_243X), - CLK("omap-sham", "ick", &sha_ick, CK_243X), - CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "rng_ick", &rng_ick, CK_243X), - CLK("omap-aes", "ick", &aes_ick, CK_243X), - CLK(NULL, "pka_ick", &pka_ick, CK_243X), - CLK(NULL, "usb_fck", &usb_fck, CK_243X), - CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), - CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), - CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), - CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), - CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), - CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), - CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), - CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), - CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), - CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), - CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), - CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), + CLK(NULL, "gpt1_ick", &gpt1_ick), + CLK(NULL, "gpt1_fck", &gpt1_fck), + CLK(NULL, "gpt2_ick", &gpt2_ick), + CLK(NULL, "gpt2_fck", &gpt2_fck), + CLK(NULL, "gpt3_ick", &gpt3_ick), + CLK(NULL, "gpt3_fck", &gpt3_fck), + CLK(NULL, "gpt4_ick", &gpt4_ick), + CLK(NULL, "gpt4_fck", &gpt4_fck), + CLK(NULL, "gpt5_ick", &gpt5_ick), + CLK(NULL, "gpt5_fck", &gpt5_fck), + CLK(NULL, "gpt6_ick", &gpt6_ick), + CLK(NULL, "gpt6_fck", &gpt6_fck), + CLK(NULL, "gpt7_ick", &gpt7_ick), + CLK(NULL, "gpt7_fck", &gpt7_fck), + CLK(NULL, "gpt8_ick", &gpt8_ick), + CLK(NULL, "gpt8_fck", &gpt8_fck), + CLK(NULL, "gpt9_ick", &gpt9_ick), + CLK(NULL, "gpt9_fck", &gpt9_fck), + CLK(NULL, "gpt10_ick", &gpt10_ick), + CLK(NULL, "gpt10_fck", &gpt10_fck), + CLK(NULL, "gpt11_ick", &gpt11_ick), + CLK(NULL, "gpt11_fck", &gpt11_fck), + CLK(NULL, "gpt12_ick", &gpt12_ick), + CLK(NULL, "gpt12_fck", &gpt12_fck), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick), + CLK(NULL, "mcspi1_ick", &mcspi1_ick), + CLK(NULL, "mcspi1_fck", &mcspi1_fck), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick), + CLK(NULL, "mcspi2_ick", &mcspi2_ick), + CLK(NULL, "mcspi2_fck", &mcspi2_fck), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick), + CLK(NULL, "mcspi3_ick", &mcspi3_ick), + CLK(NULL, "mcspi3_fck", &mcspi3_fck), + CLK(NULL, "uart1_ick", &uart1_ick), + CLK(NULL, "uart1_fck", &uart1_fck), + CLK(NULL, "uart2_ick", &uart2_ick), + CLK(NULL, "uart2_fck", &uart2_fck), + CLK(NULL, "uart3_ick", &uart3_ick), + CLK(NULL, "uart3_fck", &uart3_fck), + CLK(NULL, "gpios_ick", &gpios_ick), + CLK(NULL, "gpios_fck", &gpios_fck), + CLK("omap_wdt", "ick", &mpu_wdt_ick), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck), + CLK(NULL, "sync_32k_ick", &sync_32k_ick), + CLK(NULL, "wdt1_ick", &wdt1_ick), + CLK(NULL, "omapctrl_ick", &omapctrl_ick), + CLK(NULL, "icr_ick", &icr_ick), + CLK("omap24xxcam", "fck", &cam_fck), + CLK(NULL, "cam_fck", &cam_fck), + CLK("omap24xxcam", "ick", &cam_ick), + CLK(NULL, "cam_ick", &cam_ick), + CLK(NULL, "mailboxes_ick", &mailboxes_ick), + CLK(NULL, "wdt4_ick", &wdt4_ick), + CLK(NULL, "wdt4_fck", &wdt4_fck), + CLK(NULL, "mspro_ick", &mspro_ick), + CLK(NULL, "mspro_fck", &mspro_fck), + CLK(NULL, "fac_ick", &fac_ick), + CLK(NULL, "fac_fck", &fac_fck), + CLK("omap_hdq.0", "ick", &hdq_ick), + CLK(NULL, "hdq_ick", &hdq_ick), + CLK("omap_hdq.1", "fck", &hdq_fck), + CLK(NULL, "hdq_fck", &hdq_fck), + CLK("omap_i2c.1", "ick", &i2c1_ick), + CLK(NULL, "i2c1_ick", &i2c1_ick), + CLK(NULL, "i2chs1_fck", &i2chs1_fck), + CLK("omap_i2c.2", "ick", &i2c2_ick), + CLK(NULL, "i2c2_ick", &i2c2_ick), + CLK(NULL, "i2chs2_fck", &i2chs2_fck), + CLK(NULL, "gpmc_fck", &gpmc_fck), + CLK(NULL, "sdma_fck", &sdma_fck), + CLK(NULL, "sdma_ick", &sdma_ick), + CLK(NULL, "sdrc_ick", &sdrc_ick), + CLK(NULL, "des_ick", &des_ick), + CLK("omap-sham", "ick", &sha_ick), + CLK(NULL, "sha_ick", &sha_ick), + CLK("omap_rng", "ick", &rng_ick), + CLK(NULL, "rng_ick", &rng_ick), + CLK("omap-aes", "ick", &aes_ick), + CLK(NULL, "aes_ick", &aes_ick), + CLK(NULL, "pka_ick", &pka_ick), + CLK(NULL, "usb_fck", &usb_fck), + CLK("musb-omap2430", "ick", &usbhs_ick), + CLK(NULL, "usbhs_ick", &usbhs_ick), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick), + CLK(NULL, "mmchs1_ick", &mmchs1_ick), + CLK(NULL, "mmchs1_fck", &mmchs1_fck), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick), + CLK(NULL, "mmchs2_ick", &mmchs2_ick), + CLK(NULL, "mmchs2_fck", &mmchs2_fck), + CLK(NULL, "gpio5_ick", &gpio5_ick), + CLK(NULL, "gpio5_fck", &gpio5_fck), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick), + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck), + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck), + CLK(NULL, "timer_32k_ck", &func_32k_ck), + CLK(NULL, "timer_sys_ck", &sys_ck), + CLK(NULL, "timer_ext_ck", &alt_ck), + CLK(NULL, "cpufreq_ck", &virt_prcm_set), }; static const char *enable_init_clks[] = { @@ -2019,8 +2021,6 @@ static const char *enable_init_clks[] = { int __init omap2430_clk_init(void) { - struct omap_clk *c; - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; cpu_mask = RATE_IN_243X; rate_table = omap2430_rate_table; @@ -2029,12 +2029,7 @@ int __init omap2430_clk_init(void) omap2xxx_clkt_vps_check_bootloader_rates(); - for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); - c++) { - clkdev_add(&c->lk); - if (!__clk_init(NULL, c->lk.clk)) - omap2_init_clk_hw_omap_clocks(c->lk.clk); - } + omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks)); omap2xxx_clkt_vps_late_init(); diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 476b82066cb6..6ebc7803bc3e 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -413,6 +413,14 @@ static struct clk smartreflex1_fck; DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); +static struct clk sha0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); +DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk aes0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); +DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); + /* * Modules clock nodes * @@ -838,80 +846,82 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); * clkdev */ static struct omap_clk am33xx_clks[] = { - CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), - CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), - CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), - CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), - CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), - CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), - CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), - CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), - CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), - CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), - CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), - CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), - CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), - CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), - CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), - CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), - CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), - CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), - CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), - CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), - CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), - CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), - CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), - CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), - CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), - CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), - CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), - CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), - CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), - CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), - CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), - CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), - CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), - CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), - CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "clk_32768_ck", &clk_32768_ck), + CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_24000000_ck", &virt_24000000_ck), + CLK(NULL, "virt_25000000_ck", &virt_25000000_ck), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), + CLK(NULL, "tclkin_ck", &tclkin_ck), + CLK(NULL, "dpll_core_ck", &dpll_core_ck), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), + CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck), + CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), + CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), + CLK("cpu0", NULL, &dpll_mpu_ck), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), + CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), + CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck), + CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck), + CLK(NULL, "dpll_disp_ck", &dpll_disp_ck), + CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck), + CLK(NULL, "dpll_per_ck", &dpll_per_ck), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), + CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck), + CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck), + CLK(NULL, "adc_tsc_fck", &adc_tsc_fck), + CLK(NULL, "cefuse_fck", &cefuse_fck), + CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck), + CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick), + CLK(NULL, "dcan0_fck", &dcan0_fck), + CLK("481cc000.d_can", NULL, &dcan0_fck), + CLK(NULL, "dcan1_fck", &dcan1_fck), + CLK("481d0000.d_can", NULL, &dcan1_fck), + CLK(NULL, "debugss_ick", &debugss_ick), + CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), + CLK(NULL, "mcasp0_fck", &mcasp0_fck), + CLK(NULL, "mcasp1_fck", &mcasp1_fck), + CLK(NULL, "mmu_fck", &mmu_fck), + CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), + CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), + CLK(NULL, "sha0_fck", &sha0_fck), + CLK(NULL, "aes0_fck", &aes0_fck), + CLK(NULL, "timer1_fck", &timer1_fck), + CLK(NULL, "timer2_fck", &timer2_fck), + CLK(NULL, "timer3_fck", &timer3_fck), + CLK(NULL, "timer4_fck", &timer4_fck), + CLK(NULL, "timer5_fck", &timer5_fck), + CLK(NULL, "timer6_fck", &timer6_fck), + CLK(NULL, "timer7_fck", &timer7_fck), + CLK(NULL, "usbotg_fck", &usbotg_fck), + CLK(NULL, "ieee5000_fck", &ieee5000_fck), + CLK(NULL, "wdt1_fck", &wdt1_fck), + CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk), + CLK(NULL, "l3_gclk", &l3_gclk), + CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck), + CLK(NULL, "l4hs_gclk", &l4hs_gclk), + CLK(NULL, "l3s_gclk", &l3s_gclk), + CLK(NULL, "l4fw_gclk", &l4fw_gclk), + CLK(NULL, "l4ls_gclk", &l4ls_gclk), + CLK(NULL, "clk_24mhz", &clk_24mhz), + CLK(NULL, "sysclk_div_ck", &sysclk_div_ck), + CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk), + CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk), + CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck), + CLK(NULL, "gpio0_dbclk", &gpio0_dbclk), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), + CLK(NULL, "lcd_gclk", &lcd_gclk), + CLK(NULL, "mmc_clk", &mmc_clk), + CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck), + CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck), + CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck), + CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), + CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), + CLK(NULL, "timer_sys_ck", &sys_clkin_ck), }; @@ -926,21 +936,10 @@ static const char *enable_init_clks[] = { int __init am33xx_clk_init(void) { - struct omap_clk *c; - u32 cpu_clkflg; - - if (soc_is_am33xx()) { + if (soc_is_am33xx()) cpu_mask = RATE_IN_AM33XX; - cpu_clkflg = CK_AM33XX; - } - for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - if (!__clk_init(NULL, c->lk.clk)) - omap2_init_clk_hw_omap_clocks(c->lk.clk); - } - } + omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); omap2_clk_disable_autoidle_all(); @@ -958,6 +957,14 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; } diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 4579c3c5338f..45cd26430d1f 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -3219,289 +3219,327 @@ static struct clk_hw_omap wdt3_ick_hw = { DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); /* - * clkdev + * clocks specific to omap3430es1 + */ +static struct omap_clk omap3430es1_clks[] = { + CLK(NULL, "gfx_l3_ck", &gfx_l3_ck), + CLK(NULL, "gfx_l3_fck", &gfx_l3_fck), + CLK(NULL, "gfx_l3_ick", &gfx_l3_ick), + CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck), + CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck), + CLK(NULL, "d2d_26m_fck", &d2d_26m_fck), + CLK(NULL, "fshostusb_fck", &fshostusb_fck), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1), + CLK(NULL, "fac_ick", &fac_ick), + CLK(NULL, "ssi_ick", &ssi_ick_3430es1), + CLK(NULL, "usb_l4_ick", &usb_l4_ick), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1), + CLK("omapdss_dss", "ick", &dss_ick_3430es1), + CLK(NULL, "dss_ick", &dss_ick_3430es1), +}; + +/* + * clocks specific to am35xx + */ +static struct omap_clk am35xx_clks[] = { + CLK(NULL, "ipss_ick", &ipss_ick), + CLK(NULL, "rmii_ck", &rmii_ck), + CLK(NULL, "pclk_ck", &pclk_ck), + CLK(NULL, "emac_ick", &emac_ick), + CLK(NULL, "emac_fck", &emac_fck), + CLK("davinci_emac.0", NULL, &emac_ick), + CLK("davinci_mdio.0", NULL, &emac_fck), + CLK("vpfe-capture", "master", &vpfe_ick), + CLK("vpfe-capture", "slave", &vpfe_fck), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx), + CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx), + CLK(NULL, "hecc_ck", &hecc_ck), + CLK(NULL, "uart4_ick", &uart4_ick_am35xx), + CLK(NULL, "uart4_fck", &uart4_fck_am35xx), +}; + +/* + * clocks specific to omap36xx + */ +static struct omap_clk omap36xx_clks[] = { + CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck), + CLK(NULL, "uart4_fck", &uart4_fck), +}; + +/* + * clocks common to omap36xx omap34xx + */ +static struct omap_clk omap34xx_omap36xx_clks[] = { + CLK(NULL, "aes1_ick", &aes1_ick), + CLK("omap_rng", "ick", &rng_ick), + CLK(NULL, "sha11_ick", &sha11_ick), + CLK(NULL, "des1_ick", &des1_ick), + CLK(NULL, "cam_mclk", &cam_mclk), + CLK(NULL, "cam_ick", &cam_ick), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck), + CLK(NULL, "security_l3_ick", &security_l3_ick), + CLK(NULL, "pka_ick", &pka_ick), + CLK(NULL, "icr_ick", &icr_ick), + CLK("omap-aes", "ick", &aes2_ick), + CLK("omap-sham", "ick", &sha12_ick), + CLK(NULL, "des2_ick", &des2_ick), + CLK(NULL, "mspro_ick", &mspro_ick), + CLK(NULL, "mailboxes_ick", &mailboxes_ick), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick), + CLK(NULL, "sr1_fck", &sr1_fck), + CLK(NULL, "sr2_fck", &sr2_fck), + CLK(NULL, "sr_l4_ick", &sr_l4_ick), + CLK(NULL, "security_l4_ick2", &security_l4_ick2), + CLK(NULL, "wkup_l4_ick", &wkup_l4_ick), + CLK(NULL, "dpll2_fck", &dpll2_fck), + CLK(NULL, "iva2_ck", &iva2_ck), + CLK(NULL, "modem_fck", &modem_fck), + CLK(NULL, "sad2d_ick", &sad2d_ick), + CLK(NULL, "mad2d_ick", &mad2d_ick), + CLK(NULL, "mspro_fck", &mspro_fck), + CLK(NULL, "dpll2_ck", &dpll2_ck), + CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck), +}; + +/* + * clocks common to omap36xx and omap3430es2plus + */ +static struct omap_clk omap36xx_omap3430es2plus_clks[] = { + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2), + CLK(NULL, "ssi_ick", &ssi_ick_3430es2), + CLK(NULL, "usim_fck", &usim_fck), + CLK(NULL, "usim_ick", &usim_ick), +}; + +/* + * clocks common to am35xx omap36xx and omap3430es2plus + */ +static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck), + CLK(NULL, "dpll5_ck", &dpll5_ck), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck), + CLK(NULL, "sgx_fck", &sgx_fck), + CLK(NULL, "sgx_ick", &sgx_ick), + CLK(NULL, "cpefuse_fck", &cpefuse_fck), + CLK(NULL, "ts_fck", &ts_fck), + CLK(NULL, "usbtll_fck", &usbtll_fck), + CLK("usbhs_omap", "usbtll_fck", &usbtll_fck), + CLK("usbhs_tll", "usbtll_fck", &usbtll_fck), + CLK(NULL, "usbtll_ick", &usbtll_ick), + CLK("usbhs_omap", "usbtll_ick", &usbtll_ick), + CLK("usbhs_tll", "usbtll_ick", &usbtll_ick), + CLK("omap_hsmmc.2", "ick", &mmchs3_ick), + CLK(NULL, "mmchs3_ick", &mmchs3_ick), + CLK(NULL, "mmchs3_fck", &mmchs3_fck), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2), + CLK("omapdss_dss", "ick", &dss_ick_3430es2), + CLK(NULL, "dss_ick", &dss_ick_3430es2), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), + CLK(NULL, "usbhost_ick", &usbhost_ick), + CLK("usbhs_omap", "usbhost_ick", &usbhost_ick), +}; + +/* + * common clocks */ static struct omap_clk omap3xxx_clks[] = { - CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), - CLK("twl", "fck", &osc_sys_ck, CK_3XXX), - CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), - CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), - CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), - CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), - CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), - CLK(NULL, "core_ck", &core_ck, CK_3XXX), - CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), - CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), - CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), - CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), - CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), - CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), - CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), - CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), - CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), - CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), - CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), - CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), - CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), - CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), - CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), - CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), - CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), - CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), - CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), - CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), - CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), - CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), - CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), - CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), - CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), - CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), - CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), - CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), - CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), - CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), - CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), - CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), - CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), - CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), - CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), - CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), - CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), - CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), - CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), - CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), - CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), - CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), - CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), - CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), - CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), - CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), - CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), - CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), - CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), - CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), - CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), - CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), - CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), - CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), - CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), - CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), - CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), - CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), - CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), - CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), - CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), - CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), - CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), - CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), - CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), - CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), - CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), - CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), - CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), - CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), - CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), - CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), - CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), - CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), - CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), - CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), - CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), - CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), - CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), - CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), - CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), - CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), - CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), - CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), - CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), - CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), - CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), - CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), - CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), - CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), - CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), - CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), - CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), - CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), - CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), - CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), - CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), - CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), - CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), - CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), - CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), - CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), - CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), - CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), - CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), - CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), - CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), - CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), - CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), - CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), - CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), - CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), - CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), - CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), - CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), - CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), - CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), - CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), - CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), - CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), - CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), - CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), - CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), - CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), - CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), - CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), - CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), + CLK(NULL, "apb_pclk", &dummy_apb_pclk), + CLK(NULL, "omap_32k_fck", &omap_32k_fck), + CLK(NULL, "virt_12m_ck", &virt_12m_ck), + CLK(NULL, "virt_13m_ck", &virt_13m_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), + CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck), + CLK(NULL, "osc_sys_ck", &osc_sys_ck), + CLK("twl", "fck", &osc_sys_ck), + CLK(NULL, "sys_ck", &sys_ck), + CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck), + CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck), + CLK(NULL, "sys_altclk", &sys_altclk), + CLK(NULL, "mcbsp_clks", &mcbsp_clks), + CLK(NULL, "sys_clkout1", &sys_clkout1), + CLK(NULL, "dpll1_ck", &dpll1_ck), + CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck), + CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck), + CLK(NULL, "dpll3_ck", &dpll3_ck), + CLK(NULL, "core_ck", &core_ck), + CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck), + CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck), + CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck), + CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck), + CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck), + CLK(NULL, "dpll4_ck", &dpll4_ck), + CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck), + CLK(NULL, "omap_96m_fck", &omap_96m_fck), + CLK(NULL, "cm_96m_fck", &cm_96m_fck), + CLK(NULL, "omap_54m_fck", &omap_54m_fck), + CLK(NULL, "omap_48m_fck", &omap_48m_fck), + CLK(NULL, "omap_12m_fck", &omap_12m_fck), + CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck), + CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck), + CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck), + CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck), + CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck), + CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck), + CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck), + CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck), + CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck), + CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck), + CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck), + CLK(NULL, "clkout2_src_ck", &clkout2_src_ck), + CLK(NULL, "sys_clkout2", &sys_clkout2), + CLK(NULL, "corex2_fck", &corex2_fck), + CLK(NULL, "dpll1_fck", &dpll1_fck), + CLK(NULL, "mpu_ck", &mpu_ck), + CLK(NULL, "arm_fck", &arm_fck), + CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck), + CLK(NULL, "l3_ick", &l3_ick), + CLK(NULL, "l4_ick", &l4_ick), + CLK(NULL, "rm_ick", &rm_ick), + CLK(NULL, "gpt10_fck", &gpt10_fck), + CLK(NULL, "gpt11_fck", &gpt11_fck), + CLK(NULL, "core_96m_fck", &core_96m_fck), + CLK(NULL, "mmchs2_fck", &mmchs2_fck), + CLK(NULL, "mmchs1_fck", &mmchs1_fck), + CLK(NULL, "i2c3_fck", &i2c3_fck), + CLK(NULL, "i2c2_fck", &i2c2_fck), + CLK(NULL, "i2c1_fck", &i2c1_fck), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck), + CLK(NULL, "core_48m_fck", &core_48m_fck), + CLK(NULL, "mcspi4_fck", &mcspi4_fck), + CLK(NULL, "mcspi3_fck", &mcspi3_fck), + CLK(NULL, "mcspi2_fck", &mcspi2_fck), + CLK(NULL, "mcspi1_fck", &mcspi1_fck), + CLK(NULL, "uart2_fck", &uart2_fck), + CLK(NULL, "uart1_fck", &uart1_fck), + CLK(NULL, "core_12m_fck", &core_12m_fck), + CLK("omap_hdq.0", "fck", &hdq_fck), + CLK(NULL, "hdq_fck", &hdq_fck), + CLK(NULL, "core_l3_ick", &core_l3_ick), + CLK(NULL, "sdrc_ick", &sdrc_ick), + CLK(NULL, "gpmc_fck", &gpmc_fck), + CLK(NULL, "core_l4_ick", &core_l4_ick), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick), + CLK(NULL, "mmchs2_ick", &mmchs2_ick), + CLK(NULL, "mmchs1_ick", &mmchs1_ick), + CLK("omap_hdq.0", "ick", &hdq_ick), + CLK(NULL, "hdq_ick", &hdq_ick), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick), + CLK(NULL, "mcspi4_ick", &mcspi4_ick), + CLK(NULL, "mcspi3_ick", &mcspi3_ick), + CLK(NULL, "mcspi2_ick", &mcspi2_ick), + CLK(NULL, "mcspi1_ick", &mcspi1_ick), + CLK("omap_i2c.3", "ick", &i2c3_ick), + CLK("omap_i2c.2", "ick", &i2c2_ick), + CLK("omap_i2c.1", "ick", &i2c1_ick), + CLK(NULL, "i2c3_ick", &i2c3_ick), + CLK(NULL, "i2c2_ick", &i2c2_ick), + CLK(NULL, "i2c1_ick", &i2c1_ick), + CLK(NULL, "uart2_ick", &uart2_ick), + CLK(NULL, "uart1_ick", &uart1_ick), + CLK(NULL, "gpt11_ick", &gpt11_ick), + CLK(NULL, "gpt10_ick", &gpt10_ick), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), + CLK(NULL, "omapctrl_ick", &omapctrl_ick), + CLK(NULL, "dss_tv_fck", &dss_tv_fck), + CLK(NULL, "dss_96m_fck", &dss_96m_fck), + CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck), + CLK(NULL, "utmi_p1_gfclk", &dummy_ck), + CLK(NULL, "utmi_p2_gfclk", &dummy_ck), + CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), + CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck), + CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck), + CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck), + CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck), + CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), + CLK(NULL, "init_60m_fclk", &dummy_ck), + CLK(NULL, "gpt1_fck", &gpt1_fck), + CLK(NULL, "aes2_ick", &aes2_ick), + CLK(NULL, "wkup_32k_fck", &wkup_32k_fck), + CLK(NULL, "gpio1_dbck", &gpio1_dbck), + CLK(NULL, "sha12_ick", &sha12_ick), + CLK(NULL, "wdt2_fck", &wdt2_fck), + CLK("omap_wdt", "ick", &wdt2_ick), + CLK(NULL, "wdt2_ick", &wdt2_ick), + CLK(NULL, "wdt1_ick", &wdt1_ick), + CLK(NULL, "gpio1_ick", &gpio1_ick), + CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick), + CLK(NULL, "gpt12_ick", &gpt12_ick), + CLK(NULL, "gpt1_ick", &gpt1_ick), + CLK(NULL, "per_96m_fck", &per_96m_fck), + CLK(NULL, "per_48m_fck", &per_48m_fck), + CLK(NULL, "uart3_fck", &uart3_fck), + CLK(NULL, "gpt2_fck", &gpt2_fck), + CLK(NULL, "gpt3_fck", &gpt3_fck), + CLK(NULL, "gpt4_fck", &gpt4_fck), + CLK(NULL, "gpt5_fck", &gpt5_fck), + CLK(NULL, "gpt6_fck", &gpt6_fck), + CLK(NULL, "gpt7_fck", &gpt7_fck), + CLK(NULL, "gpt8_fck", &gpt8_fck), + CLK(NULL, "gpt9_fck", &gpt9_fck), + CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck), + CLK(NULL, "gpio6_dbck", &gpio6_dbck), + CLK(NULL, "gpio5_dbck", &gpio5_dbck), + CLK(NULL, "gpio4_dbck", &gpio4_dbck), + CLK(NULL, "gpio3_dbck", &gpio3_dbck), + CLK(NULL, "gpio2_dbck", &gpio2_dbck), + CLK(NULL, "wdt3_fck", &wdt3_fck), + CLK(NULL, "per_l4_ick", &per_l4_ick), + CLK(NULL, "gpio6_ick", &gpio6_ick), + CLK(NULL, "gpio5_ick", &gpio5_ick), + CLK(NULL, "gpio4_ick", &gpio4_ick), + CLK(NULL, "gpio3_ick", &gpio3_ick), + CLK(NULL, "gpio2_ick", &gpio2_ick), + CLK(NULL, "wdt3_ick", &wdt3_ick), + CLK(NULL, "uart3_ick", &uart3_ick), + CLK(NULL, "uart4_ick", &uart4_ick), + CLK(NULL, "gpt9_ick", &gpt9_ick), + CLK(NULL, "gpt8_ick", &gpt8_ick), + CLK(NULL, "gpt7_ick", &gpt7_ick), + CLK(NULL, "gpt6_ick", &gpt6_ick), + CLK(NULL, "gpt5_ick", &gpt5_ick), + CLK(NULL, "gpt4_ick", &gpt4_ick), + CLK(NULL, "gpt3_ick", &gpt3_ick), + CLK(NULL, "gpt2_ick", &gpt2_ick), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), + CLK(NULL, "mcbsp4_ick", &mcbsp2_ick), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), + CLK(NULL, "mcbsp2_ick", &mcbsp4_ick), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), + CLK("etb", "emu_src_ck", &emu_src_ck), + CLK(NULL, "emu_src_ck", &emu_src_ck), + CLK(NULL, "pclk_fck", &pclk_fck), + CLK(NULL, "pclkx2_fck", &pclkx2_fck), + CLK(NULL, "atclk_fck", &atclk_fck), + CLK(NULL, "traceclk_src_fck", &traceclk_src_fck), + CLK(NULL, "traceclk_fck", &traceclk_fck), + CLK(NULL, "secure_32k_fck", &secure_32k_fck), + CLK(NULL, "gpt12_fck", &gpt12_fck), + CLK(NULL, "wdt1_fck", &wdt1_fck), + CLK(NULL, "timer_32k_ck", &omap_32k_fck), + CLK(NULL, "timer_sys_ck", &sys_ck), + CLK(NULL, "cpufreq_ck", &dpll1_ck), }; static const char *enable_init_clks[] = { @@ -3512,8 +3550,27 @@ static const char *enable_init_clks[] = { int __init omap3xxx_clk_init(void) { - struct omap_clk *c; - u32 cpu_clkflg = 0; + if (omap3_has_192mhz_clk()) + omap_96m_alwon_fck = omap_96m_alwon_fck_3630; + + if (cpu_is_omap3630()) { + dpll3_m3x2_ck = dpll3_m3x2_ck_3630; + dpll4_m2x2_ck = dpll4_m2x2_ck_3630; + dpll4_m3x2_ck = dpll4_m3x2_ck_3630; + dpll4_m4x2_ck = dpll4_m4x2_ck_3630; + dpll4_m5x2_ck = dpll4_m5x2_ck_3630; + dpll4_m6x2_ck = dpll4_m6x2_ck_3630; + } + + /* + * XXX This type of dynamic rewriting of the clock tree is + * deprecated and should be revised soon. + */ + if (cpu_is_omap3630()) + dpll4_dd = dpll4_dd_3630; + else + dpll4_dd = dpll4_dd_34xx; + /* * 3505 must be tested before 3517, since 3517 returns true @@ -3523,13 +3580,20 @@ int __init omap3xxx_clk_init(void) */ if (soc_is_am35xx()) { cpu_mask = RATE_IN_34XX; - cpu_clkflg = CK_AM35XX; + omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks)); + omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, + ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); + omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); - cpu_clkflg = CK_36XX; - } else if (cpu_is_ti816x()) { - cpu_mask = RATE_IN_TI816X; - cpu_clkflg = CK_TI816X; + omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks)); + omap_clocks_register(omap36xx_omap3430es2plus_clks, + ARRAY_SIZE(omap36xx_omap3430es2plus_clks)); + omap_clocks_register(omap34xx_omap36xx_clks, + ARRAY_SIZE(omap34xx_omap36xx_clks)); + omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, + ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); + omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); } else if (soc_is_am33xx()) { cpu_mask = RATE_IN_AM33XX; } else if (cpu_is_ti814x()) { @@ -3537,49 +3601,32 @@ int __init omap3xxx_clk_init(void) } else if (cpu_is_omap34xx()) { if (omap_rev() == OMAP3430_REV_ES1_0) { cpu_mask = RATE_IN_3430ES1; - cpu_clkflg = CK_3430ES1; + omap_clocks_register(omap3430es1_clks, + ARRAY_SIZE(omap3430es1_clks)); + omap_clocks_register(omap34xx_omap36xx_clks, + ARRAY_SIZE(omap34xx_omap36xx_clks)); + omap_clocks_register(omap3xxx_clks, + ARRAY_SIZE(omap3xxx_clks)); } else { /* * Assume that anything that we haven't matched yet * has 3430ES2-type clocks. */ cpu_mask = RATE_IN_3430ES2PLUS; - cpu_clkflg = CK_3430ES2PLUS; + omap_clocks_register(omap34xx_omap36xx_clks, + ARRAY_SIZE(omap34xx_omap36xx_clks)); + omap_clocks_register(omap36xx_omap3430es2plus_clks, + ARRAY_SIZE(omap36xx_omap3430es2plus_clks)); + omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, + ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); + omap_clocks_register(omap3xxx_clks, + ARRAY_SIZE(omap3xxx_clks)); } } else { WARN(1, "clock: could not identify OMAP3 variant\n"); } - if (omap3_has_192mhz_clk()) - omap_96m_alwon_fck = omap_96m_alwon_fck_3630; - - if (cpu_is_omap3630()) { - dpll3_m3x2_ck = dpll3_m3x2_ck_3630; - dpll4_m2x2_ck = dpll4_m2x2_ck_3630; - dpll4_m3x2_ck = dpll4_m3x2_ck_3630; - dpll4_m4x2_ck = dpll4_m4x2_ck_3630; - dpll4_m5x2_ck = dpll4_m5x2_ck_3630; - dpll4_m6x2_ck = dpll4_m6x2_ck_3630; - } - - /* - * XXX This type of dynamic rewriting of the clock tree is - * deprecated and should be revised soon. - */ - if (cpu_is_omap3630()) - dpll4_dd = dpll4_dd_3630; - else - dpll4_dd = dpll4_dd_34xx; - - for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); - c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - if (!__clk_init(NULL, c->lk.clk)) - omap2_init_clk_hw_omap_clocks(c->lk.clk); - } - - omap2_clk_disable_autoidle_all(); + omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 3d58f335f173..88e37a474334 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -52,6 +52,13 @@ */ #define OMAP4_DPLL_ABE_DEFFREQ 98304000 +/* + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred + * locked frequency for the USB DPLL is 960MHz. + */ +#define OMAP4_DPLL_USB_DEFFREQ 960000000 + /* Root clocks */ DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); @@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); @@ -1413,283 +1424,285 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, 0x0, NULL); /* - * clkdev + * clocks specific to omap4460 */ +static struct omap_clk omap446x_clks[] = { + CLK(NULL, "div_ts_ck", &div_ts_ck), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk), +}; + +/* + * clocks specific to omap4430 + */ +static struct omap_clk omap443x_clks[] = { + CLK(NULL, "bandgap_fclk", &bandgap_fclk), +}; +/* + * clocks common to omap44xx + */ static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), - CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), - CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), - CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), - CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), - CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), - CLK(NULL, "abe_clk", &abe_clk, CK_443X), - CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), - CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), - CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), - CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), - CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), - CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), - CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), - CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), - CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), - CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), - CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), - CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK("omapdss_dss", "ick", &dss_fck, CK_443X), - CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), - CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), - CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), - CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X), - CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X), - CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X), - CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X), - CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X), - CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X), - CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X), - CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X), - CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X), - CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X), - CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X), - CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), - CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), - CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), - CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), - CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), - CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), - CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), - CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), - CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), - CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), - CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), - CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), - CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), - CLK("omap_wdt", "ick", &dummy_ck, CK_443X), - CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck), + CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck), + CLK(NULL, "pad_clks_ck", &pad_clks_ck), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck), + CLK(NULL, "slimbus_src_clk", &slimbus_src_clk), + CLK(NULL, "slimbus_clk", &slimbus_clk), + CLK(NULL, "sys_32k_ck", &sys_32k_ck), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk), + CLK(NULL, "abe_clk", &abe_clk), + CLK(NULL, "aess_fclk", &aess_fclk), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck), + CLK(NULL, "dpll_core_ck", &dpll_core_ck), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck), + CLK(NULL, "ddrphy_ck", &ddrphy_ck), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck), + CLK(NULL, "div_core_ck", &div_core_ck), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck), + CLK(NULL, "dpll_per_ck", &dpll_per_ck), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck), + CLK(NULL, "func_12m_fclk", &func_12m_fclk), + CLK(NULL, "func_24m_clk", &func_24m_clk), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk), + CLK(NULL, "func_48m_fclk", &func_48m_fclk), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk), + CLK(NULL, "func_64m_fclk", &func_64m_fclk), + CLK(NULL, "func_96m_fclk", &func_96m_fclk), + CLK(NULL, "init_60m_fclk", &init_60m_fclk), + CLK(NULL, "l3_div_ck", &l3_div_ck), + CLK(NULL, "l4_div_ck", &l4_div_ck), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck), + CLK("smp_twd", NULL, &mpu_periphclk), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck), + CLK(NULL, "aes1_fck", &aes1_fck), + CLK(NULL, "aes2_fck", &aes2_fck), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck), + CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk), + CLK(NULL, "dss_sys_clk", &dss_sys_clk), + CLK(NULL, "dss_tv_clk", &dss_tv_clk), + CLK(NULL, "dss_dss_clk", &dss_dss_clk), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk), + CLK(NULL, "dss_fck", &dss_fck), + CLK("omapdss_dss", "ick", &dss_fck), + CLK(NULL, "fdif_fck", &fdif_fck), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk), + CLK(NULL, "sgx_clk_mux", &sgx_clk_mux), + CLK(NULL, "hsi_fck", &hsi_fck), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck), + CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck), + CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck), + CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck), + CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck), + CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk), + CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk), + CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m), + CLK(NULL, "sha2md5_fck", &sha2md5_fck), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck), + CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux), + CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux), + CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux), + CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux), + CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux), + CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux), + CLK(NULL, "timer5_sync_mux", &timer5_sync_mux), + CLK(NULL, "timer6_sync_mux", &timer6_sync_mux), + CLK(NULL, "timer7_sync_mux", &timer7_sync_mux), + CLK(NULL, "timer8_sync_mux", &timer8_sync_mux), + CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick), + CLK(NULL, "usim_ck", &usim_ck), + CLK(NULL, "usim_fclk", &usim_fclk), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck), + CLK(NULL, "auxclk0_ck", &auxclk0_ck), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck), + CLK(NULL, "auxclk1_ck", &auxclk1_ck), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck), + CLK(NULL, "auxclk2_ck", &auxclk2_ck), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck), + CLK(NULL, "auxclk3_ck", &auxclk3_ck), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck), + CLK(NULL, "auxclk4_ck", &auxclk4_ck), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), + CLK(NULL, "auxclk5_ck", &auxclk5_ck), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), + CLK("omap-gpmc", "fck", &dummy_ck), + CLK("omap_i2c.1", "ick", &dummy_ck), + CLK("omap_i2c.2", "ick", &dummy_ck), + CLK("omap_i2c.3", "ick", &dummy_ck), + CLK("omap_i2c.4", "ick", &dummy_ck), + CLK(NULL, "mailboxes_ick", &dummy_ck), + CLK("omap_hsmmc.0", "ick", &dummy_ck), + CLK("omap_hsmmc.1", "ick", &dummy_ck), + CLK("omap_hsmmc.2", "ick", &dummy_ck), + CLK("omap_hsmmc.3", "ick", &dummy_ck), + CLK("omap_hsmmc.4", "ick", &dummy_ck), + CLK("omap-mcbsp.1", "ick", &dummy_ck), + CLK("omap-mcbsp.2", "ick", &dummy_ck), + CLK("omap-mcbsp.3", "ick", &dummy_ck), + CLK("omap-mcbsp.4", "ick", &dummy_ck), + CLK("omap2_mcspi.1", "ick", &dummy_ck), + CLK("omap2_mcspi.2", "ick", &dummy_ck), + CLK("omap2_mcspi.3", "ick", &dummy_ck), + CLK("omap2_mcspi.4", "ick", &dummy_ck), + CLK(NULL, "uart1_ick", &dummy_ck), + CLK(NULL, "uart2_ick", &dummy_ck), + CLK(NULL, "uart3_ick", &dummy_ck), + CLK(NULL, "uart4_ick", &dummy_ck), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck), + CLK("omap_wdt", "ick", &dummy_ck), + CLK(NULL, "timer_32k_ck", &sys_32k_ck), /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ - CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck), + CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck), + CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck), + CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck), + CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck), }; int __init omap4xxx_clk_init(void) { - u32 cpu_clkflg; - struct omap_clk *c; int rc; if (cpu_is_omap443x()) { cpu_mask = RATE_IN_4430; - cpu_clkflg = CK_443X; + omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks)); } else if (cpu_is_omap446x() || cpu_is_omap447x()) { cpu_mask = RATE_IN_4460 | RATE_IN_4430; - cpu_clkflg = CK_446X | CK_443X; - + omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks)); if (cpu_is_omap447x()) pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); } else { return 0; } - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) { - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - if (!__clk_init(NULL, c->lk.clk)) - omap2_init_clk_hw_omap_clocks(c->lk.clk); - } - } + omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks)); omap2_clk_disable_autoidle_all(); @@ -1705,5 +1718,13 @@ int __init omap4xxx_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + return 0; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e4ec3a69ee2e..0c38ca96c840 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -23,7 +23,7 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bitops.h> - +#include <linux/clk-private.h> #include <asm/cpu.h> @@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = { }; /** + * omap_clocks_register - register an array of omap_clk + * @ocs: pointer to an array of omap_clk to register + */ +void __init omap_clocks_register(struct omap_clk oclks[], int cnt) +{ + struct omap_clk *c; + + for (c = oclks; c < oclks + cnt; c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } +} + +/** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument * @mpurate_ck_name: clk name of the clock to change rate * @@ -596,7 +611,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) return -ENOENT; r = clk_set_rate(mpurate_ck, mpurate); - if (IS_ERR_VALUE(r)) { + if (r < 0) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 60ddd8612b4d..7aa32cd292f9 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -27,9 +27,8 @@ struct omap_clk { struct clk_lookup lk; }; -#define CLK(dev, con, ck, cp) \ +#define CLK(dev, con, ck) \ { \ - .cpu = cp, \ .lk = { \ .dev_id = dev, \ .con_id = con, \ @@ -37,22 +36,6 @@ struct omap_clk { }, \ } -/* Platform flags for the clkdev-OMAP integration code */ -#define CK_242X (1 << 0) -#define CK_243X (1 << 1) /* 243x, 253x */ -#define CK_3430ES1 (1 << 2) /* 34xxES1 only */ -#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ -#define CK_AM35XX (1 << 4) /* Sitara AM35xx */ -#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ -#define CK_443X (1 << 6) -#define CK_TI816X (1 << 7) -#define CK_446X (1 << 8) -#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ - - -#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) -#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) - struct clockdomain; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) @@ -480,4 +463,5 @@ extern int am33xx_clk_init(void); extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +extern void omap_clocks_register(struct omap_clk *oclks, int cnt); #endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 40f4a03d728f..df00e7580aa7 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -110,6 +110,14 @@ void am35xx_init_late(void); void ti81xx_init_late(void); int omap2_common_pm_late_init(void); +#ifdef CONFIG_SOC_BUS +void omap_soc_device_init(void); +#else +static inline void omap_soc_device_init(void) +{ +} +#endif + #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) void omap2xxx_restart(char mode, const char *cmd); #else @@ -249,7 +257,6 @@ extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); extern int omap4_finish_suspend(unsigned long cpu_state); extern void omap4_cpu_resume(void); extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); -extern u32 omap4_mpuss_read_prev_context_state(void); #else static inline int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) @@ -277,10 +284,6 @@ static inline int omap4_finish_suspend(unsigned long cpu_state) static inline void omap4_cpu_resume(void) {} -static inline u32 omap4_mpuss_read_prev_context_state(void) -{ - return 0; -} #endif struct omap_sdrc_params; @@ -293,5 +296,8 @@ extern void omap_reserve(void); struct omap_hwmod; extern int omap_dss_reset(struct omap_hwmod *); +/* SoC specific clock initializer */ +extern int (*omap_clk_init)(void); + #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 80392fca86c6..e18709d3b95d 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -26,6 +26,7 @@ #include <linux/cpuidle.h> #include <linux/export.h> #include <linux/cpu_pm.h> +#include <asm/cpuidle.h> #include "powerdomain.h" #include "clockdomain.h" @@ -99,16 +100,18 @@ static struct omap3_idle_statedata omap3_idle_data[] = { }, }; -/* Private functions */ - -static int __omap3_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) +/** + * omap3_enter_idle - Programs OMAP3 to enter the specified state + * @dev: cpuidle device + * @drv: cpuidle driver + * @index: the index of state to be entered + */ +static int omap3_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) { struct omap3_idle_statedata *cx = &omap3_idle_data[index]; - local_fiq_disable(); - if (omap_irq_pending() || need_resched()) goto return_sleep_time; @@ -143,28 +146,11 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); return_sleep_time: - local_fiq_enable(); return index; } /** - * omap3_enter_idle - Programs OMAP3 to enter the specified state - * @dev: cpuidle device - * @drv: cpuidle driver - * @index: the index of state to be entered - * - * Called from the CPUidle framework to program the device to the - * specified target state selected by the governor. - */ -static inline int omap3_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle); -} - -/** * next_valid_state - Find next valid C-state * @dev: cpuidle device * @drv: cpuidle driver @@ -271,11 +257,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, return ret; } -static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); - static struct cpuidle_driver omap3_idle_driver = { - .name = "omap3_idle", - .owner = THIS_MODULE, + .name = "omap3_idle", + .owner = THIS_MODULE, .states = { { .enter = omap3_enter_idle_bm, @@ -348,8 +332,6 @@ static struct cpuidle_driver omap3_idle_driver = { */ int __init omap3_idle_init(void) { - struct cpuidle_device *dev; - mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); per_pd = pwrdm_lookup("per_pwrdm"); @@ -358,16 +340,5 @@ int __init omap3_idle_init(void) if (!mpu_pd || !core_pd || !per_pd || !cam_pd) return -ENODEV; - cpuidle_register_driver(&omap3_idle_driver); - - dev = &per_cpu(omap3_idle_dev, smp_processor_id()); - dev->cpu = 0; - - if (cpuidle_register_device(dev)) { - printk(KERN_ERR "%s: CPUidle register device failed\n", - __func__); - return -EIO; - } - - return 0; + return cpuidle_register(&omap3_idle_driver, NULL); } diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index d639aef0deda..c443f2e97e10 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -1,7 +1,7 @@ /* - * OMAP4 CPU idle Routines + * OMAP4+ CPU idle Routines * - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2011-2013 Texas Instruments, Inc. * Santosh Shilimkar <santosh.shilimkar@ti.com> * Rajendra Nayak <rnayak@ti.com> * @@ -14,8 +14,8 @@ #include <linux/cpuidle.h> #include <linux/cpu_pm.h> #include <linux/export.h> -#include <linux/clockchips.h> +#include <asm/cpuidle.h> #include <asm/proc-fns.h> #include "common.h" @@ -24,13 +24,13 @@ #include "clockdomain.h" /* Machine specific information */ -struct omap4_idle_statedata { +struct idle_statedata { u32 cpu_state; u32 mpu_logic_state; u32 mpu_state; }; -static struct omap4_idle_statedata omap4_idle_data[] = { +static struct idle_statedata omap4_idle_data[] = { { .cpu_state = PWRDM_POWER_ON, .mpu_state = PWRDM_POWER_ON, @@ -53,11 +53,12 @@ static struct clockdomain *cpu_clkdm[NR_CPUS]; static atomic_t abort_barrier; static bool cpu_done[NR_CPUS]; +static struct idle_statedata *state_ptr = &omap4_idle_data[0]; /* Private functions */ /** - * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions + * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions * @dev: cpuidle device * @drv: cpuidle driver * @index: the index of state to be entered @@ -66,25 +67,19 @@ static bool cpu_done[NR_CPUS]; * specified low power state selected by the governor. * Returns the amount of time spent in the low power state. */ -static int omap4_enter_idle_simple(struct cpuidle_device *dev, +static int omap_enter_idle_simple(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - local_fiq_disable(); omap_do_wfi(); - local_fiq_enable(); - return index; } -static int omap4_enter_idle_coupled(struct cpuidle_device *dev, +static int omap_enter_idle_coupled(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct omap4_idle_statedata *cx = &omap4_idle_data[index]; - int cpu_id = smp_processor_id(); - - local_fiq_disable(); + struct idle_statedata *cx = state_ptr + index; /* * CPU0 has to wait and stay ON until CPU1 is OFF state. @@ -109,8 +104,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev, } } - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); - /* * Call idle CPU PM enter notifier chain so that * VFP and per CPU interrupt context is saved. @@ -136,6 +129,7 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev, /* Wakeup CPU1 only if it is not offlined */ if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { clkdm_wakeup(cpu_clkdm[1]); + omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON); clkdm_allow_idle(cpu_clkdm[1]); } @@ -149,63 +143,49 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev, * Call idle CPU cluster PM exit notifier chain * to restore GIC and wakeupgen context. */ - if (omap4_mpuss_read_prev_context_state()) + if ((cx->mpu_state == PWRDM_POWER_RET) && + (cx->mpu_logic_state == PWRDM_POWER_OFF)) cpu_cluster_pm_exit(); - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); - fail: cpuidle_coupled_parallel_barrier(dev, &abort_barrier); cpu_done[dev->cpu] = false; - local_fiq_enable(); - return index; } -/* - * For each cpu, setup the broadcast timer because local timers - * stops for the states above C1. - */ -static void omap_setup_broadcast_timer(void *arg) -{ - int cpu = smp_processor_id(); - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu); -} - -static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); - static struct cpuidle_driver omap4_idle_driver = { .name = "omap4_idle", .owner = THIS_MODULE, - .en_core_tk_irqen = 1, .states = { { /* C1 - CPU0 ON + CPU1 ON + MPU ON */ .exit_latency = 2 + 2, .target_residency = 5, .flags = CPUIDLE_FLAG_TIME_VALID, - .enter = omap4_enter_idle_simple, + .enter = omap_enter_idle_simple, .name = "C1", - .desc = "MPUSS ON" + .desc = "CPUx ON, MPUSS ON" }, { /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ .exit_latency = 328 + 440, .target_residency = 960, - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, - .enter = omap4_enter_idle_coupled, + .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | + CPUIDLE_FLAG_TIMER_STOP, + .enter = omap_enter_idle_coupled, .name = "C2", - .desc = "MPUSS CSWR", + .desc = "CPUx OFF, MPUSS CSWR", }, { /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ .exit_latency = 460 + 518, .target_residency = 1100, - .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, - .enter = omap4_enter_idle_coupled, + .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | + CPUIDLE_FLAG_TIMER_STOP, + .enter = omap_enter_idle_coupled, .name = "C3", - .desc = "MPUSS OSWR", + .desc = "CPUx OFF, MPUSS OSWR", }, }, .state_count = ARRAY_SIZE(omap4_idle_data), @@ -215,16 +195,13 @@ static struct cpuidle_driver omap4_idle_driver = { /* Public functions */ /** - * omap4_idle_init - Init routine for OMAP4 idle + * omap4_idle_init - Init routine for OMAP4+ idle * - * Registers the OMAP4 specific cpuidle driver to the cpuidle + * Registers the OMAP4+ specific cpuidle driver to the cpuidle * framework with the valid set of states. */ int __init omap4_idle_init(void) { - struct cpuidle_device *dev; - unsigned int cpu_id = 0; - mpu_pd = pwrdm_lookup("mpu_pwrdm"); cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm"); cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm"); @@ -236,22 +213,5 @@ int __init omap4_idle_init(void) if (!cpu_clkdm[0] || !cpu_clkdm[1]) return -ENODEV; - /* Configure the broadcast timer on each cpu */ - on_each_cpu(omap_setup_broadcast_timer, NULL, 1); - - for_each_cpu(cpu_id, cpu_online_mask) { - dev = &per_cpu(omap4_idle_dev, cpu_id); - dev->cpu = cpu_id; -#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED - dev->coupled_cpus = *cpu_online_mask; -#endif - cpuidle_register_driver(&omap4_idle_driver); - - if (cpuidle_register_device(dev)) { - pr_err("%s: CPUidle register failed\n", __func__); - return -EIO; - } - } - - return 0; + return cpuidle_register(&omap4_idle_driver, cpu_online_mask); } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 1ec7f0597710..4269fc145698 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -504,140 +504,31 @@ static void omap_init_rng(void) WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); } -#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) - -#ifdef CONFIG_ARCH_OMAP2 -static struct resource omap2_sham_resources[] = { - { - .start = OMAP24XX_SEC_SHA1MD5_BASE, - .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, - .flags = IORESOURCE_MEM, - }, - { - .start = 51 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, - } -}; -static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); -#else -#define omap2_sham_resources NULL -#define omap2_sham_resources_sz 0 -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static struct resource omap3_sham_resources[] = { - { - .start = OMAP34XX_SEC_SHA1MD5_BASE, - .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, - .flags = IORESOURCE_MEM, - }, - { - .start = 49 + OMAP_INTC_START, - .flags = IORESOURCE_IRQ, - }, - { - .start = OMAP34XX_DMA_SHA1MD5_RX, - .flags = IORESOURCE_DMA, - } -}; -static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); -#else -#define omap3_sham_resources NULL -#define omap3_sham_resources_sz 0 -#endif - -static struct platform_device sham_device = { - .name = "omap-sham", - .id = -1, -}; - -static void omap_init_sham(void) +static void __init omap_init_sham(void) { - if (cpu_is_omap24xx()) { - sham_device.resource = omap2_sham_resources; - sham_device.num_resources = omap2_sham_resources_sz; - } else if (cpu_is_omap34xx()) { - sham_device.resource = omap3_sham_resources; - sham_device.num_resources = omap3_sham_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); - return; - } - platform_device_register(&sham_device); -} -#else -static inline void omap_init_sham(void) { } -#endif - -#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) - -#ifdef CONFIG_ARCH_OMAP2 -static struct resource omap2_aes_resources[] = { - { - .start = OMAP24XX_SEC_AES_BASE, - .end = OMAP24XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP24XX_DMA_AES_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP24XX_DMA_AES_RX, - .flags = IORESOURCE_DMA, - } -}; -static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); -#else -#define omap2_aes_resources NULL -#define omap2_aes_resources_sz 0 -#endif + struct omap_hwmod *oh; + struct platform_device *pdev; -#ifdef CONFIG_ARCH_OMAP3 -static struct resource omap3_aes_resources[] = { - { - .start = OMAP34XX_SEC_AES_BASE, - .end = OMAP34XX_SEC_AES_BASE + 0x4C, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP34XX_DMA_AES2_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = OMAP34XX_DMA_AES2_RX, - .flags = IORESOURCE_DMA, - } -}; -static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); -#else -#define omap3_aes_resources NULL -#define omap3_aes_resources_sz 0 -#endif + oh = omap_hwmod_lookup("sham"); + if (!oh) + return; -static struct platform_device aes_device = { - .name = "omap-aes", - .id = -1, -}; + pdev = omap_device_build("omap-sham", -1, oh, NULL, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n"); +} -static void omap_init_aes(void) +static void __init omap_init_aes(void) { - if (cpu_is_omap24xx()) { - aes_device.resource = omap2_aes_resources; - aes_device.num_resources = omap2_aes_resources_sz; - } else if (cpu_is_omap34xx()) { - aes_device.resource = omap3_aes_resources; - aes_device.num_resources = omap3_aes_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); + struct omap_hwmod *oh; + struct platform_device *pdev; + + oh = omap_hwmod_lookup("aes"); + if (!oh) return; - } - platform_device_register(&aes_device); -} -#else -static inline void omap_init_aes(void) { } -#endif + pdev = omap_device_build("omap-aes", -1, oh, NULL, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n"); +} /*-------------------------------------------------------------------------*/ @@ -764,11 +655,11 @@ static int __init omap2_init_devices(void) omap_init_dmic(); omap_init_mcpdm(); omap_init_mcspi(); + omap_init_sham(); + omap_init_aes(); } omap_init_sti(); omap_init_rng(); - omap_init_sham(); - omap_init_aes(); omap_init_vout(); omap_init_ocp2scp(); diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h index eba80dbc5218..65f80cacf178 100644 --- a/arch/arm/mach-omap2/dma.h +++ b/arch/arm/mach-omap2/dma.h @@ -22,69 +22,20 @@ /* DMA channels for 24xx */ #define OMAP24XX_DMA_NO_DEVICE 0 -#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ -#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ -#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ -#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ -#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ -#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ -#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ -#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ -#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ -#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ -#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ -#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ -#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ -#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ -#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ -#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ -#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ -#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ -#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ -#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ -#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ -#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ -#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ -#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ -#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ -#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ -#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ -#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ -#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ -#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ -#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ -#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ -#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ -#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ -#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ -#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ -#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ -#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ -#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ -#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ -#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ -#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ -#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ -#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ -#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ -#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ @@ -93,33 +44,12 @@ #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ -#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ -#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ -#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ -#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ -#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ -#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ -#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ -#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ -#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ -#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ -#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ -#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ -#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ -#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ -#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ -#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ -#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ -#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ #define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ #define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3aed4b0b9563..3a0296cfcace 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_bypass(clk); /* - * Set jitter correction. No jitter correction for OMAP4 and 3630 - * since freqsel field is no longer present + * Set jitter correction. Jitter correction applicable for OMAP343X + * only since freqsel field is no longer present on other devices. */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (cpu_is_omap343x()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; - __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); - __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); - if (__clk_get_rate(dd->clk_bypass) == rate && (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("%s: %s: set rate: entering bypass.\n", __func__, __clk_get_name(hw->clk)); + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); } else { + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; - /* No freqsel on AM335x, OMAP4 and OMAP3630 */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && - !cpu_is_omap3630()) { + /* Freqsel is available only on OMAP343X devices */ + if (cpu_is_omap343x()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); @@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); } /* * FIXME - this is all wrong. common code handles reparenting and @@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!ret) __clk_reparent(hw->clk, new_parent); - clk_disable(dd->clk_ref); - __clk_unprepare(dd->clk_ref); - clk_disable(dd->clk_bypass); - __clk_unprepare(dd->clk_bypass); - return 0; } diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index b155500e84a8..b8208b4b1bd9 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -26,7 +26,7 @@ #include "control.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_TIDSPBRIDGE_DVFS #include "omap-pm.h" #endif @@ -35,7 +35,7 @@ static struct platform_device *omap_dsp_pdev; static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_TIDSPBRIDGE_DVFS .dsp_set_min_opp = omap_pm_dsp_set_min_opp, .dsp_get_opp = omap_pm_dsp_get_opp, .cpu_set_freq = omap_pm_cpu_set_freq, diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index 4be5cfc81ab8..9c49bbe825f7 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c @@ -27,9 +27,7 @@ #include <linux/gpio.h> #include <video/omapdss.h> -#include <video/omap-panel-tfp410.h> -#include <video/omap-panel-nokia-dsi.h> -#include <video/omap-panel-picodlp.h> +#include <video/omap-panel-data.h> #include "soc.h" #include "dss-common.h" diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index fadd87435cd0..0d75889c0a6f 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -303,7 +303,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base) t = omap2_onenand_calc_async_timings(); ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; omap2_onenand_set_async_mode(onenand_base); @@ -325,7 +325,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; set_onenand_cfg(onenand_base); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 410e1bac7815..6de31739b45c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -716,7 +716,7 @@ static int gpmc_setup_irq(void) return -EINVAL; gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); - if (IS_ERR_VALUE(gpmc_irq_start)) { + if (gpmc_irq_start < 0) { pr_err("irq_alloc_descs failed\n"); return gpmc_irq_start; } @@ -801,7 +801,7 @@ static int gpmc_mem_init(void) continue; gpmc_cs_get_memconf(cs, &base, &size); rc = gpmc_cs_insert_mem(cs, base, size); - if (IS_ERR_VALUE(rc)) { + if (rc < 0) { while (--cs >= 0) if (gpmc_cs_mem_enabled(cs)) gpmc_cs_delete_mem(cs); @@ -1370,14 +1370,14 @@ static int gpmc_probe(struct platform_device *pdev) GPMC_REVISION_MINOR(l)); rc = gpmc_mem_init(); - if (IS_ERR_VALUE(rc)) { + if (rc < 0) { clk_disable_unprepare(gpmc_l3_clk); clk_put(gpmc_l3_clk); dev_err(gpmc_dev, "failed to reserve memory\n"); return rc; } - if (IS_ERR_VALUE(gpmc_setup_irq())) + if (gpmc_setup_irq() < 0) dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); /* Now the GPMC is initialised, unreserve the chip-selects */ diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 8a68f1ec66b9..0f4c18e6e60c 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -18,6 +18,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/slab.h> + +#ifdef CONFIG_SOC_BUS +#include <linux/sys_soc.h> +#endif #include <asm/cputype.h> @@ -31,8 +36,11 @@ #define OMAP4_SILICON_TYPE_STANDARD 0x01 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 +#define OMAP_SOC_MAX_NAME_LENGTH 16 + static unsigned int omap_revision; -static const char *cpu_rev; +static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; +static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; u32 omap_features; unsigned int omap_rev(void) @@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void) j = i; } - pr_info("OMAP%04x", omap_rev() >> 16); + sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); + sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); + + pr_info("%s", soc_name); if ((omap_rev() >> 8) & 0x0f) - pr_info("ES%x", (omap_rev() >> 12) & 0xf); + pr_info("%s", soc_rev); pr_info("\n"); } @@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void) cpu_name = "OMAP3503"; } + sprintf(soc_name, "%s", cpu_name); + /* Print verbose information */ - pr_info("%s ES%s (", cpu_name, cpu_rev); + pr_info("%s %s (", soc_name, soc_rev); OMAP3_SHOW_FEATURE(l2cache); OMAP3_SHOW_FEATURE(iva); @@ -291,6 +304,7 @@ void __init ti81xx_check_features(void) void __init omap3xxx_check_revision(void) { + const char *cpu_rev; u32 cpuid, idcode; u16 hawkeye; u8 rev; @@ -300,7 +314,7 @@ void __init omap3xxx_check_revision(void) * If the processor type is Cortex-A8 and the revision is 0x0 * it means its Cortex r0p0 which is 3430 ES1.0. */ - cpuid = read_cpuid(CPUID_ID); + cpuid = read_cpuid_id(); if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { omap_revision = OMAP3430_REV_ES1_0; cpu_rev = "1.0"; @@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void) cpu_rev = "1.2"; pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); } + sprintf(soc_rev, "ES%s", cpu_rev); } void __init omap4xxx_check_revision(void) @@ -460,7 +475,7 @@ void __init omap4xxx_check_revision(void) * Use ARM register to detect the correct ES version */ if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { - idcode = read_cpuid(CPUID_ID); + idcode = read_cpuid_id(); rev = (idcode & 0xf) - 1; } @@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void) omap_revision = OMAP4430_REV_ES2_3; } - pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, - ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); + sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); + sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, + (omap_rev() >> 8) & 0xf); + pr_info("%s %s\n", soc_name, soc_rev); } void __init omap5xxx_check_revision(void) @@ -529,26 +546,34 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - default: omap_revision = OMAP5430_REV_ES1_0; + break; + case 1: + default: + omap_revision = OMAP5430_REV_ES2_0; } break; case 0xb998: switch (rev) { case 0: - default: omap_revision = OMAP5432_REV_ES1_0; + break; + case 1: + default: + omap_revision = OMAP5432_REV_ES2_0; } break; default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP5430_REV_ES1_0; + omap_revision = OMAP5430_REV_ES2_0; } - pr_info("OMAP%04x ES%d.0\n", - omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); + sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); + sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); + + pr_info("%s %s\n", soc_name, soc_rev); } /* @@ -569,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap) else tap_prod_id = 0x0208; } + +#ifdef CONFIG_SOC_BUS + +static const char const *omap_types[] = { + [OMAP2_DEVICE_TYPE_TEST] = "TST", + [OMAP2_DEVICE_TYPE_EMU] = "EMU", + [OMAP2_DEVICE_TYPE_SEC] = "HS", + [OMAP2_DEVICE_TYPE_GP] = "GP", + [OMAP2_DEVICE_TYPE_BAD] = "BAD", +}; + +static const char * __init omap_get_family(void) +{ + if (cpu_is_omap24xx()) + return kasprintf(GFP_KERNEL, "OMAP2"); + else if (cpu_is_omap34xx()) + return kasprintf(GFP_KERNEL, "OMAP3"); + else if (cpu_is_omap44xx()) + return kasprintf(GFP_KERNEL, "OMAP4"); + else if (soc_is_omap54xx()) + return kasprintf(GFP_KERNEL, "OMAP5"); + else + return kasprintf(GFP_KERNEL, "Unknown"); +} + +static ssize_t omap_get_type(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", omap_types[omap_type()]); +} + +static struct device_attribute omap_soc_attr = + __ATTR(type, S_IRUGO, omap_get_type, NULL); + +void __init omap_soc_device_init(void) +{ + struct device *parent; + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return; + + soc_dev_attr->machine = soc_name; + soc_dev_attr->family = omap_get_family(); + soc_dev_attr->revision = soc_rev; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR_OR_NULL(soc_dev)) { + kfree(soc_dev_attr); + return; + } + + parent = soc_device_to_device(soc_dev); + if (!IS_ERR_OR_NULL(parent)) + device_create_file(parent, &omap_soc_attr); +} +#endif /* CONFIG_SOC_BUS */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 2c3fdd65387b..09abf99e9e57 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -55,6 +55,12 @@ #include "prm44xx.h" /* + * omap_clk_init: points to a function that does the SoC-specific + * clock initializations + */ +int (*omap_clk_init)(void); + +/* * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ @@ -271,6 +277,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, +#ifdef CONFIG_OMAP4_ERRATA_I688 + { + .virtual = OMAP4_SRAM_VA, + .pfn = __phys_to_pfn(OMAP4_SRAM_PA), + .length = PAGE_SIZE, + .type = MT_MEMORY_SO, + }, +#endif }; #endif @@ -323,6 +337,7 @@ void __init omap4_map_io(void) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); + omap_barriers_init(); } #endif /* @@ -379,6 +394,13 @@ static void __init omap_hwmod_init_postsetup(void) omap_pm_if_early_init(); } +static void __init omap_common_late_init(void) +{ + omap_mux_late_init(); + omap2_common_pm_late_init(); + omap_soc_device_init(); +} + #ifdef CONFIG_SOC_OMAP2420 void __init omap2420_init_early(void) { @@ -397,13 +419,12 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap2420_clk_init(); + omap_clk_init = omap2420_clk_init; } void __init omap2420_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap2_pm_init(); omap2_clk_enable_autoidle_all(); } @@ -427,13 +448,12 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap2430_clk_init(); + omap_clk_init = omap2430_clk_init; } void __init omap2430_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap2_pm_init(); omap2_clk_enable_autoidle_all(); } @@ -462,7 +482,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap3xxx_clk_init(); + omap_clk_init = omap3xxx_clk_init; } void __init omap3430_init_early(void) @@ -500,53 +520,47 @@ void __init ti81xx_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap3xxx_clk_init(); + omap_clk_init = omap3xxx_clk_init; } void __init omap3_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } void __init omap3430_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } void __init omap35xx_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } void __init omap3630_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } void __init am35xx_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } void __init ti81xx_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap3_pm_init(); omap2_clk_enable_autoidle_all(); } @@ -568,7 +582,7 @@ void __init am33xx_init_early(void) am33xx_clockdomains_init(); am33xx_hwmod_init(); omap_hwmod_init_postsetup(); - am33xx_clk_init(); + omap_clk_init = am33xx_clk_init; } #endif @@ -593,13 +607,12 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap4xxx_clk_init(); + omap_clk_init = omap4xxx_clk_init; } void __init omap4430_init_late(void) { - omap_mux_late_init(); - omap2_common_pm_late_init(); + omap_common_late_init(); omap4_pm_init(); omap2_clk_enable_autoidle_all(); } diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index e712d1725a8b..458f72f9dc8f 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -19,11 +19,8 @@ #include <linux/smp.h> #include <linux/io.h> -#include <asm/cacheflush.h> #include "omap-wakeupgen.h" - #include "common.h" - #include "powerdomain.h" /* @@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu) unsigned int boot_cpu = 0; void __iomem *base = omap_get_wakeupgen_base(); - flush_cache_all(); - dsb(); - /* * we're ready for shutdown now, so do it */ diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 8bcb64bcdcdb..e80327b6c81f 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -139,20 +139,6 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) } } -/** - * omap4_mpuss_read_prev_context_state: - * Function returns the MPUSS previous context state - */ -u32 omap4_mpuss_read_prev_context_state(void) -{ - u32 reg; - - reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); - reg &= OMAP4430_LOSTCONTEXT_DFF_MASK; - return reg; -} - /* * Store the CPU cluster state for L2X0 low power operations. */ diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index d9727218dd0a..2a551f997aea 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -21,7 +21,6 @@ #include <linux/io.h> #include <linux/irqchip/arm-gic.h> -#include <asm/cacheflush.h> #include <asm/smp_scu.h> #include "omap-secure.h" @@ -67,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0); /* - * If any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); @@ -84,6 +76,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * { static struct clockdomain *cpu1_clkdm; static bool booted; + static struct powerdomain *cpu1_pwrdm; void __iomem *base = omap_get_wakeupgen_base(); /* @@ -103,11 +96,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * else __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); - flush_cache_all(); - smp_wmb(); - - if (!cpu1_clkdm) + if (!cpu1_clkdm && !cpu1_pwrdm) { cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); + } /* * The SGI(Software Generated Interrupts) are not wakeup capable @@ -120,7 +112,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * * Section : * 4.3.4.2 Power States of CPU0 and CPU1 */ - if (booted) { + if (booted && cpu1_pwrdm && cpu1_clkdm) { /* * GIC distributor control register has changed between * CortexA9 r1pX and r2pX. The Control Register secure @@ -141,7 +133,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * gic_dist_disable(); } + /* + * Ensure that CPU power state is set to ON to avoid CPU + * powerdomain transition on wfi + */ clkdm_wakeup(cpu1_clkdm); + omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON); clkdm_allow_idle(cpu1_clkdm); if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { @@ -168,38 +165,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * return 0; } -static void __init wakeup_secondary(void) -{ - void *startup_addr = omap_secondary_startup; - void __iomem *base = omap_get_wakeupgen_base(); - - if (cpu_is_omap446x()) { - startup_addr = omap_secondary_startup_4460; - pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; - } - - /* - * Write the address of secondary startup routine into the - * AuxCoreBoot1 where ROM code will jump and start executing - * on secondary core once out of WFE - * A barrier is added to ensure that write buffer is drained - */ - if (omap_secure_apis_support()) - omap_auxcoreboot_addr(virt_to_phys(startup_addr)); - else - __raw_writel(virt_to_phys(omap5_secondary_startup), - base + OMAP_AUX_CORE_BOOT_1); - - smp_wmb(); - - /* - * Send a 'sev' to wake the secondary core from WFE. - * Drain the outstanding writes to memory - */ - dsb_sev(); - mb(); -} - /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. @@ -209,7 +174,7 @@ static void __init omap4_smp_init_cpus(void) unsigned int i = 0, ncores = 1, cpu_id; /* Use ARM cpuid check here, as SoC detection will not work so early */ - cpu_id = read_cpuid(CPUID_ID) & CPU_MASK; + cpu_id = read_cpuid_id() & CPU_MASK; if (cpu_id == CPU_CORTEX_A9) { /* * Currently we can't call ioremap here because @@ -235,6 +200,8 @@ static void __init omap4_smp_init_cpus(void) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { + void *startup_addr = omap_secondary_startup; + void __iomem *base = omap_get_wakeupgen_base(); /* * Initialise the SCU and wake up the secondary core using @@ -242,7 +209,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) */ if (scu_base) scu_enable(scu_base); - wakeup_secondary(); + + if (cpu_is_omap446x()) { + startup_addr = omap_secondary_startup_4460; + pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; + } + + /* + * Write the address of secondary startup routine into the + * AuxCoreBoot1 where ROM code will jump and start executing + * on secondary core once out of WFE + * A barrier is added to ensure that write buffer is drained + */ + if (omap_secure_apis_support()) + omap_auxcoreboot_addr(virt_to_phys(startup_addr)); + else + __raw_writel(virt_to_phys(omap5_secondary_startup), + base + OMAP_AUX_CORE_BOOT_1); + } struct smp_operations omap4_smp_ops __initdata = { diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 708bb115a27f..13b27ffaf45e 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -22,6 +22,7 @@ #include <linux/of_platform.h> #include <linux/export.h> #include <linux/irqchip/arm-gic.h> +#include <linux/of_address.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> @@ -240,15 +241,21 @@ void __iomem *omap4_get_sar_ram_base(void) */ static int __init omap4_sar_ram_init(void) { + unsigned long sar_base; + /* * To avoid code running on other OMAPs in * multi-omap builds */ - if (!cpu_is_omap44xx()) + if (cpu_is_omap44xx()) + sar_base = OMAP44XX_SAR_RAM_BASE; + else if (soc_is_omap54xx()) + sar_base = OMAP54XX_SAR_RAM_BASE; + else return -ENOMEM; /* Static mapping, never released */ - sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); + sar_ram_base = ioremap(sar_base, SZ_16K); if (WARN_ON(!sar_ram_base)) return -ENOMEM; @@ -258,6 +265,21 @@ omap_early_initcall(omap4_sar_ram_init); void __init omap_gic_of_init(void) { + struct device_node *np; + + /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ + if (!cpu_is_omap446x()) + goto skip_errata_init; + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); + gic_dist_base_addr = of_iomap(np, 0); + WARN_ON(!gic_dist_base_addr); + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); + twd_base = of_iomap(np, 0); + WARN_ON(!twd_base); + +skip_errata_init: omap_wakeupgen_init(); irqchip_init(); } diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h index e170fe803b04..792b1069f724 100644 --- a/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/arch/arm/mach-omap2/omap4-sar-layout.h @@ -20,13 +20,13 @@ #define SAR_BANK4_OFFSET 0x3000 /* Scratch pad memory offsets from SAR_BANK1 */ -#define SCU_OFFSET0 0xd00 -#define SCU_OFFSET1 0xd04 -#define OMAP_TYPE_OFFSET 0xd10 -#define L2X0_SAVE_OFFSET0 0xd14 -#define L2X0_SAVE_OFFSET1 0xd18 -#define L2X0_AUXCTRL_OFFSET 0xd1c -#define L2X0_PREFETCH_CTRL_OFFSET 0xd20 +#define SCU_OFFSET0 0xfe4 +#define SCU_OFFSET1 0xfe8 +#define OMAP_TYPE_OFFSET 0xfec +#define L2X0_SAVE_OFFSET0 0xff0 +#define L2X0_SAVE_OFFSET1 0xff4 +#define L2X0_AUXCTRL_OFFSET 0xff8 +#define L2X0_PREFETCH_CTRL_OFFSET 0xffc /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 @@ -48,13 +48,13 @@ #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ -#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) -#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) -#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) -#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) -#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) #endif diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a2582bb3cab3..a086ba15868b 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h @@ -28,5 +28,6 @@ #define OMAP54XX_PRCM_MPU_BASE 0x48243000 #define OMAP54XX_SCM_BASE 0x4a002000 #define OMAP54XX_CTRL_BASE 0x4a002800 +#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 #endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 381be7ac0c17..eeea4fa28fbc 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -131,7 +131,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) int oh_cnt, i, ret = 0; oh_cnt = of_property_count_strings(node, "ti,hwmods"); - if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) { + if (oh_cnt <= 0) { dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n"); return -ENODEV; } @@ -815,20 +815,17 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name) } oh = omap_hwmod_lookup(oh_name); - if (IS_ERR_OR_NULL(oh)) { + if (!oh) { WARN(1, "%s: no hwmod for %s\n", __func__, oh_name); - return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV); + return ERR_PTR(-ENODEV); } - if (IS_ERR_OR_NULL(oh->od)) { + if (!oh->od) { WARN(1, "%s: no omap_device for %s\n", __func__, oh_name); - return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV); + return ERR_PTR(-ENODEV); } - if (IS_ERR_OR_NULL(oh->od->pdev)) - return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV); - return &oh->od->pdev->dev; } diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c2c798c08c2b..93f213b6a784 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -138,6 +138,7 @@ #include <linux/spinlock.h> #include <linux/slab.h> #include <linux/bootmem.h> +#include <linux/cpu.h> #include <asm/system_misc.h> @@ -610,8 +611,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ - oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; - return 0; } @@ -645,8 +644,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ - oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; - return 0; } @@ -1368,7 +1365,9 @@ static void _enable_sysc(struct omap_hwmod *oh) } if (sf & SYSC_HAS_MIDLEMODE) { - if (oh->flags & HWMOD_SWSUP_MSTANDBY) { + if (oh->flags & HWMOD_FORCE_MSTANDBY) { + idlemode = HWMOD_IDLEMODE_FORCE; + } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { idlemode = HWMOD_IDLEMODE_NO; } else { if (sf & SYSC_HAS_ENAWAKEUP) @@ -1440,7 +1439,8 @@ static void _idle_sysc(struct omap_hwmod *oh) } if (sf & SYSC_HAS_MIDLEMODE) { - if (oh->flags & HWMOD_SWSUP_MSTANDBY) { + if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || + (oh->flags & HWMOD_FORCE_MSTANDBY)) { idlemode = HWMOD_IDLEMODE_FORCE; } else { if (sf & SYSC_HAS_ENAWAKEUP) @@ -1663,7 +1663,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; if (oh->clkdm) { @@ -2154,7 +2154,7 @@ static int _enable(struct omap_hwmod *oh) if (soc_ops.enable_module) soc_ops.enable_module(oh); if (oh->flags & HWMOD_BLOCK_WFI) - disable_hlt(); + cpu_idle_poll_ctrl(true); if (soc_ops.update_context_lost) soc_ops.update_context_lost(oh); @@ -2218,7 +2218,7 @@ static int _idle(struct omap_hwmod *oh) _del_initiator_dep(oh, mpu_oh); if (oh->flags & HWMOD_BLOCK_WFI) - enable_hlt(); + cpu_idle_poll_ctrl(false); if (soc_ops.disable_module) soc_ops.disable_module(oh); @@ -2328,7 +2328,7 @@ static int _shutdown(struct omap_hwmod *oh) _del_initiator_dep(oh, mpu_oh); /* XXX what about the other system initiators here? dma, dsp */ if (oh->flags & HWMOD_BLOCK_WFI) - enable_hlt(); + cpu_idle_poll_ctrl(false); if (soc_ops.disable_module) soc_ops.disable_module(oh); _disable_clocks(oh); @@ -2413,7 +2413,7 @@ static int __init _init(struct omap_hwmod *oh, void *data) _init_mpu_rt_base(oh, NULL); r = _init_clocks(oh, NULL); - if (IS_ERR_VALUE(r)) { + if (r < 0) { WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); return -EINVAL; } diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index d43d9b608eda..fe5962921f07 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm { * * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out * of idle, rather than relying on module smart-idle - * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out - * of standby, rather than relying on module smart-standby + * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and + * out of standby, rather than relying on module smart-standby * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for * SDRAM controller, etc. XXX probably belongs outside the main hwmod file * XXX Should be HWMOD_SETUP_NO_RESET @@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm { * correctly, or this is being abused to deal with some PM latency * issues -- but we're currently suffering from a shortage of * folks who are able to track these issues down properly. + * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device + * is kept in force-standby mode. Failing to do so causes PM problems + * with musb on OMAP3630 at least. Note that musb has a dedicated register + * to control MSTANDBY signal when MIDLEMODE is set to force-standby. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -471,21 +475,20 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_16BIT_REG (1 << 8) #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) #define HWMOD_BLOCK_WFI (1 << 10) +#define HWMOD_FORCE_MSTANDBY (1 << 11) /* * omap_hwmod._int_flags definitions * These are for internal use only and are managed by the omap_hwmod code. * * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module - * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - * causes the first call to _enable() to only update the pinmux */ #define _HWMOD_NO_MPU_PORT (1 << 0) -#define _HWMOD_WAKEUP_ENABLED (1 << 1) -#define _HWMOD_SYSCONFIG_LOADED (1 << 2) -#define _HWMOD_SKIP_ENABLE (1 << 3) +#define _HWMOD_SYSCONFIG_LOADED (1 << 1) +#define _HWMOD_SKIP_ENABLE (1 << 2) /* * omap_hwmod._state definitions diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 6a764af6c6d3..5137cc84b504 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__mcbsp2, &omap2420_l4_core__msdi1, &omap2xxx_l4_core__rng, + &omap2xxx_l4_core__sham, + &omap2xxx_l4_core__aes, &omap2420_l4_core__hdq1w, &omap2420_l4_wkup__counter_32k, &omap2420_l3__gpmc, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index d2d3840557c3..4ce999ee3ee9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2430_l4_core__mcbsp5, &omap2430_l4_core__hdq1w, &omap2xxx_l4_core__rng, + &omap2xxx_l4_core__sham, + &omap2xxx_l4_core__aes, &omap2430_l4_wkup__counter_32k, &omap2430_l3__gpmc, NULL, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 47901a5e76de..5fd40d4a989e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = { { } }; +static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = { + { + .pa_start = 0x480a4000, + .pa_end = 0x480a4000 + 0x64 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = { + { + .pa_start = 0x480a6000, + .pa_end = 0x480a6000 + 0x50 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + /* * Common interconnect data */ @@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = { .addr = omap2_rng_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; + +/* l4 core -> sham interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_sham_hwmod, + .clk = "sha_ick", + .addr = omap2xxx_sham_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> aes interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_aes_hwmod, + .clk = "aes_ick", + .addr = omap2xxx_aes_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index e596117004d4..c8c64b3e1acc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = { .flags = HWMOD_INIT_NO_RESET, .class = &omap2_rng_hwmod_class, }; + +/* SHAM */ + +static struct omap_hwmod_class_sysconfig omap2_sham_sysc = { + .rev_offs = 0x5c, + .sysc_offs = 0x60, + .syss_offs = 0x64, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2xxx_sham_class = { + .name = "sham", + .sysc = &omap2_sham_sysc, +}; + +static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = { + { .irq = 51 + OMAP_INTC_START, }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = { + { .name = "rx", .dma_req = 13 }, + { .dma_req = -1 } +}; + +struct omap_hwmod omap2xxx_sham_hwmod = { + .name = "sham", + .mpu_irqs = omap2_sham_mpu_irqs, + .sdma_reqs = omap2_sham_sdma_chs, + .main_clk = "l4_ck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 4, + .module_bit = OMAP24XX_EN_SHA_SHIFT, + .idlest_reg_id = 4, + .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT, + }, + }, + .class = &omap2xxx_sham_class, +}; + +/* AES */ + +static struct omap_hwmod_class_sysconfig omap2_aes_sysc = { + .rev_offs = 0x44, + .sysc_offs = 0x48, + .syss_offs = 0x4c, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2xxx_aes_class = { + .name = "aes", + .sysc = &omap2_aes_sysc, +}; + +static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = { + { .name = "tx", .dma_req = 9 }, + { .name = "rx", .dma_req = 10 }, + { .dma_req = -1 } +}; + +struct omap_hwmod omap2xxx_aes_hwmod = { + .name = "aes", + .sdma_reqs = omap2_aes_sdma_chs, + .main_clk = "l4_ck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 4, + .module_bit = OMAP24XX_EN_AES_SHIFT, + .idlest_reg_id = 4, + .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT, + }, + }, + .class = &omap2xxx_aes_class, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 26eee4a556ad..01d8f324450a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -28,6 +28,7 @@ #include "prm-regbits-33xx.h" #include "i2c.h" #include "mmc.h" +#include "wd_timer.h" /* * IP blocks @@ -417,8 +418,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { * - clkdiv32k * - debugss * - ocp watch point - * - aes0 - * - sha0 */ #if 0 /* @@ -499,25 +498,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { }, }, }; +#endif /* - * 'aes' class + * 'aes0' class */ -static struct omap_hwmod_class am33xx_aes_hwmod_class = { - .name = "aes", +static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { + .rev_offs = 0x80, + .sysc_offs = 0x84, + .syss_offs = 0x88, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class am33xx_aes0_hwmod_class = { + .name = "aes0", + .sysc = &am33xx_aes0_sysc, }; static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { - { .irq = 102 + OMAP_INTC_START, }, + { .irq = 103 + OMAP_INTC_START, }, { .irq = -1 }, }; +static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = { + { .name = "tx", .dma_req = 6, }, + { .name = "rx", .dma_req = 5, }, + { .dma_req = -1 } +}; + static struct omap_hwmod am33xx_aes0_hwmod = { - .name = "aes0", - .class = &am33xx_aes_hwmod_class, + .name = "aes", + .class = &am33xx_aes0_hwmod_class, .clkdm_name = "l3_clkdm", .mpu_irqs = am33xx_aes0_irqs, - .main_clk = "l3_gclk", + .sdma_reqs = am33xx_aes0_edma_reqs, + .main_clk = "aes0_fck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, @@ -526,21 +541,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = { }, }; -/* sha0 */ +/* sha0 HIB2 (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { + .rev_offs = 0x100, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + static struct omap_hwmod_class am33xx_sha0_hwmod_class = { .name = "sha0", + .sysc = &am33xx_sha0_sysc, }; static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { - { .irq = 108 + OMAP_INTC_START, }, + { .irq = 109 + OMAP_INTC_START, }, { .irq = -1 }, }; +static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = { + { .name = "rx", .dma_req = 36, }, + { .dma_req = -1 } +}; + static struct omap_hwmod am33xx_sha0_hwmod = { - .name = "sha0", + .name = "sham", .class = &am33xx_sha0_hwmod_class, .clkdm_name = "l3_clkdm", .mpu_irqs = am33xx_sha0_irqs, + .sdma_reqs = am33xx_sha0_edma_reqs, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -550,8 +579,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = { }, }; -#endif - /* ocmcram */ static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { .name = "ocmcram", @@ -2087,8 +2114,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = { }; /* 'wd_timer' class */ +static struct omap_hwmod_class_sysconfig wdt_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { .name = "wd_timer", + .sysc = &wdt_sysc, + .pre_shutdown = &omap2_wd_timer_disable, }; /* @@ -2099,6 +2139,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = { .name = "wd_timer2", .class = &am33xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE, .main_clk = "wdt1_fck", .prcm = { .omap4 = { @@ -3434,6 +3475,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3 main -> sha0 HIB2 */ +static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { + { + .pa_start = 0x53100000, + .pa_end = 0x53100000 + SZ_512 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_sha0_hwmod, + .clk = "sha0_fck", + .addr = am33xx_sha0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> AES0 HIB2 */ +static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { + { + .pa_start = 0x53500000, + .pa_end = 0x53500000 + SZ_1M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_aes0_hwmod, + .clk = "aes0_fck", + .addr = am33xx_aes0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_fw__emif_fw, &am33xx_l3_main__emif, @@ -3514,6 +3591,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_s__usbss, &am33xx_l4_hs__cpgmac0, &am33xx_cpgmac0__mdio, + &am33xx_l3_main__sha0, + &am33xx_l3_main__aes0, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ac7e03ec952f..4083606ea1da 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { * Erratum ID: i479 idle_req / idle_ack mechanism potentially * broken when autoidle is enabled * workaround is to disable the autoidle bit at module level. + * + * Enabling the device in any other MIDLEMODE setting but force-idle + * causes core_pwrdm not enter idle states at least on OMAP3630. + * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY + * signal when MIDLEMODE is set to force-idle. */ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, + | HWMOD_FORCE_MSTANDBY, }; /* usb_otg_hs */ @@ -3545,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ +static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { + .sidle_shift = 4, + .srst_shift = 1, + .autoidle_shift = 0, +}; + +static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { + .rev_offs = 0x5c, + .sysc_offs = 0x60, + .syss_offs = 0x64, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap3_sham_sysc_fields, +}; + +static struct omap_hwmod_class omap3xxx_sham_class = { + .name = "sham", + .sysc = &omap3_sham_sysc, +}; + +static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { + { .irq = 49 + OMAP_INTC_START, }, + { .irq = -1 } +}; + +static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap3xxx_sham_hwmod = { + .name = "sham", + .mpu_irqs = omap3_sham_mpu_irqs, + .sdma_reqs = omap3_sham_sdma_reqs, + .main_clk = "sha12_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_SHA12_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, + }, + }, + .class = &omap3xxx_sham_class, +}; + +static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { + { + .pa_start = 0x480c3000, + .pa_end = 0x480c3000 + 0x64 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_sham_hwmod, + .clk = "sha12_ick", + .addr = omap3xxx_sham_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> AES */ +static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { + .sidle_shift = 6, + .srst_shift = 1, + .autoidle_shift = 0, +}; + +static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { + .rev_offs = 0x44, + .sysc_offs = 0x48, + .syss_offs = 0x4c, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap3xxx_aes_sysc_fields, +}; + +static struct omap_hwmod_class omap3xxx_aes_class = { + .name = "aes", + .sysc = &omap3_aes_sysc, +}; + +static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, }, + { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod omap3xxx_aes_hwmod = { + .name = "aes", + .sdma_reqs = omap3_aes_sdma_reqs, + .main_clk = "aes2_ick", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_AES2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, + }, + }, + .class = &omap3xxx_aes_class, +}; + +static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { + { + .pa_start = 0x480c5000, + .pa_end = 0x480c5000 + 0x50 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_aes_hwmod, + .clk = "aes2_ick", + .addr = omap3xxx_aes_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3596,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { }; /* GP-only hwmod links */ -static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { +static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_sec__timer12, + &omap3xxx_l4_core__sham, + &omap3xxx_l4_core__aes, + NULL +}; + +static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_sec__timer12, + &omap3xxx_l4_core__sham, + &omap3xxx_l4_core__aes, + NULL +}; + +static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_sec__timer12, + /* + * Apparently the SHA/MD5 and AES accelerator IP blocks are + * only present on some AM35xx chips, and no one knows which + * ones. See + * http://www.spinics.net/lists/arm-kernel/msg215466.html So + * if you need these IP blocks on an AM35xx, try uncommenting + * the following lines. + */ + /* &omap3xxx_l4_core__sham, */ + /* &omap3xxx_l4_core__aes, */ NULL }; @@ -3704,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod_ocp_if **h = NULL; + struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL; unsigned int rev; omap_hwmod_init(); @@ -3714,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; - /* Register GP-only hwmod links. */ - if (omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); - if (r < 0) - return r; - } - rev = omap_rev(); /* @@ -3732,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void) rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap34xx_hwmod_ocp_ifs; + h_gp = omap34xx_gp_hwmod_ocp_ifs; } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { h = am35xx_hwmod_ocp_ifs; + h_gp = am35xx_gp_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { h = omap36xx_hwmod_ocp_ifs; + h_gp = omap36xx_gp_hwmod_ocp_ifs; } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; @@ -3746,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; + /* Register GP-only hwmod links. */ + if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { + r = omap_hwmod_register_links(h_gp); + if (r < 0) + return r; + } + + /* * Register hwmod links specific to certain ES levels of a * particular family of silicon (e.g., 34xx ES1.0) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0e47d2e1687c..eaba9dc91a0d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2719,7 +2719,17 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "func_48m_fclk", + /* + * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP + * block as an "optional clock," and normally should never be + * specified as the main_clk for an OMAP IP block. However it + * turns out that this clock is actually the main clock for + * the ocp2scp_usb_phy IP block: + * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html + * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems + * to be the best workaround. + */ + .main_clk = "ocp2scp_usb_phy_phy_48m", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index cfcce299177c..6e04ff7065e1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod; extern struct omap_hwmod omap2xxx_counter_32k_hwmod; extern struct omap_hwmod omap2xxx_gpmc_hwmod; extern struct omap_hwmod omap2xxx_rng_hwmod; +extern struct omap_hwmod omap2xxx_sham_hwmod; +extern struct omap_hwmod omap2xxx_aes_hwmod; /* Common interface data across OMAP2xxx */ extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; @@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1edd000a8143..0b339861d751 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -217,7 +217,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) return 0; d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); - if (!(IS_ERR_OR_NULL(d))) + if (d) (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, (void *)pwrdm, &pwrdm_suspend_fops); @@ -261,8 +261,8 @@ static int __init pm_dbg_init(void) return 0; d = debugfs_create_dir("pm_debug", NULL); - if (IS_ERR_OR_NULL(d)) - return PTR_ERR(d); + if (!d) + return -EINVAL; (void) debugfs_create_file("count", S_IRUGO, d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 673a4c1d1d76..e742118fcfd2 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -218,7 +218,7 @@ static int omap_pm_enter(suspend_state_t suspend_state) static int omap_pm_begin(suspend_state_t state) { - disable_hlt(); + cpu_idle_poll_ctrl(true); if (cpu_is_omap34xx()) omap_prcm_irq_prepare(); return 0; @@ -226,8 +226,7 @@ static int omap_pm_begin(suspend_state_t state) static void omap_pm_end(void) { - enable_hlt(); - return; + cpu_idle_poll_ctrl(false); } static void omap_pm_finish(void) @@ -265,6 +264,12 @@ static void __init omap4_init_voltages(void) omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); } +static inline void omap_init_cpufreq(void) +{ + struct platform_device_info devinfo = { .name = "omap-cpufreq", }; + platform_device_register_full(&devinfo); +} + static int __init omap2_common_pm_init(void) { if (!of_have_populated_dt()) @@ -294,6 +299,9 @@ int __init omap2_common_pm_late_init(void) /* Smartreflex device init */ omap_devinit_smartreflex(); + + /* cpufreq dummy device instantiation */ + omap_init_cpufreq(); } #ifdef CONFIG_SUSPEND diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index b59d93908341..ce956b0a7ba4 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -200,22 +200,17 @@ static int omap2_can_sleep(void) static void omap2_pm_idle(void) { - local_fiq_disable(); - if (!omap2_can_sleep()) { if (omap_irq_pending()) - goto out; + return; omap2_enter_mpu_retention(); - goto out; + return; } if (omap_irq_pending()) - goto out; + return; omap2_enter_full_retention(); - -out: - local_fiq_enable(); } static void __init prcm_setup_regs(void) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 2d93d8b23835..c01859398b54 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -346,19 +346,14 @@ void omap_sram_idle(void) static void omap3_pm_idle(void) { - local_fiq_disable(); - if (omap_irq_pending()) - goto out; + return; trace_cpu_idle(1, smp_processor_id()); omap_sram_idle(); trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); - -out: - local_fiq_enable(); } #ifdef CONFIG_SUSPEND @@ -757,14 +752,12 @@ int __init omap3_pm_init(void) pr_err("Memory allocation failed when allocating for secure sram context\n"); local_irq_disable(); - local_fiq_disable(); omap_dma_global_context_save(); omap3_save_secure_ram_context(); omap_dma_global_context_restore(); local_irq_enable(); - local_fiq_enable(); } omap3_save_scratchpad_contents(); diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index ea62e75ef21d..a251f87fa2a2 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -126,16 +126,12 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) * omap_default_idle - OMAP4 default ilde routine.' * * Implements OMAP4 memory, IO ordering requirements which can't be addressed - * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and - * by secondary CPU with CONFIG_CPUIDLE. + * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and + * by secondary CPU with CONFIG_CPU_IDLE. */ static void omap_default_idle(void) { - local_fiq_disable(); - omap_do_wfi(); - - local_fiq_enable(); } /** @@ -147,8 +143,8 @@ static void omap_default_idle(void) int __init omap4_pm_init(void) { int ret; - struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup; - struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; + struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; + struct clockdomain *ducati_clkdm, *l3_2_clkdm; if (omap_rev() == OMAP4430_REV_ES1_0) { WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); @@ -175,27 +171,19 @@ int __init omap4_pm_init(void) * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as * expected. The hardware recommendation is to enable static * dependencies for these to avoid system lock ups or random crashes. - * The L4 wakeup depedency is added to workaround the OCP sync hardware - * BUG with 32K synctimer which lead to incorrect timer value read - * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which - * are part of L4 wakeup clockdomain. */ mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); emif_clkdm = clkdm_lookup("l3_emif_clkdm"); l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); - l4_per_clkdm = clkdm_lookup("l4_per_clkdm"); - l4wkup = clkdm_lookup("l4_wkup_clkdm"); ducati_clkdm = clkdm_lookup("ducati_clkdm"); - if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) || - (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) + if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || + (!l3_2_clkdm) || (!ducati_clkdm)) goto err2; ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); - ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm); - ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup); ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); if (ret) { diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 8e61d80bf6b3..86babd740d41 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -52,7 +52,6 @@ enum { #define ALREADYACTIVE_SWITCH 0 #define FORCEWAKEUP_SWITCH 1 #define LOWPOWERSTATE_SWITCH 2 -#define ERROR_SWITCH 3 /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, { u8 sleep_switch; - if (curr_pwrst < 0) { - WARN_ON(1); - sleep_switch = ERROR_SWITCH; - } else if (curr_pwrst < PWRDM_POWER_ON) { + if (curr_pwrst < PWRDM_POWER_ON) { if (curr_pwrst > pwrst && pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && arch_pwrdm->pwrdm_set_lowpwrstchange) { @@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) */ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) { - u8 curr_pwrst, next_pwrst, sleep_switch; + u8 next_pwrst, sleep_switch; + int curr_pwrst; int ret = 0; bool hwsup = false; @@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) pwrdm_lock(pwrdm); curr_pwrst = pwrdm_read_pwrst(pwrdm); + if (curr_pwrst < 0) { + ret = -EINVAL; + goto osps_out; + } + next_pwrst = pwrdm_read_next_pwrst(pwrdm); if (curr_pwrst == pwrst && next_pwrst == pwrst) goto osps_out; sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, pwrst, &hwsup); - if (sleep_switch == ERROR_SWITCH) { - ret = -EINVAL; - goto osps_out; - } ret = pwrdm_set_next_pwrst(pwrdm, pwrst); if (ret) @@ -1182,7 +1180,7 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm) { int i; - if (IS_ERR_OR_NULL(pwrdm)) { + if (!pwrdm) { pr_debug("powerdomain: %s: invalid powerdomain pointer\n", __func__); return 1; diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index d35f98aabf7a..415c7e0c9393 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); + return __raw_readl(prm_base + inst + reg); } /* Write into a register in a CM/PRM instance in the PRM module */ void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); + __raw_writel(val, prm_base + inst + reg); } /* Read-modify-write a register in a PRM module. Caller must lock */ @@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx()) + if (!cpu_is_omap44xx() && !soc_is_omap54xx()) return 0; return prm_register(&omap44xx_prm_ll_data); diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index c62116bbc760..18fdeeb3a44a 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP54XX_CLASS 0x54000054 #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) +#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) +#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2bdd4cf17a8f..63e6384fa72e 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -62,6 +62,7 @@ #define OMAP2_MPU_SOURCE "sys_ck" #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE #define OMAP4_MPU_SOURCE "sys_clkin_ck" +#define OMAP5_MPU_SOURCE "sys_clkin" #define OMAP2_32K_SOURCE "func_32k_ck" #define OMAP3_32K_SOURCE "omap_32k_fck" #define OMAP4_32K_SOURCE "sys_32k_ck" @@ -287,7 +288,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, r = -EINVAL; } else { r = clk_set_parent(timer->fclk, src); - if (IS_ERR_VALUE(r)) + if (r < 0) pr_warn("%s: %s cannot set source\n", __func__, oh->name); clk_put(src); @@ -487,7 +488,7 @@ static void __init realtime_counter_init(void) pr_err("%s: ioremap failed\n", __func__); return; } - sys_clk = clk_get(NULL, "sys_clkin_ck"); + sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); @@ -547,6 +548,8 @@ static inline void __init realtime_counter_init(void) clksrc_nr, clksrc_src) \ void __init omap##name##_gptimer_timer_init(void) \ { \ + if (omap_clk_init) \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ @@ -556,6 +559,8 @@ void __init omap##name##_gptimer_timer_init(void) \ clksrc_nr, clksrc_src) \ void __init omap##name##_sync32k_timer_init(void) \ { \ + if (omap_clk_init) \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ /* Enable the use of clocksource="gp_timer" kernel parameter */ \ @@ -597,7 +602,7 @@ void __init omap4_local_timer_init(void) int err; if (of_have_populated_dt()) { - twd_local_timer_of_register(); + clocksource_of_init(); return; } @@ -616,7 +621,7 @@ void __init omap4_local_timer_init(void) #ifdef CONFIG_SOC_OMAP5 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", - 2, OMAP4_MPU_SOURCE); + 2, OMAP5_MPU_SOURCE); void __init omap5_realtime_timer_init(void) { int err; |