diff options
Diffstat (limited to 'arch/arm/mach-prima2')
| -rw-r--r-- | arch/arm/mach-prima2/Kconfig | 7 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/common.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/common.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/l2x0.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/platsmp.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/rstc.c | 99 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/rtciobrg.c | 2 |
7 files changed, 77 insertions, 58 deletions
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 6988b117fc17..3e8189186a5b 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -1,9 +1,8 @@ config ARCH_SIRF bool "CSR SiRF" if ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER select ARCH_REQUIRE_GPIOLIB - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select MIGHT_HAVE_CACHE_L2X0 select NO_IOPORT select PINCTRL select PINCTRL_SIRF @@ -17,7 +16,6 @@ menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" config ARCH_ATLAS6 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" default y - select CPU_V7 select SIRF_IRQ help Support for CSR SiRFSoC ARM Cortex A9 Platform @@ -25,7 +23,6 @@ config ARCH_ATLAS6 config ARCH_PRIMA2 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" default y - select CPU_V7 select SIRF_IRQ select ZONE_DMA help @@ -35,9 +32,7 @@ config ARCH_MARCO bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform" default y select ARM_GIC - select CPU_V7 select HAVE_ARM_SCU if SMP - select HAVE_SMP select SMP_ON_UP if SMP help Support for CSR SiRFSoC ARM Cortex A9 Platform diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index d49aff74de98..47c7819edb9b 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -15,7 +15,7 @@ #include <linux/of_platform.h> #include "common.h" -void __init sirfsoc_init_late(void) +static void __init sirfsoc_init_late(void) { sirfsoc_pm_init(); } @@ -27,7 +27,7 @@ static __init void sirfsoc_map_io(void) } #ifdef CONFIG_ARCH_ATLAS6 -static const char *atlas6_dt_match[] __initdata = { +static const char *atlas6_dt_match[] __initconst = { "sirf,atlas6", NULL }; @@ -37,12 +37,11 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") .map_io = sirfsoc_map_io, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, - .restart = sirfsoc_restart, MACHINE_END #endif #ifdef CONFIG_ARCH_PRIMA2 -static const char *prima2_dt_match[] __initdata = { +static const char *prima2_dt_match[] __initconst = { "sirf,prima2", NULL }; @@ -53,12 +52,11 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") .dma_zone_size = SZ_256M, .init_late = sirfsoc_init_late, .dt_compat = prima2_dt_match, - .restart = sirfsoc_restart, MACHINE_END #endif #ifdef CONFIG_ARCH_MARCO -static const char *marco_dt_match[] __initdata = { +static const char *marco_dt_match[] __initconst = { "sirf,marco", NULL }; @@ -69,6 +67,5 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") .map_io = sirfsoc_map_io, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, - .restart = sirfsoc_restart, MACHINE_END #endif diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 4b768060a858..07d3e5ed9264 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -23,7 +23,6 @@ extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); extern void __init sirfsoc_of_irq_init(void); -extern void sirfsoc_restart(enum reboot_mode, const char *); extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); #ifndef CONFIG_DEBUG_LL diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c index cbcbe9cb094c..c7102539c0b0 100644 --- a/arch/arm/mach-prima2/l2x0.c +++ b/arch/arm/mach-prima2/l2x0.c @@ -11,24 +11,23 @@ #include <linux/of.h> #include <asm/hardware/cache-l2x0.h> -struct l2x0_aux -{ +struct l2x0_aux { u32 val; u32 mask; }; -static struct l2x0_aux prima2_l2x0_aux __initconst = { +static const struct l2x0_aux prima2_l2x0_aux __initconst = { .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT, .mask = 0, }; -static struct l2x0_aux marco_l2x0_aux __initconst = { +static const struct l2x0_aux marco_l2x0_aux __initconst = { .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), .mask = L2X0_AUX_CTRL_MASK, }; -static struct of_device_id sirf_l2x0_ids[] __initconst = { +static const struct of_device_id sirf_l2x0_ids[] __initconst = { { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, }, { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, }, {}, diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index e358b0736dea..335c12e92262 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -138,9 +138,9 @@ static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus) } struct smp_operations sirfsoc_smp_ops __initdata = { - .smp_prepare_cpus = sirfsoc_smp_prepare_cpus, - .smp_secondary_init = sirfsoc_secondary_init, - .smp_boot_secondary = sirfsoc_boot_secondary, + .smp_prepare_cpus = sirfsoc_smp_prepare_cpus, + .smp_secondary_init = sirfsoc_secondary_init, + .smp_boot_secondary = sirfsoc_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = sirfsoc_cpu_die, #endif diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c index ccb53391147a..4887a2a4c698 100644 --- a/arch/arm/mach-prima2/rstc.c +++ b/arch/arm/mach-prima2/rstc.c @@ -13,57 +13,38 @@ #include <linux/device.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/platform_device.h> #include <linux/reboot.h> +#include <linux/reset-controller.h> -void __iomem *sirfsoc_rstc_base; -static DEFINE_MUTEX(rstc_lock); - -static struct of_device_id rstc_ids[] = { - { .compatible = "sirf,prima2-rstc" }, - { .compatible = "sirf,marco-rstc" }, - {}, -}; +#include <asm/system_misc.h> -static int __init sirfsoc_of_rstc_init(void) -{ - struct device_node *np; +#define SIRFSOC_RSTBIT_NUM 64 - np = of_find_matching_node(NULL, rstc_ids); - if (!np) { - pr_err("unable to find compatible sirf rstc node in dtb\n"); - return -ENOENT; - } - - sirfsoc_rstc_base = of_iomap(np, 0); - if (!sirfsoc_rstc_base) - panic("unable to map rstc cpu registers\n"); - - of_node_put(np); - - return 0; -} -early_initcall(sirfsoc_of_rstc_init); +static void __iomem *sirfsoc_rstc_base; +static DEFINE_MUTEX(rstc_lock); -int sirfsoc_reset_device(struct device *dev) +static int sirfsoc_reset_module(struct reset_controller_dev *rcdev, + unsigned long sw_reset_idx) { - u32 reset_bit; + u32 reset_bit = sw_reset_idx; - if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit)) + if (reset_bit >= SIRFSOC_RSTBIT_NUM) return -EINVAL; mutex_lock(&rstc_lock); - if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) { + if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) { /* * Writing 1 to this bit resets corresponding block. Writing 0 to this * bit de-asserts reset signal of the corresponding block. * datasheet doesn't require explicit delay between the set and clear * of reset bit. it could be shorter if tests pass. */ - writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit, + writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit), sirfsoc_rstc_base + (reset_bit / 32) * 4); msleep(10); - writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit, + writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit), sirfsoc_rstc_base + (reset_bit / 32) * 4); } else { /* @@ -73,9 +54,9 @@ int sirfsoc_reset_device(struct device *dev) * datasheet doesn't require explicit delay between the set and clear * of reset bit. it could be shorter if tests pass. */ - writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8); + writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8); msleep(10); - writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4); + writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4); } mutex_unlock(&rstc_lock); @@ -83,9 +64,57 @@ int sirfsoc_reset_device(struct device *dev) return 0; } +static struct reset_control_ops sirfsoc_rstc_ops = { + .reset = sirfsoc_reset_module, +}; + +static struct reset_controller_dev sirfsoc_reset_controller = { + .ops = &sirfsoc_rstc_ops, + .nr_resets = SIRFSOC_RSTBIT_NUM, +}; + #define SIRFSOC_SYS_RST_BIT BIT(31) -void sirfsoc_restart(enum reboot_mode mode, const char *cmd) +static void sirfsoc_restart(enum reboot_mode mode, const char *cmd) { writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); } + +static int sirfsoc_rstc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + sirfsoc_rstc_base = of_iomap(np, 0); + if (!sirfsoc_rstc_base) { + dev_err(&pdev->dev, "unable to map rstc cpu registers\n"); + return -ENOMEM; + } + + sirfsoc_reset_controller.of_node = np; + arm_pm_restart = sirfsoc_restart; + + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + reset_controller_register(&sirfsoc_reset_controller); + + return 0; +} + +static const struct of_device_id rstc_ids[] = { + { .compatible = "sirf,prima2-rstc" }, + { .compatible = "sirf,marco-rstc" }, + {}, +}; + +static struct platform_driver sirfsoc_rstc_driver = { + .probe = sirfsoc_rstc_probe, + .driver = { + .name = "sirfsoc_rstc", + .owner = THIS_MODULE, + .of_match_table = rstc_ids, + }, +}; + +static int __init sirfsoc_rstc_init(void) +{ + return platform_driver_register(&sirfsoc_rstc_driver); +} +subsys_initcall(sirfsoc_rstc_init); diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c index 9f2da2eec4dc..a17c88b74fa1 100644 --- a/arch/arm/mach-prima2/rtciobrg.c +++ b/arch/arm/mach-prima2/rtciobrg.c @@ -137,4 +137,4 @@ postcore_initcall(sirfsoc_rtciobrg_init); MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, " "Barry Song <baohua.song@csr.com>"); MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); -MODULE_LICENSE("GPL"); +MODULE_LICENSE("GPL v2"); |