diff options
Diffstat (limited to 'arch/arm/mach-prima2')
| -rw-r--r-- | arch/arm/mach-prima2/Kconfig | 23 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/common.c | 37 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/common.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/clkdev.h | 15 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/debug-macro.S | 29 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/entry-macro.S | 22 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/hardware.h | 15 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/irqs.h | 17 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/map.h | 18 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/timex.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/uart.h | 29 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/include/mach/uncompress.h | 41 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/irq.c | 129 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/lluart.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/platsmp.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/timer-marco.c | 316 | ||||
| -rw-r--r-- | arch/arm/mach-prima2/timer-prima2.c | 241 |
18 files changed, 69 insertions, 909 deletions
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 4f7379fe01e2..80ca974b2f82 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -1,6 +1,26 @@ +config ARCH_SIRF + bool "CSR SiRF" if ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select MIGHT_HAVE_CACHE_L2X0 + select NO_IOPORT + select PINCTRL + select PINCTRL_SIRF + help + Support for CSR SiRFprimaII/Marco/Polo platforms + if ARCH_SIRF -menu "CSR SiRF primaII/Marco/Polo Specific Features" +menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" + +config ARCH_ATLAS6 + bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" + default y + select CPU_V7 + select SIRF_IRQ + help + Support for CSR SiRFSoC ARM Cortex A9 Platform config ARCH_PRIMA2 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" @@ -16,6 +36,7 @@ config ARCH_MARCO default y select ARM_GIC select CPU_V7 + select HAVE_ARM_SCU if SMP select HAVE_SMP select SMP_ON_UP help diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index bfe360cbd177..7a6b4a323125 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -4,8 +4,7 @@ obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o -obj-$(CONFIG_SIRF_IRQ) += irq.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o -obj-$(CONFIG_ARCH_MARCO) += timer-marco.o + +CFLAGS_hotplug.o += -march=armv7-a diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 2d57aa479a7b..4f94cd87972a 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -6,6 +6,7 @@ * Licensed under GPLv2 or later. */ +#include <linux/clocksource.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/irqchip.h> @@ -31,12 +32,38 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } +static __init void sirfsoc_init_time(void) +{ + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); + clocksource_of_init(); +} + static __init void sirfsoc_map_io(void) { sirfsoc_map_lluart(); sirfsoc_map_scu(); } +#ifdef CONFIG_ARCH_ATLAS6 +static const char *atlas6_dt_match[] __initdata = { + "sirf,atlas6", + NULL +}; + +DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") + /* Maintainer: Barry Song <baohua.song@csr.com> */ + .nr_irqs = 128, + .map_io = sirfsoc_map_io, + .init_irq = irqchip_init, + .init_time = sirfsoc_init_time, + .init_machine = sirfsoc_mach_init, + .init_late = sirfsoc_init_late, + .dt_compat = atlas6_dt_match, + .restart = sirfsoc_restart, +MACHINE_END +#endif + #ifdef CONFIG_ARCH_PRIMA2 static const char *prima2_dt_match[] __initdata = { "sirf,prima2", @@ -45,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ + .nr_irqs = 128, .map_io = sirfsoc_map_io, - .init_irq = sirfsoc_of_irq_init, - .init_time = sirfsoc_prima2_timer_init, -#ifdef CONFIG_MULTI_IRQ_HANDLER - .handle_irq = sirfsoc_handle_irq, -#endif + .init_irq = irqchip_init, + .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, @@ -70,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, .init_irq = irqchip_init, - .init_time = sirfsoc_marco_timer_init, + .init_time = sirfsoc_init_time, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index b7c26b62e4a7..81135cd88e54 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -13,8 +13,8 @@ #include <asm/mach/time.h> #include <asm/exception.h> -extern void sirfsoc_prima2_timer_init(void); -extern void sirfsoc_marco_timer_init(void); +#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) +#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) extern struct smp_operations sirfsoc_smp_ops; extern void sirfsoc_secondary_startup(void); diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h deleted file mode 100644 index 66932518b1b7..000000000000 --- a/arch/arm/mach-prima2/include/mach/clkdev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/clkdev.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S deleted file mode 100644 index cd97492bb075..000000000000 --- a/arch/arm/mach-prima2/include/mach/debug-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/debug-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <mach/hardware.h> -#include <mach/uart.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical - ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] - .endm - - .macro busyuart,rd,rx - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] - tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY - beq 1001b - .endm - diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S deleted file mode 100644 index 86434e7a5be9..000000000000 --- a/arch/arm/mach-prima2/include/mach/entry-macro.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/entry-macro.S - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <mach/hardware.h> - -#define SIRFSOC_INT_ID 0x38 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =sirfsoc_intc_base - ldr \base, [\base] - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq - cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f - movges \irqnr, #0 - .endm diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h deleted file mode 100644 index 105b96964f25..000000000000 --- a/arch/arm/mach-prima2/include/mach/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/hardware.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_HARDWARE_H__ -#define __MACH_HARDWARE_H__ - -#include <asm/sizes.h> -#include <mach/map.h> - -#endif diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h deleted file mode 100644 index b778a0f248ed..000000000000 --- a/arch/arm/mach-prima2/include/mach/irqs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/irqs.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define SIRFSOC_INTENAL_IRQ_START 0 -#define SIRFSOC_INTENAL_IRQ_END 127 -#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1) -#define NR_IRQS 288 - -#endif diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h deleted file mode 100644 index 6f243532570c..000000000000 --- a/arch/arm/mach-prima2/include/mach/map.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * memory & I/O static mapping definitions for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_MAP_H__ -#define __MACH_PRIMA2_MAP_H__ - -#include <linux/const.h> - -#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) - -#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h deleted file mode 100644 index d6f98a75e562..000000000000 --- a/arch/arm/mach-prima2/include/mach/timex.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/timex.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_TIMEX_H__ -#define __MACH_TIMEX_H__ - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h deleted file mode 100644 index c10510d01a44..000000000000 --- a/arch/arm/mach-prima2/include/mach/uart.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uart.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __MACH_PRIMA2_SIRFSOC_UART_H -#define __MACH_PRIMA2_SIRFSOC_UART_H - -/* UART-1: used as serial debug port */ -#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) -#define SIRFSOC_UART1_PA_BASE 0xb0060000 -#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) -#define SIRFSOC_UART1_PA_BASE 0xcc060000 -#else -#define SIRFSOC_UART1_PA_BASE 0 -#endif -#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) -#define SIRFSOC_UART1_SIZE SZ_4K - -#define SIRFSOC_UART_TXFIFO_STATUS 0x0114 -#define SIRFSOC_UART_TXFIFO_DATA 0x0118 - -#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) -#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) - -#endif diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h deleted file mode 100644 index d1513a33709a..000000000000 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-prima2/include/mach/uncompress.h - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/uart.h> - -void arch_decomp_setup(void) -{ -} - -static __inline__ void putc(char c) -{ - /* - * during kernel decompression, all mappings are flat: - * virt_addr == phys_addr - */ - if (!SIRFSOC_UART1_PA_BASE) - return; - - while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) - & SIRFSOC_UART1_TXFIFO_FULL) - barrier(); - - __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); -} - -static inline void flush(void) -{ -} - -#endif - diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c deleted file mode 100644 index 6c0f3e9c43fb..000000000000 --- a/arch/arm/mach-prima2/irq.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * interrupt controller support for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/irqdomain.h> -#include <linux/syscore_ops.h> -#include <asm/mach/irq.h> -#include <asm/exception.h> -#include <mach/hardware.h> - -#define SIRFSOC_INT_RISC_MASK0 0x0018 -#define SIRFSOC_INT_RISC_MASK1 0x001C -#define SIRFSOC_INT_RISC_LEVEL0 0x0020 -#define SIRFSOC_INT_RISC_LEVEL1 0x0024 -#define SIRFSOC_INIT_IRQ_ID 0x0038 - -void __iomem *sirfsoc_intc_base; - -static __init void -sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); - ct = gc->chip_types; - - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->regs.mask = SIRFSOC_INT_RISC_MASK0; - - irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); -} - -static __init void sirfsoc_irq_init(void) -{ - sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); - sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, - SIRFSOC_INTENAL_IRQ_END + 1 - 32); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); -} - -asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) -{ - u32 irqstat, irqnr; - - irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID); - irqnr = irqstat & 0xff; - - handle_IRQ(irqnr, regs); -} - -static struct of_device_id intc_ids[] = { - { .compatible = "sirf,prima2-intc" }, - {}, -}; - -void __init sirfsoc_of_irq_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, intc_ids); - if (!np) - return; - - sirfsoc_intc_base = of_iomap(np, 0); - if (!sirfsoc_intc_base) - panic("unable to map intc cpu registers\n"); - - irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, - &irq_domain_simple_ops, NULL); - - of_node_put(np); - - sirfsoc_irq_init(); -} - -struct sirfsoc_irq_status { - u32 mask0; - u32 mask1; - u32 level0; - u32 level1; -}; - -static struct sirfsoc_irq_status sirfsoc_irq_st; - -static int sirfsoc_irq_suspend(void) -{ - sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); - - return 0; -} - -static void sirfsoc_irq_resume(void) -{ - writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); - writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); - writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); - writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); -} - -static struct syscore_ops sirfsoc_irq_syscore_ops = { - .suspend = sirfsoc_irq_suspend, - .resume = sirfsoc_irq_resume, -}; - -static int __init sirfsoc_irq_pm_init(void) -{ - register_syscore_ops(&sirfsoc_irq_syscore_ops); - return 0; -} -device_initcall(sirfsoc_irq_pm_init); diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index a89f9b3c8cc5..99c0c927ca4a 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c @@ -9,8 +9,18 @@ #include <linux/kernel.h> #include <asm/page.h> #include <asm/mach/map.h> -#include <mach/map.h> -#include <mach/uart.h> +#include "common.h" + +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) +#define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif + +#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) +#define SIRFSOC_UART1_SIZE SZ_4K void __init sirfsoc_map_lluart(void) { diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 4b788310f6a6..1c3de7bed841 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -11,14 +11,12 @@ #include <linux/delay.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/mach/map.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> #include <asm/cacheflush.h> #include <asm/cputype.h> -#include <mach/map.h> #include "common.h" @@ -49,13 +47,6 @@ void __init sirfsoc_map_scu(void) static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) { /* - * if any interrupts are already enabled for the primary - * core (e.g. timer irq), then they will not have been enabled - * for us: do so - */ - gic_secondary_init(0); - - /* * let the primary processor know we're out of the * pen, then head off into the C entry point */ diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c deleted file mode 100644 index f4eea2e97eb0..000000000000 --- a/arch/arm/mach-prima2/timer-marco.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> -#include <linux/bitops.h> -#include <linux/irq.h> -#include <linux/clk.h> -#include <linux/slab.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <linux/of_address.h> -#include <asm/sched_clock.h> -#include <asm/localtimer.h> -#include <asm/mach/time.h> - -#include "common.h" - -#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 -#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0018 -#define SIRFSOC_TIMER_MATCH_1 0x001c -#define SIRFSOC_TIMER_COUNTER_0 0x0048 -#define SIRFSOC_TIMER_COUNTER_1 0x004c -#define SIRFSOC_TIMER_INTR_STATUS 0x0060 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064 -#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068 -#define SIRFSOC_TIMER_64COUNTER_LO 0x006c -#define SIRFSOC_TIMER_64COUNTER_HI 0x0070 -#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074 -#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078 -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c -#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080 - -#define SIRFSOC_TIMER_REG_CNT 6 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_WATCHDOG_EN, - SIRFSOC_TIMER_32COUNTER_0_CTRL, - SIRFSOC_TIMER_32COUNTER_1_CTRL, - SIRFSOC_TIMER_64COUNTER_CTRL, - SIRFSOC_TIMER_64COUNTER_RLATCHED_LO, - SIRFSOC_TIMER_64COUNTER_RLATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* disable count and interrupt */ -static inline void sirfsoc_timer_count_disable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* enable count and interrupt */ -static inline void sirfsoc_timer_count_enable(int idx) -{ - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7, - sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); -} - -/* timer interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - int cpu = smp_processor_id(); - - /* clear timer interrupt */ - writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - if (ce->mode == CLOCK_EVT_MODE_ONESHOT) - sirfsoc_timer_count_disable(cpu); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - int cpu = smp_processor_id(); - - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + - 4 * cpu); - writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + - 4 * cpu); - - /* enable the tick */ - sirfsoc_timer_count_enable(cpu); - - return 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - switch (mode) { - case CLOCK_EVT_MODE_ONESHOT: - /* enable in set_next_event */ - break; - default: - break; - } - - sirfsoc_timer_count_disable(smp_processor_id()); -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], - sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -#ifdef CONFIG_LOCAL_TIMERS - -static struct irqaction sirfsoc_timer1_irq = { - .name = "sirfsoc_timer1", - .flags = IRQF_TIMER | IRQF_NOBALANCING, - .handler = sirfsoc_timer_interrupt, -}; - -static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce) -{ - /* Use existing clock_event for cpu 0 */ - if (!smp_processor_id()) - return 0; - - ce->irq = sirfsoc_timer1_irq.irq; - ce->name = "local_timer"; - ce->features = sirfsoc_clockevent.features; - ce->rating = sirfsoc_clockevent.rating; - ce->set_mode = sirfsoc_timer_set_mode; - ce->set_next_event = sirfsoc_timer_set_next_event; - ce->shift = sirfsoc_clockevent.shift; - ce->mult = sirfsoc_clockevent.mult; - ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns; - ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns; - - sirfsoc_timer1_irq.dev_id = ce; - BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq)); - irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1)); - - clockevents_register_device(ce); - return 0; -} - -static void sirfsoc_local_timer_stop(struct clock_event_device *ce) -{ - sirfsoc_timer_count_disable(1); - - remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq); -} - -static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = { - .setup = sirfsoc_local_timer_setup, - .stop = sirfsoc_local_timer_stop, -}; -#endif /* CONFIG_LOCAL_TIMERS */ - -static void __init sirfsoc_clockevent_init(void) -{ - clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); - - sirfsoc_clockevent.max_delta_ns = - clockevent_delta2ns(-2, &sirfsoc_clockevent); - sirfsoc_clockevent.min_delta_ns = - clockevent_delta2ns(2, &sirfsoc_clockevent); - - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&sirfsoc_clockevent); -#ifdef CONFIG_LOCAL_TIMERS - local_timer_register(&sirfsoc_local_timer_ops); -#endif -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_marco_timer_init(void) -{ - unsigned long rate; - u32 timer_div; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - /* Initialize the timer dividers */ - timer_div = rate / CLOCK_TICK_RATE - 1; - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); - writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); - - /* Initialize timer counters to 0 */ - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); - writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | - BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); - - /* Clear all interrupts */ - writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,marco-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); - if (!sirfsoc_timer_irq.irq) - panic("No irq passed for timer0 via DT\n"); - -#ifdef CONFIG_LOCAL_TIMERS - sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1); - if (!sirfsoc_timer1_irq.irq) - panic("No irq passed for timer1 via DT\n"); -#endif - - of_node_put(np); -} diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c deleted file mode 100644 index 6da584f8a949..000000000000 --- a/arch/arm/mach-prima2/timer-prima2.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * System timer for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> -#include <linux/bitops.h> -#include <linux/irq.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <mach/map.h> -#include <asm/sched_clock.h> -#include <asm/mach/time.h> - -#include "common.h" - -#define SIRFSOC_TIMER_COUNTER_LO 0x0000 -#define SIRFSOC_TIMER_COUNTER_HI 0x0004 -#define SIRFSOC_TIMER_MATCH_0 0x0008 -#define SIRFSOC_TIMER_MATCH_1 0x000C -#define SIRFSOC_TIMER_MATCH_2 0x0010 -#define SIRFSOC_TIMER_MATCH_3 0x0014 -#define SIRFSOC_TIMER_MATCH_4 0x0018 -#define SIRFSOC_TIMER_MATCH_5 0x001C -#define SIRFSOC_TIMER_STATUS 0x0020 -#define SIRFSOC_TIMER_INT_EN 0x0024 -#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028 -#define SIRFSOC_TIMER_DIV 0x002C -#define SIRFSOC_TIMER_LATCH 0x0030 -#define SIRFSOC_TIMER_LATCHED_LO 0x0034 -#define SIRFSOC_TIMER_LATCHED_HI 0x0038 - -#define SIRFSOC_TIMER_WDT_INDEX 5 - -#define SIRFSOC_TIMER_LATCH_BIT BIT(0) - -#define SIRFSOC_TIMER_REG_CNT 11 - -static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { - SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2, - SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5, - SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV, - SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI, -}; - -static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; - -static void __iomem *sirfsoc_timer_base; -static void __init sirfsoc_of_timer_map(void); - -/* timer0 interrupt handler */ -static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - - WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); - - /* clear timer0 interrupt */ - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -/* read 64-bit timer counter */ -static cycle_t sirfsoc_timer_read(struct clocksource *cs) -{ - u64 cycles; - - /* latch the 64-bit timer counter */ - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); - cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return cycles; -} - -static int sirfsoc_timer_set_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - unsigned long now, next; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - next = now + delta; - writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); - - return next - now > delta ? -ETIME : 0; -} - -static void sirfsoc_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *ce) -{ - u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - WARN_ON(1); - break; - case CLOCK_EVT_MODE_ONESHOT: - writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static void sirfsoc_clocksource_suspend(struct clocksource *cs) -{ - int i; - - writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) - sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); -} - -static void sirfsoc_clocksource_resume(struct clocksource *cs) -{ - int i; - - for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) - writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); - - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); -} - -static struct clock_event_device sirfsoc_clockevent = { - .name = "sirfsoc_clockevent", - .rating = 200, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = sirfsoc_timer_set_mode, - .set_next_event = sirfsoc_timer_set_next_event, -}; - -static struct clocksource sirfsoc_clocksource = { - .name = "sirfsoc_clocksource", - .rating = 200, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = sirfsoc_timer_read, - .suspend = sirfsoc_clocksource_suspend, - .resume = sirfsoc_clocksource_resume, -}; - -static struct irqaction sirfsoc_timer_irq = { - .name = "sirfsoc_timer0", - .flags = IRQF_TIMER, - .irq = 0, - .handler = sirfsoc_timer_interrupt, - .dev_id = &sirfsoc_clockevent, -}; - -/* Overwrite weak default sched_clock with more precise one */ -static u32 notrace sirfsoc_read_sched_clock(void) -{ - return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff); -} - -static void __init sirfsoc_clockevent_init(void) -{ - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, - 2, -2); -} - -/* initialize the kernel jiffy timer source */ -void __init sirfsoc_prima2_timer_init(void) -{ - unsigned long rate; - struct clk *clk; - - /* initialize clocking early, we want to set the OS timer */ - sirfsoc_of_clk_init(); - - /* timer's input clock is io clock */ - clk = clk_get_sys("io", NULL); - - BUG_ON(IS_ERR(clk)); - - rate = clk_get_rate(clk); - - BUG_ON(rate < CLOCK_TICK_RATE); - BUG_ON(rate % CLOCK_TICK_RATE); - - sirfsoc_of_timer_map(); - - writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); - writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); - writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); - - BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); - - setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE); - - BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); - - sirfsoc_clockevent_init(); -} - -static struct of_device_id timer_ids[] = { - { .compatible = "sirf,prima2-tick" }, - {}, -}; - -static void __init sirfsoc_of_timer_map(void) -{ - struct device_node *np; - const unsigned int *intspec; - - np = of_find_matching_node(NULL, timer_ids); - if (!np) - return; - sirfsoc_timer_base = of_iomap(np, 0); - if (!sirfsoc_timer_base) - panic("unable to map timer cpu registers\n"); - - /* Get the interrupts property */ - intspec = of_get_property(np, "interrupts", NULL); - BUG_ON(!intspec); - sirfsoc_timer_irq.irq = be32_to_cpup(intspec); - - of_node_put(np); -} |