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-rw-r--r--arch/arm/mach-tegra/reset-handler.S21
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 39dc9e7834f3..f527b2c2dea7 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -40,9 +40,12 @@
* re-enabling sdram.
*
* r6: SoC ID
+ * r8: CPU part number
*/
ENTRY(tegra_resume)
- bl v7_invalidate_l1
+ check_cpu_part_num 0xc09, r8, r9
+ bleq v7_invalidate_l1
+ blne tegra_init_l2_for_a15
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@@ -70,7 +73,8 @@ no_cpu0_chk:
str r1, [r2]
1:
- check_cpu_part_num 0xc09, r8, r9
+ mov32 r9, 0xc09
+ cmp r8, r9
bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */
@@ -178,6 +182,19 @@ after_errata:
1:
#endif
+ /* Waking up from LP1? */
+ ldr r8, [r12, #RESET_DATA(MASK_LP1)]
+ tst r8, r11 @ if in_lp1
+ beq __is_not_lp1
+ cmp r10, #0
+ bne __die @ only CPU0 can be here
+ ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
+ cmp lr, #0
+ bleq __die @ no LP1 startup handler
+ THUMB( add lr, lr, #1 ) @ switch to Thumb mode
+ bx lr
+__is_not_lp1:
+
/* Waking up from LP2? */
ldr r9, [r12, #RESET_DATA(MASK_LP2)]
tst r9, r11 @ if in_lp2