diff options
Diffstat (limited to 'arch/arm/plat-nomadik')
| -rw-r--r-- | arch/arm/plat-nomadik/Kconfig | 22 | ||||
| -rw-r--r-- | arch/arm/plat-nomadik/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/plat-nomadik/include/plat/mtu.h | 48 | ||||
| -rw-r--r-- | arch/arm/plat-nomadik/timer.c | 147 |
4 files changed, 222 insertions, 0 deletions
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig new file mode 100644 index 000000000000..159daf583f85 --- /dev/null +++ b/arch/arm/plat-nomadik/Kconfig @@ -0,0 +1,22 @@ +# We keep common IP's here for Nomadik and other similar +# familiy of processors from ST-Ericsson. At the moment we have +# just MTU, others to follow soon. + +config PLAT_NOMADIK + bool + depends on ARCH_NOMADIK || ARCH_U8500 + default y + help + Common platform code for Nomadik and other ST-Ericsson + platforms. + +if PLAT_NOMADIK + +config HAS_MTU + bool + help + Support for Multi Timer Unit. MTU provides access + to multiple interrupt generating programmable + 32-bit free running decrementing counters. + +endif diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile new file mode 100644 index 000000000000..37c7cdd0f8f0 --- /dev/null +++ b/arch/arm/plat-nomadik/Makefile @@ -0,0 +1,5 @@ +# arch/arm/plat-nomadik/Makefile +# Copyright 2009 ST-Ericsson +# Licensed under GPLv2 + +obj-$(CONFIG_HAS_MTU) += timer.o diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h new file mode 100644 index 000000000000..42c907258b14 --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/mtu.h @@ -0,0 +1,48 @@ +#ifndef __PLAT_MTU_H +#define __PLAT_MTU_H + +/* should be set by the platform code */ +extern void __iomem *mtu_base; + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#endif /* __PLAT_MTU_H */ + diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c new file mode 100644 index 000000000000..62f18ad43a28 --- /dev/null +++ b/arch/arm/plat-nomadik/timer.c @@ -0,0 +1,147 @@ +/* + * linux/arch/arm/mach-nomadik/timer.c + * + * Copyright (C) 2008 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clockchips.h> +#include <linux/jiffies.h> +#include <asm/mach/time.h> + +#include <plat/mtu.h> + +static u32 nmdk_count; /* accumulated count */ +static u32 nmdk_cycle; /* write-once */ + +/* setup by the platform code */ +void __iomem *mtu_base; + +/* + * clocksource: the MTU device is a decrementing counters, so we negate + * the value being read. + */ +static cycle_t nmdk_read_timer(struct clocksource *cs) +{ + u32 count = readl(mtu_base + MTU_VAL(0)); + return nmdk_count + nmdk_cycle - count; + +} + +static struct clocksource nmdk_clksrc = { + .name = "mtu_0", + .rating = 120, + .read = nmdk_read_timer, + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * Clockevent device: currently only periodic mode is supported + */ +static void nmdk_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + unsigned long flags; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* enable interrupts -- and count current value? */ + raw_local_irq_save(flags); + writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC); + raw_local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_ONESHOT: + BUG(); /* Not supported, yet */ + /* FALLTHROUGH */ + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + /* disable irq */ + raw_local_irq_save(flags); + writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC); + raw_local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device nmdk_clkevt = { + .name = "mtu_0", + .features = CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .rating = 100, + .set_mode = nmdk_clkevt_mode, +}; + +/* + * IRQ Handler for the timer 0 of the MTU block. The irq is not shared + * as we are the only users of mtu0 by now. + */ +static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) +{ + /* ack: "interrupt clear register" */ + writel(1 << 0, mtu_base + MTU_ICR); + + /* we can't count lost ticks, unfortunately */ + nmdk_count += nmdk_cycle; + nmdk_clkevt.event_handler(&nmdk_clkevt); + + return IRQ_HANDLED; +} + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +static struct irqaction nmdk_timer_irq = { + .name = "Nomadik Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = nmdk_timer_interrupt, +}; + +static void nmdk_timer_reset(void) +{ + u32 cr; + + writel(0, mtu_base + MTU_CR(0)); /* off */ + + /* configure load and background-load, and fire it up */ + writel(nmdk_cycle, mtu_base + MTU_LR(0)); + writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); + cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS; + writel(cr, mtu_base + MTU_CR(0)); + writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); +} + +void __init nmdk_timer_init(void) +{ + unsigned long rate; + int bits; + + rate = CLOCK_TICK_RATE; /* 2.4MHz */ + nmdk_cycle = (rate + HZ/2) / HZ; + + /* Init the timer and register clocksource */ + nmdk_timer_reset(); + + nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift); + bits = 8*sizeof(nmdk_count); + nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits); + + if (clocksource_register(&nmdk_clksrc)) + printk(KERN_ERR "timer: failed to initialize clock " + "source %s\n", nmdk_clksrc.name); + + /* Register irq and clockevents */ + setup_irq(IRQ_MTU0, &nmdk_timer_irq); + nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); + nmdk_clkevt.cpumask = cpumask_of(0); + clockevents_register_device(&nmdk_clkevt); +} |