diff options
Diffstat (limited to 'arch/arm/plat-omap/include/mach')
27 files changed, 806 insertions, 412 deletions
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 073a2c5569f0..f9f65e1ba3f1 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -22,7 +22,8 @@ struct clkops { void (*disable)(struct clk *); }; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) struct clksel_rate { u32 val; @@ -51,7 +52,7 @@ struct dpll_data { u8 max_divider; u32 max_tolerance; u16 max_multiplier; -# if defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) u8 modes; void __iomem *autoidle_reg; void __iomem *idlest_reg; @@ -83,7 +84,8 @@ struct clk { void (*init)(struct clk *); __u8 enable_bit; __s8 usecount; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) u8 fixed_div; void __iomem *clksel_reg; u32 clksel_mask; @@ -119,7 +121,7 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_init_one(struct clk *clk); +extern void clk_preinit(struct clk *clk); extern int clk_register(struct clk *clk); extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h index 0ecf36deb17b..fdeab421b4dc 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/mach/common.h @@ -33,8 +33,6 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; -extern void omap_serial_init(void); -extern void omap_serial_enable_clocks(int enable); #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) extern int omap_register_i2c_bus(int bus_id, u32 clkrate, struct i2c_board_info const *info, @@ -62,6 +60,7 @@ struct omap_globals { void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +void omap2_set_globals_443x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ void omap2_set_globals_tap(struct omap_globals *); diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index 269147f3836f..8140dbccb7bc 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -1,9 +1,9 @@ /* * arch/arm/plat-omap/include/mach/control.h * - * OMAP2/3 System Control Module definitions + * OMAP2/3/4 System Control Module definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley @@ -144,6 +144,10 @@ #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) +/* 34xx D2D idle-related pins, handled by PM core */ +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -189,8 +193,18 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_IVA2_BOOTMOD bits */ +#define OMAP3_IVA2_BOOTMOD_SHIFT 0 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) + +/* CONTROL_PADCONF_X bits */ +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) + #ifndef __ASSEMBLY__ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index 98b144252364..fc60c4ebcc28 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h @@ -5,8 +5,12 @@ * * Copyright (C) 2004, 2008 Nokia Corporation * + * Copyright (C) 2009 Texas Instruments. + * * Written by Tony Lindgren <tony.lindgren@nokia.com> * + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343) #define cpu_is_omap243x() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap343x() 0 +#define cpu_is_omap44xx() 0 +#define cpu_is_omap443x() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) @@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430) # define cpu_is_omap3430() is_omap3430() #endif +# if defined(CONFIG_ARCH_OMAP4) +# undef cpu_is_omap44xx +# undef cpu_is_omap443x +# define cpu_is_omap44xx() 1 +# define cpu_is_omap443x() 1 +# endif + /* Macros to detect if we have OMAP1 or OMAP2 */ #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ cpu_is_omap16xx()) -#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ + cpu_is_omap44xx()) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 @@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP3430_REV_ES3_0 0x34303034 #define OMAP3430_REV_ES3_1 0x34304034 +#define OMAP443X_CLASS 0x44300034 + /* * omap_chip bits * diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S index 1b11f5c6a2d9..ac24050e3416 100644 --- a/arch/arm/plat-omap/include/mach/debug-macro.S +++ b/arch/arm/plat-omap/include/mach/debug-macro.S @@ -36,7 +36,7 @@ add \rx, \rx, #0x00004000 @ UART 3 #endif -#elif CONFIG_ARCH_OMAP3 +#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) moveq \rx, #0x48000000 @ physical base address movne \rx, #0xd8000000 @ virtual base orr \rx, \rx, #0x0006a000 diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h index 54fe9665b182..8c1eae88737e 100644 --- a/arch/arm/plat-omap/include/mach/dma.h +++ b/arch/arm/plat-omap/include/mach/dma.h @@ -48,6 +48,7 @@ /* Hardware registers for omap2 and omap3 */ #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) #define OMAP_DMA4_REVISION 0x00 #define OMAP_DMA4_GCR 0x78 @@ -144,6 +145,7 @@ #define OMAP_DMA4_CSSA_U(n) 0 #define OMAP_DMA4_CDSA_L(n) 0 #define OMAP_DMA4_CDSA_U(n) 0 +#define OMAP1_DMA_COLOR(n) 0 /*----------------------------------------------------------------------------*/ @@ -531,7 +533,7 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi); /* Chaining APIs */ #ifndef CONFIG_ARCH_OMAP1 extern int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int chain_id, u16 ch_status, + void (*callback) (int lch, u16 ch_status, void *data), int *chain_id, int no_of_chans, int chain_mode, diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S index 2276f89671d8..56426ed45ef4 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/plat-omap/include/mach/entry-macro.S @@ -3,6 +3,9 @@ * * Low-level IRQ helper macros for OMAP-based platforms * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. @@ -10,6 +13,7 @@ #include <mach/hardware.h> #include <mach/io.h> #include <mach/irqs.h> +#include <asm/hardware/gic.h> #if defined(CONFIG_ARCH_OMAP1) @@ -56,15 +60,21 @@ .endm #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) -#if defined(CONFIG_ARCH_OMAP24XX) #include <mach/omap24xx.h> -#endif -#if defined(CONFIG_ARCH_OMAP34XX) #include <mach/omap34xx.h> -#endif +/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ +#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) +#elif defined(CONFIG_ARCH_OMAP34XX) +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) +#endif +#if defined(CONFIG_ARCH_OMAP4) +#include <mach/omap44xx.h> +#endif #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ @@ -77,6 +87,7 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm +#ifndef CONFIG_ARCH_OMAP4 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =OMAP2_VA_IC_BASE ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ @@ -92,6 +103,68 @@ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ .endm +#else + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an + * interrupt if it's between 30 and 1020. The test_for_ipi + * routine below will pick up on IPIs. + * A simple read from the controller will tell us the number + * of the highest priority enabled interrupt. + * We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =OMAP44XX_VA_GIC_CPU_BASE + ldr \irqstat, [\base, #GIC_CPU_INTACK] + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt + * on the controller, since this requires the original irqstat + * value which we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + it cc + strcc \irqstat, [\base, #GIC_CPU_EOI] + it cs + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + itt eq + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm +#endif .macro irq_prio_table .endm diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h new file mode 100644 index 000000000000..b64fbee4d567 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h @@ -0,0 +1,42 @@ +/* + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h + * + * Copyright (C) 2009 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__ + +#define GPMC_TIMINGS_SMC91C96 (1 << 4) +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */ +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */ +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */ + +struct omap_smc91x_platform_data { + int cs; + int gpio_irq; + int gpio_pwrdwn; + int gpio_reset; + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */ + u32 flags; + int (*retime)(void); +}; + +#if defined(CONFIG_SMC91X) || \ + defined(CONFIG_SMC91X_MODULE) + +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d); + +#else + +#define board_smc91x_data NULL + +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d) +{ +} + +#endif +#endif diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 3dc423ed3e80..26c1fbff08aa 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h @@ -285,5 +285,6 @@ #include "omap16xx.h" #include "omap24xx.h" #include "omap34xx.h" +#include "omap44xx.h" #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h index 577f492f2d3c..886248d32b49 100644 --- a/arch/arm/plat-omap/include/mach/hwa742.h +++ b/arch/arm/plat-omap/include/mach/hwa742.h @@ -2,10 +2,6 @@ #define _HWA742_H struct hwa742_platform_data { - void (*power_up)(struct device *dev); - void (*power_down)(struct device *dev); - unsigned long (*get_clock_rate)(struct device *dev); - unsigned te_connected:1; }; diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index 0610d7e2b3d7..3b2814720569 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h @@ -6,6 +6,9 @@ * Copied from arch/arm/mach-sa1100/include/mach/io.h * Copyright (C) 1997-1999 Russell King * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -157,6 +160,40 @@ #define DSP_MMU_34XX_VIRT 0xe2000000 #define DSP_MMU_34XX_SIZE SZ_4K + +#elif defined(CONFIG_ARCH_OMAP4) +/* We map both L3 and L4 on OMAP4 */ +#define L3_44XX_PHYS L3_44XX_BASE +#define L3_44XX_VIRT 0xd4000000 +#define L3_44XX_SIZE SZ_1M + +#define L4_44XX_PHYS L4_44XX_BASE +#define L4_44XX_VIRT 0xda000000 +#define L4_44XX_SIZE SZ_4M + + +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE +#define L4_WK_44XX_VIRT 0xda300000 +#define L4_WK_44XX_SIZE SZ_1M + +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE +#define L4_PER_44XX_VIRT 0xd8000000 +#define L4_PER_44XX_SIZE SZ_4M + +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE +#define L4_EMU_44XX_VIRT 0xe4000000 +#define L4_EMU_44XX_SIZE SZ_64M + +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE +#define OMAP44XX_GPMC_VIRT 0xe0000000 +#define OMAP44XX_GPMC_SIZE SZ_1M + + +#define IO_OFFSET 0x90000000 +#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ + #endif #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h new file mode 100644 index 000000000000..769b00b4c34a --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu.h @@ -0,0 +1,168 @@ +/* + * omap iommu: main structures + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU_H +#define __MACH_IOMMU_H + +struct iotlb_entry { + u32 da; + u32 pa; + u32 pgsz, prsvd, valid; + union { + u16 ap; + struct { + u32 endian, elsz, mixed; + }; + }; +}; + +struct iommu { + const char *name; + struct module *owner; + struct clk *clk; + void __iomem *regbase; + struct device *dev; + + unsigned int refcount; + struct mutex iommu_lock; /* global for this whole object */ + + /* + * We don't change iopgd for a situation like pgd for a task, + * but share it globally for each iommu. + */ + u32 *iopgd; + spinlock_t page_table_lock; /* protect iopgd */ + + int nr_tlb_entries; + + struct list_head mmap; + struct mutex mmap_lock; /* protect mmap */ + + int (*isr)(struct iommu *obj); + + void *ctx; /* iommu context: registres saved area */ +}; + +struct cr_regs { + union { + struct { + u16 cam_l; + u16 cam_h; + }; + u32 cam; + }; + union { + struct { + u16 ram_l; + u16 ram_h; + }; + u32 ram; + }; +}; + +struct iotlb_lock { + short base; + short vict; +}; + +/* architecture specific functions */ +struct iommu_functions { + unsigned long version; + + int (*enable)(struct iommu *obj); + void (*disable)(struct iommu *obj); + u32 (*fault_isr)(struct iommu *obj, u32 *ra); + + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); + + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); + int (*cr_valid)(struct cr_regs *cr); + u32 (*cr_to_virt)(struct cr_regs *cr); + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); + + u32 (*get_pte_attr)(struct iotlb_entry *e); + + void (*save_ctx)(struct iommu *obj); + void (*restore_ctx)(struct iommu *obj); + ssize_t (*dump_ctx)(struct iommu *obj, char *buf); +}; + +struct iommu_platform_data { + const char *name; + const char *clk_name; + const int nr_tlb_entries; +}; + +#if defined(CONFIG_ARCH_OMAP1) +#error "iommu for this processor not implemented yet" +#else +#include <mach/iommu2.h> +#endif + +/* + * utilities for super page(16MB, 1MB, 64KB and 4KB) + */ + +#define iopgsz_max(bytes) \ + (((bytes) >= SZ_16M) ? SZ_16M : \ + ((bytes) >= SZ_1M) ? SZ_1M : \ + ((bytes) >= SZ_64K) ? SZ_64K : \ + ((bytes) >= SZ_4K) ? SZ_4K : 0) + +#define bytes_to_iopgsz(bytes) \ + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) + +#define iopgsz_to_bytes(iopgsz) \ + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) + +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) + +/* + * global functions + */ +extern u32 iommu_arch_version(void); + +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); +extern u32 iotlb_cr_to_virt(struct cr_regs *cr); + +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void flush_iotlb_page(struct iommu *obj, u32 da); +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); +extern void flush_iotlb_all(struct iommu *obj); + +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); + +extern struct iommu *iommu_get(const char *name); +extern void iommu_put(struct iommu *obj); + +extern void iommu_save_ctx(struct iommu *obj); +extern void iommu_restore_ctx(struct iommu *obj); + +extern int install_iommu_arch(const struct iommu_functions *ops); +extern void uninstall_iommu_arch(const struct iommu_functions *ops); + +extern int foreach_iommu_device(void *data, + int (*fn)(struct device *, void *)); + +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf); +extern size_t dump_tlb_entries(struct iommu *obj, char *buf); + +#endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h new file mode 100644 index 000000000000..10ad05f410e9 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu2.h @@ -0,0 +1,96 @@ +/* + * omap iommu: omap2 architecture specific definitions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU2_H +#define __MACH_IOMMU2_H + +#include <linux/io.h> + +/* + * MMU Register offsets + */ +#define MMU_REVISION 0x00 +#define MMU_SYSCONFIG 0x10 +#define MMU_SYSSTATUS 0x14 +#define MMU_IRQSTATUS 0x18 +#define MMU_IRQENABLE 0x1c +#define MMU_WALKING_ST 0x40 +#define MMU_CNTL 0x44 +#define MMU_FAULT_AD 0x48 +#define MMU_TTB 0x4c +#define MMU_LOCK 0x50 +#define MMU_LD_TLB 0x54 +#define MMU_CAM 0x58 +#define MMU_RAM 0x5c +#define MMU_GFLUSH 0x60 +#define MMU_FLUSH_ENTRY 0x64 +#define MMU_READ_CAM 0x68 +#define MMU_READ_RAM 0x6c +#define MMU_EMU_FAULT_AD 0x70 + +#define MMU_REG_SIZE 256 + +/* + * MMU Register bit definitions + */ +#define MMU_LOCK_BASE_SHIFT 10 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) +#define MMU_LOCK_BASE(x) \ + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) + +#define MMU_LOCK_VICT_SHIFT 4 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) +#define MMU_LOCK_VICT(x) \ + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) + +#define MMU_CAM_VATAG_SHIFT 12 +#define MMU_CAM_VATAG_MASK \ + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) +#define MMU_CAM_P (1 << 3) +#define MMU_CAM_V (1 << 2) +#define MMU_CAM_PGSZ_MASK 3 +#define MMU_CAM_PGSZ_1M (0 << 0) +#define MMU_CAM_PGSZ_64K (1 << 0) +#define MMU_CAM_PGSZ_4K (2 << 0) +#define MMU_CAM_PGSZ_16M (3 << 0) + +#define MMU_RAM_PADDR_SHIFT 12 +#define MMU_RAM_PADDR_MASK \ + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) +#define MMU_RAM_ENDIAN_SHIFT 9 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ELSZ_SHIFT 7 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_MIXED_SHIFT 6 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK + +/* + * register accessors + */ +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) +{ + return __raw_readl(obj->regbase + offs); +} + +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) +{ + __raw_writel(val, obj->regbase + offs); +} + +#endif /* __MACH_IOMMU2_H */ diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h new file mode 100644 index 000000000000..bdc7ce5d7a4a --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iovmm.h @@ -0,0 +1,94 @@ +/* + * omap iommu: simple virtual address space management + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOMMU_MMAP_H +#define __IOMMU_MMAP_H + +struct iovm_struct { + struct iommu *iommu; /* iommu object which this belongs to */ + u32 da_start; /* area definition */ + u32 da_end; + u32 flags; /* IOVMF_: see below */ + struct list_head list; /* linked in ascending order */ + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */ + void *va; /* mpu side mapped address */ +}; + +/* + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) + * + * lower 16 bit is used for h/w and upper 16 bit is for s/w. + */ +#define IOVMF_SW_SHIFT 16 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT) +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1) +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL + +/* + * iovma: h/w flags derived from cam and ram attribute + */ +#define IOVMF_CAM_MASK (~((1 << 10) - 1)) +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK) + +#define IOVMF_PGSZ_MASK (3 << 0) +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M + +#define IOVMF_ENDIAN_MASK (1 << 9) +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE + +#define IOVMF_ELSZ_MASK (3 << 7) +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE + +#define IOVMF_MIXED_MASK (1 << 6) +#define IOVMF_MIXED MMU_RAM_MIXED + +/* + * iovma: s/w flags, used for mapping and umapping internally. + */ +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT) + +/* "superpages" is supported just with physically linear pages */ +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) + +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) + + +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); +extern u32 iommu_vmap(struct iommu *obj, u32 da, + const struct sg_table *sgt, u32 flags); +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_vfree(struct iommu *obj, const u32 da); +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, + u32 flags); +extern void iommu_kunmap(struct iommu *obj, u32 da); +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_kfree(struct iommu *obj, u32 da); + +extern void *da_to_va(struct iommu *obj, u32 da); + +#endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index 7f57ee66f364..fb7cb7723990 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h @@ -4,6 +4,9 @@ * Copyright (C) Greg Lonnon 2001 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -422,6 +425,94 @@ #define INT_34XX_BENCH_MPU_EMUL 3 + +#define IRQ_GIC_START 32 +#define INT_44XX_LOCALTIMER_IRQ 29 +#define INT_44XX_LOCALWDT_IRQ 30 + +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) + +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) + +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) + + /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ #define OMAP_MAX_GPIO_LINES 192 @@ -467,6 +558,7 @@ #ifndef __ASSEMBLY__ extern void omap_init_irq(void); +extern int omap_irq_pending(void); #endif #include <mach/hardware.h> diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h index 232923aaf61d..45ea3ae3c995 100644 --- a/arch/arm/plat-omap/include/mach/keypad.h +++ b/arch/arm/plat-omap/include/mach/keypad.h @@ -33,7 +33,11 @@ struct omap_kp_platform_data { #define GROUP_3 (3 << 16) #define GROUP_MASK GROUP_3 +#define KEY_PERSISTENT 0x00800000 +#define KEYNUM_MASK 0x00EFFFFF #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \ + KEY_PERSISTENT) #endif diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h index 99ed564d9277..9ad41dc484c1 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/mach/memory.h @@ -38,7 +38,8 @@ */ #if defined(CONFIG_ARCH_OMAP1) #define PHYS_OFFSET UL(0x10000000) -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) #define PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h index 24335d4932f5..696edfc145a6 100644 --- a/arch/arm/plat-omap/include/mach/omap24xx.h +++ b/arch/arm/plat-omap/include/mach/omap24xx.h @@ -85,23 +85,5 @@ #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) -#if defined(CONFIG_ARCH_OMAP2420) - -#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE -#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE -#define OMAP2_CM_BASE OMAP2420_CM_BASE -#define OMAP2_PRM_BASE OMAP2420_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) - -#elif defined(CONFIG_ARCH_OMAP2430) - -#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE -#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE -#define OMAP2_CM_BASE OMAP2430_CM_BASE -#define OMAP2_PRM_BASE OMAP2430_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) - -#endif - #endif /* __ASM_ARCH_OMAP24XX_H */ diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h index ab640151d3ec..f8d186a73712 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/mach/omap34xx.h @@ -31,13 +31,9 @@ #define L4_34XX_BASE 0x48000000 #define L4_WK_34XX_BASE 0x48300000 -#define L4_WK_OMAP_BASE L4_WK_34XX_BASE #define L4_PER_34XX_BASE 0x49000000 -#define L4_PER_OMAP_BASE L4_PER_34XX_BASE #define L4_EMU_34XX_BASE 0x54000000 -#define L4_EMU_BASE L4_EMU_34XX_BASE #define L3_34XX_BASE 0x68000000 -#define L3_OMAP_BASE L3_34XX_BASE #define OMAP3430_32KSYNCT_BASE 0x48320000 #define OMAP3430_CM_BASE 0x48004800 @@ -83,15 +79,6 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) -#if defined(CONFIG_ARCH_OMAP3430) - -#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE -#define OMAP2_CM_BASE OMAP3430_CM_BASE -#define OMAP2_PRM_BASE OMAP3430_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) - -#endif - #define OMAP34XX_DSP_BASE 0x58000000 #define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) #define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h new file mode 100644 index 000000000000..15dec7f1c7c0 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap44xx.h @@ -0,0 +1,46 @@ +/*: + * Address mappings and base address for OMAP4 interconnects + * and peripherals. + * + * Copyright (C) 2009 Texas Instruments + * + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_OMAP44XX_H +#define __ASM_ARCH_OMAP44XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_44XX_BASE 0x4a000000 +#define L4_WK_44XX_BASE 0x4a300000 +#define L4_PER_44XX_BASE 0x48000000 +#define L4_EMU_44XX_BASE 0x54000000 +#define L3_44XX_BASE 0x44000000 +#define OMAP4430_32KSYNCT_BASE 0x4a304000 +#define OMAP4430_CM_BASE 0x4a004000 +#define OMAP4430_PRM_BASE 0x48306000 +#define OMAP44XX_GPMC_BASE 0x50000000 +#define OMAP443X_SCM_BASE 0x4a002000 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE +#define OMAP44XX_IC_BASE 0x48200000 +#define OMAP44XX_IVA_INTC_BASE 0x40000000 +#define IRQ_SIR_IRQ 0x0040 +#define OMAP44XX_GIC_DIST_BASE 0x48241000 +#define OMAP44XX_GIC_CPU_BASE 0x48240100 +#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) +#define OMAP44XX_SCU_BASE 0x48240000 +#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE) +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 +#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) +#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 +#define OMAP44XX_WKUPGEN_BASE 0x48281000 +#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) + +#endif /* __ASM_ARCH_OMAP44XX_H */ + diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h index 4649d302c263..72f433d7d827 100644 --- a/arch/arm/plat-omap/include/mach/onenand.h +++ b/arch/arm/plat-omap/include/mach/onenand.h @@ -9,8 +9,12 @@ * published by the Free Software Foundation. */ +#include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#define ONENAND_SYNC_READ (1 << 0) +#define ONENAND_SYNC_READWRITE (1 << 1) + struct omap_onenand_platform_data { int cs; int gpio_irq; @@ -18,8 +22,22 @@ struct omap_onenand_platform_data { int nr_parts; int (*onenand_setup)(void __iomem *, int freq); int dma_channel; + u8 flags; }; -int omap2_onenand_rephase(void); - #define ONENAND_MAX_PARTITIONS 8 + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); + +#else + +#define board_onenand_data NULL + +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) +{ +} + +#endif diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h deleted file mode 100644 index ce6ee7927537..000000000000 --- a/arch/arm/plat-omap/include/mach/pm.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/pm.h - * - * Header file for OMAP Power Management Routines - * - * Author: MontaVista Software, Inc. - * support@mvista.com - * - * Copyright 2002 MontaVista Software Inc. - * - * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_PM_H -#define __ASM_ARCH_OMAP_PM_H - -/* - * ---------------------------------------------------------------------------- - * Register and offset definitions to be used in PM assembler code - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00) -#define ARM_IDLECT1_ASM_OFFSET 0x04 -#define ARM_IDLECT2_ASM_OFFSET 0x08 - -#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00) -#define EMIFS_CONFIG_ASM_OFFSET 0x0c -#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 - -/* - * ---------------------------------------------------------------------------- - * Power management bitmasks - * ---------------------------------------------------------------------------- - */ -#define IDLE_WAIT_CYCLES 0x00000fff -#define PERIPHERAL_ENABLE 0x2 - -#define SELF_REFRESH_MODE 0x0c000001 -#define IDLE_EMIFS_REQUEST 0xc -#define MODEM_32K_EN 0x1 -#define PER_EN 0x1 - -#define CPU_SUSPEND_SIZE 200 -#define ULPD_LOW_PWR_EN 0x0001 -#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 -#define ULPD_SETUP_ANALOG_CELL_3_VAL 0 -#define ULPD_POWER_CTRL_REG_VAL 0x0219 - -#define DSP_IDLE_DELAY 10 -#define DSP_IDLE 0x0040 -#define DSP_RST 0x0004 -#define DSP_ENABLE 0x0002 -#define SUFFICIENT_DSP_RESET_TIME 1000 -#define DEFAULT_MPUI_CONFIG 0x05cf -#define ENABLE_XORCLK 0x2 -#define DSP_CLOCK_ENABLE 0x2000 -#define DSP_IDLE_MODE 0x2 -#define TC_IDLE_REQUEST (0x0000000c) - -#define IRQ_LEVEL2 (1<<0) -#define IRQ_KEYBOARD (1<<1) -#define IRQ_UART2 (1<<15) - -#define PDE_BIT 0x08 -#define PWD_EN_BIT 0x04 -#define EN_PERCK_BIT 0x04 - -#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 -#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 -#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 -#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 - -/* Both big sleep and deep sleep use same values. Difference is in ULPD. */ -#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 -#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP1610_IDLECT3_VAL 0x3f -#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c -#define OMAP1610_IDLECT3 0xfffece24 -#define OMAP1610_IDLE_LOOP_REQUEST 0x0400 - -#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 -#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP730_IDLECT3_VAL 0x3f -#define OMAP730_IDLECT3 0xfffece24 -#define OMAP730_IDLE_LOOP_REQUEST 0x0C00 - -#if !defined(CONFIG_ARCH_OMAP730) && \ - !defined(CONFIG_ARCH_OMAP15XX) && \ - !defined(CONFIG_ARCH_OMAP16XX) && \ - !defined(CONFIG_ARCH_OMAP24XX) -#warning "Power management for this processor not implemented yet" -#endif - -#ifndef __ASSEMBLER__ - -#include <linux/clk.h> - -extern void prevent_idle_sleep(void); -extern void allow_idle_sleep(void); - -extern void omap_pm_idle(void); -extern void omap_pm_suspend(void); -extern void omap730_cpu_suspend(unsigned short, unsigned short); -extern void omap1510_cpu_suspend(unsigned short, unsigned short); -extern void omap1610_cpu_suspend(unsigned short, unsigned short); -extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, - void __iomem *sdrc_power); -extern void omap730_idle_loop_suspend(void); -extern void omap1510_idle_loop_suspend(void); -extern void omap1610_idle_loop_suspend(void); -extern void omap24xx_idle_loop_suspend(void); - -extern unsigned int omap730_cpu_suspend_sz; -extern unsigned int omap1510_cpu_suspend_sz; -extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap24xx_cpu_suspend_sz; -extern unsigned int omap730_idle_loop_suspend_sz; -extern unsigned int omap1510_idle_loop_suspend_sz; -extern unsigned int omap1610_idle_loop_suspend_sz; -extern unsigned int omap24xx_idle_loop_suspend_sz; - -#ifdef CONFIG_OMAP_SERIAL_WAKE -extern void omap_serial_wake_trigger(int enable); -#else -#define omap_serial_wakeup_init() {} -#define omap_serial_wake_trigger(x) {} -#endif /* CONFIG_OMAP_SERIAL_WAKE */ - -#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) -#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) -#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] - -#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) -#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) -#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] - -#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) -#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) -#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] - -#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) -#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] - -#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) -#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] - -#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) -#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] - -#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x -#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] -#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] - -/* - * List of global OMAP registers to preserve. - * More ones like CP and general purpose register values are preserved - * with the stack pointer in sleep.S. - */ - -enum arm_save_state { - ARM_SLEEP_SAVE_START = 0, - /* - * MPU control registers 32 bits - */ - ARM_SLEEP_SAVE_ARM_CKCTL, - ARM_SLEEP_SAVE_ARM_IDLECT1, - ARM_SLEEP_SAVE_ARM_IDLECT2, - ARM_SLEEP_SAVE_ARM_IDLECT3, - ARM_SLEEP_SAVE_ARM_EWUPCT, - ARM_SLEEP_SAVE_ARM_RSTCT1, - ARM_SLEEP_SAVE_ARM_RSTCT2, - ARM_SLEEP_SAVE_ARM_SYSST, - ARM_SLEEP_SAVE_SIZE -}; - -enum dsp_save_state { - DSP_SLEEP_SAVE_START = 0, - /* - * DSP registers 16 bits - */ - DSP_SLEEP_SAVE_DSP_IDLECT2, - DSP_SLEEP_SAVE_SIZE -}; - -enum ulpd_save_state { - ULPD_SLEEP_SAVE_START = 0, - /* - * ULPD registers 16 bits - */ - ULPD_SLEEP_SAVE_ULPD_IT_STATUS, - ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, - ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, - ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, - ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, - ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, - ULPD_SLEEP_SAVE_SIZE -}; - -enum mpui1510_save_state { - MPUI1510_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI1510_SLEEP_SAVE_MPUI_CTRL, - MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, - MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, -#if defined(CONFIG_ARCH_OMAP15XX) - MPUI1510_SLEEP_SAVE_SIZE -#else - MPUI1510_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum mpui730_save_state { - MPUI730_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI730_SLEEP_SAVE_MPUI_CTRL, - MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI730_SLEEP_SAVE_EMIFS_CONFIG, - MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, -#if defined(CONFIG_ARCH_OMAP730) - MPUI730_SLEEP_SAVE_SIZE -#else - MPUI730_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum mpui1610_save_state { - MPUI1610_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI1610_SLEEP_SAVE_MPUI_CTRL, - MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, - MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, -#if defined(CONFIG_ARCH_OMAP16XX) - MPUI1610_SLEEP_SAVE_SIZE -#else - MPUI1610_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum omap24xx_save_state { - OMAP24XX_SLEEP_SAVE_START = 0, - OMAP24XX_SLEEP_SAVE_INTC_MIR0, - OMAP24XX_SLEEP_SAVE_INTC_MIR1, - OMAP24XX_SLEEP_SAVE_INTC_MIR2, - - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM, - - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM, - - OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM, - - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM, - - OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, - OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, - OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO3_OE, - OMAP24XX_SLEEP_SAVE_GPIO4_OE, - OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, - OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, - OMAP24XX_SLEEP_SAVE_SIZE -}; - -#endif /* ASSEMBLER */ -#endif /* __ASM_ARCH_OMAP_PM_H */ diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h index 8a676a04be48..13abd02d1527 100644 --- a/arch/arm/plat-omap/include/mach/serial.h +++ b/arch/arm/plat-omap/include/mach/serial.h @@ -1,5 +1,8 @@ /* - * arch/arm/plat-omap/include/mach/serial.h + * arch/arm/plat-omap/include/mach/serial.h + * + * Copyright (C) 2009 Texas Instruments + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,19 +18,28 @@ #define OMAP_UART1_BASE 0xfffb0000 #define OMAP_UART2_BASE 0xfffb0800 #define OMAP_UART3_BASE 0xfffb9800 +#define OMAP_MAX_NR_PORTS 3 #elif defined(CONFIG_ARCH_OMAP2) /* OMAP2 serial ports */ #define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART3_BASE 0x4806e000 +#define OMAP_MAX_NR_PORTS 3 #elif defined(CONFIG_ARCH_OMAP3) /* OMAP3 serial ports */ #define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART3_BASE 0x49020000 +#define OMAP_MAX_NR_PORTS 3 +#elif defined(CONFIG_ARCH_OMAP4) +/* OMAP4 serial ports */ +#define OMAP_UART1_BASE 0x4806a000 +#define OMAP_UART2_BASE 0x4806c000 +#define OMAP_UART3_BASE 0x48020000 +#define OMAP_UART4_BASE 0x4806e000 +#define OMAP_MAX_NR_PORTS 4 #endif -#define OMAP_MAX_NR_PORTS 3 #define OMAP1510_BASE_BAUD (12000000/16) #define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16) @@ -40,4 +52,13 @@ __ret; \ }) +#ifndef __ASSEMBLER__ +extern void omap_serial_init(void); +extern int omap_uart_can_sleep(void); +extern void omap_uart_check_wakeup(void); +extern void omap_uart_prepare_suspend(void); +extern void omap_uart_prepare_idle(int num); +extern void omap_uart_resume_idle(int num); +#endif + #endif diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h new file mode 100644 index 000000000000..dcaa8fde7063 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/smp.h @@ -0,0 +1,51 @@ +/* + * OMAP4 machine specific smp.h + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Interface functions needed for the SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_SMP_H +#define OMAP_ARCH_SMP_H + +#include <asm/hardware/gic.h> + +/* + * set_event() is used to wake up secondary core from wfe using sev. ROM + * code puts the second core into wfe(standby). + * + */ +#define set_event() __asm__ __volatile__ ("sev" : : : "memory") + +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); + +/* + * We use Soft IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +/* + * Read MPIDR: Multiprocessor affinity register + */ +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +#endif diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index ab35d622dcf5..dca7c16ae903 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h index 69f0ceed500b..f337e1761e2c 100644 --- a/arch/arm/plat-omap/include/mach/usb.h +++ b/arch/arm/plat-omap/include/mach/usb.h @@ -27,13 +27,7 @@ #define UDC_BASE OMAP2_UDC_BASE #define OMAP_OHCI_BASE OMAP2_OHCI_BASE -#ifdef CONFIG_USB_MUSB_SOC extern void usb_musb_init(void); -#else -static inline void usb_musb_init(void) -{ -} -#endif #endif diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h index dc104cd96197..b97dfafeebda 100644 --- a/arch/arm/plat-omap/include/mach/vmalloc.h +++ b/arch/arm/plat-omap/include/mach/vmalloc.h @@ -17,5 +17,5 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) |