diff options
Diffstat (limited to 'arch/arm64/boot/dts/allwinner')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index c455b24dd079..f9eede0a8bd3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -239,7 +239,7 @@ }; /* - * The A64 chip cannot work without this regulator off, although + * The A64 chip cannot work with this regulator off, although * it seems to be only driving the AR100 core. * Maybe we don't still know well about CPUs domain. */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1583afd034ae..cca554c8353f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -142,6 +142,15 @@ clock-output-names = "ext-osc32k"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -191,6 +200,7 @@ timer { compatible = "arm,armv8-timer"; + allwinner,erratum-unknown1; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 |