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-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi228
1 files changed, 200 insertions, 28 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index a88a15f2352b..32bd140ac9fd 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
@@ -165,6 +166,9 @@
min-residency-us = <2000>;
local-timer-stop;
};
+ };
+
+ domain-idle-states {
CLUSTER_RET: cluster-retention {
compatible = "domain-idle-state";
@@ -188,31 +192,31 @@
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: cpu-pd0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
- CPU_PD1: cpu-pd1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
- CPU_PD2: cpu-pd2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
- CPU_PD3: cpu-pd3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&CPU_SLEEP_0>;
};
- CLUSTER_PD: cluster-pd {
+ CLUSTER_PD: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
};
@@ -261,7 +265,7 @@
thermal-sensors = <&tsens 4>;
trips {
- cpu2_3_alert0: trip-point@0 {
+ cpu2_3_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
@@ -291,7 +295,7 @@
thermal-sensors = <&tsens 2>;
trips {
- gpu_alert0: trip-point@0 {
+ gpu_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
@@ -311,7 +315,7 @@
thermal-sensors = <&tsens 1>;
trips {
- cam_alert0: trip-point@0 {
+ cam_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "hot";
@@ -326,7 +330,7 @@
thermal-sensors = <&tsens 0>;
trips {
- modem_alert0: trip-point@0 {
+ modem_alert0: trip-point0 {
temperature = <85000>;
hysteresis = <2000>;
type = "hot";
@@ -336,7 +340,7 @@
};
- cpu_opp_table: cpu_opp_table {
+ cpu_opp_table: cpu-opp-table {
compatible = "operating-points-v2";
opp-shared;
@@ -354,17 +358,6 @@
};
};
- gpu_opp_table: opp_table {
- compatible = "operating-points-v2";
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- };
- opp-19200000 {
- opp-hz = /bits/ 64 <19200000>;
- };
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -374,13 +367,13 @@
};
clocks {
- xo_board: xo_board {
+ xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk: sleep_clk {
+ sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -608,6 +601,21 @@
status = "disabled";
};
+ blsp_i2c1: i2c@78b5000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
@@ -638,6 +646,21 @@
status = "disabled";
};
+ blsp_i2c5: i2c@78b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b9000 0x500>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>;
@@ -955,6 +978,17 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ };
+ };
};
mdss: mdss@1a00000 {
@@ -1224,6 +1258,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
in-ports {
port {
tpiu_in: endpoint {
@@ -1240,6 +1276,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1279,6 +1317,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1313,6 +1353,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
in-ports {
port {
etf_in: endpoint {
@@ -1337,6 +1379,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
in-ports {
port {
etr_in: endpoint {
@@ -1353,6 +1397,8 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ status = "disabled";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1398,6 +1444,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
+ status = "disabled";
};
debug@852000 {
@@ -1406,6 +1453,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
+ status = "disabled";
};
debug@854000 {
@@ -1414,6 +1462,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
+ status = "disabled";
};
debug@856000 {
@@ -1422,9 +1471,10 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
+ status = "disabled";
};
- etm@85c000 {
+ etm0: etm@85c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85c000 0x1000>;
@@ -1434,6 +1484,8 @@
cpu = <&CPU0>;
+ status = "disabled";
+
out-ports {
port {
etm0_out: endpoint {
@@ -1443,7 +1495,7 @@
};
};
- etm@85d000 {
+ etm1: etm@85d000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85d000 0x1000>;
@@ -1453,6 +1505,8 @@
cpu = <&CPU1>;
+ status = "disabled";
+
out-ports {
port {
etm1_out: endpoint {
@@ -1462,7 +1516,7 @@
};
};
- etm@85e000 {
+ etm2: etm@85e000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85e000 0x1000>;
@@ -1472,6 +1526,8 @@
cpu = <&CPU2>;
+ status = "disabled";
+
out-ports {
port {
etm2_out: endpoint {
@@ -1481,7 +1537,7 @@
};
};
- etm@85f000 {
+ etm3: etm@85f000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85f000 0x1000>;
@@ -1491,6 +1547,8 @@
cpu = <&CPU3>;
+ status = "disabled";
+
out-ports {
port {
etm3_out: endpoint {
@@ -1500,6 +1558,93 @@
};
};
+ /* System CTIs */
+ /* CTI 0 - TMC connections */
+ cti@810000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x810000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ status = "disabled";
+ };
+
+ /* CTI 1 - TPIU connections */
+ cti@811000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x811000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ status = "disabled";
+ };
+
+ /* CTIs 2-11 - no information - not instantiated */
+
+ /* Core CTIs; CTIs 12-15 */
+ /* CTI - CPU-0 */
+ cti@858000 {
+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+ "arm,primecell";
+ reg = <0x858000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU0>;
+ arm,cs-dev-assoc = <&etm0>;
+
+ status = "disabled";
+ };
+
+ /* CTI - CPU-1 */
+ cti@859000 {
+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+ "arm,primecell";
+ reg = <0x859000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU1>;
+ arm,cs-dev-assoc = <&etm1>;
+
+ status = "disabled";
+ };
+
+ /* CTI - CPU-2 */
+ cti@85a000 {
+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+ "arm,primecell";
+ reg = <0x85a000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU2>;
+ arm,cs-dev-assoc = <&etm2>;
+
+ status = "disabled";
+ };
+
+ /* CTI - CPU-3 */
+ cti@85b000 {
+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+ "arm,primecell";
+ reg = <0x85b000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU3>;
+ arm,cs-dev-assoc = <&etm3>;
+
+ status = "disabled";
+ };
+
+
venus: video-codec@1d00000 {
compatible = "qcom,msm8916-venus";
reg = <0x01d00000 0xff000>;
@@ -1601,6 +1746,33 @@
#size-cells = <0>;
};
};
+
+ cci: cci@1b0c000 {
+ compatible = "qcom,msm8916-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1b0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb", "cci_ahb",
+ "cci", "camss_ahb";
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>;
+ assigned-clock-rates = <80000000>, <19200000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cci0_default>;
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
smd {
@@ -1611,7 +1783,7 @@
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
- rpm_requests {
+ rpm-requests {
compatible = "qcom,rpm-msm8916";
qcom,smd-channels = "rpm_requests";
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-23 11:46:50 +0100