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-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi52
1 files changed, 29 insertions, 23 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ca70ff73f171..799c75fa7981 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -42,7 +42,7 @@
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- gic_its: gic-its@18200000 {
+ gic_its: gic-its@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
@@ -67,7 +67,7 @@
reg = <0x0 0x900000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 153>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
@@ -82,7 +82,7 @@
reg = <0x0 0x910000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 154>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
@@ -100,7 +100,7 @@
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 146>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
@@ -110,7 +110,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 147>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
@@ -120,7 +120,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 148>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
};
main_pmx0: pinmux@11c000 {
@@ -147,7 +147,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
- power-domains = <&k3_pds 110>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
@@ -158,7 +158,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
- power-domains = <&k3_pds 111>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
@@ -169,7 +169,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
- power-domains = <&k3_pds 112>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
@@ -180,14 +180,14 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
- power-domains = <&k3_pds 113>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
ecap0: pwm@3100000 {
compatible = "ti,am654-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x0 0x03100000 0x0 0x60>;
- power-domains = <&k3_pds 39>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
};
@@ -197,7 +197,7 @@
reg = <0x0 0x2100000 0x0 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 137 1>;
- power-domains = <&k3_pds 137>;
+ power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -207,7 +207,7 @@
reg = <0x0 0x2110000 0x0 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 138 1>;
- power-domains = <&k3_pds 138>;
+ power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
@@ -219,7 +219,7 @@
reg = <0x0 0x2120000 0x0 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 139 1>;
- power-domains = <&k3_pds 139>;
+ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -229,7 +229,7 @@
reg = <0x0 0x2130000 0x0 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 140 1>;
- power-domains = <&k3_pds 140>;
+ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -239,7 +239,7 @@
reg = <0x0 0x2140000 0x0 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 141 1>;
- power-domains = <&k3_pds 141>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -247,7 +247,7 @@
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@@ -306,7 +306,7 @@
ranges = <0x0 0x0 0x4000000 0x20000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 151>;
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
@@ -345,7 +345,7 @@
ranges = <0x0 0x0 0x4020000 0x20000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 152>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
@@ -413,6 +413,12 @@
ti,sci-rm-range-vint = <0x0>;
ti,sci-rm-range-global-event = <0x1>;
};
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
};
main_gpio0: main_gpio0@600000 {
@@ -451,7 +457,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
@@ -470,7 +476,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
@@ -483,7 +489,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
@@ -502,7 +508,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 12:16:03 +0100