diff options
Diffstat (limited to 'arch/arm64/boot')
292 files changed, 9614 insertions, 986 deletions
diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts index 63e375cd9eb4..bd54b5165129 100644 --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts @@ -24,7 +24,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - memory@1,e0000000 { + memory@1e0000000 { device_type = "memory"; reg = <0x1 0xe0000000 0x0 0x0>; }; diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 21149b346a60..0db7b60b49a1 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb @@ -47,3 +48,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index e6d5bc0f7a61..d1f415acd7b5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -53,7 +53,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index 0af6dcdf7515..dec9960a7440 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -41,7 +41,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index bfb806cf6d7a..fd3794678c33 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -52,7 +52,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 4f8529d5ac00..c8303a66438d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -68,7 +68,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 50ed2e9f10ed..6c65d5bc16ba 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -79,7 +79,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 87847116ab6d..6eab61a12cd8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -39,25 +39,35 @@ leds { compatible = "gpio-leds"; - led-0 { + led0: led-0 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_BLUE>; gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + retain-state-suspended; }; - led-1 { + led1: led-1 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_GREEN>; gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ + retain-state-suspended; }; - led-2 { + led2: led-2 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_RED>; gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + retain-state-suspended; }; }; + multi-led { + compatible = "leds-group-multicolor"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + leds = <&led0>, <&led1>, <&led2>; + }; + reg_ps: ps-regulator { compatible = "regulator-fixed"; regulator-name = "ps"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index 0a5607f73049..c6007df99938 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -98,7 +98,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index 1128030e4c25..b407e1dd08a7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -74,7 +74,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 57ac18738c99..ce4aa44c3353 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -107,27 +107,19 @@ gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - }; - opp-432000000 { opp-hz = /bits/ 64 <432000000>; }; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -216,21 +208,21 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_alert1: cpu_alert1 { + cpu_alert1: cpu-alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts new file mode 100644 index 000000000000..bb2cde59bd03 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Tanix TX1"; + compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + ethernet0 = &sdio_wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "hidden"; + linux,code = <BTN_0>; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + default-state = "on"; + }; + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + max-frequency = <100000000>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1120000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 4c3921ac236c..b69032c44557 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -68,7 +68,7 @@ states = <1100000 0>, <1300000 1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts index a3e040da38a0..3a7ee44708a2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -103,7 +103,7 @@ states = <1100000 0x0>, <1300000 0x1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; @@ -170,7 +170,7 @@ non-removable; status = "okay"; - rtl8189etv: sdio_wifi@1 { + rtl8189etv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index d7f8bad6bb98..b699bb900e13 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -85,7 +85,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts index 7ec5ac850a0d..ae85131aac9c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts @@ -97,7 +97,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts index 22530ace12d5..734481e998b8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -52,7 +52,7 @@ regulator-max-microvolt = <3300000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 381d58cea092..3be1e8c2fdb9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -34,7 +34,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 6fc65e8db220..6c3bfe3d09d9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -33,7 +33,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts index fb31dcb1cb6d..a3f65a45bd26 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts @@ -11,7 +11,7 @@ serial1 = &uart1; /* BT-UART */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index 92745128fcfe..13b07141c334 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -32,7 +32,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index b710f1a0f53a..66fe03910d5e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -5,13 +5,13 @@ #include "sun50i-h6-pine-h64.dts" +/delete-node/ ®_gmac_3v3; + / { model = "Pine H64 model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - /delete-node/ reg_gmac_3v3; - - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 1ffd68f43f87..3910393be1f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -22,7 +22,7 @@ stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index d11e5041bae9..8a8591c4e7dd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -68,7 +68,7 @@ status = "disabled"; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b2e85e52d1a1..f8ecd7db4868 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -194,7 +194,7 @@ }; i2c0_pins: i2c0-pins { - pins = "PI6", "PI7"; + pins = "PI5", "PI6"; function = "i2c0"; }; @@ -775,6 +775,15 @@ #reset-cells = <1>; }; + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-h616-nmi", + "allwinner,sun9i-a80-nmi"; + reg = <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h616-r-pinctrl"; reg = <0x07022000 0x400>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts index ac0a2b7ea6f3..a1d0cac4d244 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -41,7 +41,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts index b6e3c169797f..c204dd43c726 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts @@ -42,7 +42,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts new file mode 100644 index 000000000000..ee30584b6ad7 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Anbernic RG35XX 2024"; + chassis-type = "handset"; + compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys_gamepad: gpio-keys-gamepad { + compatible = "gpio-keys"; + + button-a { + label = "Action-Pad A"; + gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_EAST>; + }; + + button-b { + label = "Action-Pad B"; + gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_SOUTH>; + }; + + button-down { + label = "D-Pad Down"; + gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-l1 { + label = "Key L1"; + gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TL>; + }; + + button-l2 { + label = "Key L2"; + gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TL2>; + }; + + button-left { + label = "D-Pad left"; + gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-menu { + label = "Key Menu"; + gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_MODE>; + }; + + button-r1 { + label = "Key R1"; + gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TR>; + }; + + button-r2 { + label = "Key R2"; + gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TR2>; + }; + + button-right { + label = "D-Pad Right"; + gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-select { + label = "Key Select"; + gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_SELECT>; + }; + button-start { + label = "Key Start"; + gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_START>; + }; + + button-up { + label = "D-Pad Up"; + gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + label = "Action-Pad X"; + gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_NORTH>; + }; + + button-y { + label = "Action Pad Y"; + gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_WEST>; + }; + }; + + gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + + button-vol-up { + label = "Key Volume Up"; + gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-vol-down { + label = "Key Volume Down"; + gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + default-state = "on"; + }; + }; + + reg_vcc5v: regulator-vcc5v { /* USB-C power input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc1>; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + disable-wp; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_cldo3>; + vcc-pc-supply = <®_cldo3>; + vcc-pe-supply = <®_cldo3>; + vcc-pf-supply = <®_cldo3>; + vcc-pg-supply = <®_aldo4>; + vcc-ph-supply = <®_cldo3>; + vcc-pi-supply = <®_cldo3>; +}; + +&r_rsb { + status = "okay"; + + axp717: pmic@3a3 { + compatible = "x-powers,axp717"; + reg = <0x3a3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + + regulators { + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <940000>; + regulator-max-microvolt = <940000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* 1.8v - unused */ + }; + + reg_aldo2: aldo2 { + /* 1.8v - unused */ + }; + + reg_aldo3: aldo3 { + /* 1.8v - unused */ + }; + + reg_aldo4: aldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; + }; + + reg_bldo1: bldo1 { + /* 1.8v - unused */ + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll"; + }; + + reg_bldo3: bldo3 { + /* 2.8v - unused */ + }; + + reg_bldo4: bldo4 { + /* 1.2v - unused */ + }; + + reg_cldo1: cldo1 { + /* 3.3v - audio codec - not yet implemented */ + }; + + reg_cldo2: cldo2 { + /* 3.3v - unused */ + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_boost: boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5200000>; + regulator-name = "boost"; + }; + + reg_cpusldo: cpusldo { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ +&usbotg { + dr_mode = "peripheral"; /* USB type-C receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts new file mode 100644 index 000000000000..63036256917f --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>. + */ + +#include "sun50i-h700-anbernic-rg35xx-plus.dts" + +/ { + model = "Anbernic RG35XX H"; + compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; +}; + +&gpio_keys_gamepad { + button-thumbl { + label = "GPIO Thumb Left"; + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + label = "GPIO Thumb Right"; + gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_THUMBR>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts new file mode 100644 index 000000000000..60a8e4922103 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + */ + +#include "sun50i-h700-anbernic-rg35xx-2024.dts" + +/ { + model = "Anbernic RG35XX Plus"; + compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +/* SDIO WiFi RTL8821CS */ +&mmc1 { + vmmc-supply = <®_cldo4>; + vqmmc-supply = <®_aldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ + interrupt-names = "host-wake"; + }; +}; + +/* Bluetooth RTL8821CS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ + enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ + host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ + }; +}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 072fe20cfca0..cbbc53c47921 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -79,7 +79,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 170 4>, <0 171 4>, <0 172 4>, diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index dbf2dce8d1d6..da9de4986660 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -39,6 +39,7 @@ / { model = "Annapurna Labs Alpine v2"; compatible = "al,alpine-v2"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -89,6 +90,22 @@ clock-frequency = <1000000>; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -97,22 +114,6 @@ interrupt-parent = <&gic>; ranges; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - }; - gic: interrupt-controller@f0200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ @@ -150,7 +151,7 @@ al,msi-num-spis = <160>; }; - io-fabric { + io-fabric@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 3ea178acdddf..8b6156b5af65 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -244,7 +244,7 @@ next-level-cache = <&cluster3_l2>; }; - cluster0_l2: cache@0 { + cluster0_l2: cache-0 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -253,7 +253,7 @@ cache-unified; }; - cluster1_l2: cache@100 { + cluster1_l2: cache-100 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -262,7 +262,7 @@ cache-unified; }; - cluster2_l2: cache@200 { + cluster2_l2: cache-200 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -271,7 +271,7 @@ cache-unified; }; - cluster3_l2: cache@300 { + cluster3_l2: cache-300 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -318,7 +318,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f0000000 { + gic: interrupt-controller@f0800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; @@ -361,7 +361,7 @@ interrupt-parent = <&gic>; }; - io-fabric { + io-fabric@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi index 568bcc39ce9f..6c1b7b8fe354 100644 --- a/arch/arm64/boot/dts/amd/elba-16core.dtsi +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2023 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi index 46b6c6783f58..d12e9a7b5587 100644 --- a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2022 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts index c3f4da2f7449..20b0fa0807a1 100644 --- a/arch/arm64/boot/dts/amd/elba-asic.dts +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Device Tree file for AMD Pensando Elba Board. * diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi index cf761a05a81f..6ea2d777c8c9 100644 --- a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2023 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi index 674890cf2a34..758bce0a0b2a 100644 --- a/arch/arm64/boot/dts/amd/elba.dtsi +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2022 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 2e8069002ec1..6e05cf1a3df6 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -15,7 +15,7 @@ chosen { }; - memory { + memory@100000000 { device_type = "memory"; reg = < 0x1 0x00000000 0x0 0x80000000 >; }; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 033e10e12b18..e7644cddf06f 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -15,7 +15,7 @@ chosen { }; - memory { + memory@100000000 { device_type = "memory"; reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ }; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 65ebac3082e2..ea5721ea02f0 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -211,6 +211,13 @@ }; }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <1 12 0xff04>; @@ -236,13 +243,6 @@ #size-cells = <2>; ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - pmdpll: pmdpll@170000f0 { compatible = "apm,xgene-pcppll-v2-clock"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 988928c60f15..532401bc9c66 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -112,6 +112,13 @@ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ @@ -122,7 +129,7 @@ }; pmu { - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; + compatible = "apm,potenza-pmu"; interrupts = <1 12 0xff04>; }; @@ -137,12 +144,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; pcppll: pcppll@17000100 { compatible = "apm,xgene-pcppll-clock"; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index b897f5542c0a..98ed2b329ed6 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -773,14 +773,14 @@ }; }; - big_cluster_thermal_zone: big-cluster-thermal { + big_cluster_thermal_zone: big-cl-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 21>; status = "disabled"; }; - little_cluster_thermal_zone: little-cluster-thermal { + little_cluster_thermal_zone: little-cl-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 22>; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index 31929e2377d8..f38c5b6ef657 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -84,11 +84,11 @@ thermal-sensors = <&scmi_sensors0 3>; }; - big-cluster-thermal { + big-cl-thermal { thermal-sensors = <&scmi_sensors0 21>; }; - little-cluster-thermal { + little-cl-thermal { thermal-sensors = <&scmi_sensors0 22>; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 8db4243a4947..9115c99d0dc0 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -102,7 +102,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index e01cf4f54077..8b924812322c 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -594,6 +594,7 @@ reg-names = "nand", "nand-int-base"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "nand_ctlrdy"; + brcm,wp-not-connected; status = "disabled"; nandcs: nand@0 { diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts index 030ffa5364fb..e5b37643296b 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts @@ -34,7 +34,6 @@ }; &nand_controller { - brcm,wp-not-connected; status = "okay"; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index dec5a110f1e8..f43cfe66b6af 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -50,7 +50,7 @@ bootargs = "earlycon=uart8250,mmio32,0x66130000"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 1d314f17bbdd..c50df1d02797 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -47,7 +47,7 @@ bootargs = "earlycon=uart8250,mmio32,0x66130000"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000001 0x00000000>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 896d1f33b5b6..cfd9fd23a1c2 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -102,7 +102,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index d8516ec0dae7..857fa427e195 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -142,7 +142,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 8ad31dee11a3..cc860a80af51 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -361,24 +361,24 @@ }; pmu { - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; + compatible = "cavium,thunder-pmu"; interrupts = <1 7 4>; }; + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "refclk50mhz"; - }; - - gic0: interrupt-controller@8010,00000000 { + gic0: interrupt-controller@801000000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; @@ -397,7 +397,7 @@ }; }; - uaa0: serial@87e0,24000000 { + uaa0: serial@87e024000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x24000000 0x0 0x1000>; interrupts = <1 21 4>; @@ -405,7 +405,7 @@ clock-names = "apb_pclk"; }; - uaa1: serial@87e0,25000000 { + uaa1: serial@87e025000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x25000000 0x0 0x1000>; interrupts = <1 22 4>; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts index d005e1e79c3d..89fc4107a0c4 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -14,7 +14,7 @@ model = "Cavium ThunderX2 CN99XX"; compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index 3419bd252696..6dfe78a7d4ab 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -83,7 +83,7 @@ }; pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + compatible = "brcm,vulcan-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ }; @@ -103,7 +103,6 @@ /* ECAM at 0x3000_0000 - 0x4000_0000 */ reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; /* * PCI ranges: diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7fbbec04bff0..0b9053b9b2b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1468,6 +1468,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; num-cs = <1>; + fifo-depth = <256>; status = "disabled"; }; @@ -1487,6 +1488,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1506,6 +1508,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1525,6 +1528,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi3_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1544,6 +1548,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi4_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 2ba67c3d0681..0706c8534ceb 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -93,6 +93,8 @@ compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; + clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; + clock-names = "cluster0_clk"; }; cpu1: cpu@1 { device_type = "cpu"; @@ -117,6 +119,8 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; + clock-names = "cluster1_clk"; }; cpu5: cpu@101 { device_type = "cpu"; @@ -254,6 +258,28 @@ "dout_peri_uart", "dout_peri_ip"; }; + cmu_cpucl1: clock-controller@10800000 { + compatible = "samsung,exynos850-cmu-cpucl1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL1_DBG>; + clock-names = "oscclk", "dout_cpucl1_switch", + "dout_cpucl1_dbg"; + }; + + cmu_cpucl0: clock-controller@10900000 { + compatible = "samsung,exynos850-cmu-cpucl0"; + reg = <0x10900000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL0_DBG>; + clock-names = "oscclk", "dout_cpucl0_switch", + "dout_cpucl0_dbg"; + }; + cmu_g3d: clock-controller@11400000 { compatible = "samsung,exynos850-cmu-g3d"; reg = <0x11400000 0x8000>; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index c871a2f49fda..0248329da49a 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -435,6 +435,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -526,6 +527,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -617,6 +619,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -708,6 +711,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -799,6 +803,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -890,6 +895,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -981,6 +987,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -1072,6 +1079,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1163,6 +1171,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1254,6 +1263,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1345,6 +1355,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1434,6 +1445,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 6ccade2c8cb4..6be15e990b65 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -29,8 +29,8 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; + pinctrl-names = "default"; button-vol-down { label = "KEY_VOLUMEDOWN"; @@ -103,8 +103,6 @@ }; &serial_0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 55e6bcb3689e..eddb6b326fde 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -373,9 +373,393 @@ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi1: usi@109000c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1000>; + status = "disabled"; + + hsi2c_1: i2c@10900000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_1: serial@10900000 { + compatible = "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart1_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_1: spi@10900000 { + compatible = "google,gs101-spi"; + reg = <0x10900000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@109100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; + + hsi2c_2: i2c@10910000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@10910000 { + compatible = "google,gs101-uart"; + reg = <0x10910000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@10910000 { + compatible = "google,gs101-spi"; + reg = <0x10910000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@109200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1008>; + status = "disabled"; + + hsi2c_3: i2c@10920000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@10920000 { + compatible = "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@10920000 { + compatible = "google,gs101-spi"; + reg = <0x10920000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi4: usi@109300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; + + hsi2c_4: i2c@10930000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@10930000 { + compatible = "google,gs101-uart"; + reg = <0x10930000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@10930000 { + compatible = "google,gs101-spi"; + reg = <0x10930000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@109400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1010>; + status = "disabled"; + + hsi2c_5: i2c@10940000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@10940000 { + compatible = "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@10940000 { + compatible = "google,gs101-spi"; + reg = <0x10940000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6: usi@109500c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; + + hsi2c_6: i2c@10950000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10950000 { + compatible = "google,gs101-uart"; + reg = <0x10950000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_6: spi@10950000 { + compatible = "google,gs101-spi"; + reg = <0x10950000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7: usi@109600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1018>; + status = "disabled"; + + hsi2c_7: i2c@10960000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@10960000 { + compatible = "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@10960000 { + compatible = "google,gs101-spi"; + reg = <0x10960000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi8: usi@109700c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x109700c0 0x20>; ranges; #address-cells = <1>; @@ -393,18 +777,44 @@ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hsi2c8_bus>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@10970000 { + compatible = "google,gs101-uart"; + reg = <0x10970000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@10970000 { + compatible = "google,gs101-spi"; + reg = <0x10970000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi8_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; usi_uart: usi@10a000c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10a000c0 0x20>; ranges; #address-cells = <1>; @@ -419,16 +829,72 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - interrupts = <GIC_SPI 634 - IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + pinctrl-0 = <&uart0_bus>; + pinctrl-names = "default"; samsung,uart-fifosize = <256>; status = "disabled"; }; }; + usi14: usi@10a200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10a200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1028>; + status = "disabled"; + + hsi2c_14: i2c@10a20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10a20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@10a20000 { + compatible = "google,gs101-uart"; + reg = <0x10a20000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_14: spi@10a20000 { + compatible = "google,gs101-spi"; + reg = <0x10a20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_peric1: clock-controller@10c00000 { compatible = "google,gs101-cmu-peric1"; reg = <0x10c00000 0x4000>; @@ -451,9 +917,228 @@ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi0: usi@10d100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1000>; + status = "disabled"; + + hsi2c_0: i2c@10d10000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_usi0: serial@10d10000 { + compatible = "google,gs101-uart"; + reg = <0x10d10000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart0_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_0: spi@10d10000 { + compatible = "google,gs101-spi"; + reg = <0x10d10000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@10d200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1004>; + status = "disabled"; + + hsi2c_9: i2c@10d20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10d20000 { + compatible = "google,gs101-uart"; + reg = <0x10d20000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@10d20000 { + compatible = "google,gs101-spi"; + reg = <0x10d20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@10d300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1008>; + status = "disabled"; + + hsi2c_10: i2c@10d30000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10d30000 { + compatible = "google,gs101-uart"; + reg = <0x10d30000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@10d30000 { + compatible = "google,gs101-spi"; + reg = <0x10d30000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@10d400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x100c>; + status = "disabled"; + + hsi2c_11: i2c@10d40000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10d40000 { + compatible = "google,gs101-uart"; + reg = <0x10d40000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@10d40000 { + compatible = "google,gs101-spi"; + reg = <0x10d40000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi12: usi@10d500c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10d500c0 0x20>; ranges; #address-cells = <1>; @@ -471,11 +1156,93 @@ interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&hsi2c12_bus>; - pinctrl-names = "default"; clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@10d50000 { + compatible = "google,gs101-uart"; + reg = <0x10d50000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_12: spi@10d50000 { + compatible = "google,gs101-spi"; + reg = <0x10d50000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi13: usi@10d600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1014>; + status = "disabled"; + + hsi2c_13: i2c@10d60000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@10d60000 { + compatible = "google,gs101-uart"; + reg = <0x10d60000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_13: spi@10d60000 { + compatible = "google,gs101-spi"; + reg = <0x10d60000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spi13_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 045250d0a040..bd443c2bc5a4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb @@ -98,6 +99,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-aster.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb @@ -166,6 +171,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb @@ -259,4 +265,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb +dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index fe9093b3c02e..a0f7bbd691a0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -81,7 +81,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts index ed4e69e87e30..195bdbafdf7c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts @@ -10,7 +10,7 @@ /dts-v1/; #include <dt-bindings/clock/fsl,qoriq-clockgen.h> -#include "fsl-ls1028a-kontron-sl28.dts" +#include "fsl-ls1028a-kontron-sl28-var3.dts" / { model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts new file mode 100644 index 000000000000..08851ca407a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 3 which has one ethernet ports. + * + * Copyright (C) 2024 Michael Walle <michael@walle.cc> + * + */ + +/dts-v1/; + +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (Single PHY)"; + compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ae534c23b970..70b8731029c4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1099,21 +1099,25 @@ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 /* BAR4 (PF5) - non-prefetchable memory */ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; enetc_port0: ethernet@0,0 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000000 0 0 0 0>; status = "disabled"; }; enetc_port1: ethernet@0,1 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000100 0 0 0 0>; status = "disabled"; }; enetc_port2: ethernet@0,2 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000200 0 0 0 0>; phy-mode = "internal"; status = "disabled"; @@ -1126,14 +1130,14 @@ }; enetc_mdio_pf3: mdio@0,3 { - compatible = "fsl,enetc-mdio"; + compatible = "pci1957,ee01", "fsl,enetc-mdio"; reg = <0x000300 0 0 0 0>; #address-cells = <1>; #size-cells = <0>; }; ethernet@0,4 { - compatible = "fsl,enetc-ptp"; + compatible = "pci1957,ee02", "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; little-endian; @@ -1143,7 +1147,7 @@ mscc_felix: ethernet-switch@0,5 { reg = <0x000500 0 0 0 0>; /* IEP INT_B */ - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <2>; status = "disabled"; mscc_felix_ports: ports { @@ -1201,7 +1205,7 @@ }; enetc_port3: ethernet@0,6 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000600 0 0 0 0>; phy-mode = "internal"; status = "disabled"; @@ -1216,7 +1220,7 @@ rcec@1f,0 { reg = <0x00f800 0 0 0 0>; /* IEP INT_A */ - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d333b773bc45..8ee6d8c0ef61 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -276,7 +276,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 0x4>, <0 107 0x4>, <0 95 0x4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1aa38ed09aa4..8352197cea6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -12,6 +12,13 @@ #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 8581ea55d254..245bbd615c81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,6 +12,13 @@ #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 0b7292835906..ccba0a135b24 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -247,11 +247,6 @@ <1 10 4>; /* Hypervisor PPI, active-low */ }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index e665c629e1a1..96055593204a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -748,7 +748,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; - scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_scl>; + pinctrl-1 = <&i2c0_scl_gpio>; + scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -761,6 +764,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_scl>; + pinctrl-1 = <&i2c1_scl_gpio>; + scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -773,6 +780,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_scl>; + pinctrl-1 = <&i2c2_scl_gpio>; + scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -785,6 +796,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c3_scl>; + pinctrl-1 = <&i2c3_scl_gpio>; + scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -797,7 +812,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; - scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_scl>; + pinctrl-1 = <&i2c4_scl_gpio>; + scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -810,6 +828,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c5_scl>; + pinctrl-1 = <&i2c5_scl_gpio>; + scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -822,6 +844,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c6_scl>; + pinctrl-1 = <&i2c6_scl_gpio>; + scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -834,6 +860,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c7_scl>; + pinctrl-1 = <&i2c7_scl_gpio>; + scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -1669,6 +1699,80 @@ }; }; + pinmux_i2crv: pinmux@70010012c { + compatible = "pinctrl-single"; + reg = <0x00000007 0x0010012c 0x0 0xc>; + #address-cells = <2>; + #size-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; + + i2c1_scl: i2c1-scl-pins { + pinctrl-single,bits = <0x0 0 0x7>; + }; + + i2c1_scl_gpio: i2c1-scl-gpio-pins { + pinctrl-single,bits = <0x0 0x1 0x7>; + }; + + i2c2_scl: i2c2-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 3)>; + }; + + i2c2_scl_gpio: i2c2-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; + }; + + i2c3_scl: i2c3-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 6)>; + }; + + i2c3_scl_gpio: i2c3-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; + }; + + i2c4_scl: i2c4-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 9)>; + }; + + i2c4_scl_gpio: i2c4-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; + }; + + i2c5_scl: i2c5-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 12)>; + }; + + i2c5_scl_gpio: i2c5-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; + }; + + i2c6_scl: i2c6-scl-pins { + pinctrl-single,bits = <0x4 0x2 0x7>; + }; + + i2c6_scl_gpio: i2c6-scl-gpio-pins { + pinctrl-single,bits = <0x4 0x1 0x7>; + }; + + i2c7_scl: i2c7-scl-pins { + pinctrl-single,bits = <0x4 0x2 0x7>; + }; + + i2c7_scl_gpio: i2c7-scl-gpio-pins { + pinctrl-single,bits = <0x4 0x1 0x7>; + }; + + i2c0_scl: i2c0-scl-pins { + pinctrl-single,bits = <0x8 0 (0x7 << 10)>; + }; + + i2c0_scl_gpio: i2c0-scl-gpio-pins { + pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 9f88583aa25e..eafef8718a0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -25,6 +25,7 @@ i2c7 = &mpcie1_i2c; i2c8 = &mpcie0_i2c; i2c9 = &pcieclk_i2c; + i2c10 = &i2c5; mmc0 = &esdhc0; mmc1 = &esdhc1; serial0 = &uart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi index 0580ea30cfbc..e914291e63a1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -71,3 +71,12 @@ reg = <0x54>; }; }; + +&i2c5 { + status = "okay"; + + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 07afeb78ed56..897cbb7b6742 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/clock/imx8-lpcg.h> +#include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/firmware/imx/rsrc.h> audio_ipg_clk: clock-audio-ipg { @@ -119,13 +120,96 @@ audio_subsys: bus@59000000 { #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59000000 0x10000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, + <&edma0 1 0 0>, + <&edma0 2 0 0>, + <&edma0 3 0 FSL_EDMA_RX>, + <&edma0 4 0 FSL_EDMA_RX>, + <&edma0 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <0>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59010000 0x10000>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba"; + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + sai0: sai@59040000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sai0_lpcg 1>, + clocks = <&sai0_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai0_lpcg 0>, + <&sai0_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -139,9 +223,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59050000 0x10000>; interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sai1_lpcg 1>, + clocks = <&sai1_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai1_lpcg 0>, + <&sai1_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -155,9 +239,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59060000 0x10000>; interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sai2_lpcg 1>, + clocks = <&sai2_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai2_lpcg 0>, + <&sai2_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -171,9 +255,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59070000 0x10000>; interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sai3_lpcg 1>, + clocks = <&sai3_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai3_lpcg 0>, + <&sai3_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -239,6 +323,40 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_0_CH23>; }; + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + sai0_lpcg: clock-controller@59440000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59440000 0x10000>; @@ -333,6 +451,101 @@ audio_subsys: bus@59000000 { status = "disabled"; }; + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59800000 0x10000>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, + <&edma1 1 0 0>, + <&edma1 2 0 0>, + <&edma1 3 0 FSL_EDMA_RX>, + <&edma1 4 0 FSL_EDMA_RX>, + <&edma1 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <1>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 10 0 0>; + dma-names = "tx"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk", "core"; + power-domains = <&pd IMX_SC_R_MQS_0>; + status = "disabled"; + }; + edma1: dma-controller@599f0000 { compatible = "fsl,imx8qm-edma"; reg = <0x599f0000 0xc0000>; @@ -481,4 +694,60 @@ audio_subsys: bus@59000000 { "sai3_rx_bclk", "sai4_rx_bclk"; }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi new file mode 100644 index 000000000000..92752c0c5eb5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; +}; + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + interrupt-parent = <&cm40_intmux>; + + cm40_lpuart: serial@37220000 { + compatible = "fsl,imx8qxp-lpuart"; + reg = <0x37220000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + status = "disabled"; + }; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>, + <&cm40_i2c_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_intmux: intmux@37400000 { + compatible = "fsl,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + + cm40_uart_lpcg: clock-controller@37620000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37620000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>; + clock-output-names = "cm40_lpcg_uart_clk", + "cm40_lpcg_uart_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index e7783cc2d830..77d2928997b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -21,7 +21,6 @@ img_subsys: bus@58000000 { interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; @@ -35,7 +34,6 @@ img_subsys: bus@58000000 { interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts new file mode 100644 index 000000000000..c974f5dc0283 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Aster Board"; + compatible = "toradex,colibri-imx8x-aster", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts new file mode 100644 index 000000000000..f2bf15463ae8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8x-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts new file mode 100644 index 000000000000..fd425c70cf2b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board"; + compatible = "toradex,colibri-imx8x-iris-v2", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts new file mode 100644 index 000000000000..e5e2346ce4f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris Board"; + compatible = "toradex,colibri-imx8x-iris", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi new file mode 100644 index 000000000000..66b0fcc6687d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +#include "imx8dx.dtsi" +#include "imx8x-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8DX Module"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi new file mode 100644 index 000000000000..ce76efc1a041 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" + +&gpu_3d0 { + assigned-clock-rates = <372000000>, <372000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 2123d431e061..2412ab145c06 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -16,6 +16,8 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart0; + serial1 = &lpuart1; + serial6 = &cm40_lpuart; }; chosen { @@ -51,6 +53,16 @@ }; }; + m2_uart1_sel: regulator-m2uart1sel { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_uart1_sel"; + gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + mux3_en: regulator-0 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -340,6 +352,12 @@ status = "okay"; }; +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -354,6 +372,16 @@ status = "okay"; }; +&cm40_intmux { + status = "disabled"; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "disabled"; +}; + &lsio_gpio4 { status = "okay"; }; @@ -595,6 +623,15 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a0674c5c5576..7e54cf202858 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/dma/fsl-edma.h> +#include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -104,7 +105,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; @@ -231,6 +232,7 @@ }; /* sorted in register address */ + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" @@ -241,3 +243,14 @@ #include "imx8dxl-ss-conn.dtsi" #include "imx8dxl-ss-lsio.dtsi" #include "imx8dxl-ss-ddr.dtsi" + +&cm40_intmux { + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index bd5b365867fd..90d1901df2b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -72,6 +72,20 @@ enable-active-high; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + reg_vddext_3v3: regulator-vddext-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDEXT_3V3"; @@ -381,7 +395,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec1>; reg = <0x50>; @@ -441,6 +455,9 @@ assigned-clock-rates = <24000000>; powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&buck5_reg>; + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v5>; port { ov5640_to_mipi_csi2: endpoint { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index d643381417f1..affbc67c2ef6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -117,7 +117,6 @@ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 41c966147b94..429be2bab8a2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -57,7 +57,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 5e2cbaf27e0f..35ae0faa815b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -297,7 +297,7 @@ }; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index 1cff0b829357..ce20de259805 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,name = "verdin-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -32,6 +32,25 @@ sound-dai = <&sai2>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + startup-delay-us = <100000>; + }; }; /* Verdin SPI_1 */ @@ -58,6 +77,11 @@ status = "okay"; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; @@ -93,6 +117,7 @@ /* Verdin PCIE_1 */ &pcie0 { + vpcie-supply = <®_pcie>; status = "okay"; }; @@ -115,6 +140,11 @@ status = "okay"; }; +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin I2S_1 */ &sai2 { status = "okay"; @@ -143,8 +173,16 @@ /* Verdin USB_2 */ &usbotg2 { + #address-cells = <1>; + #size-cells = <0>; disable-over-current; status = "okay"; + + usb-hub@1 { + compatible = "usb424,2744"; + reg = <1>; + vdd-supply = <®_usb_hub>; + }; }; /* Verdin SD_1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi index 3c4b8ca125e3..1d8d146d9eeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-nau8822"; + simple-audio-card,name = "verdin-nau8822"; simple-audio-card,routing = "Headphones", "LHP", "Headphones", "RHP", @@ -78,6 +78,11 @@ status = "okay"; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &gpio_expander_21 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi index 1e28c78e381f..763f069e8405 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi @@ -81,6 +81,11 @@ pinctrl-0 = <&pinctrl_gpios_ext_yavia>; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &hwmon_temp { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 6f0811587142..4768b05fd765 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -110,6 +110,22 @@ startup-delay-us = <200000>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + reg_usb_otg1_vbus: regulator-usb-otg1 { compatible = "regulator-fixed"; enable-active-high; @@ -333,16 +349,6 @@ "SODIMM_212", "SODIMM_151", "SODIMM_153"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <1 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; }; /* On-module I2C */ diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 8a1b42b94dce..9535dedcef59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1168,6 +1168,13 @@ remote-endpoint = <&lcdif_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; @@ -1253,7 +1260,6 @@ reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; @@ -1274,7 +1280,6 @@ reg = <0x32e50000 0x200>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts index 000e2c0596df..d25032e3ceab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -112,3 +112,19 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5>; + dvdd-supply = <&buck5>; + pvdd-supply = <&buck5>; + a2vdd-supply = <&buck5>; + v1p2-supply = <&buck5>; + }; +}; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index cc2ff59ac53b..6d85a0b052c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -158,3 +158,19 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5_reg>; + dvdd-supply = <&buck5_reg>; + pvdd-supply = <&buck5_reg>; + a2vdd-supply = <&buck5_reg>; + v1p2-supply = <&buck5_reg>; + }; +}; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 0b71f50d936e..41330210a05f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -125,3 +125,19 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5>; + dvdd-supply = <&buck5>; + pvdd-supply = <&buck5>; + a2vdd-supply = <&buck5>; + v1p2-supply = <&buck5>; + }; +}; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 269e70f66a13..9e0259ddf4bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -30,7 +30,7 @@ port { hdmi_connector_in: endpoint { - remote-endpoint = <&adv7533_out>; + remote-endpoint = <&adv7535_out>; }; }; }; @@ -52,6 +52,27 @@ enable-active-high; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vddext_3v3: regulator-vddext-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; @@ -193,15 +214,11 @@ hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; + v3p3-supply = <®_vddext_3v3>; ports { #address-cells = <1>; @@ -210,7 +227,7 @@ port@0 { reg = <0>; - adv7533_in: endpoint { + adv7535_in: endpoint { remote-endpoint = <&dsi_out>; }; }; @@ -218,7 +235,7 @@ port@1 { reg = <1>; - adv7533_out: endpoint { + adv7535_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; @@ -227,7 +244,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec1>; reg = <0x50>; @@ -284,6 +301,8 @@ assigned-clock-rates = <24000000>; powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v5>; port { ov5640_to_mipi_csi2: endpoint { @@ -335,7 +354,7 @@ reg = <1>; dsi_out: endpoint { - remote-endpoint = <&adv7533_in>; + remote-endpoint = <&adv7535_in>; data-lanes = <1 2 3 4>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index a6b94d1957c9..3434b189fa58 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -126,7 +126,6 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; port { typec1_dr_sw: endpoint { diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 932c8b05c75f..a5f9cfb46e5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1104,6 +1104,13 @@ remote-endpoint = <&lcdif_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; @@ -1213,7 +1220,6 @@ reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index a08057410bde..e5d3901f2913 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -340,7 +340,7 @@ &i2c3 { /* Connected to USB Hub */ usb-typec@52 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 2c19766ebf09..9b8f97a84e61 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -197,10 +197,8 @@ }; &i2c2 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; }; &i2c3 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts index b11d694b98e1..d241db3743a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -144,7 +144,6 @@ pinctrl-0 = <&pinctrl_eqos>; nvmem-cells = <ðmac1>; nvmem-cell-names = "mac-address"; - phy-supply = <®_baseboard_vdd3v3>; phy-handle = <ðphy0>; phy-mode = "rgmii-id"; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index b749e28e5ede..ac7ec7533a3c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -167,6 +167,16 @@ VDDIO-supply = <®_vdd_3p3v_awo>; }; + csi2exp: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "CSI2_#RESET", "CSI2_#PWDN", + "CSI_#PWDN", "CSI_#RESET"; + }; + typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9beba8d6a0df..8be5b2a57f27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -145,6 +145,27 @@ }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -198,6 +219,10 @@ cpu-supply = <®_arm>; }; +&aud2htx { + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -524,6 +549,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -790,6 +825,16 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index 61c2a63efc6d..0fd5c3abcdb7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -200,8 +200,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -241,8 +244,11 @@ }; &i2c6 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -602,38 +608,50 @@ pinctrl_i2c1: i2c1grp { fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>; + <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e0>, + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e0>; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e0>, + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e0>; }; pinctrl_i2c2: i2c2grp { fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>; + <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e0>, + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e0>; }; pinctrl_i2c3: i2c3grp { fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>; + <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e0>, + <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e0>; }; pinctrl_i2c4: i2c4grp { fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>; + <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e0>, + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e0>; }; pinctrl_i2c5: i2c5grp { fsl,pins = - <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>, - <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>; + <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e0>, + <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e0>; }; pinctrl_i2c6: i2c6grp { fsl,pins = - <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>, - <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>; + <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001e0>, + <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001e0>; + }; + + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e0>, + <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e0>; }; pinctrl_lcd0_backlight: lcd0-backlightgrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts new file mode 100644 index 000000000000..5fd1614982cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Emcraft Systems + * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "imx8mp.dtsi" + +/ { + model = "Emcraft Systems i.MX8MPlus NavQ+ Kit"; + compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <10000>; + qca,disable-smarteee; + qca,disable-hibernation-mode; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + }; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 86d3da36e4f3..c51ed7d991d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -135,6 +135,18 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "X44"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + display: display { /* * Display is not fixed, so compatible has to be added from @@ -470,6 +482,28 @@ "", "", "", ""; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c2 { clock-frequency = <384000>; pinctrl-names = "default", "gpio"; @@ -531,6 +565,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &pcf85063 { /* RTC_EVENT# is connected on MBa8MPxL */ pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index e7bf032265e0..2f740d74707b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -68,7 +68,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi index 41c79d2ebdd6..cda1671d2259 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi @@ -8,6 +8,10 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + aliases { + ethernet1 = ð1; + }; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; pinctrl-names = "default"; @@ -151,6 +155,38 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@3,0 { + reg = <0x1800 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + eth1: ethernet@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; }; /* GPS */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi index d5c400b355af..e63811b38c64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi @@ -8,6 +8,10 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + aliases { + ethernet1 = ð1; + }; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; pinctrl-names = "default"; @@ -163,6 +167,38 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@4,0 { + reg = <0x2000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + eth1: ethernet@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; }; /* GPS */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso index 270a9114da97..edf22ff549a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso @@ -62,12 +62,25 @@ status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + mipi_csi_0_in: endpoint { remote-endpoint = <&imx219_to_mipi_csi2>; data-lanes = <1 2>; }; }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index cae586cd45bd..a77e9a44d9fa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -404,6 +404,12 @@ label = "vdd_dram"; }; + channel@9e { + gw,mode = <2>; + reg = <0x9e>; + label = "vdd_1p0"; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 7e9e4b13b5c5..6e6b9c2c4640 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mp-wm8904"; + simple-audio-card,name = "verdin-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -32,6 +32,25 @@ sound-dai = <&sai1>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + startup-delay-us = <100000>; + }; }; &backlight { @@ -70,6 +89,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; @@ -110,8 +134,14 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { + vpcie-supply = <®_pcie>; status = "okay"; }; @@ -138,6 +168,11 @@ vin-supply = <®_3p3v>; }; +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin I2S_1 */ &sai1 { assigned-clocks = <&clk IMX8MP_CLK_SAI1>; @@ -181,6 +216,25 @@ status = "okay"; }; +&usb_dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_3_0: usb-hub@1 { + compatible = "usb424,5744"; + reg = <1>; + peer-hub = <&usb_hub_2_0>; + vdd-supply = <®_usb_hub>; + }; + + usb_hub_2_0: usb-hub@2 { + compatible = "usb424,2744"; + reg = <2>; + peer-hub = <&usb_hub_3_0>; + vdd-supply = <®_usb_hub>; + }; +}; + /* Verdin SD_1 */ &usdhc2 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index a509b2b7fa85..42ed44a11711 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -22,7 +22,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mp-nau8822"; + simple-audio-card,name = "verdin-nau8822"; simple-audio-card,routing = "Headphones", "LHP", "Headphones", "RHP", @@ -93,6 +93,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &gpio_expander_21 { status = "okay"; vcc-supply = <®_1p8v>; @@ -131,6 +136,11 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 8482393f3cac..1d15f7449c58 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -112,6 +112,11 @@ status = "okay"; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index db1722f0d80e..a7b261ff3e4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -100,6 +100,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &hwmon_temp { status = "okay"; }; @@ -117,6 +122,11 @@ status = "okay"; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index faa17cbbe2fd..aef4bef4bccd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -116,6 +116,22 @@ vin-supply = <®_vdd_3v3>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; enable-active-high; @@ -439,16 +455,6 @@ "SODIMM_256", "SODIMM_48", "SODIMM_44"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; }; /* On-module I2C */ @@ -664,8 +670,6 @@ }; }; -/* TODO: Verdin I2C_3_HDMI */ - /* Verdin I2C_4_CSI */ &i2c3 { clock-frequency = <400000>; @@ -764,6 +768,16 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + /* Verdin PCIE_1 */ &pcie { pinctrl-names = "default"; @@ -1106,8 +1120,6 @@ pinctrl_hdmi_hog: hdmihoggrp { fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ - <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ - <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ }; @@ -1163,6 +1175,19 @@ <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ }; + /* Verdin I2C_3_HDMI */ + pinctrl_i2c5: i2c5grp { + fsl,pins = + <MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c6>, /* SODIMM 59 */ + <MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c6>; /* SODIMM 57 */ + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c6>, /* SODIMM 59 */ + <MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c6>; /* SODIMM 57 */ + }; + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bfc5c81a5bd4..f3837d526fcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -836,6 +836,23 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_hdmimix: power-domain@14 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domain@15 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; @@ -1513,6 +1530,16 @@ status = "disabled"; }; + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + status = "disabled"; + }; }; sdma3: dma-controller@30e00000 { @@ -1630,7 +1657,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <500000000>; + clock-frequency = <266000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1640,7 +1667,7 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <500000000>; + assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1725,6 +1752,13 @@ remote-endpoint = <&lcdif1_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; @@ -1889,6 +1923,136 @@ #power-domain-cells = <1>; #clock-cells = <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells = <1>; + }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts index 366693f31992..e92b5d5a66b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts @@ -42,7 +42,7 @@ status = "okay"; typec_ptn5100: usb-typec@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x50>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 8055a2c23035..b268ba7a0e12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -429,7 +429,7 @@ }; typec_ptn5100: usb-typec@52 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c6dc3ba0d43b..e03186bbc415 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1290,6 +1290,13 @@ remote-endpoint = <&lcdif_mipi_dsi>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 77ac0efdfaad..5c6b39c6933f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -39,6 +39,20 @@ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; }; &i2c1 { @@ -71,6 +85,37 @@ status = "okay"; }; +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -130,6 +175,12 @@ >; }; + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 @@ -149,6 +200,41 @@ >; }; + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 + >; + }; + + pinctrl_lpspi2_cs: lpspi2csgrp { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 8360bb851ac0..cee13e58762c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -44,6 +44,22 @@ }; }; }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; }; &dsp { @@ -149,7 +165,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; reg = <0x50>; @@ -188,6 +204,47 @@ }; +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; + scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, + <49152000>, + <12288000>, + <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -218,6 +275,53 @@ status = "okay"; }; +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg IMX_LPCG_CLK_0>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg IMX_LPCG_CLK_0>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + &thermal_zones { pmic-thermal { polling-delay-passive = <250>; @@ -314,6 +418,21 @@ }; &iomuxc { + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { + fsl,pins = < + IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c + IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 @@ -385,6 +504,25 @@ >; }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 + IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 10e16d84c0c3..0313f295de2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -317,6 +317,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 24bb253b938d..e937e5f8fa8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -127,12 +127,70 @@ pinctrl-1 = <&pinctrl_lpi2c7>; status = "okay"; + ptn5150_1: typec@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + status = "disabled"; + }; + pcal6408: gpio@21 { compatible = "nxp,pcal9554b"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; + + ptn5150_2: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec2>; + status = "disabled"; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <110>; + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <110>; + status = "okay"; +}; + +&usbmisc2 { + status = "okay"; }; &usdhc0 { @@ -224,6 +282,32 @@ >; }; + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8ULP_PAD_PTF3__PTF3 0x3 + >; + }; + + pinctrl_typec2: typec2grp { + fsl,pins = < + MX8ULP_PAD_PTF5__PTF5 0x3 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTF2__USB0_ID 0x10003 + MX8ULP_PAD_PTF4__USB0_OC 0x10003 + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTF6__USB1_OC 0x10003 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c4a0082f30d3..e32d5afcf4a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -252,6 +252,38 @@ #reset-cells = <1>; }; + crypto: crypto@292e0000 { + compatible = "fsl,sec-v4.0"; + reg = <0x292e0000 0x10000>; + ranges = <0 0x292e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + tpm5: tpm@29340000 { compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; reg = <0x29340000 0x1000>; @@ -472,6 +504,68 @@ status = "disabled"; }; + usbotg1: usb@29900000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + reg = <0x29900000 0x200>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_USB0>; + power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@29900200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29900200 0x200>; + #index-cells = <1>; + status = "disabled"; + }; + + usbphy1: usb-phy@29910000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29910000 0x10000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbotg2: usb@29920000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + reg = <0x29920000 0x200>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_USB1>; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + phys = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc2: usbmisc@29920200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29920200 0x200>; + #index-cells = <1>; + status = "disabled"; + }; + + usbphy2: usb-phy@29930000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29930000 0x10000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + fec: ethernet@29950000 { compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x29950000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 9921ea13ab48..d400d85f42a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/usb/pd.h> #include "imx93.dtsi" / { @@ -38,7 +39,7 @@ no-map; }; - vdev1vring0: vdev1vring0@a4000000 { + vdev1vring0: vdev1vring0@a4010000 { reg = <0 0xa4010000 0 0x8000>; no-map; }; @@ -48,8 +49,8 @@ no-map; }; - rsc_table: rsc-table@2021f000 { - reg = <0 0x2021f000 0 0x1000>; + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; no-map; }; @@ -104,9 +105,85 @@ status = "okay"; }; -&eqos { +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; +}; + +&eqos { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; phy-mode = "rgmii-id"; phy-handle = <ðphy1>; status = "okay"; @@ -120,13 +197,17 @@ ethphy1: ethernet-phy@1 { reg = <1>; eee-broken-1000t; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; &fec { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; phy-mode = "rgmii-id"; phy-handle = <ðphy2>; fsl,magic-packet; @@ -140,6 +221,9 @@ ethphy2: ethernet-phy@2 { reg = <2>; eee-broken-1000t; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; @@ -156,21 +240,58 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; @@ -183,6 +304,118 @@ status = "okay"; }; +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -203,6 +436,25 @@ >; }; + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e @@ -222,6 +474,32 @@ >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e @@ -238,9 +516,63 @@ >; }; + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe @@ -267,9 +599,41 @@ >; }; + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe @@ -279,4 +643,17 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 601c94e1fac8..4a3f42355cb8 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -183,6 +184,20 @@ status = "disabled"; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -316,6 +331,8 @@ clocks = <&clk IMX93_CLK_LPI2C1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -328,6 +345,8 @@ clocks = <&clk IMX93_CLK_LPI2C2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -340,6 +359,8 @@ clocks = <&clk IMX93_CLK_LPSPI1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -352,6 +373,8 @@ clocks = <&clk IMX93_CLK_LPSPI2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -361,7 +384,7 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg"; - dmas = <&edma1 17 0 1>, <&edma1 16 0 0>; + dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -372,7 +395,7 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; - dmas = <&edma1 19 0 1>, <&edma1 18 0 0>; + dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -400,7 +423,7 @@ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -509,8 +532,7 @@ reg = <0x44530000 0x10000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; #io-channel-cells = <1>; @@ -693,6 +715,8 @@ clocks = <&clk IMX93_CLK_LPI2C3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -705,6 +729,8 @@ clocks = <&clk IMX93_CLK_LPI2C4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -717,6 +743,8 @@ clocks = <&clk IMX93_CLK_LPSPI3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -729,6 +757,8 @@ clocks = <&clk IMX93_CLK_LPSPI4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -738,7 +768,7 @@ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; - dmas = <&edma2 18 0 1>, <&edma2 17 0 0>; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -749,7 +779,7 @@ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; - dmas = <&edma2 20 0 1>, <&edma2 19 0 0>; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -760,7 +790,7 @@ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; - dmas = <&edma2 22 0 1>, <&edma2 21 0 0>; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -771,7 +801,7 @@ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; - dmas = <&edma2 24 0 1>, <&edma2 23 0 0>; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -814,7 +844,7 @@ <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 59 0 1>, <&edma2 58 0 0>; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -827,7 +857,7 @@ <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -846,7 +876,7 @@ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUD_XCVR_GATE>; clock-names = "ipg", "phy", "spba", "pll_ipg"; - dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -857,7 +887,7 @@ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; - dmas = <&edma2 88 0 1>, <&edma2 87 0 0>; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -868,7 +898,7 @@ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; - dmas = <&edma2 90 0 1>, <&edma2 89 0 0>; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -882,6 +912,8 @@ clocks = <&clk IMX93_CLK_LPI2C5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -894,6 +926,8 @@ clocks = <&clk IMX93_CLK_LPI2C6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -906,6 +940,8 @@ clocks = <&clk IMX93_CLK_LPI2C7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -918,6 +954,8 @@ clocks = <&clk IMX93_CLK_LPI2C8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -930,6 +968,8 @@ clocks = <&clk IMX93_CLK_LPSPI5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -942,6 +982,8 @@ clocks = <&clk IMX93_CLK_LPSPI6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -954,6 +996,8 @@ clocks = <&clk IMX93_CLK_LPSPI7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -966,6 +1010,8 @@ clocks = <&clk IMX93_CLK_LPSPI8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -986,6 +1032,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1000,6 +1049,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1030,6 +1082,8 @@ fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -1052,6 +1106,8 @@ assigned-clock-rates = <100000000>, <250000000>; intf_mode = <&wakeupmix_gpr 0x28>; snps,clk-csr = <0>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -1063,6 +1119,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1136,6 +1195,15 @@ reg = <0x47510000 0x10000>; #address-cells = <1>; #size-cells = <1>; + + eth_mac1: mac-address@4ec { + reg = <0x4ec 0x6>; + }; + + eth_mac2: mac-address@4f2 { + reg = <0x4f2 0x6>; + }; + }; s4muap: mailbox@47520000 { @@ -1167,6 +1235,50 @@ status = "disabled"; }; + usbotg1: usb@4c100000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c100200 0x200>; + #index-cells = <1>; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c200200 0x200>; + #index-cells = <1>; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 427467df42bf..815241526a0d 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -316,17 +316,11 @@ &mipi_dsi { samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; +}; - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&lvds_bridge_in>; - }; - }; - }; +&mipi_dsi_out { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_bridge_in>; }; &pwm3 { diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 5ac1cc9ff50e..fc19ae2e8d3b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2017-2021 NXP + * Copyright 2017-2021, 2024 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -14,6 +14,18 @@ #address-cells = <2>; #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_buf: shm@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd0000000 0x0 0x80>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -77,6 +89,19 @@ }; firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -113,6 +138,16 @@ status = "disabled"; }; + usdhc0: mmc@402f0000 { + compatible = "nxp,s32g2-usdhc"; + reg = <0x402f0000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 32>, <&clks 31>, <&clks 33>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index 9118d8d2ee01..00070c949e2a 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2019-2021 NXP + * Copyright 2019-2021, 2024 NXP */ /dts-v1/; @@ -32,3 +32,7 @@ &uart0 { status = "okay"; }; + +&usdhc0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index e05ee854cdf5..b3fc12899cae 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2019-2021 NXP + * Copyright 2019-2021, 2024 NXP */ /dts-v1/; @@ -38,3 +38,7 @@ &uart1 { status = "okay"; }; + +&usdhc0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi new file mode 100644 index 000000000000..c1b08992754b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2021-2023 NXP + * + * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> + * Ciprian Costea <ciprianmarian.costea@nxp.com> + * Andra-Teodora Ilie <andra.ilie@nxp.com> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "nxp,s32g3"; + interrupt-parent = <&gic>; + #address-cells = <0x02>; + #size-cells = <0x02>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + + dfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shm@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd0000000 0x0 0x80>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x80000000>; + + uart0: serial@401c8000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401c8000 0x3000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart1: serial@401cc000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401cc000 0x3000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + uart2: serial@402bc000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x402bc000 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + usdhc0: mmc@402f0000 { + compatible = "nxp,s32g3-usdhc", + "nxp,s32g2-usdhc"; + reg = <0x402f0000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 32>, + <&clks 31>, + <&clks 33>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + gic: interrupt-controller@50800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50800000 0x10000>, + <0x50900000 0x200000>, + <0x50400000 0x2000>, + <0x50410000 0x2000>, + <0x50420000 0x2000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */ + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */ + arm,no-tick-in-suspend; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts new file mode 100644 index 000000000000..9d674819876e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2021-2023 NXP + * + * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) + */ + +/dts-v1/; + +#include "s32g3.dtsi" + +/ { + model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)"; + compatible = "nxp,s32g399a-rdb3", "nxp,s32g3"; + + aliases { + mmc0 = &usdhc0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 4GiB RAM */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>, + <0x8 0x80000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc0 { + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..f6bc001c3832 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@1 { @@ -38,6 +45,13 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@2 { @@ -45,6 +59,13 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@3 { @@ -52,13 +73,33 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; }; + L2: l2-cache { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index f0672ec65b26..2d304efe081d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -82,7 +82,7 @@ }; }; - reg_sys_5v: regulator@0 { + reg_sys_5v: regulator-0 { compatible = "regulator-fixed"; regulator-name = "SYS_5V"; regulator-min-microvolt = <5000000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - reg_vdd_3v3: regulator@1 { + reg_vdd_3v3: regulator-1 { compatible = "regulator-fixed"; regulator-name = "VDD_3V3"; regulator-min-microvolt = <3300000>; @@ -101,7 +101,7 @@ vin-supply = <®_sys_5v>; }; - reg_5v_hub: regulator@2 { + reg_5v_hub: regulator-2 { compatible = "regulator-fixed"; regulator-name = "5V_HUB"; regulator-min-microvolt = <5000000>; @@ -514,6 +514,7 @@ #address-cells = <1>; #size-cells = <0>; port@0 { + reg = <0>; adv7533_in: endpoint { remote-endpoint = <&dsi_out0>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index be808bb2544e..a589954c29e2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -852,7 +852,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - tsensor: tsensor@0,f7030700 { + tsensor: tsensor@f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index c4eaebbb448f..b7792d443189 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -54,7 +54,7 @@ ranges = <0 0 0x0 0x90000000 0x08000000>, <1 0 0x0 0x98000000 0x08000000>; - nor-flash@0,0 { + nor-flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "numonyx,js28f00a", "cfi-flash"; @@ -75,7 +75,7 @@ }; }; - cpld@1,0 { + cpld@100000000 { compatible = "hisilicon,hip05-cpld"; reg = <1 0x0 0x100>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 65ddc0698f82..d0912ca5f237 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -279,6 +279,12 @@ }; }; + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, @@ -298,12 +304,6 @@ #size-cells = <2>; ranges; - refclk200mhz: refclk200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart0: serial@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index f46c33d10750..3d7285e6700e 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -258,6 +258,48 @@ }; }; + eth2: ethernet-0 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet-1 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth0: ethernet-4 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet-5 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + refclk: refclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, @@ -374,12 +416,6 @@ }; }; - refclk: refclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; @@ -436,7 +472,7 @@ }; }; - dsaf0: dsa@c7000000 { + dsaf0: dsa@c5000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; @@ -570,42 +606,6 @@ }; }; - eth0: ethernet-4 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet-5 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet-0 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet-1 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - sas0: sas@c3000000 { compatible = "hisilicon,hip06-sas-v2"; reg = <0 0xc3000000 0 0x10000>; @@ -733,7 +733,7 @@ status = "disabled"; }; - pcie0: pcie@a0090000 { + pcie0: pcie@b0000000 { compatible = "hisilicon,hip06-pcie-ecam"; reg = <0 0xb0000000 0 0x2000000>, <0 0xa0090000 0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 81d907ef43ed..00a6bfa7478c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1013,6 +1013,42 @@ }; }; + eth0: ethernet-0 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet-1 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth2: ethernet-2 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet-3 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, @@ -1343,7 +1379,7 @@ }; }; - dsaf0: dsa@c7000000 { + dsaf0: dsa@c5000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; @@ -1483,42 +1519,6 @@ }; }; - eth0: ethernet@4 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet@5 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet@0 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet@1 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - infiniband@c4000000 { compatible = "hisilicon,hns-roce-v1"; reg = <0x0 0xc4000000 0x0 0x100000>; @@ -1724,7 +1724,7 @@ status = "disabled"; }; - p0_pcie2_a: pcie@a00a0000 { + p0_pcie2_a: pcie@af800000 { compatible = "hisilicon,hip07-pcie-ecam"; reg = <0 0xaf800000 0 0x800000>, <0 0xa00a0000 0 0x10000>; @@ -1745,7 +1745,7 @@ 0x0 0 0 4 &mbigen_pcie2_a 671 4>; status = "disabled"; }; - p0_sec_a: crypto@d2000000 { + p0_sec_a: crypto@d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x0 0xd0000000 0x0 0x10000>, <0x0 0xd2000000 0x0 0x10000>, @@ -1786,7 +1786,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto@8,d2000000 { + p0_sec_b: crypto@8d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000>, <0x8 0xd2000000 0x0 0x10000>, @@ -1827,7 +1827,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto@400,d2000000 { + p1_sec_a: crypto@400d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000>, <0x400 0xd2000000 0x0 0x10000>, @@ -1868,7 +1868,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto@408,d2000000 { + p1_sec_b: crypto@408d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000>, <0x408 0xd2000000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index 781761d2942b..ae00e9e54e82 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -70,7 +70,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 76aafa172eb0..2a5eeb21da47 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -80,7 +80,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/lg/lg1312-ref.dts b/arch/arm64/boot/dts/lg/lg1312-ref.dts index 260a2c5b19e5..cdd10f138098 100644 --- a/arch/arm64/boot/dts/lg/lg1312-ref.dts +++ b/arch/arm64/boot/dts/lg/lg1312-ref.dts @@ -22,7 +22,7 @@ serial2 = &uart2; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts index e89ae853788a..6ace977ff4cf 100644 --- a/arch/arm64/boot/dts/lg/lg1313-ref.dts +++ b/arch/arm64/boot/dts/lg/lg1313-ref.dts @@ -22,7 +22,7 @@ serial2 = &uart2; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 5591939e057b..75377c292bcb 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -68,7 +68,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts index d6d37a1f6f38..91c2f8b4edfa 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts @@ -25,8 +25,6 @@ /* Actual device is MV88E6361 */ switch: switch@0 { compatible = "marvell,mv88e6190"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 870bb380a40a..b3cc2b7b5d19 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -114,54 +114,84 @@ }; &mdio { + /* Switch is @3, not @1 */ + /delete-node/ ethernet-switch@1; extphy: ethernet-phy@1 { reg = <1>; reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; }; -}; -&switch0 { - reg = <3>; + switch0: ethernet-switch@3 { + compatible = "marvell,mv88e6085"; + reg = <3>; - reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + dsa,member = <0 0>; - ethernet-ports { - switch0port1: ethernet-port@1 { - reg = <1>; - label = "lan0"; - phy-handle = <&switch0phy0>; - }; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch0port0: ethernet-port@0 { + reg = <0>; + label = "cpu"; + ethernet = <ð0>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; - switch0port2: ethernet-port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; + switch0port1: ethernet-port@1 { + reg = <1>; + label = "lan0"; + phy-handle = <&switch0phy0>; + }; - switch0port3: ethernet-port@3 { - reg = <3>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; + switch0port2: ethernet-port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; - switch0port4: ethernet-port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; + switch0port3: ethernet-port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; - switch0port5: ethernet-port@5 { - reg = <5>; - label = "wan"; - phy-handle = <&extphy>; - phy-mode = "sgmii"; + switch0port4: ethernet-port@4 { + reg = <4>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + switch0port5: ethernet-port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&extphy>; + phy-mode = "sgmii"; + }; }; - }; - mdio { - switch0phy3: ethernet-phy@14 { - reg = <0x14>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: ethernet-phy@11 { + reg = <0x11>; + }; + switch0phy1: ethernet-phy@12 { + reg = <0x12>; + }; + switch0phy2: ethernet-phy@13 { + reg = <0x13>; + }; + switch0phy3: ethernet-phy@14 { + reg = <0x14>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f1a9f2234359..54453b0a91f9 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -216,8 +216,6 @@ assigned-clock-rates = <20000000>; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 1cc3fa1c354d..9603223dd761 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -68,7 +68,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 7ec7c789d87e..fdf88cd0eb02 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -61,7 +61,7 @@ compatible = "simple-bus"; ranges = <0x0 0x0 0xf0000000 0x1000000>; - smmu: iommu@5000000 { + smmu: iommu@100000 { compatible = "marvell,ap806-smmu-500", "arm,mmu-500"; reg = <0x100000 0x100000>; dma-coherent; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 6fcc34f7b464..5e7d6de3cdde 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -26,7 +26,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ap0_reg_mmc_vccq: ap0_mmc_vccq@0 { + ap0_reg_mmc_vccq: regulator-1 { compatible = "regulator-gpio"; regulator-name = "ap0_mmc_vccq"; regulator-min-microvolt = <1800000>; @@ -36,7 +36,7 @@ 3300000 0x0>; }; - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + cp0_reg_usb3_vbus1: regulator-2 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -45,16 +45,16 @@ gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy0: cp0_usb3_phy0 { + cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; }; - cp0_usb3_0_phy1: cp0_usb3_phy1 { + cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus1>; }; - cp0_reg_sd_vccq: cp0_sd_vccq@0 { + cp0_reg_sd_vccq: regulator-3 { compatible = "regulator-gpio"; regulator-name = "cp0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -64,7 +64,7 @@ 3300000 0x0>; }; - cp0_reg_sd_vcc: cp0_sd_vcc@0 { + cp0_reg_sd_vcc: regulator-4 { compatible = "regulator-fixed"; regulator-name = "cp0_sd_vcc"; regulator-min-microvolt = <3300000>; @@ -82,7 +82,6 @@ tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; - status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 6eb6a175de38..be56a2336265 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -30,7 +30,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ap0_reg_sd_vccq: ap0_sd_vccq@0 { + ap0_reg_sd_vccq: regulator-1 { compatible = "regulator-gpio"; regulator-name = "ap0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -39,7 +39,7 @@ states = <1800000 0x1 3300000 0x0>; }; - cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + cp0_reg_usb3_vbus0: regulator-2 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci0-vbus"; regulator-min-microvolt = <5000000>; @@ -48,12 +48,12 @@ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy0: cp0_usb3_phy@0 { + cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus0>; }; - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + cp0_reg_usb3_vbus1: regulator-3 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -62,12 +62,12 @@ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy1: cp0_usb3_phy@1 { + cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus1>; }; - cp0_reg_sd_vccq: cp0_sd_vccq@0 { + cp0_reg_sd_vccq: regulator-4 { compatible = "regulator-gpio"; regulator-name = "cp0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -77,7 +77,7 @@ 3300000 0x0>; }; - cp0_reg_sd_vcc: cp0_sd_vcc@0 { + cp0_reg_sd_vcc: regulator-5 { compatible = "regulator-fixed"; regulator-name = "cp0_sd_vcc"; regulator-min-microvolt = <3300000>; @@ -87,7 +87,7 @@ regulator-always-on; }; - cp0_sfp_eth0: sfp-eth@0 { + cp0_sfp_eth0: sfp-eth-1 { compatible = "sff,sfp"; i2c-bus = <&cp0_sfpp0_i2c>; los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; @@ -311,8 +311,6 @@ reg = <0x700680 0x50>; flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; /* On-board MUX does not allow higher frequencies */ diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index ff8422fae31b..ad7360c83048 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -18,7 +18,7 @@ ethernet4 = &cp1_eth1; }; - cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + cp1_reg_usb3_vbus0: regulator-6 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&cp1_xhci0_vbus_pins>; @@ -29,12 +29,12 @@ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; }; - cp1_usb3_0_phy0: cp1_usb3_phy0 { + cp1_usb3_0_phy0: usb-phy-3 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp1_reg_usb3_vbus0>; }; - cp1_sfp_eth1: sfp-eth1 { + cp1_sfp_eth1: sfp-eth-2 { compatible = "sff,sfp"; i2c-bus = <&cp1_i2c0>; los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; @@ -138,8 +138,6 @@ reg = <0x700680 0x50>; flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; /* On-board MUX does not allow higher frequencies */ diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index 512a4fa2861e..e753cfdac697 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -17,7 +17,7 @@ ethernet5 = &cp2_eth0; }; - cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + cp2_reg_usb3_vbus0: regulator-7 { compatible = "regulator-fixed"; regulator-name = "cp2-xhci0-vbus"; regulator-min-microvolt = <5000000>; @@ -26,12 +26,12 @@ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; }; - cp2_usb3_0_phy0: cp2_usb3_phy0 { + cp2_usb3_0_phy0: usb-phy-4 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp2_reg_usb3_vbus0>; }; - cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + cp2_reg_usb3_vbus1: regulator-8 { compatible = "regulator-fixed"; regulator-name = "cp2-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -40,12 +40,12 @@ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; }; - cp2_usb3_0_phy1: cp2_usb3_phy1 { + cp2_usb3_0_phy1: usb-phy-5 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp2_reg_usb3_vbus1>; }; - cp2_reg_sd_vccq: cp2_sd_vccq@0 { + cp2_reg_sd_vccq: regulator-9 { compatible = "regulator-gpio"; regulator-name = "cp2_sd_vcc"; regulator-min-microvolt = <1800000>; @@ -54,7 +54,7 @@ states = <1800000 0x1 3300000 0x0>; }; - cp2_sfp_eth0: sfp-eth0 { + cp2_sfp_eth0: sfp-eth-3 { compatible = "sff,sfp"; i2c-bus = <&cp2_sfpp0_i2c>; los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 9cbd6dd8f671..d0b03dc4d3f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -165,7 +165,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 24075cd91420..c3029e0abacc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -447,7 +447,7 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - reg = <0x6 0x110102d4 0x24>; + reg = <0x6 0x110102f8 0x24>; }; mdio3: mdio@61101031c { @@ -460,7 +460,7 @@ reg = <0x6 0x1101031c 0x24>; }; - serdes: serdes@10808000 { + serdes: serdes@610808000 { compatible = "microchip,sparx5-serdes"; #phy-cells = <1>; clocks = <&sys_clk>; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f3e226de5e5e..2c5574734c9e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -15,234 +15,234 @@ leds { compatible = "gpio-leds"; - led@0 { + led-0 { label = "twr0:green"; gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; }; - led@1 { + led-1 { label = "twr0:yellow"; gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; }; - led@2 { + led-2 { label = "twr1:green"; gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; }; - led@3 { + led-3 { label = "twr1:yellow"; gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; }; - led@4 { + led-4 { label = "twr2:green"; gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; }; - led@5 { + led-5 { label = "twr2:yellow"; gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; }; - led@6 { + led-6 { label = "twr3:green"; gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; }; - led@7 { + led-7 { label = "twr3:yellow"; gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; }; - led@8 { + led-8 { label = "eth12:green"; gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@9 { + led-9 { label = "eth12:yellow"; gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@10 { + led-10 { label = "eth13:green"; gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@11 { + led-11 { label = "eth13:yellow"; gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@12 { + led-12 { label = "eth14:green"; gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@13 { + led-13 { label = "eth14:yellow"; gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@14 { + led-14 { label = "eth15:green"; gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@15 { + led-15 { label = "eth15:yellow"; gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@16 { + led-16 { label = "eth48:green"; gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@17 { + led-17 { label = "eth48:yellow"; gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@18 { + led-18 { label = "eth49:green"; gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@19 { + led-19 { label = "eth49:yellow"; gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@20 { + led-20 { label = "eth50:green"; gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@21 { + led-21 { label = "eth50:yellow"; gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@22 { + led-22 { label = "eth51:green"; gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@23 { + led-23 { label = "eth51:yellow"; gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@24 { + led-24 { label = "eth52:green"; gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@25 { + led-25 { label = "eth52:yellow"; gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@26 { + led-26 { label = "eth53:green"; gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@27 { + led-27 { label = "eth53:yellow"; gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@28 { + led-28 { label = "eth54:green"; gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@29 { + led-29 { label = "eth54:yellow"; gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@30 { + led-30 { label = "eth55:green"; gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@31 { + led-31 { label = "eth55:yellow"; gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@32 { + led-32 { label = "eth56:green"; gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@33 { + led-33 { label = "eth56:yellow"; gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@34 { + led-34 { label = "eth57:green"; gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@35 { + led-35 { label = "eth57:yellow"; gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@36 { + led-36 { label = "eth58:green"; gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@37 { + led-37 { label = "eth58:yellow"; gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@38 { + led-38 { label = "eth59:green"; gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@39 { + led-39 { label = "eth59:yellow"; gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@40 { + led-40 { label = "eth60:green"; gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@41 { + led-41 { label = "eth60:yellow"; gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@42 { + led-42 { label = "eth61:green"; gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@43 { + led-43 { label = "eth61:yellow"; gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@44 { + led-44 { label = "eth62:green"; gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@45 { + led-45 { label = "eth62:yellow"; gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@46 { + led-46 { label = "eth63:green"; gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@47 { + led-47 { label = "eth63:yellow"; gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -274,15 +274,6 @@ &spi0 { status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0>; - }; -}; - -&spi0 { - status = "okay"; spi@0 { compatible = "spi-mux"; mux-controls = <&mux>; @@ -395,13 +386,13 @@ }; &axi { - i2c0_imux: i2c0-imux@0 { + i2c0_imux: i2c-mux-0 { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; #size-cells = <0>; i2c-parent = <&i2c0>; }; - i2c0_emux: i2c0-emux@0 { + i2c0_emux: i2c-mux-1 { compatible = "i2c-mux-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -427,62 +418,62 @@ pinctrl-10 = <&i2cmux_10>; pinctrl-11 = <&i2cmux_11>; pinctrl-12 = <&i2cmux_pins_i>; - i2c_sfp1: i2c_sfp1 { + i2c_sfp1: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp2: i2c_sfp2 { + i2c_sfp2: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp3: i2c_sfp3 { + i2c_sfp3: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp4: i2c_sfp4 { + i2c_sfp4: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp5: i2c_sfp5 { + i2c_sfp5: i2c@4 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp6: i2c_sfp6 { + i2c_sfp6: i2c@5 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp7: i2c_sfp7 { + i2c_sfp7: i2c@6 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp8: i2c_sfp8 { + i2c_sfp8: i2c@7 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp9: i2c_sfp9 { + i2c_sfp9: i2c@8 { reg = <0x8>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp10: i2c_sfp10 { + i2c_sfp10: i2c@9 { reg = <0x9>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp11: i2c_sfp11 { + i2c_sfp11: i2c@a { reg = <0xa>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp12: i2c_sfp12 { + i2c_sfp12: i2c@b { reg = <0xb>; #address-cells = <1>; #size-cells = <0>; @@ -495,42 +486,42 @@ &gpio 61 GPIO_ACTIVE_HIGH &gpio 54 GPIO_ACTIVE_HIGH>; idle-state = <0x8>; - i2c_sfp13: i2c_sfp13 { + i2c_sfp13: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp14: i2c_sfp14 { + i2c_sfp14: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp15: i2c_sfp15 { + i2c_sfp15: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp16: i2c_sfp16 { + i2c_sfp16: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp17: i2c_sfp17 { + i2c_sfp17: i2c@4 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp18: i2c_sfp18 { + i2c_sfp18: i2c@5 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp19: i2c_sfp19 { + i2c_sfp19: i2c@6 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp20: i2c_sfp20 { + i2c_sfp20: i2c@7 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 82ce007d9959..af2f1831f07f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -15,42 +15,42 @@ leds { compatible = "gpio-leds"; - led@0 { + led-0 { label = "eth60:yellow"; gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led-1 { label = "eth60:green"; gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led-2 { label = "eth61:yellow"; gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led-3 { label = "eth61:green"; gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@4 { + led-4 { label = "eth62:yellow"; gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@5 { + led-5 { label = "eth62:green"; gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@6 { + led-6 { label = "eth63:yellow"; gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@7 { + led-7 { label = "eth63:green"; gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; default-state = "off"; @@ -89,15 +89,6 @@ &spi0 { status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0>; - }; -}; - -&spi0 { - status = "okay"; spi@0 { compatible = "spi-mux"; mux-controls = <&mux>; @@ -129,7 +120,7 @@ }; &axi { - i2c0_imux: i2c0-imux@0 { + i2c0_imux: i2c-mux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; #size-cells = <0>; @@ -146,22 +137,22 @@ pinctrl-2 = <&i2cmux_s31>; pinctrl-3 = <&i2cmux_s32>; pinctrl-4 = <&i2cmux_pins_i>; - i2c_sfp1: i2c_sfp1 { + i2c_sfp1: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp2: i2c_sfp2 { + i2c_sfp2: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp3: i2c_sfp3 { + i2c_sfp3: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp4: i2c_sfp4 { + i2c_sfp4: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index a5ab2bc0f835..eeceb5b292a8 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -16,7 +16,7 @@ stdout-path = &serial0; }; - memory { + memory@0 { reg = <0x0 0x0 0x0 0x40000000>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 14d58859bb55..683ac124523b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -9,8 +9,8 @@ compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@7000d000/as3722@40"; - rtc1 = "/rtc@7000e000"; + rtc0 = &as3722; + rtc1 = &tegra_rtc; serial0 = &uarta; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7e24a212c7e4..5bcccfef3f7f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -572,7 +572,7 @@ status = "disabled"; }; - rtc@7000e000 { + tegra_rtc: rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 9ebb7369256e..2e5b6b2c1f56 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -25,7 +25,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 47f8268e46bf..882b1d1f4ada 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2004,7 +2004,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 78cbfdd98dd1..f2e2d8d6845b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4406,6 +4406,22 @@ */ status = "disabled"; }; + + crypto@15820000 { + compatible = "nvidia,tegra234-se-aes"; + reg = <0x00 0x15820000 0x00 0x10000>; + clocks = <&bpmp TEGRA234_CLK_SE>; + iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>; + dma-coherent; + }; + + crypto@15840000 { + compatible = "nvidia,tegra234-se-hash"; + reg = <0x00 0x15840000 0x00 0x10000>; + clocks = <&bpmp TEGRA234_CLK_SE>; + iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>; + dma-coherent; + }; }; pcie@140a0000 { diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7d40ec5e7d21..f63abb43e9fe 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9ffad7d1f2b6..aba08424aa38 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -91,7 +91,7 @@ compatible = "gpio-leds"; - led@1 { + led-1 { label = "apq8016-sbc:green:user1"; function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_GREEN>; @@ -100,7 +100,7 @@ default-state = "off"; }; - led@2 { + led-2 { label = "apq8016-sbc:green:user2"; function = LED_FUNCTION_DISK_ACTIVITY; color = <LED_COLOR_ID_GREEN>; @@ -109,7 +109,7 @@ default-state = "off"; }; - led@3 { + led-3 { label = "apq8016-sbc:green:user3"; function = LED_FUNCTION_DISK_ACTIVITY; color = <LED_COLOR_ID_GREEN>; @@ -118,7 +118,7 @@ default-state = "off"; }; - led@4 { + led-4 { label = "apq8016-sbc:green:user4"; color = <LED_COLOR_ID_GREEN>; gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; @@ -127,7 +127,7 @@ default-state = "off"; }; - led@5 { + led-5 { label = "apq8016-sbc:yellow:wlan"; function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_YELLOW>; @@ -136,7 +136,7 @@ default-state = "off"; }; - led@6 { + led-6 { label = "apq8016-sbc:blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = <LED_COLOR_ID_BLUE>; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 1b8379ba87f9..34e2f80514a3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -16,7 +16,7 @@ stdout-path = "serial0"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e5b89753aa5c..5d42de829e75 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -323,6 +323,13 @@ bias-disable; }; + serial_5_pins: serial5-state { + pins = "gpio9", "gpio16"; + function = "blsp5_uart"; + drive-strength = <8>; + bias-disable; + }; + i2c_0_pins: i2c-0-state { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; @@ -349,7 +356,7 @@ "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17"; + "gpio15", "gpio17"; function = "qpic"; drive-strength = <8>; bias-disable; @@ -471,6 +478,18 @@ status = "disabled"; }; + blsp1_uart6: serial@78b4000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b4000 0x200>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-0 = <&serial_5_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; @@ -864,6 +883,16 @@ "ahb", "axi_m_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@20000000 { @@ -929,6 +958,16 @@ "axi_m_sticky", "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 3a3e794c022f..7f0c2c1b8a94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -12,7 +12,7 @@ / { model = "Longcheer L8150"; - compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; + compatible = "longcheer,l8150", "qcom,msm8916"; chassis-type = "handset"; aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index ac527a3a0826..c11a845e91bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916"; chassis-type = "handset"; aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 2937495940ea..4bbbee80b5e4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -128,6 +128,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 3c49dac92d2d..c50f81a68897 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -23,6 +23,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index c2800ad2dd5b..5e933fb8b363 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -26,6 +26,30 @@ }; }; + clk_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&clk_pwm 0 100000>; + + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + + pinctrl-0 = <&backlight_en_default>; + pinctrl-names = "default"; + }; + + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&backlight_pwm_default>; + pinctrl-names = "default"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -66,6 +90,19 @@ pinctrl-0 = <&motor_en_default>; pinctrl-names = "default"; }; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp_a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; }; &blsp_i2c1 { @@ -94,6 +131,26 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen: touchscreen@20 { + compatible = "zinitix,bt541"; + reg = <0x20>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -166,6 +223,18 @@ }; &tlmm { + backlight_en_default: backlight-en-default-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default: backlight-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; @@ -200,4 +269,18 @@ drive-strength = <2>; bias-disable; }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 42843771ae2a..b438fa81886c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -5,6 +5,9 @@ /* SM5504 MUIC instead of SM5502 */ /delete-node/ &muic; +/* Touchscreen varies depending on model variant */ +/delete-node/ &touchscreen; + &blsp_i2c1 { muic: extcon@14 { compatible = "siliconmitus,sm5504-muic"; @@ -14,3 +17,12 @@ pinctrl-names = "default"; }; }; + +/* On rossa backlight is controlled with MIPI DCS commands */ +&clk_pwm { + status = "disabled"; +}; + +&clk_pwm_backlight { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index aa6c39482a2f..0c599e71a464 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -286,6 +286,12 @@ pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index f1011bb641c6..5d818fe057dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1323,6 +1323,20 @@ snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1601e46549e7..8d2cb6f41095 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1929,6 +1929,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@608000 { @@ -1982,6 +1992,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@610000 { @@ -2032,6 +2052,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 876c6921ddf0..d8cc0d729e99 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -98,30 +98,35 @@ gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>; pinctrl-names = "default"; - pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>; - button-vol-down { - label = "Volume Down"; - gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - wakeup-source; + button-camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA_FOCUS>; debounce-interval = <15>; }; button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA>; debounce-interval = <15>; }; - button-camera-focus { - label = "Camera Focus"; - gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_CAMERA_FOCUS>; + button-vol-down { + label = "Volume Down"; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + wakeup-source; + debounce-interval = <15>; + }; + + button-vol-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; debounce-interval = <15>; }; }; @@ -345,6 +350,14 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + }; + focus_n: focus-n-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; @@ -405,9 +418,33 @@ }; }; -&pm8998_resin { - linux,code = <KEY_VOLUMEUP>; +&pmi8998_lpg { + qcom,power-source = <1>; + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_RED>; + }; + }; }; &qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4dfe2d09ac28..d795b2bbe133 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -972,6 +972,16 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_phy: phy@1c06000 { diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 11158c2bd524..b20a639cddf3 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -71,8 +71,8 @@ }; pm6150_typec: typec@1500 { - compatible = "qcom,pm6150-typec, - qcom,pm8150b-typec"; + compatible = "qcom,pm6150-typec", + "qcom,pm8150b-typec"; reg = <0x1500>, <0x1700>; interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index d13a1ab7c20b..0fce45276e5c 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -118,6 +118,16 @@ status = "disabled"; }; + pm6150l_lpg: pwm { + compatible = "qcom,pm6150l-lpg", "qcom,pm8150l-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..106110a9f551 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -165,7 +165,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; }; @@ -694,10 +694,31 @@ clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; qcom,tcsr-reg = <&tcsr_regs 0xb244>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1380,6 +1401,27 @@ snps,usb3_lpm_capable; maximum-speed = "super-speed"; dr_mode = "otg"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -1858,7 +1900,7 @@ compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0x0 0x0f521000 0x0 0x1000>; reg-names = "freq-domain0"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&lmh_cluster 0>; interrupt-names = "dcvsh-irq-0"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; @@ -1866,6 +1908,18 @@ #freq-domain-cells = <1>; #clock-cells = <1>; }; + + lmh_cluster: lmh@f550800 { + compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; + reg = <0x0 0x0f550800 0x0 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; }; thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 4ff9fc24e50e..f3432701945f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -77,6 +77,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + connector@0 { compatible = "usb-c-connector"; reg = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index e4bfad50a669..47ca2d000341 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -9,7 +9,9 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7280.dtsi" #include "pm7250b.dtsi" @@ -35,10 +37,45 @@ serial0 = &uart5; }; + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8350c_pwm 3 65535>; + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pmic_lcd_bl_en>; + pinctrl-names = "default"; + }; + chosen { stdout-path = "serial0:115200n8"; }; + lcd_disp_bias: regulator-lcd-disp-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_disp_bias"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_disp_bias_en>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -158,129 +195,151 @@ vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -312,116 +371,217 @@ vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p62>; + avdd-supply = <&lcd_disp_bias>; + avee-supply = <&lcd_disp_bias>; + + backlight = <&pm8350c_pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + +&pm7250b_gpios { + lcd_disp_bias_en: lcd-disp-bias-en-state { + pins = "gpio2"; + function = "func1"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_gpios { + pmic_lcd_bl_en: pmic-lcd-bl-en-state { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + output-low; + power-source = <0>; + }; + + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + output-low; + power-source = <0>; + }; +}; + +&pm7325_gpios { + key_vol_up_default: key-vol-up-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; +}; + &pm8350c_pwm { + pinctrl-0 = <&pmic_lcd_bl_pwm>; + pinctrl-names = "default"; status = "okay"; multi-led { @@ -448,10 +608,39 @@ }; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/modem.mbn"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcm6490/wpss.mbn"; + status = "okay"; +}; + &sdhc_1 { non-removable; no-sd; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a05d0234f7fc..ac451f378056 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1516,6 +1516,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 97824c769ba3..a085ff5b5fb2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -17,7 +17,6 @@ #include "pmk8350.dtsi" /delete-node/ &ipa_fw_mem; -/delete-node/ &remoteproc_mpss; /delete-node/ &rmtfs_mem; /delete-node/ &adsp_mem; /delete-node/ &cdsp_mem; @@ -39,6 +38,20 @@ stdout-path = "serial0:115200n8"; }; + dp-connector { + compatible = "dp-connector"; + label = "DP"; + type = "mini"; + + hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -121,6 +134,49 @@ }; }; + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -153,129 +209,154 @@ vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7b_2p952: ldo7 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <3544000>; + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1304000>; + regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -304,109 +385,128 @@ vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; @@ -430,10 +530,102 @@ <GCC_WPSS_RSCP_CLK>; }; +&i2c1 { + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l18b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&dp_connector_in>; +}; + +&mdss_edp_phy { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcs6490/modem.mdt"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcs6490/wpss.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ @@ -449,7 +641,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -464,9 +665,49 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p912>; + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp_out>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + status = "okay"; }; &wifi { memory-region = <&wlan_fw_mem>; }; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&edp_hot_plug_det { + function = "gpio"; + bias-disable; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 832f472c4b7a..f2a5e2e40461 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -177,7 +177,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 6e9dd0312adc..bb5191422660 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -262,6 +262,46 @@ status = "okay"; }; +&pm4125_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm4125_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pm4125_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -535,14 +575,8 @@ status = "okay"; }; -&usb_qmpphy { - vdda-phy-supply = <&pm4125_l12>; - vdda-pll-supply = <&pm4125_l13>; - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "host"; +&usb_dwc3_hs { + remote-endpoint = <&pm4125_hs_in>; }; &usb_hsphy { @@ -552,12 +586,23 @@ status = "okay"; }; +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + status = "okay"; +}; + +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; vdd-1.3-rfa-supply = <&pm4125_l10>; vdd-3.3-ch0-supply = <&pm4125_l22>; qcom,ath10k-calibration-variant = "Thundercomm_RB1"; + firmware-name = "qcm2290"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 696d6d43c56b..2c39bb1b97db 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -678,6 +678,7 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; qcom,ath10k-calibration-variant = "Thundercomm_RB2"; + firmware-name = "qrb4210"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 5e4287f8c8cd..4f805c47fbfd 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -283,7 +283,7 @@ vreg_l13c_2p96: ldo13 { regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 231cea1f0fa8..31de73594839 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3677,6 +3677,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c04000 { @@ -3777,6 +3787,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c14000 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f3a6da8b2890..8513be297120 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -944,6 +944,8 @@ ap_spi_fp: &spi10 { vddrf-supply = <&pp1300_l2c>; vddch0-supply = <&pp3300_l10c>; max-speed = <3200000>; + + qcom,local-bd-address-broken; }; }; @@ -1165,6 +1167,7 @@ ap_spi_fp: &spi10 { }; &pm6150l_gpios { + status = "disabled"; /* No GPIOs are consumed or configured */ gpio-line-names = "AP_SUSPEND", "", "", diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2b481e20ae38..4774a859bd7e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1585,9 +1585,12 @@ compatible = "qcom,sc7180-qmp-ufs-phy", "qcom,sm7150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2309,6 +2312,7 @@ compatible = "qcom,sc7180-dcc", "qcom,dcc"; reg = <0x0 0x010a2000 0x0 0x1000>, <0x0 0x010ae000 0x0 0x2000>; + status = "disabled"; }; stm@6002000 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7e7f0f0fb41b..cea294a4ecfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2273,6 +2273,16 @@ <0x100 &apps_smmu 0x1c81 0x1>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2352,6 +2362,8 @@ <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -2374,6 +2386,13 @@ status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sc7280-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; @@ -4458,6 +4477,11 @@ opp-hz = /bits/ 64 <506666667>; required-opps = <&rpmhpd_opp_nom>; }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 0c22f3efec20..6af99116c715 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -51,6 +51,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>, + <&tlmm 58 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; @@ -329,12 +331,18 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; }; vreg_l10e_2p9: ldo10 { regulator-min-microvolt = <2904000>; regulator-max-microvolt = <2904000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; }; vreg_l16e_3p0: ldo16 { @@ -350,49 +358,58 @@ zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; }; &i2c1 { clock-frequency = <100000>; - pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-0 = <&i2c1_active>; pinctrl-names = "default"; status = "okay"; - hid@10 { + touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; }; }; &i2c7 { - clock-frequency = <100000>; + clock-frequency = <1000000>; - pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-0 = <&i2c7_active>; pinctrl-names = "default"; status = "okay"; - hid@5 { + keyboard@5 { compatible = "hid-over-i2c"; reg = <0x5>; hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kb_int_default>; + pinctrl-names = "default"; }; - hid@2c { + touchpad@2c { compatible = "hid-over-i2c"; reg = <0x2c>; hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tp_int_default>; + pinctrl-names = "default"; }; }; @@ -669,14 +686,6 @@ drive-strength = <2>; }; - i2c1_hid_active: i2c1-hid-active-state { - pins = "gpio122"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; - i2c7_active: i2c7-active-state { pins = "gpio98", "gpio99"; function = "qup7"; @@ -685,8 +694,8 @@ drive-strength = <2>; }; - i2c7_hid_active: i2c7-hid-active-state { - pins = "gpio37", "gpio24"; + kb_int_default: kb-int-default-state { + pins = "gpio37"; function = "gpio"; bias-pull-up; @@ -718,6 +727,22 @@ }; }; + tp_int_default: tp-int-default-state { + pins = "gpio24"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio122"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + usbprim_sbu_default: usbprim-sbu-state { oe-n-pins { pins = "gpio152"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 32afc78d5b76..6d5878f3b26d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1777,6 +1777,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1888,6 +1898,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1c0c000 { @@ -2000,6 +2020,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c16000 { @@ -2112,6 +2142,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c1c000 { @@ -2225,7 +2265,6 @@ gpu: gpu@2c00000 { compatible = "qcom,adreno-680.1", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; @@ -2805,7 +2844,7 @@ power-domains = <&rpmhpd SC8180X_MMCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -2878,7 +2917,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -2964,7 +3003,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, @@ -3030,7 +3069,8 @@ reg = <0 0xae90000 0 0x200>, <0 0xae90200 0 0x200>, <0 0xae90400 0 0x600>, - <0 0xae90a00 0 0x400>; + <0 0xae90a00 0 0x400>, + <0 0xae91000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -3106,7 +3146,8 @@ reg = <0 0xae98000 0 0x200>, <0 0xae98200 0 0x200>, <0 0xae98400 0 0x600>, - <0 0xae98a00 0 0x400>; + <0 0xae98a00 0 0x400>, + <0 0xae99000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <13>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 15ae94c1602d..f325066e24d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -100,6 +100,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; @@ -731,22 +733,14 @@ pinctrl-0 = <&pcie4_default>; status = "okay"; +}; - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - bus-range = <0x01 0xff>; - - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; - qcom,ath11k-calibration-variant = "LE_X13S"; - }; + qcom,ath11k-calibration-variant = "LE_X13S"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a5b194813079..0403811264d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -50,7 +50,8 @@ reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -77,7 +78,8 @@ reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -99,7 +101,8 @@ reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -121,7 +124,8 @@ reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -144,6 +148,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -166,6 +171,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -188,6 +194,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -210,6 +217,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; @@ -300,6 +308,7 @@ scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -862,6 +871,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@18b { + reg = <0x18b 0x1>; + bits = <5 3>; + }; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; @@ -1731,6 +1752,8 @@ linux,pci-domain = <6>; num-lanes = <1>; + msi-map = <0x0 &its 0xe0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -1774,11 +1797,22 @@ reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1831,6 +1865,8 @@ linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &its 0xd0000 0x10000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, @@ -1872,11 +1908,22 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -1929,6 +1976,8 @@ linux,pci-domain = <4>; num-lanes = <4>; + msi-map = <0x0 &its 0xc0000 0x10000>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, @@ -1970,11 +2019,22 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2030,6 +2090,8 @@ linux,pci-domain = <3>; num-lanes = <2>; + msi-map = <0x0 &its 0xb0000 0x10000>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, @@ -2071,11 +2133,22 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie2b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 { @@ -2128,6 +2201,8 @@ linux,pci-domain = <2>; num-lanes = <4>; + msi-map = <0x0 &its 0xa0000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, @@ -2169,11 +2244,22 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie2a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2a_phy: phy@1c24000 { @@ -3361,10 +3447,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -3421,10 +3509,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -4448,6 +4538,11 @@ #thermal-sensor-cells = <1>; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0 0x0c264000 0 0x4>; + }; + tsens1: thermal-sensor@c265000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ @@ -4799,7 +4894,7 @@ #size-cells = <2>; ranges; - msi-controller@17a40000 { + its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; @@ -4966,6 +5061,11 @@ <0 0x18592000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 819a5f8825e7..a4b722e0fc1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -90,6 +90,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; key-camera-focus { label = "Camera Focus"; @@ -645,6 +647,13 @@ bias-disable; }; + gpio_keys_default: gpio-keys-default-state { + pins = "gpio64", "gpio113"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + imx300_vana_default: imx300-vana-default-state { pins = "gpio50"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 057579ae3013..e2708c74e95a 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -116,6 +116,33 @@ }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + port { + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1000000>; + status = "okay"; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; @@ -240,8 +267,8 @@ status = "okay"; }; -&usb3_dwc3 { - dr_mode = "peripheral"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &wcnss { diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 32a7bd59e1ec..176b0119fe6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -441,6 +441,47 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e3fa7-ams559nk06"; + reg = <0>; + + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default>; + + power-supply = <&vreg_l6b_3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm660l_gpios { vol_up_pin: vol-up-state { pins = "gpio7"; @@ -481,6 +522,29 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + panel_default: panel-default-state { + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mode-pins { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + touchscreen_default: ts-default-state { ts-reset-pins { pins = "gpio99"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 1f517328199b..9a6d3d0c0ee4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -195,6 +195,12 @@ gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; enable-active-high; + /* + * FIXME: this regulator is responsible for VBUS on the left USB + * port. Keep it always on until we can correctly model this + * relationship. + */ + regulator-always-on; pinctrl-names = "default"; pinctrl-0 = <&pcie0_pwren_state>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f20be99ee7e..10de2bd46ffc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2375,6 +2375,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2479,6 +2489,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0a000 { diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7dbdf8ca6de6..da1704061d58 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -224,7 +224,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; @@ -411,7 +411,7 @@ hwlocks = <&tcsr_mutex 3>; }; - soc: soc { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 24bcec3366ef..ad704f4e147c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1205,6 +1205,37 @@ status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm6350-ipa"; @@ -2033,6 +2064,14 @@ remote-endpoint = <&mdss_dsi0_in>; }; }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2070,6 +2109,86 @@ }; }; + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index de670b407ef1..6cb6f503fdac 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -609,6 +609,11 @@ firmware-name = "qcom/sm8150/cdsp.mbn"; }; +&remoteproc_mpss { + firmware-name = "qcom/sm8150/modem.mbn"; + status = "okay"; +}; + &remoteproc_slpi { status = "okay"; @@ -713,3 +718,14 @@ &usb_2_dwc3 { dr_mode = "host"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l1a_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + + qcom,ath10k-calibration-variant = "Qualcomm_sm8150hdk"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a35c0852b5a1..ff22e4346660 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1901,6 +1901,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2011,6 +2021,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 6f54f50a70b0..41f117474872 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -636,7 +636,8 @@ connector { compatible = "usb-c-connector"; - power-role = "source"; + op-sink-microwatt = <10000000>; + power-role = "dual"; data-role = "dual"; self-powered; @@ -645,6 +646,12 @@ PDO_FIXED_USB_COMM | PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 3000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_USB_COMM | + PDO_FIXED_DATA_SWAP) + PDO_VAR(5000, 12000, 5000)>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -661,6 +668,8 @@ }; &pm8150b_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 39bd8f0eba1e..fe5485256b22 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2203,6 +2203,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2318,6 +2328,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2433,6 +2453,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c16000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index b43d264ed42b..4c25ab2f5670 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -42,6 +42,7 @@ compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a5e7dbbd8c6c..f7c4700f00c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> @@ -1572,6 +1573,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1669,6 +1680,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -1730,6 +1751,11 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; freq-table-hz = <75000000 300000000>, <0 0>, diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 0786cff07b89..3be46b56c723 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -95,6 +95,7 @@ compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index c7d05945aa51..7b62ead68e77 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -467,6 +467,14 @@ vdda-pll-supply = <&vreg_l5b_0p88>; vdda18-supply = <&vreg_l1c_1p8>; vdda33-supply = <&vreg_l2b_3p07>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,pre-emphasis-amplitude-bp = <40000>; + qcom,pre-emphasis-duration-bp = <20000>; + qcom,hs-amplitude-bp = <2000>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-rise-fall-time-bp = <(-4100)>; }; &usb_1_qmpphy { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..7f32035aab7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1850,6 +1850,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1971,6 +1981,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2363,6 +2383,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2665,6 +2686,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2731,6 +2753,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts new file mode 100644 index 000000000000..85e0d3d66e16 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/cs35l45.h> +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +/* TODO: Only one SID of PMR735D seems accessible? */ + +/delete-node/ &hwfence_shbuf; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; +/ { + model = "Sony Xperia 1 V"; + compatible = "sony,pdx234", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c16 = &i2c_hub_2; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8550b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + mpss_mem: mpss-region@89800000 { + reg = <0x0 0x89800000 0x0 0x10800000>; + no-map; + }; + + splash@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0x0 0xe6440000 0x0 0x2dd000>; + no-map; + }; + + rmtfs_mem: memory@f8b00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8b00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + ramoops@ffd00000 { + compatible = "ramoops"; + reg = <0x0 0xffd00000 0x0 0xc0000>; + console-size = <0x40000>; + record-size = <0x1000>; + pmsg-size = <0x40000>; + ecc-size = <16>; + }; + + rdtag-store-region@ffdc0000 { + reg = <0x0 0xffdc0000 0x0 0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + pm8550_bob1: bob1 { + regulator-name = "pm8550_bob1"; + regulator-min-microvolt = <3416000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* TODO: bob2 @ 2.704-3.008V doesn't fall into the vreg driver constraints */ + + pm8550_l1: ldo1 { + regulator-name = "pm8550_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l2: ldo2 { + regulator-name = "pm8550_l2"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L4 exists in cmd-db, but the board seems to crash on access */ + + pm8550_l5: ldo5 { + regulator-name = "pm8550_l5"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l6: ldo6 { + regulator-name = "pm8550_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l7: ldo7 { + regulator-name = "pm8550_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l8: ldo8 { + regulator-name = "pm8550_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l9: ldo9 { + regulator-name = "pm8550_l9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l10: ldo10 { + regulator-name = "pm8550_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l11: ldo11 { + regulator-name = "pm8550_l11"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l12: ldo12 { + regulator-name = "pm8550_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l13: ldo13 { + regulator-name = "pm8550_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l14: ldo14 { + regulator-name = "pm8550_l14"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l15: ldo15 { + regulator-name = "pm8550_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l16: ldo16 { + regulator-name = "pm8550_l16"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550_l17: ldo17 { + regulator-name = "pm8550_l17"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + pm8550vs_0_l1: ldo1 { + regulator-name = "pm8550vs_0_l1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_0_l3: ldo3 { + regulator-name = "pm8550vs_0_l3"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + pm8550vs_1_l1: ldo1 { + regulator-name = "pm8550vs_1_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L3 exists in cmd-db, but the board seems to crash on access */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + pm8550vs_2_s4: smps4 { + regulator-name = "pm8550vs_2_s4"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_2_s5: smps5 { + regulator-name = "pm8550vs_2_s5"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_2_l1: ldo1 { + regulator-name = "pm8550vs_2_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_2_l2: ldo2 { + regulator-name = "pm8550vs_2_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_2_l3: ldo3 { + regulator-name = "pm8550vs_2_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + pm8550ve_s4: smps4 { + regulator-name = "pm8550ve_s4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550ve_l1: ldo1 { + regulator-name = "pm8550ve_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550ve_l2: ldo2 { + regulator-name = "pm8550ve_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550ve_l3: ldo3 { + regulator-name = "pm8550ve_l3"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + pm8550vs_3_s1: smps1 { + regulator-name = "pm8550vs_3_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_s2: smps2 { + regulator-name = "pm8550vs_3_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_s3: smps3 { + regulator-name = "pm8550vs_3_s3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_s4: smps4 { + regulator-name = "pm8550vs_3_s4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_s5: smps5 { + regulator-name = "pm8550vs_3_s5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_s6: smps6 { + regulator-name = "pm8550vs_3_s6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_l1: ldo1 { + regulator-name = "pm8550vs_3_l1"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_l2: ldo2 { + regulator-name = "pm8550vs_3_l2"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8550vs_3_l3: ldo3 { + regulator-name = "pm8550vs_3_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* TODO: Unknown PMIC @ k, l, PM8010 @ m, n */ +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c_hub_2 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <1000000>; + status = "okay"; + + /* NXP NFC @ 28 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* LX Semi SW82907 touchscreen @ 28 */ +}; + +&i2c10 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + +&i2c11 { + clock-frequency = <1000000>; + status = "okay"; + + cs35l41_l: speaker-amp@30 { + compatible = "cirrus,cs35l45"; + reg = <0x30>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; + + cs35l41_r: speaker-amp@31 { + compatible = "cirrus,cs35l45"; + reg = <0x31>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&pm8550vs_2_l1>; + vdda-pll-supply = <&pm8550vs_2_l3>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + vol_down_n: volume-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio12"; + function = "normal"; + power-source = <1>; + bias-pull-down; + output-disable; + input-enable; + }; +}; + +&pm8550b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550vs_g_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio4"; + function = "normal"; + power-source = <0x01>; + drive-push-pull; + output-low; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xf>; + qcom,tune-usb2-preem = /bits/ 8 <0x7>; + vdd18-supply = <&pm8550_l15>; + vdd3-supply = <&pm8550_l5>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/Sony/yodo/adsp.mbn", + "qcom/sm8550/Sony/yodo/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/Sony/yodo/cdsp.mbn", + "qcom/sm8550/Sony/yodo/cdsp_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&pm8550_l9>; + vqmmc-supply = <&pm8550_l8>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&pm8550vs_2_l1>; + vdda12-supply = <&pm8550vs_2_l3>; + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&pm8550vs_2_l3>; + vdda-pll-supply = <&pm8550ve_l3>; + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..171fdb213cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1770,6 +1774,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1883,6 +1897,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -3227,12 +3251,21 @@ reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x40 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + dma-coherent; ports { #address-cells = <1>; @@ -3968,6 +4001,7 @@ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; }; intc: interrupt-controller@17100000 { @@ -4316,6 +4350,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -4454,6 +4489,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 4450273f9667..d04ceaa73c2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -641,10 +641,6 @@ status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..4e94f7fe4d2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21"; @@ -827,10 +835,6 @@ remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ba72d8f38420..434ad2f12332 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -485,9 +485,9 @@ no-map; }; - /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { - reg = <0 0x81c80000 0 0x74000>; + reg = <0 0x81c80000 0 0x75000>; no-map; }; @@ -2294,6 +2294,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2422,6 +2432,16 @@ <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2591,6 +2611,143 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + }; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + }; + + opp-770000000 { + opp-hz = /bits/ 64 <770000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-834000000 { + opp-hz = /bits/ 64 <834000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2604,6 +2761,50 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; @@ -3584,14 +3785,16 @@ compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4845,6 +5048,8 @@ label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; @@ -5002,6 +5207,8 @@ label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; @@ -5084,6 +5291,38 @@ <&apps_smmu 0x19c8 0x0>; dma-coherent; }; + + /* note: secure cb9 in downstream */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c0c 0x20>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + + iommus = <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 6a0a54532e5f..c5c2895b37c7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -9,6 +9,7 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; @@ -598,8 +599,6 @@ compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -619,6 +618,9 @@ port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; @@ -680,16 +682,32 @@ status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &swr0 { status = "okay"; + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Left Woofer */ left_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -700,8 +718,7 @@ left_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in left_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -734,13 +751,14 @@ &swr3 { status = "okay"; + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Right Woofer */ right_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_23_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -751,8 +769,7 @@ right_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in right_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -817,6 +834,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -837,6 +856,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -857,6 +878,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi new file mode 100644 index 000000000000..04301f772fbd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { +}; + +&spmi_bus1 { + smb2360_0: pmic@7 { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_0_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_1: pmic@a { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_1_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_2: pmic@b { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index e76d29053d79..2061fbe7b75a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -9,6 +9,7 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 QCP"; @@ -409,8 +410,6 @@ compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -430,6 +429,9 @@ port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; @@ -491,6 +493,21 @@ status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -513,6 +530,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -533,6 +552,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -553,6 +574,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 8e517f76189e..a8dfd8146706 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3088,7 +3088,7 @@ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; @@ -4095,8 +4095,6 @@ mdss_dp3_in: endpoint { remote-endpoint = <&mdss_intf5_out>; - - link-frequencies = /bits/ 64 <8100000000>; }; }; @@ -4221,6 +4219,48 @@ #clock-cells = <0>; }; + spmi: arbiter@c400000 { + compatible = "qcom,x1e80100-spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x400000>, + <0 0x0c440000 0 0x80000>; + reg-names = "core", "chnls", "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c432000 { + reg = <0 0x0c432000 0 0x4000>, + <0 0x0c4d0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 39aefe66a794..ba50e292bdbb 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -48,7 +48,7 @@ clock-output-names = "osc27M"; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index a3c10ceeb586..e8af39193e75 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -47,7 +47,7 @@ clock-output-names = "osc27M"; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 34802cc62983..3a7f6e35b7f7 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -109,7 +109,7 @@ }; arm_pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>; @@ -127,7 +127,7 @@ #clock-cells = <0>; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5f3e0e61d78d..fbd214a1a638 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -62,6 +62,9 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb +dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtbo +r8a77970-eagle-function-expansion-dtbs := r8a77970-eagle.dtb r8a77970-eagle-function-expansion.dtbo +dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso new file mode 100644 index 000000000000..3aa243c5f04c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Eagle V3M Function expansion board. + * + * Copyright (C) 2024 Niklas Söderlund <niklas.soderlund@ragnatech.se> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + /* CN4 */ + /* Eagle: SW18 set to OFF */ + cvbs-in-cn4 { + compatible = "composite-video-connector"; + label = "CVBS IN CN4"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + /* CN2 */ + /* Eagle: SW35 set 5, 6 and 8 to OFF */ + hdmi-in-cn2 { + compatible = "hdmi-connector"; + label = "HDMI IN CN2"; + type = "a"; + + port { + hdmi_in_con2: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + + /* CN3 */ + /* Eagle: SW18 set to OFF */ + hdmi-in-cn3 { + compatible = "hdmi-connector"; + label = "HDMI IN CN3"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; +}; + +/* Disconnect MAX9286 GMSL I2C. */ +&i2c3 { + status = "disabled"; +}; + +/* Connect expansion board I2C. */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + gpio@27 { + compatible = "onnn,pca9654"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + + vin0_adv7612_en { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "VIN0_ADV7612_ENn"; + }; + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>, <0x50>, <0x52>, <0x54>, <0x56>, <0x58>; + reg-names = "main", "afe", "rep", "edid", "hdmi", "cp"; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_in_con2>; + }; + }; + + port@2 { + reg = <2>; + + adv7612_out: endpoint { + remote-endpoint = <&vin0_in>; + }; + }; + }; + }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; + interrupt-parent = <&gpio3>; + interrupts = <03 IRQ_TYPE_LEVEL_LOW>, <04 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + +}; + +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + +&pfc { + vin0_pins_parallel: vin0 { + groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb"; + function = "vin0"; + }; +}; + +&vin0 { + status = "okay"; + + pinctrl-0 = <&vin0_pins_parallel>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin0_in: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + remote-endpoint = <&adv7612_out>; + }; + }; + }; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index abfda5c6ca16..bc65a7b4d999 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -14,9 +14,9 @@ compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; aliases { - serial0 = &hscif0; - serial1 = &hscif1; - eth0 = &rswitch; + serial0 = &hscif0; + serial1 = &hscif1; + ethernet0 = &rswitch; }; chosen { diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index bc8616a56c03..cfbe8c8680cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -18,11 +18,12 @@ aliases { serial0 = &hscif0; + serial1 = &hscif2; ethernet0 = &avb0; }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:921600n8"; }; @@ -90,6 +91,14 @@ status = "okay"; }; +&hscif2 { + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -144,7 +153,7 @@ }; &pfc { - pinctrl-0 = <&scif_clk_pins>; + pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>; pinctrl-names = "default"; avb0_pins: avb0 { @@ -170,6 +179,11 @@ function = "hscif0"; }; + hscif2_pins: hscif2 { + groups = "hscif2_data", "hscif2_ctrl"; + function = "hscif2"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; @@ -190,6 +204,11 @@ groups = "scif_clk"; function = "scif_clk"; }; + + scif_clk2_pins: scif-clk2 { + groups = "scif_clk2"; + function = "scif_clk2"; + }; }; &rpc { @@ -228,3 +247,7 @@ &scif_clk { clock-frequency = <24000000>; }; + +&scif_clk2 { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 11885729181b..6d791024cabe 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -144,13 +144,19 @@ method = "smc"; }; - /* External SCIF clock - to be overridden by boards that provide it */ + /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; + scif_clk2: scif-clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -297,6 +303,76 @@ resets = <&cpg 917>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779h0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779h0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; @@ -318,6 +394,106 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779h0-thermal"; + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 611>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; @@ -403,6 +579,57 @@ status = "disabled"; }; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk2>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779h0", "renesas,etheravb-rcar-gen4"; @@ -446,6 +673,7 @@ phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; + iommus = <&ipmmu_hc 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -547,6 +775,170 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk2>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac1 0x45>, <&dmac1 0x44>, + <&dmac2 0x45>, <&dmac2 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac1 0x47>, <&dmac1 0x46>, + <&dmac2 0x47>, <&dmac2 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + dmas = <&dmac1 0x49>, <&dmac1 0x48>, + <&dmac2 0x49>, <&dmac2 0x48>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + dmas = <&dmac1 0x4b>, <&dmac1 0x4a>, + <&dmac2 0x4b>, <&dmac2 0x4a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; @@ -580,6 +972,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac2: dma-controller@e7351000 { @@ -605,6 +1005,10 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <8>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>; }; mmc0: mmc@ee140000 { @@ -618,6 +1022,7 @@ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; status = "disabled"; }; @@ -637,6 +1042,106 @@ status = "disabled"; }; + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_ir: iommu@eed80000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vc: iommu@eedc0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeedc0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_3dg: iommu@eee00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@eee80000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@eeec0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeeec0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: iommu@eef00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -653,6 +1158,36 @@ }; }; + thermal-zones { + sensor_thermal_cr52: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ca76: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8721f4c9fa0f..d2365def1059 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -598,6 +598,7 @@ gpio-ranges = <&pinctrl 0 0 152>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&irqc>; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 964b0a475eee..165bfcfef3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -54,10 +54,6 @@ }; }; -&pinctrl { - interrupt-parent = <&irqc>; -}; - &soc { interrupt-parent = <&gic>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index de590996e10a..433860987f73 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +#include <dt-bindings/gpio/gpio.h> #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" @@ -23,6 +24,63 @@ &i2c0 { clock-frequency = <400000>; + da9062: pmic@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + gpio-controller; + #gpio-cells = <2>; + + gpio { + compatible = "dlg,da9062-gpio"; + }; + + onkey { + compatible = "dlg,da9062-onkey"; + }; + + pmic-good-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PMIC_PGOOD"; + }; + + rtc { + compatible = "dlg,da9062-rtc"; + }; + + sd0-pwr-sel-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + line-name = "SD0_PWR_SEL"; + }; + + sd1-pwr-sel-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "SD1_PWR_SEL"; + }; + + sw-et0-en-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "SW_ET0_EN#"; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + status = "disabled"; + }; + }; + versa3: clock-generator@68 { compatible = "renesas,5p35023"; reg = <0x68>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..8a3d302f1535 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -25,7 +25,7 @@ * SW_OFF - SD2 is connected to SoC * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ -#define SW_CONFIG2 SW_ON +#define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON / { @@ -36,8 +36,8 @@ #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; #else - eth0 = ð0; - eth1 = ð1; + ethernet0 = ð0; + ethernet1 = ð1; #endif }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index b48b98c13705..e5c0dbf794ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index dcee2e28916f..23ae2d9de382 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -21,7 +21,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index b16b7ca02379..7f14206d53c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -21,7 +21,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 62af0cb94839..734f87db4d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -141,7 +141,7 @@ }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index da44a15a8adf..a251c4343548 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -111,7 +111,7 @@ &i2c0 { status = "okay"; - tas5707a@1d { + audio-codec@1d { compatible = "ti,tas5711"; reg = <0x1d>; reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; @@ -124,7 +124,7 @@ PVDD_C-supply = <&_vcc_reg>; PVDD_D-supply = <&_vcc_reg>; - port@0 { + port { tas_speaker: endpoint { dai-format = "i2s"; remote-endpoint = <&i2s_hpcmout1>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index a01579cb3b79..79f6db2455c1 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -111,7 +111,7 @@ &i2c0 { status = "okay"; - tas5707@1b { + audio-codec@1b { compatible = "ti,tas5711"; reg = <0x1b>; reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; @@ -124,7 +124,7 @@ PVDD_C-supply = <&_vcc_reg>; PVDD_D-supply = <&_vcc_reg>; - port@0 { + port { tas_speaker: endpoint { dai-format = "i2s"; remote-endpoint = <&i2s_hpcmout1>; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index e27eb3ed1d47..31952d361a8a 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -113,7 +113,7 @@ }; }; - idle-states{ + idle-states { entry-method = "psci"; CORE_PD: core_pd { @@ -135,18 +135,6 @@ }; }; - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) - | IRQ_TYPE_LEVEL_HIGH)>; - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -165,7 +153,7 @@ }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, @@ -185,6 +173,18 @@ }; soc { + gic: interrupt-controller@12001000 { + compatible = "arm,gic-400"; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x2000>, + <0 0x12004000 0 0x2000>, + <0 0x12006000 0 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) + | IRQ_TYPE_LEVEL_HIGH)>; + }; + pmu_gate: pmu-gate { compatible = "sprd,sc9860-pmu-gate"; sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ @@ -207,7 +207,7 @@ #clock-cells = <1>; }; - aon_prediv: aon-prediv { + aon_prediv: aon-prediv@402d0000 { compatible = "sprd,sc9860-aon-prediv"; reg = <0 0x402d0000 0 0x400>; clocks = <&ext_26m>, <&pll 0>, @@ -684,33 +684,5 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - - key-volumedown { - label = "Volume Down Key"; - linux,code = <KEY_VOLUMEDOWN>; - gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; - debounce-interval = <2>; - wakeup-source; - }; - - key-volumeup { - label = "Volume Up Key"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - - key-power { - label = "Power Key"; - linux,code = <KEY_POWER>; - gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 22d81ace740a..53e5b77d70b5 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -134,7 +134,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi index 206a4afdab1c..9b4ee0bdd69f 100644 --- a/arch/arm64/boot/dts/sprd/sharkl3.dtsi +++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi @@ -24,7 +24,7 @@ #size-cells = <1>; ranges = <0 0 0x20e00000 0x4000>; - apahb_gate: apahb-gate { + apahb_gate: apahb-gate@0 { compatible = "sprd,sc9863a-apahb-gate"; reg = <0x0 0x1020>; #clock-cells = <1>; @@ -39,7 +39,7 @@ #size-cells = <1>; ranges = <0 0 0x402b0000 0x4000>; - pmu_gate: pmu-gate { + pmu_gate: pmu-gate@0 { compatible = "sprd,sc9863a-pmu-gate"; reg = <0 0x1200>; clocks = <&ext_26m>; @@ -56,7 +56,7 @@ #size-cells = <1>; ranges = <0 0 0x402e0000 0x4000>; - aonapb_gate: aonapb-gate { + aonapb_gate: aonapb-gate@0 { compatible = "sprd,sc9863a-aonapb-gate"; reg = <0 0x1100>; #clock-cells = <1>; @@ -71,7 +71,7 @@ #size-cells = <1>; ranges = <0 0 0x40353000 0x3000>; - pll: pll { + pll: pll@0 { compatible = "sprd,sc9863a-pll"; reg = <0 0x100>; clocks = <&ext_26m>; @@ -88,7 +88,7 @@ #size-cells = <1>; ranges = <0 0 0x40359000 0x3000>; - mpll: mpll { + mpll: mpll@0 { compatible = "sprd,sc9863a-mpll"; reg = <0 0x100>; #clock-cells = <1>; @@ -103,7 +103,7 @@ #size-cells = <1>; ranges = <0 0 0x4035c000 0x3000>; - rpll: rpll { + rpll: rpll@0 { compatible = "sprd,sc9863a-rpll"; reg = <0 0x100>; clocks = <&ext_26m>; @@ -120,7 +120,7 @@ #size-cells = <1>; ranges = <0 0 0x40363000 0x3000>; - dpll: dpll { + dpll: dpll@0 { compatible = "sprd,sc9863a-dpll"; reg = <0 0x100>; #clock-cells = <1>; @@ -135,7 +135,7 @@ #size-cells = <1>; ranges = <0 0 0x60800000 0x3000>; - mm_gate: mm-gate { + mm_gate: mm-gate@0 { compatible = "sprd,sc9863a-mm-gate"; reg = <0 0x1100>; #clock-cells = <1>; @@ -150,7 +150,7 @@ #size-cells = <1>; ranges = <0 0 0x71300000 0x4000>; - apapb_gate: apapb-gate { + apapb_gate: apapb-gate@0 { compatible = "sprd,sc9863a-apapb-gate"; reg = <0 0x1000>; clocks = <&ext_26m>; diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts index 6b95fd94cee3..1ce3cbbd9668 100644 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts @@ -24,7 +24,7 @@ spi0 = &adi_bus; }; - memory{ + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x60000000>, <0x1 0x80000000 0 0x60000000>; @@ -34,6 +34,34 @@ stdout-path = "serial1:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + key-volumedown { + label = "Volume Down Key"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; + debounce-interval = <2>; + wakeup-source; + }; + + key-volumeup { + label = "Volume Up Key"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; + debounce-interval = <2>; + wakeup-source; + }; + + key-power { + label = "Power Key"; + linux,code = <KEY_POWER>; + gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; + debounce-interval = <2>; + wakeup-source; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index fece49704b5c..7068bfd2f4c3 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -64,7 +64,7 @@ reg = <0 0x70b00000 0 0x40000>; }; - ap-apb { + ap-apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 66791a974f8f..7a82896dcbf6 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,23 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + i2c2_pins_a: i2c2-0 { + pins { + pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */ + <STM32_PINMUX('B', 4, AF9)>; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_a: i2c2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* I2C2_SCL */ + <STM32_PINMUX('B', 4, ANALOG)>; /* I2C2_SDA */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */ @@ -60,6 +77,28 @@ }; }; + spi3_pins_a: spi3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 7, AF1)>, /* SPI3_SCK */ + <STM32_PINMUX('B', 8, AF1)>; /* SPI3_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 10, AF1)>; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 7, ANALOG)>, /* SPI3_SCK */ + <STM32_PINMUX('B', 8, ANALOG)>, /* SPI3_MOSI */ + <STM32_PINMUX('B', 10, ANALOG)>; /* SPI3_MISO */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ @@ -90,3 +129,46 @@ }; }; }; + +&pinctrl_z { + i2c8_pins_a: i2c8-0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C8_SCL */ + <STM32_PINMUX('Z', 3, AF8)>; /* I2C8_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c8_sleep_pins_a: i2c8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C8_SCL */ + <STM32_PINMUX('Z', 3, ANALOG)>; /* I2C8_SDA */ + }; + }; +}; + +&pinctrl_z { + spi8_pins_a: spi8-0 { + pins1 { + pinmux = <STM32_PINMUX('Z', 2, AF3)>, /* SPI8_SCK */ + <STM32_PINMUX('Z', 0, AF3)>; /* SPI8_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */ + bias-disable; + }; + }; + + spi8_sleep_pins_a: spi8-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('Z', 2, ANALOG)>, /* SPI8_SCK */ + <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI8_MOSI */ + <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5dd4f3580a60..4b48e4ed2d28 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -3,7 +3,9 @@ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ +#include <dt-bindings/clock/st,stm32mp25-rcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/st,stm32mp25-rcc.h> / { #address-cells = <2>; @@ -35,34 +37,16 @@ }; clocks { - ck_flexgen_08: ck-flexgen-08 { + clk_dsi_txbyte: txbyteclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <100000000>; + clock-frequency = <0>; }; - ck_flexgen_51: ck-flexgen-51 { + clk_rcbsec: clk-rcbsec { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_ls_mcu: ck-icn-ls-mcu { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_vdec: ck-icn-p-vdec { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_venc: ck-icn-p-venc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; + clock-frequency = <64000000>; }; }; @@ -109,10 +93,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&intc>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; always-on; }; @@ -123,18 +107,220 @@ interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; + spi2: spi@400b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ck_flexgen_08>; + clocks = <&rcc CK_KER_USART2>; + access-controllers = <&rifsc 32>; + status = "disabled"; + }; + + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c3: i2c@40140000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40140000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C3>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 43>; + status = "disabled"; + }; + + i2c4: i2c@40150000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40150000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C4>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 44>; + status = "disabled"; + }; + + i2c5: i2c@40160000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40160000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C5>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 45>; + status = "disabled"; + }; + + i2c6: i2c@40170000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40170000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C6>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 46>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + spi1: spi@40230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + spi6: spi@40350000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40350000 0x400>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI6>; + resets = <&rcc SPI6_R>; + access-controllers = <&rifsc 27>; + status = "disabled"; + }; + + spi7: spi@40360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40360000 0x400>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI7>; + resets = <&rcc SPI7_R>; + access-controllers = <&rifsc 28>; + status = "disabled"; + }; + + spi8: spi@46020000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 48>; status = "disabled"; }; @@ -143,11 +329,13 @@ arm,primecell-periphid = <0x00353180>; reg = <0x48220000 0x400>, <0x44230400 0x8>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ck_flexgen_51>; + clocks = <&rcc CK_KER_SDMMC1 >; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&rifsc 76>; status = "disabled"; }; }; @@ -168,6 +356,93 @@ }; }; + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; @@ -186,7 +461,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; status = "disabled"; }; @@ -197,7 +472,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x10000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; status = "disabled"; }; @@ -208,7 +483,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x20000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; status = "disabled"; }; @@ -219,7 +494,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x30000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; status = "disabled"; }; @@ -230,7 +505,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x40000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; status = "disabled"; }; @@ -241,7 +516,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x50000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; status = "disabled"; }; @@ -252,7 +527,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x60000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; status = "disabled"; }; @@ -263,7 +538,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x70000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; status = "disabled"; }; @@ -274,7 +549,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x80000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; status = "disabled"; }; @@ -285,7 +560,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x90000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name = "GPIOJ"; status = "disabled"; }; @@ -296,7 +571,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0xa0000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; st,bank-name = "GPIOK"; status = "disabled"; }; @@ -315,7 +590,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index af48e82efe8a..029f88981961 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -20,4 +20,11 @@ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; }; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 17f197c5b22b..f689b47c5010 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,22 +5,21 @@ */ #include "stm32mp253.dtsi" -/ { - soc@0 { - rifsc: rifsc-bus@42080000 { - vdec: vdec@480d0000 { - compatible = "st,stm32mp25-vdec"; - reg = <0x480d0000 0x3c8>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ck_icn_p_vdec>; - }; +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_VDEC>; + access-controllers = <&rifsc 89>; - venc: venc@480e0000 { - compatible = "st,stm32mp25-venc"; - reg = <0x480e0000 0x800>; - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ck_icn_ls_mcu>; - }; - }; }; -}; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_VENC>; + access-controllers = <&rifsc 90>; + }; +};
\ No newline at end of file diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index b2d3afb15758..27b7360e5dba 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -55,6 +55,26 @@ status = "okay"; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <13>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <7>; + clock-frequency = <400000>; + status = "disabled"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -68,6 +88,20 @@ status = "okay"; }; +&spi3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + status = "disabled"; +}; + +&spi8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi8_pins_a>; + pinctrl-1 = <&spi8_sleep_pins_a>; + status = "disabled"; +}; + &usart2 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart2_pins_a>; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 53d616c3cfed..71e4bfcc9e81 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -88,7 +88,7 @@ }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 047a83cee603..690b4ed9c29b 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -304,7 +304,7 @@ }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 9a722c2473fb..2c327cc320cf 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -131,6 +132,8 @@ k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo +k3-am642-phyboard-electra-gpio-fan-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ @@ -161,19 +164,21 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ - k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ - k3-am69-sk-csi2-dual-imx219-dtbs \ + k3-am68-sk-base-board-csi2-dual-imx219.dtb \ + k3-am69-sk-csi2-dual-imx219.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721e-sk-csi2-dual-imx219-dtbs \ + k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ +DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@ DTC_FLAGS_k3-am625-sk += -@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am62p5-sk += -@ DTC_FLAGS_k3-am642-evm += -@ +DTC_FLAGS_k3-am642-phyboard-electra-rdk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-am68-sk-base-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index c4149059a4c5..9a17bd3e59c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -166,7 +166,6 @@ interrupt-parent = <&gic500>; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - ti,power-button; regulators { buck1_reg: buck1 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index e9cffca073ef..448a59dc53a7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -619,10 +619,11 @@ usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; @@ -644,10 +645,11 @@ usbss1: dwc3-usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 6c4cec8728e4..e8f4d136e5df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -22,6 +22,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,mclk-fs = <256>; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -35,7 +36,6 @@ "Line", "Line In Jack"; codec_dai: simple-audio-card,codec { - clocks = <&audio_refclk1>; sound-dai = <&wm8904_1a>; }; @@ -43,6 +43,15 @@ sound-dai = <&mcasp0>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; }; /* Verdin ETHs */ @@ -160,7 +169,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -183,6 +193,11 @@ status = "okay"; }; +/* Do not force CTRL_SLEEP_MOCI# always enabled */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin SD_1 */ &sdhci1 { status = "okay"; @@ -203,7 +218,15 @@ }; &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + usb-hub@1 { + compatible = "usb424,2744"; + reg = <1>; + vdd-supply = <®_usb_hub>; + }; }; /* Verdin CTRL_WAKE1_MICO# */ @@ -211,6 +234,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index be62648e7818..74eec1a1abca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -181,7 +181,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -232,6 +233,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi index 77b1beb638ad..754216d8ac14 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi @@ -81,10 +81,10 @@ &main_gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, - <&pinctrl_gpio_1>, - <&pinctrl_gpio_2>, - <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; }; /* Verdin I2C_1 */ @@ -149,6 +149,15 @@ status = "okay"; }; +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; +}; + /* Verdin I2C_3_HDMI */ &mcu_i2c0 { status = "okay"; @@ -192,6 +201,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi index 997dfafd27eb..7372d392ec8a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -159,7 +159,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -205,6 +206,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index e8d8857ad51f..2038c5e04639 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -76,7 +76,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */ }; opp-table { @@ -138,6 +138,22 @@ vin-supply = <®_1v8>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + /* Verdin SD_1 Power Supply */ reg_sdhc1_vmmc: regulator-sdhci1 { compatible = "regulator-fixed"; @@ -457,6 +473,13 @@ >; }; + /* Verdin SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: main-gpio1-48-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ + >; + }; + /* Verdin DSI_1_INT# (pulled-up as active-low) */ pinctrl_dsi1_int: main-gpio1-49-default-pins { pinctrl-single,pins = < @@ -571,7 +594,6 @@ AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ - AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ >; }; @@ -979,14 +1001,6 @@ "", "", ""; - - verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <31 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - }; }; &main_gpio1 { @@ -1407,6 +1421,15 @@ "", "", ""; + + verdin_pcie_1_reset_hog: pcie-1-reset-hog { + gpio-hog; + /* Verdin PCIE_1_RESET# (SODIMM 244) */ + gpios = <0 GPIO_ACTIVE_LOW>; + line-name = "PCIE_1_RESET#"; + output-low; + status = "disabled"; + }; }; /* Verdin CAN_2 */ @@ -1441,10 +1464,12 @@ /* Verdin SD_1 */ &sdhci1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; + pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; disable-wp; vmmc-supply = <®_sdhc1_vmmc>; vqmmc-supply = <®_sdhc1_vqmmc>; + ti,fails-without-test-cd; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 23ce1bfda8d6..66ddf2dc51af 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -21,6 +21,16 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; target-module@2b300050 { diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index a34e0df2ab86..18e3070a8683 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -82,6 +82,17 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pins_default>; + /* Internal power on time(Figure 8-3) * 2 */ + post-power-on-delay-ms = <10>; + /* Re-enable time(Figure 8-2) + 20uS */ + power-off-delay-us = <80>; + reset-gpios = <&main_gpio0 38 GPIO_ACTIVE_LOW>; + }; + vsys_5v0: regulator-1 { bootph-all; compatible = "regulator-fixed"; @@ -104,20 +115,6 @@ regulator-boot-on; }; - wlan_en: regulator-3 { - /* OUTPUT of SN74AVC2T244DQMR */ - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - vin-supply = <&vdd_3v3>; - gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_pins_default>; - }; - vdd_3v3_sd: regulator-4 { /* output of TPS22918DBVR-U21 */ bootph-all; @@ -292,6 +289,8 @@ pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ + AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ >; }; @@ -383,7 +382,6 @@ AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ - AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; @@ -597,6 +595,9 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; }; cpsw3g_phy1: ethernet-phy@1 { @@ -615,7 +616,7 @@ "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ "EEPROM_WP", /* 10 */ "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ - "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */ "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ @@ -839,13 +840,13 @@ }; &sdhci2 { - vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index a83a90497857..50d2573c840e 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -31,7 +31,7 @@ can_tc1: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; }; @@ -66,6 +66,35 @@ }; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Lyra"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "External Speaker", "SPOP", + "External Speaker", "SPOM"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp2>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&audio_refclk1>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -82,6 +111,15 @@ }; }; + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_3v3_mmc: regulator-vcc-3v3-mmc { compatible = "regulator-fixed"; regulator-name = "VCC_3V3_MMC"; @@ -90,9 +128,24 @@ regulator-always-on; regulator-boot-on; }; + + vcc_3v3_sw: regulator-vcc-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; }; &main_pmx0 { + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ @@ -150,6 +203,15 @@ >; }; + main_mcasp2_pins_default: main-mcasp2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */ + AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */ + AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ @@ -254,6 +316,21 @@ clock-frequency = <100000>; status = "okay"; + audio_codec: audio-codec@18 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; + + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + ai3x-micbias-vg = <2>; + + AVDD-supply = <&vcc_3v3_sw>; + IOVDD-supply = <&vcc_3v3_sw>; + DRVDD-supply = <&vcc_3v3_sw>; + DVDD-supply = <&vcc_1v8>; + }; + gpio_exp: gpio-expander@21 { pinctrl-names = "default"; pinctrl-0 = <&gpio_exp_int_pins_default>; @@ -271,6 +348,24 @@ "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; }; + usb-pd@22 { + compatible = "ti,tps6598x"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + sii9022: bridge-hdmi@39 { compatible = "sil,sii9022"; reg = <0x39>; @@ -329,6 +424,28 @@ status = "okay"; }; +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp2_pins_default>; + + /* MCASP_IIS_MODE */ + op-mode = <0>; + tdm-slots = <2>; + + /* 0: INACTIVE, 1: TX, 2: RX */ + serial-dir = < + 0 0 1 2 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + &sdhci1 { vmmc-supply = <&vcc_3v3_mmc>; vqmmc-supply = <&vddshv5_sdio>; @@ -350,7 +467,13 @@ }; &usb0 { - dr_mode = "peripheral"; + usb-role-switch; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; }; &usb1 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index aa1e057082f0..bf9c2d9c6439 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -573,7 +573,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - no-1-8-v; status = "disabled"; }; @@ -597,16 +596,16 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - no-1-8-v; status = "disabled"; }; usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; @@ -621,15 +620,18 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; usbss1: dwc3-usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; @@ -644,6 +646,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -1051,4 +1055,11 @@ #size-cells = <0>; }; }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index f7bec484705a..98043e9aa316 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,16 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f241637a5642..fa43cd0b631e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -113,6 +113,20 @@ regulator-boot-on; }; + vddshv_sdio: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -342,6 +356,12 @@ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ >; }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; }; &mcu_pmx0 { @@ -580,6 +600,7 @@ /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 7337a9e13535..900d1f9530a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -635,6 +635,58 @@ status = "disabled"; }; + usbss0: usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + fss: bus@fc00000 { compatible = "simple-bus"; reg = <0x00 0x0fc00000 0x00 0x70000>; @@ -673,6 +725,7 @@ assigned-clock-parents = <&k3_clks 13 11>; clock-names = "fck"; power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; dmas = <&main_pktdma 0xc600 15>, <&main_pktdma 0xc601 15>, @@ -696,6 +749,7 @@ label = "port1"; phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; + status = "disabled"; }; cpsw_port2: port@2 { @@ -704,6 +758,7 @@ label = "port2"; phys = <&phy_gmii_sel 2>; mac-address = [00 00 00 00 00 00]; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index a84756c336d0..c71d9624ea27 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -18,6 +18,16 @@ reg = <0x14 0x4>; bootph-all; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index e86f34e835c1..6e7234659111 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -27,6 +27,8 @@ spi0 = &ospi0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; }; chosen { @@ -297,6 +299,12 @@ bootph-all; }; + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + main_wlirq_pins_default: main-wlirq-default-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */ @@ -340,6 +348,36 @@ }; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; @@ -431,16 +469,19 @@ pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + status = "okay"; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; + status = "okay"; }; &cpsw_port2 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + status = "okay"; }; &cpsw3g_mdio { @@ -463,6 +504,35 @@ }; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + &mcasp1 { status = "okay"; #sound-dai-cells = <0>; @@ -493,7 +563,7 @@ pinctrl-0 = <&ospi0_pins_default>; bootph-all; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 53fe1d065ddb..e20e4ffd0f1f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -473,7 +473,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; /* main_uart1 is reserved for firmware usage */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso new file mode 100644 index 000000000000..5057658061b4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Nathan Morrisson <nmorrisson@phytec.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include "k3-pinctrl.h" + +&{/} { + fan: gpio-fan { + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 8600 1>; + gpios = <&main_gpio0 28 GPIO_ACTIVE_LOW>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_fan_pins_default>; + }; +}; + +&main_pmx0 { + gpio_fan_pins_default: gpio-fan-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x070, PIN_OUTPUT, 7) /* (V18) GPMC0_AD13.GPIO0_28 */ + >; + }; +}; + +&thermal_zones { + main0_thermal: main0-thermal { + trips { + main0_thermal_trip0: main0-thermal-trip { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&main0_thermal_trip0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8237b8c815b8..6df331ccb970 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -42,7 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&can_tc1_pins_default>; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; }; @@ -51,7 +51,7 @@ pinctrl-names = "default"; pinctrl-0 = <&can_tc2_pins_default>; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>; }; @@ -275,7 +275,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; &main_uart1 { @@ -283,7 +282,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; - current-speed = <115200>; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 67cd41bf806e..5b028b3a3192 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -381,7 +381,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; &main_uart1 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi index c50a585dd638..ef7897763ef8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi @@ -43,9 +43,33 @@ }; &icssg0_eth { - status = "disabled"; -}; + compatible = "ti,am654-sr1-icssg-prueth"; -&icssg0_mdio { - status = "disabled"; + ti,prus = <&pru0_0>, <&rtu0_0>, <&pru0_1>, <&rtu0_1>; + firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf", + "ti-pruss/am65x-rtu0-prueth-fw.elf", + "ti-pruss/am65x-pru1-prueth-fw.elf", + "ti-pruss/am65x-rtu1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, /* MII mode */ + <2>; + + dmas = <&main_udmap 0xc100>, /* egress slice 0 */ + <&main_udmap 0xc101>, /* egress slice 0 */ + <&main_udmap 0xc102>, /* egress slice 0 */ + <&main_udmap 0xc103>, /* egress slice 0 */ + <&main_udmap 0xc104>, /* egress slice 1 */ + <&main_udmap 0xc105>, /* egress slice 1 */ + <&main_udmap 0xc106>, /* egress slice 1 */ + <&main_udmap 0xc107>, /* egress slice 1 */ + <&main_udmap 0x4100>, /* ingress slice 0 */ + <&main_udmap 0x4101>, /* ingress slice 1 */ + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ff857117d719..ed71561c5bd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -66,7 +66,7 @@ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; ti,serdes-clk = <&serdes0_clk>; #clock-cells = <1>; - mux-controls = <&serdes_mux 0>; + mux-controls = <&serdes0_mux 0>; }; serdes1: serdes@910000 { @@ -81,7 +81,7 @@ assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; ti,serdes-clk = <&serdes1_clk>; #clock-cells = <1>; - mux-controls = <&serdes_mux 1>; + mux-controls = <&serdes1_mux 0>; }; main_uart0: serial@2800000 { @@ -89,7 +89,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; @@ -436,18 +435,13 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x5>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; - ti,otap-del-sel-hs400 = <0x0>; - ti,trm-icp = <0x8>; + ti,itap-del-sel-ddr52 = <0x0>; dma-coherent; status = "disabled"; }; @@ -459,18 +453,19 @@ clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; clock-names = "clk_ahb", "clk_xin"; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0x8>; ti,otap-del-sel-sdr104 = <0x7>; ti,otap-del-sel-ddr50 = <0x4>; - ti,otap-del-sel-ddr52 = <0x4>; - ti,otap-del-sel-hs200 = <0x7>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; dma-coherent; status = "disabled"; }; @@ -483,20 +478,25 @@ ranges = <0x0 0x0 0x00100000 0x1c000>; serdes0_clk: clock@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4080 0x4>; + + serdes0_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* lane select */ + }; }; serdes1_clk: clock@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; - }; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4090 0x4>; - serdes_mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ - <0x4090 0x3>; /* SERDES1 lane select */ + serdes1_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* lane select */ + }; }; dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 6ff3ccc39fb4..8feab9317644 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -43,7 +43,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; @@ -286,7 +285,11 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 37527890ddea..eee072e44a42 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -59,7 +59,6 @@ reg = <0x42300000 0x100>; interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 50de2a448a3a..d88651c297a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -517,18 +517,18 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 657f9cc9f4ea..9386bf3ef9f6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -440,7 +440,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; @@ -452,7 +451,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; @@ -464,7 +462,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; @@ -476,7 +473,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; @@ -488,7 +484,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; @@ -500,7 +495,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; @@ -512,7 +506,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; @@ -524,7 +517,6 @@ reg = <0x00 0x02870000 0x00 0x100>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; @@ -536,7 +528,6 @@ reg = <0x00 0x02880000 0x00 0x100>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; @@ -548,7 +539,6 @@ reg = <0x00 0x02890000 0x00 0x100>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 7cf21c99956e..fccaabfb1348 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -259,7 +259,6 @@ reg = <0x00 0x42300000 0x00 0x100>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 2>; clock-names = "fclk"; @@ -271,7 +270,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 2>; clock-names = "fclk"; @@ -520,10 +518,12 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c7eafbc862f9..0da785be80ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1337,7 +1337,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; @@ -1349,7 +1348,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 0>; clock-names = "fclk"; @@ -1361,7 +1359,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>; clock-names = "fclk"; @@ -1373,7 +1370,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>; clock-names = "fclk"; @@ -1385,7 +1381,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 0>; clock-names = "fclk"; @@ -1397,7 +1392,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 0>; clock-names = "fclk"; @@ -1409,7 +1403,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 0>; clock-names = "fclk"; @@ -1421,7 +1414,6 @@ reg = <0x00 0x02870000 0x00 0x100>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 0>; clock-names = "fclk"; @@ -1433,7 +1425,6 @@ reg = <0x00 0x02880000 0x00 0x100>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 0>; clock-names = "fclk"; @@ -1445,7 +1436,6 @@ reg = <0x00 0x02890000 0x00 0x100>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 4618b697fbc4..9349ae07c046 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -243,7 +243,6 @@ reg = <0x00 0x42300000 0x00 0x100>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 0>; clock-names = "fclk"; @@ -255,7 +254,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; @@ -346,10 +344,14 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* HBMC/OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b70c8615e3c1..9ed6949b40e9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -459,7 +459,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 146 3>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; @@ -470,7 +469,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x200>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 350 3>; clock-names = "fclk"; power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; @@ -481,7 +479,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x200>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 351 3>; clock-names = "fclk"; power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; @@ -492,7 +489,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x200>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 352 3>; clock-names = "fclk"; power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; @@ -503,7 +499,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x200>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 353 3>; clock-names = "fclk"; power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; @@ -514,7 +509,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x200>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 354 3>; clock-names = "fclk"; power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; @@ -525,7 +519,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x200>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 355 3>; clock-names = "fclk"; power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; @@ -536,7 +529,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x200>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 356 3>; clock-names = "fclk"; power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; @@ -547,7 +539,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x200>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 357 3>; clock-names = "fclk"; power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; @@ -558,7 +549,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x200>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 358 3>; clock-names = "fclk"; power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; @@ -778,8 +768,6 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index eaf7f709440e..5ccb04c7c462 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -298,7 +298,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; @@ -309,7 +308,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x200>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index be4502fe1c9d..568e6a04619d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -117,6 +117,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index cee3a8661d5e..bf3c246d13d1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -226,10 +226,7 @@ &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - status = "disabled"; + status = "okay"; }; &main_gpio1 { @@ -369,6 +366,13 @@ }; +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; @@ -377,7 +381,6 @@ pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; status = "okay"; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 81fd7afac8c5..d511b25d62e3 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -343,16 +343,16 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index b67c37460a73..6a4554c6c9c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -404,7 +404,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; @@ -415,7 +414,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x200>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 388 0>; clock-names = "fclk"; power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; @@ -426,7 +424,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x200>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 389 0>; clock-names = "fclk"; power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; @@ -437,7 +434,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x200>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 390 0>; clock-names = "fclk"; power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; @@ -448,7 +444,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x200>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 391 0>; clock-names = "fclk"; power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; @@ -459,7 +454,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x200>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 392 0>; clock-names = "fclk"; power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; @@ -470,7 +464,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x200>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 393 0>; clock-names = "fclk"; power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; @@ -481,7 +474,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x200>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 394 0>; clock-names = "fclk"; power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; @@ -492,7 +484,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x200>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 395 0>; clock-names = "fclk"; power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; @@ -503,7 +494,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x200>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 396 0>; clock-names = "fclk"; power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; @@ -914,8 +904,6 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - sdhci-caps-mask = <0x00000003 0x00000000>; - no-1-8-v; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 77a8d99139ec..2e18d91ae92f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -304,7 +304,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 397 0>; clock-names = "fclk"; power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; @@ -315,7 +314,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x200>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; @@ -674,10 +672,13 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 6e2e92ffe745..da7368ed6b52 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -234,6 +234,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 25d20d803230..34d0e0be3fe6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -169,7 +169,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |