diff options
Diffstat (limited to 'arch/arm')
878 files changed, 17199 insertions, 45412 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aad7400e0913..2201ff3002a7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,7 +6,7 @@ config ARM select HAVE_DMA_API_DEBUG select HAVE_IDE if PCI || ISA || PCMCIA select HAVE_DMA_ATTRS - select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7) + select HAVE_DMA_CONTIGUOUS if MMU select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION @@ -273,13 +273,12 @@ config ARCH_INTEGRATOR select ARM_AMBA select ARCH_HAS_CPUFREQ select COMMON_CLK - select CLK_VERSATILE + select COMMON_CLK_VERSATILE select HAVE_TCM select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER @@ -289,13 +288,12 @@ config ARCH_INTEGRATOR config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select CLKDEV_LOOKUP - select HAVE_MACH_CLKDEV + select COMMON_CLK + select COMMON_CLK_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE - select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB @@ -312,7 +310,6 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB - select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD @@ -350,17 +347,22 @@ config ARCH_AT91 This enables support for systems based on Atmel AT91RM9200 and AT91SAM9* processors. -config ARCH_BCMRING - bool "Broadcom BCMRING" - depends on MMU - select CPU_V6 +config ARCH_BCM2835 + bool "Broadcom BCM2835 family" + select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA + select ARM_ERRATA_411920 select ARM_TIMER_SP804 select CLKDEV_LOOKUP + select COMMON_CLK + select CPU_V6 select GENERIC_CLOCKEVENTS - select ARCH_WANT_OPTIONAL_GPIOLIB + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + select USE_OF help - Support for Broadcom's BCMRing platform. + This enables support for the Broadcom BCM2835 SoC. This SoC is + use in the Raspberry Pi, and Roku 2 devices. config ARCH_HIGHBANK bool "Calxeda Highbank-based" @@ -384,6 +386,8 @@ config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select CPU_ARM720T select ARCH_USES_GETTIMEOFFSET + select COMMON_CLK + select CLKDEV_LOOKUP select NEED_MACH_MEMORY_H help Support for Cirrus Logic 711x/721x/731x based boards. @@ -407,21 +411,19 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_PRIMA2 - bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" - select CPU_V7 +config ARCH_SIRF + bool "CSR SiRF" select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP + select COMMON_CLK select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_SIRF select USE_OF - select ZONE_DMA help - Support for CSR SiRFSoC ARM Cortex A9 Platform + Support for CSR SiRFprimaII/Marco/Polo platforms config ARCH_EBSA110 bool "EBSA-110" @@ -456,7 +458,7 @@ config ARCH_FOOTBRIDGE select FOOTBRIDGE select GENERIC_CLOCKEVENTS select HAVE_IDE - select NEED_MACH_IO_H + select NEED_MACH_IO_H if !MMU select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -483,7 +485,9 @@ config ARCH_MXS select CLKSRC_MMIO select COMMON_CLK select HAVE_CLK_PREPARE + select MULTI_IRQ_HANDLER select PINCTRL + select SPARSE_IRQ select USE_OF help Support for Freescale MXS-based family of processors @@ -513,7 +517,6 @@ config ARCH_IOP13XX select PCI select ARCH_SUPPORTS_MSI select VMSPLIT_1G - select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NEED_RET_TO_USER help @@ -523,7 +526,6 @@ config ARCH_IOP32X bool "IOP32x-based" depends on MMU select CPU_XSCALE - select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -536,7 +538,6 @@ config ARCH_IOP33X bool "IOP33x-based" depends on MMU select CPU_XSCALE - select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -576,7 +577,6 @@ config ARCH_DOVE select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the Marvell Dove SoC 88AP510 @@ -587,7 +587,6 @@ config ARCH_KIRKWOOD select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: @@ -614,7 +613,6 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: @@ -627,7 +625,6 @@ config ARCH_ORION5X select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: @@ -652,8 +649,9 @@ config ARCH_KS8695 bool "Micrel/Kendin KS8695" select CPU_ARM922T select ARCH_REQUIRE_GPIOLIB - select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H + select CLKSRC_MMIO + select GENERIC_CLOCKEVENTS help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. @@ -683,7 +681,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ select USE_OF select COMMON_CLK @@ -710,14 +707,6 @@ config ARCH_PICOXCELL family of Femtocell devices. The picoxcell support requires device tree for all boards. -config ARCH_PNX4008 - bool "Philips Nexperia PNX4008 Mobile" - select CPU_ARM926T - select CLKDEV_LOOKUP - select ARCH_USES_GETTIMEOFFSET - help - This enables support for Philips PNX4008 mobile platform. - config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU @@ -913,7 +902,6 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H - select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). @@ -932,6 +920,7 @@ config ARCH_U300 select COMMON_CLK select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB + select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. @@ -1006,6 +995,10 @@ config ARCH_VT8500 select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB + select USE_OF + select COMMON_CLK + select HAVE_CLK + select CLKDEV_LOOKUP help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. @@ -1032,8 +1025,6 @@ source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-at91/Kconfig" -source "arch/arm/mach-bcmring/Kconfig" - source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-cns3xxx/Kconfig" @@ -1119,6 +1110,8 @@ source "arch/arm/mach-exynos/Kconfig" source "arch/arm/mach-shmobile/Kconfig" +source "arch/arm/mach-prima2/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" @@ -1130,8 +1123,6 @@ source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" source "arch/arm/plat-versatile/Kconfig" -source "arch/arm/mach-vt8500/Kconfig" - source "arch/arm/mach-w90x900/Kconfig" # Definitions to make life easier @@ -1180,12 +1171,6 @@ config XSCALE_PMU depends on CPU_XSCALE default y -config CPU_HAS_PMU - depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ - (!ARCH_OMAP3 || OMAP3_EMU) - default y - bool - config MULTI_IRQ_HANDLER bool help @@ -1624,6 +1609,7 @@ config ARCH_NR_GPIO default 355 if ARCH_U8500 default 264 if MACH_H4700 default 512 if SOC_OMAP5 + default 288 if ARCH_VT8500 default 0 help Maximum number of GPIOs in the system. @@ -1758,7 +1744,7 @@ config HIGHPTE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && CPU_HAS_PMU + depends on PERF_EVENTS default y help Enable hardware performance counter support for perf events. If @@ -2261,7 +2247,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5PC100 && !ARCH_TEGRA + depends on !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK def_bool y diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index f15f82bf3a50..e968a52e4881 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -356,15 +356,15 @@ choice is nothing connected to read from the DCC. config DEBUG_SEMIHOSTING - bool "Kernel low-level debug output via semihosting I" + bool "Kernel low-level debug output via semihosting I/O" help Semihosting enables code running on an ARM target to use the I/O facilities on a host debugger/emulator through a - simple SVC calls. The host debugger or emulator must have + simple SVC call. The host debugger or emulator must have semihosting enabled for the special svc call to be trapped otherwise the kernel will crash. - This is known to work with OpenOCD, as wellas + This is known to work with OpenOCD, as well as ARM's Fast Models, or any other controlling environment that implements semihosting. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 30eae87ead6d..a2eb4fe068b9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -136,7 +136,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_AT91) := at91 -machine-$(CONFIG_ARCH_BCMRING) := bcmring +machine-$(CONFIG_ARCH_BCM2835) := bcm2835 machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx machine-$(CONFIG_ARCH_DAVINCI) := davinci @@ -167,7 +167,6 @@ machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2 machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell -machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_PRIMA2) := prima2 machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_REALVIEW) := realview @@ -284,10 +283,10 @@ zImage Image xipImage bootpImage uImage: vmlinux zinstall uinstall install: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ -%.dtb: +%.dtb: scripts $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ -dtbs: +dtbs: scripts $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ # We use MRPROPER_FILES and CLEAN_FILES now diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b8c64b80bafc..bc67cbff3944 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -653,16 +653,21 @@ __armv7_mmu_cache_on: mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables #endif + mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client + bic r6, r6, #1 << 31 @ 32-bit translation system + bic r6, r6, #3 << 0 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control + mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index a9af4db7234c..c634f87e230e 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -17,4 +17,64 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44e09000 { + status = "okay"; + }; + + i2c1: i2c@44e0b000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; + }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d6a97d9eff72..185d6325a458 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -17,4 +17,104 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44e09000 { + status = "okay"; + }; + + i2c1: i2c@44e0b000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; + }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index bd0cff3f808c..bb31bff01998 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -69,95 +69,146 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x44e07000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <96>; }; - gpio2: gpio@4804C000 { + gpio2: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x4804c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <98>; }; - gpio3: gpio@481AC000 { + gpio3: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ac000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <32>; }; - gpio4: gpio@481AE000 { + gpio4: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ae000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <62>; }; - uart1: serial@44E09000 { + uart1: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; + reg = <0x44e09000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <72>; + status = "disabled"; }; uart2: serial@48022000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; + reg = <0x48022000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <73>; + status = "disabled"; }; uart3: serial@48024000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; + reg = <0x48024000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <74>; + status = "disabled"; }; - uart4: serial@481A6000 { + uart4: serial@481a6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; + reg = <0x481a6000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <44>; + status = "disabled"; }; - uart5: serial@481A8000 { + uart5: serial@481a8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; + reg = <0x481a8000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <45>; + status = "disabled"; }; - uart6: serial@481AA000 { + uart6: serial@481aa000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; + reg = <0x481aa000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <46>; + status = "disabled"; }; - i2c1: i2c@44E0B000 { + i2c1: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; + reg = <0x44e0b000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <70>; + status = "disabled"; }; - i2c2: i2c@4802A000 { + i2c2: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <71>; + status = "disabled"; }; - i2c3: i2c@4819C000 { + i2c3: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; + reg = <0x4819c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <30>; + status = "disabled"; }; wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; + reg = <0x44e35000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <91>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 66389c1c6f62..7c95f76398de 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -104,6 +104,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -113,6 +114,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -122,6 +124,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index b460d6ce9eb5..195019b7ca0e 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -95,6 +95,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioB: gpio@fffff400 { @@ -104,6 +105,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioC: gpio@fffff600 { @@ -113,6 +115,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioD: gpio@fffff800 { @@ -122,6 +125,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioE: gpio@fffffa00 { @@ -131,6 +135,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 7829a4d0cb22..96514c134e54 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -15,7 +15,7 @@ compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; chosen { - bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index bafa8806fc17..63751b1e744b 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -113,6 +113,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioB: gpio@fffff400 { @@ -122,6 +123,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioC: gpio@fffff600 { @@ -131,6 +133,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioD: gpio@fffff800 { @@ -140,6 +143,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioE: gpio@fffffa00 { @@ -149,6 +153,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index bfac0dfc332c..ef9336ae9614 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -107,6 +107,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -116,6 +117,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -125,6 +127,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioD: gpio@fffffa00 { @@ -134,6 +137,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 4a18c393b136..8a387a8d61b7 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -115,6 +115,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -124,6 +125,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -133,6 +135,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; pioD: gpio@fffffa00 { @@ -142,6 +145,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts new file mode 100644 index 000000000000..7dd860f83f96 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/memreserve/ 0x0c000000 0x04000000; +/include/ "bcm2835.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + + memory { + reg = <0 0x10000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi new file mode 100644 index 000000000000..0b619398532c --- /dev/null +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -0,0 +1,39 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "brcm,bcm2835"; + model = "BCM2835"; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlyprintk console=ttyAMA0"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7e000000 0x20000000 0x02000000>; + + timer { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7e003000 0x1000>; + interrupts = <1 0>, <1 1>, <1 2>, <1 3>; + clock-frequency = <1000000>; + }; + + intc: interrupt-controller { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart@20201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; + clock-frequency = <3000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 3180a9c588b9..748ba7aa746c 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -194,6 +194,8 @@ interrupts = <0 47 0x4>; #address-cells = <1>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; ranges; prcmu-timer-4@80157450 { @@ -330,6 +332,7 @@ ab8500@5 { compatible = "stericsson,ab8500"; reg = <5>; /* mailbox 5 is i2c */ + interrupt-parent = <&intc>; interrupts = <0 40 0x4>; interrupt-controller; #interrupt-cells = <2>; @@ -371,7 +374,7 @@ }; ab8500-ponkey { - compatible = "stericsson,ab8500-ponkey"; + compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 0x4 7 0x4>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; @@ -389,6 +392,12 @@ compatible = "stericsson,ab8500-debug"; }; + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; @@ -471,48 +480,63 @@ }; i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; interrupts = <0 21 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; interrupts = <0 22 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; interrupts = <0 55 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; interrupts = <0 12 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; interrupts = <0 51 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; ssp@80002000 { compatible = "arm,pl022", "arm,primecell"; - reg = <80002000 0x1000>; + reg = <0x80002000 0x1000>; interrupts = <0 14 0x4>; #address-cells = <1>; #size-cells = <0>; @@ -580,6 +604,39 @@ status = "disabled"; }; + msp0: msp@80123000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80123000 0x1000>; + interrupts = <0 31 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + msp1: msp@80124000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80124000 0x1000>; + interrupts = <0 62 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + // HDMI sound + msp2: msp@80117000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80117000 0x1000>; + interrupts = <0 98 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + msp3: msp@80125000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80125000 0x1000>; + interrupts = <0 62 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + external-bus@50000000 { compatible = "simple-bus"; reg = <0x50000000 0x4000000>; diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index d79b28d9c963..a4ba31b23c88 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -166,9 +166,116 @@ #size-cells = <0>; autorepeat; button@21 { - label = "GPIO Key UP"; + label = "Interrupt Key"; linux,code = <103>; gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; }; }; diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi new file mode 100644 index 000000000000..f97f70f83374 --- /dev/null +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -0,0 +1,67 @@ +/* + * Common devices used in different OMAP boards + */ + +/ { + elpida_ECB240ABACN: lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts new file mode 100644 index 000000000000..2131d77dc9c9 --- /dev/null +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -0,0 +1,95 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson HREF platform with Device Tree"; + compatible = "st-ericsson,hrefv60+"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + uart@80120000 { + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; + + i2c@80004000 { + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + tps61052@33 { + compatible = "tps61052"; + reg = <0x33>; + }; + }; + + i2c@80128000 { + lp5521@0x33 { + compatible = "lp5521"; + reg = <0x33>; + }; + + lp5521@0x34 { + compatible = "lp5521"; + reg = <0x34>; + }; + + bh1780@0x29 { + compatible = "rohm,bh1780gli"; + reg = <0x33>; + }; + }; + + sound { + compatible = "stericsson,snd-soc-mop500"; + + stericsson,cpu-dai = <&msp1 &msp3>; + stericsson,audio-codec = <&codec>; + }; + + msp1: msp@80124000 { + status = "okay"; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index e3486f486b40..035c13f9d3c0 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -42,12 +42,13 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 20912b1d8893..384d8b66f337 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -31,6 +31,22 @@ bus-width = <4>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { @@ -39,6 +55,47 @@ pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "green"; + gpios = <&gpio2 1 0>; + linux,default-trigger = "default-on"; }; }; }; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 757a327ff3e8..85c3864b6a56 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -36,7 +36,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..9ca4ca70c1bc 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -43,7 +43,7 @@ ranges; icoll: interrupt-controller@80000000 { - compatible = "fsl,imx23-icoll", "fsl,mxs-icoll"; + compatible = "fsl,imx23-icoll", "fsl,icoll"; interrupt-controller; #interrupt-cells = <1>; reg = <0x80000000 0x2000>; @@ -52,6 +52,7 @@ dma-apbh@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 15>; }; ecc@80008000 { @@ -67,6 +68,7 @@ reg-names = "gpmi-nand", "bch"; interrupts = <13>, <56>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 34>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -74,6 +76,7 @@ ssp0: ssp@80010000 { reg = <0x80010000 0x2000>; interrupts = <15 14>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -140,6 +143,17 @@ fsl,pull-up = <0>; }; + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ + 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < @@ -183,7 +197,6 @@ 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; fsl,drive-strength = <1>; @@ -280,6 +293,7 @@ dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 16>; }; dcp@80028000 { @@ -306,12 +320,14 @@ compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; interrupts = <46 45>; + clocks = <&clks 38>; status = "disabled"; }; ssp1: ssp@80034000 { reg = <0x80034000 0x2000>; interrupts = <2 20>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -329,9 +345,10 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx23-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { @@ -383,20 +400,23 @@ pwm: pwm@80064000 { compatible = "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 30>; #pwm-cells = <2>; fsl,pwm-number = <5>; status = "disabled"; }; timrot@80068000 { + compatible = "fsl,imx23-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - status = "disabled"; + interrupts = <28 29 30 31>; }; auart0: serial@8006c000 { compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <24 25 23>; + clocks = <&clks 32>; status = "disabled"; }; @@ -404,6 +424,7 @@ compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <59 60 58>; + clocks = <&clks 32>; status = "disabled"; }; @@ -411,11 +432,15 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80070000 0x2000>; interrupts = <0>; + clocks = <&clks 32>, <&clks 16>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; - usbphy@8007c000 { + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 41>; status = "disabled"; }; }; @@ -428,8 +453,12 @@ reg = <0x80080000 0x80000>; ranges; - usbctrl@80080000 { + usb0: usb@80080000 { + compatible = "fsl,imx23-usb", "fsl,imx27-usb"; reg = <0x80080000 0x40000>; + interrupts = <11>; + fsl,usbphy = <&usbphy0>; + clocks = <&clks 40>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..af50469e34b2 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts @@ -23,10 +23,6 @@ soc { aipi@10000000 { /* aipi */ - wdog@10002000 { - status = "okay"; - }; - serial@1000a000 { fsl,uart-has-rtscts; status = "okay"; @@ -49,7 +45,7 @@ i2c@1001d000 { clock-frequency = <400000>; status = "okay"; - at24@4c { + at24@52 { compatible = "at,24c32"; pagesize = <32>; reg = <0x52>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..3e54f1498841 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -62,7 +62,6 @@ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x4000>; interrupts = <27>; - status = "disabled"; }; uart1: serial@1000a000 { diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index b383417a558f..5171667a7763 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts new file mode 100644 index 000000000000..05c892e931e3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -0,0 +1,99 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +/include/ "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10049 Board"; + compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + spi3_pins_cfa10049: spi3-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ + 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ + 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ + 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + + ssp3: ssp@80016000 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_cfa10049>; + status = "okay"; + + gpio5: gpio5@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + }; + + gpio6: gpio6@1 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; + + }; + }; + + apbx@80040000 { + i2c1: i2c@8005a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 773c0e84d1fb..a0ad71ca3a44 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -46,11 +46,28 @@ wp-gpios = <&gpio0 28 0>; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ @@ -128,6 +145,10 @@ status = "okay"; }; + lradc@80050000 { + status = "okay"; + }; + i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -140,6 +161,12 @@ VDDIO-supply = <®_3p3v>; }; + + at24@51 { + compatible = "at24,24c32"; + pagesize = <32>; + reg = <0x51>; + }; }; pwm: pwm@80064000 { diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 183a3fd2d859..3bab6b00c52d 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -23,6 +23,8 @@ apb@80000000 { apbh@80000000 { gpmi-nand@8000c000 { + #address-cells = <1>; + #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; @@ -61,19 +63,40 @@ &mmc0_cd_cfg &mmc0_sck_cfg>; bus-width = <8>; - wp-gpios = <&gpio3 10 1>; + wp-gpios = <&gpio3 10 0>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ + 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -129,6 +152,7 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; status = "okay"; sgtl5000: codec@0a { @@ -151,32 +175,51 @@ }; }; + lradc@80050000 { + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; status = "okay"; }; - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; + usbphy0: usbphy@8007c000 { status = "okay"; }; - auart3: serial@80070000 { + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + + auart0: serial@8006a000 { pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; + pinctrl-0 = <&auart0_2pins_a>; status = "okay"; }; }; }; ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy0_pins_a>; + status = "okay"; + }; + + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy1_pins_a>; + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio3 11 0>; status = "okay"; }; @@ -198,6 +241,30 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 12 0>; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 13 0>; + }; }; sound { diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 62bf767409a6..37be532f0055 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -25,7 +25,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ @@ -34,6 +34,24 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + mac0_pins_gpio: mac0-gpio-mode@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ + 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ + 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ + 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ + 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ + 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ + 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ + 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ + 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; }; @@ -72,8 +90,9 @@ ahb@80080000 { mac0: ethernet@800f0000 { phy-mode = "rmii"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio_mode"; pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&mac0_pins_gpio>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..59fbfba23df8 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -27,6 +27,8 @@ serial2 = &auart2; serial3 = &auart3; serial4 = &auart4; + ethernet0 = &mac0; + ethernet1 = &mac1; }; cpus { @@ -50,7 +52,7 @@ ranges; icoll: interrupt-controller@80000000 { - compatible = "fsl,imx28-icoll", "fsl,mxs-icoll"; + compatible = "fsl,imx28-icoll", "fsl,icoll"; interrupt-controller; #interrupt-cells = <1>; reg = <0x80000000 0x2000>; @@ -65,6 +67,7 @@ dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 25>; }; perfmon@80006000 { @@ -81,34 +84,47 @@ reg-names = "gpmi-nand", "bch"; interrupts = <88>, <41>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 50>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; ssp0: ssp@80010000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80010000 0x2000>; interrupts = <96 82>; + clocks = <&clks 46>; fsl,ssp-dma-channel = <0>; status = "disabled"; }; ssp1: ssp@80012000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80012000 0x2000>; interrupts = <97 83>; + clocks = <&clks 47>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80014000 0x2000>; interrupts = <98 84>; + clocks = <&clks 48>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; ssp3: ssp@80016000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80016000 0x2000>; interrupts = <99 85>; + clocks = <&clks 49>; fsl,ssp-dma-channel = <3>; status = "disabled"; }; @@ -410,6 +426,28 @@ fsl,pull-up = <1>; }; + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ + 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ + 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < @@ -453,6 +491,16 @@ fsl,pull-up = <0>; }; + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -507,6 +555,49 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ + 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ + 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ + 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + usbphy0_pins_a: usbphy0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy0_pins_b: usbphy0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy1_pins_a: usbphy1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -523,6 +614,7 @@ dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 26>; }; dcp@80028000 { @@ -551,6 +643,7 @@ compatible = "fsl,imx28-lcdif"; reg = <0x80030000 0x2000>; interrupts = <38 86>; + clocks = <&clks 55>; status = "disabled"; }; @@ -558,6 +651,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80032000 0x2000>; interrupts = <8>; + clocks = <&clks 58>, <&clks 58>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -565,6 +660,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80034000 0x2000>; interrupts = <9>; + clocks = <&clks 59>, <&clks 59>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -611,15 +708,17 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { compatible = "fsl,imx28-saif"; reg = <0x80042000 0x2000>; interrupts = <59 80>; + clocks = <&clks 53>; fsl,saif-dma-channel = <4>; status = "disabled"; }; @@ -633,12 +732,16 @@ compatible = "fsl,imx28-saif"; reg = <0x80046000 0x2000>; interrupts = <58 81>; + clocks = <&clks 54>; fsl,saif-dma-channel = <5>; status = "disabled"; }; lradc@80050000 { + compatible = "fsl,imx28-lradc"; reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; status = "disabled"; }; @@ -677,20 +780,23 @@ pwm: pwm@80064000 { compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 44>; #pwm-cells = <2>; fsl,pwm-number = <8>; status = "disabled"; }; timrot@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - status = "disabled"; + interrupts = <48 49 50 51>; }; auart0: serial@8006a000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; + clocks = <&clks 45>; status = "disabled"; }; @@ -698,6 +804,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; + clocks = <&clks 45>; status = "disabled"; }; @@ -705,6 +812,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; + clocks = <&clks 45>; status = "disabled"; }; @@ -712,6 +820,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; + clocks = <&clks 45>; status = "disabled"; }; @@ -719,6 +828,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; + clocks = <&clks 45>; status = "disabled"; }; @@ -726,18 +836,22 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80074000 0x1000>; interrupts = <47>; + clocks = <&clks 45>, <&clks 26>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; usbphy0: usbphy@8007c000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 62>; status = "disabled"; }; usbphy1: usbphy@8007e000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007e000 0x2000>; + clocks = <&clks 63>; status = "disabled"; }; }; @@ -754,6 +868,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80080000 0x10000>; interrupts = <93>; + clocks = <&clks 60>; fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -762,6 +877,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80090000 0x10000>; interrupts = <92>; + clocks = <&clks 61>; fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -775,6 +891,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f0000 0x4000>; interrupts = <101>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -782,6 +900,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f4000 0x4000>; interrupts = <102>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 59d9789e5508..cbd2b1c7487b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -25,23 +25,31 @@ aips@70000000 { /* aips-1 */ spba@70000000 { esdhc@70004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; fsl,cd-controller; fsl,wp-controller; status = "okay"; }; esdhc@70008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; cd-gpios = <&gpio1 6 0>; wp-gpios = <&gpio1 5 0>; status = "okay"; }; uart3: serial@7000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@70010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; status = "okay"; @@ -169,31 +177,43 @@ }; }; - wdog@73f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc-babbage"; - reg = <0x73fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ + 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ + 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ + 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ + 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ + 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ + 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ + >; + }; + }; }; uart1: serial@73fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; fsl,uart-has-rtscts; status = "okay"; }; uart2: serial@73fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@80000000 { /* aips-2 */ - sdma@83fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - i2c@83fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -206,10 +226,14 @@ }; audmux@83fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@83fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "mii"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..2f71a91ca98e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -130,6 +130,34 @@ }; }; + usb@73f80000 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@73f80200 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@73f80400 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@73f80600 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; @@ -174,7 +202,6 @@ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@73f9c000 { /* WDOG2 */ @@ -184,6 +211,122 @@ status = "disabled"; }; + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc"; + reg = <0x73fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ + 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ + 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ + 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ + 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ + 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ + 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ + 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ + 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ + 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ + 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ + 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ + 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ + 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ + 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ + 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ + 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ + 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ + 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ + 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ + 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ + 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ + 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ + 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ + 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ + 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ + 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ + 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ + 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ + 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ + 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ + 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ + 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ + 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ + 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ + 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ + 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ + 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ + 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ + 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ + >; + }; + }; + }; + uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; @@ -219,6 +362,7 @@ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; cspi@83fc0000 { diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..4be76f223526 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -25,31 +25,66 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_2>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio1 9 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-ard"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ + 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ + 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ + 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ + 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ + 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ + 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ + 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ + 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ + 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ + 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ + 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ + 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ + 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ + 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ + 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ + 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ + 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ + 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ + 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ + 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ + 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ + 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ + 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ + 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ + 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ + 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ + 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ + 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ + 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ + 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ + 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ + 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ + 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; status = "okay"; }; }; - - aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - }; }; eim-cs1@f4000000 { diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 9c798034675e..a124d1e25258 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -25,12 +25,16 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio3 14 0>; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -56,32 +60,45 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-evk"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; pmic: mc13892@08 { @@ -96,6 +113,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 2d803a9a6949..08948af86d1a 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -25,6 +25,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; status = "okay"; }; @@ -35,32 +37,46 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-qsb"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ + 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -72,6 +88,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -158,10 +176,14 @@ }; audmux@63fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 08091029168e..06c68580c842 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -25,22 +25,30 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio4 11 0>; status = "okay"; }; esdhc@50008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; non-removable; status = "okay"; }; uart3: serial@5000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -72,35 +80,49 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; non-removable; status = "okay"; }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-smd"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; uart2: serial@53fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; codec: sgtl5000@0a { @@ -120,6 +142,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -139,6 +163,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..221cf3321b0a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -135,6 +135,34 @@ }; }; + usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@53f80200 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; @@ -179,7 +207,6 @@ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@53f9c000 { /* WDOG2 */ @@ -189,6 +216,161 @@ status = "disabled"; }; + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ + 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ + 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ + 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ + 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ + 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ + 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ + 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ + 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ + 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ + 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ + 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ + 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ + 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ + 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + + pinctrl_esdhc1_2: esdhc1grp-2 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ + 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ + 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ + 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ + 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ + 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ + 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ + 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ + 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ + >; + }; + }; + + esdhc3 { + pinctrl_esdhc3_1: esdhc3grp-1 { + fsl,pins = < + 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ + 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ + 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ + 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ + 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ + 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ + 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ + 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ + 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ + 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ + 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ + 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ + 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ + 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ + 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ + 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ + 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ + 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ + >; + }; + }; + }; + uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; @@ -203,6 +385,20 @@ status = "disabled"; }; + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + status = "disabled"; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; @@ -277,6 +473,7 @@ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; cspi@63fc0000 { diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d792581672cc..15df4c105e89 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -28,8 +28,27 @@ status = "disabled"; /* gpmi nand conflicts with SD */ }; + aips-bus@02000000 { /* AIPS1 */ + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ + 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ + >; + }; + }; + }; + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_2>; phy-mode = "rgmii"; status = "okay"; }; @@ -52,6 +71,8 @@ }; uart4: serial@021f0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..d152328285a1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -46,15 +46,20 @@ iomuxc@020e0000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_hog>; + pinctrl-0 = <&pinctrl_hog>; - gpios { - pinctrl_gpio_hog: gpiohog { + hog { + pinctrl_hog: hoggrp { fsl,pins = < - 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - >; + 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ + 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ + 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ + 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ + 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ + >; }; }; }; @@ -63,6 +68,9 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; status = "okay"; }; @@ -71,12 +79,16 @@ }; ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; cd-gpios = <&gpio7 0 0>; wp-gpios = <&gpio7 1 0>; vmmc-supply = <®_3p3v>; @@ -84,6 +96,8 @@ }; usdhc@0219c000 { /* uSDHC4 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; cd-gpios = <&gpio2 6 0>; wp-gpios = <&gpio2 7 0>; vmmc-supply = <®_3p3v>; @@ -99,7 +113,7 @@ uart2: serial@021e8000 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2_1>; + pinctrl-0 = <&pinctrl_uart2_1>; }; i2c@021a0000 { /* I2C1 */ @@ -111,6 +125,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + clocks = <&clks 169>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a181178..e596c28c214d 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -22,28 +22,51 @@ }; soc { - aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { uart1: serial@02020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; + + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ + 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ + 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ + 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; status = "okay"; }; usdhc@02194000 { /* uSDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..35e5895ba3df 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -97,18 +97,23 @@ dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; + clocks = <&clks 106>; }; gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 13 0x04>, <0 15 0x04>; - interrupt-names = "gpmi-dma", "bch"; - fsl,gpmi-dma-channel = <0>; - status = "disabled"; + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 152>, <&clks 153>, <&clks 151>, + <&clks 150>, <&clks 149>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; }; timer@00a00600 { @@ -150,6 +155,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; interrupts = <0 31 0x04>; + clocks = <&clks 112>, <&clks 112>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -159,6 +166,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; interrupts = <0 32 0x04>; + clocks = <&clks 113>, <&clks 113>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -168,6 +177,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; interrupts = <0 33 0x04>; + clocks = <&clks 114>, <&clks 114>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -177,6 +188,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; interrupts = <0 34 0x04>; + clocks = <&clks 115>, <&clks 115>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -186,6 +199,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 0x04>; + clocks = <&clks 116>, <&clks 116>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -193,6 +208,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -205,6 +222,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 0x04>; + clocks = <&clks 178>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <38 37>; status = "disabled"; @@ -214,6 +232,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 0x04>; + clocks = <&clks 179>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <42 41>; status = "disabled"; @@ -223,6 +242,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 0x04>; + clocks = <&clks 180>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <46 45>; status = "disabled"; @@ -362,20 +382,22 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 0x04>; - status = "disabled"; + clocks = <&clks 0>; }; wdog@020c0000 { /* WDOG2 */ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 0x04>; + clocks = <&clks 0>; status = "disabled"; }; - ccm@020c4000 { + clks: ccm@020c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; }; anatop@020c8000 { @@ -472,12 +494,14 @@ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + clocks = <&clks 182>; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; + clocks = <&clks 183>; }; snvs@020cc000 { @@ -514,86 +538,207 @@ /* shared pinctrl settings */ audmux { pinctrl_audmux_1: audmux-1 { - fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + fsl,pins = < + 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ + 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ + 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ + 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + >; + }; + }; + + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ + 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ + 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; }; }; gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + fsl,pins = < + 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + >; }; }; i2c1 { pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + fsl,pins = < + 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ + 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ + >; }; }; - serial2 { - pinctrl_serial2_1: serial2grp-1 { - fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ - 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ + 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ + >; + }; + }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ + 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ + >; + }; + }; + + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ + >; }; }; usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ + 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ + 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ + 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + >; + }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + >; }; }; usdhc4 { pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ + 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ + 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ + 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + >; }; - }; - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + >; }; }; }; @@ -612,6 +757,9 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 0x04>; + clocks = <&clks 155>, <&clks 155>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin"; }; }; @@ -635,7 +783,9 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -643,7 +793,9 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -651,6 +803,8 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -658,13 +812,24 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks 162>; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; + clocks = <&clks 117>, <&clks 117>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -677,6 +842,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 0x04>; + clocks = <&clks 163>, <&clks 163>, <&clks 163>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -684,6 +851,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 0x04>; + clocks = <&clks 164>, <&clks 164>, <&clks 164>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -691,6 +860,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 0x04>; + clocks = <&clks 165>, <&clks 165>, <&clks 165>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -698,6 +869,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 0x04>; + clocks = <&clks 166>, <&clks 166>, <&clks 166>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -707,6 +880,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a0000 0x4000>; interrupts = <0 36 0x04>; + clocks = <&clks 125>; status = "disabled"; }; @@ -716,6 +890,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a4000 0x4000>; interrupts = <0 37 0x04>; + clocks = <&clks 126>; status = "disabled"; }; @@ -725,6 +900,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a8000 0x4000>; interrupts = <0 38 0x04>; + clocks = <&clks 127>; status = "disabled"; }; @@ -788,6 +964,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -795,6 +973,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -802,6 +982,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -809,6 +991,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 80f74e256408..0514fb41627e 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -26,6 +26,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 45bc4bb04e57..31f2157cd7d7 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -7,7 +7,7 @@ compatible = "qcom,msm8660-surf", "qcom,msm8660"; interrupt-parent = <&intc>; - intc: interrupt-controller@02080000 { + intc: interrupt-controller@2080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; #interrupt-cells = <3>; @@ -15,6 +15,23 @@ < 0x02081000 0x1000 >; }; + timer@2000004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x02000004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@2000024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 0 0x301>; + reg = <0x02000024 0x10>, + <0x02000034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; + serial@19c400000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts new file mode 100644 index 000000000000..9e621b5ad3dd --- /dev/null +++ b/arch/arm/boot/dts/msm8960-cdp.dts @@ -0,0 +1,41 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8960 CDP"; + compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x80000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x80000>; + }; + + serial@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + }; +}; diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 25b50b759dec..77b84e17c477 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap2.dtsi" +/include/ "omap2420.dtsi" / { model = "TI OMAP2420 H4 board"; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi new file mode 100644 index 000000000000..bfd76b4a0ddc --- /dev/null +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -0,0 +1,48 @@ +/* + * Device Tree Source for OMAP2420 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2420", "ti,omap2"; + + ocp { + omap2420_pmx: pinmux@48000030 { + compatible = "ti,omap2420-padconf", "pinctrl-single"; + reg = <0x48000030 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi new file mode 100644 index 000000000000..4565d9750f4d --- /dev/null +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -0,0 +1,92 @@ +/* + * Device Tree Source for OMAP243x SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2"; + + ocp { + omap2430_pmx: pinmux@49002030 { + compatible = "ti,omap2430-padconf", "pinctrl-single"; + reg = <0x49002030 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <64>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>, /* RX interrupt */ + <61>; /* RX overflow interrupt */ + interrupt-names = "common", "tx", "rx", "rx_overflow"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@4808c000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808c000 0xff>; + reg-names = "mpu"; + interrupts = <17>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@4808e000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808e000 0xff>; + reg-names = "mpu"; + interrupts = <18>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <19>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index cdcb98c7e075..c38cf76df81f 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -7,16 +7,44 @@ */ /dts-v1/; -/include/ "omap3.dtsi" +/include/ "omap36xx.dtsi" / { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; + model = "TI OMAP3 BeagleBoard xM"; + compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; }; &i2c1 { @@ -27,11 +55,17 @@ interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - vsim: regulator@10 { + vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; }; }; @@ -67,3 +101,15 @@ &mmc3 { status = "disabled"; }; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index f349ee9182ce..e8ba1c247a39 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -17,6 +17,15 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; }; &i2c1 { @@ -46,3 +55,7 @@ reg = <0x5c>; }; }; + +&twl_gpio { + ti,use-leds; +}; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi new file mode 100644 index 000000000000..89808ce01673 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * The Gumstix Overo must be combined with an expansion board. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + overo { + label = "overo:blue:COM"; + gpios = <&twl_gpio 19 0>; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +/* i2c2 pins are used for gpio */ +&i2c2 { + status = "disabled"; +}; + +/* on board microSD slot */ +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* optional on board WiFi */ +&mmc2 { + bus-width = <4>; +}; + +&twl_gpio { + ti,use-leds; +}; diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts new file mode 100644 index 000000000000..a13d12de77ff --- /dev/null +++ b/arch/arm/boot/dts/omap3-tobi.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +/include/ "omap3-overo.dtsi" + +/ { + model = "TI OMAP3 Gumstix Overo on Tobi"; + compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc3 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 810947198208..f38ea8771b44 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -17,7 +17,6 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; - serial3 = &uart4; }; cpus { @@ -69,6 +68,24 @@ reg = <0x48200000 0x1000>; }; + omap3_pmx_core: pinmux@48002030 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002030 0x05cc>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap3_pmx_wkup: pinmux@0x48002a58 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002a58 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; ti,hwmods = "gpio1"; @@ -141,12 +158,6 @@ clock-frequency = <48000000>; }; - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; #address-cells = <1>; @@ -220,5 +231,74 @@ compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@49022000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49022000 0xff>, + <0x49028000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <17>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>, /* RX interrupt */ + <4>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <1280>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@49024000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49024000 0xff>, + <0x4902a000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <22>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>, /* RX interrupt */ + <5>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@49026000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49026000 0xff>; + reg-names = "mpu"; + interrupts = <23>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <27>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi new file mode 100644 index 000000000000..96bf0287cb9f --- /dev/null +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -0,0 +1,25 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + }; + + ocp { + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 9880c12877b3..20b966ee1bb3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 PandaBoard"; @@ -126,3 +127,13 @@ ti,non-removable; bus-width = <4>; }; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 72216e932fc0..94a23b39033d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 SDP board"; @@ -18,7 +19,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - vdd_eth: fixedregulator@0 { + vdd_eth: fixedregulator-vdd-eth { compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; regulator-min-microvolt = <3300000>; @@ -28,7 +29,7 @@ regulator-boot-on; }; - vbat: fixedregulator@2 { + vbat: fixedregulator-vbat { compatible = "regulator-fixed"; regulator-name = "VBAT"; regulator-min-microvolt = <3750000>; @@ -115,6 +116,33 @@ }; }; +&omap4_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ + 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ + 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ + 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ + 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ + 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ + 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ + 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ + >; + }; +}; + &i2c1 { clock-frequency = <400000>; @@ -226,3 +254,98 @@ bus-width = <4>; ti,non-removable; }; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00000012 /* KEY_E */ + 0x00010013 /* KEY_R */ + 0x00020014 /* KEY_T */ + 0x00030066 /* KEY_HOME */ + 0x0004003f /* KEY_F5 */ + 0x000500f0 /* KEY_UNKNOWN */ + 0x00060017 /* KEY_I */ + 0x0007002a /* KEY_LEFTSHIFT */ + 0x01000020 /* KEY_D*/ + 0x01010021 /* KEY_F */ + 0x01020022 /* KEY_G */ + 0x010300e7 /* KEY_SEND */ + 0x01040040 /* KEY_F6 */ + 0x010500f0 /* KEY_UNKNOWN */ + 0x01060025 /* KEY_K */ + 0x0107001c /* KEY_ENTER */ + 0x0200002d /* KEY_X */ + 0x0201002e /* KEY_C */ + 0x0202002f /* KEY_V */ + 0x0203006b /* KEY_END */ + 0x02040041 /* KEY_F7 */ + 0x020500f0 /* KEY_UNKNOWN */ + 0x02060034 /* KEY_DOT */ + 0x0207003a /* KEY_CAPSLOCK */ + 0x0300002c /* KEY_Z */ + 0x0301004e /* KEY_KPLUS */ + 0x03020030 /* KEY_B */ + 0x0303003b /* KEY_F1 */ + 0x03040042 /* KEY_F8 */ + 0x030500f0 /* KEY_UNKNOWN */ + 0x03060018 /* KEY_O */ + 0x03070039 /* KEY_SPACE */ + 0x04000011 /* KEY_W */ + 0x04010015 /* KEY_Y */ + 0x04020016 /* KEY_U */ + 0x0403003c /* KEY_F2 */ + 0x04040073 /* KEY_VOLUMEUP */ + 0x040500f0 /* KEY_UNKNOWN */ + 0x04060026 /* KEY_L */ + 0x04070069 /* KEY_LEFT */ + 0x0500001f /* KEY_S */ + 0x05010023 /* KEY_H */ + 0x05020024 /* KEY_J */ + 0x0503003d /* KEY_F3 */ + 0x05040043 /* KEY_F9 */ + 0x05050072 /* KEY_VOLUMEDOWN */ + 0x05060032 /* KEY_M */ + 0x0507006a /* KEY_RIGHT */ + 0x06000010 /* KEY_Q */ + 0x0601001e /* KEY_A */ + 0x06020031 /* KEY_N */ + 0x0603009e /* KEY_BACK */ + 0x0604000e /* KEY_BACKSPACE */ + 0x060500f0 /* KEY_UNKNOWN */ + 0x06060019 /* KEY_P */ + 0x06070067 /* KEY_UP */ + 0x07000094 /* KEY_PROG1 */ + 0x07010095 /* KEY_PROG2 */ + 0x070200ca /* KEY_PROG3 */ + 0x070300cb /* KEY_PROG4 */ + 0x0704003e /* KEY_F4 */ + 0x070500f0 /* KEY_UNKNOWN */ + 0x07060160 /* KEY_OK */ + 0x0707006c>; /* KEY_DOWN */ + linux,input-no-autorepeat; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 8a780b2a5083..3883f94fdbd0 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -30,12 +30,35 @@ cpus { cpu@0 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; }; + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + + L2: l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@0x48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x20>; + interrupts = <1 13 0x304>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -61,30 +84,6 @@ /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. - * - * MPU -+-- MPU_PRIVATE - GIC, L2 - * | - * +----------------+----------+ - * | | | - * + +- EMIF - DDR | - * | | | - * | + +--------+ - * | | | - * | +- L4_ABE - AESS, MCBSP, TIMERs... - * | | - * +- L3_MAIN --+- L4_CORE - IPs... - * | - * +- L4_PER - IPs... - * | - * +- L4_CFG -+- L4_WKUP - IPs... - * | | - * | +- IPs... - * +- IPU ----+ - * | | - * +- DSP ----+ - * | | - * +- DSS ----+ - * * Since that will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. @@ -96,16 +95,27 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; + omap4_pmx_core: pinmux@4a100040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + omap4_pmx_wkup: pinmux@4a31e040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a31e040 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; }; gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; + reg = <0x4a310000 0x200>; + interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -115,6 +125,8 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = <0 30 0x4>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -124,6 +136,8 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = <0 31 0x4>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -133,6 +147,8 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = <0 32 0x4>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -142,6 +158,8 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = <0 33 0x4>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -151,6 +169,8 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = <0 34 0x4>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -160,30 +180,40 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -191,6 +221,8 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -198,6 +230,8 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -205,6 +239,8 @@ i2c4: i2c@48350000 { compatible = "ti,omap4-i2c"; + reg = <0x48350000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -212,6 +248,8 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; + reg = <0x48098000 0x200>; + interrupts = <0 65 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -220,6 +258,8 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; + reg = <0x4809a000 0x200>; + interrupts = <0 66 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -228,6 +268,8 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; + reg = <0x480b8000 0x200>; + interrupts = <0 91 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -236,6 +278,8 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; + reg = <0x480ba000 0x200>; + interrupts = <0 48 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -244,6 +288,8 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = <0 83 0x4>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -251,30 +297,40 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; }; mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; }; mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; }; mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d5000 0x400>; + interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; }; wdt2: wdt@4a314000 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x4a314000 0x80>; + interrupts = <0 80 0x4>; ti,hwmods = "wd_timer2"; }; @@ -282,6 +338,7 @@ compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; @@ -291,11 +348,89 @@ compatible = "ti,omap4-dmic"; reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@48096000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x48096000 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = <0 16 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + keypad: keypad@4a31c000 { + compatible = "ti,omap4-keypad"; + reg = <0x4a31c000 0x80>; + interrupts = <0 120 0x4>; + reg-names = "mpu"; + ti,hwmods = "kbd"; + }; + + emif1: emif@4c000000 { + compatible = "ti,emif-4d"; + reg = <0x4c000000 0x100>; + interrupts = <0 110 0x4>; + ti,hwmods = "emif1"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + + emif2: emif@4d000000 { + compatible = "ti,emif-4d"; + reg = <0x4d000000 0x100>; + interrupts = <0 111 0x4>; + ti,hwmods = "emif2"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + ocp2scp { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 200c39ad1c82..9c41a3f311aa 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -17,4 +17,68 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; + + vmmcsd_fixed: fixedregulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + + /* Pressure Sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + + /* Temperature Sensor */ + tmp102@48{ + compatible = "ti,tmp102"; + reg = <0x48>; + }; +}; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x02020073 /* VOLUP */ + 0x02030072 /* VOLDOWM */ + 0x020400e7 /* SEND */ + 0x02050066 /* HOME */ + 0x0206006b /* END */ + 0x020700d9>; /* SEARCH */ + linux,input-no-autorepeat; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e527083746..5db33f481a33 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,9 +33,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; }; @@ -145,6 +157,41 @@ #interrupt-cells = <1>; }; + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + i2c4: i2c@4807A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + }; + + i2c5: i2c@4807C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c5"; + }; + uart1: serial@4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; @@ -180,5 +227,97 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + }; + + mmc4: mmc@480d1000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc4"; + ti,needs-special-reset; + }; + + mmc5: mmc@480d5000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc5"; + ti,needs-special-reset; + }; + + keypad: keypad@4ae1c000 { + compatible = "ti,omap4-keypad"; + ti,hwmods = "kbd"; + }; + + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; + + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; }; }; diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..90fdbd77f274 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -135,13 +135,11 @@ ssp0: ssp@20084000 { #address-cells = <1>; #size-cells = <0>; - pl022,num-chipselects = <1>; + num-cs = <1>; cs-gpios = <&gpio 3 5 0>; eeprom: at25@0 { - pl022,hierarchy = <0>; pl022,interface = <0>; - pl022,slave-tx-disable = <0>; pl022,com-mode = <0>; pl022,rx-level-trig = <1>; pl022,tx-level-trig = <1>; @@ -191,16 +189,14 @@ leds { compatible = "gpio-leds"; - led0 { - gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */ - linux,default-trigger = "heartbeat"; + led0 { /* red */ + gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ default-state = "off"; }; - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; + led1 { /* green */ + gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ + linux,default-trigger = "heartbeat"; }; }; }; diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts deleted file mode 100644 index 34ae3a64ba25..000000000000 --- a/arch/arm/boot/dts/prima2-cb.dts +++ /dev/null @@ -1,424 +0,0 @@ -/dts-v1/; -/ { - model = "SiRF Prima2 eVB"; - compatible = "sirf,prima2-cb", "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; - linux,stdout-path = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - }; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { - compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - }; - - reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x10000>; - interrupts = <27>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x10000>; - interrupts = <17>; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x10000>; - interrupts = <18>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x10000>; - interrupts = <19>; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - }; - - gpio: gpio-controller@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-gpio-pinmux"; - reg = <0xb0120000 0x10000>; - gpio-controller; - interrupt-controller; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts new file mode 100644 index 000000000000..57286b4e7b87 --- /dev/null +++ b/arch/arm/boot/dts/prima2-evb.dts @@ -0,0 +1,37 @@ +/* + * DTS file for CSR SiRFprimaII Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "prima2.dtsi" + +/ { + model = "CSR SiRFprimaII Evaluation Board"; + compatible = "sirf,prima2", "sirf,prima2-cb"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + axi { + peri-iobg { + uart@b0060000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + }; + spi@b00d0000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + }; + spi@b0170000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi new file mode 100644 index 000000000000..055fca542120 --- /dev/null +++ b/arch/arm/boot/dts/prima2.dtsi @@ -0,0 +1,640 @@ +/* + * DTS file for CSR SiRFprimaII SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,prima2"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + l2-cache-controller@80040000 { + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + reg = <0x80040000 0x1000>; + interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; + }; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clock-controller@88000000 { + compatible = "sirf,prima2-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + display@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx531"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + multimedia@a0000000 { + compatible = "sirf,prima2-video-codec"; + reg = <0xa0000000 0x8000000>; + interrupts = <5>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x10000>; + interrupts = <17>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x10000>; + interrupts = <18>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x10000>; + interrupts = <19>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + }; + + usp2: usp@b00a0000 { + cell-index = <2>; + compatible = "sirf,prima2-usp"; + reg = <0xb00a0000 0x10000>; + interrupts = <22>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + }; + + gpio: pinctrl@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,prima2-pinctrl"; + reg = <0xb0120000 0x10000>; + interrupts = <43 44 45 46 47>; + gpio-controller; + interrupt-controller; + + lcd_16pins_a: lcd0@0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0@1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0@2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0@0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0@0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1@0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2@0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2@1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0@0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1@0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0@0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1@0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0@0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1@0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2@0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3@0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + gps_pins_a: gps@0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip@0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0@0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1@0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2@0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc3_pins_a: sdmmc3@0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc4_pins_a: sdmmc4@0 { + sdmmc4 { + sirf,pins = "sdmmc4grp"; + sirf,function = "sdmmc4"; + }; + }; + sdmmc5_pins_a: sdmmc5@0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s@0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + ac97_pins_a: ac97@0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand@0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0@0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1@0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usp2_pins_a: usp2@0 { + usp2 { + sirf,pins = "usp2grp"; + sirf,function = "usp2"; + }; + }; + usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { + usb0_utmi_drvbus { + sirf,pins = "usb0_utmi_drvbusgrp"; + sirf,function = "usb0_utmi_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst@0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count@0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst@0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst@0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + }; + + sd4: sdhci@56400000 { + cell-index = <4>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56400000 0x100000>; + interrupts = <39>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + }; + + sata@b00f0000 { + compatible = "synopsys,dwc-ahsata"; + reg = <0xb8020000 0x10000>; + interrupts = <37>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi new file mode 100644 index 000000000000..d7c5d721a5c7 --- /dev/null +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -0,0 +1,14 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA27x familiy SoC"; + compatible = "marvell,pxa27x"; + + pxabus { + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <34>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi new file mode 100644 index 000000000000..f18aad35e8b3 --- /dev/null +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -0,0 +1,132 @@ +/* + * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Marvell PXA2xx family SoC"; + compatible = "marvell,pxa2xx"; + interrupt-parent = <&pxairq>; + + aliases { + serial0 = &ffuart; + serial1 = &btuart; + serial2 = &stuart; + serial3 = &hwuart; + i2c0 = &pwri2c; + i2c1 = &pxai2c1; + }; + + cpus { + cpu@0 { + compatible = "arm,xscale"; + }; + }; + + pxabus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxairq: interrupt-controller@40d00000 { + #interrupt-cells = <1>; + compatible = "marvell,pxa-intc"; + interrupt-controller; + interrupt-parent; + marvell,intc-nr-irqs = <32>; + reg = <0x40d00000 0xd0>; + }; + + gpio: gpio@40e00000 { + compatible = "mrvl,pxa-gpio"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x40e00000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <10>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <0x2>; + ranges; + + gcb0: gpio@40e00000 { + reg = <0x40e00000 0x4>; + }; + + gcb1: gpio@40e00004 { + reg = <0x40e00004 0x4>; + }; + + gcb2: gpio@40e00008 { + reg = <0x40e00008 0x4>; + }; + gcb3: gpio@40e0000c { + reg = <0x40e0000c 0x4>; + }; + }; + + ffuart: uart@40100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40100000 0x30>; + interrupts = <22>; + status = "disabled"; + }; + + btuart: uart@40200000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40200000 0x30>; + interrupts = <21>; + status = "disabled"; + }; + + stuart: uart@40700000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40700000 0x30>; + interrupts = <20>; + status = "disabled"; + }; + + hwuart: uart@41100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x41100000 0x30>; + interrupts = <7>; + status = "disabled"; + }; + + pxai2c1: i2c@40301680 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40301680 0x30>; + interrupts = <18>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb0: ohci@4c000000 { + compatible = "mrvl,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + status = "disabled"; + }; + + mmc0: mmc@41100000 { + compatible = "mrvl,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + status = "disabled"; + }; + + rtc@40900000 { + compatible = "marvell,pxa-rtc"; + reg = <0x40900000 0x3c>; + interrupts = <30 31>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi new file mode 100644 index 000000000000..f9d92da86783 --- /dev/null +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -0,0 +1,32 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA3xx familiy SoC"; + compatible = "marvell,pxa3xx"; + + pxabus { + pwri2c: i2c@40f500c0 { + compatible = "mrvl,pwri2c"; + reg = <0x40f500c0 0x30>; + interrupts = <6>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + nand0: nand@43100000 { + compatible = "marvell,pxa3xx-nand"; + reg = <0x43100000 90>; + interrupts = <45>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <56>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..a3be44d86bcd 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -25,6 +25,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 7e334d4cae21..702c0baa6004 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "db8500.dtsi" +/include/ "dbx5x0.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -83,6 +83,22 @@ }; soc-u9500 { + + sound { + compatible = "stericsson,snd-soc-mop500"; + + stericsson,cpu-dai = <&msp1 &msp3>; + stericsson,audio-codec = <&codec>; + }; + + msp1: msp@80124000 { + status = "okay"; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + external-bus@50000000 { status = "okay"; @@ -111,7 +127,6 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; - #gpio-cells = <1>; cd-gpios = <&gpio6 26 0x4>; // 218 cd-inverted; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index f146dbf6f7f8..c3ef1ad26b6a 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -275,6 +275,160 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; pmc { @@ -310,6 +464,72 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; + /* Hack until board-harmony-pcie.c is removed */ + status = "disabled"; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-harmony", "nvidia,tegra-audio-wm8903"; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts new file mode 100644 index 000000000000..a2d6d6541f83 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Medcom-Wide board"; + compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-medcom-wide", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Medcom-Wide"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 684a9e1ff7e9..ddf287f52d49 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -272,12 +272,170 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&p5valw_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "+1.2vs_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "+1.0vs_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "+3.7vs_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "+1.1vs_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "+1.2vs_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "+3.3vs_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "+2.85vs_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + /* + * Research indicates this should be + * 1.8v; other boards that use this + * rail for the same purpose need it + * set to 1.8v. The schematic signal + * name is incorrect; perhaps copied + * from an incorrect NVIDIA reference. + */ + regulator-name = "+2.85vs_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "+3.3vs_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "+3.3vs_rtc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; + pmc { + nvidia,invert-interrupt; + }; + usb@c5000000 { status = "okay"; }; @@ -325,6 +483,21 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-alc5632-paz00", "nvidia,tegra-audio-alc5632"; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts new file mode 100644 index 000000000000..331a3ef24d59 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Plutux board"; + compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-plutux", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Plutux"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 85e621ab2968..e60dc7124e92 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -374,6 +374,154 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + temperature-sensor@4c { compatible = "nct1008"; reg = <0x4c>; @@ -387,6 +535,10 @@ }; }; + pmc { + nvidia,invert-interrupt; + }; + memory-controller@0x7000f400 { emc-table@190000 { reg = <190000>; @@ -473,6 +625,40 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-seaboard", "nvidia,tegra-audio-wm8903"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi new file mode 100644 index 000000000000..f18cec9f6a77 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -0,0 +1,449 @@ +/include/ "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + bus-width = <4>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts new file mode 100644 index 000000000000..9aff31b0fe4a --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-tec", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design TEC"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index be90544e6b59..3e5952fcfbc5 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -289,6 +289,158 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -317,6 +469,60 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-ventana", "nvidia,tegra-audio-wm8903"; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 6916310bf58f..c636d002d6d8 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -261,6 +261,286 @@ gpio-controller; #gpio-cells = <2>; }; + + max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + interrupts = <0 86 0x4>; + + maxim,system-power-controller; + + mbatt-supply = <&usb0_vbus_reg>; + in-v1-supply = <&mbatt_reg>; + in-v2-supply = <&mbatt_reg>; + in-v3-supply = <&mbatt_reg>; + in1-supply = <&mbatt_reg>; + in2-supply = <&nvvdd_sv3_reg>; + in3-supply = <&mbatt_reg>; + in4-supply = <&mbatt_reg>; + in5-supply = <&mbatt_reg>; + in6-supply = <&mbatt_reg>; + in7-supply = <&mbatt_reg>; + in8-supply = <&mbatt_reg>; + in9-supply = <&mbatt_reg>; + in10-supply = <&mbatt_reg>; + in11-supply = <&mbatt_reg>; + in12-supply = <&mbatt_reg>; + in13-supply = <&mbatt_reg>; + in14-supply = <&mbatt_reg>; + in15-supply = <&mbatt_reg>; + in16-supply = <&mbatt_reg>; + in17-supply = <&nvvdd_sv3_reg>; + in18-supply = <&nvvdd_sv3_reg>; + in19-supply = <&mbatt_reg>; + in20-supply = <&mbatt_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + mbatt_reg: regulator@0 { + reg = <0>; + regulator-compatible = "mbatt"; + regulator-name = "vbat_pmu"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sd1"; + regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sd2"; + regulator-name = "nvvdd_sv2,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + nvvdd_sv3_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sd3"; + regulator-name = "nvvdd_sv3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "nvvdd_ldo2,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; + regulator-name = "nvvdd_ldo3,vcom_1v8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "nvvdd_ldo4,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "nvvdd_ldo7,avddio_audio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; + regulator-name = "nvvdd_ldo9,avdd_cam*"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo10"; + regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo11"; + regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@15 { + reg = <15>; + regulator-compatible = "ldo12"; + regulator-name = "nvvdd_ldo12,vddio_sdio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@16 { + reg = <16>; + regulator-compatible = "ldo13"; + regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@17 { + reg = <17>; + regulator-compatible = "ldo14"; + regulator-name = "nvvdd_ldo14,avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@18 { + reg = <18>; + regulator-compatible = "ldo15"; + regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@19 { + reg = <19>; + regulator-compatible = "ldo16"; + regulator-name = "nvvdd_ldo16,vdd_dbrtr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + regulator@20 { + reg = <20>; + regulator-compatible = "ldo17"; + regulator-name = "nvvdd_ldo17,vddio_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@21 { + reg = <21>; + regulator-compatible = "ldo18"; + regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@22 { + reg = <22>; + regulator-compatible = "ldo19"; + regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@23 { + reg = <23>; + regulator-compatible = "ldo20"; + regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@24 { + reg = <24>; + regulator-compatible = "out5v"; + regulator-name = "usb0_vbus_reg"; + }; + + regulator@25 { + reg = <25>; + regulator-compatible = "out33v"; + regulator-name = "pmu_out3v3"; + }; + + regulator@26 { + reg = <26>; + regulator-compatible = "bbat"; + regulator-name = "pmu_bbat"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2400000>; + regulator-always-on; + }; + + regulator@27 { + reg = <27>; + regulator-compatible = "sdby"; + regulator-name = "vdd_aon"; + regulator-always-on; + }; + + regulator@28 { + reg = <28>; + regulator-compatible = "vrtc"; + regulator-name = "vrtc,pmu_vccadc"; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -284,6 +564,21 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb0_vbus_reg: regulator { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8753-whistler", "nvidia,tegra-audio-wm8753"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 405d1673904e..67a6cd910b96 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -123,7 +123,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts new file mode 100644 index 000000000000..dd4222f00eca --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -0,0 +1,87 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A02 version of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; + compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 68 0>; /* GPIO PI4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 63 0>; /* GPIO PH7 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 83 0>; /* GPIO PK3 */ + }; + }; +}; + diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts new file mode 100644 index 000000000000..0828f097ca86 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -0,0 +1,98 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A04 and later versions of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; + compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + reg = <100>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 238 0>; /* GPIO PDD6 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 236 0>; /* GPIO PDD4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 234 0>; /* GPIO PDD2 */ + }; + + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + reg = <106>; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 232 0>; /* GPIO PDD0 */ + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts deleted file mode 100644 index c169bced131e..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu.dts +++ /dev/null @@ -1,171 +0,0 @@ -/dts-v1/; - -/include/ "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - clock-frequency = <408000000>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <88 0x04>; /*gpio PL0 */ - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = <179 0x04>; /* gpio PW3 */ - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - tps62361 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - }; - - ahub { - i2s@70080400 { - status = "okay"; - }; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi new file mode 100644 index 000000000000..d10c9c5a3606 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -0,0 +1,475 @@ +/include/ "tegra30.dtsi" + +/** + * This file contains common DT entry for all fab version of Cardhu. + * There is multiple fab version of Cardhu starting from A01 to A07. + * Cardhu fab version A01 and A03 are not supported. Cardhu fab version + * A02 will have different sets of GPIOs for fixed regulator compare to + * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are + * compatible with fab version A04. Based on Cardhu fab version, the + * related dts file need to be chosen like for Cardhu fab version A02, + * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use + * tegra30-cardhu-a04.dts. + * The identification of board is done in two ways, by looking the sticker + * on PCB and by reading board id eeprom. + * The stciker will have number like 600-81291-1000-002 C.3. In this 4th + * number is the fab version like here it is 002 and hence fab version A02. + * The (downstream internal) U-Boot of Cardhu display the board-id as + * follows: + * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 + * In this Fab version is 02 i.e. A02. + * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). + * The location 0x8 of this eeprom contains the Fab version. It is 1 byte + * wide. + */ + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + }; + }; + + serial@70006000 { + status = "okay"; + clock-frequency = <408000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + + /* ALS and Proximity sensor */ + isl29028@44 { + compatible = "isil,isl29028"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <88 0x04>; /*gpio PL0 */ + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <179 0x04>; /* gpio PW3 */ + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + tps62361 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <0 86 0x4>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vdd1"; + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vdd2"; + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vddctrl"; + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vio"; + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + ahub { + i2s@70080400 { + status = "okay"; + }; + }; + + pmc { + status = "okay"; + nvidia,invert-interrupt; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio 220 0>; /* gpio PBB4 */ + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ + }; + + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 25 0>; /* gpio PD1 */ + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 30 0>; /* gpio PD6 */ + }; + + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 95 0>; /* gpio PL7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 142 0>; /* gpio PR6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 143 0>; /* gpio PR7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 144 0>; /* gpio PS0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 24 0>; /* gpio PD0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 94 0>; /* gpio PL6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 92 0>; /* gpio PL4 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 152 0>; /* GPIO PT0 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-cardhu", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Cardhu"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 3e4334d14efb..b1497c7d7d68 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -117,7 +117,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi new file mode 100644 index 000000000000..a63272422d76 --- /dev/null +++ b/arch/arm/boot/dts/tps65217.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65217.pdf + */ + +&tps { + compatible = "ti,tps65217"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; + }; + }; +}; diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi new file mode 100644 index 000000000000..92693a89160e --- /dev/null +++ b/arch/arm/boot/dts/tps65910.dtsi @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65910.pdf + */ + +&tps { + compatible = "ti,tps65910"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vrtc_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vrtc"; + }; + + vio_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vio"; + }; + + vdd1_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vdd1"; + }; + + vdd2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vdd2"; + }; + + vdd3_reg: regulator@4 { + reg = <4>; + regulator-compatible = "vdd3"; + }; + + vdig1_reg: regulator@5 { + reg = <5>; + regulator-compatible = "vdig1"; + }; + + vdig2_reg: regulator@6 { + reg = <6>; + regulator-compatible = "vdig2"; + }; + + vpll_reg: regulator@7 { + reg = <7>; + regulator-compatible = "vpll"; + }; + + vdac_reg: regulator@8 { + reg = <8>; + regulator-compatible = "vdac"; + }; + + vaux1_reg: regulator@9 { + reg = <9>; + regulator-compatible = "vaux1"; + }; + + vaux2_reg: regulator@10 { + reg = <10>; + regulator-compatible = "vaux2"; + }; + + vaux33_reg: regulator@11 { + reg = <11>; + regulator-compatible = "vaux33"; + }; + + vmmc_reg: regulator@12 { + reg = <12>; + regulator-compatible = "vmmc"; + }; + }; +}; diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 22f4d1394ed3..ff000172c93c 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -19,19 +19,19 @@ interrupts = <11>; }; - vdac: regulator@0 { + vdac: regulator-vdac { compatible = "ti,twl4030-vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vpll2: regulator@1 { + vpll2: regulator-vpll2 { compatible = "ti,twl4030-vpll2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vmmc1: regulator@2 { + vmmc1: regulator-vmmc1 { compatible = "ti,twl4030-vmmc1"; regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..123e2c40218a 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi @@ -20,70 +20,70 @@ interrupts = <11>; }; - vaux1: regulator@0 { + vaux1: regulator-vaux1 { compatible = "ti,twl6030-vaux1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vaux2: regulator@1 { + vaux2: regulator-vaux2 { compatible = "ti,twl6030-vaux2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2800000>; }; - vaux3: regulator@2 { + vaux3: regulator-vaux3 { compatible = "ti,twl6030-vaux3"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vmmc: regulator@3 { + vmmc: regulator-vmmc { compatible = "ti,twl6030-vmmc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; }; - vpp: regulator@4 { + vpp: regulator-vpp { compatible = "ti,twl6030-vpp"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2500000>; }; - vusim: regulator@5 { + vusim: regulator-vusim { compatible = "ti,twl6030-vusim"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2900000>; }; - vdac: regulator@6 { + vdac: regulator-vdac { compatible = "ti,twl6030-vdac"; }; - vana: regulator@7 { + vana: regulator-vana { compatible = "ti,twl6030-vana"; }; - vcxio: regulator@8 { + vcxio: regulator-vcxio { compatible = "ti,twl6030-vcxio"; regulator-always-on; }; - vusb: regulator@9 { + vusb: regulator-vusb { compatible = "ti,twl6030-vusb"; }; - v1v8: regulator@10 { + v1v8: regulator-v1v8 { compatible = "ti,twl6030-v1v8"; regulator-always-on; }; - v2v1: regulator@11 { + v2v1: regulator-v2v1 { compatible = "ti,twl6030-v2v1"; regulator-always-on; }; - clk32kg: regulator@12 { + clk32kg: regulator-clk32kg { compatible = "ti,twl6030-clk32kg"; }; }; diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts new file mode 100644 index 000000000000..567cf4e8ab84 --- /dev/null +++ b/arch/arm/boot/dts/vt8500-bv07.dts @@ -0,0 +1,36 @@ +/* + * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "vt8500.dtsi" + +/ { + model = "Benign BV07 Netbook"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <16>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi new file mode 100644 index 000000000000..d8645e990b21 --- /dev/null +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -0,0 +1,116 @@ +/* + * vt8500.dtsi - Device tree file for VIA VT8500 SoC + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "via,vt8500"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + intc: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "via,vt8500-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + fb@d800e400 { + compatible = "via,vt8500-fb"; + reg = <0xd800e400 0x400>; + interrupts = <12>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&ref24>; + }; + + uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts new file mode 100644 index 000000000000..fd4e248074c6 --- /dev/null +++ b/arch/arm/boot/dts/wm8505-ref.dts @@ -0,0 +1,36 @@ +/* + * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8505.dtsi" + +/ { + model = "Wondermedia WM8505 Netbook"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <32>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi new file mode 100644 index 000000000000..b459691655ab --- /dev/null +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -0,0 +1,143 @@ +/* + * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8505"; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8505-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007100 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007100 0x200>; + interrupts = <43>; + }; + + uhci@d8007300 { + compatible = "platform-uhci"; + reg = <0xd8007300 0x200>; + interrupts = <43>; + }; + + fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&ref24>; + }; + + uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&ref24>; + }; + + uart@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <31>; + clocks = <&ref24>; + }; + + uart@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <30>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts new file mode 100644 index 000000000000..cefd938f842f --- /dev/null +++ b/arch/arm/boot/dts/wm8650-mid.dts @@ -0,0 +1,36 @@ +/* + * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8650.dtsi" + +/ { + model = "Wondermedia WM8650-MID Tablet"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <16>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi new file mode 100644 index 000000000000..83b9467559bb --- /dev/null +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -0,0 +1,147 @@ +/* + * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8650"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8650-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + arm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + sdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x328>; + divisor-mask = <0x3f>; + enable-reg = <0x254>; + enable-bit = <18>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index 7d8718468e0d..90610c7030f7 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig @@ -33,7 +33,7 @@ CONFIG_AEABI=y CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096" +CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw" CONFIG_CMDLINE_FORCE=y CONFIG_KEXEC=y CONFIG_VFP=y diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig new file mode 100644 index 000000000000..7aea70253c63 --- /dev/null +++ b/arch/arm/configs/bcm2835_defconfig @@ -0,0 +1,95 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_PERF=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_JUMP_LABEL=y +# CONFIG_BLOCK is not set +CONFIG_ARCH_BCM2835=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_CLEANCACHE=y +CONFIG_SECCOMP=y +CONFIG_CC_STACKPROTECTOR=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_TTY_PRINTK=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_TEST_KSTRTOX=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig deleted file mode 100644 index 9e6a8fe13164..000000000000 --- a/arch/arm/configs/bcmring_defconfig +++ /dev/null @@ -1,79 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_HOTPLUG is not set -# CONFIG_ELF_CORE is not set -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set -CONFIG_PERF_EVENTS=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_BCMRING=y -CONFIG_BCM_ZRELADDR=0x8000 -CONFIG_CPU_32v6K=y -CONFIG_NO_HZ=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_ZBOOT_ROM_TEXT=0x0e000000 -CONFIG_ZBOOT_ROM_BSS=0x0ea00000 -CONFIG_ZBOOT_ROM=y -CONFIG_NET=y -# CONFIG_WIRELESS is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y -CONFIG_MTD_NAND_BCM_UMI=y -CONFIG_MTD_NAND_BCM_UMI_HWCS=y -# CONFIG_MISC_DEVICES is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_CONSOLE_TRANSLATIONS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_LEGACY_PTY_COUNT=64 -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_FILE_LOCKING is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -# CONFIG_JFFS2_FS_SECURITY is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_HEADERS_CHECK=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 3c9f32f9b6b4..565132d02105 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y CONFIG_MACH_IMX51_DT=y CONFIG_MACH_MX51_3DS=y CONFIG_MACH_EUKREA_CPUIMX51SD=y -CONFIG_MACH_MX51_EFIKAMX=y -CONFIG_MACH_MX51_EFIKASB=y -CONFIG_MACH_IMX53_DT=y +CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_MXC_PWM=y CONFIG_SMP=y diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig index 26146ffea1a5..8c49df66cac3 100644 --- a/arch/arm/configs/kzm9d_defconfig +++ b/arch/arm/configs/kzm9d_defconfig @@ -8,6 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16 CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index 2388c8610627..5d0c66708960 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig @@ -14,6 +14,7 @@ CONFIG_NAMESPACES=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 4edcfb4e4dee..36d60dda310c 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_MXS=y CONFIG_MACH_MXS_DT=y -CONFIG_MACH_MX23EVK=y -CONFIG_MACH_MX28EVK=y -CONFIG_MACH_STMP378X_DEVB=y -CONFIG_MACH_TX28=y -CONFIG_MACH_M28EVK=y -CONFIG_MACH_APX4DEVKIT=y # CONFIG_ARM_THUMB is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index e58edc36b406..62303043db9c 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y CONFIG_I2C_CHARDEV=y CONFIG_SPI=y CONFIG_SPI_OMAP24XX=y +CONFIG_PINCTRL_SINGLE=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_TWL4030=y diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig deleted file mode 100644 index 35a31ccacc32..000000000000 --- a/arch/arm/configs/pnx4008_defconfig +++ /dev/null @@ -1,472 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_AUDIT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_ARCH_PNX4008=y -CONFIG_PREEMPT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="mem=64M console=ttyS0,115200" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=m -CONFIG_PM=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_IPV6_PRIVACY=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETFILTER=y -CONFIG_IP_VS=m -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_IP_SCTP=m -CONFIG_ATM=y -CONFIG_ATM_CLIP=y -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m -CONFIG_LLC2=m -CONFIG_IPX=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_IPDDP_DECAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_ECONET=m -CONFIG_ECONET_AUNUDP=y -CONFIG_ECONET_NATIVE=y -CONFIG_WAN_ROUTER=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_PKTGEN=m -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_SLRAM=m -CONFIG_MTD_PHRAM=m -CONFIG_MTD_MTDRAM=m -CONFIG_MTD_DOC2000=m -CONFIG_MTD_DOC2001=m -CONFIG_MTD_DOC2001PLUS=m -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_NANDSIM=m -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_CDROM_PKTCDVD=m -CONFIG_EEPROM_LEGACY=m -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_DEBUG=m -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_NET_ETHERNET=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=m -# CONFIG_USB_NET_CDC_SUBSET is not set -CONFIG_WAN=y -CONFIG_HDLC=m -CONFIG_HDLC_RAW=m -CONFIG_HDLC_RAW_ETH=m -CONFIG_HDLC_CISCO=m -CONFIG_HDLC_FR=m -CONFIG_HDLC_PPP=m -CONFIG_HDLC_X25=m -CONFIG_DLCI=m -CONFIG_WAN_ROUTER_DRIVERS=m -CONFIG_LAPBETHER=m -CONFIG_X25_ASY=m -CONFIG_ATM_TCP=m -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPPOATM=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NETCONSOLE=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -CONFIG_KEYBOARD_LKKBD=m -CONFIG_KEYBOARD_NEWTON=m -CONFIG_KEYBOARD_SUNKBD=m -CONFIG_KEYBOARD_XTKBD=m -CONFIG_MOUSE_PS2=m -CONFIG_MOUSE_SERIAL=m -CONFIG_MOUSE_VSXXXAA=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_IFORCE_USB=y -CONFIG_JOYSTICK_IFORCE_232=y -CONFIG_JOYSTICK_WARRIOR=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_GUNZE=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_RAW=m -CONFIG_GAMEPORT_NS558=m -CONFIG_GAMEPORT_L4=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_USBPCWATCHDOG=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_DUMMY=m -CONFIG_SND_VIRMIDI=m -CONFIG_SND_MTPAV=m -CONFIG_SND_SERIAL_U16550=m -CONFIG_SND_MPU401=m -CONFIG_SND_USB_AUDIO=m -CONFIG_SOUND_PRIME=m -CONFIG_USB_HID=m -CONFIG_USB_HIDDEV=y -CONFIG_USB_KBD=m -CONFIG_USB_MOUSE=m -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_MON=y -CONFIG_USB_SL811_HCD=m -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_RIO500=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_LED=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_TEST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DUMMY_HCD=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_MMC=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=m -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_AUTOFS_FS=m -CONFIG_AUTOFS4_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_TMPFS=y -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=m -CONFIG_CRAMFS=y -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V4=y -CONFIG_RPCSEC_GSS_SPKM3=m -CONFIG_SMB_FS=m -CONFIG_CIFS=m -CONFIG_NCP_FS=m -CONFIG_NCPFS_PACKET_SIGNING=y -CONFIG_NCPFS_IOCTL_LOCKING=y -CONFIG_NCPFS_STRONG=y -CONFIG_NCPFS_NFS_NS=y -CONFIG_NCPFS_OS2_NS=y -CONFIG_NCPFS_NLS=y -CONFIG_NCPFS_EXTRAS=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_SECURITY=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRC16=m diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index c328ac65479a..807d4e2acb17 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -1,4 +1,6 @@ CONFIG_EXPERIMENTAL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_ARCH_PRIMA2=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_ARCH_SIRF=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y @@ -36,7 +36,6 @@ CONFIG_SPI=y CONFIG_SPI_SIRF=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set -# CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_USB_FILE_STORAGE=m CONFIG_USB_MASS_STORAGE=m diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index db2245353f0f..0d6bb738c6de 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_TEGRA=y +CONFIG_DMADEVICES=y +CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 03fb93621d0d..5c8b3bf4d825 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -320,4 +320,12 @@ .size \name , . - \name .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req +#ifndef CONFIG_CPU_USE_DOMAINS + adds \tmp, \addr, #\size - 1 + sbcccs \tmp, \tmp, \limit + bcs \bad +#endif + .endm + #endif /* __ASM_ASSEMBLER_H__ */ diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 2ae842df4551..5c44dcb0987b 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -203,6 +203,13 @@ static inline void dma_free_writecombine(struct device *dev, size_t size, } /* + * This can be called during early boot to increase the size of the atomic + * coherent DMA pool above the default value of 256KiB. It must be called + * before postcore_initcall. + */ +extern void __init init_dma_coherent_pool_size(unsigned long size); + +/* * This can be called during boot to increase the size of the consistent * DMA region above it's default value of 2MB. It must be called before the * memory allocator is initialised, i.e. before any core_initcall. diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17ca905b..295e2e40151b 100644 --- a/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -8,4 +8,7 @@ * warranty of any kind, whether express or implied. */ -extern void __init tauros2_init(void); +#define CACHE_TAUROS2_PREFETCH_ON (1 << 0) +#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + +extern void __init tauros2_init(unsigned int features); diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 2ff2c75a4639..02fe2fbe2477 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void); #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 -#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 -#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ - IOP3XX_PCI_IO_WINDOW_SIZE - 1) -#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ - IOP3XX_PCI_LOWER_IO_PA) +\ - IOP3XX_PCI_LOWER_IO_VA) - +#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 815c669fec0a..8f4db67533e5 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif +/* PCI fixed i/o mapping */ +#define PCI_IO_VIRT_BASE 0xfee00000 + +extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); + /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include <mach/io.h> +#elif defined(CONFIG_PCI) +#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) +#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index a6efcdd6fd25..195ac2f9d3d3 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -9,6 +9,9 @@ * * Page table mapping constructs and function prototypes */ +#ifndef __ASM_MACH_MAP_H +#define __ASM_MACH_MAP_H + #include <asm/io.h> struct map_desc { @@ -34,6 +37,8 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); +extern void vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) +#define vm_reserve_area_early(a,s,c) do { } while (0) +#endif + #endif diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 26c511fddf8f..db9fedb57f2c 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -11,6 +11,8 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H +#include <linux/ioport.h> + struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -42,6 +44,8 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ + struct resource io_res; + char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ @@ -55,6 +59,15 @@ struct pci_sys_data { void pci_common_init(struct hw_pci *); /* + * Setup early fixed I/O mapping. + */ +#if defined(CONFIG_PCI) +extern void pci_map_io_early(unsigned long pfn); +#else +static inline void pci_map_io_early(unsigned long pfn) {} +#endif + +/* * PCI controllers */ extern struct pci_ops iop3xx_ops; diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index e965f1b560f1..5f6ddcc56452 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -187,6 +187,7 @@ static inline unsigned long __phys_to_virt(unsigned long x) #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) #endif #endif +#endif /* __ASSEMBLY__ */ #ifndef PHYS_OFFSET #ifdef PLAT_PHYS_OFFSET @@ -196,6 +197,8 @@ static inline unsigned long __phys_to_virt(unsigned long x) #endif #endif +#ifndef __ASSEMBLY__ + /* * PFNs are used to describe any physical page; this means * PFN 0 == physical address 0. diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index e074948d8143..625cd621a436 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -12,6 +12,13 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ -/* Nothing to see here... */ +/* + * The ARMv7 CPU PMU supports up to 32 event counters. + */ +#define ARMPMU_MAX_HWEVENTS 32 + +#define HW_OP_UNSUPPORTED 0xFFFF +#define C(_x) PERF_COUNT_HW_CACHE_##_x +#define CACHE_OP_UNSUPPORTED 0xFFFF #endif /* __ARM_PERF_EVENT_H__ */ diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index 4432305f4a2a..a26170dce02e 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h @@ -16,69 +16,30 @@ #include <linux/perf_event.h> /* - * Types of PMUs that can be accessed directly and require mutual - * exclusion between profiling tools. - */ -enum arm_pmu_type { - ARM_PMU_DEVICE_CPU = 0, - ARM_NUM_PMU_DEVICES, -}; - -/* * struct arm_pmu_platdata - ARM PMU platform data * * @handle_irq: an optional handler which will be called from the * interrupt and passed the address of the low level handler, * and can be used to implement any platform specific handling * before or after calling it. - * @enable_irq: an optional handler which will be called after - * request_irq and be used to handle some platform specific - * irq enablement - * @disable_irq: an optional handler which will be called before - * free_irq and be used to handle some platform specific - * irq disablement + * @runtime_resume: an optional handler which will be called by the + * runtime PM framework following a call to pm_runtime_get(). + * Note that if pm_runtime_get() is called more than once in + * succession this handler will only be called once. + * @runtime_suspend: an optional handler which will be called by the + * runtime PM framework following a call to pm_runtime_put(). + * Note that if pm_runtime_get() is called more than once in + * succession this handler will only be called following the + * final call to pm_runtime_put() that actually disables the + * hardware. */ struct arm_pmu_platdata { irqreturn_t (*handle_irq)(int irq, void *dev, irq_handler_t pmu_handler); - void (*enable_irq)(int irq); - void (*disable_irq)(int irq); + int (*runtime_resume)(struct device *dev); + int (*runtime_suspend)(struct device *dev); }; -#ifdef CONFIG_CPU_HAS_PMU - -/** - * reserve_pmu() - reserve the hardware performance counters - * - * Reserve the hardware performance counters in the system for exclusive use. - * Returns 0 on success or -EBUSY if the lock is already held. - */ -extern int -reserve_pmu(enum arm_pmu_type type); - -/** - * release_pmu() - Relinquish control of the performance counters - * - * Release the performance counters and allow someone else to use them. - */ -extern void -release_pmu(enum arm_pmu_type type); - -#else /* CONFIG_CPU_HAS_PMU */ - -#include <linux/err.h> - -static inline int -reserve_pmu(enum arm_pmu_type type) -{ - return -ENODEV; -} - -static inline void -release_pmu(enum arm_pmu_type type) { } - -#endif /* CONFIG_CPU_HAS_PMU */ - #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ @@ -103,7 +64,6 @@ struct pmu_hw_events { struct arm_pmu { struct pmu pmu; - enum arm_pmu_type type; cpumask_t active_irqs; char *name; irqreturn_t (*handle_irq)(int irq_num, void *dev); @@ -118,6 +78,8 @@ struct arm_pmu { void (*start)(void); void (*stop)(void); void (*reset)(void *); + int (*request_irq)(irq_handler_t handler); + void (*free_irq)(void); int (*map_event)(struct perf_event *event); int num_events; atomic_t active_events; @@ -129,7 +91,9 @@ struct arm_pmu { #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) -int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); +extern const struct dev_pm_ops armpmu_dev_pm_ops; + +int armpmu_register(struct arm_pmu *armpmu, char *name, int type); u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, @@ -139,6 +103,13 @@ int armpmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx); +int armpmu_map_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask); + #endif /* CONFIG_HW_PERF_EVENTS */ #endif /* __ARM_PMU_H__ */ diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index 314d4664eae7..99a19512ee26 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -199,6 +199,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, { pgtable_page_dtor(pte); +#ifdef CONFIG_ARM_LPAE + tlb_add_flush(tlb, addr); +#else /* * With the classic ARM MMU, a pte page has two corresponding pmd * entries, each covering 1MB. @@ -206,6 +209,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, addr &= PMD_MASK; tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); tlb_add_flush(tlb, addr + SZ_1M); +#endif tlb_remove_page(tlb, pte); } diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 479a6352e0b5..77bd79f2ffdb 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -101,28 +101,39 @@ extern int __get_user_1(void *); extern int __get_user_2(void *); extern int __get_user_4(void *); -#define __get_user_x(__r2,__p,__e,__s,__i...) \ +#define __GUP_CLOBBER_1 "lr", "cc" +#ifdef CONFIG_CPU_USE_DOMAINS +#define __GUP_CLOBBER_2 "ip", "lr", "cc" +#else +#define __GUP_CLOBBER_2 "lr", "cc" +#endif +#define __GUP_CLOBBER_4 "lr", "cc" + +#define __get_user_x(__r2,__p,__e,__l,__s) \ __asm__ __volatile__ ( \ __asmeq("%0", "r0") __asmeq("%1", "r2") \ + __asmeq("%3", "r1") \ "bl __get_user_" #__s \ : "=&r" (__e), "=r" (__r2) \ - : "0" (__p) \ - : __i, "cc") + : "0" (__p), "r" (__l) \ + : __GUP_CLOBBER_##__s) -#define get_user(x,p) \ +#define __get_user_check(x,p) \ ({ \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ register unsigned long __r2 asm("r2"); \ + register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ switch (sizeof(*(__p))) { \ case 1: \ - __get_user_x(__r2, __p, __e, 1, "lr"); \ - break; \ + __get_user_x(__r2, __p, __e, __l, 1); \ + break; \ case 2: \ - __get_user_x(__r2, __p, __e, 2, "r3", "lr"); \ + __get_user_x(__r2, __p, __e, __l, 2); \ break; \ case 4: \ - __get_user_x(__r2, __p, __e, 4, "lr"); \ + __get_user_x(__r2, __p, __e, __l, 4); \ break; \ default: __e = __get_user_bad(); break; \ } \ @@ -130,42 +141,57 @@ extern int __get_user_4(void *); __e; \ }) +#define get_user(x,p) \ + ({ \ + might_fault(); \ + __get_user_check(x,p); \ + }) + extern int __put_user_1(void *, unsigned int); extern int __put_user_2(void *, unsigned int); extern int __put_user_4(void *, unsigned int); extern int __put_user_8(void *, unsigned long long); -#define __put_user_x(__r2,__p,__e,__s) \ +#define __put_user_x(__r2,__p,__e,__l,__s) \ __asm__ __volatile__ ( \ __asmeq("%0", "r0") __asmeq("%2", "r2") \ + __asmeq("%3", "r1") \ "bl __put_user_" #__s \ : "=&r" (__e) \ - : "0" (__p), "r" (__r2) \ + : "0" (__p), "r" (__r2), "r" (__l) \ : "ip", "lr", "cc") -#define put_user(x,p) \ +#define __put_user_check(x,p) \ ({ \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __r2 asm("r2") = (x); \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ + register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ switch (sizeof(*(__p))) { \ case 1: \ - __put_user_x(__r2, __p, __e, 1); \ + __put_user_x(__r2, __p, __e, __l, 1); \ break; \ case 2: \ - __put_user_x(__r2, __p, __e, 2); \ + __put_user_x(__r2, __p, __e, __l, 2); \ break; \ case 4: \ - __put_user_x(__r2, __p, __e, 4); \ + __put_user_x(__r2, __p, __e, __l, 4); \ break; \ case 8: \ - __put_user_x(__r2, __p, __e, 8); \ + __put_user_x(__r2, __p, __e, __l, 8); \ break; \ default: __e = __put_user_bad(); break; \ } \ __e; \ }) +#define put_user(x,p) \ + ({ \ + might_fault(); \ + __put_user_check(x,p); \ + }) + #else /* CONFIG_MMU */ /* @@ -219,6 +245,7 @@ do { \ unsigned long __gu_addr = (unsigned long)(ptr); \ unsigned long __gu_val; \ __chk_user_ptr(ptr); \ + might_fault(); \ switch (sizeof(*(ptr))) { \ case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ @@ -300,6 +327,7 @@ do { \ unsigned long __pu_addr = (unsigned long)(ptr); \ __typeof__(*(ptr)) __pu_val = (x); \ __chk_user_ptr(ptr); \ + might_fault(); \ switch (sizeof(*(ptr))) { \ case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 0cab47d4a83f..2fde5fd1acce 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -404,6 +404,7 @@ #define __NR_setns (__NR_SYSCALL_BASE+375) #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) + /* 378 for kcmp */ /* * The following SWIs are ARM private. @@ -483,6 +484,7 @@ */ #define __IGNORE_fadvise64_64 #define __IGNORE_migrate_pages +#define __IGNORE_kcmp #endif /* __KERNEL__ */ #endif /* __ASM_ARM_UNISTD_H */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 8951577c4ced..d81f3a6d9ad8 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -68,8 +68,7 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o -obj-$(CONFIG_CPU_HAS_PMU) += pmu.o -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2b2f25e7fef5..9b722612553d 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -13,6 +13,7 @@ #include <linux/io.h> #include <asm/mach-types.h> +#include <asm/mach/map.h> #include <asm/mach/pci.h> static int debug_pci; @@ -270,15 +271,6 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); - - -void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) -{ - if (debug_pci) - printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. Currently this is CyberPro 20x0 only. @@ -423,6 +415,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } +static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) +{ + int ret; + struct pci_host_bridge_window *window; + + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); + } + + list_for_each_entry(window, &sys->resources, list) { + if (resource_type(window->res) == IORESOURCE_IO) + return 0; + } + + sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; + sys->io_res.end = (busnr + 1) * SZ_64K - 1; + sys->io_res.flags = IORESOURCE_IO; + sys->io_res.name = sys->io_res_name; + sprintf(sys->io_res_name, "PCI%d I/O", busnr); + + ret = request_resource(&ioport_resource, &sys->io_res); + if (ret) { + pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); + return ret; + } + pci_add_resource_offset(&sys->resources, &sys->io_res, + sys->io_offset); + + return 0; +} + static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -445,11 +469,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); + ret = pcibios_init_resources(nr, sys); + if (ret) { + kfree(sys); + break; } if (hw->scan) @@ -627,3 +650,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } + +void __init pci_map_io_early(unsigned long pfn) +{ + struct map_desc pci_io_desc = { + .virtual = PCI_IO_VIRT_BASE, + .type = MT_DEVICE, + .length = SZ_64K, + }; + + pci_io_desc.pfn = pfn; + iotable_init(&pci_io_desc, 1); +} diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 463ff4a0ec8a..e337879595e5 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -387,6 +387,7 @@ /* 375 */ CALL(sys_setns) CALL(sys_process_vm_readv) CALL(sys_process_vm_writev) + CALL(sys_ni_syscall) /* reserved for sys_kcmp */ #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index ba386bd94107..281bf3301241 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -159,6 +159,12 @@ static int debug_arch_supported(void) arch >= ARM_DEBUG_ARCH_V7_1; } +/* Can we determine the watchpoint access type from the fsr? */ +static int debug_exception_updates_fsr(void) +{ + return 0; +} + /* Determine number of WRP registers available. */ static int get_num_wrp_resources(void) { @@ -604,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) /* Aligned */ break; case 1: - /* Allow single byte watchpoint. */ - if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) - break; case 2: /* Allow halfword watchpoints and breakpoints. */ if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) break; + case 3: + /* Allow single byte watchpoint. */ + if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) + break; default: ret = -EINVAL; goto out; @@ -619,18 +626,35 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) info->address &= ~alignment_mask; info->ctrl.len <<= offset; - /* - * Currently we rely on an overflow handler to take - * care of single-stepping the breakpoint when it fires. - * In the case of userspace breakpoints on a core with V7 debug, - * we can use the mismatch feature as a poor-man's hardware - * single-step, but this only works for per-task breakpoints. - */ - if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) || - !core_has_mismatch_brps() || !bp->hw.bp_target)) { - pr_warning("overflow handler required but none found\n"); - ret = -EINVAL; + if (!bp->overflow_handler) { + /* + * Mismatch breakpoints are required for single-stepping + * breakpoints. + */ + if (!core_has_mismatch_brps()) + return -EINVAL; + + /* We don't allow mismatch breakpoints in kernel space. */ + if (arch_check_bp_in_kernelspace(bp)) + return -EPERM; + + /* + * Per-cpu breakpoints are not supported by our stepping + * mechanism. + */ + if (!bp->hw.bp_target) + return -EINVAL; + + /* + * We only support specific access types if the fsr + * reports them. + */ + if (!debug_exception_updates_fsr() && + (info->ctrl.type == ARM_BREAKPOINT_LOAD || + info->ctrl.type == ARM_BREAKPOINT_STORE)) + return -EINVAL; } + out: return ret; } @@ -706,10 +730,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, goto unlock; /* Check that the access type matches. */ - access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W : - HW_BREAKPOINT_R; - if (!(access & hw_breakpoint_type(wp))) - goto unlock; + if (debug_exception_updates_fsr()) { + access = (fsr & ARM_FSR_ACCESS_MASK) ? + HW_BREAKPOINT_W : HW_BREAKPOINT_R; + if (!(access & hw_breakpoint_type(wp))) + goto unlock; + } /* We have a winner. */ info->trigger = addr; diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index ab243b87118d..93971b1a4f0b 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -12,68 +12,15 @@ */ #define pr_fmt(fmt) "hw perfevents: " fmt -#include <linux/bitmap.h> -#include <linux/interrupt.h> #include <linux/kernel.h> -#include <linux/export.h> -#include <linux/perf_event.h> #include <linux/platform_device.h> -#include <linux/spinlock.h> +#include <linux/pm_runtime.h> #include <linux/uaccess.h> -#include <asm/cputype.h> -#include <asm/irq.h> #include <asm/irq_regs.h> #include <asm/pmu.h> #include <asm/stacktrace.h> -/* - * ARMv6 supports a maximum of 3 events, starting from index 0. If we add - * another platform that supports more, we need to increase this to be the - * largest of all platforms. - * - * ARMv7 supports up to 32 events: - * cycle counter CCNT + 31 events counters CNT0..30. - * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. - */ -#define ARMPMU_MAX_HWEVENTS 32 - -static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); -static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); -static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); - -#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) - -/* Set at runtime when we know what CPU type we are. */ -static struct arm_pmu *cpu_pmu; - -const char *perf_pmu_name(void) -{ - if (!cpu_pmu) - return NULL; - - return cpu_pmu->pmu.name; -} -EXPORT_SYMBOL_GPL(perf_pmu_name); - -int perf_num_counters(void) -{ - int max_events = 0; - - if (cpu_pmu != NULL) - max_events = cpu_pmu->num_events; - - return max_events; -} -EXPORT_SYMBOL_GPL(perf_num_counters); - -#define HW_OP_UNSUPPORTED 0xFFFF - -#define C(_x) \ - PERF_COUNT_HW_CACHE_##_x - -#define CACHE_OP_UNSUPPORTED 0xFFFF - static int armpmu_map_cache_event(const unsigned (*cache_map) [PERF_COUNT_HW_CACHE_MAX] @@ -104,7 +51,7 @@ armpmu_map_cache_event(const unsigned (*cache_map) } static int -armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) +armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) { int mapping = (*event_map)[config]; return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; @@ -116,19 +63,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config) return (int)(config & raw_event_mask); } -static int map_cpu_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask) +int +armpmu_map_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask) { u64 config = event->attr.config; switch (event->attr.type) { case PERF_TYPE_HARDWARE: - return armpmu_map_event(event_map, config); + return armpmu_map_hw_event(event_map, config); case PERF_TYPE_HW_CACHE: return armpmu_map_cache_event(cache_map, config); case PERF_TYPE_RAW: @@ -222,7 +170,6 @@ armpmu_stop(struct perf_event *event, int flags) */ if (!(hwc->state & PERF_HES_STOPPED)) { armpmu->disable(hwc, hwc->idx); - barrier(); /* why? */ armpmu_event_update(event, hwc, hwc->idx); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; } @@ -350,99 +297,41 @@ validate_group(struct perf_event *event) return 0; } -static irqreturn_t armpmu_platform_irq(int irq, void *dev) +static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) { struct arm_pmu *armpmu = (struct arm_pmu *) dev; struct platform_device *plat_device = armpmu->plat_device; struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); - return plat->handle_irq(irq, dev, armpmu->handle_irq); + if (plat && plat->handle_irq) + return plat->handle_irq(irq, dev, armpmu->handle_irq); + else + return armpmu->handle_irq(irq, dev); } static void armpmu_release_hardware(struct arm_pmu *armpmu) { - int i, irq, irqs; - struct platform_device *pmu_device = armpmu->plat_device; - struct arm_pmu_platdata *plat = - dev_get_platdata(&pmu_device->dev); - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - - for (i = 0; i < irqs; ++i) { - if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) - continue; - irq = platform_get_irq(pmu_device, i); - if (irq >= 0) { - if (plat && plat->disable_irq) - plat->disable_irq(irq); - free_irq(irq, armpmu); - } - } - - release_pmu(armpmu->type); + armpmu->free_irq(); + pm_runtime_put_sync(&armpmu->plat_device->dev); } static int armpmu_reserve_hardware(struct arm_pmu *armpmu) { - struct arm_pmu_platdata *plat; - irq_handler_t handle_irq; - int i, err, irq, irqs; + int err; struct platform_device *pmu_device = armpmu->plat_device; if (!pmu_device) return -ENODEV; - err = reserve_pmu(armpmu->type); + pm_runtime_get_sync(&pmu_device->dev); + err = armpmu->request_irq(armpmu_dispatch_irq); if (err) { - pr_warning("unable to reserve pmu\n"); + armpmu_release_hardware(armpmu); return err; } - plat = dev_get_platdata(&pmu_device->dev); - if (plat && plat->handle_irq) - handle_irq = armpmu_platform_irq; - else - handle_irq = armpmu->handle_irq; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - if (irqs < 1) { - pr_err("no irqs for PMUs defined\n"); - return -ENODEV; - } - - for (i = 0; i < irqs; ++i) { - err = 0; - irq = platform_get_irq(pmu_device, i); - if (irq < 0) - continue; - - /* - * If we have a single PMU interrupt that we can't shift, - * assume that we're running on a uniprocessor machine and - * continue. Otherwise, continue without this interrupt. - */ - if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { - pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", - irq, i); - continue; - } - - err = request_irq(irq, handle_irq, - IRQF_DISABLED | IRQF_NOBALANCING, - "arm-pmu", armpmu); - if (err) { - pr_err("unable to request IRQ%d for ARM PMU counters\n", - irq); - armpmu_release_hardware(armpmu); - return err; - } else if (plat && plat->enable_irq) - plat->enable_irq(irq); - - cpumask_set_cpu(i, &armpmu->active_irqs); - } - return 0; } @@ -581,6 +470,32 @@ static void armpmu_disable(struct pmu *pmu) armpmu->stop(); } +#ifdef CONFIG_PM_RUNTIME +static int armpmu_runtime_resume(struct device *dev) +{ + struct arm_pmu_platdata *plat = dev_get_platdata(dev); + + if (plat && plat->runtime_resume) + return plat->runtime_resume(dev); + + return 0; +} + +static int armpmu_runtime_suspend(struct device *dev) +{ + struct arm_pmu_platdata *plat = dev_get_platdata(dev); + + if (plat && plat->runtime_suspend) + return plat->runtime_suspend(dev); + + return 0; +} +#endif + +const struct dev_pm_ops armpmu_dev_pm_ops = { + SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) +}; + static void __init armpmu_init(struct arm_pmu *armpmu) { atomic_set(&armpmu->active_events, 0); @@ -598,174 +513,14 @@ static void __init armpmu_init(struct arm_pmu *armpmu) }; } -int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) +int armpmu_register(struct arm_pmu *armpmu, char *name, int type) { armpmu_init(armpmu); + pr_info("enabled with %s PMU driver, %d counters available\n", + armpmu->name, armpmu->num_events); return perf_pmu_register(&armpmu->pmu, name, type); } -/* Include the PMU-specific implementations. */ -#include "perf_event_xscale.c" -#include "perf_event_v6.c" -#include "perf_event_v7.c" - -/* - * Ensure the PMU has sane values out of reset. - * This requires SMP to be available, so exists as a separate initcall. - */ -static int __init -cpu_pmu_reset(void) -{ - if (cpu_pmu && cpu_pmu->reset) - return on_each_cpu(cpu_pmu->reset, NULL, 1); - return 0; -} -arch_initcall(cpu_pmu_reset); - -/* - * PMU platform driver and devicetree bindings. - */ -static struct of_device_id armpmu_of_device_ids[] = { - {.compatible = "arm,cortex-a9-pmu"}, - {.compatible = "arm,cortex-a8-pmu"}, - {.compatible = "arm,arm1136-pmu"}, - {.compatible = "arm,arm1176-pmu"}, - {}, -}; - -static struct platform_device_id armpmu_plat_device_ids[] = { - {.name = "arm-pmu"}, - {}, -}; - -static int __devinit armpmu_device_probe(struct platform_device *pdev) -{ - if (!cpu_pmu) - return -ENODEV; - - cpu_pmu->plat_device = pdev; - return 0; -} - -static struct platform_driver armpmu_driver = { - .driver = { - .name = "arm-pmu", - .of_match_table = armpmu_of_device_ids, - }, - .probe = armpmu_device_probe, - .id_table = armpmu_plat_device_ids, -}; - -static int __init register_pmu_driver(void) -{ - return platform_driver_register(&armpmu_driver); -} -device_initcall(register_pmu_driver); - -static struct pmu_hw_events *armpmu_get_cpu_events(void) -{ - return &__get_cpu_var(cpu_hw_events); -} - -static void __init cpu_pmu_init(struct arm_pmu *armpmu) -{ - int cpu; - for_each_possible_cpu(cpu) { - struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); - events->events = per_cpu(hw_events, cpu); - events->used_mask = per_cpu(used_mask, cpu); - raw_spin_lock_init(&events->pmu_lock); - } - armpmu->get_hw_events = armpmu_get_cpu_events; - armpmu->type = ARM_PMU_DEVICE_CPU; -} - -/* - * PMU hardware loses all context when a CPU goes offline. - * When a CPU is hotplugged back in, since some hardware registers are - * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading - * junk values out of them. - */ -static int __cpuinit pmu_cpu_notify(struct notifier_block *b, - unsigned long action, void *hcpu) -{ - if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) - return NOTIFY_DONE; - - if (cpu_pmu && cpu_pmu->reset) - cpu_pmu->reset(NULL); - - return NOTIFY_OK; -} - -static struct notifier_block __cpuinitdata pmu_cpu_notifier = { - .notifier_call = pmu_cpu_notify, -}; - -/* - * CPU PMU identification and registration. - */ -static int __init -init_hw_perf_events(void) -{ - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); - - /* ARM Ltd CPUs. */ - if (0x41 == implementor) { - switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ - cpu_pmu = armv6pmu_init(); - break; - case 0xB020: /* ARM11mpcore */ - cpu_pmu = armv6mpcore_pmu_init(); - break; - case 0xC080: /* Cortex-A8 */ - cpu_pmu = armv7_a8_pmu_init(); - break; - case 0xC090: /* Cortex-A9 */ - cpu_pmu = armv7_a9_pmu_init(); - break; - case 0xC050: /* Cortex-A5 */ - cpu_pmu = armv7_a5_pmu_init(); - break; - case 0xC0F0: /* Cortex-A15 */ - cpu_pmu = armv7_a15_pmu_init(); - break; - case 0xC070: /* Cortex-A7 */ - cpu_pmu = armv7_a7_pmu_init(); - break; - } - /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: - cpu_pmu = xscale1pmu_init(); - break; - case 2: - cpu_pmu = xscale2pmu_init(); - break; - } - } - - if (cpu_pmu) { - pr_info("enabled with %s PMU driver, %d counters available\n", - cpu_pmu->name, cpu_pmu->num_events); - cpu_pmu_init(cpu_pmu); - register_cpu_notifier(&pmu_cpu_notifier); - armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); - } else { - pr_info("no hardware support available\n"); - } - - return 0; -} -early_initcall(init_hw_perf_events); - /* * Callchain handling code. */ diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c new file mode 100644 index 000000000000..8d7d8d4de9d6 --- /dev/null +++ b/arch/arm/kernel/perf_event_cpu.c @@ -0,0 +1,295 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + */ +#define pr_fmt(fmt) "CPU PMU: " fmt + +#include <linux/bitmap.h> +#include <linux/export.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include <asm/cputype.h> +#include <asm/irq_regs.h> +#include <asm/pmu.h> + +/* Set at runtime when we know what CPU type we are. */ +static struct arm_pmu *cpu_pmu; + +static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); +static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); +static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); + +/* + * Despite the names, these two functions are CPU-specific and are used + * by the OProfile/perf code. + */ +const char *perf_pmu_name(void) +{ + if (!cpu_pmu) + return NULL; + + return cpu_pmu->pmu.name; +} +EXPORT_SYMBOL_GPL(perf_pmu_name); + +int perf_num_counters(void) +{ + int max_events = 0; + + if (cpu_pmu != NULL) + max_events = cpu_pmu->num_events; + + return max_events; +} +EXPORT_SYMBOL_GPL(perf_num_counters); + +/* Include the PMU-specific implementations. */ +#include "perf_event_xscale.c" +#include "perf_event_v6.c" +#include "perf_event_v7.c" + +static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) +{ + return &__get_cpu_var(cpu_hw_events); +} + +static void cpu_pmu_free_irq(void) +{ + int i, irq, irqs; + struct platform_device *pmu_device = cpu_pmu->plat_device; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + + for (i = 0; i < irqs; ++i) { + if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs)) + continue; + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) + free_irq(irq, cpu_pmu); + } +} + +static int cpu_pmu_request_irq(irq_handler_t handler) +{ + int i, err, irq, irqs; + struct platform_device *pmu_device = cpu_pmu->plat_device; + + if (!pmu_device) + return -ENODEV; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + if (irqs < 1) { + pr_err("no irqs for PMUs defined\n"); + return -ENODEV; + } + + for (i = 0; i < irqs; ++i) { + err = 0; + irq = platform_get_irq(pmu_device, i); + if (irq < 0) + continue; + + /* + * If we have a single PMU interrupt that we can't shift, + * assume that we're running on a uniprocessor machine and + * continue. Otherwise, continue without this interrupt. + */ + if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { + pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", + irq, i); + continue; + } + + err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu", + cpu_pmu); + if (err) { + pr_err("unable to request IRQ%d for ARM PMU counters\n", + irq); + return err; + } + + cpumask_set_cpu(i, &cpu_pmu->active_irqs); + } + + return 0; +} + +static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu) +{ + int cpu; + for_each_possible_cpu(cpu) { + struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); + events->events = per_cpu(hw_events, cpu); + events->used_mask = per_cpu(used_mask, cpu); + raw_spin_lock_init(&events->pmu_lock); + } + + cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; + cpu_pmu->request_irq = cpu_pmu_request_irq; + cpu_pmu->free_irq = cpu_pmu_free_irq; + + /* Ensure the PMU has sane values out of reset. */ + if (cpu_pmu && cpu_pmu->reset) + on_each_cpu(cpu_pmu->reset, NULL, 1); +} + +/* + * PMU hardware loses all context when a CPU goes offline. + * When a CPU is hotplugged back in, since some hardware registers are + * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading + * junk values out of them. + */ +static int __cpuinit cpu_pmu_notify(struct notifier_block *b, + unsigned long action, void *hcpu) +{ + if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) + return NOTIFY_DONE; + + if (cpu_pmu && cpu_pmu->reset) + cpu_pmu->reset(NULL); + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = { + .notifier_call = cpu_pmu_notify, +}; + +/* + * PMU platform driver and devicetree bindings. + */ +static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = { + {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, + {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, + {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, + {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, + {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, + {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, + {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, + {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, + {}, +}; + +static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = { + {.name = "arm-pmu"}, + {}, +}; + +/* + * CPU PMU identification and probing. + */ +static struct arm_pmu *__devinit probe_current_pmu(void) +{ + struct arm_pmu *pmu = NULL; + int cpu = get_cpu(); + unsigned long cpuid = read_cpuid_id(); + unsigned long implementor = (cpuid & 0xFF000000) >> 24; + unsigned long part_number = (cpuid & 0xFFF0); + + pr_info("probing PMU on CPU %d\n", cpu); + + /* ARM Ltd CPUs. */ + if (0x41 == implementor) { + switch (part_number) { + case 0xB360: /* ARM1136 */ + case 0xB560: /* ARM1156 */ + case 0xB760: /* ARM1176 */ + pmu = armv6pmu_init(); + break; + case 0xB020: /* ARM11mpcore */ + pmu = armv6mpcore_pmu_init(); + break; + case 0xC080: /* Cortex-A8 */ + pmu = armv7_a8_pmu_init(); + break; + case 0xC090: /* Cortex-A9 */ + pmu = armv7_a9_pmu_init(); + break; + case 0xC050: /* Cortex-A5 */ + pmu = armv7_a5_pmu_init(); + break; + case 0xC0F0: /* Cortex-A15 */ + pmu = armv7_a15_pmu_init(); + break; + case 0xC070: /* Cortex-A7 */ + pmu = armv7_a7_pmu_init(); + break; + } + /* Intel CPUs [xscale]. */ + } else if (0x69 == implementor) { + part_number = (cpuid >> 13) & 0x7; + switch (part_number) { + case 1: + pmu = xscale1pmu_init(); + break; + case 2: + pmu = xscale2pmu_init(); + break; + } + } + + put_cpu(); + return pmu; +} + +static int __devinit cpu_pmu_device_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct arm_pmu *(*init_fn)(void); + struct device_node *node = pdev->dev.of_node; + + if (cpu_pmu) { + pr_info("attempt to register multiple PMU devices!"); + return -ENOSPC; + } + + if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) { + init_fn = of_id->data; + cpu_pmu = init_fn(); + } else { + cpu_pmu = probe_current_pmu(); + } + + if (!cpu_pmu) + return -ENODEV; + + cpu_pmu->plat_device = pdev; + cpu_pmu_init(cpu_pmu); + register_cpu_notifier(&cpu_pmu_hotplug_notifier); + armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); + + return 0; +} + +static struct platform_driver cpu_pmu_driver = { + .driver = { + .name = "arm-pmu", + .pm = &armpmu_dev_pm_ops, + .of_match_table = cpu_pmu_of_device_ids, + }, + .probe = cpu_pmu_device_probe, + .id_table = cpu_pmu_plat_device_ids, +}; + +static int __init register_pmu_driver(void) +{ + return platform_driver_register(&cpu_pmu_driver); +} +device_initcall(register_pmu_driver); diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index c90fcb2b6967..6ccc07971745 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, static int armv6_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv6_perf_map, + return armpmu_map_event(event, &armv6_perf_map, &armv6_perf_cache_map, 0xFF); } @@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init armv6pmu_init(void) +static struct arm_pmu *__devinit armv6pmu_init(void) { return &armv6pmu; } @@ -679,7 +679,7 @@ static struct arm_pmu *__init armv6pmu_init(void) static int armv6mpcore_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv6mpcore_perf_map, + return armpmu_map_event(event, &armv6mpcore_perf_map, &armv6mpcore_perf_cache_map, 0xFF); } @@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init armv6mpcore_pmu_init(void) +static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) { return &armv6mpcore_pmu; } #else -static struct arm_pmu *__init armv6pmu_init(void) +static struct arm_pmu *__devinit armv6pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv6mpcore_pmu_init(void) +static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index f04070bd2183..bd4b090ebcfd 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info) static int armv7_a8_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a8_perf_map, + return armpmu_map_event(event, &armv7_a8_perf_map, &armv7_a8_perf_cache_map, 0xFF); } static int armv7_a9_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a9_perf_map, + return armpmu_map_event(event, &armv7_a9_perf_map, &armv7_a9_perf_cache_map, 0xFF); } static int armv7_a5_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a5_perf_map, + return armpmu_map_event(event, &armv7_a5_perf_map, &armv7_a5_perf_cache_map, 0xFF); } static int armv7_a15_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a15_perf_map, + return armpmu_map_event(event, &armv7_a15_perf_map, &armv7_a15_perf_cache_map, 0xFF); } static int armv7_a7_map_event(struct perf_event *event) { - return map_cpu_event(event, &armv7_a7_perf_map, + return armpmu_map_event(event, &armv7_a7_perf_map, &armv7_a7_perf_cache_map, 0xFF); } @@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = { .max_period = (1LLU << 32) - 1, }; -static u32 __init armv7_read_num_pmnc_events(void) +static u32 __devinit armv7_read_num_pmnc_events(void) { u32 nb_cnt; @@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void) return nb_cnt + 1; } -static struct arm_pmu *__init armv7_a8_pmu_init(void) +static struct arm_pmu *__devinit armv7_a8_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A8"; armv7pmu.map_event = armv7_a8_map_event; @@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a9_pmu_init(void) +static struct arm_pmu *__devinit armv7_a9_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A9"; armv7pmu.map_event = armv7_a9_map_event; @@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a5_pmu_init(void) +static struct arm_pmu *__devinit armv7_a5_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A5"; armv7pmu.map_event = armv7_a5_map_event; @@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a15_pmu_init(void) +static struct arm_pmu *__devinit armv7_a15_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A15"; armv7pmu.map_event = armv7_a15_map_event; @@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__init armv7_a7_pmu_init(void) +static struct arm_pmu *__devinit armv7_a7_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A7"; armv7pmu.map_event = armv7_a7_map_event; @@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void) return &armv7pmu; } #else -static struct arm_pmu *__init armv7_a8_pmu_init(void) +static struct arm_pmu *__devinit armv7_a8_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a9_pmu_init(void) +static struct arm_pmu *__devinit armv7_a9_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a5_pmu_init(void) +static struct arm_pmu *__devinit armv7_a5_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a15_pmu_init(void) +static struct arm_pmu *__devinit armv7_a15_pmu_init(void) { return NULL; } -static struct arm_pmu *__init armv7_a7_pmu_init(void) +static struct arm_pmu *__devinit armv7_a7_pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index f759fe0bab63..426e19f380a2 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val) static int xscale_map_event(struct perf_event *event) { - return map_cpu_event(event, &xscale_perf_map, + return armpmu_map_event(event, &xscale_perf_map, &xscale_perf_cache_map, 0xFF); } @@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init xscale1pmu_init(void) +static struct arm_pmu *__devinit xscale1pmu_init(void) { return &xscale1pmu; } @@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__init xscale2pmu_init(void) +static struct arm_pmu *__devinit xscale2pmu_init(void) { return &xscale2pmu; } #else -static struct arm_pmu *__init xscale1pmu_init(void) +static struct arm_pmu *__devinit xscale1pmu_init(void) { return NULL; } -static struct arm_pmu *__init xscale2pmu_init(void) +static struct arm_pmu *__devinit xscale2pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c deleted file mode 100644 index 2334bf8a650a..000000000000 --- a/arch/arm/kernel/pmu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * linux/arch/arm/kernel/pmu.c - * - * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles - * Copyright (C) 2010 ARM Ltd, Will Deacon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/err.h> -#include <linux/kernel.h> -#include <linux/module.h> - -#include <asm/pmu.h> - -/* - * PMU locking to ensure mutual exclusion between different subsystems. - */ -static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)]; - -int -reserve_pmu(enum arm_pmu_type type) -{ - return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0; -} -EXPORT_SYMBOL_GPL(reserve_pmu); - -void -release_pmu(enum arm_pmu_type type) -{ - clear_bit_unlock(type, pmu_lock); -} -EXPORT_SYMBOL_GPL(release_pmu); diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index fef42b21cecb..e1f906989bb8 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -11,7 +11,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/clk.h> -#include <linux/cpufreq.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> @@ -96,7 +95,52 @@ static void twd_timer_stop(struct clock_event_device *clk) disable_percpu_irq(clk->irq); } -#ifdef CONFIG_CPU_FREQ +#ifdef CONFIG_COMMON_CLK + +/* + * Updates clockevent frequency when the cpu frequency changes. + * Called on the cpu that is changing frequency with interrupts disabled. + */ +static void twd_update_frequency(void *new_rate) +{ + twd_timer_rate = *((unsigned long *) new_rate); + + clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); +} + +static int twd_rate_change(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct clk_notifier_data *cnd = data; + + /* + * The twd clock events must be reprogrammed to account for the new + * frequency. The timer is local to a cpu, so cross-call to the + * changing cpu. + */ + if (flags == POST_RATE_CHANGE) + smp_call_function(twd_update_frequency, + (void *)&cnd->new_rate, 1); + + return NOTIFY_OK; +} + +static struct notifier_block twd_clk_nb = { + .notifier_call = twd_rate_change, +}; + +static int twd_clk_init(void) +{ + if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) + return clk_notifier_register(twd_clk, &twd_clk_nb); + + return 0; +} +core_initcall(twd_clk_init); + +#elif defined (CONFIG_CPU_FREQ) + +#include <linux/cpufreq.h> /* * Updates clockevent frequency when the cpu frequency changes. diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index f7945218b8c6..b0179b89a04c 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -420,20 +420,23 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) #endif instr = *(u32 *) pc; } else if (thumb_mode(regs)) { - get_user(instr, (u16 __user *)pc); + if (get_user(instr, (u16 __user *)pc)) + goto die_sig; if (is_wide_instruction(instr)) { unsigned int instr2; - get_user(instr2, (u16 __user *)pc+1); + if (get_user(instr2, (u16 __user *)pc+1)) + goto die_sig; instr <<= 16; instr |= instr2; } - } else { - get_user(instr, (u32 __user *)pc); + } else if (get_user(instr, (u32 __user *)pc)) { + goto die_sig; } if (call_undef_hook(regs, instr) == 0) return; +die_sig: #ifdef CONFIG_DEBUG_USER if (user_debug & UDBG_UNDEFINED) { printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index d6dacc69254e..395d5fbb8fa2 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c @@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq) { pr_info("Switching to timer-based delay loop\n"); lpj_fine = freq / HZ; + loops_per_jiffy = lpj_fine; arm_delay_ops.delay = __timer_delay; arm_delay_ops.const_udelay = __timer_const_udelay; arm_delay_ops.udelay = __timer_udelay; diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 11093a7c3e32..9b06bb41fca6 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S @@ -16,8 +16,9 @@ * __get_user_X * * Inputs: r0 contains the address + * r1 contains the address limit, which must be preserved * Outputs: r0 is the error code - * r2, r3 contains the zero-extended value + * r2 contains the zero-extended value * lr corrupted * * No other registers must be altered. (see <asm/uaccess.h> @@ -27,33 +28,39 @@ * Note also that it is intended that __get_user_bad is not global. */ #include <linux/linkage.h> +#include <asm/assembler.h> #include <asm/errno.h> #include <asm/domain.h> ENTRY(__get_user_1) + check_uaccess r0, 1, r1, r2, __get_user_bad 1: TUSER(ldrb) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__get_user_1) ENTRY(__get_user_2) -#ifdef CONFIG_THUMB2_KERNEL -2: TUSER(ldrb) r2, [r0] -3: TUSER(ldrb) r3, [r0, #1] + check_uaccess r0, 2, r1, r2, __get_user_bad +#ifdef CONFIG_CPU_USE_DOMAINS +rb .req ip +2: ldrbt r2, [r0], #1 +3: ldrbt rb, [r0], #0 #else -2: TUSER(ldrb) r2, [r0], #1 -3: TUSER(ldrb) r3, [r0] +rb .req r0 +2: ldrb r2, [r0] +3: ldrb rb, [r0, #1] #endif #ifndef __ARMEB__ - orr r2, r2, r3, lsl #8 + orr r2, r2, rb, lsl #8 #else - orr r2, r3, r2, lsl #8 + orr r2, rb, r2, lsl #8 #endif mov r0, #0 mov pc, lr ENDPROC(__get_user_2) ENTRY(__get_user_4) + check_uaccess r0, 4, r1, r2, __get_user_bad 4: TUSER(ldr) r2, [r0] mov r0, #0 mov pc, lr diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index 7db25990c589..3d73dcb959b0 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S @@ -16,6 +16,7 @@ * __put_user_X * * Inputs: r0 contains the address + * r1 contains the address limit, which must be preserved * r2, r3 contains the value * Outputs: r0 is the error code * lr corrupted @@ -27,16 +28,19 @@ * Note also that it is intended that __put_user_bad is not global. */ #include <linux/linkage.h> +#include <asm/assembler.h> #include <asm/errno.h> #include <asm/domain.h> ENTRY(__put_user_1) + check_uaccess r0, 1, r1, ip, __put_user_bad 1: TUSER(strb) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__put_user_1) ENTRY(__put_user_2) + check_uaccess r0, 2, r1, ip, __put_user_bad mov ip, r2, lsr #8 #ifdef CONFIG_THUMB2_KERNEL #ifndef __ARMEB__ @@ -60,12 +64,14 @@ ENTRY(__put_user_2) ENDPROC(__put_user_2) ENTRY(__put_user_4) + check_uaccess r0, 4, r1, ip, __put_user_bad 4: TUSER(str) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__put_user_4) ENTRY(__put_user_8) + check_uaccess r0, 8, r1, ip, __put_user_bad #ifdef CONFIG_THUMB2_KERNEL 5: TUSER(str) r2, [r0] 6: TUSER(str) r3, [r0, #4] diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 104ca40d8d18..aaa443b48c91 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void) at91_st_read(AT91_ST_SR); /* Make IRQs happen for the system timer */ - setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); + setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq); /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used * directly for the clocksource and all clockevents, after adjusting diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 156e639257c9..af50ff3281c7 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -644,6 +644,8 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, }, }; @@ -662,10 +664,12 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9260_rtt_device.num_resources = 2; + at91sam9260_rtt_device.num_resources = 3; rtt_resources[1].start = AT91SAM9260_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; + rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; + rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 06c0c6e025b9..11e9fa835cde 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -609,6 +609,8 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, } }; @@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9261_rtt_device.num_resources = 2; + at91sam9261_rtt_device.num_resources = 3; rtt_resources[1].start = AT91SAM9261_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; + rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; + rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 1e176aaaaecb..7c0898fe20fa 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -1015,6 +1015,8 @@ static struct resource rtt0_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, } }; @@ -1031,6 +1033,8 @@ static struct resource rtt1_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, } }; @@ -1052,14 +1056,14 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed only for the chosen RTT: * GPBR will serve as the storage for RTC time offset */ - at91sam9263_rtt0_device.num_resources = 2; + at91sam9263_rtt0_device.num_resources = 3; at91sam9263_rtt1_device.num_resources = 1; pdev = &at91sam9263_rtt0_device; r = rtt0_resources; break; case 1: at91sam9263_rtt0_device.num_resources = 1; - at91sam9263_rtt1_device.num_resources = 2; + at91sam9263_rtt1_device.num_resources = 3; pdev = &at91sam9263_rtt1_device; r = rtt1_resources; break; @@ -1072,6 +1076,8 @@ static void __init at91_add_device_rtt_rtc(void) pdev->name = "rtc-at91sam9"; r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; r[1].end = r[1].start + 3; + r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; + r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 06073996a382..1b47319ca00b 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1293,6 +1293,8 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, } }; @@ -1310,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9g45_rtt_device.num_resources = 2; + at91sam9g45_rtt_device.num_resources = 3; rtt_resources[1].start = AT91SAM9G45_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; + rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; + rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index ea4479e7c3f4..1fad22f7e21f 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -688,6 +688,8 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, } }; @@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9rl_rtt_device.num_resources = 2; + at91sam9rl_rtt_device.num_resources = 3; rtt_resources[1].start = AT91SAM9RL_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; + rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; + rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index 46090e642d8e..6bd7300a2bc5 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c @@ -47,7 +47,7 @@ static void at91x40_idle(void) * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ - __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR); + __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR)); cpu_do_idle(); } diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c index 6ca680a1d5d1..ee06d7bcdf76 100644 --- a/arch/arm/mach-at91/at91x40_time.c +++ b/arch/arm/mach-at91/at91x40_time.c @@ -29,10 +29,10 @@ #include <mach/at91_tc.h> #define at91_tc_read(field) \ - __raw_readl(AT91_TC + field) + __raw_readl(AT91_IO_P2V(AT91_TC) + field) #define at91_tc_write(field, value) \ - __raw_writel(value, AT91_TC + field); + __raw_writel(value, AT91_IO_P2V(AT91_TC) + field); /* * 3 counter/timer units present. diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index de2ec6b8fea7..188c82971ebd 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -63,6 +63,12 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) +#define cpu_has_240M_plla() (cpu_is_at91sam9261() \ + || cpu_is_at91sam9263() \ + || cpu_is_at91sam9rl()) + +#define cpu_has_210M_plla() (cpu_is_at91sam9260()) + #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ @@ -706,6 +712,12 @@ static int __init at91_pmc_init(unsigned long main_clock) } else if (cpu_has_800M_plla()) { if (plla.rate_hz > 800000000) pll_overclock = true; + } else if (cpu_has_240M_plla()) { + if (plla.rate_hz > 240000000) + pll_overclock = true; + } else if (cpu_has_210M_plla()) { + if (plla.rate_hz > 210000000) + pll_overclock = true; } else { if (plla.rate_hz > 209000000) pll_overclock = true; diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 09242b67d277..711a7892d331 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -67,13 +67,13 @@ * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) #else /* * Identity mapping for the non MMU case. */ #define AT91_IO_PHYS_BASE AT91_BASE_SYS -#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) #endif #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 6f6118d1576a..97ad68a826f8 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = { 0, }; -static inline const u32* decomp_soc_detect(u32 dbgu_base) +static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) { u32 cidr, socid; @@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void) int i = 0; const u32* usarts; - usarts = decomp_soc_detect(AT91_BASE_DBGU0); + usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); if (!usarts) - usarts = decomp_soc_detect(AT91_BASE_DBGU1); + usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); if (!usarts) { at91_uart = NULL; return; diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 944bffb08991..e6f52de1062f 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) { struct map_desc *desc = &sram_desc[bank]; - desc->virtual = AT91_IO_VIRT_BASE - length; + desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length; if (bank > 0) desc->virtual -= sram_desc[bank - 1].length; @@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) } static struct map_desc at91_io_desc __initdata = { - .virtual = AT91_VA_BASE_SYS, + .virtual = (unsigned long)AT91_VA_BASE_SYS, .pfn = __phys_to_pfn(AT91_BASE_SYS), .length = SZ_16K, .type = MT_DEVICE, diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile new file mode 100644 index 000000000000..4c3892fe02c3 --- /dev/null +++ b/arch/arm/mach-bcm2835/Makefile @@ -0,0 +1 @@ +obj-y += bcm2835.o diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot new file mode 100644 index 000000000000..0831fd1764e7 --- /dev/null +++ b/arch/arm/mach-bcm2835/Makefile.boot @@ -0,0 +1,5 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 + +dtb-y += bcm2835-rpi-b.dtb diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c new file mode 100644 index 000000000000..f6fea4933571 --- /dev/null +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/irqchip/bcm2835.h> +#include <linux/of_platform.h> +#include <linux/bcm2835_timer.h> +#include <linux/clk/bcm2835.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/bcm2835_soc.h> + +static struct map_desc io_map __initdata = { + .virtual = BCM2835_PERIPH_VIRT, + .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS), + .length = BCM2835_PERIPH_SIZE, + .type = MT_DEVICE +}; + +void __init bcm2835_map_io(void) +{ + iotable_init(&io_map, 1); +} + +void __init bcm2835_init(void) +{ + int ret; + + bcm2835_init_clocks(); + + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, + NULL); + if (ret) { + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); + } +} + +static const char * const bcm2835_compat[] = { + "brcm,bcm2835", + NULL +}; + +DT_MACHINE_START(BCM2835, "BCM2835") + .map_io = bcm2835_map_io, + .init_irq = bcm2835_init_irq, + .handle_irq = bcm2835_handle_irq, + .init_machine = bcm2835_init, + .timer = &bcm2835_timer, + .dt_compat = bcm2835_compat +MACHINE_END diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h index 0406513be7d8..d4dfcf7a9cda 100644 --- a/arch/arm/mach-versatile/include/mach/io.h +++ b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h @@ -1,7 +1,8 @@ /* - * arch/arm/mach-versatile/include/mach/io.h + * Copyright (C) 2012 Stephen Warren * - * Copyright (C) 2003 ARM Limited + * Derived from code: + * Copyright (C) 2010 Broadcom * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,16 +13,17 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H -#define PCIO_BASE 0xeb000000ul +#ifndef __MACH_BCM2835_BCM2835_SOC_H__ +#define __MACH_BCM2835_BCM2835_SOC_H__ + +#include <asm/sizes.h> -#define __io(a) ((a) + PCIO_BASE) +#define BCM2835_PERIPH_PHYS 0x20000000 +#define BCM2835_PERIPH_VIRT 0xf0000000 +#define BCM2835_PERIPH_SIZE SZ_16M +#define BCM2835_DEBUG_PHYS 0x20201000 +#define BCM2835_DEBUG_VIRT 0xf0201000 #endif diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/mach-bcm2835/include/mach/debug-macro.S new file mode 100644 index 000000000000..8a161e44ae28 --- /dev/null +++ b/arch/arm/mach-bcm2835/include/mach/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2010 Broadcom + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <mach/bcm2835_soc.h> + + .macro addruart, rp, rv, tmp + ldr \rp, =BCM2835_DEBUG_PHYS + ldr \rv, =BCM2835_DEBUG_VIRT + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-bcm2835/include/mach/timex.h index 6ea02f2176b7..6d021e136ae3 100644 --- a/arch/arm/mach-pnx4008/include/mach/param.h +++ b/arch/arm/mach-bcm2835/include/mach/timex.h @@ -1,7 +1,7 @@ /* - * arch/arm/mach-pnx4008/include/mach/param.h + * BCM2835 system clock frequency * - * Copyright (C) 1999 ARM Limited + * Copyright (C) 2010 Broadcom * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,4 +18,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define HZ 100 +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#define CLOCK_TICK_RATE (1000000) + +#endif diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h new file mode 100644 index 000000000000..cc46dcc72377 --- /dev/null +++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2010 Broadcom + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/io.h> +#include <linux/amba/serial.h> +#include <mach/bcm2835_soc.h> + +#define UART0_BASE BCM2835_DEBUG_PHYS + +#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR) +#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR) +#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR) + +static inline void putc(int c) +{ + while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF) + barrier(); + + __raw_writel(c, BCM2835_UART_DR); +} + +static inline void flush(void) +{ + int fr; + + do { + fr = __raw_readl(BCM2835_UART_FR); + barrier(); + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig deleted file mode 100644 index 9170d16dca50..000000000000 --- a/arch/arm/mach-bcmring/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -choice - prompt "Processor selection in BCMRING family of devices" - depends on ARCH_BCMRING - default ARCH_BCM11107 - -config ARCH_FPGA11107 - bool "FPGA11107" - -config ARCH_BCM11107 - bool "BCM11107" -endchoice - -menu "BCMRING Options" - depends on ARCH_BCMRING - -config BCM_ZRELADDR - hex "Compressed ZREL ADDR" - -endmenu diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile deleted file mode 100644 index f8d9fcedf917..000000000000 --- a/arch/arm/mach-bcmring/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o -obj-y += csp/ diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot deleted file mode 100644 index aef2467757fa..000000000000 --- a/arch/arm/mach-bcmring/Makefile.boot +++ /dev/null @@ -1,6 +0,0 @@ -# Address where decompressor will be written and eventually executed. -# -# default to SDRAM -zreladdr-y += $(CONFIG_BCM_ZRELADDR) -params_phys-y := 0x00000800 - diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c deleted file mode 100644 index 45c97b1ee9b1..000000000000 --- a/arch/arm/mach-bcmring/arch.c +++ /dev/null @@ -1,199 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/spinlock.h> -#include <linux/module.h> - -#include <linux/proc_fs.h> -#include <linux/sysctl.h> - -#include <asm/irq.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/time.h> -#include <asm/pmu.h> - -#include <asm/mach/arch.h> -#include <mach/dma.h> -#include <mach/hardware.h> -#include <mach/csp/mm_io.h> -#include <mach/csp/chipcHw_def.h> -#include <mach/csp/chipcHw_inline.h> - -#include <cfg_global.h> - -#include "core.h" - -HW_DECLARE_SPINLOCK(arch) -HW_DECLARE_SPINLOCK(gpio) -#if defined(CONFIG_DEBUG_SPINLOCK) - EXPORT_SYMBOL(bcmring_gpio_reg_lock); -#endif - -/* sysctl */ -static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */ - -static void bcmring_restart(char mode, const char *cmd) -{ - printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot); - - if (mode == 'h') { - /* Reboot configured in proc entry */ - if (bcmring_arch_warm_reboot) { - printk("warm reset\n"); - /* Issue Warm reset (do not reset ethernet switch, keep alive) */ - chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM); - } else { - /* Force reset of everything */ - printk("force reset\n"); - chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); - } - } else { - /* Force reset of everything */ - printk("force reset\n"); - chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); - } -} - -static struct ctl_table_header *bcmring_sysctl_header; - -static struct ctl_table bcmring_sysctl_warm_reboot[] = { - { - .procname = "warm", - .data = &bcmring_arch_warm_reboot, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec}, - {} -}; - -static struct ctl_table bcmring_sysctl_reboot[] = { - { - .procname = "reboot", - .mode = 0555, - .child = bcmring_sysctl_warm_reboot}, - {} -}; - -static struct resource nand_resource[] = { - [0] = { - .start = MM_ADDR_IO_NAND, - .end = MM_ADDR_IO_NAND + 0x1000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device nand_device = { - .name = "bcm-nand", - .id = -1, - .resource = nand_resource, - .num_resources = ARRAY_SIZE(nand_resource), -}; - -static struct resource pmu_resource = { - .start = IRQ_PMUIRQ, - .end = IRQ_PMUIRQ, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .resource = &pmu_resource, - .num_resources = 1, -}; - - -static struct platform_device *devices[] __initdata = { - &nand_device, - &pmu_device, -}; - -/**************************************************************************** -* -* Called from the customize_machine function in arch/arm/kernel/setup.c -* -* The customize_machine function is tagged as an arch_initcall -* (see include/linux/init.h for the order that the various init sections -* are called in. -* -*****************************************************************************/ -static void __init bcmring_init_machine(void) -{ - - bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot); - - /* Enable spread spectrum */ - chipcHw_enableSpreadSpectrum(); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - bcmring_amba_init(); - - dma_init(); -} - -/**************************************************************************** -* -* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags -* passed in by the boot loader. -* -*****************************************************************************/ - -static void __init bcmring_fixup(struct tag *t, char **cmdline, - struct meminfo *mi) { -#ifdef CONFIG_BLK_DEV_INITRD - printk(KERN_NOTICE "bcmring_fixup\n"); - t->hdr.tag = ATAG_CORE; - t->hdr.size = tag_size(tag_core); - t->u.core.flags = 0; - t->u.core.pagesize = PAGE_SIZE; - t->u.core.rootdev = 31 << 8 | 0; - t = tag_next(t); - - t->hdr.tag = ATAG_MEM; - t->hdr.size = tag_size(tag_mem32); - t->u.mem.start = CFG_GLOBAL_RAM_BASE; - t->u.mem.size = CFG_GLOBAL_RAM_SIZE; - - t = tag_next(t); - - t->hdr.tag = ATAG_NONE; - t->hdr.size = 0; -#endif -} - -/**************************************************************************** -* -* Machine Description -* -*****************************************************************************/ - -MACHINE_START(BCMRING, "BCMRING") - /* Maintainer: Broadcom Corporation */ - .fixup = bcmring_fixup, - .map_io = bcmring_map_io, - .init_early = bcmring_init_early, - .init_irq = bcmring_init_irq, - .timer = &bcmring_timer, - .init_machine = bcmring_init_machine, - .restart = bcmring_restart, -MACHINE_END diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c deleted file mode 100644 index ad237a42d265..000000000000 --- a/arch/arm/mach-bcmring/clock.c +++ /dev/null @@ -1,223 +0,0 @@ -/***************************************************************************** -* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/clkdev.h> -#include <mach/csp/hw_cfg.h> -#include <mach/csp/chipcHw_def.h> -#include <mach/csp/chipcHw_reg.h> -#include <mach/csp/chipcHw_inline.h> - -#include "clock.h" - -#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) -#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1) -#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2) -#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) -#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE) - -#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL) - -static DEFINE_SPINLOCK(clk_lock); - -static void __clk_enable(struct clk *clk) -{ - if (!clk) - return; - - /* enable parent clock first */ - if (clk->parent) - __clk_enable(clk->parent); - - if (clk->use_cnt++ == 0) { - if (clk_is_pll1(clk)) { /* PLL1 */ - chipcHw_pll1Enable(clk->rate_hz, 0); - } else if (clk_is_pll2(clk)) { /* PLL2 */ - chipcHw_pll2Enable(clk->rate_hz); - } else if (clk_is_using_xtal(clk)) { /* source is crystal */ - if (!clk_is_primary(clk)) - chipcHw_bypassClockEnable(clk->csp_id); - } else { /* source is PLL */ - chipcHw_setClockEnable(clk->csp_id); - } - } -} - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (!clk) - return -EINVAL; - - spin_lock_irqsave(&clk_lock, flags); - __clk_enable(clk); - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void __clk_disable(struct clk *clk) -{ - if (!clk) - return; - - BUG_ON(clk->use_cnt == 0); - - if (--clk->use_cnt == 0) { - if (clk_is_pll1(clk)) { /* PLL1 */ - chipcHw_pll1Disable(); - } else if (clk_is_pll2(clk)) { /* PLL2 */ - chipcHw_pll2Disable(); - } else if (clk_is_using_xtal(clk)) { /* source is crystal */ - if (!clk_is_primary(clk)) - chipcHw_bypassClockDisable(clk->csp_id); - } else { /* source is PLL */ - chipcHw_setClockDisable(clk->csp_id); - } - } - - if (clk->parent) - __clk_disable(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (!clk) - return; - - spin_lock_irqsave(&clk_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clk_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->rate_hz; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - unsigned long actual; - unsigned long rate_hz; - - if (!clk) - return -EINVAL; - - if (!clk_is_programmable(clk)) - return -EINVAL; - - if (clk->use_cnt) - return -EBUSY; - - spin_lock_irqsave(&clk_lock, flags); - actual = clk->parent->rate_hz; - rate_hz = min(actual, rate); - spin_unlock_irqrestore(&clk_lock, flags); - - return rate_hz; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - unsigned long actual; - unsigned long rate_hz; - - if (!clk) - return -EINVAL; - - if (!clk_is_programmable(clk)) - return -EINVAL; - - if (clk->use_cnt) - return -EBUSY; - - spin_lock_irqsave(&clk_lock, flags); - actual = clk->parent->rate_hz; - rate_hz = min(actual, rate); - rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz); - clk->rate_hz = rate_hz; - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -struct clk *clk_get_parent(struct clk *clk) -{ - if (!clk) - return NULL; - - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - struct clk *old_parent; - - if (!clk || !parent) - return -EINVAL; - - if (!clk_is_primary(parent) || !clk_is_bypassable(clk)) - return -EINVAL; - - /* if more than one user, parent is not allowed */ - if (clk->use_cnt > 1) - return -EBUSY; - - if (clk->parent == parent) - return 0; - - spin_lock_irqsave(&clk_lock, flags); - old_parent = clk->parent; - clk->parent = parent; - if (clk_is_using_xtal(parent)) - clk->mode |= CLK_MODE_XTAL; - else - clk->mode &= (~CLK_MODE_XTAL); - - /* if clock is active */ - if (clk->use_cnt != 0) { - clk->use_cnt--; - /* enable clock with the new parent */ - __clk_enable(clk); - /* disable the old parent */ - __clk_disable(old_parent); - } - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_set_parent); diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h deleted file mode 100644 index 5e0b98138973..000000000000 --- a/arch/arm/mach-bcmring/clock.h +++ /dev/null @@ -1,33 +0,0 @@ -/***************************************************************************** -* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ -#include <mach/csp/chipcHw_def.h> - -#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */ -#define CLK_TYPE_PLL1 2 /* PPL1 */ -#define CLK_TYPE_PLL2 4 /* PPL2 */ -#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */ -#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */ - -#define CLK_MODE_XTAL 1 /* clock source is from crystal */ - -struct clk { - const char *name; /* clock name */ - unsigned int type; /* clock type */ - unsigned int mode; /* current mode */ - volatile int use_bypass; /* indicate if it's in bypass mode */ - chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */ - unsigned long rate_hz; /* clock rate in Hz */ - unsigned int use_cnt; /* usage count */ - struct clk *parent; /* parent clock */ -}; diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c deleted file mode 100644 index adbfb1994582..000000000000 --- a/arch/arm/mach-bcmring/core.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * derived from linux/arch/arm/mach-versatile/core.c - * linux/arch/arm/mach-bcmring/core.c - * - * Copyright (C) 1999 - 2003 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Portions copyright Broadcom 2008 */ - -#include <linux/init.h> -#include <linux/device.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/amba/bus.h> -#include <linux/clkdev.h> - -#include <mach/csp/mm_addr.h> -#include <mach/hardware.h> -#include <linux/io.h> -#include <asm/irq.h> -#include <asm/hardware/arm_timer.h> -#include <asm/hardware/timer-sp.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <cfg_global.h> - -#include "clock.h" - -#include <csp/secHw.h> -#include <mach/csp/secHw_def.h> -#include <mach/csp/chipcHw_inline.h> -#include <mach/csp/tmrHw_reg.h> - -static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL); -static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL); - -static struct clk pll1_clk = { - .name = "PLL1", - .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1, - .rate_hz = 2000000000, - .use_cnt = 7, -}; - -static struct clk uart_clk = { - .name = "UART", - .type = CLK_TYPE_PROGRAMMABLE, - .csp_id = chipcHw_CLOCK_UART, - .rate_hz = HW_CFG_UART_CLK_HZ, - .parent = &pll1_clk, -}; - -static struct clk dummy_apb_pclk = { - .name = "BUSCLK", - .type = CLK_TYPE_PRIMARY, - .mode = CLK_MODE_XTAL, -}; - -/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ -#if defined(CONFIG_ARCH_FPGA11107) -/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ -/* slow down Linux's sense of time */ -#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) -#else -#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) -#endif - -static struct clk sp804_timer012_clk = { - .name = "sp804-timer-0,1,2", - .type = CLK_TYPE_PRIMARY, - .mode = CLK_MODE_XTAL, - .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000, -}; - -static struct clk sp804_timer3_clk = { - .name = "sp804-timer-3", - .type = CLK_TYPE_PRIMARY, - .mode = CLK_MODE_XTAL, - .rate_hz = TIMER3_FREQUENCY_KHZ * 1000, -}; - -static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, { /* UART0 */ - .dev_id = "uarta", - .clk = &uart_clk, - }, { /* UART1 */ - .dev_id = "uartb", - .clk = &uart_clk, - }, { /* SP804 timer 0 */ - .dev_id = "sp804", - .con_id = "timer0", - .clk = &sp804_timer012_clk, - }, { /* SP804 timer 1 */ - .dev_id = "sp804", - .con_id = "timer1", - .clk = &sp804_timer012_clk, - }, { /* SP804 timer 3 */ - .dev_id = "sp804", - .con_id = "timer3", - .clk = &sp804_timer3_clk, - } -}; - -static struct amba_device *amba_devs[] __initdata = { - &uartA_device, - &uartB_device, -}; - -void __init bcmring_amba_init(void) -{ - int i; - u32 bus_clock; - -/* Linux is run initially in non-secure mode. Secure peripherals */ -/* generate FIQ, and must be handled in secure mode. Until we have */ -/* a linux security monitor implementation, keep everything in */ -/* non-secure mode. */ - chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU); - secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL | - secHw_BLK_MASK_KEY_SCAN | - secHw_BLK_MASK_TOUCH_SCREEN | - secHw_BLK_MASK_UART0 | - secHw_BLK_MASK_UART1 | - secHw_BLK_MASK_WATCHDOG | - secHw_BLK_MASK_SPUM | - secHw_BLK_MASK_DDR2 | - secHw_BLK_MASK_SPU | - secHw_BLK_MASK_PKA | - secHw_BLK_MASK_RNG | - secHw_BLK_MASK_RTC | - secHw_BLK_MASK_OTP | - secHw_BLK_MASK_BOOT | - secHw_BLK_MASK_MPU | - secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR); - - /* Only the devices attached to the AMBA bus are enabled just before the bus is */ - /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */ - /* driver to access these blocks. The bus is probed, and the drivers are loaded. */ - /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */ - bus_clock = chipcHw_REG_BUS_CLOCK_GE - | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1; - - chipcHw_busInterfaceClockEnable(bus_clock); - - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } -} - -/* - * Where is the timer (VA)? - */ -#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR) -#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20)) -#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40)) -#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60)) - -static int __init bcmring_clocksource_init(void) -{ - /* setup timer1 as free-running clocksource */ - sp804_clocksource_init(TIMER1_VA_BASE, "timer1"); - - /* setup timer3 as free-running clocksource */ - sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); - - return 0; -} - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -void __init bcmring_init_timer(void) -{ - printk(KERN_INFO "bcmring_init_timer\n"); - /* - * Initialise to a known state (all timers off) - */ - writel(0, TIMER0_VA_BASE + TIMER_CTRL); - writel(0, TIMER1_VA_BASE + TIMER_CTRL); - writel(0, TIMER2_VA_BASE + TIMER_CTRL); - writel(0, TIMER3_VA_BASE + TIMER_CTRL); - - /* - * Make irqs happen for the system timer - */ - bcmring_clocksource_init(); - - sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0"); -} - -struct sys_timer bcmring_timer = { - .init = bcmring_init_timer, -}; - -void __init bcmring_init_early(void) -{ - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); -} diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h deleted file mode 100644 index e0e02c48f9b1..000000000000 --- a/arch/arm/mach-bcmring/core.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * linux/arch/arm/mach-versatile/core.h - * - * Copyright (C) 2004 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Portions copyright Broadcom 2008 */ -#ifndef __ASM_ARCH_BCMRING_H -#define __ASM_ARCH_BCMRING_H - -void __init bcmring_amba_init(void); -void __init bcmring_map_io(void); -void __init bcmring_init_irq(void); -void __init bcmring_init_early(void); - -extern struct sys_timer bcmring_timer; -#endif diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile deleted file mode 100644 index 648c0377530e..000000000000 --- a/arch/arm/mach-bcmring/csp/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += dmac/ -obj-y += tmr/ -obj-y += chipc/ diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile deleted file mode 100644 index 673952768ee5..000000000000 --- a/arch/arm/mach-bcmring/csp/chipc/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c deleted file mode 100644 index 96273ff34956..000000000000 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ /dev/null @@ -1,776 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file chipcHw.c -* -* @brief Low level Various CHIP clock controlling routines -* -* @note -* -* These routines provide basic clock controlling functionality only. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/errno.h> -#include <csp/stdint.h> -#include <csp/module.h> - -#include <mach/csp/chipcHw_def.h> -#include <mach/csp/chipcHw_inline.h> - -#include <csp/reg.h> -#include <csp/delay.h> - -/* ---- Private Constants and Types --------------------------------------- */ - -/* VPM alignment algorithm uses this */ -#define MAX_PHASE_ADJUST_COUNT 0xFFFF /* Max number of times allowed to adjust the phase */ -#define MAX_PHASE_ALIGN_ATTEMPTS 10 /* Max number of attempt to align the phase */ - -/* Local definition of clock type */ -#define PLL_CLOCK 1 /* PLL Clock */ -#define NON_PLL_CLOCK 2 /* Divider clock */ - -static int chipcHw_divide(int num, int denom) - __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Set clock fequency for miscellaneous configurable clocks -* -* This function sets clock frequency -* -* @return Configured clock frequency in hertz -* -*/ -/****************************************************************************/ -chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; - uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ - uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ - uint32_t dependentClockType = 0; - uint32_t vcoHz = 0; - - /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - uint64_t adjustFreq = 0; - - vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - - /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ - adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz * - (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC)); - vcoFreqPll1Hz += (uint32_t) adjustFreq; - } else { - vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - } - vcoFreqPll2Hz = - chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - - switch (clock) { - case chipcHw_CLOCK_DDR: - pPLLReg = &pChipcHw->DDRClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ARM: - pPLLReg = &pChipcHw->ARMClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ESW: - pPLLReg = &pChipcHw->ESWClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_VPM: - pPLLReg = &pChipcHw->VPMClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ESW125: - pPLLReg = &pChipcHw->ESW125Clock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_UART: - pPLLReg = &pChipcHw->UARTClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SDIO0: - pPLLReg = &pChipcHw->SDIO0Clock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SDIO1: - pPLLReg = &pChipcHw->SDIO1Clock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SPI: - pPLLReg = &pChipcHw->SPIClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ETM: - pPLLReg = &pChipcHw->ETMClock; - vcoHz = vcoFreqPll1Hz; - break; - case chipcHw_CLOCK_USB: - pPLLReg = &pChipcHw->USBClock; - vcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_LCD: - pPLLReg = &pChipcHw->LCDClock; - vcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_APM: - pPLLReg = &pChipcHw->APMClock; - vcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_BUS: - pClockCtrl = &pChipcHw->ACLKClock; - pDependentClock = &pChipcHw->ARMClock; - vcoHz = vcoFreqPll1Hz; - dependentClockType = PLL_CLOCK; - break; - case chipcHw_CLOCK_OTP: - pClockCtrl = &pChipcHw->OTPClock; - break; - case chipcHw_CLOCK_I2C: - pClockCtrl = &pChipcHw->I2CClock; - break; - case chipcHw_CLOCK_I2S0: - pClockCtrl = &pChipcHw->I2S0Clock; - break; - case chipcHw_CLOCK_RTBUS: - pClockCtrl = &pChipcHw->RTBUSClock; - pDependentClock = &pChipcHw->ACLKClock; - dependentClockType = NON_PLL_CLOCK; - break; - case chipcHw_CLOCK_APM100: - pClockCtrl = &pChipcHw->APM100Clock; - pDependentClock = &pChipcHw->APMClock; - vcoHz = vcoFreqPll2Hz; - dependentClockType = PLL_CLOCK; - break; - case chipcHw_CLOCK_TSC: - pClockCtrl = &pChipcHw->TSCClock; - break; - case chipcHw_CLOCK_LED: - pClockCtrl = &pChipcHw->LEDClock; - break; - case chipcHw_CLOCK_I2S1: - pClockCtrl = &pChipcHw->I2S1Clock; - break; - } - - if (pPLLReg) { - /* Obtain PLL clock frequency */ - if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { - /* Return crystal clock frequency when bypassed */ - return chipcHw_XTAL_FREQ_Hz; - } else if (clock == chipcHw_CLOCK_DDR) { - /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); - } else { - /* From chip revision number B0, LCD clock is internally divided by 2 */ - if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { - vcoHz >>= 1; - } - /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); - } - } else if (pClockCtrl) { - /* Obtain divider clock frequency */ - uint32_t div; - uint32_t freq = 0; - - if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { - /* Return crystal clock frequency when bypassed */ - return chipcHw_XTAL_FREQ_Hz; - } else if (pDependentClock) { - /* Identify the dependent clock frequency */ - switch (dependentClockType) { - case PLL_CLOCK: - if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { - /* Use crystal clock frequency when dependent PLL clock is bypassed */ - freq = chipcHw_XTAL_FREQ_Hz; - } else { - /* Obtain PLL clock frequency using VCO dividers */ - div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; - freq = div ? chipcHw_divide(vcoHz, div) : 0; - } - break; - case NON_PLL_CLOCK: - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { - freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); - } else { - if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { - /* Use crystal clock frequency when dependent divider clock is bypassed */ - freq = chipcHw_XTAL_FREQ_Hz; - } else { - /* Obtain divider clock frequency using XTAL dividers */ - div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; - freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); - } - } - break; - } - } else { - /* Dependent on crystal clock */ - freq = chipcHw_XTAL_FREQ_Hz; - } - - div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; - return chipcHw_divide(freq, (div ? div : 256)); - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Set clock fequency for miscellaneous configurable clocks -* -* This function sets clock frequency -* -* @return Configured clock frequency in Hz -* -*/ -/****************************************************************************/ -chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ - uint32_t freq /* [ IN ] Clock frequency in Hz */ - ) { - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - volatile uint32_t *pDependentClock = (uint32_t *) 0x0; - uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ - uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ - uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ - uint32_t dependentClockType = 0; - uint32_t vcoHz = 0; - uint32_t desVcoHz = 0; - - /* Get VCO frequencies */ - if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - uint64_t adjustFreq = 0; - - vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - - /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ - adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz * - (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC)); - vcoFreqPll1Hz += (uint32_t) adjustFreq; - - /* Desired VCO frequency */ - desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); - } else { - vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * - chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - } - vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); - - switch (clock) { - case chipcHw_CLOCK_DDR: - /* Configure the DDR_ctrl:BUS ratio settings */ - { - REG_LOCAL_IRQ_SAVE; - /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); - REG_LOCAL_IRQ_RESTORE; - } - pPLLReg = &pChipcHw->DDRClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ARM: - pPLLReg = &pChipcHw->ARMClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ESW: - pPLLReg = &pChipcHw->ESWClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_VPM: - /* Configure the VPM:BUS ratio settings */ - { - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) - << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); - REG_LOCAL_IRQ_RESTORE; - } - pPLLReg = &pChipcHw->VPMClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ESW125: - pPLLReg = &pChipcHw->ESW125Clock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_UART: - pPLLReg = &pChipcHw->UARTClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SDIO0: - pPLLReg = &pChipcHw->SDIO0Clock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SDIO1: - pPLLReg = &pChipcHw->SDIO1Clock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_SPI: - pPLLReg = &pChipcHw->SPIClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_ETM: - pPLLReg = &pChipcHw->ETMClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - break; - case chipcHw_CLOCK_USB: - pPLLReg = &pChipcHw->USBClock; - vcoHz = vcoFreqPll2Hz; - desVcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_LCD: - pPLLReg = &pChipcHw->LCDClock; - vcoHz = vcoFreqPll2Hz; - desVcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_APM: - pPLLReg = &pChipcHw->APMClock; - vcoHz = vcoFreqPll2Hz; - desVcoHz = vcoFreqPll2Hz; - break; - case chipcHw_CLOCK_BUS: - pClockCtrl = &pChipcHw->ACLKClock; - pDependentClock = &pChipcHw->ARMClock; - vcoHz = vcoFreqPll1Hz; - desVcoHz = desVcoFreqPll1Hz; - dependentClockType = PLL_CLOCK; - break; - case chipcHw_CLOCK_OTP: - pClockCtrl = &pChipcHw->OTPClock; - break; - case chipcHw_CLOCK_I2C: - pClockCtrl = &pChipcHw->I2CClock; - break; - case chipcHw_CLOCK_I2S0: - pClockCtrl = &pChipcHw->I2S0Clock; - break; - case chipcHw_CLOCK_RTBUS: - pClockCtrl = &pChipcHw->RTBUSClock; - pDependentClock = &pChipcHw->ACLKClock; - dependentClockType = NON_PLL_CLOCK; - break; - case chipcHw_CLOCK_APM100: - pClockCtrl = &pChipcHw->APM100Clock; - pDependentClock = &pChipcHw->APMClock; - vcoHz = vcoFreqPll2Hz; - desVcoHz = vcoFreqPll2Hz; - dependentClockType = PLL_CLOCK; - break; - case chipcHw_CLOCK_TSC: - pClockCtrl = &pChipcHw->TSCClock; - break; - case chipcHw_CLOCK_LED: - pClockCtrl = &pChipcHw->LEDClock; - break; - case chipcHw_CLOCK_I2S1: - pClockCtrl = &pChipcHw->I2S1Clock; - break; - } - - if (pPLLReg) { - /* Select XTAL as bypass source */ - reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO); - reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); - /* For DDR settings use only the PLL divider clock */ - if (pPLLReg == &pChipcHw->DDRClock) { - /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); - /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); - } else { - /* From chip revision number B0, LCD clock is internally divided by 2 */ - if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { - desVcoHz >>= 1; - vcoHz >>= 1; - } - /* Set MDIV to change the frequency */ - reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); - reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); - /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); - } - /* Wait for for atleast 200ns as per the protocol to change frequency */ - udelay(1); - /* Do not bypass */ - reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); - /* Return the configured frequency */ - return freq; - } else if (pClockCtrl) { - uint32_t divider = 0; - - /* Divider clock should not be bypassed */ - reg32_modify_and(pClockCtrl, - ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); - - /* Identify the clock source */ - if (pDependentClock) { - switch (dependentClockType) { - case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); - break; - case NON_PLL_CLOCK: - { - uint32_t sourceClock = 0; - - if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { - sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); - } else { - uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; - sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); - } - divider = chipcHw_divide(sourceClock, freq); - } - break; - } - } else { - divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq); - } - - if (divider) { - REG_LOCAL_IRQ_SAVE; - /* Set the divider to obtain the required frequency */ - *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); - REG_LOCAL_IRQ_RESTORE; - return freq; - } - } - - return 0; -} - -EXPORT_SYMBOL(chipcHw_setClockFrequency); - -/****************************************************************************/ -/** -* @brief Set VPM clock in sync with BUS clock for Chip Rev #A0 -* -* This function does the phase adjustment between VPM and BUS clock -* -* @return >= 0 : On success (# of adjustment required) -* -1 : On failure -* -*/ -/****************************************************************************/ -static int vpmPhaseAlignA0(void) -{ - uint32_t phaseControl; - uint32_t phaseValue; - uint32_t prevPhaseComp; - int iter = 0; - int adjustCount = 0; - int count = 0; - - for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; - phaseValue = 0; - prevPhaseComp = 0; - - /* Step 1: Look for falling PH_COMP transition */ - - /* Read the contents of VPM Clock resgister */ - phaseValue = pChipcHw->VPMClock; - do { - /* Store previous value of phase comparator */ - prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; - /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; - - if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { - phaseControl = (0x3F & (phaseControl - 1)); - } else { - /* Increment to the Phase count value for next write, if Phase is not stable. */ - phaseControl = (0x3F & (phaseControl + 1)); - } - /* Count number of adjustment made */ - adjustCount++; - } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */ - ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && /* Look for a falling edge */ - (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */ - ); - - if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { - /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ - return -1; - } - - /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */ - - for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { - phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; - /* Count number of adjustment made */ - adjustCount++; - } - - if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { - /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ - return -1; - } - - if (count != 5) { - /* Detected false transition */ - continue; - } - - /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */ - - for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { - phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; - /* Count number of adjustment made */ - adjustCount++; - } - - if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { - /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ - return -1; - } - - if (count != 3) { - /* Detected noisy transition */ - continue; - } - - /* Step 4: Keep moving backward before the original transition took place. */ - - for (count = 0; (count < 5); count++) { - phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - phaseValue = pChipcHw->VPMClock; - /* Count number of adjustment made */ - adjustCount++; - } - - if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { - /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ - return -1; - } - - if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) { - /* Detected false transition */ - continue; - } - - /* Step 5: Re discover the valid transition */ - - do { - /* Store previous value of phase comparator */ - prevPhaseComp = phaseValue; - /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= - chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - /* Read the contents of VPM Clock resgister. */ - phaseValue = pChipcHw->VPMClock; - - if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { - phaseControl = (0x3F & (phaseControl - 1)); - } else { - /* Increment to the Phase count value for next write, if Phase is not stable. */ - phaseControl = (0x3F & (phaseControl + 1)); - } - - /* Count number of adjustment made */ - adjustCount++; - } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT)); - - if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { - /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ - return -1; - } else { - /* Valid phase must have detected */ - break; - } - } - - /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); - { - REG_LOCAL_IRQ_SAVE; - - pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); - /* Load new phase value */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - - REG_LOCAL_IRQ_RESTORE; - } - /* Return the status */ - return (int)adjustCount; -} - -/****************************************************************************/ -/** -* @brief Set VPM clock in sync with BUS clock -* -* This function does the phase adjustment between VPM and BUS clock -* -* @return >= 0 : On success (# of adjustment required) -* -1 : On failure -* -*/ -/****************************************************************************/ -int chipcHw_vpmPhaseAlign(void) -{ - - if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) { - return vpmPhaseAlignA0(); - } else { - uint32_t phaseControl = chipcHw_getVpmPhaseControl(); - uint32_t phaseValue = 0; - int adjustCount = 0; - - /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; - /* Disable HW VPM phase alignment */ - chipcHw_vpmHwPhaseAlignDisable(); - /* Enable SW VPM phase alignment */ - chipcHw_vpmSwPhaseAlignEnable(); - /* Adjust VPM phase */ - while (adjustCount < MAX_PHASE_ADJUST_COUNT) { - phaseValue = chipcHw_getVpmHwPhaseAlignStatus(); - - /* Adjust phase control value */ - if (phaseValue > 0xF) { - /* Increment phase control value */ - phaseControl++; - } else if (phaseValue < 0xF) { - /* Decrement phase control value */ - phaseControl--; - } else { - /* Enable VPM access */ - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; - /* Return adjust count */ - return adjustCount; - } - /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); - /* Wait atleast 20 ns */ - udelay(1); - /* Toggle the LOAD_CH after phase control is written. */ - pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; - /* Count adjustment */ - adjustCount++; - } - } - - /* Disable VPM access */ - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; - return -1; -} - -/****************************************************************************/ -/** -* @brief Local Divide function -* -* This function does the divide -* -* @return divide value -* -*/ -/****************************************************************************/ -static int chipcHw_divide(int num, int denom) -{ - int r; - int t = 1; - - /* Shift denom and t up to the largest value to optimize algorithm */ - /* t contains the units of each divide */ - while ((denom & 0x40000000) == 0) { /* fails if denom=0 */ - denom = denom << 1; - t = t << 1; - } - - /* Initialize the result */ - r = 0; - - do { - /* Determine if there exists a positive remainder */ - if ((num - denom) >= 0) { - /* Accumlate t to the result and calculate a new remainder */ - num = num - denom; - r = r + t; - } - /* Continue to shift denom and shift t down to 0 */ - denom = denom >> 1; - t = t >> 1; - } while (t != 0); - - return r; -} diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c deleted file mode 100644 index 367df75d4bb3..000000000000 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file chipcHw_init.c -* -* @brief Low level CHIPC PLL configuration functions -* -* @note -* -* These routines provide basic PLL controlling functionality only. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/errno.h> -#include <csp/stdint.h> -#include <csp/module.h> - -#include <mach/csp/chipcHw_def.h> -#include <mach/csp/chipcHw_inline.h> - -#include <csp/reg.h> -#include <csp/delay.h> -/* ---- Private Constants and Types --------------------------------------- */ - -/* - Calculation for NDIV_i to obtain VCO frequency - ----------------------------------------------- - - Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f) - for Freq_vco = VCO_FREQ_MHz - Freq_ref = chipcHw_XTAL_FREQ_Hz - PLL_P1 = PLL_P2 = 1 - and - PLL_NDIV_f = 0 - - We get: - PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz - - Calculation for PLL MDIV to obtain frequency Freq_x for channel x - ----------------------------------------------------------------- - Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x - - PLL_MDIV_x = VCO_FREQ_MHz / Freq_x -*/ - -/* ---- Private Variables ------------------------------------------------- */ -/****************************************************************************/ -/** -* @brief Initializes the PLL2 -* -* This function initializes the PLL2 -* -*/ -/****************************************************************************/ -void chipcHw_pll2Enable(uint32_t vcoFreqHz) -{ - uint32_t pllPreDivider2 = 0; - - { - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; - - pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | - chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | - (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) << - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P1 << - chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P2 << - chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); - - /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; - - /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider2 = pllPreDivider2; - /* Set NDIV Frac */ - pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; - - /* This has to be removed once the default values are fixed for PLL2. */ - pChipcHw->PLLControl12 = 0x38000700; - pChipcHw->PLLControl22 = 0x00000015; - - /* Reset PLL2 */ - if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; - } else { - pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; - } - REG_LOCAL_IRQ_RESTORE; - } - - /* Insert certain amount of delay before deasserting ARESET. */ - udelay(1); - - { - REG_LOCAL_IRQ_SAVE; - /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig2 &= - ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); - - REG_LOCAL_IRQ_RESTORE; - - } - - /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) - ; - - { - REG_LOCAL_IRQ_SAVE; - /* Remove digital reset */ - pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; - - REG_LOCAL_IRQ_RESTORE; - } -} - -EXPORT_SYMBOL(chipcHw_pll2Enable); - -/****************************************************************************/ -/** -* @brief Initializes the PLL1 -* -* This function initializes the PLL1 -* -*/ -/****************************************************************************/ -void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) -{ - uint32_t pllPreDivider = 0; - - { - REG_LOCAL_IRQ_SAVE; - - pChipcHw->PLLConfig = - chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET; - /* Setting VCO frequency */ - if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - pllPreDivider = - chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 | - ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) - - 1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P1 << - chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P2 << - chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); - } else { - pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | - chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | - (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) << - chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P1 << - chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | - (chipcHw_REG_PLL_PREDIVIDER_P2 << - chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); - } - - /* Enable CHIPC registers to control the PLL */ - pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; - - /* Set pre divider to get desired VCO frequency */ - pChipcHw->PLLPreDivider = pllPreDivider; - /* Set NDIV Frac */ - if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; - } else { - pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | - chipcHw_REG_PLL_DIVIDER_NDIV_f; - } - - /* Reset PLL1 */ - if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; - } else { - pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN; - } - - REG_LOCAL_IRQ_RESTORE; - - /* Insert certain amount of delay before deasserting ARESET. */ - udelay(1); - - { - REG_LOCAL_IRQ_SAVE; - /* Remove analog reset and Power on the PLL */ - pChipcHw->PLLConfig &= - ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN); - REG_LOCAL_IRQ_RESTORE; - } - - /* Wait until PLL is locked */ - while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) - || !(pChipcHw-> - PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) - ; - - /* Remove digital reset */ - { - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; - REG_LOCAL_IRQ_RESTORE; - } - } -} - -EXPORT_SYMBOL(chipcHw_pll1Enable); - -/****************************************************************************/ -/** -* @brief Initializes the chipc module -* -* This function initializes the PLLs and core system clocks -* -*/ -/****************************************************************************/ - -void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */ - ) { -#if !(defined(__KERNEL__) && !defined(STANDALONE)) - delay_init(); -#endif - - /* Do not program PLL, when warm reset */ - if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) { - chipcHw_pll1Enable(initParam->pllVcoFreqHz, - initParam->ssSupport); - chipcHw_pll2Enable(initParam->pll2VcoFreqHz); - } else { - /* Clear sticky bits */ - chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET); - } - /* Clear sticky bits */ - chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); - - /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - pChipcHw->ACLKClock = - (pChipcHw-> - ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> - armBusRatio & - chipcHw_REG_ACLKClock_CLK_DIV_MASK); - - /* Set various core component frequencies. The order in which this is done is important for some. */ - /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ - /* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */ - /* then VPM and RTBUS. */ - - chipcHw_setClockFrequency(chipcHw_CLOCK_ARM, - initParam->busClockFreqHz * - initParam->armBusRatio); - chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz); - chipcHw_setClockFrequency(chipcHw_CLOCK_VPM, - initParam->busClockFreqHz * - initParam->vpmBusRatio); - chipcHw_setClockFrequency(chipcHw_CLOCK_DDR, - initParam->busClockFreqHz * - initParam->ddrBusRatio); - chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS, - initParam->busClockFreqHz / 2); -} diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c deleted file mode 100644 index 2671d8896bbb..000000000000 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ /dev/null @@ -1,124 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <mach/csp/chipcHw_def.h> -#include <mach/csp/chipcHw_inline.h> -#include <csp/intcHw.h> -#include <csp/cache.h> - -/* ---- Private Constants and Types --------------------------------------- */ -/* ---- Private Variables ------------------------------------------------- */ -void chipcHw_reset_run_from_aram(void); - -typedef void (*RUNFUNC) (void); - -/****************************************************************************/ -/** -* @brief warmReset -* -* @note warmReset configures the clocks which are not reset back to the state -* required to execute on reset. To do so we need to copy the code into internal -* memory to change the ARM clock while we are not executing from DDR. -*/ -/****************************************************************************/ -void chipcHw_reset(uint32_t mask) -{ - int i = 0; - RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM; - - /* Disable all interrupts */ - intcHw_irq_disable(INTCHW_INTC0, 0xffffffff); - intcHw_irq_disable(INTCHW_INTC1, 0xffffffff); - intcHw_irq_disable(INTCHW_SINTC, 0xffffffff); - - { - REG_LOCAL_IRQ_SAVE; - if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) { - chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); - } - /* Bypass the PLL clocks before reboot */ - pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; - pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; - - /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ - do { - ((uint32_t *) MM_IO_BASE_ARAM)[i] = - ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; - i++; - } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - - CSP_CACHE_FLUSH_ALL; - - /* run the function from ARAM */ - runFunc(); - - /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */ - REG_LOCAL_IRQ_RESTORE; - } -} - -/* This function must run from internal memory */ -void chipcHw_reset_run_from_aram(void) -{ -/* Make sure, pipeline is filled with instructions coming from ARAM */ -__asm (" nop \n\t" - " nop \n\t" -#if defined(__KERNEL__) && !defined(STANDALONE) - " MRC p15,#0x0,r0,c1,c0,#0 \n\t" - " BIC r0,r0,#0xd \n\t" - " MCR p15,#0x0,r0,c1,c0,#0 \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" -#endif - " nop \n\t" - " nop \n\t" -/* Bypass the ARM clock and switch to XTAL clock */ - " MOV r2,#0x80000000 \n\t" - " LDR r3,[r2,#8] \n\t" - " ORR r3,r3,#0x20000 \n\t" - " STR r3,[r2,#8] \n\t" - - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" - " nop \n\t" -/* Issue reset */ - " MOV r3,#0x2 \n\t" - " STR r3,[r2,#0x80] \n\t" -/* End here */ - " MOV pc,pc \n\t"); -/* 0xe1a0f00f == asm ("mov r15, r15"); */ -} diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c deleted file mode 100644 index 54ad964fe94c..000000000000 --- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* Copyright 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ -/****************************************************************************/ -/** -* @file chipcHw_str.c -* -* @brief Contains strings which are useful to linux and csp -* -* @note -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <mach/csp/chipcHw_inline.h> - -/* ---- Private Constants and Types --------------------------------------- */ - -static const char *gMuxStr[] = { - "GPIO", /* 0 */ - "KeyPad", /* 1 */ - "I2C-Host", /* 2 */ - "SPI", /* 3 */ - "Uart", /* 4 */ - "LED-Mtx-P", /* 5 */ - "LED-Mtx-S", /* 6 */ - "SDIO-0", /* 7 */ - "SDIO-1", /* 8 */ - "PCM", /* 9 */ - "I2S", /* 10 */ - "ETM", /* 11 */ - "Debug", /* 12 */ - "Misc", /* 13 */ - "0xE", /* 14 */ - "0xF", /* 15 */ -}; - -/****************************************************************************/ -/** -* @brief Retrieves a string representation of the mux setting for a pin. -* -* @return Pointer to a character string. -*/ -/****************************************************************************/ - -const char *chipcHw_getGpioPinFunctionStr(int pin) -{ - if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) { - return ""; - } - - return gMuxStr[chipcHw_getGpioPinFunction(pin)]; -} diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile deleted file mode 100644 index fb1104fe56b2..000000000000 --- a/arch/arm/mach-bcmring/csp/dmac/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c deleted file mode 100644 index 6b9be2e98e51..000000000000 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ /dev/null @@ -1,917 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw.c -* -* @brief Low level DMA controller driver routines -* -* @note -* -* These routines provide basic DMA functionality only. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <csp/string.h> -#include <stddef.h> - -#include <csp/dmacHw.h> -#include <mach/csp/dmacHw_reg.h> -#include <mach/csp/dmacHw_priv.h> -#include <mach/csp/chipcHw_inline.h> - -/* ---- External Function Prototypes ------------------------------------- */ - -/* Allocate DMA control blocks */ -dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; - -uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2; -uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2; - -/****************************************************************************/ -/** -* @brief Get maximum FIFO for a DMA channel -* -* @return Maximum allowable FIFO size -* -* -*/ -/****************************************************************************/ -static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - uint32_t val = 0; - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t *pMiscReg = - (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); - - switch (pCblk->channel) { - case 0: - val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; - break; - case 1: - val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; - break; - case 2: - val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; - break; - case 3: - val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; - break; - case 4: - val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; - break; - case 5: - val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; - break; - case 6: - val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; - break; - case 7: - val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; - break; - } - - if (val <= 0x4) { - return 8 << val; - } else { - dmacHw_ASSERT(0); - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Program channel register to initiate transfer -* -* @return void -* -* -* @note -* - Descriptor buffer MUST ALWAYS be flushed before calling this function -* - This function should also be called from ISR to program the channel with -* pending descriptors -*/ -/****************************************************************************/ -void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ) { - dmacHw_DESC_RING_t *pRing; - dmacHw_DESC_t *pProg; - dmacHw_CBLK_t *pCblk; - - pCblk = dmacHw_HANDLE_TO_CBLK(handle); - pRing = dmacHw_GET_DESC_RING(pDescriptor); - - if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) { - /* Not safe yet to program the channel */ - return; - } - - if (pCblk->varDataStarted) { - if (pCblk->descUpdated) { - pCblk->descUpdated = 0; - pProg = - (dmacHw_DESC_t *) ((uint32_t) - dmacHw_REG_LLP(pCblk->module, - pCblk->channel) + - pRing->virt2PhyOffset); - - /* Load descriptor if not loaded */ - if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) { - dmacHw_SET_SAR(pCblk->module, pCblk->channel, - pProg->sar); - dmacHw_SET_DAR(pCblk->module, pCblk->channel, - pProg->dar); - dmacHw_REG_CTL_LO(pCblk->module, - pCblk->channel) = - pProg->ctl.lo; - dmacHw_REG_CTL_HI(pCblk->module, - pCblk->channel) = - pProg->ctl.hi; - } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) { - /* Return as end descriptor is processed */ - return; - } else { - dmacHw_ASSERT(0); - } - } else { - return; - } - } else { - if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) { - /* Do not make a single chain, rather process one descriptor at a time */ - pProg = pRing->pHead; - /* Point to the next descriptor for next iteration */ - dmacHw_NEXT_DESC(pRing, pHead); - } else { - /* Return if no more pending descriptor */ - if (pRing->pEnd == NULL) { - return; - } - - pProg = pRing->pProg; - if (pConfig->transferMode == - dmacHw_TRANSFER_MODE_CONTINUOUS) { - /* Make sure a complete ring can be formed */ - dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd-> - llp == pRing->pProg); - /* Make sure pProg pointing to the pHead */ - dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg == - pRing->pHead); - /* Make a complete ring */ - do { - pRing->pProg->ctl.lo |= - (dmacHw_REG_CTL_LLP_DST_EN | - dmacHw_REG_CTL_LLP_SRC_EN); - pRing->pProg = - (dmacHw_DESC_t *) pRing->pProg->llp; - } while (pRing->pProg != pRing->pHead); - } else { - /* Make a single long chain */ - while (pRing->pProg != pRing->pEnd) { - pRing->pProg->ctl.lo |= - (dmacHw_REG_CTL_LLP_DST_EN | - dmacHw_REG_CTL_LLP_SRC_EN); - pRing->pProg = - (dmacHw_DESC_t *) pRing->pProg->llp; - } - } - } - - /* Program the channel registers */ - dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar); - dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar); - dmacHw_SET_LLP(pCblk->module, pCblk->channel, - (uint32_t) pProg - pRing->virt2PhyOffset); - dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) = - pProg->ctl.lo; - dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) = - pProg->ctl.hi; - if (pRing->pEnd) { - /* Remember the descriptor to use next */ - pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp; - } - /* Indicate no more pending descriptor */ - pRing->pEnd = (dmacHw_DESC_t *) NULL; - } - /* Start DMA operation */ - dmacHw_DMA_START(pCblk->module, pCblk->channel); -} - -/****************************************************************************/ -/** -* @brief Initializes DMA -* -* This function initializes DMA CSP driver -* -* @note -* Must be called before using any DMA channel -*/ -/****************************************************************************/ -void dmacHw_initDma(void) -{ - - uint32_t i = 0; - - dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0); - dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1); - - /* Enable access to the DMA block */ - chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0); - chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1); - - if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) { - dmacHw_ASSERT(0); - } - - memset((void *)dmacHw_gCblk, 0, - sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1)); - for (i = 0; i < dmaChannelCount_0; i++) { - dmacHw_gCblk[i].module = 0; - dmacHw_gCblk[i].channel = i; - } - for (i = 0; i < dmaChannelCount_1; i++) { - dmacHw_gCblk[i + dmaChannelCount_0].module = 1; - dmacHw_gCblk[i + dmaChannelCount_0].channel = i; - } -} - -/****************************************************************************/ -/** -* @brief Exit function for DMA -* -* This function isolates DMA from the system -* -*/ -/****************************************************************************/ -void dmacHw_exitDma(void) -{ - /* Disable access to the DMA block */ - chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0); - chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1); -} - -/****************************************************************************/ -/** -* @brief Gets a handle to a DMA channel -* -* This function returns a handle, representing a control block of a particular DMA channel -* -* @return -1 - On Failure -* handle - On Success, representing a channel control block -* -* @note -* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ - ) { - int idx; - - switch ((channelId >> 8)) { - case 0: - dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0); - idx = (channelId & 0xff); - break; - case 1: - dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1); - idx = dmaChannelCount_0 + (channelId & 0xff); - break; - default: - dmacHw_ASSERT(0); - return (dmacHw_HANDLE_t) -1; - } - - return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]); -} - -/****************************************************************************/ -/** -* @brief Initializes a DMA channel for use -* -* This function initializes and resets a DMA channel for use -* -* @return -1 - On Failure -* 0 - On Success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - int module = pCblk->module; - int channel = pCblk->channel; - - /* Reinitialize the control block */ - memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t)); - pCblk->module = module; - pCblk->channel = channel; - - /* Enable DMA controller */ - dmacHw_DMA_ENABLE(pCblk->module); - /* Reset DMA channel */ - dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel); - dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel); - dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel); - dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel); - - /* Clear all raw interrupt status */ - dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); - - /* Mask event specific interrupts */ - dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel); - dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel); - dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel); - dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel); - dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel); - - return 0; -} - -/****************************************************************************/ -/** -* @brief Finds amount of memory required to form a descriptor ring -* -* -* @return Number of bytes required to form a descriptor ring -* -* -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ - ) { - /* Need extra 4 byte to ensure 32 bit alignment */ - return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) + - sizeof(uint32_t); -} - -/****************************************************************************/ -/** -* @brief Initializes descriptor ring -* -* This function will initializes the descriptor ring of a DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* @note -* - "len" parameter should be obtained from "dmacHw_descriptorLen" -* - Descriptor buffer MUST be 32 bit aligned and uncached as it is -* accessed by ARM and DMA -*/ -/****************************************************************************/ -int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ - uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ - uint32_t len, /* [ IN ] Size of the pBuf */ - uint32_t num /* [ IN ] Number of descriptor in the ring */ - ) { - uint32_t i; - dmacHw_DESC_RING_t *pRing; - dmacHw_DESC_t *pDesc; - - /* Check the alignment of the descriptor */ - if ((uint32_t) pDescriptorVirt & 0x00000003) { - dmacHw_ASSERT(0); - return -1; - } - - /* Check if enough space has been allocated for descriptor ring */ - if (len < dmacHw_descriptorLen(num)) { - return -1; - } - - pRing = dmacHw_GET_DESC_RING(pDescriptorVirt); - pRing->pHead = - (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t)); - pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead; - pRing->pProg = dmacHw_DESC_INIT; - /* Initialize link item chain, starting from the head */ - pDesc = pRing->pHead; - /* Find the offset between virtual to physical address */ - pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr; - - /* Form the descriptor ring */ - for (i = 0; i < num - 1; i++) { - /* Clear link list item */ - memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t)); - /* Point to the next item in the physical address */ - pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset; - /* Point to the next item in the virtual address */ - pDesc->llp = (uint32_t) (pDesc + 1); - /* Mark descriptor is ready to use */ - pDesc->ctl.hi = dmacHw_DESC_FREE; - /* Look into next link list item */ - pDesc++; - } - - /* Clear last link list item */ - memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t)); - /* Last item pointing to the first item in the - physical address to complete the ring */ - pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset; - /* Last item pointing to the first item in the - virtual address to complete the ring - */ - pDesc->llp = (uint32_t) pRing->pHead; - /* Mark descriptor is ready to use */ - pDesc->ctl.hi = dmacHw_DESC_FREE; - /* Set the number of descriptors in the ring */ - pRing->num = num; - return 0; -} - -/****************************************************************************/ -/** -* @brief Configure DMA channel -* -* @return 0 : On success -* -1 : On failure -*/ -/****************************************************************************/ -int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - uint32_t cfgHigh = 0; - int srcTrSize; - int dstTrSize; - - pCblk->varDataStarted = 0; - pCblk->userData = NULL; - - /* Configure - - Burst transaction when enough data in available in FIFO - - AHB Access protection 1 - - Source and destination peripheral ports - */ - cfgHigh = - dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 | - dmacHw_SRC_PERI_INTF(pConfig-> - srcPeripheralPort) | - dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort); - /* Set priority */ - dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel, - pConfig->channelPriority); - - if (pConfig->dstStatusRegisterAddress != 0) { - /* Destination status update enable */ - cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT; - /* Configure status registers */ - dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel, - pConfig->dstStatusRegisterAddress); - } - - if (pConfig->srcStatusRegisterAddress != 0) { - /* Source status update enable */ - cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT; - /* Source status update enable */ - dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel, - pConfig->srcStatusRegisterAddress); - } - /* Configure the config high register */ - dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh; - - /* Clear all raw interrupt status */ - dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); - - /* Configure block interrupt */ - if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) { - dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel); - } else { - dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel); - } - /* Configure complete transfer interrupt */ - if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) { - dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel); - } else { - dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel); - } - /* Configure error interrupt */ - if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) { - dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel); - } else { - dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel); - } - /* Configure gather register */ - if (pConfig->srcGatherWidth) { - srcTrSize = - dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); - if (! - ((pConfig->srcGatherWidth % srcTrSize) - && (pConfig->srcGatherJump % srcTrSize))) { - dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) = - ((pConfig->srcGatherWidth / - srcTrSize) << 20) | (pConfig->srcGatherJump / - srcTrSize); - } else { - return -1; - } - } - /* Configure scatter register */ - if (pConfig->dstScatterWidth) { - dstTrSize = - dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); - if (! - ((pConfig->dstScatterWidth % dstTrSize) - && (pConfig->dstScatterJump % dstTrSize))) { - dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) = - ((pConfig->dstScatterWidth / - dstTrSize) << 20) | (pConfig->dstScatterJump / - dstTrSize); - } else { - return -1; - } - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Indicates whether DMA transfer is in progress or completed -* -* @return DMA transfer status -* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing -* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed -* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error -* -*/ -/****************************************************************************/ -dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) { - return dmacHw_TRANSFER_STATUS_BUSY; - } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) & - (0x00000001 << pCblk->channel)) { - return dmacHw_TRANSFER_STATUS_ERROR; - } - - return dmacHw_TRANSFER_STATUS_DONE; -} - -/****************************************************************************/ -/** -* @brief Set descriptors for known data length -* -* When DMA has to work as a flow controller, this function prepares the -* descriptor chain to transfer data -* -* from: -* - Memory to memory -* - Peripheral to memory -* - Memory to Peripheral -* - Peripheral to Peripheral -* -* @return -1 - On failure -* 0 - On success -* -*/ -/****************************************************************************/ -int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Data length in bytes */ - ) { - dmacHw_TRANSACTION_WIDTH_e dstTrWidth; - dmacHw_TRANSACTION_WIDTH_e srcTrWidth; - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - dmacHw_DESC_t *pStart; - dmacHw_DESC_t *pProg; - int srcTs = 0; - int blkTs = 0; - int oddSize = 0; - int descCount = 0; - int count = 0; - int dstTrSize = 0; - int srcTrSize = 0; - uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE; - - dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); - srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); - - /* Skip Tx if buffer is NULL or length is unknown */ - if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) { - /* Do not initiate transfer */ - return -1; - } - - /* Ensure scatter and gather are transaction aligned */ - if ((pConfig->srcGatherWidth % srcTrSize) - || (pConfig->dstScatterWidth % dstTrSize)) { - return -2; - } - - /* - Background 1: DMAC can not perform DMA if source and destination addresses are - not properly aligned with the channel's transaction width. So, for successful - DMA transfer, transaction width must be set according to the alignment of the - source and destination address. - */ - - /* Adjust destination transaction width if destination address is not aligned properly */ - dstTrWidth = pConfig->dstMaxTransactionWidth; - while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) { - dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth); - dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth); - } - - /* Adjust source transaction width if source address is not aligned properly */ - srcTrWidth = pConfig->srcMaxTransactionWidth; - while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) { - srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth); - srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth); - } - - /* Find the maximum transaction per descriptor */ - if (pConfig->maxDataPerBlock - && ((pConfig->maxDataPerBlock / srcTrSize) < - dmacHw_MAX_BLOCKSIZE)) { - maxBlockSize = pConfig->maxDataPerBlock / srcTrSize; - } - - /* Find number of source transactions needed to complete the DMA transfer */ - srcTs = dataLen / srcTrSize; - /* Find the odd number of bytes that need to be transferred as single byte transaction width */ - if (srcTs && (dstTrSize > srcTrSize)) { - oddSize = dataLen % dstTrSize; - /* Adjust source transaction count due to "oddSize" */ - srcTs = srcTs - (oddSize / srcTrSize); - } else { - oddSize = dataLen % srcTrSize; - } - /* Adjust "descCount" due to "oddSize" */ - if (oddSize) { - descCount++; - } - /* Find the number of descriptor needed for total "srcTs" */ - if (srcTs) { - descCount += ((srcTs - 1) / maxBlockSize) + 1; - } - - /* Check the availability of "descCount" discriptors in the ring */ - pProg = pRing->pHead; - for (count = 0; (descCount <= pRing->num) && (count < descCount); - count++) { - if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) { - /* Sufficient descriptors are not available */ - return -3; - } - pProg = (dmacHw_DESC_t *) pProg->llp; - } - - /* Remember the link list item to program the channel registers */ - pStart = pProg = pRing->pHead; - /* Make a link list with "descCount(=count)" number of descriptors */ - while (count) { - /* Reset channel control information */ - pProg->ctl.lo = 0; - /* Enable source gather if configured */ - if (pConfig->srcGatherWidth) { - pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE; - } - /* Enable destination scatter if configured */ - if (pConfig->dstScatterWidth) { - pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE; - } - /* Set source and destination address */ - pProg->sar = (uint32_t) pSrcAddr; - pProg->dar = (uint32_t) pDstAddr; - /* Use "devCtl" to mark that user memory need to be freed later if needed */ - if (pProg == pRing->pHead) { - pProg->devCtl = dmacHw_FREE_USER_MEMORY; - } else { - pProg->devCtl = 0; - } - - blkTs = srcTs; - - /* Special treatmeant for last descriptor */ - if (count == 1) { - /* Mark the last descriptor */ - pProg->ctl.lo &= - ~(dmacHw_REG_CTL_LLP_DST_EN | - dmacHw_REG_CTL_LLP_SRC_EN); - /* Treatment for odd data bytes */ - if (oddSize) { - /* Adjust for single byte transaction width */ - switch (pConfig->transferType) { - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: - dstTrWidth = - dmacHw_DST_TRANSACTION_WIDTH_8; - blkTs = - (oddSize / srcTrSize) + - ((oddSize % srcTrSize) ? 1 : 0); - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: - srcTrWidth = - dmacHw_SRC_TRANSACTION_WIDTH_8; - blkTs = oddSize; - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_MEM: - srcTrWidth = - dmacHw_SRC_TRANSACTION_WIDTH_8; - dstTrWidth = - dmacHw_DST_TRANSACTION_WIDTH_8; - blkTs = oddSize; - break; - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL: - /* Do not adjust the transaction width */ - break; - } - } else { - srcTs -= blkTs; - } - } else { - if (srcTs / maxBlockSize) { - blkTs = maxBlockSize; - } - /* Remaining source transactions for next iteration */ - srcTs -= blkTs; - } - /* Must have a valid source transactions */ - dmacHw_ASSERT(blkTs > 0); - /* Set control information */ - if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) { - pProg->ctl.lo |= pConfig->transferType | - pConfig->srcUpdate | - pConfig->dstUpdate | - srcTrWidth | - dstTrWidth | - pConfig->srcMaxBurstWidth | - pConfig->dstMaxBurstWidth | - pConfig->srcMasterInterface | - pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; - } else { - uint32_t transferType = 0; - switch (pConfig->transferType) { - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: - transferType = dmacHw_REG_CTL_TTFC_PM_PERI; - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: - transferType = dmacHw_REG_CTL_TTFC_MP_PERI; - break; - default: - dmacHw_ASSERT(0); - } - pProg->ctl.lo |= transferType | - pConfig->srcUpdate | - pConfig->dstUpdate | - srcTrWidth | - dstTrWidth | - pConfig->srcMaxBurstWidth | - pConfig->dstMaxBurstWidth | - pConfig->srcMasterInterface | - pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; - } - - /* Set block transaction size */ - pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK; - /* Look for next descriptor */ - if (count > 1) { - /* Point to the next descriptor */ - pProg = (dmacHw_DESC_t *) pProg->llp; - - /* Update source and destination address for next iteration */ - switch (pConfig->transferType) { - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: - if (pConfig->dstScatterWidth) { - pDstAddr = - (char *)pDstAddr + - blkTs * srcTrSize + - (((blkTs * srcTrSize) / - pConfig->dstScatterWidth) * - pConfig->dstScatterJump); - } else { - pDstAddr = - (char *)pDstAddr + - blkTs * srcTrSize; - } - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: - if (pConfig->srcGatherWidth) { - pSrcAddr = - (char *)pDstAddr + - blkTs * srcTrSize + - (((blkTs * srcTrSize) / - pConfig->srcGatherWidth) * - pConfig->srcGatherJump); - } else { - pSrcAddr = - (char *)pSrcAddr + - blkTs * srcTrSize; - } - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_MEM: - if (pConfig->dstScatterWidth) { - pDstAddr = - (char *)pDstAddr + - blkTs * srcTrSize + - (((blkTs * srcTrSize) / - pConfig->dstScatterWidth) * - pConfig->dstScatterJump); - } else { - pDstAddr = - (char *)pDstAddr + - blkTs * srcTrSize; - } - - if (pConfig->srcGatherWidth) { - pSrcAddr = - (char *)pDstAddr + - blkTs * srcTrSize + - (((blkTs * srcTrSize) / - pConfig->srcGatherWidth) * - pConfig->srcGatherJump); - } else { - pSrcAddr = - (char *)pSrcAddr + - blkTs * srcTrSize; - } - break; - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL: - /* Do not adjust the address */ - break; - default: - dmacHw_ASSERT(0); - } - } else { - /* At the end of transfer "srcTs" must be zero */ - dmacHw_ASSERT(srcTs == 0); - } - count--; - } - - /* Remember the descriptor to initialize the registers */ - if (pRing->pProg == dmacHw_DESC_INIT) { - pRing->pProg = pStart; - } - /* Indicate that the descriptor is updated */ - pRing->pEnd = pProg; - /* Head pointing to the next descriptor */ - pRing->pHead = (dmacHw_DESC_t *) pProg->llp; - /* Update Tail pointer if destination is a peripheral, - because no one is going to read from the pTail - */ - if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) { - pRing->pTail = pRing->pHead; - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Provides DMA controller attributes -* -* -* @return DMA controller attributes -* -* @note -* None -*/ -/****************************************************************************/ -uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - switch (attr) { - case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM: - return dmacHw_GET_NUM_CHANNEL(pCblk->module); - case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE: - return (1 << - (dmacHw_GET_MAX_BLOCK_SIZE - (pCblk->module, pCblk->module) + 2)) - 8; - case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM: - return dmacHw_GET_NUM_INTERFACE(pCblk->module); - case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH: - return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module, - pCblk->channel); - case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE: - return GetFifoSize(handle); - } - dmacHw_ASSERT(0); - return 0; -} diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c deleted file mode 100644 index a1f328357aa4..000000000000 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ /dev/null @@ -1,1017 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw_extra.c -* -* @brief Extra Low level DMA controller driver routines -* -* @note -* -* These routines provide basic DMA functionality only. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/stdint.h> -#include <stddef.h> - -#include <csp/dmacHw.h> -#include <mach/csp/dmacHw_reg.h> -#include <mach/csp/dmacHw_priv.h> - -extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; /* Declared in dmacHw.c */ - -/* ---- External Function Prototypes ------------------------------------- */ - -/* ---- Internal Use Function Prototypes --------------------------------- */ -/****************************************************************************/ -/** -* @brief Overwrites data length in the descriptor -* -* This function overwrites data length in the descriptor -* -* -* @return void -* -* @note -* This is only used for PCM channel -*/ -/****************************************************************************/ -void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - size_t dataLen /* [ IN ] Data length in bytes */ - ); - -/****************************************************************************/ -/** -* @brief Helper function to display DMA registers -* -* @return void -* -* -* @note -* None -*/ -/****************************************************************************/ -static void DisplayRegisterContents(int module, /* [ IN ] DMA Controller unit (0-1) */ - int channel, /* [ IN ] DMA Channel (0-7) / -1(all) */ - int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */ - ) { - int chan; - - (*fpPrint) ("Displaying register content \n\n"); - (*fpPrint) ("Module %d: Interrupt raw transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module))); - (*fpPrint) ("Module %d: Interrupt raw block 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module))); - (*fpPrint) ("Module %d: Interrupt raw src transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module))); - (*fpPrint) ("Module %d: Interrupt raw dst transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module))); - (*fpPrint) ("Module %d: Interrupt raw error 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module))); - (*fpPrint) ("--------------------------------------------------\n"); - (*fpPrint) ("Module %d: Interrupt stat transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module))); - (*fpPrint) ("Module %d: Interrupt stat block 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module))); - (*fpPrint) ("Module %d: Interrupt stat src transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module))); - (*fpPrint) ("Module %d: Interrupt stat dst transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module))); - (*fpPrint) ("Module %d: Interrupt stat error 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module))); - (*fpPrint) ("--------------------------------------------------\n"); - (*fpPrint) ("Module %d: Interrupt mask transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module))); - (*fpPrint) ("Module %d: Interrupt mask block 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module))); - (*fpPrint) ("Module %d: Interrupt mask src transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module))); - (*fpPrint) ("Module %d: Interrupt mask dst transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module))); - (*fpPrint) ("Module %d: Interrupt mask error 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module))); - (*fpPrint) ("--------------------------------------------------\n"); - (*fpPrint) ("Module %d: Interrupt clear transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module))); - (*fpPrint) ("Module %d: Interrupt clear block 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module))); - (*fpPrint) ("Module %d: Interrupt clear src transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module))); - (*fpPrint) ("Module %d: Interrupt clear dst transfer 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module))); - (*fpPrint) ("Module %d: Interrupt clear error 0x%X\n", - module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module))); - (*fpPrint) ("--------------------------------------------------\n"); - (*fpPrint) ("Module %d: SW source req 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module))); - (*fpPrint) ("Module %d: SW dest req 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module))); - (*fpPrint) ("Module %d: SW source signal 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module))); - (*fpPrint) ("Module %d: SW dest signal 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module))); - (*fpPrint) ("Module %d: SW source last 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module))); - (*fpPrint) ("Module %d: SW dest last 0x%X\n", - module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module))); - (*fpPrint) ("--------------------------------------------------\n"); - (*fpPrint) ("Module %d: misc config 0x%X\n", - module, (uint32_t) (dmacHw_REG_MISC_CFG(module))); - (*fpPrint) ("Module %d: misc channel enable 0x%X\n", - module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module))); - (*fpPrint) ("Module %d: misc ID 0x%X\n", - module, (uint32_t) (dmacHw_REG_MISC_ID(module))); - (*fpPrint) ("Module %d: misc test 0x%X\n", - module, (uint32_t) (dmacHw_REG_MISC_TEST(module))); - - if (channel == -1) { - for (chan = 0; chan < 8; chan++) { - (*fpPrint) - ("--------------------------------------------------\n"); - (*fpPrint) - ("Module %d: Channel %d Source 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_SAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Destination 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_DAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d LLP 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_LLP(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Control (LO) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CTL_LO(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Control (HI) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CTL_HI(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Source Stats 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_SSTAT(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Dest Stats 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_DSTAT(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Source Stats Addr 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_SSTATAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Dest Stats Addr 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_DSTATAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Config (LO) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CFG_LO(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Config (HI) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CFG_HI(module, chan))); - } - } else { - chan = channel; - (*fpPrint) - ("--------------------------------------------------\n"); - (*fpPrint) - ("Module %d: Channel %d Source 0x%X\n", - module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Destination 0x%X\n", - module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d LLP 0x%X\n", - module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Control (LO) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CTL_LO(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Control (HI) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CTL_HI(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Source Stats 0x%X\n", - module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Dest Stats 0x%X\n", - module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Source Stats Addr 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_SSTATAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Dest Stats Addr 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_DSTATAR(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Config (LO) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CFG_LO(module, chan))); - (*fpPrint) - ("Module %d: Channel %d Config (HI) 0x%X\n", - module, chan, - (uint32_t) (dmacHw_REG_CFG_HI(module, chan))); - } -} - -/****************************************************************************/ -/** -* @brief Helper function to display descriptor ring -* -* @return void -* -* -* @note -* None -*/ -/****************************************************************************/ -static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */ - int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */ - ) { - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - dmacHw_DESC_t *pStart; - - if (pRing->pHead == NULL) { - return; - } - - pStart = pRing->pHead; - - while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) { - if (pStart == pRing->pHead) { - (*fpPrint) ("Head\n"); - } - if (pStart == pRing->pTail) { - (*fpPrint) ("Tail\n"); - } - if (pStart == pRing->pProg) { - (*fpPrint) ("Prog\n"); - } - if (pStart == pRing->pEnd) { - (*fpPrint) ("End\n"); - } - if (pStart == pRing->pFree) { - (*fpPrint) ("Free\n"); - } - (*fpPrint) ("0x%X:\n", (uint32_t) pStart); - (*fpPrint) ("sar 0x%0X\n", pStart->sar); - (*fpPrint) ("dar 0x%0X\n", pStart->dar); - (*fpPrint) ("llp 0x%0X\n", pStart->llp); - (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); - (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); - (*fpPrint) ("sstat 0x%0X\n", pStart->sstat); - (*fpPrint) ("dstat 0x%0X\n", pStart->dstat); - (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl); - - pStart = (dmacHw_DESC_t *) pStart->llp; - } - if (pStart == pRing->pHead) { - (*fpPrint) ("Head\n"); - } - if (pStart == pRing->pTail) { - (*fpPrint) ("Tail\n"); - } - if (pStart == pRing->pProg) { - (*fpPrint) ("Prog\n"); - } - if (pStart == pRing->pEnd) { - (*fpPrint) ("End\n"); - } - if (pStart == pRing->pFree) { - (*fpPrint) ("Free\n"); - } - (*fpPrint) ("0x%X:\n", (uint32_t) pStart); - (*fpPrint) ("sar 0x%0X\n", pStart->sar); - (*fpPrint) ("dar 0x%0X\n", pStart->dar); - (*fpPrint) ("llp 0x%0X\n", pStart->llp); - (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); - (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); - (*fpPrint) ("sstat 0x%0X\n", pStart->sstat); - (*fpPrint) ("dstat 0x%0X\n", pStart->dstat); - (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl); -} - -/****************************************************************************/ -/** -* @brief Check if DMA channel is the flow controller -* -* @return 1 : If DMA is a flow controller -* 0 : Peripheral is the flow controller -* -* @note -* None -*/ -/****************************************************************************/ -static inline int DmaIsFlowController(void *pDescriptor /* [ IN ] Descriptor buffer */ - ) { - uint32_t ttfc = - (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl. - lo & dmacHw_REG_CTL_TTFC_MASK; - - switch (ttfc) { - case dmacHw_REG_CTL_TTFC_MM_DMAC: - case dmacHw_REG_CTL_TTFC_MP_DMAC: - case dmacHw_REG_CTL_TTFC_PM_DMAC: - case dmacHw_REG_CTL_TTFC_PP_DMAC: - return 1; - } - - return 0; -} - -/****************************************************************************/ -/** -* @brief Overwrites data length in the descriptor -* -* This function overwrites data length in the descriptor -* -* -* @return void -* -* @note -* This is only used for PCM channel -*/ -/****************************************************************************/ -void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - size_t dataLen /* [ IN ] Data length in bytes */ - ) { - dmacHw_DESC_t *pProg; - dmacHw_DESC_t *pHead; - int srcTs = 0; - int srcTrSize = 0; - - pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead; - pProg = pHead; - - srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); - srcTs = dataLen / srcTrSize; - do { - pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK; - pProg = (dmacHw_DESC_t *) pProg->llp; - } while (pProg != pHead); -} - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the DMA channel specific interrupt -* -* -* @return void -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); - dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); -} - -/****************************************************************************/ -/** -* @brief Returns the cause of channel specific DMA interrupt -* -* This function returns the cause of interrupt -* -* @return Interrupt status, each bit representing a specific type of interrupt -* -* @note -* Should be called under the context of ISR -*/ -/****************************************************************************/ -dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE; - - if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) & - ((0x00000001 << pCblk->channel))) { - status |= dmacHw_INTERRUPT_STATUS_TRANS; - } - if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) & - ((0x00000001 << pCblk->channel))) { - status |= dmacHw_INTERRUPT_STATUS_BLOCK; - } - if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) & - ((0x00000001 << pCblk->channel))) { - status |= dmacHw_INTERRUPT_STATUS_ERROR; - } - - return status; -} - -/****************************************************************************/ -/** -* @brief Indentifies a DMA channel causing interrupt -* -* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e -* -* @return NULL : No channel causing DMA interrupt -* ! NULL : Handle to a channel causing DMA interrupt -* @note -* dmacHw_clearInterrupt() must be called with a valid handle after calling this function -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getInterruptSource(void) -{ - uint32_t i; - - for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) { - if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) & - ((0x00000001 << dmacHw_gCblk[i].channel))) - || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) & - ((0x00000001 << dmacHw_gCblk[i].channel))) - || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) & - ((0x00000001 << dmacHw_gCblk[i].channel))) - ) { - return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]); - } - } - return dmacHw_CBLK_TO_HANDLE(NULL); -} - -/****************************************************************************/ -/** -* @brief Estimates number of descriptor needed to perform certain DMA transfer -* -* -* @return On failure : -1 -* On success : Number of descriptor count -* -* -*/ -/****************************************************************************/ -int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Data length in bytes */ - ) { - int srcTs = 0; - int oddSize = 0; - int descCount = 0; - int dstTrSize = 0; - int srcTrSize = 0; - uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE; - dmacHw_TRANSACTION_WIDTH_e dstTrWidth; - dmacHw_TRANSACTION_WIDTH_e srcTrWidth; - - dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); - srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); - - /* Skip Tx if buffer is NULL or length is unknown */ - if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) { - /* Do not initiate transfer */ - return -1; - } - - /* Ensure scatter and gather are transaction aligned */ - if (pConfig->srcGatherWidth % srcTrSize - || pConfig->dstScatterWidth % dstTrSize) { - return -1; - } - - /* - Background 1: DMAC can not perform DMA if source and destination addresses are - not properly aligned with the channel's transaction width. So, for successful - DMA transfer, transaction width must be set according to the alignment of the - source and destination address. - */ - - /* Adjust destination transaction width if destination address is not aligned properly */ - dstTrWidth = pConfig->dstMaxTransactionWidth; - while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) { - dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth); - dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth); - } - - /* Adjust source transaction width if source address is not aligned properly */ - srcTrWidth = pConfig->srcMaxTransactionWidth; - while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) { - srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth); - srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth); - } - - /* Find the maximum transaction per descriptor */ - if (pConfig->maxDataPerBlock - && ((pConfig->maxDataPerBlock / srcTrSize) < - dmacHw_MAX_BLOCKSIZE)) { - maxBlockSize = pConfig->maxDataPerBlock / srcTrSize; - } - - /* Find number of source transactions needed to complete the DMA transfer */ - srcTs = dataLen / srcTrSize; - /* Find the odd number of bytes that need to be transferred as single byte transaction width */ - if (srcTs && (dstTrSize > srcTrSize)) { - oddSize = dataLen % dstTrSize; - /* Adjust source transaction count due to "oddSize" */ - srcTs = srcTs - (oddSize / srcTrSize); - } else { - oddSize = dataLen % srcTrSize; - } - /* Adjust "descCount" due to "oddSize" */ - if (oddSize) { - descCount++; - } - - /* Find the number of descriptor needed for total "srcTs" */ - if (srcTs) { - descCount += ((srcTs - 1) / maxBlockSize) + 1; - } - - return descCount; -} - -/****************************************************************************/ -/** -* @brief Check the existence of pending descriptor -* -* This function confirmes if there is any pending descriptor in the chain -* to program the channel -* -* @return 1 : Channel need to be programmed with pending descriptor -* 0 : No more pending descriptor to programe the channel -* -* @note -* - This function should be called from ISR in case there are pending -* descriptor to program the channel. -* -* Example: -* -* dmac_isr () -* { -* ... -* if (dmacHw_descriptorPending (handle)) -* { -* dmacHw_initiateTransfer (handle); -* } -* } -* -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - - /* Make sure channel is not busy */ - if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) { - /* Check if pEnd is not processed */ - if (pRing->pEnd) { - /* Something left for processing */ - return 1; - } - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Program channel register to stop transfer -* -* Ensures the channel is not doing any transfer after calling this function -* -* @return void -* -*/ -/****************************************************************************/ -void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk; - - pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - /* Stop the channel */ - dmacHw_DMA_STOP(pCblk->module, pCblk->channel); -} - -/****************************************************************************/ -/** -* @brief Deallocates source or destination memory, allocated -* -* This function can be called to deallocate data memory that was DMAed successfully -* -* @return On failure : -1 -* On success : Number of buffer freed -* -* @note -* This function will be called ONLY, when source OR destination address is pointing -* to dynamic memory -*/ -/****************************************************************************/ -int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ - ) { - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - uint32_t count = 0; - - if (fpFree == NULL) { - return -1; - } - - while ((pRing->pFree != pRing->pTail) - && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) { - if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) { - /* Identify, which memory to free */ - if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) { - (*fpFree) ((void *)pRing->pFree->dar); - } else { - /* Destination was a peripheral */ - (*fpFree) ((void *)pRing->pFree->sar); - } - /* Unmark user memory to indicate it is freed */ - pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY; - } - dmacHw_NEXT_DESC(pRing, pFree); - - count++; - } - - return count; -} - -/****************************************************************************/ -/** -* @brief Prepares descriptor ring, when source peripheral working as a flow controller -* -* This function will update the discriptor ring by allocating buffers, when source peripheral -* has to work as a flow controller to transfer data from: -* - Peripheral to memory. -* -* @return On failure : -1 -* On success : Number of descriptor updated -* -* -* @note -* Channel must be configured for peripheral to memory transfer -* -*/ -/****************************************************************************/ -int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t srcAddr, /* [ IN ] Source peripheral address */ - void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ - int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ - int num /* [ IN ] Number of descriptor to set */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_DESC_t *pProg = NULL; - dmacHw_DESC_t *pLast = NULL; - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - uint32_t dstAddr; - uint32_t controlParam; - int i; - - dmacHw_ASSERT(pConfig->transferType == - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM); - - if (num > pRing->num) { - return -1; - } - - pLast = pRing->pEnd; /* Last descriptor updated */ - pProg = pRing->pHead; /* First descriptor in the new list */ - - controlParam = pConfig->srcUpdate | - pConfig->dstUpdate | - pConfig->srcMaxTransactionWidth | - pConfig->dstMaxTransactionWidth | - pConfig->srcMasterInterface | - pConfig->dstMasterInterface | - pConfig->srcMaxBurstWidth | - pConfig->dstMaxBurstWidth | - dmacHw_REG_CTL_TTFC_PM_PERI | - dmacHw_REG_CTL_LLP_DST_EN | - dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN; - - for (i = 0; i < num; i++) { - /* Allocate Rx buffer only for idle descriptor */ - if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) || - ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail) - ) { - /* Rx descriptor is not idle */ - break; - } - /* Set source address */ - pRing->pHead->sar = srcAddr; - if (fpAlloc) { - /* Allocate memory for buffer in descriptor */ - dstAddr = (uint32_t) (*fpAlloc) (len); - /* Check the destination address */ - if (dstAddr == 0) { - if (i == 0) { - /* Not a single descriptor is available */ - return -1; - } - break; - } - /* Set destination address */ - pRing->pHead->dar = dstAddr; - } - /* Set control information */ - pRing->pHead->ctl.lo = controlParam; - /* Use "devCtl" to mark the memory that need to be freed later */ - pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY; - /* Descriptor is now owned by the channel */ - pRing->pHead->ctl.hi = 0; - /* Remember the descriptor last updated */ - pRing->pEnd = pRing->pHead; - /* Update next descriptor */ - dmacHw_NEXT_DESC(pRing, pHead); - } - - /* Mark the end of the list */ - pRing->pEnd->ctl.lo &= - ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN); - /* Connect the list */ - if (pLast != pProg) { - pLast->ctl.lo |= - dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN; - } - /* Mark the descriptors are updated */ - pCblk->descUpdated = 1; - if (!pCblk->varDataStarted) { - /* LLP must be pointing to the first descriptor */ - dmacHw_SET_LLP(pCblk->module, pCblk->channel, - (uint32_t) pProg - pRing->virt2PhyOffset); - /* Channel, handling variable data started */ - pCblk->varDataStarted = 1; - } - - return i; -} - -/****************************************************************************/ -/** -* @brief Read data DMAed to memory -* -* This function will read data that has been DMAed to memory while transferring from: -* - Memory to memory -* - Peripheral to memory -* -* @param handle - -* @param ppBbuf - -* @param pLen - -* -* @return 0 - No more data is available to read -* 1 - More data might be available to read -* -*/ -/****************************************************************************/ -int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void **ppBbuf, /* [ OUT ] Data received */ - size_t *pLlen /* [ OUT ] Length of the data received */ - ) { - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - - (void)handle; - - if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) { - if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) || - (pRing->pTail == pRing->pHead) - ) { - /* No receive data available */ - *ppBbuf = (char *)NULL; - *pLlen = 0; - - return 0; - } - } - - /* Return read buffer and length */ - *ppBbuf = (char *)pRing->pTail->dar; - - /* Extract length of the received data */ - if (DmaIsFlowController(pDescriptor)) { - uint32_t srcTrSize = 0; - - switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) { - case dmacHw_REG_CTL_SRC_TR_WIDTH_8: - srcTrSize = 1; - break; - case dmacHw_REG_CTL_SRC_TR_WIDTH_16: - srcTrSize = 2; - break; - case dmacHw_REG_CTL_SRC_TR_WIDTH_32: - srcTrSize = 4; - break; - case dmacHw_REG_CTL_SRC_TR_WIDTH_64: - srcTrSize = 8; - break; - default: - dmacHw_ASSERT(0); - } - /* Calculate length from the block size */ - *pLlen = - (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) * - srcTrSize; - } else { - /* Extract length from the source peripheral */ - *pLlen = pRing->pTail->sstat; - } - - /* Advance tail to next descriptor */ - dmacHw_NEXT_DESC(pRing, pTail); - - return 1; -} - -/****************************************************************************/ -/** -* @brief Set descriptor carrying control information -* -* This function will be used to send specific control information to the device -* using the DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t ctlAddress, /* [ IN ] Address of the device control register */ - uint32_t control /* [ IN ] Device control information */ - ) { - dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); - - if (ctlAddress == 0) { - return -1; - } - - /* Check the availability of descriptors in the ring */ - if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) { - return -1; - } - /* Set control information */ - pRing->pHead->devCtl = control; - /* Set source and destination address */ - pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl; - pRing->pHead->dar = ctlAddress; - /* Set control parameters */ - if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) { - pRing->pHead->ctl.lo = pConfig->transferType | - dmacHw_SRC_ADDRESS_UPDATE_MODE_INC | - dmacHw_DST_ADDRESS_UPDATE_MODE_INC | - dmacHw_SRC_TRANSACTION_WIDTH_32 | - pConfig->dstMaxTransactionWidth | - dmacHw_SRC_BURST_WIDTH_0 | - dmacHw_DST_BURST_WIDTH_0 | - pConfig->srcMasterInterface | - pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; - } else { - uint32_t transferType = 0; - switch (pConfig->transferType) { - case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: - transferType = dmacHw_REG_CTL_TTFC_PM_PERI; - break; - case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: - transferType = dmacHw_REG_CTL_TTFC_MP_PERI; - break; - default: - dmacHw_ASSERT(0); - } - pRing->pHead->ctl.lo = transferType | - dmacHw_SRC_ADDRESS_UPDATE_MODE_INC | - dmacHw_DST_ADDRESS_UPDATE_MODE_INC | - dmacHw_SRC_TRANSACTION_WIDTH_32 | - pConfig->dstMaxTransactionWidth | - dmacHw_SRC_BURST_WIDTH_0 | - dmacHw_DST_BURST_WIDTH_0 | - pConfig->srcMasterInterface | - pConfig->dstMasterInterface | - pConfig->flowControler | dmacHw_REG_CTL_INT_EN; - } - - /* Set block transaction size to one 32 bit transaction */ - pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1; - - /* Remember the descriptor to initialize the registers */ - if (pRing->pProg == dmacHw_DESC_INIT) { - pRing->pProg = pRing->pHead; - } - pRing->pEnd = pRing->pHead; - - /* Advance the descriptor */ - dmacHw_NEXT_DESC(pRing, pHead); - - /* Update Tail pointer if destination is a peripheral */ - if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) { - pRing->pTail = pRing->pHead; - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Sets channel specific user data -* -* This function associates user data to a specific DMA channel -* -*/ -/****************************************************************************/ -void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *userData /* [ IN ] User data */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - pCblk->userData = userData; -} - -/****************************************************************************/ -/** -* @brief Gets channel specific user data -* -* This function returns user data specific to a DMA channel -* -* @return user data -*/ -/****************************************************************************/ -void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - return pCblk->userData; -} - -/****************************************************************************/ -/** -* @brief Resets descriptor control information -* -* @return void -*/ -/****************************************************************************/ -void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ - ) { - int i; - dmacHw_DESC_RING_t *pRing; - dmacHw_DESC_t *pDesc; - - pRing = dmacHw_GET_DESC_RING(pDescriptor); - pDesc = pRing->pHead; - - for (i = 0; i < pRing->num; i++) { - /* Mark descriptor is ready to use */ - pDesc->ctl.hi = dmacHw_DESC_FREE; - /* Look into next link list item */ - pDesc++; - } - pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead; - pRing->pProg = dmacHw_DESC_INIT; -} - -/****************************************************************************/ -/** -* @brief Displays channel specific registers and other control parameters -* -* @return void -* -* -* @note -* None -*/ -/****************************************************************************/ -void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ - ) { - dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - - DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint); - DisplayDescRing(pDescriptor, fpPrint); -} diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile deleted file mode 100644 index 244a61ab7697..000000000000 --- a/arch/arm/mach-bcmring/csp/tmr/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += tmrHw.o diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c deleted file mode 100644 index 16225e43f3c3..000000000000 --- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ /dev/null @@ -1,576 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file tmrHw.c -* -* @brief Low level Timer driver routines -* -* @note -* -* These routines provide basic timer functionality only. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/errno.h> -#include <csp/stdint.h> - -#include <csp/tmrHw.h> -#include <mach/csp/tmrHw_reg.h> - -#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 -#define tmrHw_MILLISEC_PER_SEC (1000) - -#define tmrHw_LOW_1_RESOLUTION_COUNT (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC) -#define tmrHw_LOW_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT) -#define tmrHw_LOW_16_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 16) -#define tmrHw_LOW_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT) -#define tmrHw_LOW_256_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 256) -#define tmrHw_LOW_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT) - -#define tmrHw_HIGH_1_RESOLUTION_COUNT (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC) -#define tmrHw_HIGH_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT) -#define tmrHw_HIGH_16_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 16) -#define tmrHw_HIGH_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT) -#define tmrHw_HIGH_256_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 256) -#define tmrHw_HIGH_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT) - -static void ResetTimer(tmrHw_ID_t timerId) - __attribute__ ((section(".aramtext"))); -static int tmrHw_divide(int num, int denom) - __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Get timer capability -* -* This function returns various capabilities/attributes of a timer -* -* @return Capability -* -*/ -/****************************************************************************/ -uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ -) { - switch (capability) { - case tmrHw_CAPABILITY_CLOCK: - return (timerId <= - 1) ? tmrHw_LOW_RESOLUTION_CLOCK : - tmrHw_HIGH_RESOLUTION_CLOCK; - case tmrHw_CAPABILITY_RESOLUTION: - return 32; - default: - return 0; - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Resets a timer -* -* This function initializes timer -* -* @return void -* -*/ -/****************************************************************************/ -static void ResetTimer(tmrHw_ID_t timerId /* [ IN ] Timer Id */ -) { - /* Reset timer */ - pTmrHw[timerId].LoadValue = 0; - pTmrHw[timerId].CurrentValue = 0xFFFFFFFF; - pTmrHw[timerId].Control = 0; - pTmrHw[timerId].BackgroundLoad = 0; - /* Always configure as a 32 bit timer */ - pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT; - /* Clear interrupt only if raw status interrupt is set */ - if (pTmrHw[timerId].RawInterruptStatus) { - pTmrHw[timerId].InterruptClear = 0xFFFFFFFF; - } -} - -/****************************************************************************/ -/** -* @brief Sets counter value for an interval in ms -* -* @return On success: Effective counter value set -* On failure: 0 -* -*/ -/****************************************************************************/ -static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ -) { - uint32_t scale = 0; - uint32_t count = 0; - - if (timerId == 0 || timerId == 1) { - if (msec <= tmrHw_LOW_1_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; - scale = tmrHw_LOW_1_RESOLUTION_COUNT; - } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; - scale = tmrHw_LOW_16_RESOLUTION_COUNT; - } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; - scale = tmrHw_LOW_256_RESOLUTION_COUNT; - } else { - return 0; - } - - count = msec * scale; - /* Set counter value */ - pTmrHw[timerId].LoadValue = count; - pTmrHw[timerId].BackgroundLoad = count; - - } else if (timerId == 2 || timerId == 3) { - if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; - scale = tmrHw_HIGH_1_RESOLUTION_COUNT; - } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; - scale = tmrHw_HIGH_16_RESOLUTION_COUNT; - } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; - scale = tmrHw_HIGH_256_RESOLUTION_COUNT; - } else { - return 0; - } - - count = msec * scale; - /* Set counter value */ - pTmrHw[timerId].LoadValue = count; - pTmrHw[timerId].BackgroundLoad = count; - } - return count / scale; -} - -/****************************************************************************/ -/** -* @brief Configures a periodic timer in terms of timer interrupt rate -* -* This function initializes a periodic timer to generate specific number of -* timer interrupt per second -* -* @return On success: Effective timer frequency -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ -) { - uint32_t resolution = 0; - uint32_t count = 0; - ResetTimer(timerId); - - /* Set timer mode periodic */ - pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; - /* Set timer in highest resolution */ - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; - - if (rate && (timerId == 0 || timerId == 1)) { - if (rate > tmrHw_LOW_RESOLUTION_CLOCK) { - return 0; - } - resolution = tmrHw_LOW_RESOLUTION_CLOCK; - } else if (rate && (timerId == 2 || timerId == 3)) { - if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) { - return 0; - } else { - resolution = tmrHw_HIGH_RESOLUTION_CLOCK; - } - } else { - return 0; - } - /* Find the counter value */ - count = resolution / rate; - /* Set counter value */ - pTmrHw[timerId].LoadValue = count; - pTmrHw[timerId].BackgroundLoad = count; - - return resolution / count; -} - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt after -* certain time interval -* -* This function initializes a periodic timer to generate timer interrupt -* after every time interval in millisecond -* -* @return On success: Effective interval set in milli-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ -) { - ResetTimer(timerId); - - /* Set timer mode periodic */ - pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; - - return SetTimerPeriod(timerId, msec); -} - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt just once -* after certain time interval -* -* This function initializes a periodic timer to generate a single ticks after -* certain time interval in millisecond -* -* @return On success: Effective interval set in milli-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ -) { - ResetTimer(timerId); - - /* Set timer mode oneshot */ - pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; - pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT; - - return SetTimerPeriod(timerId, msec); -} - -/****************************************************************************/ -/** -* @brief Configures a timer to run as a free running timer -* -* This function initializes a timer to run as a free running timer -* -* @return Timer resolution (count / sec) -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - uint32_t divider /* [ IN ] Dividing the clock frequency */ -) { - uint32_t scale = 0; - - ResetTimer(timerId); - /* Set timer as free running mode */ - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC; - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; - - if (divider >= 64) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; - scale = 256; - } else if (divider >= 8) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; - scale = 16; - } else { - pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; - scale = 1; - } - - if (timerId == 0 || timerId == 1) { - return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale); - } else if (timerId == 2 || timerId == 3) { - return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale); - } - - return 0; -} - -/****************************************************************************/ -/** -* @brief Starts a timer -* -* This function starts a preconfigured timer -* -* @return -1 - On Failure -* 0 - On Success -* -*/ -/****************************************************************************/ -int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE; - return 0; -} - -/****************************************************************************/ -/** -* @brief Stops a timer -* -* This function stops a running timer -* -* @return -1 - On Failure -* 0 - On Success -* -*/ -/****************************************************************************/ -int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE; - return 0; -} - -/****************************************************************************/ -/** -* @brief Gets current timer count -* -* This function returns the current timer value -* -* @return Current downcounting timer value -* -*/ -/****************************************************************************/ -uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - /* return 32 bit timer value */ - switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) { - case tmrHw_CONTROL_FREE_RUNNING: - if (pTmrHw[timerId].CurrentValue) { - return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue; - } - break; - case tmrHw_CONTROL_PERIODIC: - case tmrHw_CONTROL_ONESHOT: - return pTmrHw[timerId].BackgroundLoad - - pTmrHw[timerId].CurrentValue; - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Gets timer count rate -* -* This function returns the number of counts per second -* -* @return Count rate -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - uint32_t divider = 0; - - switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) { - case tmrHw_CONTROL_PRESCALE_1: - divider = 1; - break; - case tmrHw_CONTROL_PRESCALE_16: - divider = 16; - break; - case tmrHw_CONTROL_PRESCALE_256: - divider = 256; - break; - default: - tmrHw_ASSERT(0); - } - - if (timerId == 0 || timerId == 1) { - return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider); - } else { - return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider); - } - return 0; -} - -/****************************************************************************/ -/** -* @brief Enables timer interrupt -* -* This function enables the timer interrupt -* -* @return N/A -* -*/ -/****************************************************************************/ -void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE; -} - -/****************************************************************************/ -/** -* @brief Disables timer interrupt -* -* This function disable the timer interrupt -* -* @return N/A -* -*/ -/****************************************************************************/ -void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE; -} - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the timer interrupt -* -* @return N/A -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - pTmrHw[timerId].InterruptClear = 0x1; -} - -/****************************************************************************/ -/** -* @brief Gets the interrupt status -* -* This function returns timer interrupt status -* -* @return Interrupt status -*/ -/****************************************************************************/ -tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) { - if (pTmrHw[timerId].InterruptStatus) { - return tmrHw_INTERRUPT_STATUS_SET; - } else { - return tmrHw_INTERRUPT_STATUS_UNSET; - } -} - -/****************************************************************************/ -/** -* @brief Indentifies a timer causing interrupt -* -* This functions returns a timer causing interrupt -* -* @return 0xFFFFFFFF : No timer causing an interrupt -* ! 0xFFFFFFFF : timer causing an interrupt -* @note -* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function -*/ -/****************************************************************************/ -tmrHw_ID_t tmrHw_getInterruptSource(void /* void */ -) { - int i; - - for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) { - if (pTmrHw[i].InterruptStatus) { - return i; - } - } - - return 0xFFFFFFFF; -} - -/****************************************************************************/ -/** -* @brief Displays specific timer registers -* -* -* @return void -* -*/ -/****************************************************************************/ -void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ -) { - (*fpPrint) ("Displaying register contents \n\n"); - (*fpPrint) ("Timer %d: Load value 0x%X\n", timerId, - pTmrHw[timerId].LoadValue); - (*fpPrint) ("Timer %d: Background load value 0x%X\n", timerId, - pTmrHw[timerId].BackgroundLoad); - (*fpPrint) ("Timer %d: Control 0x%X\n", timerId, - pTmrHw[timerId].Control); - (*fpPrint) ("Timer %d: Interrupt clear 0x%X\n", timerId, - pTmrHw[timerId].InterruptClear); - (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId, - pTmrHw[timerId].RawInterruptStatus); - (*fpPrint) ("Timer %d: Interrupt status 0x%X\n", timerId, - pTmrHw[timerId].InterruptStatus); -} - -/****************************************************************************/ -/** -* @brief Use a timer to perform a busy wait delay for a number of usecs. -* -* @return N/A -*/ -/****************************************************************************/ -void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - unsigned long usecs /* [ IN ] usec to delay */ -) { - tmrHw_RATE_t usec_tick_rate; - tmrHw_COUNT_t start_time; - tmrHw_COUNT_t delta_time; - - start_time = tmrHw_GetCurrentCount(timerId); - usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000); - delta_time = usecs * usec_tick_rate; - - /* Busy wait */ - while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time)) - ; -} - -/****************************************************************************/ -/** -* @brief Local Divide function -* -* This function does the divide -* -* @return divide value -* -*/ -/****************************************************************************/ -static int tmrHw_divide(int num, int denom) -{ - int r; - int t = 1; - - /* Shift denom and t up to the largest value to optimize algorithm */ - /* t contains the units of each divide */ - while ((denom & 0x40000000) == 0) { /* fails if denom=0 */ - denom = denom << 1; - t = t << 1; - } - - /* Initialize the result */ - r = 0; - - do { - /* Determine if there exists a positive remainder */ - if ((num - denom) >= 0) { - /* Accumlate t to the result and calculate a new remainder */ - num = num - denom; - r = r + t; - } - /* Continue to shift denom and shift t down to 0 */ - denom = denom >> 1; - t = t >> 1; - } while (t != 0); - return r; -} diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c deleted file mode 100644 index e5fd241fccdc..000000000000 --- a/arch/arm/mach-bcmring/dma.c +++ /dev/null @@ -1,1518 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dma.c -* -* @brief Implements the DMA interface. -*/ -/****************************************************************************/ - -/* ---- Include Files ---------------------------------------------------- */ - -#include <linux/module.h> -#include <linux/device.h> -#include <linux/dma-mapping.h> -#include <linux/interrupt.h> -#include <linux/sched.h> -#include <linux/irqreturn.h> -#include <linux/proc_fs.h> -#include <linux/slab.h> - -#include <mach/timer.h> - -#include <linux/pfn.h> -#include <linux/atomic.h> -#include <mach/dma.h> - -/* ---- Public Variables ------------------------------------------------- */ - -/* ---- Private Constants and Types -------------------------------------- */ - -#define MAKE_HANDLE(controllerIdx, channelIdx) (((controllerIdx) << 4) | (channelIdx)) - -#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) -#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) - - -/* ---- Private Variables ------------------------------------------------ */ - -static DMA_Global_t gDMA; -static struct proc_dir_entry *gDmaDir; - -#include "dma_device.c" - -/* ---- Private Function Prototypes -------------------------------------- */ - -/* ---- Functions ------------------------------------------------------- */ - -/****************************************************************************/ -/** -* Displays information for /proc/dma/channels -*/ -/****************************************************************************/ - -static int dma_proc_read_channels(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int controllerIdx; - int channelIdx; - int limit = count - 200; - int len = 0; - DMA_Channel_t *channel; - - if (down_interruptible(&gDMA.lock) < 0) { - return -ERESTARTSYS; - } - - for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; - controllerIdx++) { - for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; - channelIdx++) { - if (len >= limit) { - break; - } - - channel = - &gDMA.controller[controllerIdx].channel[channelIdx]; - - len += - sprintf(buf + len, "%d:%d ", controllerIdx, - channelIdx); - - if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) != - 0) { - len += - sprintf(buf + len, "Dedicated for %s ", - DMA_gDeviceAttribute[channel-> - devType].name); - } else { - len += sprintf(buf + len, "Shared "); - } - - if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) { - len += sprintf(buf + len, "No ISR "); - } - - if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) { - len += sprintf(buf + len, "Fifo: 128 "); - } else { - len += sprintf(buf + len, "Fifo: 64 "); - } - - if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) { - len += - sprintf(buf + len, "InUse by %s", - DMA_gDeviceAttribute[channel-> - devType].name); -#if (DMA_DEBUG_TRACK_RESERVATION) - len += - sprintf(buf + len, " (%s:%d)", - channel->fileName, - channel->lineNum); -#endif - } else { - len += sprintf(buf + len, "Avail "); - } - - if (channel->lastDevType != DMA_DEVICE_NONE) { - len += - sprintf(buf + len, "Last use: %s ", - DMA_gDeviceAttribute[channel-> - lastDevType]. - name); - } - - len += sprintf(buf + len, "\n"); - } - } - up(&gDMA.lock); - *eof = 1; - - return len; -} - -/****************************************************************************/ -/** -* Displays information for /proc/dma/devices -*/ -/****************************************************************************/ - -static int dma_proc_read_devices(char *buf, char **start, off_t offset, - int count, int *eof, void *data) -{ - int limit = count - 200; - int len = 0; - int devIdx; - - if (down_interruptible(&gDMA.lock) < 0) { - return -ERESTARTSYS; - } - - for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) { - DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx]; - - if (devAttr->name == NULL) { - continue; - } - - if (len >= limit) { - break; - } - - len += sprintf(buf + len, "%-12s ", devAttr->name); - - if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { - len += - sprintf(buf + len, "Dedicated %d:%d ", - devAttr->dedicatedController, - devAttr->dedicatedChannel); - } else { - len += sprintf(buf + len, "Shared DMA:"); - if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) { - len += sprintf(buf + len, "0"); - } - if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) { - len += sprintf(buf + len, "1"); - } - len += sprintf(buf + len, " "); - } - if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) { - len += sprintf(buf + len, "NoISR "); - } - if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) { - len += sprintf(buf + len, "Allow-128 "); - } - - len += - sprintf(buf + len, - "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n", - devAttr->numTransfers, devAttr->transferTicks, - devAttr->transferBytes, - devAttr->ring.bytesAllocated); - - } - - up(&gDMA.lock); - *eof = 1; - - return len; -} - -/****************************************************************************/ -/** -* Determines if a DMA_Device_t is "valid". -* -* @return -* TRUE - dma device is valid -* FALSE - dma device isn't valid -*/ -/****************************************************************************/ - -static inline int IsDeviceValid(DMA_Device_t device) -{ - return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES); -} - -/****************************************************************************/ -/** -* Translates a DMA handle into a pointer to a channel. -* -* @return -* non-NULL - pointer to DMA_Channel_t -* NULL - DMA Handle was invalid -*/ -/****************************************************************************/ - -static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle) -{ - int controllerIdx; - int channelIdx; - - controllerIdx = CONTROLLER_FROM_HANDLE(handle); - channelIdx = CHANNEL_FROM_HANDLE(handle); - - if ((controllerIdx > DMA_NUM_CONTROLLERS) - || (channelIdx > DMA_NUM_CHANNELS)) { - return NULL; - } - return &gDMA.controller[controllerIdx].channel[channelIdx]; -} - -/****************************************************************************/ -/** -* Interrupt handler which is called to process DMA interrupts. -*/ -/****************************************************************************/ - -static irqreturn_t dma_interrupt_handler(int irq, void *dev_id) -{ - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - int irqStatus; - - channel = (DMA_Channel_t *) dev_id; - - /* Figure out why we were called, and knock down the interrupt */ - - irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle); - dmacHw_clearInterrupt(channel->dmacHwHandle); - - if ((channel->devType < 0) - || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) { - printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n", - channel->devType); - return IRQ_NONE; - } - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - /* Update stats */ - - if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) { - devAttr->transferTicks += - (timer_get_tick_count() - devAttr->transferStartTime); - } - - if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) { - printk(KERN_ERR - "dma_interrupt_handler: devType :%d DMA error (%s)\n", - channel->devType, devAttr->name); - } else { - devAttr->numTransfers++; - devAttr->transferBytes += devAttr->numBytes; - } - - /* Call any installed handler */ - - if (devAttr->devHandler != NULL) { - devAttr->devHandler(channel->devType, irqStatus, - devAttr->userData); - } - - return IRQ_HANDLED; -} - -/****************************************************************************/ -/** -* Allocates memory to hold a descriptor ring. The descriptor ring then -* needs to be populated by making one or more calls to -* dna_add_descriptors. -* -* The returned descriptor ring will be automatically initialized. -* -* @return -* 0 Descriptor ring was allocated successfully -* -EINVAL Invalid parameters passed in -* -ENOMEM Unable to allocate memory for the desired number of descriptors. -*/ -/****************************************************************************/ - -int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */ - int numDescriptors /* Number of descriptors that need to be allocated. */ - ) { - size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors); - - if ((ring == NULL) || (numDescriptors <= 0)) { - return -EINVAL; - } - - ring->physAddr = 0; - ring->descriptorsAllocated = 0; - ring->bytesAllocated = 0; - - ring->virtAddr = dma_alloc_writecombine(NULL, - bytesToAlloc, - &ring->physAddr, - GFP_KERNEL); - if (ring->virtAddr == NULL) { - return -ENOMEM; - } - - ring->bytesAllocated = bytesToAlloc; - ring->descriptorsAllocated = numDescriptors; - - return dma_init_descriptor_ring(ring, numDescriptors); -} - -EXPORT_SYMBOL(dma_alloc_descriptor_ring); - -/****************************************************************************/ -/** -* Releases the memory which was previously allocated for a descriptor ring. -*/ -/****************************************************************************/ - -void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */ - ) { - if (ring->virtAddr != NULL) { - dma_free_writecombine(NULL, - ring->bytesAllocated, - ring->virtAddr, ring->physAddr); - } - - ring->bytesAllocated = 0; - ring->descriptorsAllocated = 0; - ring->virtAddr = NULL; - ring->physAddr = 0; -} - -EXPORT_SYMBOL(dma_free_descriptor_ring); - -/****************************************************************************/ -/** -* Initializes a descriptor ring, so that descriptors can be added to it. -* Once a descriptor ring has been allocated, it may be reinitialized for -* use with additional/different regions of memory. -* -* Note that if 7 descriptors are allocated, it's perfectly acceptable to -* initialize the ring with a smaller number of descriptors. The amount -* of memory allocated for the descriptor ring will not be reduced, and -* the descriptor ring may be reinitialized later -* -* @return -* 0 Descriptor ring was initialized successfully -* -ENOMEM The descriptor which was passed in has insufficient space -* to hold the desired number of descriptors. -*/ -/****************************************************************************/ - -int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */ - int numDescriptors /* Number of descriptors to initialize. */ - ) { - if (ring->virtAddr == NULL) { - return -EINVAL; - } - if (dmacHw_initDescriptor(ring->virtAddr, - ring->physAddr, - ring->bytesAllocated, numDescriptors) < 0) { - printk(KERN_ERR - "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n"); - return -ENOMEM; - } - - return 0; -} - -EXPORT_SYMBOL(dma_init_descriptor_ring); - -/****************************************************************************/ -/** -* Determines the number of descriptors which would be required for a -* transfer of the indicated memory region. -* -* This function also needs to know which DMA device this transfer will -* be destined for, so that the appropriate DMA configuration can be retrieved. -* DMA parameters such as transfer width, and whether this is a memory-to-memory -* or memory-to-peripheral, etc can all affect the actual number of descriptors -* required. -* -* @return -* > 0 Returns the number of descriptors required for the indicated transfer -* -ENODEV - Device handed in is invalid. -* -EINVAL Invalid parameters -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ) { - int numDescriptors; - DMA_DeviceAttribute_t *devAttr; - - if (!IsDeviceValid(device)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[device]; - - numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config, - (void *)srcData, - (void *)dstData, - numBytes); - if (numDescriptors < 0) { - printk(KERN_ERR - "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n"); - return -EINVAL; - } - - return numDescriptors; -} - -EXPORT_SYMBOL(dma_calculate_descriptor_count); - -/****************************************************************************/ -/** -* Adds a region of memory to the descriptor ring. Note that it may take -* multiple descriptors for each region of memory. It is the callers -* responsibility to allocate a sufficiently large descriptor ring. -* -* @return -* 0 Descriptors were added successfully -* -ENODEV Device handed in is invalid. -* -EINVAL Invalid parameters -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */ - DMA_Device_t device, /* DMA Device that descriptors are for */ - dma_addr_t srcData, /* Place to get data (memory or device) */ - dma_addr_t dstData, /* Place to put data (memory or device) */ - size_t numBytes /* Number of bytes to transfer to the device */ - ) { - int rc; - DMA_DeviceAttribute_t *devAttr; - - if (!IsDeviceValid(device)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[device]; - - rc = dmacHw_setDataDescriptor(&devAttr->config, - ring->virtAddr, - (void *)srcData, - (void *)dstData, numBytes); - if (rc < 0) { - printk(KERN_ERR - "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n", - rc); - return -ENOMEM; - } - - return 0; -} - -EXPORT_SYMBOL(dma_add_descriptors); - -/****************************************************************************/ -/** -* Sets the descriptor ring associated with a device. -* -* Once set, the descriptor ring will be associated with the device, even -* across channel request/free calls. Passing in a NULL descriptor ring -* will release any descriptor ring currently associated with the device. -* -* Note: If you call dma_transfer, or one of the other dma_alloc_ functions -* the descriptor ring may be released and reallocated. -* -* Note: This function will release the descriptor memory for any current -* descriptor ring associated with this device. -* -* @return -* 0 Descriptors were added successfully -* -ENODEV Device handed in is invalid. -*/ -/****************************************************************************/ - -int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */ - DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */ - ) { - DMA_DeviceAttribute_t *devAttr; - - if (!IsDeviceValid(device)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[device]; - - /* Free the previously allocated descriptor ring */ - - dma_free_descriptor_ring(&devAttr->ring); - - if (ring != NULL) { - /* Copy in the new one */ - - devAttr->ring = *ring; - } - - /* Set things up so that if dma_transfer is called then this descriptor */ - /* ring will get freed. */ - - devAttr->prevSrcData = 0; - devAttr->prevDstData = 0; - devAttr->prevNumBytes = 0; - - return 0; -} - -EXPORT_SYMBOL(dma_set_device_descriptor_ring); - -/****************************************************************************/ -/** -* Retrieves the descriptor ring associated with a device. -* -* @return -* 0 Descriptors were added successfully -* -ENODEV Device handed in is invalid. -*/ -/****************************************************************************/ - -int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */ - DMA_DescriptorRing_t *ring /* Place to store retrieved ring */ - ) { - DMA_DeviceAttribute_t *devAttr; - - memset(ring, 0, sizeof(*ring)); - - if (!IsDeviceValid(device)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[device]; - - *ring = devAttr->ring; - - return 0; -} - -EXPORT_SYMBOL(dma_get_device_descriptor_ring); - -/****************************************************************************/ -/** -* Configures a DMA channel. -* -* @return -* >= 0 - Initialization was successful. -* -* -EBUSY - Device is currently being used. -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -static int ConfigChannel(DMA_Handle_t handle) -{ - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - int controllerIdx; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[channel->devType]; - controllerIdx = CONTROLLER_FROM_HANDLE(handle); - - if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) { - if (devAttr->config.transferType == - dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) { - devAttr->config.dstPeripheralPort = - devAttr->dmacPort[controllerIdx]; - } else if (devAttr->config.transferType == - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) { - devAttr->config.srcPeripheralPort = - devAttr->dmacPort[controllerIdx]; - } - } - - if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) { - printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n"); - return -EIO; - } - - return 0; -} - -/****************************************************************************/ -/** -* Initializes all of the data structures associated with the DMA. -* @return -* >= 0 - Initialization was successful. -* -* -EBUSY - Device is currently being used. -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -int dma_init(void) -{ - int rc = 0; - int controllerIdx; - int channelIdx; - DMA_Device_t devIdx; - DMA_Channel_t *channel; - DMA_Handle_t dedicatedHandle; - - memset(&gDMA, 0, sizeof(gDMA)); - - sema_init(&gDMA.lock, 0); - init_waitqueue_head(&gDMA.freeChannelQ); - - /* Initialize the Hardware */ - - dmacHw_initDma(); - - /* Start off by marking all of the DMA channels as shared. */ - - for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; - controllerIdx++) { - for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; - channelIdx++) { - channel = - &gDMA.controller[controllerIdx].channel[channelIdx]; - - channel->flags = 0; - channel->devType = DMA_DEVICE_NONE; - channel->lastDevType = DMA_DEVICE_NONE; - -#if (DMA_DEBUG_TRACK_RESERVATION) - channel->fileName = ""; - channel->lineNum = 0; -#endif - - channel->dmacHwHandle = - dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID - (controllerIdx, - channelIdx)); - dmacHw_initChannel(channel->dmacHwHandle); - } - } - - /* Record any special attributes that channels may have */ - - gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; - gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; - gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; - gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; - - /* Now walk through and record the dedicated channels. */ - - for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) { - DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx]; - - if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) - && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) { - printk(KERN_ERR - "DMA Device: %s Can only request NO_ISR for dedicated devices\n", - devAttr->name); - rc = -EINVAL; - goto out; - } - - if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { - /* This is a dedicated device. Mark the channel as being reserved. */ - - if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) { - printk(KERN_ERR - "DMA Device: %s DMA Controller %d is out of range\n", - devAttr->name, - devAttr->dedicatedController); - rc = -EINVAL; - goto out; - } - - if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) { - printk(KERN_ERR - "DMA Device: %s DMA Channel %d is out of range\n", - devAttr->name, - devAttr->dedicatedChannel); - rc = -EINVAL; - goto out; - } - - dedicatedHandle = - MAKE_HANDLE(devAttr->dedicatedController, - devAttr->dedicatedChannel); - channel = HandleToChannel(dedicatedHandle); - - if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) != - 0) { - printk - ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n", - devAttr->name, - devAttr->dedicatedController, - devAttr->dedicatedChannel, - DMA_gDeviceAttribute[channel->devType]. - name); - rc = -EBUSY; - goto out; - } - - channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED; - channel->devType = devIdx; - - if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) { - channel->flags |= DMA_CHANNEL_FLAG_NO_ISR; - } - - /* For dedicated channels, we can go ahead and configure the DMA channel now */ - /* as well. */ - - ConfigChannel(dedicatedHandle); - } - } - - /* Go through and register the interrupt handlers */ - - for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; - controllerIdx++) { - for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; - channelIdx++) { - channel = - &gDMA.controller[controllerIdx].channel[channelIdx]; - - if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) { - snprintf(channel->name, sizeof(channel->name), - "dma %d:%d %s", controllerIdx, - channelIdx, - channel->devType == - DMA_DEVICE_NONE ? "" : - DMA_gDeviceAttribute[channel->devType]. - name); - - rc = - request_irq(IRQ_DMA0C0 + - (controllerIdx * - DMA_NUM_CHANNELS) + - channelIdx, - dma_interrupt_handler, - IRQF_DISABLED, channel->name, - channel); - if (rc != 0) { - printk(KERN_ERR - "request_irq for IRQ_DMA%dC%d failed\n", - controllerIdx, channelIdx); - } - } - } - } - - /* Create /proc/dma/channels and /proc/dma/devices */ - - gDmaDir = proc_mkdir("dma", NULL); - - if (gDmaDir == NULL) { - printk(KERN_ERR "Unable to create /proc/dma\n"); - } else { - create_proc_read_entry("channels", 0, gDmaDir, - dma_proc_read_channels, NULL); - create_proc_read_entry("devices", 0, gDmaDir, - dma_proc_read_devices, NULL); - } - -out: - - up(&gDMA.lock); - - return rc; -} - -/****************************************************************************/ -/** -* Reserves a channel for use with @a dev. If the device is setup to use -* a shared channel, then this function will block until a free channel -* becomes available. -* -* @return -* >= 0 - A valid DMA Handle. -* -EBUSY - Device is currently being used. -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -#if (DMA_DEBUG_TRACK_RESERVATION) -DMA_Handle_t dma_request_channel_dbg - (DMA_Device_t dev, const char *fileName, int lineNum) -#else -DMA_Handle_t dma_request_channel(DMA_Device_t dev) -#endif -{ - DMA_Handle_t handle; - DMA_DeviceAttribute_t *devAttr; - DMA_Channel_t *channel; - int controllerIdx; - int controllerIdx2; - int channelIdx; - - if (down_interruptible(&gDMA.lock) < 0) { - return -ERESTARTSYS; - } - - if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) { - handle = -ENODEV; - goto out; - } - devAttr = &DMA_gDeviceAttribute[dev]; - -#if (DMA_DEBUG_TRACK_RESERVATION) - { - char *s; - - s = strrchr(fileName, '/'); - if (s != NULL) { - fileName = s + 1; - } - } -#endif - if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) { - /* This device has already been requested and not been freed */ - - printk(KERN_ERR "%s: device %s is already requested\n", - __func__, devAttr->name); - handle = -EBUSY; - goto out; - } - - if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { - /* This device has a dedicated channel. */ - - channel = - &gDMA.controller[devAttr->dedicatedController]. - channel[devAttr->dedicatedChannel]; - if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) { - handle = -EBUSY; - goto out; - } - - channel->flags |= DMA_CHANNEL_FLAG_IN_USE; - devAttr->flags |= DMA_DEVICE_FLAG_IN_USE; - -#if (DMA_DEBUG_TRACK_RESERVATION) - channel->fileName = fileName; - channel->lineNum = lineNum; -#endif - handle = - MAKE_HANDLE(devAttr->dedicatedController, - devAttr->dedicatedChannel); - goto out; - } - - /* This device needs to use one of the shared channels. */ - - handle = DMA_INVALID_HANDLE; - while (handle == DMA_INVALID_HANDLE) { - /* Scan through the shared channels and see if one is available */ - - for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS; - controllerIdx2++) { - /* Check to see if we should try on controller 1 first. */ - - controllerIdx = controllerIdx2; - if ((devAttr-> - flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) { - controllerIdx = 1 - controllerIdx; - } - - /* See if the device is available on the controller being tested */ - - if ((devAttr-> - flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx)) - != 0) { - for (channelIdx = 0; - channelIdx < DMA_NUM_CHANNELS; - channelIdx++) { - channel = - &gDMA.controller[controllerIdx]. - channel[channelIdx]; - - if (((channel-> - flags & - DMA_CHANNEL_FLAG_IS_DEDICATED) == - 0) - && - ((channel-> - flags & DMA_CHANNEL_FLAG_IN_USE) - == 0)) { - if (((channel-> - flags & - DMA_CHANNEL_FLAG_LARGE_FIFO) - != 0) - && - ((devAttr-> - flags & - DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) - == 0)) { - /* This channel is a large fifo - don't tie it up */ - /* with devices that we don't want using it. */ - - continue; - } - - channel->flags |= - DMA_CHANNEL_FLAG_IN_USE; - channel->devType = dev; - devAttr->flags |= - DMA_DEVICE_FLAG_IN_USE; - -#if (DMA_DEBUG_TRACK_RESERVATION) - channel->fileName = fileName; - channel->lineNum = lineNum; -#endif - handle = - MAKE_HANDLE(controllerIdx, - channelIdx); - - /* Now that we've reserved the channel - we can go ahead and configure it */ - - if (ConfigChannel(handle) != 0) { - handle = -EIO; - printk(KERN_ERR - "dma_request_channel: ConfigChannel failed\n"); - } - goto out; - } - } - } - } - - /* No channels are currently available. Let's wait for one to free up. */ - - { - DEFINE_WAIT(wait); - - prepare_to_wait(&gDMA.freeChannelQ, &wait, - TASK_INTERRUPTIBLE); - up(&gDMA.lock); - schedule(); - finish_wait(&gDMA.freeChannelQ, &wait); - - if (signal_pending(current)) { - /* We don't currently hold gDMA.lock, so we return directly */ - - return -ERESTARTSYS; - } - } - - if (down_interruptible(&gDMA.lock)) { - return -ERESTARTSYS; - } - } - -out: - up(&gDMA.lock); - - return handle; -} - -/* Create both _dbg and non _dbg functions for modules. */ - -#if (DMA_DEBUG_TRACK_RESERVATION) -#undef dma_request_channel -DMA_Handle_t dma_request_channel(DMA_Device_t dev) -{ - return dma_request_channel_dbg(dev, __FILE__, __LINE__); -} - -EXPORT_SYMBOL(dma_request_channel_dbg); -#endif -EXPORT_SYMBOL(dma_request_channel); - -/****************************************************************************/ -/** -* Frees a previously allocated DMA Handle. -*/ -/****************************************************************************/ - -int dma_free_channel(DMA_Handle_t handle /* DMA handle. */ - ) { - int rc = 0; - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - - if (down_interruptible(&gDMA.lock) < 0) { - return -ERESTARTSYS; - } - - channel = HandleToChannel(handle); - if (channel == NULL) { - rc = -EINVAL; - goto out; - } - - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) { - channel->lastDevType = channel->devType; - channel->devType = DMA_DEVICE_NONE; - } - channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE; - devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE; - -out: - up(&gDMA.lock); - - wake_up_interruptible(&gDMA.freeChannelQ); - - return rc; -} - -EXPORT_SYMBOL(dma_free_channel); - -/****************************************************************************/ -/** -* Determines if a given device has been configured as using a shared -* channel. -* -* @return -* 0 Device uses a dedicated channel -* > zero Device uses a shared channel -* < zero Error code -*/ -/****************************************************************************/ - -int dma_device_is_channel_shared(DMA_Device_t device /* Device to check. */ - ) { - DMA_DeviceAttribute_t *devAttr; - - if (!IsDeviceValid(device)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[device]; - - return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0); -} - -EXPORT_SYMBOL(dma_device_is_channel_shared); - -/****************************************************************************/ -/** -* Allocates buffers for the descriptors. This is normally done automatically -* but needs to be done explicitly when initiating a dma from interrupt -* context. -* -* @return -* 0 Descriptors were allocated successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */ - dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ) { - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - int numDescriptors; - size_t ringBytesRequired; - int rc = 0; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - if (devAttr->config.transferType != transferType) { - return -EINVAL; - } - - /* Figure out how many descriptors we need. */ - - /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */ - /* srcData, dstData, numBytes); */ - - numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config, - (void *)srcData, - (void *)dstData, - numBytes); - if (numDescriptors < 0) { - printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n", - __func__); - return -EINVAL; - } - - /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */ - /* a new one. */ - - ringBytesRequired = dmacHw_descriptorLen(numDescriptors); - - /* printk("ringBytesRequired: %d\n", ringBytesRequired); */ - - if (ringBytesRequired > devAttr->ring.bytesAllocated) { - /* Make sure that this code path is never taken from interrupt context. */ - /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */ - /* allocation needs to have already been done. */ - - might_sleep(); - - /* Free the old descriptor ring and allocate a new one. */ - - dma_free_descriptor_ring(&devAttr->ring); - - /* And allocate a new one. */ - - rc = - dma_alloc_descriptor_ring(&devAttr->ring, - numDescriptors); - if (rc < 0) { - printk(KERN_ERR - "%s: dma_alloc_descriptor_ring(%d) failed\n", - __func__, numDescriptors); - return rc; - } - /* Setup the descriptor for this transfer */ - - if (dmacHw_initDescriptor(devAttr->ring.virtAddr, - devAttr->ring.physAddr, - devAttr->ring.bytesAllocated, - numDescriptors) < 0) { - printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", - __func__); - return -EINVAL; - } - } else { - /* We've already got enough ring buffer allocated. All we need to do is reset */ - /* any control information, just in case the previous DMA was stopped. */ - - dmacHw_resetDescriptorControl(devAttr->ring.virtAddr); - } - - /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */ - /* as last time, then we don't need to call setDataDescriptor again. */ - - if (dmacHw_setDataDescriptor(&devAttr->config, - devAttr->ring.virtAddr, - (void *)srcData, - (void *)dstData, numBytes) < 0) { - printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n", - __func__); - return -EINVAL; - } - - /* Remember the critical information for this transfer so that we can eliminate */ - /* another call to dma_alloc_descriptors if the caller reuses the same buffers */ - - devAttr->prevSrcData = srcData; - devAttr->prevDstData = dstData; - devAttr->prevNumBytes = numBytes; - - return 0; -} - -EXPORT_SYMBOL(dma_alloc_descriptors); - -/****************************************************************************/ -/** -* Allocates and sets up descriptors for a double buffered circular buffer. -* -* This is primarily intended to be used for things like the ingress samples -* from a microphone. -* -* @return -* > 0 Number of descriptors actually allocated. -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ - dma_addr_t srcData, /* Physical address of source data */ - dma_addr_t dstData1, /* Physical address of first destination buffer */ - dma_addr_t dstData2, /* Physical address of second destination buffer */ - size_t numBytes /* Number of bytes in each destination buffer */ - ) { - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - int numDst1Descriptors; - int numDst2Descriptors; - int numDescriptors; - size_t ringBytesRequired; - int rc = 0; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - /* Figure out how many descriptors we need. */ - - /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */ - /* srcData, dstData, numBytes); */ - - numDst1Descriptors = - dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData, - (void *)dstData1, numBytes); - if (numDst1Descriptors < 0) { - return -EINVAL; - } - numDst2Descriptors = - dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData, - (void *)dstData2, numBytes); - if (numDst2Descriptors < 0) { - return -EINVAL; - } - numDescriptors = numDst1Descriptors + numDst2Descriptors; - /* printk("numDescriptors: %d\n", numDescriptors); */ - - /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */ - /* a new one. */ - - ringBytesRequired = dmacHw_descriptorLen(numDescriptors); - - /* printk("ringBytesRequired: %d\n", ringBytesRequired); */ - - if (ringBytesRequired > devAttr->ring.bytesAllocated) { - /* Make sure that this code path is never taken from interrupt context. */ - /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */ - /* allocation needs to have already been done. */ - - might_sleep(); - - /* Free the old descriptor ring and allocate a new one. */ - - dma_free_descriptor_ring(&devAttr->ring); - - /* And allocate a new one. */ - - rc = - dma_alloc_descriptor_ring(&devAttr->ring, - numDescriptors); - if (rc < 0) { - printk(KERN_ERR - "%s: dma_alloc_descriptor_ring(%d) failed\n", - __func__, ringBytesRequired); - return rc; - } - } - - /* Setup the descriptor for this transfer. Since this function is used with */ - /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */ - /* setDataDescriptor will keep trying to append onto the end. */ - - if (dmacHw_initDescriptor(devAttr->ring.virtAddr, - devAttr->ring.physAddr, - devAttr->ring.bytesAllocated, - numDescriptors) < 0) { - printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__); - return -EINVAL; - } - - /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */ - /* as last time, then we don't need to call setDataDescriptor again. */ - - if (dmacHw_setDataDescriptor(&devAttr->config, - devAttr->ring.virtAddr, - (void *)srcData, - (void *)dstData1, numBytes) < 0) { - printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n", - __func__); - return -EINVAL; - } - if (dmacHw_setDataDescriptor(&devAttr->config, - devAttr->ring.virtAddr, - (void *)srcData, - (void *)dstData2, numBytes) < 0) { - printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n", - __func__); - return -EINVAL; - } - - /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */ - /* try to make the 'prev' variables right. */ - - devAttr->prevSrcData = 0; - devAttr->prevDstData = 0; - devAttr->prevNumBytes = 0; - - return numDescriptors; -} - -EXPORT_SYMBOL(dma_alloc_double_dst_descriptors); - -/****************************************************************************/ -/** -* Initiates a transfer when the descriptors have already been setup. -* -* This is a special case, and normally, the dma_transfer_xxx functions should -* be used. -* -* @return -* 0 Transfer was started successfully -* -ENODEV Invalid handle -*/ -/****************************************************************************/ - -int dma_start_transfer(DMA_Handle_t handle) -{ - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config, - devAttr->ring.virtAddr); - - /* Since we got this far, everything went successfully */ - - return 0; -} - -EXPORT_SYMBOL(dma_start_transfer); - -/****************************************************************************/ -/** -* Stops a previously started DMA transfer. -* -* @return -* 0 Transfer was stopped successfully -* -ENODEV Invalid handle -*/ -/****************************************************************************/ - -int dma_stop_transfer(DMA_Handle_t handle) -{ - DMA_Channel_t *channel; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - - dmacHw_stopTransfer(channel->dmacHwHandle); - - return 0; -} - -EXPORT_SYMBOL(dma_stop_transfer); - -/****************************************************************************/ -/** -* Waits for a DMA to complete by polling. This function is only intended -* to be used for testing. Interrupts should be used for most DMA operations. -*/ -/****************************************************************************/ - -int dma_wait_transfer_done(DMA_Handle_t handle) -{ - DMA_Channel_t *channel; - dmacHw_TRANSFER_STATUS_e status; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - - while ((status = - dmacHw_transferCompleted(channel->dmacHwHandle)) == - dmacHw_TRANSFER_STATUS_BUSY) { - ; - } - - if (status == dmacHw_TRANSFER_STATUS_ERROR) { - printk(KERN_ERR "%s: DMA transfer failed\n", __func__); - return -EIO; - } - return 0; -} - -EXPORT_SYMBOL(dma_wait_transfer_done); - -/****************************************************************************/ -/** -* Initiates a DMA, allocating the descriptors as required. -* -* @return -* 0 Transfer was started successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV) -*/ -/****************************************************************************/ - -int dma_transfer(DMA_Handle_t handle, /* DMA Handle */ - dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ) { - DMA_Channel_t *channel; - DMA_DeviceAttribute_t *devAttr; - int rc = 0; - - channel = HandleToChannel(handle); - if (channel == NULL) { - return -ENODEV; - } - - devAttr = &DMA_gDeviceAttribute[channel->devType]; - - if (devAttr->config.transferType != transferType) { - return -EINVAL; - } - - /* We keep track of the information about the previous request for this */ - /* device, and if the attributes match, then we can use the descriptors we setup */ - /* the last time, and not have to reinitialize everything. */ - - { - rc = - dma_alloc_descriptors(handle, transferType, srcData, - dstData, numBytes); - if (rc != 0) { - return rc; - } - } - - /* And kick off the transfer */ - - devAttr->numBytes = numBytes; - devAttr->transferStartTime = timer_get_tick_count(); - - dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config, - devAttr->ring.virtAddr); - - /* Since we got this far, everything went successfully */ - - return 0; -} - -EXPORT_SYMBOL(dma_transfer); - -/****************************************************************************/ -/** -* Set the callback function which will be called when a transfer completes. -* If a NULL callback function is set, then no callback will occur. -* -* @note @a devHandler will be called from IRQ context. -* -* @return -* 0 - Success -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */ - DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */ - void *userData /* Pointer which will be passed to devHandler. */ - ) { - DMA_DeviceAttribute_t *devAttr; - unsigned long flags; - - if (!IsDeviceValid(dev)) { - return -ENODEV; - } - devAttr = &DMA_gDeviceAttribute[dev]; - - local_irq_save(flags); - - devAttr->userData = userData; - devAttr->devHandler = devHandler; - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(dma_set_device_handler); diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c deleted file mode 100644 index ca0ad736870b..000000000000 --- a/arch/arm/mach-bcmring/dma_device.c +++ /dev/null @@ -1,593 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dma_device.c -* -* @brief private array of DMA_DeviceAttribute_t -*/ -/****************************************************************************/ - -DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = { - [DMA_DEVICE_MEM_TO_MEM] = /* MEM 2 MEM */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "mem-to-mem", - .config = { - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - - }, - }, - [DMA_DEVICE_VPM_MEM_TO_MEM] = /* VPM */ - { - .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR, - .name = "vpm", - .dedicatedController = 0, - .dedicatedChannel = 0, - /* reserve DMA0:0 for VPM */ - }, - [DMA_DEVICE_NAND_MEM_TO_MEM] = /* NAND */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "nand", - .config = { - .srcPeripheralPort = 0, - .dstPeripheralPort = 0, - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_6, - }, - }, - [DMA_DEVICE_PIF_MEM_TO_DEV] = /* PIF TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1 - | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO - | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC, - .name = "pif_tx", - .dmacPort = {14, 5}, - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - /* dstPeripheralPort = 5 or 14 */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - .maxDataPerBlock = 16256, - }, - }, - [DMA_DEVICE_PIF_DEV_TO_MEM] = /* PIF RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1 - | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO - /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */ - | DMA_DEVICE_FLAG_PORT_PER_DMAC, - .name = "pif_rx", - .dmacPort = {14, 5}, - .config = { - /* srcPeripheralPort = 5 or 14 */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - .maxDataPerBlock = 16256, - }, - }, - [DMA_DEVICE_I2S0_DEV_TO_MEM] = /* I2S RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "i2s0_rx", - .config = { - .srcPeripheralPort = 0, /* SRC: I2S0 */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_I2S0_MEM_TO_DEV] = /* I2S TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "i2s0_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 1, /* DST: I2S0 */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_I2S1_DEV_TO_MEM] = /* I2S1 RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA1, - .name = "i2s1_rx", - .config = { - .srcPeripheralPort = 2, /* SRC: I2S1 */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_I2S1_MEM_TO_DEV] = /* I2S1 TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA1, - .name = "i2s1_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 3, /* DST: I2S1 */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_ESW_MEM_TO_DEV] = /* ESW TX */ - { - .name = "esw_tx", - .flags = DMA_DEVICE_FLAG_IS_DEDICATED, - .dedicatedController = 1, - .dedicatedChannel = 3, - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 1, /* DST: ESW (MTP) */ - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_DISABLE, - /* DMAx_AHB_SSTATARy */ - .srcStatusRegisterAddress = 0x00000000, - /* DMAx_AHB_DSTATARy */ - .dstStatusRegisterAddress = 0x30490010, - /* DMAx_AHB_CFGy */ - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - /* DMAx_AHB_CTLy */ - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - }, - }, - [DMA_DEVICE_ESW_DEV_TO_MEM] = /* ESW RX */ - { - .name = "esw_rx", - .flags = DMA_DEVICE_FLAG_IS_DEDICATED, - .dedicatedController = 1, - .dedicatedChannel = 2, - .config = { - .srcPeripheralPort = 0, /* SRC: ESW (PTM) */ - .dstPeripheralPort = 0, /* DST: memory */ - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_DISABLE, - /* DMAx_AHB_SSTATARy */ - .srcStatusRegisterAddress = 0x30480010, - /* DMAx_AHB_DSTATARy */ - .dstStatusRegisterAddress = 0x00000000, - /* DMAx_AHB_CFGy */ - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - /* DMAx_AHB_CTLy */ - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - }, - }, - [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] = /* APM Codec A Ingress */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "apm_a_rx", - .config = { - .srcPeripheralPort = 2, /* SRC: Codec A Ingress FIFO */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] = /* APM Codec A Egress */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "apm_a_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 3, /* DST: Codec A Egress FIFO */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] = /* APM Codec B Ingress */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "apm_b_rx", - .config = { - .srcPeripheralPort = 4, /* SRC: Codec B Ingress FIFO */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] = /* APM Codec B Egress */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "apm_b_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 5, /* DST: Codec B Egress FIFO */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] = /* APM Codec C Ingress */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA1, - .name = "apm_c_rx", - .config = { - .srcPeripheralPort = 4, /* SRC: Codec C Ingress FIFO */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] = /* PCM0 RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "pcm0_rx", - .config = { - .srcPeripheralPort = 12, /* SRC: PCM0 */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] = /* PCM0 TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0, - .name = "pcm0_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 13, /* DST: PCM0 */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] = /* PCM1 RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA1, - .name = "pcm1_rx", - .config = { - .srcPeripheralPort = 14, /* SRC: PCM1 */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, - .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, - }, - }, - [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] = /* PCM1 TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA1, - .name = "pcm1_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 15, /* DST: PCM1 */ - .srcStatusRegisterAddress = 0, - .dstStatusRegisterAddress = 0, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_SPUM_DEV_TO_MEM] = /* SPUM RX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "spum_rx", - .config = { - .srcPeripheralPort = 6, /* SRC: Codec A Ingress FIFO */ - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - /* Busrt size **MUST** be 16 for SPUM to work */ - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - /* on the RX side, SPU needs to be the flow controller */ - .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL, - }, - }, - [DMA_DEVICE_SPUM_MEM_TO_DEV] = /* SPUM TX */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "spum_tx", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .dstPeripheralPort = 7, /* DST: SPUM */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, - /* Busrt size **MUST** be 16 for SPUM to work */ - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16, - .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, - }, - }, - [DMA_DEVICE_MEM_TO_VRAM] = /* MEM 2 VRAM */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "mem-to-vram", - .config = { - .srcPeripheralPort = 0, /* SRC: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - }, - }, - [DMA_DEVICE_VRAM_TO_MEM] = /* VRAM 2 MEM */ - { - .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, - .name = "vram-to-mem", - .config = { - .dstPeripheralPort = 0, /* DST: memory */ - .srcStatusRegisterAddress = 0x00000000, - .dstStatusRegisterAddress = 0x00000000, - .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, - .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, - .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, - .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, - .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, - .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, - .errorInterrupt = dmacHw_INTERRUPT_ENABLE, - .channelPriority = dmacHw_CHANNEL_PRIORITY_7, - .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, - .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, - .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, - .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, - }, - }, -}; -EXPORT_SYMBOL(DMA_gDeviceAttribute); /* primarily for dma-test.c */ diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h deleted file mode 100644 index f01da877148e..000000000000 --- a/arch/arm/mach-bcmring/include/cfg_global.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#include <cfg_global_defines.h> - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h deleted file mode 100644 index b5beb0b30734..000000000000 --- a/arch/arm/mach-bcmring/include/cfg_global_defines.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CFG_GLOBAL_DEFINES_H -#define CFG_GLOBAL_DEFINES_H - -/* CHIP */ -#define BCM1103 1 - -#define BCM1191 4 -#define BCM2153 5 -#define BCM2820 6 - -#define BCM2826 8 -#define FPGA11107 9 -#define BCM11107 10 -#define BCM11109 11 -#define BCM11170 12 -#define BCM11110 13 -#define BCM11211 14 - -/* CFG_GLOBAL_CHIP_FAMILY types */ -#define CFG_GLOBAL_CHIP_FAMILY_NONE 0 -#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2 -#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4 -#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8 - -#define IMAGE_HEADER_SIZE_CHECKSUM 4 -#endif diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h deleted file mode 100644 index caa20e59db99..000000000000 --- a/arch/arm/mach-bcmring/include/csp/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_CACHE_H -#define CSP_CACHE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/stdint.h> - -/* ---- Public Constants and Types --------------------------------------- */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include <asm/cacheflush.h> - -#define CSP_CACHE_FLUSH_ALL flush_cache_all() - -#else - -#define CSP_CACHE_FLUSH_ALL - -#endif - -#endif /* CSP_CACHE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h deleted file mode 100644 index 8b3d80367293..000000000000 --- a/arch/arm/mach-bcmring/include/csp/delay.h +++ /dev/null @@ -1,36 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_DELAY_H -#define CSP_DELAY_H - -/* ---- Include Files ---------------------------------------------------- */ - -/* Some CSP routines require use of the following delay routines. Use the OS */ -/* version if available, otherwise use a CSP specific definition. */ -/* void udelay(unsigned long usecs); */ -/* void mdelay(unsigned long msecs); */ - -#if defined(__KERNEL__) && !defined(STANDALONE) - #include <linux/delay.h> -#else - #include <mach/csp/delay.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_DELAY_H */ diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h deleted file mode 100644 index e6a1dc484ca7..000000000000 --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ /dev/null @@ -1,596 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw.h -* -* @brief API definitions for low level DMA controller driver -* -*/ -/****************************************************************************/ -#ifndef _DMACHW_H -#define _DMACHW_H - -#include <stddef.h> - -#include <csp/stdint.h> -#include <mach/csp/dmacHw_reg.h> - -/* Define DMA Channel ID using DMA controller number (m) and channel number (c). - - System specific channel ID should be defined as follows - - For example: - - #include <dmacHw.h> - ... - #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5) - #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0) - #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1) - #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3) - #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4) - ... - #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4) - #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5) - #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6) - ... -*/ -#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c) - -typedef enum { - dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */ - dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */ - dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */ - dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */ - dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */ - dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */ - dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */ - dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */ -} dmacHw_CHANNEL_PRIORITY_e; - -/* Source destination master interface */ -typedef enum { - dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */ - dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */ - dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */ - dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */ -} dmacHw_MASTER_INTERFACE_e; - -typedef enum { - dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */ - dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */ - dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */ -} dmacHw_TRANSACTION_WIDTH_e; - -typedef enum { - dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */ - dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */ - dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ - dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ -} dmacHw_BURST_WIDTH_e; - -typedef enum { - dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */ - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */ - dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */ - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */ -} dmacHw_TRANSFER_TYPE_e; - -typedef enum { - dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */ - dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */ - dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */ -} dmacHw_TRANSFER_MODE_e; - -typedef enum { - dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */ - dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */ - dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */ - dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */ -} dmacHw_ADDRESS_UPDATE_MODE_e; - -typedef enum { - dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */ - dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */ -} dmacHw_FLOW_CONTROL_e; - -typedef enum { - dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */ - dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */ - dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */ -} dmacHw_TRANSFER_STATUS_e; - -typedef enum { - dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */ - dmacHw_INTERRUPT_ENABLE /* Interrupt enable */ -} dmacHw_INTERRUPT_e; - -typedef enum { - dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */ - dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */ - dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */ - dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */ -} dmacHw_INTERRUPT_STATUS_e; - -typedef enum { - dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */ - dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */ - dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */ -} dmacHw_CONTROLLER_ATTRIB_e; - -typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */ -typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using - "dmacHw_MAKE_CHANNEL_ID" macro - */ -/* DMA channel configuration parameters */ -typedef struct { - uint32_t srcPeripheralPort; /* Source peripheral port */ - uint32_t dstPeripheralPort; /* Destination peripheral port */ - uint32_t srcStatusRegisterAddress; /* Source status register address */ - uint32_t dstStatusRegisterAddress; /* Destination status register address of type */ - - uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */ - uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */ - uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */ - uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */ - uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor. - 0 = Maximum possible. - */ - - dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */ - dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */ - dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */ - dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */ - dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */ - dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */ - dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */ - dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */ - dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */ - dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */ - dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */ - dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */ - dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */ - dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */ - dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */ -} dmacHw_CONFIG_t; - -/****************************************************************************/ -/** -* @brief Initializes DMA -* -* This function initializes DMA CSP driver -* -* @note -* Must be called before using any DMA channel -*/ -/****************************************************************************/ -void dmacHw_initDma(void); - -/****************************************************************************/ -/** -* @brief Exit function for DMA -* -* This function isolates DMA from the system -* -*/ -/****************************************************************************/ -void dmacHw_exitDma(void); - -/****************************************************************************/ -/** -* @brief Gets a handle to a DMA channel -* -* This function returns a handle, representing a control block of a particular DMA channel -* -* @return -1 - On Failure -* handle - On Success, representing a channel control block -* -* @note -* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ - ); - -/****************************************************************************/ -/** -* @brief Initializes a DMA channel for use -* -* This function initializes and resets a DMA channel for use -* -* @return -1 - On Failure -* 0 - On Success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Estimates number of descriptor needed to perform certain DMA transfer -* -* -* @return On failure : -1 -* On success : Number of descriptor count -* -* -*/ -/****************************************************************************/ -int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Data length in bytes */ - ); - -/****************************************************************************/ -/** -* @brief Initializes descriptor ring -* -* This function will initializes the descriptor ring of a DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* @note -* - "len" parameter should be obtained from "dmacHw_descriptorLen" -* - Descriptor buffer MUST be 32 bit aligned and uncached as it -* is accessed by ARM and DMA -*/ -/****************************************************************************/ -int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ - uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ - uint32_t len, /* [ IN ] Size of the pBuf */ - uint32_t num /* [ IN ] Number of descriptor in the ring */ - ); - -/****************************************************************************/ -/** -* @brief Finds amount of memory required to form a descriptor ring -* -* -* @return Number of bytes required to form a descriptor ring -* -* -* @note -* None -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ - ); - -/****************************************************************************/ -/** -* @brief Configure DMA channel -* -* @return 0 : On success -* -1 : On failure -*/ -/****************************************************************************/ -int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ - ); - -/****************************************************************************/ -/** -* @brief Set descriptors for known data length -* -* When DMA has to work as a flow controller, this function prepares the -* descriptor chain to transfer data -* -* from: -* - Memory to memory -* - Peripheral to memory -* - Memory to Peripheral -* - Peripheral to Peripheral -* -* @return -1 - On failure -* 0 - On success -* -*/ -/****************************************************************************/ -int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ - void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ - size_t dataLen /* [ IN ] Length in bytes */ - ); - -/****************************************************************************/ -/** -* @brief Indicates whether DMA transfer is in progress or completed -* -* @return DMA transfer status -* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing -* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed -* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error -* -*/ -/****************************************************************************/ -dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Set descriptor carrying control information -* -* This function will be used to send specific control information to the device -* using the DMA channel -* -* -* @return -1 - On failure -* 0 - On success -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t ctlAddress, /* [ IN ] Address of the device control register */ - uint32_t control /* [ IN ] Device control information */ - ); - -/****************************************************************************/ -/** -* @brief Read data DMA transferred to memory -* -* This function will read data that has been DMAed to memory while transferring from: -* - Memory to memory -* - Peripheral to memory -* -* @return 0 - No more data is available to read -* 1 - More data might be available to read -* -*/ -/****************************************************************************/ -int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void **ppBbuf, /* [ OUT ] Data received */ - size_t *pLlen /* [ OUT ] Length of the data received */ - ); - -/****************************************************************************/ -/** -* @brief Prepares descriptor ring, when source peripheral working as a flow controller -* -* This function will form the descriptor ring by allocating buffers, when source peripheral -* has to work as a flow controller to transfer data from: -* - Peripheral to memory. -* -* @return -1 - On failure -* 0 - On success -* -* -* @note -* None -*/ -/****************************************************************************/ -int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - uint32_t srcAddr, /* [ IN ] Source peripheral address */ - void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ - int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ - int num /* [ IN ] Number of descriptor to set */ - ); - -/****************************************************************************/ -/** -* @brief Program channel register to initiate transfer -* -* @return void -* -* -* @note -* - Descriptor buffer MUST ALWAYS be flushed before calling this function -* - This function should also be called from ISR to program the channel with -* pending descriptors -*/ -/****************************************************************************/ -void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Resets descriptor control information -* -* @return void -*/ -/****************************************************************************/ -void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Program channel register to stop transfer -* -* Ensures the channel is not doing any transfer after calling this function -* -* @return void -* -*/ -/****************************************************************************/ -void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Check the existence of pending descriptor -* -* This function confirmes if there is any pending descriptor in the chain -* to program the channel -* -* @return 1 : Channel need to be programmed with pending descriptor -* 0 : No more pending descriptor to programe the channel -* -* @note -* - This function should be called from ISR in case there are pending -* descriptor to program the channel. -* -* Example: -* -* dmac_isr () -* { -* ... -* if (dmacHw_descriptorPending (handle)) -* { -* dmacHw_initiateTransfer (handle); -* } -* } -* -*/ -/****************************************************************************/ -uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor /* [ IN ] Descriptor buffer */ - ); - -/****************************************************************************/ -/** -* @brief Deallocates source or destination memory, allocated -* -* This function can be called to deallocate data memory that was DMAed successfully -* -* @return -1 - On failure -* 0 - On success -* -* @note -* This function will be called ONLY, when source OR destination address is pointing -* to dynamic memory -*/ -/****************************************************************************/ -int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ - ); - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the DMA channel specific interrupt -* -* @return N/A -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Returns the cause of channel specific DMA interrupt -* -* This function returns the cause of interrupt -* -* @return Interrupt status, each bit representing a specific type of interrupt -* of type dmacHw_INTERRUPT_STATUS_e -* @note -* This function should be called under the context of ISR -*/ -/****************************************************************************/ -dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Indentifies a DMA channel causing interrupt -* -* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e -* -* @return NULL : No channel causing DMA interrupt -* ! NULL : Handle to a channel causing DMA interrupt -* @note -* dmacHw_clearInterrupt() must be called with a valid handle after calling this function -*/ -/****************************************************************************/ -dmacHw_HANDLE_t dmacHw_getInterruptSource(void); - -/****************************************************************************/ -/** -* @brief Sets channel specific user data -* -* This function associates user data to a specific DMA channel -* -*/ -/****************************************************************************/ -void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *userData /* [ IN ] User data */ - ); - -/****************************************************************************/ -/** -* @brief Gets channel specific user data -* -* This function returns user data specific to a DMA channel -* -* @return user data -*/ -/****************************************************************************/ -void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ - ); - -/****************************************************************************/ -/** -* @brief Displays channel specific registers and other control parameters -* -* -* @return void -* -* @note -* None -*/ -/****************************************************************************/ -void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - void *pDescriptor, /* [ IN ] Descriptor buffer */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ - ); - -/****************************************************************************/ -/** -* @brief Provides DMA controller attributes -* -* -* @return DMA controller attributes -* -* @note -* None -*/ -/****************************************************************************/ -uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ - dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */ - ); - -#endif /* _DMACHW_H */ diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h deleted file mode 100644 index 51357dd5b666..000000000000 --- a/arch/arm/mach-bcmring/include/csp/errno.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_ERRNO_H -#define CSP_ERRNO_H - -/* ---- Include Files ---------------------------------------------------- */ - -#if defined(__KERNEL__) -#include <linux/errno.h> -#elif defined(CSP_SIMULATION) -#include <asm-generic/errno.h> -#else -#include <errno.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_ERRNO_H */ diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h deleted file mode 100644 index 1c639c8ee08f..000000000000 --- a/arch/arm/mach-bcmring/include/csp/intcHw.h +++ /dev/null @@ -1,40 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -/****************************************************************************/ -/** -* @file intcHw.h -* -* @brief generic interrupt controller API -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _INTCHW_H -#define _INTCHW_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <mach/csp/intcHw_reg.h> - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask); -static inline void intcHw_irq_enable(void *basep, uint32_t mask); - -#endif /* _INTCHW_H */ - diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h deleted file mode 100644 index c30d2a5975a6..000000000000 --- a/arch/arm/mach-bcmring/include/csp/module.h +++ /dev/null @@ -1,32 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_MODULE_H -#define CSP_MODULE_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include <linux/module.h> -#else - #define EXPORT_SYMBOL(symbol) -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_MODULE_H */ diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h deleted file mode 100644 index 56654d23c3d7..000000000000 --- a/arch/arm/mach-bcmring/include/csp/reg.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file reg.h -* -* @brief Generic register definitions used in CSP -*/ -/****************************************************************************/ - -#ifndef CSP_REG_H -#define CSP_REG_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/stdint.h> - -/* ---- Public Constants and Types --------------------------------------- */ - -#define __REG32(x) (*((volatile uint32_t *)(x))) -#define __REG16(x) (*((volatile uint16_t *)(x))) -#define __REG8(x) (*((volatile uint8_t *) (x))) - -/* Macros used to define a sequence of reserved registers. The start / end */ -/* are byte offsets in the particular register definition, with the "end" */ -/* being the offset of the next un-reserved register. E.g. if offsets */ -/* 0x10 through to 0x1f are reserved, then this reserved area could be */ -/* specified as follows. */ -/* typedef struct */ -/* { */ -/* uint32_t reg1; offset 0x00 */ -/* uint32_t reg2; offset 0x04 */ -/* uint32_t reg3; offset 0x08 */ -/* uint32_t reg4; offset 0x0c */ -/* REG32_RSVD(0x10, 0x20); */ -/* uint32_t reg5; offset 0x20 */ -/* ... */ -/* } EXAMPLE_REG_t; */ -#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)] -#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)] -#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)] - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */ -/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */ -/* flags variable to be declared locally. */ -/* e.g. */ -/* statement1; */ -/* { */ -/* REG_LOCAL_IRQ_SAVE; */ -/* <multiple statements here> */ -/* REG_LOCAL_IRQ_RESTORE; */ -/* } */ -/* statement2; */ -/* */ - -#if defined(__KERNEL__) && !defined(STANDALONE) -#include <mach/hardware.h> -#include <linux/interrupt.h> - -#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \ - unsigned long flags; HW_IRQ_SAVE(reg32, flags) - -#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags) - -#else - -#define REG_LOCAL_IRQ_SAVE -#define REG_LOCAL_IRQ_RESTORE - -#endif - -static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg &= value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg |= value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, - uint32_t value) -{ - REG_LOCAL_IRQ_SAVE; - *reg = (*reg & mask) | value; - REG_LOCAL_IRQ_RESTORE; -} - -static inline void reg32_write(volatile uint32_t *reg, uint32_t value) -{ - *reg = value; -} - -#endif /* CSP_REG_H */ diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h deleted file mode 100644 index b9d7e0732dfc..000000000000 --- a/arch/arm/mach-bcmring/include/csp/secHw.h +++ /dev/null @@ -1,65 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw.h -* -* @brief Definitions for accessing low level security features -* -*/ -/****************************************************************************/ -#ifndef SECHW_H -#define SECHW_H - -typedef void (*secHw_FUNC_t) (void); - -typedef enum { - secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ - secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ -} secHw_MODE; - -/****************************************************************************/ -/** -* @brief Requesting to execute the function in secure mode -* -* This function requests the given function to run in secure mode -* -*/ -/****************************************************************************/ -void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ - ); - -/****************************************************************************/ -/** -* @brief Sets the mode -* -* his function sets the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_SetMode(secHw_MODE /* Processor mode */ - ); - -/****************************************************************************/ -/** -* @brief Get the current mode -* -* This function retieves the processor mode (secure/non-secure) -* -*/ -/****************************************************************************/ -void secHw_GetMode(secHw_MODE *); - -#endif /* SECHW_H */ diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h deleted file mode 100644 index 3a8718bbf700..000000000000 --- a/arch/arm/mach-bcmring/include/csp/stdint.h +++ /dev/null @@ -1,30 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CSP_STDINT_H -#define CSP_STDINT_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ -#include <linux/types.h> -#else -#include <stdint.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* CSP_STDINT_H */ diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h deleted file mode 100644 index ad9e4005f141..000000000000 --- a/arch/arm/mach-bcmring/include/csp/string.h +++ /dev/null @@ -1,34 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - - -#ifndef CSP_STRING_H -#define CSP_STRING_H - -/* ---- Include Files ---------------------------------------------------- */ - -#ifdef __KERNEL__ - #include <linux/string.h> -#else - #include <string.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_STRING_H */ - diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h deleted file mode 100644 index 2cbb530db8ea..000000000000 --- a/arch/arm/mach-bcmring/include/csp/tmrHw.h +++ /dev/null @@ -1,263 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file tmrHw.h -* -* @brief API definitions for low level Timer driver -* -*/ -/****************************************************************************/ -#ifndef _TMRHW_H -#define _TMRHW_H - -#include <csp/stdint.h> - -typedef uint32_t tmrHw_ID_t; /* Timer ID */ -typedef uint32_t tmrHw_COUNT_t; /* Timer count */ -typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */ -typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */ - -typedef enum { - tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */ - tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */ -} tmrHw_INTERRUPT_STATUS_e; - -typedef enum { - tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */ - tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */ -} tmrHw_CAPABILITY_e; - -/****************************************************************************/ -/** -* @brief Get timer capability -* -* This function returns various capabilities/attributes of a timer -* -* @return Numeric capability -* -*/ -/****************************************************************************/ -uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer in terms of timer interrupt rate -* -* This function initializes a periodic timer to generate specific number of -* timer interrupt per second -* -* @return On success: Effective timer frequency -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt after -* certain time interval -* -* This function initializes a periodic timer to generate timer interrupt -* after every time interval in millisecond -* -* @return On success: Effective interval set in mili-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ -); - -/****************************************************************************/ -/** -* @brief Configures a periodic timer to generate timer interrupt just once -* after certain time interval -* -* This function initializes a periodic timer to generate a single ticks after -* certain time interval in millisecond -* -* @return On success: Effective interval set in mili-second -* On failure: 0 -* -*/ -/****************************************************************************/ -tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ -); - -/****************************************************************************/ -/** -* @brief Configures a timer to run as a free running timer -* -* This function initializes a timer to run as a free running timer -* -* @return Timer resolution (count / sec) -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ - uint32_t divider /* [ IN ] Dividing the clock frequency */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Starts a timer -* -* This function starts a preconfigured timer -* -* @return -1 - On Failure -* 0 - On Success -*/ -/****************************************************************************/ -int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Stops a timer -* -* This function stops a running timer -* -* @return -1 - On Failure -* 0 - On Success -*/ -/****************************************************************************/ -int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Gets current timer count -* -* This function returns the current timer value -* -* @return Current downcounting timer value -* -*/ -/****************************************************************************/ -tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Gets timer count rate -* -* This function returns the number of counts per second -* -* @return Count rate -* -*/ -/****************************************************************************/ -tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ -) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Enables timer interrupt -* -* This function enables the timer interrupt -* -* @return N/A -* -*/ -/****************************************************************************/ -void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Disables timer interrupt -* -* This function disable the timer interrupt -* -* @return N/A -*/ -/****************************************************************************/ -void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Clears the interrupt -* -* This function clears the timer interrupt -* -* @return N/A -* -* @note -* Must be called under the context of ISR -*/ -/****************************************************************************/ -void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Gets the interrupt status -* -* This function returns timer interrupt status -* -* @return Interrupt status -*/ -/****************************************************************************/ -tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ -); - -/****************************************************************************/ -/** -* @brief Indentifies a timer causing interrupt -* -* This functions returns a timer causing interrupt -* -* @return 0xFFFFFFFF : No timer causing an interrupt -* ! 0xFFFFFFFF : timer causing an interrupt -* @note -* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function -*/ -/****************************************************************************/ -tmrHw_ID_t tmrHw_getInterruptSource(void); - -/****************************************************************************/ -/** -* @brief Displays specific timer registers -* -* -* @return void -* -*/ -/****************************************************************************/ -void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ -); - -/****************************************************************************/ -/** -* @brief Use a timer to perform a busy wait delay for a number of usecs. -* -* @return N/A -*/ -/****************************************************************************/ -void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ - unsigned long usecs /* [ IN ] usec to delay */ -) __attribute__ ((section(".aramtext"))); - -#endif /* _TMRHW_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h deleted file mode 100644 index 30fa2d540630..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/cap.h +++ /dev/null @@ -1,63 +0,0 @@ -/***************************************************************************** -* Copyright 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CAP_H -#define CAP_H - -/* ---- Include Files ---------------------------------------------------- */ -/* ---- Public Constants and Types --------------------------------------- */ -typedef enum { - CAP_NOT_PRESENT = 0, - CAP_PRESENT -} CAP_RC_T; - -typedef enum { - CAP_VPM, - CAP_ETH_PHY, - CAP_ETH_GMII, - CAP_ETH_SGMII, - CAP_USB, - CAP_TSC, - CAP_EHSS, - CAP_SDIO, - CAP_UARTB, - CAP_KEYPAD, - CAP_CLCD, - CAP_GE, - CAP_LEDM, - CAP_BBL, - CAP_VDEC, - CAP_PIF, - CAP_APM, - CAP_SPU, - CAP_PKA, - CAP_RNG, -} CAP_CAPABILITY_T; - -typedef enum { - CAP_LCD_WVGA = 0, - CAP_LCD_VGA = 0x1, - CAP_LCD_WQVGA = 0x2, - CAP_LCD_QVGA = 0x3 -} CAP_LCD_RES_T; - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index); -static inline uint32_t cap_getMaxArmSpeedHz(void); -static inline uint32_t cap_getMaxVpmSpeedHz(void); -static inline CAP_LCD_RES_T cap_getMaxLcdRes(void); - -#endif diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h deleted file mode 100644 index 933ce68ed90b..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ /dev/null @@ -1,409 +0,0 @@ -/***************************************************************************** -* Copyright 2009 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CAP_INLINE_H -#define CAP_INLINE_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <mach/csp/cap.h> -#include <cfg_global.h> - -/* ---- Public Constants and Types --------------------------------------- */ -#define CAP_CONFIG0_VPM_DIS 0x00000001 -#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002 -#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004 -#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008 -#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010 -#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020 -#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040 -#define CAP_CONFIG0_USB0_DIS 0x00000080 -#define CAP_CONFIG0_USB1_DIS 0x00000100 -#define CAP_CONFIG0_TSC_DIS 0x00000200 -#define CAP_CONFIG0_EHSS0_DIS 0x00000400 -#define CAP_CONFIG0_EHSS1_DIS 0x00000800 -#define CAP_CONFIG0_SDIO0_DIS 0x00001000 -#define CAP_CONFIG0_SDIO1_DIS 0x00002000 -#define CAP_CONFIG0_UARTB_DIS 0x00004000 -#define CAP_CONFIG0_KEYPAD_DIS 0x00008000 -#define CAP_CONFIG0_CLCD_DIS 0x00010000 -#define CAP_CONFIG0_GE_DIS 0x00020000 -#define CAP_CONFIG0_LEDM_DIS 0x00040000 -#define CAP_CONFIG0_BBL_DIS 0x00080000 -#define CAP_CONFIG0_VDEC_DIS 0x00100000 -#define CAP_CONFIG0_PIF_DIS 0x00200000 -#define CAP_CONFIG0_RESERVED1_DIS 0x00400000 -#define CAP_CONFIG0_RESERVED2_DIS 0x00800000 - -#define CAP_CONFIG1_APMA_DIS 0x00000001 -#define CAP_CONFIG1_APMB_DIS 0x00000002 -#define CAP_CONFIG1_APMC_DIS 0x00000004 -#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600 -#define CAP_CONFIG1_CLCD_RES_SHIFT 9 -#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT) -#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT) -#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT) -#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT) - -#define CAP_CONFIG2_SPU_DIS 0x00000010 -#define CAP_CONFIG2_PKA_DIS 0x00000020 -#define CAP_CONFIG2_RNG_DIS 0x00000080 - -#if (CFG_GLOBAL_CHIP == BCM11107) -#define capConfig0 0 -#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA -#define capConfig2 0 -#define CAP_APM_MAX_NUM_CHANS 3 -#elif (CFG_GLOBAL_CHIP == FPGA11107) -#define capConfig0 0 -#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA -#define capConfig2 0 -#define CAP_APM_MAX_NUM_CHANS 3 -#elif (CFG_GLOBAL_CHIP == BCM11109) -#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) -#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) -#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) -#define CAP_APM_MAX_NUM_CHANS 2 -#elif (CFG_GLOBAL_CHIP == BCM11170) -#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) -#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) -#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) -#define CAP_APM_MAX_NUM_CHANS 2 -#elif (CFG_GLOBAL_CHIP == BCM11110) -#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) -#define capConfig1 CAP_CONFIG1_APMC_DIS -#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) -#define CAP_APM_MAX_NUM_CHANS 2 -#elif (CFG_GLOBAL_CHIP == BCM11211) -#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS) -#define capConfig1 CAP_CONFIG1_APMC_DIS -#define capConfig2 0 -#define CAP_APM_MAX_NUM_CHANS 2 -#else -#error CFG_GLOBAL_CHIP type capabilities not defined -#endif - -#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) -#define CAP_HW_CFG_ARM_CLK_HZ 500000000 -#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) -#define CAP_HW_CFG_ARM_CLK_HZ 300000000 -#elif (CFG_GLOBAL_CHIP == BCM11211) -#define CAP_HW_CFG_ARM_CLK_HZ 666666666 -#else -#error CFG_GLOBAL_CHIP type capabilities not defined -#endif - -#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) -#define CAP_HW_CFG_VPM_CLK_HZ 333333333 -#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) -#define CAP_HW_CFG_VPM_CLK_HZ 200000000 -#else -#error CFG_GLOBAL_CHIP type capabilities not defined -#endif - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -/**************************************************************************** -* cap_isPresent - -* -* PURPOSE: -* Determines if the chip has a certain capability present -* -* PARAMETERS: -* capability - type of capability to determine if present -* -* RETURNS: -* CAP_PRESENT or CAP_NOT_PRESENT -****************************************************************************/ -static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index) -{ - CAP_RC_T returnVal = CAP_NOT_PRESENT; - - switch (capability) { - case CAP_VPM: - { - if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_ETH_PHY: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_ETH_GMII: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_ETH_SGMII: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_USB: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_TSC: - { - if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_EHSS: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_SDIO: - { - if ((index == 0) - && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_UARTB: - { - if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_KEYPAD: - { - if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_CLCD: - { - if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_GE: - { - if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_LEDM: - { - if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_BBL: - { - if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_VDEC: - { - if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_PIF: - { - if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_APM: - { - if ((index == 0) - && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 1) - && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) { - returnVal = CAP_PRESENT; - } - if ((index == 2) - && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_SPU: - { - if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_PKA: - { - if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - case CAP_RNG: - { - if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) { - returnVal = CAP_PRESENT; - } - } - break; - - default: - { - } - break; - } - return returnVal; -} - -/**************************************************************************** -* cap_getMaxArmSpeedHz - -* -* PURPOSE: -* Determines the maximum speed of the ARM CPU -* -* PARAMETERS: -* none -* -* RETURNS: -* clock speed in Hz that the ARM processor is able to run at -****************************************************************************/ -static inline uint32_t cap_getMaxArmSpeedHz(void) -{ -#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) - return 500000000; -#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) - return 300000000; -#elif (CFG_GLOBAL_CHIP == BCM11211) - return 666666666; -#else -#error CFG_GLOBAL_CHIP type capabilities not defined -#endif -} - -/**************************************************************************** -* cap_getMaxVpmSpeedHz - -* -* PURPOSE: -* Determines the maximum speed of the VPM -* -* PARAMETERS: -* none -* -* RETURNS: -* clock speed in Hz that the VPM is able to run at -****************************************************************************/ -static inline uint32_t cap_getMaxVpmSpeedHz(void) -{ -#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) - return 333333333; -#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) - return 200000000; -#else -#error CFG_GLOBAL_CHIP type capabilities not defined -#endif -} - -/**************************************************************************** -* cap_getMaxLcdRes - -* -* PURPOSE: -* Determines the maximum LCD resolution capabilities -* -* PARAMETERS: -* none -* -* RETURNS: -* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA -* -****************************************************************************/ -static inline CAP_LCD_RES_T cap_getMaxLcdRes(void) -{ - return (CAP_LCD_RES_T) - ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >> - CAP_CONFIG1_CLCD_RES_SHIFT); -} - -#endif diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h deleted file mode 100644 index 161973385faf..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ /dev/null @@ -1,1123 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CHIPC_DEF_H -#define CHIPC_DEF_H - -/* ---- Include Files ----------------------------------------------------- */ - -#include <csp/stdint.h> -#include <csp/errno.h> -#include <csp/reg.h> -#include <mach/csp/chipcHw_reg.h> - -/* ---- Public Constants and Types ---------------------------------------- */ - -/* Set 1 to configure DDR/VPM phase alignment by HW */ -#define chipcHw_DDR_HW_PHASE_ALIGN 0 -#define chipcHw_VPM_HW_PHASE_ALIGN 0 - -typedef uint32_t chipcHw_freq; - -/* Configurable miscellaneous clocks */ -typedef enum { - chipcHw_CLOCK_DDR, /* DDR PHY Clock */ - chipcHw_CLOCK_ARM, /* ARM Clock */ - chipcHw_CLOCK_ESW, /* Ethernet Switch Clock */ - chipcHw_CLOCK_VPM, /* VPM Clock */ - chipcHw_CLOCK_ESW125, /* Ethernet MII Clock */ - chipcHw_CLOCK_UART, /* UART Clock */ - chipcHw_CLOCK_SDIO0, /* SDIO 0 Clock */ - chipcHw_CLOCK_SDIO1, /* SDIO 1 Clock */ - chipcHw_CLOCK_SPI, /* SPI Clock */ - chipcHw_CLOCK_ETM, /* ARM ETM Clock */ - - chipcHw_CLOCK_BUS, /* BUS Clock */ - chipcHw_CLOCK_OTP, /* OTP Clock */ - chipcHw_CLOCK_I2C, /* I2C Host Clock */ - chipcHw_CLOCK_I2S0, /* I2S 0 Host Clock */ - chipcHw_CLOCK_RTBUS, /* DDR PHY Configuration Clock */ - chipcHw_CLOCK_APM100, /* APM100 Clock */ - chipcHw_CLOCK_TSC, /* Touch screen Clock */ - chipcHw_CLOCK_LED, /* LED Clock */ - - chipcHw_CLOCK_USB, /* USB Clock */ - chipcHw_CLOCK_LCD, /* LCD CLock */ - chipcHw_CLOCK_APM, /* APM Clock */ - - chipcHw_CLOCK_I2S1, /* I2S 1 Host Clock */ -} chipcHw_CLOCK_e; - -/* System booting strap options */ -typedef enum { - chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART, - chipcHw_BOOT_DEVICE_SERIAL_FLASH = - chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH, - chipcHw_BOOT_DEVICE_NOR_FLASH_16 = - chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16, - chipcHw_BOOT_DEVICE_NAND_FLASH_8 = - chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8, - chipcHw_BOOT_DEVICE_NAND_FLASH_16 = - chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 -} chipcHw_BOOT_DEVICE_e; - -/* System booting modes */ -typedef enum { - chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL, - chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW, - chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT, - chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET -} chipcHw_BOOT_MODE_e; - -/* NAND Flash page size strap options */ -typedef enum { - chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512, - chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048, - chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096, - chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT -} chipcHw_NAND_PAGESIZE_e; - -/* GPIO Pin function */ -typedef enum { - chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD, - chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH, - chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI, - chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART, - chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP, - chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS, - chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0, - chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1, - chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM, - chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S, - chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM, - chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG, - chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC, - chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO -} chipcHw_GPIO_FUNCTION_e; - -/* PIN Output slew rate */ -typedef enum { - chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH, - chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL -} chipcHw_PIN_SLEW_RATE_e; - -/* PIN Current drive strength */ -typedef enum { - chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA, - chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA, - chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA, - chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA, - chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA, - chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA -} chipcHw_PIN_CURRENT_STRENGTH_e; - -/* PIN Pull up register settings */ -typedef enum { - chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE, - chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP, - chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN -} chipcHw_PIN_PULL_e; - -/* PIN input type settings */ -typedef enum { - chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS, - chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST -} chipcHw_PIN_INPUTTYPE_e; - -/* Allow/Disalow the support of spread spectrum */ -typedef enum { - chipcHw_SPREAD_SPECTRUM_DISALLOW, /* Spread spectrum support is not allowed */ - chipcHw_SPREAD_SPECTRUM_ALLOW /* Spread spectrum support is allowed */ -} chipcHw_SPREAD_SPECTRUM_e; - -typedef struct { - chipcHw_SPREAD_SPECTRUM_e ssSupport; /* Allow/Disalow to support spread spectrum. - If supported, call chipcHw_enableSpreadSpectrum () - to activate the spread spectrum with desired spread. */ - uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */ - uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */ - uint32_t busClockFreqHz; /* Bus clock frequency in Hz */ - uint32_t armBusRatio; /* ARM clock : Bus clock */ - uint32_t vpmBusRatio; /* VPM clock : Bus clock */ - uint32_t ddrBusRatio; /* DDR clock : Bus clock */ -} chipcHw_INIT_PARAM_t; - -/* CHIP revision number */ -typedef enum { - chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0, - chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0 -} chipcHw_REV_NUMBER_e; - -typedef enum { - chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE, - chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST, - chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM, - chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW -} chipcHw_VPM_HW_PHASE_INTR_e; - -typedef enum { - chipcHw_DDR_HW_PHASE_MARGIN_STRICT, /* Strict margin for DDR phase align condition */ - chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for DDR phase align condition */ - chipcHw_DDR_HW_PHASE_MARGIN_WIDE /* Wider margin for DDR phase align condition */ -} chipcHw_DDR_HW_PHASE_MARGIN_e; - -typedef enum { - chipcHw_VPM_HW_PHASE_MARGIN_STRICT, /* Strict margin for VPM phase align condition */ - chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for VPM phase align condition */ - chipcHw_VPM_HW_PHASE_MARGIN_WIDE /* Wider margin for VPM phase align condition */ -} chipcHw_VPM_HW_PHASE_MARGIN_e; - -#define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */ - -/* Programmable pin defines */ -#define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF) - /* GPIO pin 0 - 60 */ -#define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */ -#define chipcHw_PIN_NVI_A (chipcHw_GPIO_COUNT + 1) /* NVI Interface */ -#define chipcHw_PIN_NVI_D (chipcHw_GPIO_COUNT + 2) /* NVI Interface */ -#define chipcHw_PIN_NVI_OEB (chipcHw_GPIO_COUNT + 3) /* NVI Interface */ -#define chipcHw_PIN_NVI_WEB (chipcHw_GPIO_COUNT + 4) /* NVI Interface */ -#define chipcHw_PIN_NVI_CS (chipcHw_GPIO_COUNT + 5) /* NVI Interface */ -#define chipcHw_PIN_NVI_NAND_CSB (chipcHw_GPIO_COUNT + 6) /* NVI Interface */ -#define chipcHw_PIN_NVI_FLASHWP (chipcHw_GPIO_COUNT + 7) /* NVI Interface */ -#define chipcHw_PIN_NVI_NAND_RDYB (chipcHw_GPIO_COUNT + 8) /* NVI Interface */ -#define chipcHw_PIN_CL_DATA_0_17 (chipcHw_GPIO_COUNT + 9) /* LCD Data 0 - 17 */ -#define chipcHw_PIN_CL_DATA_18_20 (chipcHw_GPIO_COUNT + 10) /* LCD Data 18 - 20 */ -#define chipcHw_PIN_CL_DATA_21_23 (chipcHw_GPIO_COUNT + 11) /* LCD Data 21 - 23 */ -#define chipcHw_PIN_CL_POWER (chipcHw_GPIO_COUNT + 12) /* LCD Power */ -#define chipcHw_PIN_CL_ACK (chipcHw_GPIO_COUNT + 13) /* LCD Ack */ -#define chipcHw_PIN_CL_FP (chipcHw_GPIO_COUNT + 14) /* LCD FP */ -#define chipcHw_PIN_CL_LP (chipcHw_GPIO_COUNT + 15) /* LCD LP */ -#define chipcHw_PIN_UARTRXD (chipcHw_GPIO_COUNT + 16) /* UART Receive */ - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -/****************************************************************************/ -/** -* @brief Initializes the clock module -* -*/ -/****************************************************************************/ -void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */ - ) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Enables the PLL1 -* -* This function enables the PLL1 -* -*/ -/****************************************************************************/ -void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */ - chipcHw_SPREAD_SPECTRUM_e ssSupport /* [ IN ] SS status */ - ) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Enables the PLL2 -* -* This function enables the PLL2 -* -*/ -/****************************************************************************/ -void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */ - ) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Disable the PLL1 -* -*/ -/****************************************************************************/ -static inline void chipcHw_pll1Disable(void); - -/****************************************************************************/ -/** -* @brief Disable the PLL2 -* -*/ -/****************************************************************************/ -static inline void chipcHw_pll2Disable(void); - -/****************************************************************************/ -/** -* @brief Set clock fequency for miscellaneous configurable clocks -* -* This function sets clock frequency -* -* @return Configured clock frequency in KHz -* -*/ -/****************************************************************************/ -chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Set clock fequency for miscellaneous configurable clocks -* -* This function sets clock frequency -* -* @return Configured clock frequency in Hz -* -*/ -/****************************************************************************/ -chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ - uint32_t freq /* [ IN ] Clock frequency in Hz */ - ) __attribute__ ((section(".aramtext"))); - -/****************************************************************************/ -/** -* @brief Set VPM clock in sync with BUS clock -* -* This function does the phase adjustment between VPM and BUS clock -* -* @return >= 0 : On success ( # of adjustment required ) -* -1 : On failure -*/ -/****************************************************************************/ -int chipcHw_vpmPhaseAlign(void); - -/****************************************************************************/ -/** -* @brief Enables core a clock of a certain device -* -* This function enables a core clock -* -* @return void -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ); - -/****************************************************************************/ -/** -* @brief Disabled a core clock of a certain device -* -* This function disables a core clock -* -* @return void -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ); - -/****************************************************************************/ -/** -* @brief Enables bypass clock of a certain device -* -* This function enables bypass clock -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ); - -/****************************************************************************/ -/** -* @brief Disabled bypass clock of a certain device -* -* This function disables bypass clock -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ - ); - -/****************************************************************************/ -/** -* @brief Get Numeric Chip ID -* -* This function returns Chip ID that includes the revison number -* -* @return Complete numeric Chip ID -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getChipId(void); - -/****************************************************************************/ -/** -* @brief Get Chip Product ID -* -* This function returns Chip Product ID -* -* @return Chip Product ID -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getChipProductId(void); - -/****************************************************************************/ -/** -* @brief Get revision number -* -* This function returns revision number of the chip -* -* @return Revision number -*/ -/****************************************************************************/ -static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void); - -/****************************************************************************/ -/** -* @brief Enables bus interface clock -* -* Enables bus interface clock of various device -* -* @return void -* -* @note use chipcHw_REG_BUS_CLOCK_XXXX -*/ -/****************************************************************************/ -static inline void chipcHw_busInterfaceClockEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Disables bus interface clock -* -* Disables bus interface clock of various device -* -* @return void -* -* @note use chipcHw_REG_BUS_CLOCK_XXXX -*/ -/****************************************************************************/ -static inline void chipcHw_busInterfaceClockDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Enables various audio channels -* -* Enables audio channel -* -* @return void -* -* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_audioChannelEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Disables various audio channels -* -* Disables audio channel -* -* @return void -* -* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_audioChannelDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Soft resets devices -* -* Soft resets various devices -* -* @return void -* -* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines -*/ -/****************************************************************************/ -static inline void chipcHw_softReset(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ - ); - -static inline void chipcHw_softResetDisable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ - ); - -static inline void chipcHw_softResetEnable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Configures misc CHIP functionality -* -* Configures CHIP functionality -* -* @return void -* -* @note use chipcHw_REG_MISC_CTRL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_miscControl(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ - ); - -static inline void chipcHw_miscControlDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ - ); - -static inline void chipcHw_miscControlEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Set OTP options -* -* Set OTP options -* -* @return void -* -* @note use chipcHw_REG_OTP_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_setOTPOption(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Get sticky bits -* -* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getStickyBits(void); - -/****************************************************************************/ -/** -* @brief Set sticky bits -* -* @return void -* -* @note use chipcHw_REG_STICKY_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_setStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Clear sticky bits -* -* @return void -* -* @note use chipcHw_REG_STICKY_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_clearStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Get software override strap options -* -* Retrieves software override strap options -* -* @return Software override strap value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getSoftStraps(void); - -/****************************************************************************/ -/** -* @brief Set software override strap options -* -* set software override strap options -* -* @return nothing -* -*/ -/****************************************************************************/ -static inline void chipcHw_setSoftStraps(uint32_t strapOptions); - -/****************************************************************************/ -/** -* @brief Get pin strap options -* -* Retrieves pin strap options -* -* @return Pin strap value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getPinStraps(void); - -/****************************************************************************/ -/** -* @brief Get valid pin strap options -* -* Retrieves valid pin strap options -* -* @return valid Pin strap value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getValidStraps(void); - -/****************************************************************************/ -/** -* @brief Initialize valid pin strap options -* -* Retrieves valid pin strap options by copying HW strap options to soft register -* (if chipcHw_STRAPS_SOFT_OVERRIDE not set) -* -* @return nothing -* -*/ -/****************************************************************************/ -static inline void chipcHw_initValidStraps(void); - -/****************************************************************************/ -/** -* @brief Get status (enabled/disabled) of bus interface clock -* -* This function returns the status of devices' bus interface clock -* -* @return Bus interface clock -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getBusInterfaceClockStatus(void); - -/****************************************************************************/ -/** -* @brief Get boot device -* -* This function returns the device type used in booting the system -* -* @return Boot device of type chipcHw_BOOT_DEVICE_e -* -*/ -/****************************************************************************/ -static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void); - -/****************************************************************************/ -/** -* @brief Get boot mode -* -* This function returns the way the system was booted -* -* @return Boot mode of type chipcHw_BOOT_MODE_e -* -*/ -/****************************************************************************/ -static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void); - -/****************************************************************************/ -/** -* @brief Get NAND flash page size -* -* This function returns the NAND device page size -* -* @return Boot NAND device page size -* -*/ -/****************************************************************************/ -static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void); - -/****************************************************************************/ -/** -* @brief Get NAND flash address cycle configuration -* -* This function returns the NAND flash address cycle configuration -* -* @return 0 = Do not extra address cycle, 1 = Add extra cycle -* -*/ -/****************************************************************************/ -static inline int chipcHw_getNandExtraCycle(void); - -/****************************************************************************/ -/** -* @brief Activates PIF interface -* -* This function activates PIF interface by taking control of LCD pins -* -* @note -* When activated, LCD pins will be defined as follows for PIF operation -* -* CLD[17:0] = pif_data[17:0] -* CLD[23:18] = pif_address[5:0] -* CLPOWER = pif_wr_str -* CLCP = pif_rd_str -* CLAC = pif_hat1 -* CLFP = pif_hrdy1 -* CLLP = pif_hat2 -* GPIO[42] = pif_hrdy2 -* -* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_activatePifInterface(void); - -/****************************************************************************/ -/** -* @brief Activates LCD interface -* -* This function activates LCD interface -* -* @note -* When activated, LCD pins will be defined as follows -* -* CLD[17:0] = LCD data -* CLD[23:18] = LCD data -* CLPOWER = LCD power -* CLCP = -* CLAC = LCD ack -* CLFP = -* CLLP = -*/ -/****************************************************************************/ -static inline void chipcHw_activateLcdInterface(void); - -/****************************************************************************/ -/** -* @brief Deactivates PIF/LCD interface -* -* This function deactivates PIF/LCD interface -* -* @note -* When deactivated LCD pins will be in rti-stated -* -*/ -/****************************************************************************/ -static inline void chipcHw_deactivatePifLcdInterface(void); - -/****************************************************************************/ -/** -* @brief Get to know the configuration of GPIO pin -* -*/ -/****************************************************************************/ -static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin /* GPIO Pin number */ - ); - -/****************************************************************************/ -/** -* @brief Configure GPIO pin function -* -*/ -/****************************************************************************/ -static inline void chipcHw_setGpioPinFunction(int pin, /* GPIO Pin number */ - chipcHw_GPIO_FUNCTION_e func /* Configuration function */ - ); - -/****************************************************************************/ -/** -* @brief Set Pin slew rate -* -* This function sets the slew of individual pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ - chipcHw_PIN_SLEW_RATE_e slewRate /* Pin slew rate */ - ); - -/****************************************************************************/ -/** -* @brief Set Pin output drive current -* -* This function sets output drive current of individual pin -* -* Note: Avoid the use of the word 'current' since linux headers define this -* to be the current task. -*/ -/****************************************************************************/ -static inline void chipcHw_setPinOutputCurrent(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ - chipcHw_PIN_CURRENT_STRENGTH_e curr /* Pin current rating */ - ); - -/****************************************************************************/ -/** -* @brief Set Pin pullup register -* -* This function sets pullup register of individual pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinPullup(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ - chipcHw_PIN_PULL_e pullup /* Pullup register settings */ - ); - -/****************************************************************************/ -/** -* @brief Set Pin input type -* -* This function sets input type of individual Pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinInputType(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ - chipcHw_PIN_INPUTTYPE_e inputType /* Pin input type */ - ); - -/****************************************************************************/ -/** -* @brief Retrieves a string representation of the mux setting for a pin. -* -* @return Pointer to a character string. -*/ -/****************************************************************************/ - -const char *chipcHw_getGpioPinFunctionStr(int pin); - -/****************************************************************************/ -/** @brief issue warmReset - */ -/****************************************************************************/ -void chipcHw_reset(uint32_t mask); - -/****************************************************************************/ -/** @brief clock reconfigure - */ -/****************************************************************************/ -void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio, - uint32_t ddrRatio); - -/****************************************************************************/ -/** -* @brief Enable Spread Spectrum -* -* @note chipcHw_Init() must be called earlier -*/ -/****************************************************************************/ -static inline void chipcHw_enableSpreadSpectrum(void); - -/****************************************************************************/ -/** -* @brief Disable Spread Spectrum -* -*/ -/****************************************************************************/ -static inline void chipcHw_disableSpreadSpectrum(void); - -/****************************************************************************/ -/** @brief Checks if software strap is enabled - * - * @return 1 : When enable - * 0 : When disable - */ -/****************************************************************************/ -static inline int chipcHw_isSoftwareStrapsEnable(void); - -/****************************************************************************/ -/** @brief Enable software strap - */ -/****************************************************************************/ -static inline void chipcHw_softwareStrapsEnable(void); - -/****************************************************************************/ -/** @brief Disable software strap - */ -/****************************************************************************/ -static inline void chipcHw_softwareStrapsDisable(void); - -/****************************************************************************/ -/** @brief PLL test enable - */ -/****************************************************************************/ -static inline void chipcHw_pllTestEnable(void); - -/****************************************************************************/ -/** @brief PLL2 test enable - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestEnable(void); - -/****************************************************************************/ -/** @brief PLL test disable - */ -/****************************************************************************/ -static inline void chipcHw_pllTestDisable(void); - -/****************************************************************************/ -/** @brief PLL2 test disable - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestDisable(void); - -/****************************************************************************/ -/** @brief Get PLL test status - */ -/****************************************************************************/ -static inline int chipcHw_isPllTestEnable(void); - -/****************************************************************************/ -/** @brief Get PLL2 test status - */ -/****************************************************************************/ -static inline int chipcHw_isPll2TestEnable(void); - -/****************************************************************************/ -/** @brief PLL test select - */ -/****************************************************************************/ -static inline void chipcHw_pllTestSelect(uint32_t val); - -/****************************************************************************/ -/** @brief PLL2 test select - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestSelect(uint32_t val); - -/****************************************************************************/ -/** @brief Get PLL test selected option - */ -/****************************************************************************/ -static inline uint8_t chipcHw_getPllTestSelected(void); - -/****************************************************************************/ -/** @brief Get PLL2 test selected option - */ -/****************************************************************************/ -static inline uint8_t chipcHw_getPll2TestSelected(void); - -/****************************************************************************/ -/** -* @brief Enables DDR SW phase alignment interrupt -*/ -/****************************************************************************/ -static inline void chipcHw_ddrPhaseAlignInterruptEnable(void); - -/****************************************************************************/ -/** -* @brief Disables DDR SW phase alignment interrupt -*/ -/****************************************************************************/ -static inline void chipcHw_ddrPhaseAlignInterruptDisable(void); - -/****************************************************************************/ -/** -* @brief Set VPM SW phase alignment interrupt mode -* -* This function sets VPM phase alignment interrupt -* -*/ -/****************************************************************************/ -static inline void -chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode); - -/****************************************************************************/ -/** -* @brief Enable DDR phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrSwPhaseAlignEnable(void); - -/****************************************************************************/ -/** -* @brief Disable DDR phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrSwPhaseAlignDisable(void); - -/****************************************************************************/ -/** -* @brief Enable DDR phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignEnable(void); - -/****************************************************************************/ -/** -* @brief Disable DDR phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignDisable(void); - -/****************************************************************************/ -/** -* @brief Enable VPM phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmSwPhaseAlignEnable(void); - -/****************************************************************************/ -/** -* @brief Disable VPM phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmSwPhaseAlignDisable(void); - -/****************************************************************************/ -/** -* @brief Enable VPM phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignEnable(void); - -/****************************************************************************/ -/** -* @brief Disable VPM phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignDisable(void); - -/****************************************************************************/ -/** -* @brief Set DDR phase alignment margin in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin /* Margin alinging DDR phase */ - ); - -/****************************************************************************/ -/** -* @brief Set VPM phase alignment margin in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin /* Margin alinging VPM phase */ - ); - -/****************************************************************************/ -/** -* @brief Checks DDR phase aligned status done by HW -* -* @return 1: When aligned -* 0: When not aligned -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_isDdrHwPhaseAligned(void); - -/****************************************************************************/ -/** -* @brief Checks VPM phase aligned status done by HW -* -* @return 1: When aligned -* 0: When not aligned -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_isVpmHwPhaseAligned(void); - -/****************************************************************************/ -/** -* @brief Get DDR phase aligned status done by HW -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void); - -/****************************************************************************/ -/** -* @brief Get VPM phase aligned status done by HW -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void); - -/****************************************************************************/ -/** -* @brief Get DDR phase control value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getDdrPhaseControl(void); - -/****************************************************************************/ -/** -* @brief Get VPM phase control value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getVpmPhaseControl(void); - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout count -* -* @note If HW fails to perform the phase alignment, it will trigger -* a DDR phase alignment timeout interrupt. -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */ - ); - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout count -* -* @note If HW fails to perform the phase alignment, it will trigger -* a VPM phase alignment timeout interrupt. -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */ - ); - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout interrupt enable -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void); - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout interrupt enable -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void); - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout interrupt disable -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void); - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout interrupt disable -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void); - -/****************************************************************************/ -/** -* @brief Clear DDR phase alignment timeout interrupt -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void); - -/****************************************************************************/ -/** -* @brief Clear VPM phase alignment timeout interrupt -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void); - -/* ---- Private Constants and Types -------------------------------------- */ - -#endif /* CHIPC_DEF_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h deleted file mode 100644 index 03238c299001..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ /dev/null @@ -1,1673 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef CHIPC_INLINE_H -#define CHIPC_INLINE_H - -/* ---- Include Files ----------------------------------------------------- */ - -#include <csp/errno.h> -#include <csp/reg.h> -#include <mach/csp/chipcHw_reg.h> -#include <mach/csp/chipcHw_def.h> - -/* ---- Private Constants and Types --------------------------------------- */ -typedef enum { - chipcHw_OPTYPE_BYPASS, /* Bypass operation */ - chipcHw_OPTYPE_OUTPUT /* Output operation */ -} chipcHw_OPTYPE_e; - -/* ---- Public Constants and Types ---------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------- */ -/* ---- Public Function Prototypes ---------------------------------------- */ -/* ---- Private Function Prototypes --------------------------------------- */ -static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, - chipcHw_OPTYPE_e type, int mode); - -/****************************************************************************/ -/** -* @brief Get Numeric Chip ID -* -* This function returns Chip ID that includes the revison number -* -* @return Complete numeric Chip ID -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getChipId(void) -{ - return pChipcHw->ChipId; -} - -/****************************************************************************/ -/** -* @brief Enable Spread Spectrum -* -* @note chipcHw_Init() must be called earlier -*/ -/****************************************************************************/ -static inline void chipcHw_enableSpreadSpectrum(void) -{ - if ((pChipcHw-> - PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != - chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = - (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | - (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); - ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; - } -} - -/****************************************************************************/ -/** -* @brief Disable Spread Spectrum -* -*/ -/****************************************************************************/ -static inline void chipcHw_disableSpreadSpectrum(void) -{ - ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; -} - -/****************************************************************************/ -/** -* @brief Get Chip Product ID -* -* This function returns Chip Product ID -* -* @return Chip Product ID -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getChipProductId(void) -{ - return (pChipcHw-> - ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> - chipcHw_REG_CHIPID_BASE_SHIFT; -} - -/****************************************************************************/ -/** -* @brief Get revision number -* -* This function returns revision number of the chip -* -* @return Revision number -*/ -/****************************************************************************/ -static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) -{ - return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; -} - -/****************************************************************************/ -/** -* @brief Enables bus interface clock -* -* Enables bus interface clock of various device -* -* @return void -* -* @note use chipcHw_REG_BUS_CLOCK_XXXX for mask -*/ -/****************************************************************************/ -static inline void chipcHw_busInterfaceClockEnable(uint32_t mask) -{ - reg32_modify_or(&pChipcHw->BusIntfClock, mask); -} - -/****************************************************************************/ -/** -* @brief Disables bus interface clock -* -* Disables bus interface clock of various device -* -* @return void -* -* @note use chipcHw_REG_BUS_CLOCK_XXXX -*/ -/****************************************************************************/ -static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) -{ - reg32_modify_and(&pChipcHw->BusIntfClock, ~mask); -} - -/****************************************************************************/ -/** -* @brief Get status (enabled/disabled) of bus interface clock -* -* This function returns the status of devices' bus interface clock -* -* @return Bus interface clock -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) -{ - return pChipcHw->BusIntfClock; -} - -/****************************************************************************/ -/** -* @brief Enables various audio channels -* -* Enables audio channel -* -* @return void -* -* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_audioChannelEnable(uint32_t mask) -{ - reg32_modify_or(&pChipcHw->AudioEnable, mask); -} - -/****************************************************************************/ -/** -* @brief Disables various audio channels -* -* Disables audio channel -* -* @return void -* -* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_audioChannelDisable(uint32_t mask) -{ - reg32_modify_and(&pChipcHw->AudioEnable, ~mask); -} - -/****************************************************************************/ -/** -* @brief Soft resets devices -* -* Soft resets various devices -* -* @return void -* -* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines -*/ -/****************************************************************************/ -static inline void chipcHw_softReset(uint64_t mask) -{ - chipcHw_softResetEnable(mask); - chipcHw_softResetDisable(mask); -} - -static inline void chipcHw_softResetDisable(uint64_t mask) -{ - uint32_t ctrl1 = (uint32_t) mask; - uint32_t ctrl2 = (uint32_t) (mask >> 32); - - /* Deassert module soft reset */ - REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 ^= ctrl1; - pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); - REG_LOCAL_IRQ_RESTORE; -} - -static inline void chipcHw_softResetEnable(uint64_t mask) -{ - uint32_t ctrl1 = (uint32_t) mask; - uint32_t ctrl2 = (uint32_t) (mask >> 32); - uint32_t unhold = 0; - - REG_LOCAL_IRQ_SAVE; - pChipcHw->SoftReset1 |= ctrl1; - /* Mask out unhold request bits */ - pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); - - /* Process unhold requests */ - if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { - unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD; - } - - if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) { - unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD; - } - - if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) { - unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD; - } - - if (unhold) { - /* Make sure unhold request is effective */ - pChipcHw->SoftReset1 &= ~unhold; - } - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Configures misc CHIP functionality -* -* Configures CHIP functionality -* -* @return void -* -* @note use chipcHw_REG_MISC_CTRL_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_miscControl(uint32_t mask) -{ - reg32_write(&pChipcHw->MiscCtrl, mask); -} - -static inline void chipcHw_miscControlDisable(uint32_t mask) -{ - reg32_modify_and(&pChipcHw->MiscCtrl, ~mask); -} - -static inline void chipcHw_miscControlEnable(uint32_t mask) -{ - reg32_modify_or(&pChipcHw->MiscCtrl, mask); -} - -/****************************************************************************/ -/** -* @brief Set OTP options -* -* Set OTP options -* -* @return void -* -* @note use chipcHw_REG_OTP_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_setOTPOption(uint64_t mask) -{ - uint32_t ctrl1 = (uint32_t) mask; - uint32_t ctrl2 = (uint32_t) (mask >> 32); - - reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1); - reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2); -} - -/****************************************************************************/ -/** -* @brief Get sticky bits -* -* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getStickyBits(void) -{ - return pChipcHw->Sticky; -} - -/****************************************************************************/ -/** -* @brief Set sticky bits -* -* @return void -* -* @note use chipcHw_REG_STICKY_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_setStickyBits(uint32_t mask) -{ - uint32_t bits = 0; - - REG_LOCAL_IRQ_SAVE; - if (mask & chipcHw_REG_STICKY_POR_BROM) { - bits |= chipcHw_REG_STICKY_POR_BROM; - } else { - uint32_t sticky; - sticky = pChipcHw->Sticky; - - if ((mask & chipcHw_REG_STICKY_BOOT_DONE) - && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { - bits |= chipcHw_REG_STICKY_BOOT_DONE; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_1) - && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) { - bits |= chipcHw_REG_STICKY_GENERAL_1; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_2) - && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) { - bits |= chipcHw_REG_STICKY_GENERAL_2; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_3) - && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) { - bits |= chipcHw_REG_STICKY_GENERAL_3; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_4) - && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) { - bits |= chipcHw_REG_STICKY_GENERAL_4; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_5) - && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) { - bits |= chipcHw_REG_STICKY_GENERAL_5; - } - } - pChipcHw->Sticky = bits; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Clear sticky bits -* -* @return void -* -* @note use chipcHw_REG_STICKY_XXXXXX -*/ -/****************************************************************************/ -static inline void chipcHw_clearStickyBits(uint32_t mask) -{ - uint32_t bits = 0; - - REG_LOCAL_IRQ_SAVE; - if (mask & - (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | - chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | - chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = pChipcHw->Sticky; - - if ((mask & chipcHw_REG_STICKY_BOOT_DONE) - && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { - bits = chipcHw_REG_STICKY_BOOT_DONE; - mask &= ~chipcHw_REG_STICKY_BOOT_DONE; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_1) - && (sticky & chipcHw_REG_STICKY_GENERAL_1)) { - bits |= chipcHw_REG_STICKY_GENERAL_1; - mask &= ~chipcHw_REG_STICKY_GENERAL_1; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_2) - && (sticky & chipcHw_REG_STICKY_GENERAL_2)) { - bits |= chipcHw_REG_STICKY_GENERAL_2; - mask &= ~chipcHw_REG_STICKY_GENERAL_2; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_3) - && (sticky & chipcHw_REG_STICKY_GENERAL_3)) { - bits |= chipcHw_REG_STICKY_GENERAL_3; - mask &= ~chipcHw_REG_STICKY_GENERAL_3; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_4) - && (sticky & chipcHw_REG_STICKY_GENERAL_4)) { - bits |= chipcHw_REG_STICKY_GENERAL_4; - mask &= ~chipcHw_REG_STICKY_GENERAL_4; - } - if ((mask & chipcHw_REG_STICKY_GENERAL_5) - && (sticky & chipcHw_REG_STICKY_GENERAL_5)) { - bits |= chipcHw_REG_STICKY_GENERAL_5; - mask &= ~chipcHw_REG_STICKY_GENERAL_5; - } - } - pChipcHw->Sticky = bits | mask; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Get software strap value -* -* Retrieves software strap value -* -* @return Software strap value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getSoftStraps(void) -{ - return pChipcHw->SoftStraps; -} - -/****************************************************************************/ -/** -* @brief Set software override strap options -* -* set software override strap options -* -* @return nothing -* -*/ -/****************************************************************************/ -static inline void chipcHw_setSoftStraps(uint32_t strapOptions) -{ - reg32_write(&pChipcHw->SoftStraps, strapOptions); -} - -/****************************************************************************/ -/** -* @brief Get Pin Strap Options -* -* This function returns the raw boot strap options -* -* @return strap options -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getPinStraps(void) -{ - return pChipcHw->PinStraps; -} - -/****************************************************************************/ -/** -* @brief Get Valid Strap Options -* -* This function returns the valid raw boot strap options -* -* @return strap options -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getValidStraps(void) -{ - uint32_t softStraps; - - /* - ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps - ** which copies HW straps to soft straps if there is no override - */ - softStraps = chipcHw_getSoftStraps(); - - return softStraps; -} - -/****************************************************************************/ -/** -* @brief Initialize valid pin strap options -* -* Retrieves valid pin strap options by copying HW strap options to soft register -* (if chipcHw_STRAPS_SOFT_OVERRIDE not set) -* -* @return nothing -* -*/ -/****************************************************************************/ -static inline void chipcHw_initValidStraps(void) -{ - uint32_t softStraps; - - REG_LOCAL_IRQ_SAVE; - softStraps = chipcHw_getSoftStraps(); - - if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) { - /* Copy HW straps to software straps */ - chipcHw_setSoftStraps(chipcHw_getPinStraps()); - } - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Get boot device -* -* This function returns the device type used in booting the system -* -* @return Boot device of type chipcHw_BOOT_DEVICE -* -*/ -/****************************************************************************/ -static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void) -{ - return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK; -} - -/****************************************************************************/ -/** -* @brief Get boot mode -* -* This function returns the way the system was booted -* -* @return Boot mode of type chipcHw_BOOT_MODE -* -*/ -/****************************************************************************/ -static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void) -{ - return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK; -} - -/****************************************************************************/ -/** -* @brief Get NAND flash page size -* -* This function returns the NAND device page size -* -* @return Boot NAND device page size -* -*/ -/****************************************************************************/ -static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void) -{ - return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK; -} - -/****************************************************************************/ -/** -* @brief Get NAND flash address cycle configuration -* -* This function returns the NAND flash address cycle configuration -* -* @return 0 = Do not extra address cycle, 1 = Add extra cycle -* -*/ -/****************************************************************************/ -static inline int chipcHw_getNandExtraCycle(void) -{ - if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ -/** -* @brief Activates PIF interface -* -* This function activates PIF interface by taking control of LCD pins -* -* @note -* When activated, LCD pins will be defined as follows for PIF operation -* -* CLD[17:0] = pif_data[17:0] -* CLD[23:18] = pif_address[5:0] -* CLPOWER = pif_wr_str -* CLCP = pif_rd_str -* CLAC = pif_hat1 -* CLFP = pif_hrdy1 -* CLLP = pif_hat2 -* GPIO[42] = pif_hrdy2 -* -* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_activatePifInterface(void) -{ - reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE); -} - -/****************************************************************************/ -/** -* @brief Activates LCD interface -* -* This function activates LCD interface -* -* @note -* When activated, LCD pins will be defined as follows -* -* CLD[17:0] = LCD data -* CLD[23:18] = LCD data -* CLPOWER = LCD power -* CLCP = -* CLAC = LCD ack -* CLFP = -* CLLP = -*/ -/****************************************************************************/ -static inline void chipcHw_activateLcdInterface(void) -{ - reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE); -} - -/****************************************************************************/ -/** -* @brief Deactivates PIF/LCD interface -* -* This function deactivates PIF/LCD interface -* -* @note -* When deactivated LCD pins will be in rti-stated -* -*/ -/****************************************************************************/ -static inline void chipcHw_deactivatePifLcdInterface(void) -{ - reg32_write(&pChipcHw->LcdPifMode, 0); -} - -/****************************************************************************/ -/** -* @brief Select GE2 -* -* This function select GE2 as the graphic engine -* -*/ -/****************************************************************************/ -static inline void chipcHw_selectGE2(void) -{ - reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL); -} - -/****************************************************************************/ -/** -* @brief Select GE3 -* -* This function select GE3 as the graphic engine -* -*/ -/****************************************************************************/ -static inline void chipcHw_selectGE3(void) -{ - reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL); -} - -/****************************************************************************/ -/** -* @brief Get to know the configuration of GPIO pin -* -*/ -/****************************************************************************/ -static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) -{ - return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & - (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin))) >> - chipcHw_REG_GPIO_MUX_POSITION(pin); -} - -/****************************************************************************/ -/** -* @brief Configure GPIO pin function -* -*/ -/****************************************************************************/ -static inline void chipcHw_setGpioPinFunction(int pin, - chipcHw_GPIO_FUNCTION_e func) -{ - REG_LOCAL_IRQ_SAVE; - *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &= - ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin)); - *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |= - func << chipcHw_REG_GPIO_MUX_POSITION(pin); - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set Pin slew rate -* -* This function sets the slew of individual pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinSlewRate(uint32_t pin, - chipcHw_PIN_SLEW_RATE_e slewRate) -{ - REG_LOCAL_IRQ_SAVE; - *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &= - ~(chipcHw_REG_SLEW_RATE_MASK << - chipcHw_REG_SLEW_RATE_POSITION(pin)); - *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |= - (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin); - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set Pin output drive current -* -* This function sets output drive current of individual pin -* -* Note: Avoid the use of the word 'current' since linux headers define this -* to be the current task. -*/ -/****************************************************************************/ -static inline void chipcHw_setPinOutputCurrent(uint32_t pin, - chipcHw_PIN_CURRENT_STRENGTH_e - curr) -{ - REG_LOCAL_IRQ_SAVE; - *((uint32_t *) chipcHw_REG_CURRENT(pin)) &= - ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin)); - *((uint32_t *) chipcHw_REG_CURRENT(pin)) |= - (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin); - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set Pin pullup register -* -* This function sets pullup register of individual pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup) -{ - REG_LOCAL_IRQ_SAVE; - *((uint32_t *) chipcHw_REG_PULLUP(pin)) &= - ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin)); - *((uint32_t *) chipcHw_REG_PULLUP(pin)) |= - (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin); - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set Pin input type -* -* This function sets input type of individual pin -* -*/ -/****************************************************************************/ -static inline void chipcHw_setPinInputType(uint32_t pin, - chipcHw_PIN_INPUTTYPE_e inputType) -{ - REG_LOCAL_IRQ_SAVE; - *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &= - ~(chipcHw_REG_INPUTTYPE_MASK << - chipcHw_REG_INPUTTYPE_POSITION(pin)); - *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |= - (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin); - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Power up the USB PHY -* -* This function powers up the USB PHY -* -*/ -/****************************************************************************/ -static inline void chipcHw_powerUpUsbPhy(void) -{ - reg32_modify_and(&pChipcHw->MiscCtrl, - chipcHw_REG_MISC_CTRL_USB_POWERON); -} - -/****************************************************************************/ -/** -* @brief Power down the USB PHY -* -* This function powers down the USB PHY -* -*/ -/****************************************************************************/ -static inline void chipcHw_powerDownUsbPhy(void) -{ - reg32_modify_or(&pChipcHw->MiscCtrl, - chipcHw_REG_MISC_CTRL_USB_POWEROFF); -} - -/****************************************************************************/ -/** -* @brief Set the 2nd USB as host -* -* This function sets the 2nd USB as host -* -*/ -/****************************************************************************/ -static inline void chipcHw_setUsbHost(void) -{ - reg32_modify_or(&pChipcHw->MiscCtrl, - chipcHw_REG_MISC_CTRL_USB_MODE_HOST); -} - -/****************************************************************************/ -/** -* @brief Set the 2nd USB as device -* -* This function sets the 2nd USB as device -* -*/ -/****************************************************************************/ -static inline void chipcHw_setUsbDevice(void) -{ - reg32_modify_and(&pChipcHw->MiscCtrl, - chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE); -} - -/****************************************************************************/ -/** -* @brief Lower layer function to enable/disable a clock of a certain device -* -* This function enables/disables a core clock -* -*/ -/****************************************************************************/ -static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, - chipcHw_OPTYPE_e type, int mode) -{ - volatile uint32_t *pPLLReg = (uint32_t *) 0x0; - volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; - - switch (clock) { - case chipcHw_CLOCK_DDR: - pPLLReg = &pChipcHw->DDRClock; - break; - case chipcHw_CLOCK_ARM: - pPLLReg = &pChipcHw->ARMClock; - break; - case chipcHw_CLOCK_ESW: - pPLLReg = &pChipcHw->ESWClock; - break; - case chipcHw_CLOCK_VPM: - pPLLReg = &pChipcHw->VPMClock; - break; - case chipcHw_CLOCK_ESW125: - pPLLReg = &pChipcHw->ESW125Clock; - break; - case chipcHw_CLOCK_UART: - pPLLReg = &pChipcHw->UARTClock; - break; - case chipcHw_CLOCK_SDIO0: - pPLLReg = &pChipcHw->SDIO0Clock; - break; - case chipcHw_CLOCK_SDIO1: - pPLLReg = &pChipcHw->SDIO1Clock; - break; - case chipcHw_CLOCK_SPI: - pPLLReg = &pChipcHw->SPIClock; - break; - case chipcHw_CLOCK_ETM: - pPLLReg = &pChipcHw->ETMClock; - break; - case chipcHw_CLOCK_USB: - pPLLReg = &pChipcHw->USBClock; - if (type == chipcHw_OPTYPE_OUTPUT) { - if (mode) { - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } else { - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } - } - break; - case chipcHw_CLOCK_LCD: - pPLLReg = &pChipcHw->LCDClock; - if (type == chipcHw_OPTYPE_OUTPUT) { - if (mode) { - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } else { - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } - } - break; - case chipcHw_CLOCK_APM: - pPLLReg = &pChipcHw->APMClock; - if (type == chipcHw_OPTYPE_OUTPUT) { - if (mode) { - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } else { - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_POWER_DOWN); - } - } - break; - case chipcHw_CLOCK_BUS: - pClockCtrl = &pChipcHw->ACLKClock; - break; - case chipcHw_CLOCK_OTP: - pClockCtrl = &pChipcHw->OTPClock; - break; - case chipcHw_CLOCK_I2C: - pClockCtrl = &pChipcHw->I2CClock; - break; - case chipcHw_CLOCK_I2S0: - pClockCtrl = &pChipcHw->I2S0Clock; - break; - case chipcHw_CLOCK_RTBUS: - pClockCtrl = &pChipcHw->RTBUSClock; - break; - case chipcHw_CLOCK_APM100: - pClockCtrl = &pChipcHw->APM100Clock; - break; - case chipcHw_CLOCK_TSC: - pClockCtrl = &pChipcHw->TSCClock; - break; - case chipcHw_CLOCK_LED: - pClockCtrl = &pChipcHw->LEDClock; - break; - case chipcHw_CLOCK_I2S1: - pClockCtrl = &pChipcHw->I2S1Clock; - break; - } - - if (pPLLReg) { - switch (type) { - case chipcHw_OPTYPE_OUTPUT: - /* PLL clock output enable/disable */ - if (mode) { - if (clock == chipcHw_CLOCK_DDR) { - /* DDR clock enable is inverted */ - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); - } else { - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); - } - } else { - if (clock == chipcHw_CLOCK_DDR) { - /* DDR clock disable is inverted */ - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); - } else { - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); - } - } - break; - case chipcHw_OPTYPE_BYPASS: - /* PLL clock bypass enable/disable */ - if (mode) { - reg32_modify_or(pPLLReg, - chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); - } else { - reg32_modify_and(pPLLReg, - ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); - } - break; - } - } else if (pClockCtrl) { - switch (type) { - case chipcHw_OPTYPE_OUTPUT: - if (mode) { - reg32_modify_or(pClockCtrl, - chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE); - } else { - reg32_modify_and(pClockCtrl, - ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE); - } - break; - case chipcHw_OPTYPE_BYPASS: - if (mode) { - reg32_modify_or(pClockCtrl, - chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); - } else { - reg32_modify_and(pClockCtrl, - ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); - } - break; - } - } -} - -/****************************************************************************/ -/** -* @brief Disables a core clock of a certain device -* -* This function disables a core clock -* -* @note no change in power consumption -*/ -/****************************************************************************/ -static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock) -{ - - /* Disable output of the clock */ - chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0); -} - -/****************************************************************************/ -/** -* @brief Enable a core clock of a certain device -* -* This function enables a core clock -* -* @note no change in power consumption -*/ -/****************************************************************************/ -static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock) -{ - - /* Enable output of the clock */ - chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1); -} - -/****************************************************************************/ -/** -* @brief Enables bypass clock of a certain device -* -* This function enables bypass clock -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock) -{ - /* Enable bypass clock */ - chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1); -} - -/****************************************************************************/ -/** -* @brief Disabled bypass clock of a certain device -* -* This function disables bypass clock -* -* @note Doesnot affect the bus interface clock -*/ -/****************************************************************************/ -static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) -{ - /* Disable bypass clock */ - chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0); - -} - -/****************************************************************************/ -/** @brief Checks if software strap is enabled - * - * @return 1 : When enable - * 0 : When disable - */ -/****************************************************************************/ -static inline int chipcHw_isSoftwareStrapsEnable(void) -{ - return pChipcHw->SoftStraps & 0x00000001; -} - -/****************************************************************************/ -/** @brief Enable software strap - */ -/****************************************************************************/ -static inline void chipcHw_softwareStrapsEnable(void) -{ - reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001); -} - -/****************************************************************************/ -/** @brief Disable software strap - */ -/****************************************************************************/ -static inline void chipcHw_softwareStrapsDisable(void) -{ - reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001)); -} - -/****************************************************************************/ -/** @brief PLL test enable - */ -/****************************************************************************/ -static inline void chipcHw_pllTestEnable(void) -{ - reg32_modify_or(&pChipcHw->PLLConfig, - chipcHw_REG_PLL_CONFIG_TEST_ENABLE); -} - -/****************************************************************************/ -/** @brief PLL2 test enable - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestEnable(void) -{ - reg32_modify_or(&pChipcHw->PLLConfig2, - chipcHw_REG_PLL_CONFIG_TEST_ENABLE); -} - -/****************************************************************************/ -/** @brief PLL test disable - */ -/****************************************************************************/ -static inline void chipcHw_pllTestDisable(void) -{ - reg32_modify_and(&pChipcHw->PLLConfig, - ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE); -} - -/****************************************************************************/ -/** @brief PLL2 test disable - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestDisable(void) -{ - reg32_modify_and(&pChipcHw->PLLConfig2, - ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE); -} - -/****************************************************************************/ -/** @brief Get PLL test status - */ -/****************************************************************************/ -static inline int chipcHw_isPllTestEnable(void) -{ - return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; -} - -/****************************************************************************/ -/** @brief Get PLL2 test status - */ -/****************************************************************************/ -static inline int chipcHw_isPll2TestEnable(void) -{ - return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; -} - -/****************************************************************************/ -/** @brief PLL test select - */ -/****************************************************************************/ -static inline void chipcHw_pllTestSelect(uint32_t val) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK; - pChipcHw->PLLConfig |= - (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** @brief PLL2 test select - */ -/****************************************************************************/ -static inline void chipcHw_pll2TestSelect(uint32_t val) -{ - - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK; - pChipcHw->PLLConfig2 |= - (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** @brief Get PLL test selected option - */ -/****************************************************************************/ -static inline uint8_t chipcHw_getPllTestSelected(void) -{ - return (uint8_t) ((pChipcHw-> - PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) - >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); -} - -/****************************************************************************/ -/** @brief Get PLL2 test selected option - */ -/****************************************************************************/ -static inline uint8_t chipcHw_getPll2TestSelected(void) -{ - return (uint8_t) ((pChipcHw-> - PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) - >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); -} - -/****************************************************************************/ -/** -* @brief Disable the PLL1 -* -*/ -/****************************************************************************/ -static inline void chipcHw_pll1Disable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disable the PLL2 -* -*/ -/****************************************************************************/ -static inline void chipcHw_pll2Disable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Enables DDR SW phase alignment interrupt -*/ -/****************************************************************************/ -static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disables DDR SW phase alignment interrupt -*/ -/****************************************************************************/ -static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set VPM SW phase alignment interrupt mode -* -* This function sets VPM phase alignment interrupt -*/ -/****************************************************************************/ -static inline void -chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode) -{ - REG_LOCAL_IRQ_SAVE; - if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) { - pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; - } else { - pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; - } - pChipcHw->VPMPhaseCtrl2 = - (pChipcHw-> - VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK << - chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Enable DDR phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrSwPhaseAlignEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disable DDR phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrSwPhaseAlignDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Enable DDR phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disable DDR phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Enable VPM phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmSwPhaseAlignEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disable VPM phase alignment in software -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmSwPhaseAlignDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Enable VPM phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Disable VPM phase alignment in hardware -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Set DDR phase alignment margin in hardware -* -*/ -/****************************************************************************/ -static inline void -chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin) -{ - uint32_t ge = 0; - uint32_t le = 0; - - switch (margin) { - case chipcHw_DDR_HW_PHASE_MARGIN_STRICT: - ge = 0x0F; - le = 0x0F; - break; - case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM: - ge = 0x03; - le = 0x3F; - break; - case chipcHw_DDR_HW_PHASE_MARGIN_WIDE: - ge = 0x01; - le = 0x7F; - break; - } - - { - REG_LOCAL_IRQ_SAVE; - - pChipcHw->DDRPhaseCtrl1 &= - ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK << - chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT) - || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK << - chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT)); - - pChipcHw->DDRPhaseCtrl1 |= - ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT) - || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT)); - - REG_LOCAL_IRQ_RESTORE; - } -} - -/****************************************************************************/ -/** -* @brief Set VPM phase alignment margin in hardware -* -*/ -/****************************************************************************/ -static inline void -chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) -{ - uint32_t ge = 0; - uint32_t le = 0; - - switch (margin) { - case chipcHw_VPM_HW_PHASE_MARGIN_STRICT: - ge = 0x0F; - le = 0x0F; - break; - case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM: - ge = 0x03; - le = 0x3F; - break; - case chipcHw_VPM_HW_PHASE_MARGIN_WIDE: - ge = 0x01; - le = 0x7F; - break; - } - - { - REG_LOCAL_IRQ_SAVE; - - pChipcHw->VPMPhaseCtrl1 &= - ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK << - chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT) - || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK << - chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT)); - - pChipcHw->VPMPhaseCtrl1 |= - ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT) - || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT)); - - REG_LOCAL_IRQ_RESTORE; - } -} - -/****************************************************************************/ -/** -* @brief Checks DDR phase aligned status done by HW -* -* @return 1: When aligned -* 0: When not aligned -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; -} - -/****************************************************************************/ -/** -* @brief Checks VPM phase aligned status done by HW -* -* @return 1: When aligned -* 0: When not aligned -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; -} - -/****************************************************************************/ -/** -* @brief Get DDR phase aligned status done by HW -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> - chipcHw_REG_DDR_PHASE_STATUS_SHIFT; -} - -/****************************************************************************/ -/** -* @brief Get VPM phase aligned status done by HW -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> - chipcHw_REG_VPM_PHASE_STATUS_SHIFT; -} - -/****************************************************************************/ -/** -* @brief Get DDR phase control value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getDdrPhaseControl(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> - chipcHw_REG_DDR_PHASE_CTRL_SHIFT; -} - -/****************************************************************************/ -/** -* @brief Get VPM phase control value -* -*/ -/****************************************************************************/ -static inline uint32_t chipcHw_getVpmPhaseControl(void) -{ - return (pChipcHw-> - PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> - chipcHw_REG_VPM_PHASE_CTRL_SHIFT; -} - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout count -* -* @note If HW fails to perform the phase alignment, it will trigger -* a DDR phase alignment timeout interrupt. -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl2 &= - ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK << - chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT); - pChipcHw->DDRPhaseCtrl2 |= - (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) << - chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout count -* -* @note If HW fails to perform the phase alignment, it will trigger -* a VPM phase alignment timeout interrupt. -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl2 &= - ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK << - chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT); - pChipcHw->VPMPhaseCtrl2 |= - (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) << - chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Clear DDR phase alignment timeout interrupt -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void) -{ - REG_LOCAL_IRQ_SAVE; - /* Clear timeout interrupt service bit */ - pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED; - pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief Clear VPM phase alignment timeout interrupt -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void) -{ - REG_LOCAL_IRQ_SAVE; - /* Clear timeout interrupt service bit */ - pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED; - pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout interrupt enable -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */ - /* Enable timeout interrupt */ - pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout interrupt enable -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void) -{ - REG_LOCAL_IRQ_SAVE; - chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */ - /* Enable timeout interrupt */ - pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief DDR phase alignment timeout interrupt disable -* -*/ -/****************************************************************************/ -static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -/****************************************************************************/ -/** -* @brief VPM phase alignment timeout interrupt disable -* -*/ -/****************************************************************************/ -static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void) -{ - REG_LOCAL_IRQ_SAVE; - pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE; - REG_LOCAL_IRQ_RESTORE; -} - -#endif /* CHIPC_INLINE_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h deleted file mode 100644 index b162448f613c..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ /dev/null @@ -1,530 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file chipcHw_reg.h -* -* @brief Definitions for low level chip control registers -* -*/ -/****************************************************************************/ -#ifndef CHIPCHW_REG_H -#define CHIPCHW_REG_H - -#include <mach/csp/mm_io.h> -#include <csp/reg.h> -#include <mach/csp/ddrcReg.h> - -#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC - -typedef struct { - uint32_t ChipId; /* Chip ID */ - uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ - uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */ - uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */ - uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */ - uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */ - uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */ - uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */ - uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */ - uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */ - uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */ - - uint32_t ACLKClock; /* ACLK Clock (Divider) */ - uint32_t OTPClock; /* OTP Clock (Divider) */ - uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */ - uint32_t I2S0Clock; /* I2S0 Clock (Divider) */ - uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */ - uint32_t pad1; - uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */ - uint32_t TSCClock; /* TSC Clock (Divider) */ - uint32_t LEDClock; /* LED Clock (Divider) */ - - uint32_t USBClock; /* PLL2 Channel 1 for USB clock */ - uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */ - uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */ - - uint32_t BusIntfClock; /* Bus interface clock */ - - uint32_t PLLStatus; /* PLL status register (PLL1) */ - uint32_t PLLConfig; /* PLL configuration register (PLL1) */ - uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */ - uint32_t PLLDivider; /* PLL divider control register (PLL1) */ - uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */ - uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */ - - uint32_t I2S1Clock; /* I2S1 Clock */ - uint32_t AudioEnable; /* Enable/ disable audio channel */ - uint32_t SoftReset1; /* Reset blocks */ - uint32_t SoftReset2; /* Reset blocks */ - uint32_t Spare1; /* Phase align interrupts */ - uint32_t Sticky; /* Sticky bits */ - uint32_t MiscCtrl; /* Misc. control */ - uint32_t pad3[3]; - - uint32_t PLLStatus2; /* PLL status register (PLL2) */ - uint32_t PLLConfig2; /* PLL configuration register (PLL2) */ - uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */ - uint32_t PLLDivider2; /* PLL divider control register (PLL2) */ - uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */ - uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */ - - uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */ - uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */ - uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */ - uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */ - uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */ - uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */ - uint32_t pad4[9]; - - uint32_t SoftOTP1; /* Software OTP control */ - uint32_t SoftOTP2; /* Software OTP control */ - uint32_t SoftStraps; /* Software strap */ - uint32_t PinStraps; /* Pin Straps */ - uint32_t DiffOscCtrl; /* Diff oscillator control */ - uint32_t DiagsCtrl; /* Diagnostic control */ - uint32_t DiagsOutputCtrl; /* Diagnostic output enable */ - uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */ - - uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */ - - uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */ - uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */ - uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */ - uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */ - uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */ - uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */ - uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */ - uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */ - - uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */ - uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */ - uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */ - uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */ - uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */ - uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */ - uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */ - uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */ - uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */ - uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */ - - uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */ - uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */ - uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */ - uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */ - uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */ - - uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */ - uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */ - uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ -} chipcHw_REG_t; - -#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) - -#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 -#define chipcHw_REG_CHIPID_BASE_SHIFT 12 -#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF -#define chipcHw_REG_REV_A0 0xA00 -#define chipcHw_REG_REV_B0 0x0B0 - -#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */ -#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */ -#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */ -#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */ -#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */ -#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */ -#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */ -#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */ -#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */ -#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */ -#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */ -#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */ -#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17 - -#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */ -#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */ -#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */ -#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */ -#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */ -#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */ -#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */ -#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */ -#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */ -#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */ -#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask - - 00000000 = divide-by-256 - 00000001 = divide-by-1 - 00000010 = divide-by-2 - 00000011 = divide-by-3 - 00000100 = divide-by-4 - 00000101 = divide-by-5 - 00000110 = divide-by-6 - . - . - 11111011 = divide-by-251 - 11111100 = divide-by-252 - 11111101 = divide-by-253 - 11111110 = divide-by-254 - */ - -#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */ -#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */ -#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */ -#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */ -#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */ - -#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0 -#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4 -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8 -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00 -#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000 -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */ -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */ -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */ -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */ -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */ -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */ - -#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz) -#define chipcHw_REG_PLL_PREDIVIDER_P1 1 -#define chipcHw_REG_PLL_PREDIVIDER_P2 1 - -#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000 -#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */ - -#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */ - -#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f / - chipcHw_REG_PLL_DIVIDER_FRAC - = 0, when SS is disable - */ - -#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz))) - -#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3 - -/* System booting strap options */ -#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */ - -#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */ -#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */ -#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */ -#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */ -#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */ -#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */ - -/* System boot option */ -#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */ -#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */ -#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */ - -/* NAND Flash page size strap options */ -#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */ -#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */ -#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */ -#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */ -#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */ - -#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */ -#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */ - -/* Secure boot mode strap options */ -#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */ -#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */ -#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */ -#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */ -#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */ - -/* Slave Mode straps */ -#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */ -#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */ - -/* Strap pin options */ -#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10) - -/* PIF/LCD pin sharing defines */ -#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */ -#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */ - -#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */ - -/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */ -#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */ -#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */ -#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */ -#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */ -#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */ -#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */ -#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */ -#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */ -#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */ -#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */ -#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */ -#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */ -#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */ -#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */ -#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3)) -#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2) -#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */ - -#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */ -#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */ - /* Pins beyond 42 are defined by skipping 8 bits within the register */ -#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) -#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) -#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */ - -#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */ -#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */ -#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */ -#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */ -#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */ -#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */ -#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */ - /* Pins beyond 42 are defined by skipping 8 bits */ -#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) -#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) - -#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */ -#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */ -#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */ -#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */ - /* Pins beyond 42 are defined by skipping 4 bits */ -#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4))) -#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1)) - -#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */ -#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */ -#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */ - /* Pins beyond 42 are defined by skipping 2 bits */ -#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5))) -#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F))) - -/* Device connected to the bus clock */ -#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */ -#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */ -#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */ -#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */ -#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */ -#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */ -#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */ -#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */ -#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */ -#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */ -#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */ -#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */ -#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */ -#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */ -#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */ -#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */ -#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */ -#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */ -#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */ -#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */ -#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */ -#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */ -#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */ -#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */ -#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */ -#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */ -#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */ -#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */ -#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */ -#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */ -#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */ -#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */ - -/* Software resets defines */ -#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */ -#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */ -#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */ -#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */ -#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */ -#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */ -#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */ -#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */ -#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */ -#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */ -#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */ -#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */ -#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */ -#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */ -#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */ -#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */ -#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */ -#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */ -#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */ -#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */ -#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */ -#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */ -#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */ -#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */ -#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */ -#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */ -#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */ -#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */ -#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */ -#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */ -#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */ -#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */ -#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */ -#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */ -#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */ -#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */ -#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */ -#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */ -#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */ -#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */ -#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */ -#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */ -#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */ -#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */ -#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */ - -#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */ -#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */ -#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */ -#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */ - -/* Audio channel control defines */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */ -#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */ - -/* Misc. chip control defines */ -#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */ -#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */ -#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */ -#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */ -#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */ -#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */ -#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */ -#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */ -#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */ -#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */ -#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */ -#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */ - -/* OTP configuration defines */ -#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */ -#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */ -#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */ -#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */ -#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */ -#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */ -#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */ -#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */ -#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */ -#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */ -#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */ -#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */ -#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */ -#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */ -#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */ -#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */ -#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */ -#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */ -#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */ -#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */ -#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */ -#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */ -#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */ - -/* Sticky bit defines */ -#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */ -#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */ -#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */ -#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */ -#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */ -#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */ -#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */ -#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */ -#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */ -#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */ -#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */ -#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */ -#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */ - - /* HW phase alignment defines *//* Spare1 register definitions */ -#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */ -#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */ -#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */ -#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */ - /* DDRPhaseCtrl1 register definitions */ -#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */ -#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */ -#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */ -#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23 -#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */ -#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16 -#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */ -#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 - /* VPMPhaseCtrl1 register definitions */ -#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */ -#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */ -#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */ -#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23 -#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */ -#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16 -#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */ -#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 - /* PhaseAlignStatus register definitions */ -#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */ -#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */ -#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24 -#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */ -#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */ -#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */ -#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16 -#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */ -#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */ -#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8 -#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */ -#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */ -#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */ -#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0 - /* DDRPhaseCtrl2 register definitions */ -#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ -#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ -#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ -#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20 -#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */ -#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 -#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */ -#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0 - /* VPMPhaseCtrl2 register definitions */ -#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */ -#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26 -#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000 -#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) -#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) -#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) -#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ -#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ -#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ -#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20 -#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */ -#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 -#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */ -#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0 - -#endif /* CHIPCHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h deleted file mode 100644 index f1b68e26fa6d..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ /dev/null @@ -1,872 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file ddrcReg.h -* -* @brief Register definitions for BCMRING DDR2 Controller and PHY -* -*/ -/****************************************************************************/ - -#ifndef DDRC_REG_H -#define DDRC_REG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* ---- Include Files ---------------------------------------------------- */ - -#include <csp/reg.h> -#include <csp/stdint.h> - -#include <mach/csp/mm_io.h> - -/* ---- Public Constants and Types --------------------------------------- */ - -/*********************************************************************/ -/* DDR2 Controller (ARM PL341) register definitions */ -/*********************************************************************/ - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* ARM PL341 DDR2 configuration registers, offset 0x000 */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - - typedef struct { - uint32_t memcStatus; - uint32_t memcCmd; - uint32_t directCmd; - uint32_t memoryCfg; - uint32_t refreshPrd; - uint32_t casLatency; - uint32_t writeLatency; - uint32_t tMrd; - uint32_t tRas; - uint32_t tRc; - uint32_t tRcd; - uint32_t tRfc; - uint32_t tRp; - uint32_t tRrd; - uint32_t tWr; - uint32_t tWtr; - uint32_t tXp; - uint32_t tXsr; - uint32_t tEsr; - uint32_t memoryCfg2; - uint32_t memoryCfg3; - uint32_t tFaw; - } ddrcReg_CTLR_MEMC_REG_t; - -#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000 -#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET)) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12) -#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12) -#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12) - -#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10) -#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10) -#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10) -#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10) -#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10) - -#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7) -#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7) -#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7) -#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7) -#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7) - -#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4) -#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4) - -#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2) -#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2) -#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2) -#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2) -#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2) - -#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0) -#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0) -#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0) -#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0) -#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0) -#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0) -#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0) -#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0) -#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0) -#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0) -#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20 -#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT) - -#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18) -#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18) -#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18) -#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18) - -#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16 -#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT) - -#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0 -#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21) -#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21) -#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21) -#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21) -#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21) - -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18) -#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18) - -#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15) -#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15) -#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */ - -#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13) - -#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7 -#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT) - -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3) - -#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0) -#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0 -#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1 -#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0 -#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_MRD_SHIFT 0 -#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RAS_SHIFT 0 -#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RC_SHIFT 0 -#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8 -#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT) - -#define ddrcReg_CTLR_T_RCD_SHIFT 0 -#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8 -#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT) - -#define ddrcReg_CTLR_T_RFC_SHIFT 0 -#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8 -#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT) - -#define ddrcReg_CTLR_T_RP_SHIFT 0 -#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_RRD_SHIFT 0 -#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_WR_SHIFT 0 -#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_WTR_SHIFT 0 -#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_XP_SHIFT 0 -#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_XSR_SHIFT 0 -#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_ESR_SHIFT 0 -#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6) -#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6) -#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6) -#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6) - -#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4) -#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4) -#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4) - -#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3) -#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3) - -#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2) -#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2) - -#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0) -#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0) -#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0) -#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0 -#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8 -#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT) - -#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0 -#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT) - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - -#define ddrcReg_CTLR_QOS_CNT 16 -#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1) - - typedef struct { - uint32_t cfg[ddrcReg_CTLR_QOS_CNT]; - } ddrcReg_CTLR_QOS_REG_t; - -#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100 -#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET)) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2 -#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT) - -#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1 -#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT) - -#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0) - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* ARM PL341 Memory chip configuration registers, offset 0x200 */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - -#define ddrcReg_CTLR_CHIP_CNT 4 -#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1) - - typedef struct { - uint32_t cfg[ddrcReg_CTLR_CHIP_CNT]; - } ddrcReg_CTLR_CHIP_REG_t; - -#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200 -#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET)) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16) -#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16) -#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16) - -#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8 -#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT) - -#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0 -#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT) - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* ARM PL341 User configuration registers, offset 0x300 */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - -#define ddrcReg_CTLR_USER_OUTPUT_CNT 2 - - typedef struct { - uint32_t input; - uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT]; - uint32_t feature; - } ddrcReg_CTLR_USER_REG_t; - -#define ddrcReg_CTLR_USER_REG_OFFSET 0x300 -#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET)) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0 -#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0 -#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT) - -#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1 -#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 - -/* ----------------------------------------------------- */ - -#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2) -#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0) - -/*********************************************************************/ -/* Broadcom DDR23 PHY register definitions */ -/*********************************************************************/ - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* Broadcom DDR23 PHY Address and Control register definitions */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - - typedef struct { - uint32_t revision; - uint32_t pmCtl; - REG32_RSVD(0x0008, 0x0010); - uint32_t pllStatus; - uint32_t pllCfg; - uint32_t pllPreDiv; - uint32_t pllDiv; - uint32_t pllCtl1; - uint32_t pllCtl2; - uint32_t ssCtl; - uint32_t ssCfg; - uint32_t vdlStatic; - uint32_t vdlDynamic; - uint32_t padIdle; - uint32_t pvtComp; - uint32_t padDrive; - uint32_t clkRgltrCtl; - } ddrcReg_PHY_ADDR_CTL_REG_t; - -#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) - -/* @todo These SS definitions are duplicates of ones below */ - -#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001 -#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000 -#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16 -#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */ -#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF -#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0 - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8 -#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17 -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12 -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2) -#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26) -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25) - -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20 -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8 -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4 -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24 -#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT) - -/* ----------------------------------------------------- */ -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2 -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1) -#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16 -#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20) -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16) - -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12 -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8 -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16) - -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12 -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8 -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1) -#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25) -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT) - -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0 -#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4) -#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3) -#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2) -#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1) -#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1) -#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0) - -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ -/* Broadcom DDR23 PHY Byte Lane register definitions */ -/* -------------------------------------------------------------------- */ -/* -------------------------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_CNT 2 -#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1) - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8 - - typedef struct { - uint32_t revision; - uint32_t vdlCalibrate; - uint32_t vdlStatus; - REG32_RSVD(0x000c, 0x0010); - uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT]; - uint32_t readCtl; - uint32_t readStatus; - uint32_t readClear; - uint32_t padIdleCtl; - uint32_t padDriveCtl; - uint32_t padClkCtl; - uint32_t writeCtl; - uint32_t clkRegCtl; - } ddrcReg_PHY_BYTE_LANE_REG_t; - -/* There are 2 instances of the byte Lane registers, one for each byte lane. */ -#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500 -#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600 - -#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET)) -#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET)) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8 -#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0 -#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4) -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4) - -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3) -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2) -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0) - -/* ----------------------------------------------------- */ - -/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */ -/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */ -/* register. The fine rise and fall are no longer used, so add some definitions for just */ -/* the step setting to simplify things. */ - -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8 -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4 -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16) - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6 -#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7 - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8 -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT) - -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3) -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2) -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0 -#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5) -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4) -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3) -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2) -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0) - -/* ----------------------------------------------------- */ - -#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1) -#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0) - -/*********************************************************************/ -/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */ -/*********************************************************************/ - - typedef struct { - uint32_t cfg; - uint32_t actMonCnt; - uint32_t ctl; - uint32_t lbistCtl; - uint32_t lbistSeed; - uint32_t lbistStatus; - uint32_t tieOff; - uint32_t actMonClear; - uint32_t status; - uint32_t user; - } ddrcReg_CTLR_PHY_GLUE_REG_t; - -#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700 -#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET)) - -/* ----------------------------------------------------- */ - -/* DDR2 / AXI block phase alignment interrupt control */ -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18 -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17 -#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16 -#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW - -#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15 -#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 - -/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */ -/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */ -/* controller. If 2 chips selects are being used, then software control must be enabled. */ -#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14) -#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13) - -/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */ -#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12) -#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11) -#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10) - -/* Chip select count */ -#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9 -#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8 -#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7 -#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6 -#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT) -#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT) - -#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0 -#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT) - -/* ----------------------------------------------------- */ -#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0 -#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT) - -/* ---- Public Function Prototypes --------------------------------------- */ - -#ifdef __cplusplus -} /* end extern "C" */ -#endif -#endif /* DDRC_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h deleted file mode 100644 index d67e2f8c22de..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ /dev/null @@ -1,145 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw_priv.h -* -* @brief Private Definitions for low level DMA driver -* -*/ -/****************************************************************************/ - -#ifndef _DMACHW_PRIV_H -#define _DMACHW_PRIV_H - -#include <csp/stdint.h> - -/* Data type for DMA Link List Item */ -typedef struct { - uint32_t sar; /* Source Address Register. - Address must be aligned to CTLx.SRC_TR_WIDTH. */ - uint32_t dar; /* Destination Address Register. - Address must be aligned to CTLx.DST_TR_WIDTH. */ - uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists. - Address MUST be aligned to a 32-bit boundary. */ - dmacHw_REG64_t ctl; /* Control Register. 64 bits */ - uint32_t sstat; /* Source Status Register */ - uint32_t dstat; /* Destination Status Register */ - uint32_t devCtl; /* Device specific control information */ - uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */ -} dmacHw_DESC_t; - -/* - * Descriptor ring pointers - */ -typedef struct { - int num; /* Number of link items */ - dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */ - dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */ - dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */ - dmacHw_DESC_t *pEnd; /* End of current descriptor chain */ - dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */ - uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */ -} dmacHw_DESC_RING_t; - -/* - * DMA channel control block - */ -typedef struct { - uint32_t module; /* DMA controller module (0-1) */ - uint32_t channel; /* DMA channel (0-7) */ - volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */ - volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */ - void *userData; /* Channel specifc user data */ -} dmacHw_CBLK_t; - -#define dmacHw_ASSERT(a) if (!(a)) while (1) -#define dmacHw_MAX_CHANNEL_COUNT 16 -#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF -#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE -#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF) -#define dmacHw_MAX_BLOCKSIZE 4064 -#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr) -#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1) -#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp) -#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle)) -#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp)) -#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0 - -/****************************************************************************/ -/** -* @brief Get next available transaction width -* -* -* @return On success : Next available transaction width -* On failure : dmacHw_TRANSACTION_WIDTH_8 -* -* @note -* None -*/ -/****************************************************************************/ -static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */ - ) { - if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) { - return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) - - 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT; - } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) { - return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) - - 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT; - } - - /* Default return */ - return dmacHw_SRC_TRANSACTION_WIDTH_8; -} - -/****************************************************************************/ -/** -* @brief Get number of bytes per transaction -* -* @return Number of bytes per transaction -* -* -* @note -* None -*/ -/****************************************************************************/ -static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */ - ) { - int width = 1; - switch (tw) { - case dmacHw_SRC_TRANSACTION_WIDTH_8: - width = 1; - break; - case dmacHw_SRC_TRANSACTION_WIDTH_16: - case dmacHw_DST_TRANSACTION_WIDTH_16: - width = 2; - break; - case dmacHw_SRC_TRANSACTION_WIDTH_32: - case dmacHw_DST_TRANSACTION_WIDTH_32: - width = 4; - break; - case dmacHw_SRC_TRANSACTION_WIDTH_64: - case dmacHw_DST_TRANSACTION_WIDTH_64: - width = 8; - break; - default: - dmacHw_ASSERT(0); - } - - /* Default transaction width */ - return width; -} - -#endif /* _DMACHW_PRIV_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h deleted file mode 100644 index f1ecf96f2da5..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ /dev/null @@ -1,406 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dmacHw_reg.h -* -* @brief Definitions for low level DMA registers -* -*/ -/****************************************************************************/ - -#ifndef _DMACHW_REG_H -#define _DMACHW_REG_H - -#include <csp/stdint.h> -#include <mach/csp/mm_io.h> - -/* Data type for 64 bit little endian register */ -typedef struct { - volatile uint32_t lo; /* Lower 32 bit in little endian mode */ - volatile uint32_t hi; /* Upper 32 bit in little endian mode */ -} dmacHw_REG64_t; - -/* Data type representing DMA channel registers */ -typedef struct { - dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved) - Address must be aligned to CTLx.SRC_TR_WIDTH. - */ - dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved) - Address must be aligned to CTLx.DST_TR_WIDTH. - */ - dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved) - LLP contains the pointer to the next LLI for block chaining using linked lists. - If LLPis set to 0x0, then transfers using linked lists are not enabled. - Address MUST be aligned to a 32-bit boundary. - */ - dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */ - dmacHw_REG64_t ChannelSstat; /* Source Status Register */ - dmacHw_REG64_t ChannelDstat; /* Destination Status Register */ - dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */ - dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */ - dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */ - dmacHw_REG64_t SrcGather; /* Source gather register */ - dmacHw_REG64_t DstScatter; /* Destination scatter register */ -} dmacHw_CH_REG_t; - -/* Data type for RAW interrupt status registers */ -typedef struct { - dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */ - dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */ - dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */ - dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */ - dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */ -} dmacHw_INT_RAW_t; - -/* Data type for interrupt status registers */ -typedef struct { - dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */ - dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */ - dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */ - dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */ - dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */ -} dmacHw_INT_STATUS_t; - -/* Data type for interrupt mask registers*/ -typedef struct { - dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */ - dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */ - dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */ - dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */ - dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */ -} dmacHw_INT_MASK_t; - -/* Data type for interrupt clear registers */ -typedef struct { - dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */ - dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */ - dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */ - dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */ - dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */ - dmacHw_REG64_t StatusInt; /* Status for each interrupt type */ -} dmacHw_INT_CLEAR_t; - -/* Data type for software handshaking registers */ -typedef struct { - dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */ - dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */ - dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */ - dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */ - dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */ - dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */ -} dmacHw_SW_HANDSHAKE_t; - -/* Data type for misc. registers */ -typedef struct { - dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */ - dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */ - dmacHw_REG64_t DmaIdReg; /* DMA ID Register */ - dmacHw_REG64_t DmaTestReg; /* DMA Test Register */ - dmacHw_REG64_t Reserved0; /* Reserved */ - dmacHw_REG64_t Reserved1; /* Reserved */ - dmacHw_REG64_t CompParm6; /* Component Parameter 6 */ - dmacHw_REG64_t CompParm5; /* Component Parameter 5 */ - dmacHw_REG64_t CompParm4; /* Component Parameter 4 */ - dmacHw_REG64_t CompParm3; /* Component Parameter 3 */ - dmacHw_REG64_t CompParm2; /* Component Parameter 2 */ - dmacHw_REG64_t CompParm1; /* Component Parameter 1 */ - dmacHw_REG64_t CompId; /* Compoent ID */ -} dmacHw_MISC_t; - -/* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ - -extern uint32_t dmaChannelCount_0; -extern uint32_t dmaChannelCount_1; - -/* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) - -/* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) - -/* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) - -/* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) - -/* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) - -/* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) - -/* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) - -/* Channel control registers */ -#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) -#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo) -#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo) - -#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo) -#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi) - -#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo) -#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo) -#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo) -#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo) - -#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo) -#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi) - -#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo) -#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi) - -#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo) -#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi) - -#define INT_STATUS_MASK(channel) (0x00000001 << (channel)) -#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel))) - -/* Bit mask for REG_DMACx_CTL_LO */ - -#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */ - -#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */ -#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1 -#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */ -#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */ -#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */ -#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */ - -#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */ -#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4 -#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */ -#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */ -#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */ -#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */ - -#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */ -#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */ - -#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */ -#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */ -#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */ -#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */ - -#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */ -#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */ -#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */ -#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */ - -#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */ -#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */ -#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */ -#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */ -#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */ - -#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */ -#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */ -#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */ -#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */ -#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */ - -#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */ -#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */ -#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */ -#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */ -#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */ -#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */ -#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */ -#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */ -#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */ - -#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */ -#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */ -#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */ - -#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */ -#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */ -#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */ - -#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */ -#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */ - -/* Bit mask for REG_DMACx_CTL_HI */ -#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */ -#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */ - -/* Bit mask for REG_DMACx_CFG_LO */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */ -#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */ - -#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */ -#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */ -#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */ -#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */ - -#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */ -#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */ -#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */ -#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */ -#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */ - -#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */ -#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */ -#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */ -#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */ -#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */ - -#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */ -#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */ - -#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */ - -#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */ -#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */ - -/* Bit mask for REG_DMACx_CFG_HI */ -#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */ -#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */ - -#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */ -#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */ -#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */ -#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */ - -#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */ -#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */ - -#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */ -#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */ - -/* DMA Configuration Parameters */ -#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */ -#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */ -#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */ -#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */ - -/* Define GET/SET macros to program the registers */ -#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr)) -#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr)) -#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr)) - -#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel))) -#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel))) - -#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr)) -#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr)) - -#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl)) -#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0) -#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel))) - -#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl)) -#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0) -#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel))) - -#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK) -#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE) - -#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg)) -#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0) -#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel))) -#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) -#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio)) -#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect)) - -#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg)) -#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0) -#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel))) -#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) -#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK) -#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) -#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK) - -#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) -#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8))) -#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1) -#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0) - -#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) -#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) -#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) - -#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8))) -#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8))) -#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8))) -#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8))) -#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8))) - -#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel))) -#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel))) -#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel))) - -#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1) -#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1) -#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE) -#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13) - -#endif /* _DMACHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h deleted file mode 100644 index cfa91bed9d34..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - - -#ifndef CSP_HW_CFG_H -#define CSP_HW_CFG_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include <cfg_global.h> -#include <mach/csp/cap_inline.h> - -#if defined(__KERNEL__) -#include <mach/memory_settings.h> -#else -#include <hw_cfg.h> -#endif - -/* Some items that can be defined externally, but will be set to default values */ -/* if they are not defined. */ -/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */ -/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ -/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ -/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ -/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ -/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */ -/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */ - -#if defined(CFG_GLOBAL_CHIP) - #if (CFG_GLOBAL_CHIP == FPGA11107) - #define HW_CFG_BUS_CLK_HZ 5000000 - #define HW_CFG_DDR_CTLR_CLK_HZ 10000000 - #define HW_CFG_DDR_PHY_OMIT - #define HW_CFG_UART_CLK_HZ 7500000 - #else - #define HW_CFG_PLL_VCO_HZ 2000000000 - #define HW_CFG_PLL2_VCO_HZ 1800000000 - #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ - #define HW_CFG_BUS_CLK_HZ 166666666 - #define HW_CFG_DDR_CTLR_CLK_HZ 333333333 - #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) - #define HW_CFG_UART_CLK_HZ 142857142 - #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ - #endif -#else - #define HW_CFG_PLL_VCO_HZ 1800000000 - #define HW_CFG_PLL2_VCO_HZ 1800000000 - #define HW_CFG_ARM_CLK_HZ 450000000 - #define HW_CFG_BUS_CLK_HZ 150000000 - #define HW_CFG_DDR_CTLR_CLK_HZ 300000000 - #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) - #define HW_CFG_UART_CLK_HZ 150000000 - #define HW_CFG_VPM_CLK_HZ 300000000 -#endif - -/* ---- Public Constants and Types --------------------------------------- */ -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - - -#endif /* CSP_HW_CFG_H */ - diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h deleted file mode 100644 index 0aeb6a6fe7f8..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file intcHw_reg.h -* -* @brief platform specific interrupt controller bit assignments -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _INTCHW_REG_H -#define _INTCHW_REG_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <csp/stdint.h> -#include <csp/reg.h> -#include <mach/csp/mm_io.h> - -/* ---- Public Constants and Types --------------------------------------- */ - -#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */ -#define INTCHW_NUM_INTC 3 - -/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) -#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) -#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) - -/* INTC0 - interrupt controller 0 */ -#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ -#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */ -#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */ -#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */ -#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */ -#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */ -#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */ -#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */ -#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */ -#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */ -#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */ -#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */ -#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */ -#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */ -#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */ -#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */ -#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */ -#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */ -#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */ -#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */ -#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */ -#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */ -#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */ -#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */ -#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */ -#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */ -#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */ -#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */ -#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */ -#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */ -#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */ -#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */ - -#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM) -#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM) -#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM) -#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM) -#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM) -#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM) -#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM) -#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM) -#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM) -#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM) -#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM) -#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM) -#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM) -#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM) -#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM) -#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM) -#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM) -#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM) -#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM) -#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM) -#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM) -#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM) -#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM) -#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM) -#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM) -#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM) -#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM) -#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM) -#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM) -#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM) -#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM) -#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM) - -/* INTC1 - interrupt controller 1 */ -#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */ -#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */ -#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */ -#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */ -#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */ -/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */ -#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */ -#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */ -#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */ -#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */ -#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */ -#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */ -#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */ -#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */ -#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */ -#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */ -#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */ - -#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */ -#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */ -#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */ -#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */ -#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */ -#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */ -#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */ -#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */ -#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */ -#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */ -#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */ -#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */ -#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */ - -#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM) -#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM) -#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM) -#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM) -#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM) -#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM) -#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM) -#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM) -#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM) -#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM) -#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM) -#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM) -#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM) -#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM) -#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM) -#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM) -#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM) -#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM) -#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM) -#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM) -#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM) -#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM) -#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM) -#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM) -#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM) -#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM) -#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM) -#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM) -#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM) - -/* SINTC secure int controller */ -#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */ -#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */ -#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */ -#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */ -#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */ -#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */ -#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */ -#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */ -#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */ -#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */ -#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */ -#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */ -#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */ -#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */ -#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */ -#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */ - -#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM) -#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM) -#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM) -#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM) -#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM) -#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM) -#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM) -#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM) -#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM) -#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM) -#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM) -#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM) -#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM) -#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM) -#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM) -#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM) - -/* PL192 Vectored Interrupt Controller (VIC) layout */ -#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */ -#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */ -#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */ -#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */ -#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */ -#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */ -#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */ -#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */ -#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */ -#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */ -#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */ -#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */ -#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */ -#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */ -#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */ -#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */ - -/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */ -/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */ -/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */ -/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */ - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ -/* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask) -{ - __REG32(basep + INTCHW_INTENCLEAR) = mask; -} - -/* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void *basep, uint32_t mask) -{ - __REG32(basep + INTCHW_INTENABLE) = mask; -} - -#endif /* _INTCHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h deleted file mode 100644 index ad58cf873377..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ /dev/null @@ -1,101 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file mm_addr.h -* -* @brief Memory Map address definitions -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _MM_ADDR_H -#define _MM_ADDR_H - -/* ---- Include Files ---------------------------------------------------- */ - -#if !defined(CSP_SIMULATION) -#include <cfg_global.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ - -/* Memory Map address definitions */ - -#define MM_ADDR_DDR 0x00000000 - -#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */ - -#define MM_ADDR_IO_FLASHC 0x20000000 -#define MM_ADDR_IO_BROM 0x30000000 -#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */ -#define MM_ADDR_IO_DMA0 0x30200000 -#define MM_ADDR_IO_DMA1 0x30300000 -#define MM_ADDR_IO_ESW 0x30400000 -#define MM_ADDR_IO_CLCD 0x30500000 -#define MM_ADDR_IO_PIF 0x30580000 -#define MM_ADDR_IO_APM 0x30600000 -#define MM_ADDR_IO_SPUM 0x30700000 -#define MM_ADDR_IO_VPM_PROG 0x30800000 -#define MM_ADDR_IO_VPM_DATA 0x30A00000 -#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */ -#define MM_ADDR_IO_CHIPC 0x80000000 -#define MM_ADDR_IO_UMI 0x80001000 -#define MM_ADDR_IO_NAND 0x80001800 -#define MM_ADDR_IO_LEDM 0x80002000 -#define MM_ADDR_IO_PWM 0x80002040 -#define MM_ADDR_IO_VINTC 0x80003000 -#define MM_ADDR_IO_GPIO0 0x80004000 -#define MM_ADDR_IO_GPIO1 0x80004800 -#define MM_ADDR_IO_I2CS 0x80005000 -#define MM_ADDR_IO_SPIS 0x80006000 -#define MM_ADDR_IO_HPM 0x80007400 -#define MM_ADDR_IO_HPM_REMAP 0x80007800 -#define MM_ADDR_IO_TZPC 0x80008000 -#define MM_ADDR_IO_MPU 0x80009000 -#define MM_ADDR_IO_SPUMP 0x8000a000 -#define MM_ADDR_IO_PKA 0x8000b000 -#define MM_ADDR_IO_RNG 0x8000c000 -#define MM_ADDR_IO_KEYC 0x8000d000 -#define MM_ADDR_IO_BBL 0x8000e000 -#define MM_ADDR_IO_OTP 0x8000f000 -#define MM_ADDR_IO_I2S0 0x80010000 -#define MM_ADDR_IO_I2S1 0x80011000 -#define MM_ADDR_IO_UARTA 0x80012000 -#define MM_ADDR_IO_UARTB 0x80013000 -#define MM_ADDR_IO_I2CH 0x80014020 -#define MM_ADDR_IO_SPIH 0x80015000 -#define MM_ADDR_IO_TSC 0x80016000 -#define MM_ADDR_IO_TMR 0x80017000 -#define MM_ADDR_IO_WATCHDOG 0x80017800 -#define MM_ADDR_IO_ETM 0x80018000 -#define MM_ADDR_IO_DDRC 0x80019000 -#define MM_ADDR_IO_SINTC 0x80100000 -#define MM_ADDR_IO_INTC0 0x80200000 -#define MM_ADDR_IO_INTC1 0x80201000 -#define MM_ADDR_IO_GE 0x80300000 -#define MM_ADDR_IO_USB_CTLR0 0x80400000 -#define MM_ADDR_IO_USB_CTLR1 0x80410000 -#define MM_ADDR_IO_USB_PHY 0x80420000 -#define MM_ADDR_IO_SDIOH0 0x80500000 -#define MM_ADDR_IO_SDIOH1 0x80600000 -#define MM_ADDR_IO_VDEC 0x80700000 - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* _MM_ADDR_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h deleted file mode 100644 index de92ec6a01aa..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ /dev/null @@ -1,147 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file mm_io.h -* -* @brief Memory Map I/O definitions -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef _MM_IO_H -#define _MM_IO_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <mach/csp/mm_addr.h> - -#if !defined(CSP_SIMULATION) -#include <cfg_global.h> -#endif - -/* ---- Public Constants and Types --------------------------------------- */ - -#if defined(CONFIG_MMU) - -/* This macro is referenced in <mach/io.h> - * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx - * This macro is referenced in <asm/arch/io.h> - * - * Assume VPM address is the last x MB of memory. For VPM, map to - * 0xf0000000 and up. - */ - -#ifndef MM_IO_PHYS_TO_VIRT -#ifdef __ASSEMBLY__ -#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) -#else -#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ - (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) -#endif -#endif - -/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */ - -#ifndef MM_IO_VIRT_TO_PHYS -#ifdef __ASSEMBLY__ -#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) -#else -#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) -#endif -#endif - -#else - -#ifndef MM_IO_PHYS_TO_VIRT -#define MM_IO_PHYS_TO_VIRT(phys) (phys) -#endif - -#ifndef MM_IO_VIRT_TO_PHYS -#define MM_IO_VIRT_TO_PHYS(virt) (virt) -#endif - -#endif - -/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */ -#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC) -#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND) -#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI) - -#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */ -#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */ - -#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM) -#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM) -#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0) -#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1) -#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW) -#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD) -#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF) -#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM) -#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM) -#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG) -#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA) - -#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM) - -#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC) -#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC) -#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM) -#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM) -#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC) -#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0) -#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1) -#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR) -#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG) -#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM) -#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM) -#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP) -#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC) -#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU) -#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP) -#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA) -#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG) -#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC) -#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL) -#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP) -#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0) -#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1) -#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA) -#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB) -#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH) -#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH) -#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC) -#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS) -#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS) -#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC) -#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0) -#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1) -#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE) -#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0) -#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1) -#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY) -#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0) -#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1) -#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC) - -#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD) - -/* ---- Public Variable Externs ------------------------------------------ */ -/* ---- Public Function Prototypes --------------------------------------- */ - -#endif /* _MM_IO_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h deleted file mode 100644 index d15f5f3ec2d8..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw_def.h -* -* @brief Definitions for configuring/testing secure blocks -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef SECHW_DEF_H -#define SECHW_DEF_H - -#include <mach/csp/mm_io.h> - -/* Bit mask for various secure device */ -#define secHw_BLK_MASK_CHIP_CONTROL 0x00000001 -#define secHw_BLK_MASK_KEY_SCAN 0x00000002 -#define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004 -#define secHw_BLK_MASK_UART0 0x00000008 -#define secHw_BLK_MASK_UART1 0x00000010 -#define secHw_BLK_MASK_WATCHDOG 0x00000020 -#define secHw_BLK_MASK_SPUM 0x00000040 -#define secHw_BLK_MASK_DDR2 0x00000080 -#define secHw_BLK_MASK_EXT_MEM 0x00000100 -#define secHw_BLK_MASK_ESW 0x00000200 -#define secHw_BLK_MASK_SPU 0x00010000 -#define secHw_BLK_MASK_PKA 0x00020000 -#define secHw_BLK_MASK_RNG 0x00040000 -#define secHw_BLK_MASK_RTC 0x00080000 -#define secHw_BLK_MASK_OTP 0x00100000 -#define secHw_BLK_MASK_BOOT 0x00200000 -#define secHw_BLK_MASK_MPU 0x00400000 -#define secHw_BLK_MASK_TZCTRL 0x00800000 -#define secHw_BLK_MASK_INTR 0x01000000 - -/* Trustzone register set */ -typedef struct { - volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */ - volatile uint32_t setUnsecure; /* write only. reads back as 0 */ - volatile uint32_t setSecure; /* write only. reads back as 0 */ -} secHw_TZREG_t; - -/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */ -/* is for the higher 16 bits. */ - -typedef enum { - secHw_IDX_LS = 0, - secHw_IDX_MS = 1, - secHw_IDX_NUM -} secHw_IDX_e; - -typedef struct { - volatile secHw_TZREG_t reg[secHw_IDX_NUM]; -} secHw_REGS_t; - -/****************************************************************************/ -/** -* @brief Configures a device as a secure device -* -*/ -/****************************************************************************/ -static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Configures a device as a non-secure device -* -*/ -/****************************************************************************/ -static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ - ); - -/****************************************************************************/ -/** -* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure -* -*/ -/****************************************************************************/ -static inline uint32_t secHw_getStatus(void); - -#include <mach/csp/secHw_inline.h> - -#endif /* SECHW_DEF_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h deleted file mode 100644 index 9cd6a032ab71..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ /dev/null @@ -1,79 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file secHw_inline.h -* -* @brief Definitions for configuring/testing secure blocks -* -* @note -* None -*/ -/****************************************************************************/ - -#ifndef SECHW_INLINE_H -#define SECHW_INLINE_H - -/****************************************************************************/ -/** -* @brief Configures a device as a secure device -* -*/ -/****************************************************************************/ -static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ - ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; - - if (mask & 0x0000FFFF) { - regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; - } - - if (mask & 0xFFFF0000) { - regp->reg[secHw_IDX_MS].setSecure = mask >> 16; - } -} - -/****************************************************************************/ -/** -* @brief Configures a device as a non-secure device -* -*/ -/****************************************************************************/ -static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ - ) { - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; - - if (mask & 0x0000FFFF) { - regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; - } - if (mask & 0xFFFF0000) { - regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; - } -} - -/****************************************************************************/ -/** -* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure -* -*/ -/****************************************************************************/ -static inline uint32_t secHw_getStatus(void) -{ - secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; - - return (regp->reg[1].status << 16) + regp->reg[0].status; -} - -#endif /* SECHW_INLINE_H */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h deleted file mode 100644 index 3080ac7239a1..000000000000 --- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h +++ /dev/null @@ -1,82 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file tmrHw_reg.h -* -* @brief Definitions for low level Timer registers -* -*/ -/****************************************************************************/ -#ifndef _TMRHW_REG_H -#define _TMRHW_REG_H - -#include <mach/csp/mm_io.h> -#include <mach/csp/hw_cfg.h> -/* Base address */ -#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR - -/* -This platform has four different timers running at different clock speed - -Timer one (Timer ID 0) runs at 25 MHz -Timer two (Timer ID 1) runs at 25 MHz -Timer three (Timer ID 2) runs at 150 MHz -Timer four (Timer ID 3) runs at 150 MHz -*/ -#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */ -#define tmrHw_LOW_FREQUENCY_HZ 25000000 - -#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107) -#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */ -#define tmrHw_HIGH_FREQUENCY_HZ 150000000 -#else -#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ -#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000) -#endif - -#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ -#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ -#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */ -#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */ - -typedef struct { - uint32_t LoadValue; /* Load value for timer */ - uint32_t CurrentValue; /* Current value for timer */ - uint32_t Control; /* Control register */ - uint32_t InterruptClear; /* Interrupt clear register */ - uint32_t RawInterruptStatus; /* Raw interrupt status */ - uint32_t InterruptStatus; /* Masked interrupt status */ - uint32_t BackgroundLoad; /* Background load value */ - uint32_t padding; /* Padding register */ -} tmrHw_REG_t; - -/* Control bot masks */ -#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080 -#define tmrHw_CONTROL_PERIODIC 0x00000040 -#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020 -#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C -#define tmrHw_CONTROL_PRESCALE_1 0x00000000 -#define tmrHw_CONTROL_PRESCALE_16 0x00000004 -#define tmrHw_CONTROL_PRESCALE_256 0x00000008 -#define tmrHw_CONTROL_32BIT 0x00000002 -#define tmrHw_CONTROL_ONESHOT 0x00000001 -#define tmrHw_CONTROL_FREE_RUNNING 0x00000000 - -#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT) - -#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR) - -#endif /* _TMRHW_REG_H */ diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h deleted file mode 100644 index 72543781207b..000000000000 --- a/arch/arm/mach-bcmring/include/mach/dma.h +++ /dev/null @@ -1,630 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/****************************************************************************/ -/** -* @file dma.h -* -* @brief API definitions for the linux DMA interface. -*/ -/****************************************************************************/ - -#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H) -#define ASM_ARM_ARCH_BCMRING_DMA_H - -/* ---- Include Files ---------------------------------------------------- */ - -#include <linux/kernel.h> -#include <linux/semaphore.h> -#include <csp/dmacHw.h> -#include <mach/timer.h> - -/* ---- Constants and Types ---------------------------------------------- */ - -/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */ -/* and line number of the reservation request will be recorded in the channel table */ - -#define DMA_DEBUG_TRACK_RESERVATION 1 - -#define DMA_NUM_CONTROLLERS 2 -#define DMA_NUM_CHANNELS 8 /* per controller */ - -typedef enum { - DMA_DEVICE_MEM_TO_MEM, /* For memory to memory transfers */ - DMA_DEVICE_I2S0_DEV_TO_MEM, - DMA_DEVICE_I2S0_MEM_TO_DEV, - DMA_DEVICE_I2S1_DEV_TO_MEM, - DMA_DEVICE_I2S1_MEM_TO_DEV, - DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM, - DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV, - DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM, - DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV, - DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM, /* Additional mic input for beam-forming */ - DMA_DEVICE_APM_PCM0_DEV_TO_MEM, - DMA_DEVICE_APM_PCM0_MEM_TO_DEV, - DMA_DEVICE_APM_PCM1_DEV_TO_MEM, - DMA_DEVICE_APM_PCM1_MEM_TO_DEV, - DMA_DEVICE_SPUM_DEV_TO_MEM, - DMA_DEVICE_SPUM_MEM_TO_DEV, - DMA_DEVICE_SPIH_DEV_TO_MEM, - DMA_DEVICE_SPIH_MEM_TO_DEV, - DMA_DEVICE_UART_A_DEV_TO_MEM, - DMA_DEVICE_UART_A_MEM_TO_DEV, - DMA_DEVICE_UART_B_DEV_TO_MEM, - DMA_DEVICE_UART_B_MEM_TO_DEV, - DMA_DEVICE_PIF_MEM_TO_DEV, - DMA_DEVICE_PIF_DEV_TO_MEM, - DMA_DEVICE_ESW_DEV_TO_MEM, - DMA_DEVICE_ESW_MEM_TO_DEV, - DMA_DEVICE_VPM_MEM_TO_MEM, - DMA_DEVICE_CLCD_MEM_TO_MEM, - DMA_DEVICE_NAND_MEM_TO_MEM, - DMA_DEVICE_MEM_TO_VRAM, - DMA_DEVICE_VRAM_TO_MEM, - - /* Add new entries before this line. */ - - DMA_NUM_DEVICE_ENTRIES, - DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */ - -} DMA_Device_t; - -/**************************************************************************** -* -* The DMA_Handle_t is the primary object used by callers of the API. -* -*****************************************************************************/ - -#define DMA_INVALID_HANDLE ((DMA_Handle_t) -1) - -typedef int DMA_Handle_t; - -/**************************************************************************** -* -* The DMA_DescriptorRing_t contains a ring of descriptors which is used -* to point to regions of memory. -* -*****************************************************************************/ - -typedef struct { - void *virtAddr; /* Virtual Address of the descriptor ring */ - dma_addr_t physAddr; /* Physical address of the descriptor ring */ - int descriptorsAllocated; /* Number of descriptors allocated in the descriptor ring */ - size_t bytesAllocated; /* Number of bytes allocated in the descriptor ring */ - -} DMA_DescriptorRing_t; - -/**************************************************************************** -* -* The DMA_DeviceAttribute_t contains information which describes a -* particular DMA device (or peripheral). -* -* It is anticipated that the arrary of DMA_DeviceAttribute_t's will be -* statically initialized. -* -*****************************************************************************/ - -/* The device handler is called whenever a DMA operation completes. The reaon */ -/* for it to be called will be a bitmask with one or more of the following bits */ -/* set. */ - -#define DMA_HANDLER_REASON_BLOCK_COMPLETE dmacHw_INTERRUPT_STATUS_BLOCK -#define DMA_HANDLER_REASON_TRANSFER_COMPLETE dmacHw_INTERRUPT_STATUS_TRANS -#define DMA_HANDLER_REASON_ERROR dmacHw_INTERRUPT_STATUS_ERROR - -typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason, - void *userData); - -#define DMA_DEVICE_FLAG_ON_DMA0 0x00000001 -#define DMA_DEVICE_FLAG_ON_DMA1 0x00000002 -#define DMA_DEVICE_FLAG_PORT_PER_DMAC 0x00000004 /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */ -#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST 0x00000008 /* If set, allocate from DMA1 before allocating from DMA0 */ -#define DMA_DEVICE_FLAG_IS_DEDICATED 0x00000100 -#define DMA_DEVICE_FLAG_NO_ISR 0x00000200 -#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO 0x00000400 -#define DMA_DEVICE_FLAG_IN_USE 0x00000800 /* If set, device is in use on a channel */ - -/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */ -/* determine which DMA controllers a given device can be used from, and the interface */ -/* array determeines the actual interface number to use for a given controller. */ - -typedef struct { - uint32_t flags; /* Bitmask of DMA_DEVICE_FLAG_xxx constants */ - uint8_t dedicatedController; /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */ - uint8_t dedicatedChannel; /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */ - const char *name; /* Will show up in the /proc entry */ - - uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */ - - dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */ - - void *userData; /* Passed to the devHandler */ - DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */ - - timer_tick_count_t transferStartTime; /* Time the current transfer was started */ - - /* The following statistical information will be collected and presented in a proc entry. */ - /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */ - /* a 64 bit counter. */ - - uint64_t numTransfers; /* Number of DMA transfers performed */ - uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */ - uint64_t transferBytes; /* Total bytes transferred */ - uint32_t timesBlocked; /* Number of times a channel was unavailable */ - uint32_t numBytes; /* Last transfer size */ - - /* It's not possible to free memory which is allocated for the descriptors from within */ - /* the ISR. So make the presumption that a given device will tend to use the */ - /* same sized buffers over and over again, and we keep them around. */ - - DMA_DescriptorRing_t ring; /* Ring of descriptors allocated for this device */ - - /* We stash away some of the information from the previous transfer. If back-to-back */ - /* transfers are performed from the same buffer, then we don't have to keep re-initializing */ - /* the descriptor buffers. */ - - uint32_t prevNumBytes; - dma_addr_t prevSrcData; - dma_addr_t prevDstData; - -} DMA_DeviceAttribute_t; - -/**************************************************************************** -* -* DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal -* data structures and don't belong in this header file, but are included -* merely for discussion. -* -* By the time this is implemented, these structures will be moved out into -* the appropriate C source file instead. -* -*****************************************************************************/ - -/**************************************************************************** -* -* The DMA_Channel_t contains state information about each DMA channel. Some -* of the channels are dedicated. Non-dedicated channels are shared -* amongst the other devices. -* -*****************************************************************************/ - -#define DMA_CHANNEL_FLAG_IN_USE 0x00000001 -#define DMA_CHANNEL_FLAG_IS_DEDICATED 0x00000002 -#define DMA_CHANNEL_FLAG_NO_ISR 0x00000004 -#define DMA_CHANNEL_FLAG_LARGE_FIFO 0x00000008 - -typedef struct { - uint32_t flags; /* bitmask of DMA_CHANNEL_FLAG_xxx constants */ - DMA_Device_t devType; /* Device this channel is currently reserved for */ - DMA_Device_t lastDevType; /* Device type that used this previously */ - char name[20]; /* Name passed onto request_irq */ - -#if (DMA_DEBUG_TRACK_RESERVATION) - const char *fileName; /* Place where channel reservation took place */ - int lineNum; /* Place where channel reservation took place */ -#endif - dmacHw_HANDLE_t dmacHwHandle; /* low level channel handle. */ - -} DMA_Channel_t; - -/**************************************************************************** -* -* The DMA_Controller_t contains state information about each DMA controller. -* -* The freeChannelQ is stored in the controller data structure rather than -* the channel data structure since several of the devices are accessible -* from multiple controllers, and there is no way to know which controller -* will become available first. -* -*****************************************************************************/ - -typedef struct { - DMA_Channel_t channel[DMA_NUM_CHANNELS]; - -} DMA_Controller_t; - -/**************************************************************************** -* -* The DMA_Global_t contains all of the global state information used by -* the DMA code. -* -* Callers which need to allocate a shared channel will be queued up -* on the freeChannelQ until a channel becomes available. -* -*****************************************************************************/ - -typedef struct { - struct semaphore lock; /* acquired when manipulating table entries */ - wait_queue_head_t freeChannelQ; - - DMA_Controller_t controller[DMA_NUM_CONTROLLERS]; - -} DMA_Global_t; - -/* ---- Variable Externs ------------------------------------------------- */ - -extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES]; - -/* ---- Function Prototypes ---------------------------------------------- */ - -#if defined(__KERNEL__) - -/****************************************************************************/ -/** -* Initializes the DMA module. -* -* @return -* 0 - Success -* < 0 - Error -*/ -/****************************************************************************/ - -int dma_init(void); - -#if (DMA_DEBUG_TRACK_RESERVATION) -DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName, - int lineNum); -#define dma_request_channel(dev) dma_request_channel_dbg(dev, __FILE__, __LINE__) -#else - -/****************************************************************************/ -/** -* Reserves a channel for use with @a dev. If the device is setup to use -* a shared channel, then this function will block until a free channel -* becomes available. -* -* @return -* >= 0 - A valid DMA Handle. -* -EBUSY - Device is currently being used. -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -DMA_Handle_t dma_request_channel(DMA_Device_t dev /* Device to use with the allocated channel. */ - ); -#endif - -/****************************************************************************/ -/** -* Frees a previously allocated DMA Handle. -* -* @return -* 0 - DMA Handle was released successfully. -* -EINVAL - Invalid DMA handle -*/ -/****************************************************************************/ - -int dma_free_channel(DMA_Handle_t channel /* DMA handle. */ - ); - -/****************************************************************************/ -/** -* Determines if a given device has been configured as using a shared -* channel. -* -* @return boolean -* 0 Device uses a dedicated channel -* non-zero Device uses a shared channel -*/ -/****************************************************************************/ - -int dma_device_is_channel_shared(DMA_Device_t dev /* Device to check. */ - ); - -/****************************************************************************/ -/** -* Allocates memory to hold a descriptor ring. The descriptor ring then -* needs to be populated by making one or more calls to -* dna_add_descriptors. -* -* The returned descriptor ring will be automatically initialized. -* -* @return -* 0 Descriptor ring was allocated successfully -* -ENOMEM Unable to allocate memory for the desired number of descriptors. -*/ -/****************************************************************************/ - -int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */ - int numDescriptors /* Number of descriptors that need to be allocated. */ - ); - -/****************************************************************************/ -/** -* Releases the memory which was previously allocated for a descriptor ring. -*/ -/****************************************************************************/ - -void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */ - ); - -/****************************************************************************/ -/** -* Initializes a descriptor ring, so that descriptors can be added to it. -* Once a descriptor ring has been allocated, it may be reinitialized for -* use with additional/different regions of memory. -* -* Note that if 7 descriptors are allocated, it's perfectly acceptable to -* initialize the ring with a smaller number of descriptors. The amount -* of memory allocated for the descriptor ring will not be reduced, and -* the descriptor ring may be reinitialized later -* -* @return -* 0 Descriptor ring was initialized successfully -* -ENOMEM The descriptor which was passed in has insufficient space -* to hold the desired number of descriptors. -*/ -/****************************************************************************/ - -int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */ - int numDescriptors /* Number of descriptors to initialize. */ - ); - -/****************************************************************************/ -/** -* Determines the number of descriptors which would be required for a -* transfer of the indicated memory region. -* -* This function also needs to know which DMA device this transfer will -* be destined for, so that the appropriate DMA configuration can be retrieved. -* DMA parameters such as transfer width, and whether this is a memory-to-memory -* or memory-to-peripheral, etc can all affect the actual number of descriptors -* required. -* -* @return -* > 0 Returns the number of descriptors required for the indicated transfer -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ); - -/****************************************************************************/ -/** -* Adds a region of memory to the descriptor ring. Note that it may take -* multiple descriptors for each region of memory. It is the callers -* responsibility to allocate a sufficiently large descriptor ring. -* -* @return -* 0 Descriptors were added successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */ - DMA_Device_t device, /* DMA Device that descriptors are for */ - dma_addr_t srcData, /* Place to get data (memory or device) */ - dma_addr_t dstData, /* Place to put data (memory or device) */ - size_t numBytes /* Number of bytes to transfer to the device */ - ); - -/****************************************************************************/ -/** -* Sets the descriptor ring associated with a device. -* -* Once set, the descriptor ring will be associated with the device, even -* across channel request/free calls. Passing in a NULL descriptor ring -* will release any descriptor ring currently associated with the device. -* -* Note: If you call dma_transfer, or one of the other dma_alloc_ functions -* the descriptor ring may be released and reallocated. -* -* Note: This function will release the descriptor memory for any current -* descriptor ring associated with this device. -*/ -/****************************************************************************/ - -int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */ - DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */ - ); - -/****************************************************************************/ -/** -* Retrieves the descriptor ring associated with a device. -*/ -/****************************************************************************/ - -int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */ - DMA_DescriptorRing_t *ring /* Place to store retrieved ring */ - ); - -/****************************************************************************/ -/** -* Allocates buffers for the descriptors. This is normally done automatically -* but needs to be done explicitly when initiating a dma from interrupt -* context. -* -* @return -* 0 Descriptors were allocated successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */ - dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ); - -/****************************************************************************/ -/** -* Allocates and sets up descriptors for a double buffered circular buffer. -* -* This is primarily intended to be used for things like the ingress samples -* from a microphone. -* -* @return -* > 0 Number of descriptors actually allocated. -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -* -ENOMEM Memory exhausted -*/ -/****************************************************************************/ - -int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ - dma_addr_t srcData, /* Physical address of source data */ - dma_addr_t dstData1, /* Physical address of first destination buffer */ - dma_addr_t dstData2, /* Physical address of second destination buffer */ - size_t numBytes /* Number of bytes in each destination buffer */ - ); - -/****************************************************************************/ -/** -* Initiates a transfer when the descriptors have already been setup. -* -* This is a special case, and normally, the dma_transfer_xxx functions should -* be used. -* -* @return -* 0 Transfer was started successfully -* -ENODEV Invalid handle -*/ -/****************************************************************************/ - -int dma_start_transfer(DMA_Handle_t handle); - -/****************************************************************************/ -/** -* Stops a previously started DMA transfer. -* -* @return -* 0 Transfer was stopped successfully -* -ENODEV Invalid handle -*/ -/****************************************************************************/ - -int dma_stop_transfer(DMA_Handle_t handle); - -/****************************************************************************/ -/** -* Waits for a DMA to complete by polling. This function is only intended -* to be used for testing. Interrupts should be used for most DMA operations. -*/ -/****************************************************************************/ - -int dma_wait_transfer_done(DMA_Handle_t handle); - -/****************************************************************************/ -/** -* Initiates a DMA transfer -* -* @return -* 0 Transfer was started successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -*/ -/****************************************************************************/ - -int dma_transfer(DMA_Handle_t handle, /* DMA Handle */ - dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ - dma_addr_t srcData, /* Place to get data to write to device */ - dma_addr_t dstData, /* Pointer to device data address */ - size_t numBytes /* Number of bytes to transfer to the device */ - ); - -/****************************************************************************/ -/** -* Initiates a transfer from memory to a device. -* -* @return -* 0 Transfer was started successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV) -*/ -/****************************************************************************/ - -static inline int dma_transfer_to_device(DMA_Handle_t handle, /* DMA Handle */ - dma_addr_t srcData, /* Place to get data to write to device (physical address) */ - dma_addr_t dstData, /* Pointer to device data address (physical address) */ - size_t numBytes /* Number of bytes to transfer to the device */ - ) { - return dma_transfer(handle, - dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, - srcData, dstData, numBytes); -} - -/****************************************************************************/ -/** -* Initiates a transfer from a device to memory. -* -* @return -* 0 Transfer was started successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) -*/ -/****************************************************************************/ - -static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */ - dma_addr_t srcData, /* Pointer to the device data address (physical address) */ - dma_addr_t dstData, /* Place to store data retrieved from the device (physical address) */ - size_t numBytes /* Number of bytes to retrieve from the device */ - ) { - return dma_transfer(handle, - dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, - srcData, dstData, numBytes); -} - -/****************************************************************************/ -/** -* Initiates a memory to memory transfer. -* -* @return -* 0 Transfer was started successfully -* -EINVAL Invalid device type for this kind of transfer -* (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM) -*/ -/****************************************************************************/ - -static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle, /* DMA Handle */ - dma_addr_t srcData, /* Place to transfer data from (physical address) */ - dma_addr_t dstData, /* Place to transfer data to (physical address) */ - size_t numBytes /* Number of bytes to transfer */ - ) { - return dma_transfer(handle, - dmacHw_TRANSFER_TYPE_MEM_TO_MEM, - srcData, dstData, numBytes); -} - -/****************************************************************************/ -/** -* Set the callback function which will be called when a transfer completes. -* If a NULL callback function is set, then no callback will occur. -* -* @note @a devHandler will be called from IRQ context. -* -* @return -* 0 - Success -* -ENODEV - Device handed in is invalid. -*/ -/****************************************************************************/ - -int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */ - DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */ - void *userData /* Pointer which will be passed to devHandler. */ - ); - -#endif - -#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */ diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S deleted file mode 100644 index 2f316f0e6e69..000000000000 --- a/arch/arm/mach-bcmring/include/mach/entry-macro.S +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************** -* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* - * - * Low-level IRQ helper macros for BCMRing-based platforms - * - */ -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/csp/mm_io.h> - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =(MM_IO_BASE_INTC0) - ldr \irqstat, [\base, #0] @ get status - ldr \irqnr, [\base, #0x10] @ mask with enable register - ands \irqstat, \irqstat, \irqnr - mov \irqnr, #IRQ_INTC0_START - cmp \irqstat, #0 - bne 1001f - - ldr \base, =(MM_IO_BASE_INTC1) - ldr \irqstat, [\base, #0] @ get status - ldr \irqnr, [\base, #0x10] @ mask with enable register - ands \irqstat, \irqstat, \irqnr - mov \irqnr, #IRQ_INTC1_START - cmp \irqstat, #0 - bne 1001f - - ldr \base, =(MM_IO_BASE_SINTC) - ldr \irqstat, [\base, #0] @ get status - ldr \irqnr, [\base, #0x10] @ mask with enable register - ands \irqstat, \irqstat, \irqnr - mov \irqnr, #0xffffffff @ code meaning no interrupt bits set - cmp \irqstat, #0 - beq 1002f - - mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value - -1001: - movs \tmp, \irqstat, lsl #16 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #16 - - movs \tmp, \irqstat, lsl #8 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #8 - - movs \tmp, \irqstat, lsl #4 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #4 - - movs \tmp, \irqstat, lsl #2 - movne \irqstat, \tmp - addeq \irqnr, \irqnr, #2 - - movs \tmp, \irqstat, lsl #1 - addeq \irqnr, \irqnr, #1 - orrs \base, \base, #1 - -1002: @ irqnr will be set to 0xffffffff if no irq bits are set - .endm - - .macro get_irqnr_preamble, base, tmp - .endm diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h deleted file mode 100644 index 6ae20a649a97..000000000000 --- a/arch/arm/mach-bcmring/include/mach/hardware.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * - * This file contains the hardware definitions of the BCMRing. - * - * Copyright (C) 1999 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> -#include <cfg_global.h> -#include <mach/csp/mm_io.h> - -/* Hardware addresses of major areas. - * *_START is the physical address - * *_SIZE is the size of the region - * *_BASE is the virtual address - */ -#define RAM_START PHYS_OFFSET - -#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) -#define RAM_BASE PAGE_OFFSET - -/* Macros to make managing spinlocks a bit more controlled in terms of naming. */ -/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */ -#if defined(__KERNEL__) -#define HW_DECLARE_SPINLOCK(name) DEFINE_SPINLOCK(bcmring_##name##_reg_lock); -#define HW_EXTERN_SPINLOCK(name) extern spinlock_t bcmring_##name##_reg_lock; -#define HW_IRQ_SAVE(name, val) spin_lock_irqsave(&bcmring_##name##_reg_lock, (val)) -#define HW_IRQ_RESTORE(name, val) spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val)) -#else -#define HW_DECLARE_SPINLOCK(name) -#define HW_EXTERN_SPINLOCK(name) -#define HW_IRQ_SAVE(name, val) {(void)(name); (void)(val); } -#define HW_IRQ_RESTORE(name, val) {(void)(name); (void)(val); } -#endif - -#ifndef HW_IO_PHYS_TO_VIRT -#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT -#endif -#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS - -#endif diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h deleted file mode 100644 index b279b825d4a7..000000000000 --- a/arch/arm/mach-bcmring/include/mach/irqs.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2007 Broadcom - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#if !defined(ARCH_BCMRING_IRQS_H) -#define ARCH_BCMRING_IRQS_H - -/* INTC0 - interrupt controller 0 */ -#define IRQ_INTC0_START 0 -#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */ -#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */ -#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */ -#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */ -#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */ -#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */ -#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */ -#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */ -#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */ -#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */ -#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */ -#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */ -#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */ -#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */ -#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */ -#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */ -#define IRQ_VPM 16 /* Voice process module interrupt */ -#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */ -#define IRQ_USBH1 18 /* USB1 host interrupt */ -#define IRQ_USBD 19 /* USB device interrupt */ -#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */ -#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */ -#define IRQ_TIMER0 22 /* Timer0 interrupt */ -#define IRQ_TIMER1 23 /* Timer1 interrupt */ -#define IRQ_TIMER2 24 /* Timer2 interrupt */ -#define IRQ_TIMER3 25 /* Timer3 interrupt */ -#define IRQ_SPIH 26 /* SPI host interrupt */ -#define IRQ_ESW 27 /* Ethernet switch interrupt */ -#define IRQ_APM 28 /* Audio process module interrupt */ -#define IRQ_GE 29 /* Graphic engine interrupt */ -#define IRQ_CLCD 30 /* LCD Controller interrupt */ -#define IRQ_PIF 31 /* Peripheral interface interrupt */ -#define IRQ_INTC0_END 31 - -/* INTC1 - interrupt controller 1 */ -#define IRQ_INTC1_START 32 -#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */ -#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */ -#define IRQ_I2S0 34 /* 2 I2S0 interrupt */ -#define IRQ_I2S1 35 /* 3 I2S1 interrupt */ -#define IRQ_I2CH 36 /* 4 I2C host interrupt */ -#define IRQ_I2CS 37 /* 5 I2C slave interrupt */ -#define IRQ_SPIS 38 /* 6 SPI slave interrupt */ -#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */ -#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */ -#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */ -#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */ -#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */ -#define IRQ_UARTB 44 /* 12 UARTB */ -#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */ -#define IRQ_UARTA 46 /* 14 UARTA */ -#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */ -#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */ -#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */ -#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */ -#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */ -#define IRQ_RNG 52 /* 20 Random number generator interrupt */ -#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */ -#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */ -#define IRQ_SPUM 55 /* 23 Secure process module interrupt */ -#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */ -#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */ -#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */ -#define IRQ_INTC1_END 58 - -/* SINTC secure int controller */ -#define IRQ_SINTC_START 59 -#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */ -#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */ -#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */ -#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */ -#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */ -#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */ -#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */ -#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */ -#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */ -#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */ -#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */ -#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */ -#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */ -#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */ -#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */ -#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */ - -#define IRQ_SINTC_END 74 - -/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */ -/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */ -/* to make the mapping easy for humans to decipher. */ - -#define IRQ_GPIO_0 100 - -#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1) - -/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */ -/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */ -#define NUM_GPIO_IRQS 62 - -#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS) - -#define IRQ_UNKNOWN -1 - -/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */ -#define IRQ_INTC0_VALID_MASK 0xffffffff -#define IRQ_INTC1_VALID_MASK 0x07ffffff -#define IRQ_SINTC_VALID_MASK 0x0000ffff - -#endif /* ARCH_BCMRING_IRQS_H */ diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h deleted file mode 100644 index ce5cd16f2ac4..000000000000 --- a/arch/arm/mach-bcmring/include/mach/memory_settings.h +++ /dev/null @@ -1,67 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#ifndef MEMORY_SETTINGS_H -#define MEMORY_SETTINGS_H - -/* ---- Include Files ---------------------------------------- */ -/* ---- Constants and Types ---------------------------------- */ - -/* Memory devices */ -/* NAND Flash timing for 166 MHz setting */ -#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */ -#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */ -#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */ -#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */ -#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */ -#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */ - -#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \ - | HW_CFG_NAND_tWP \ - | HW_CFG_NAND_tWR \ - | HW_CFG_NAND_tAS \ - | HW_CFG_NAND_tOE \ - | HW_CFG_NAND_tRC) - -/* NOR Flash timing for 166 MHz setting */ -#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */ -#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */ -#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */ -#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */ -#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */ -#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */ -#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */ - -#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \ - | HW_CFG_NOR_TBTA \ - | HW_CFG_NOR_TWP \ - | HW_CFG_NOR_TWR \ - | HW_CFG_NOR_TAS \ - | HW_CFG_NOR_TOE \ - | HW_CFG_NOR_TRC_TLC) - -#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR -#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR - -/* SDRAM Settings */ -/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ -/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ -/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ -/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ -#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */ - -/* ---- Variable Externs ------------------------------------- */ -/* ---- Function Prototypes ---------------------------------- */ - -#endif /* MEMORY_SETTINGS_H */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h deleted file mode 100644 index 387376ffb56b..000000000000 --- a/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************** -* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_NAND.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_NAND_H) -#define __ASM_ARCH_REG_NAND_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <csp/reg.h> -#include <mach/reg_umi.h> - -/* ---- Constants and Types ---------------------------------------------- */ - -#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */ - -/* DMA accesses by the bootstrap need hard nonvirtual addresses */ -#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0) -#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4) - -#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8) -#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8) -#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8) - -/* use appropriate offset to make sure it start at the 1K boundary */ -#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400) -#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA) - -/* Linux DMA requires physical address of the data register */ -#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8) -#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA) - -#define NAND_BUS_16BIT() (0) -#define NAND_BUS_8BIT() (!NAND_BUS_16BIT()) - -/* Register offsets */ -#define REG_NAND_CMD_OFFSET (0) -#define REG_NAND_ADDR_OFFSET (4) -#define REG_NAND_DATA8_OFFSET (8) - -#endif diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h deleted file mode 100644 index 0992842caa77..000000000000 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ /dev/null @@ -1,237 +0,0 @@ -/***************************************************************************** -* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_UMI.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_UMI_H) -#define __ASM_ARCH_REG_UMI_H - -/* ---- Include Files ---------------------------------------------------- */ -#include <csp/reg.h> -#include <mach/csp/mm_io.h> - -/* ---- Constants and Types ---------------------------------------------- */ - -/* Unified Memory Interface Ctrl Register */ -#define HW_UMI_BASE MM_IO_BASE_UMI - -/* Flash bank 0 timing and control register */ -#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00) -/* Flash bank 1 timing and control register */ -#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04) -/* Flash bank 2 timing and control register */ -#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08) -/* MMD interface and control register */ -#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c) -/* NAND timing and control register */ -#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18) -/* NAND ready/chip select register */ -#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c) -/* NAND ECC control & status register */ -#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20) -/* NAND ECC data register XXB2B1B0 */ -#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24) -/* BCH ECC Parameter N */ -#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40) -/* BCH ECC Parameter T */ -#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44) -/* BCH ECC Parameter K */ -#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48) -/* BCH ECC Contro Status */ -#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C) -/* BCH WR ECC 31:0 */ -#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50) -/* BCH WR ECC 63:32 */ -#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54) -/* BCH WR ECC 95:64 */ -#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58) -/* BCH WR ECC 127:96 */ -#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c) -/* BCH WR ECC 155:128 */ -#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60) -/* BCH Read Error Location 1,0 */ -#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64) -/* BCH Read Error Location 3,2 */ -#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68) -/* BCH Read Error Location 5,4 */ -#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c) -/* BCH Read Error Location 7,6 */ -#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70) -/* BCH Read Error Location 9,8 */ -#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74) -/* BCH Read Error Location 11,10 */ -#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78) - -/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ -/* Enable wait pin during burst write or read */ -#define REG_UMI_TCR_WAITEN 0x80000000 -/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */ -#define REG_UMI_TCR_LOWFREQ 0x40000000 -/* 1=synch write, 0=async write */ -#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 -/* 1=synch read, 0=async read */ -#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000 -/* 1=page mode read, 0=normal mode read */ -#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000 -/* page size/burst size (wrap only) */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000 -/* 4 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000 -/* 8 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000 -/* 16 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000 -/* 32 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000 -/* 64 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000 -/* 128 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000 -/* 256 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000 -/* 512 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000 -/* Page read access cycle / Burst write latency (n+2 / n+1) */ -#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_TCR_TOE_MASK 0x00000060 -/* Read access cycle / Burst read latency (n+2 / n+1) */ -#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_MMD_ICR bits */ -/* Flash write protection pin control */ -#define REG_UMI_MMD_ICR_FLASH_WP 0x8000 -/* Extend hold time for sram0, sram1 csn (39 MHz operation) */ -#define REG_UMI_MMD_ICR_XHCS 0x4000 -/* Enable SDRAM 2 interface control */ -#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000 -/* Enable merge of flash banks 0/1 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_INST512 0x1000 -/* Enable merge of flash banks 1/2 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_DATA512 0x0800 -/* Enable SDRAM interface control */ -#define REG_UMI_MMD_ICR_SDRAMEN 0x0400 -/* Polarity of busy state of Burst Wait Signal */ -#define REG_UMI_MMD_ICR_WAITPOL 0x0200 -/* Enable burst clock stopped when not accessing external burst flash/sram */ -#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100 -/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */ -#define REG_UMI_MMD_ICR_PERI1EN 0x0080 -/* Enable the peri2_csn to replace sdram_csn */ -#define REG_UMI_MMD_ICR_PERI2EN 0x0040 -/* Enable the peri3_csn to replace sdram2_csn */ -#define REG_UMI_MMD_ICR_PERI3EN 0x0020 -/* Enable sram bank1 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB1 0x0010 -/* Enable sram bank0 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB0 0x0008 -/* Polarity for assert3ed state of H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSPOL 0x0004 -/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */ -/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */ -#define REG_UMI_MMD_ICR_MRSMODE 0x0002 -/* MRS state for S/W controlled mode */ -#define REG_UMI_MMD_ICR_MRSSTATE 0x0001 - -/* REG_UMI_NAND_TCR bits */ -/* Enable software to control CS */ -#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000 -/* 16-bit nand wordsize if set */ -#define REG_UMI_NAND_TCR_WORD16 0x40000000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060 -/* Read access cycle (n+2) */ -#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_NAND_RCSR bits */ -/* Status: Ready=1, Busy=0 */ -#define REG_UMI_NAND_RCSR_RDY 0x02 -/* Keep CS asserted during operation */ -#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01 - -/* REG_UMI_NAND_ECC_CSR bits */ -/* Interrupt status - read-only */ -#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000 -/* Read: Status of ECC done, Write: clear ECC interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000 -/* Read: Status of R/B, Write: clear R/B interrupt */ -#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000 -/* 1 = Enable ECC Interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000 -/* 1 = Assert interrupt at rising edge of R/B_ */ -#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000 -/* Calculate ECC by 0=512 bytes, 1=256 bytes */ -#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080 -/* Enable ECC in hardware */ -#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001 - -/* REG_UMI_BCH_CTRL_STATUS bits */ -/* Shift to Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20 -/* Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000 -/* Indicate Errors detected during read but uncorrectable */ -#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000 -/* Indicate Errors detected during read and are correctable */ -#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000 -/* Flag indicates BCH's ECC status of read process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000 -/* Flag indicates BCH's ECC status of write process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000 -/* Pause ECC calculation */ -#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010 -/* Enable Interrupt */ -#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004 -/* Enable ECC during read */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002 -/* Enable ECC during write */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001 -/* Mask for location */ -#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF -/* location within a byte */ -#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007 -/* location within a word */ -#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 -/* location within a page (512 byte) */ -#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) -#endif diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h deleted file mode 100644 index 5a94bbb032b6..000000000000 --- a/arch/arm/mach-bcmring/include/mach/timer.h +++ /dev/null @@ -1,77 +0,0 @@ -/***************************************************************************** -* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* timer.h -* -* PURPOSE: -* -* -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(BCM_LINUX_TIMER_H) -#define BCM_LINUX_TIMER_H - -#if defined(__KERNEL__) - -/* ---- Include Files ---------------------------------------------------- */ -/* ---- Constants and Types ---------------------------------------------- */ - -typedef unsigned int timer_tick_count_t; -typedef unsigned int timer_tick_rate_t; -typedef unsigned int timer_msec_t; - -/* ---- Variable Externs ------------------------------------------------- */ -/* ---- Function Prototypes ---------------------------------------------- */ - -/**************************************************************************** -* -* timer_get_tick_count -* -* -***************************************************************************/ -timer_tick_count_t timer_get_tick_count(void); - -/**************************************************************************** -* -* timer_get_tick_rate -* -* -***************************************************************************/ -timer_tick_rate_t timer_get_tick_rate(void); - -/**************************************************************************** -* -* timer_get_msec -* -* -***************************************************************************/ -timer_msec_t timer_get_msec(void); - -/**************************************************************************** -* -* timer_ticks_to_msec -* -* -***************************************************************************/ -timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks); - -#endif /* __KERNEL__ */ -#endif /* BCM_LINUX_TIMER_H */ diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h deleted file mode 100644 index 40d033ec5892..000000000000 --- a/arch/arm/mach-bcmring/include/mach/timex.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * - * Integrator architecture timex specifications - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * Specifies the number of ticks per second - */ -#define CLOCK_TICK_RATE 100000 /* REG_SMT_TICKS_PER_SEC */ diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h deleted file mode 100644 index 9c9821b77977..000000000000 --- a/arch/arm/mach-bcmring/include/mach/uncompress.h +++ /dev/null @@ -1,43 +0,0 @@ -/***************************************************************************** -* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ -#include <mach/csp/mm_addr.h> - -#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA) -#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18)) -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - /* Send out UARTA */ - while (BCMRING_UART_0_FR & (1 << 5)) - ; - - BCMRING_UART_0_DR = c; -} - - -static inline void flush(void) -{ - /* Wait for the tx fifo to be empty */ - while ((BCMRING_UART_0_FR & (1 << 7)) == 0) - ; - - /* Wait for the final character to be sent on the txd line */ - while (BCMRING_UART_0_FR & (1 << 3)) - ; -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c deleted file mode 100644 index 437fa683bcb2..000000000000 --- a/arch/arm/mach-bcmring/irq.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/init.h> -#include <linux/stddef.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> -#include <mach/csp/intcHw_reg.h> -#include <mach/csp/mm_io.h> - -static void bcmring_mask_irq0(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_INTC0_START), - MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR); -} - -static void bcmring_unmask_irq0(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_INTC0_START), - MM_IO_BASE_INTC0 + INTCHW_INTENABLE); -} - -static void bcmring_mask_irq1(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_INTC1_START), - MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR); -} - -static void bcmring_unmask_irq1(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_INTC1_START), - MM_IO_BASE_INTC1 + INTCHW_INTENABLE); -} - -static void bcmring_mask_irq2(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_SINTC_START), - MM_IO_BASE_SINTC + INTCHW_INTENCLEAR); -} - -static void bcmring_unmask_irq2(struct irq_data *d) -{ - writel(1 << (d->irq - IRQ_SINTC_START), - MM_IO_BASE_SINTC + INTCHW_INTENABLE); -} - -static struct irq_chip bcmring_irq0_chip = { - .name = "ARM-INTC0", - .irq_ack = bcmring_mask_irq0, - .irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ - .irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ -}; - -static struct irq_chip bcmring_irq1_chip = { - .name = "ARM-INTC1", - .irq_ack = bcmring_mask_irq1, - .irq_mask = bcmring_mask_irq1, - .irq_unmask = bcmring_unmask_irq1, -}; - -static struct irq_chip bcmring_irq2_chip = { - .name = "ARM-SINTC", - .irq_ack = bcmring_mask_irq2, - .irq_mask = bcmring_mask_irq2, - .irq_unmask = bcmring_unmask_irq2, -}; - -static void vic_init(void __iomem *base, struct irq_chip *chip, - unsigned int irq_start, unsigned int vic_sources) -{ - unsigned int i; - for (i = 0; i < 32; i++) { - unsigned int irq = irq_start + i; - irq_set_chip(irq, chip); - irq_set_chip_data(irq, base); - - if (vic_sources & (1 << i)) { - irq_set_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } - writel(0, base + INTCHW_INTSELECT); - writel(0, base + INTCHW_INTENABLE); - writel(~0, base + INTCHW_INTENCLEAR); - writel(0, base + INTCHW_IRQSTATUS); - writel(~0, base + INTCHW_SOFTINTCLEAR); -} - -void __init bcmring_init_irq(void) -{ - vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip, - IRQ_INTC0_START, IRQ_INTC0_VALID_MASK); - vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip, - IRQ_INTC1_START, IRQ_INTC1_VALID_MASK); - vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip, - IRQ_SINTC_START, IRQ_SINTC_VALID_MASK); - - /* special cases */ - if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { - irq_set_handler(IRQ_GPIO0, handle_simple_irq); - } - if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { - irq_set_handler(IRQ_GPIO1, handle_simple_irq); - } -} diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c deleted file mode 100644 index 1adec78ec940..000000000000 --- a/arch/arm/mach-bcmring/mm.c +++ /dev/null @@ -1,60 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <asm/page.h> -#include <asm/mach/map.h> - -#include <mach/hardware.h> -#include <mach/csp/mm_io.h> - -#define IO_DESC(va, sz) { .virtual = va, \ - .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ - .length = sz, \ - .type = MT_DEVICE } - -#define MEM_DESC(va, sz) { .virtual = va, \ - .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ - .length = sz, \ - .type = MT_MEMORY } - -static struct map_desc bcmring_io_desc[] __initdata = { - IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */ - IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */ - - IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */ - MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */ - - IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */ - IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */ - IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD, - SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */ -}; - -void __init bcmring_map_io(void) -{ - - iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc)); - /* Maximum DMA memory allowed is 14M */ - init_consistent_dma_size(14 << 20); -} diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c deleted file mode 100644 index af9c3d7e2a0c..000000000000 --- a/arch/arm/mach-bcmring/timer.c +++ /dev/null @@ -1,61 +0,0 @@ -/***************************************************************************** -* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -#include <linux/types.h> -#include <linux/module.h> -#include <csp/tmrHw.h> - -#include <mach/timer.h> -/* The core.c file initializes timers 1 and 3 as a linux clocksource. */ -/* The real time clock should probably be the real linux clocksource. */ -/* In the meantime, this file should agree with core.c as to the */ -/* profiling timer. If the clocksource is moved to rtc later, then */ -/* we can init the profiling timer here instead. */ - -/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */ -/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */ -/* affect synchronization with scheduling and APM timing. */ - -#define PROF_TIMER 1 - -timer_tick_rate_t timer_get_tick_rate(void) -{ - return tmrHw_getCountRate(PROF_TIMER); -} - -timer_tick_count_t timer_get_tick_count(void) -{ - return tmrHw_GetCurrentCount(PROF_TIMER); /* change downcounter to upcounter */ -} - -timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks) -{ - static int tickRateMsec; - - if (tickRateMsec == 0) { - tickRateMsec = timer_get_tick_rate() / 1000; - } - - return ticks / tickRateMsec; -} - -timer_msec_t timer_get_msec(void) -{ - return timer_ticks_to_msec(timer_get_tick_count()); -} - -EXPORT_SYMBOL(timer_get_tick_count); -EXPORT_SYMBOL(timer_ticks_to_msec); -EXPORT_SYMBOL(timer_get_tick_rate); -EXPORT_SYMBOL(timer_get_msec); diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index ea036d621581..e6135363765a 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -16,12 +16,6 @@ config ARCH_CDB89712 The board includes 2 serial ports, Ethernet, IRDA, and expansion headers. It comes with 16 MB SDRAM and 8 MB flash ROM. -config ARCH_CEIVA - bool "CEIVA" - help - Say Y here if you intend to run this kernel on the Ceiva/Polaroid - PhotoMax Digital Picture Frame. - config ARCH_CLEP7312 bool "CLEP7312" help diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index 5872b49bfaed..6da6940b3656 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -9,7 +9,6 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_CEIVA) += ceiva.o obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c deleted file mode 100644 index a70147e347ac..000000000000 --- a/arch/arm/mach-clps711x/ceiva.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * linux/arch/arm/mach-clps711x/arch-ceiva.c - * - * Copyright (C) 2002, Rob Scott <rscott@mtrob.fdns.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/init.h> -#include <linux/types.h> -#include <linux/string.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <linux/kernel.h> - -#include <mach/hardware.h> -#include <asm/page.h> -#include <asm/pgtable.h> -#include <asm/sizes.h> - -#include <asm/mach/map.h> - -#include "common.h" - -static struct map_desc ceiva_io_desc[] __initdata = { - /* SED1355 controlled video RAM & registers */ - { - .virtual = CEIVA_VIRT_SED1355, - .pfn = __phys_to_pfn(CEIVA_PHYS_SED1355), - .length = SZ_2M, - .type = MT_DEVICE - } -}; - - -static void __init ceiva_map_io(void) -{ - clps711x_map_io(); - iotable_init(ceiva_io_desc, ARRAY_SIZE(ceiva_io_desc)); -} - - -MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame") - /* Maintainer: Rob Scott */ - .atag_offset = 0x100, - .map_io = ceiva_map_io, - .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, - .restart = clps711x_restart, -MACHINE_END diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 3a4af00db9e3..509243d89a32 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -19,23 +19,25 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/kernel.h> -#include <linux/mm.h> +#include <linux/io.h> #include <linux/init.h> #include <linux/interrupt.h> -#include <linux/io.h> #include <linux/irq.h> -#include <linux/sched.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> #include <asm/sizes.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/system_misc.h> +#include <mach/hardware.h> + +static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, + *clk_tint, *clk_spi; +static unsigned long latch; + /* * This maps the generic CLPS711x registers */ @@ -165,8 +167,8 @@ void __init clps711x_init_irq(void) static unsigned long clps711x_gettimeoffset(void) { unsigned long hwticks; - hwticks = LATCH - (clps_readl(TC2D) & 0xffff); /* since last underflow */ - return (hwticks * (tick_nsec / 1000)) / LATCH; + hwticks = latch - (clps_readl(TC2D) & 0xffff); + return (hwticks * (tick_nsec / 1000)) / latch; } /* @@ -184,15 +186,71 @@ static struct irqaction clps711x_timer_irq = { .handler = p720t_timer_interrupt, }; +static void add_fixed_clk(struct clk *clk, const char *name, int rate) +{ + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); + clk_register_clkdev(clk, name, NULL); +} + static void __init clps711x_timer_init(void) { - unsigned int syscon; + int osc, ext, pll, cpu, bus, timl, timh, uart, spi; + u32 tmp; + + osc = 3686400; + ext = 13000000; + + tmp = clps_readl(PLLR) >> 24; + if (tmp) + pll = (osc * tmp) / 2; + else + pll = 73728000; /* Default value */ + + tmp = clps_readl(SYSFLG2); + if (tmp & SYSFLG2_CKMODE) { + cpu = ext; + bus = cpu; + spi = 135400; + } else { + cpu = pll; + if (cpu >= 36864000) + bus = cpu / 2; + else + bus = 36864000 / 2; + spi = cpu / 576; + } + + uart = bus / 10; + + if (tmp & SYSFLG2_CKMODE) { + tmp = clps_readl(SYSCON2); + if (tmp & SYSCON2_OSTB) + timh = ext / 26; + else + timh = 541440; + } else + timh = cpu / 144; + + timl = timh / 256; + + /* All clocks are fixed */ + add_fixed_clk(clk_pll, "pll", pll); + add_fixed_clk(clk_bus, "bus", bus); + add_fixed_clk(clk_uart, "uart", uart); + add_fixed_clk(clk_timerl, "timer_lf", timl); + add_fixed_clk(clk_timerh, "timer_hf", timh); + add_fixed_clk(clk_tint, "tint", 64); + add_fixed_clk(clk_spi, "spi", spi); + + pr_info("CPU frequency set at %i Hz.\n", cpu); + + latch = (timh + HZ / 2) / HZ; - syscon = clps_readl(SYSCON1); - syscon |= SYSCON1_TC2S | SYSCON1_TC2M; - clps_writel(syscon, SYSCON1); + tmp = clps_readl(SYSCON1); + tmp |= SYSCON1_TC2S | SYSCON1_TC2M; + clps_writel(tmp, SYSCON1); - clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ + clps_writel(latch - 1, TC2D); setup_irq(IRQ_TC2OI, &clps711x_timer_irq); } diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 1dd806f2847e..c82e21ca49c7 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -31,8 +31,8 @@ #define PBDDR (0x0041) #define PCDDR (0x0042) #define PDDDR (0x0043) -#define PEDR (0x0080) -#define PEDDR (0x00c0) +#define PEDR (0x0083) +#define PEDDR (0x00c3) #define SYSCON1 (0x0100) #define SYSFLG1 (0x0140) #define MEMCFG1 (0x0180) @@ -77,7 +77,7 @@ #define KBDEOI (0x1700) #define DAIR (0x2000) -#define DAIR0 (0x2040) +#define DAIDR0 (0x2040) #define DAIDR1 (0x2080) #define DAIDR2 (0x20c0) #define DAISR (0x2100) @@ -191,8 +191,7 @@ #define UBRLCR_WRDLEN8 (3 << 17) #define UBRLCR_WRDLEN_MASK (3 << 17) -#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7) -#define SYNCIO_CFGLEN(x) ((x) & 0x7f) +#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index 118b3d930573..cb3684f8dae0 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S @@ -28,17 +28,11 @@ .endm .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx - tst \rd, #1 << 11 @ UBUSYx - bne 1001b .endm .macro busyuart,rd,rx - tst \rx, #0x1000 @ UART2 does not have CTS here - bne 1002f 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx - tst \rd, #1 << 8 @ CTS + tst \rd, #1 << 11 @ UBUSYx bne 1001b -1002: .endm diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 13a64fcd7dd1..8497775d6ee5 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -116,7 +116,6 @@ #endif /* CONFIG_ARCH_EDB7211 */ - /* * Relevant bits in port D, which controls power to the various parts of * the LCD on the EDB7211. @@ -125,51 +124,4 @@ #define EDB_PD2_LCDEN (1<<2) #define EDB_PD3_LCDBL (1<<3) - -#if defined (CONFIG_ARCH_CEIVA) - -/* - * The two flash banks are wired to chip selects 0 and 1. This is the mapping - * for them. - * - * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running - * in jumpered boot mode. - */ -#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ -#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ - -#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */ -#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */ - -#define CEIVA_FLASH_SIZE 0x100000 -#define CEIVA_FLASH_WIDTH 2 - -/* - * SED1355 LCD controller - */ -#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE -#define CEIVA_VIRT_SED1355 (0xfc000000) - -/* - * Relevant bits in port D, which controls power to the various parts of - * the LCD on the Ceiva Photo Max, and reset to the LCD controller. - */ - -// Reset line to SED1355 (must be high to operate) -#define CEIVA_PD1_LCDRST (1<<1) -// LCD panel enable (set to one, to enable LCD) -#define CEIVA_PD4_LCDEN (1<<4) -// Backlight (set to one, to turn on backlight -#define CEIVA_PD5_LCDBL (1<<5) - -/* - * Relevant bits in port B, which report the status of the buttons. - */ - -// White button -#define CEIVA_PB4_WHT_BTN (1<<4) -// Black button -#define CEIVA_PB0_BLK_BTN (1<<0) -#endif // #if defined (CONFIG_ARCH_CEIVA) - #endif diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h index ac8823ccff93..de6fd192d1c3 100644 --- a/arch/arm/mach-clps711x/include/mach/timex.h +++ b/arch/arm/mach-clps711x/include/mach/timex.h @@ -1,23 +1,2 @@ -/* - * arch/arm/mach-clps711x/include/mach/timex.h - * - * Prospector 720T architecture timex specifications - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - +/* Bogus value */ #define CLOCK_TICK_RATE 512000 diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6321567d8eaa..bd54d7b7ef85 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = { .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE0_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), - .length = DOVE_PCIE0_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = DOVE_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), - .length = DOVE_PCIE1_IO_SIZE, - .type = MT_DEVICE, }, }; @@ -289,7 +279,7 @@ void __init dove_init(void) printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); #ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(); + tauros2_init(0); #endif dove_setup_cpu_mbus(); diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index d52b0ef313b7..c91e3004a47b 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -50,14 +50,12 @@ #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_1M +#define DOVE_PCIE0_IO_SIZE SZ_64K #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 -#define DOVE_PCIE1_IO_SIZE SZ_1M +#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 +#define DOVE_PCIE1_IO_SIZE SZ_64K /* * Dove Core Registers Map diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h deleted file mode 100644 index 29c8b85355a5..000000000000 --- a/arch/arm/mach-dove/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "dove.h" - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \ - DOVE_PCIE0_IO_VIRT_BASE)) - -#endif diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 47921b0cdc65..355332d502cb 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -26,9 +26,8 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[2]; @@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; - } else { - pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; - pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + if (pp->index == 0) + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); + else + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); /* * IORESOURCE_MEM @@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res.name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; } else { - pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; + pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk(KERN_INFO "link down, ignoring\n"); } diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 6f8068692edf..f0fe6b5350e2 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = { * sparse external-decode ISAIO space */ { /* IRQ_STAT/IRQ_MCLR */ - .virtual = IRQ_STAT, + .virtual = (unsigned long)IRQ_STAT, .pfn = __phys_to_pfn(TRICK4_PHYS), .length = TRICK4_SIZE, .type = MT_DEVICE }, { /* IRQ_MASK/IRQ_MSET */ - .virtual = IRQ_MASK, + .virtual = (unsigned long)IRQ_MASK, .pfn = __phys_to_pfn(TRICK3_PHYS), .length = TRICK3_SIZE, .type = MT_DEVICE }, { /* SOFT_BASE */ - .virtual = SOFT_BASE, + .virtual = (unsigned long)SOFT_BASE, .pfn = __phys_to_pfn(TRICK1_PHYS), .length = TRICK1_SIZE, .type = MT_DEVICE }, { /* PIT_BASE */ - .virtual = PIT_BASE, + .virtual = (unsigned long)PIT_BASE, .pfn = __phys_to_pfn(TRICK0_PHYS), .length = TRICK0_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h index c93c9e43012d..afe137ee172e 100644 --- a/arch/arm/mach-ebsa110/core.h +++ b/arch/arm/mach-ebsa110/core.h @@ -31,11 +31,11 @@ #define TRICK7_PHYS 0xf3c00000 /* Virtual addresses */ -#define PIT_BASE 0xfc000000 /* trick 0 */ -#define SOFT_BASE 0xfd000000 /* trick 1 */ -#define IRQ_MASK 0xfe000000 /* trick 3 - read */ -#define IRQ_MSET 0xfe000000 /* trick 3 - write */ -#define IRQ_STAT 0xff000000 /* trick 4 - read */ -#define IRQ_MCLR 0xff000000 /* trick 4 - write */ +#define PIT_BASE IOMEM(0xfc000000) /* trick 0 */ +#define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */ +#define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */ +#define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */ +#define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */ +#define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */ #endif diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index a472777e9eba..41383bf03d4b 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/sizes.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 437c34111155..7fd705b5efe4 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/sizes.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 75cab2d7ec73..3c4c233391dc 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -21,7 +21,6 @@ #include <linux/mtd/partitions.h> #include <mach/hardware.h> -#include <mach/ts72xx.h> #include <asm/hardware/vic.h> #include <asm/mach-types.h> @@ -29,30 +28,31 @@ #include <asm/mach/arch.h> #include "soc.h" +#include "ts72xx.h" static struct map_desc ts72xx_io_desc[] __initdata = { { - .virtual = TS72XX_MODEL_VIRT_BASE, + .virtual = (unsigned long)TS72XX_MODEL_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), .length = TS72XX_MODEL_SIZE, .type = MT_DEVICE, }, { - .virtual = TS72XX_OPTIONS_VIRT_BASE, + .virtual = (unsigned long)TS72XX_OPTIONS_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), .length = TS72XX_OPTIONS_SIZE, .type = MT_DEVICE, }, { - .virtual = TS72XX_OPTIONS2_VIRT_BASE, + .virtual = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), .length = TS72XX_OPTIONS2_SIZE, .type = MT_DEVICE, }, { - .virtual = TS72XX_RTC_INDEX_VIRT_BASE, + .virtual = (unsigned long)TS72XX_RTC_INDEX_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE), .length = TS72XX_RTC_INDEX_SIZE, .type = MT_DEVICE, }, { - .virtual = TS72XX_RTC_DATA_VIRT_BASE, + .virtual = (unsigned long)TS72XX_RTC_DATA_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE), .length = TS72XX_RTC_DATA_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h index f1397a13e76b..071feaa30adc 100644 --- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h +++ b/arch/arm/mach-ep93xx/ts72xx.h @@ -14,7 +14,7 @@ */ #define TS72XX_MODEL_PHYS_BASE 0x22000000 -#define TS72XX_MODEL_VIRT_BASE 0xfebff000 +#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) #define TS72XX_MODEL_SIZE 0x00001000 #define TS72XX_MODEL_TS7200 0x00 @@ -26,7 +26,7 @@ #define TS72XX_OPTIONS_PHYS_BASE 0x22400000 -#define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000 +#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) #define TS72XX_OPTIONS_SIZE 0x00001000 #define TS72XX_OPTIONS_COM2_RS485 0x02 @@ -34,18 +34,18 @@ #define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 -#define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000 +#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) #define TS72XX_OPTIONS2_SIZE 0x00001000 #define TS72XX_OPTIONS2_TS9420 0x04 #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 -#define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 +#define TS72XX_RTC_INDEX_VIRT_BASE IOMEM(0xfebf9000) #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 #define TS72XX_RTC_INDEX_SIZE 0x00001000 -#define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 +#define TS72XX_RTC_DATA_VIRT_BASE IOMEM(0xfebf8000) #define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 #define TS72XX_RTC_DATA_SIZE 0x00001000 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 195b50eb1e57..412884dafa6c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -420,8 +420,8 @@ config MACH_EXYNOS5_DT select USE_OF select ARM_AMBA help - Machine support for Samsung Exynos4 machine with device tree enabled. - Select this if a fdt blob is available for the EXYNOS4 SoC based board. + Machine support for Samsung EXYNOS5 machine with device tree enabled. + Select this if a fdt blob is available for the EXYNOS5 SoC based board. if ARCH_EXYNOS4 diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 2f51293c1875..6a45c9a9abe9 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_cam_ctrl, .ctrlbit = (1 << 3), }, { + .name = "tsi", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 4), + }, { .name = "hsmmc", .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_aclk_133.clk, @@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { + .name = "onenand", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "nfcon", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 16), + }, { .name = "dac", .devname = "s5p-sdo", .enable = exynos4_clk_ip_tv_ctrl, @@ -615,6 +627,25 @@ static struct clk exynos4_init_clocks_off[] = { .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 21), }, { + .name = "pcm", + .devname = "samsung-pcm.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 22), + }, { + .name = "pcm", + .devname = "samsung-pcm.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 23), + }, { + .name = "slimbus", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "spdif", + .devname = "samsung-spdif", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 26), + }, { .name = "ac97", .devname = "samsung-ac97", .enable = exynos4_clk_ip_peril_ctrl, diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 1f819ffebbf1..f3171c3f3d94 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); } -static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable); -} - static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); @@ -734,10 +729,6 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), }, { - .name = "gps", - .enable = exynos5_clk_ip_gps_ctrl, - .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)), - }, { .name = "nfcon", .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 22), @@ -973,6 +964,13 @@ static struct clk exynos5_clk_mdma1 = { .ctrlbit = (1 << 4), }; +static struct clk exynos5_clk_fimd1 = { + .name = "fimd", + .devname = "exynos5-fb.1", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 0), +}; + struct clk *exynos5_clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = NULL, @@ -1202,6 +1200,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, }; +struct clksrc_clk exynos5_clk_sclk_fimd1 = { + .clk = { + .name = "sclk_fimd", + .devname = "exynos5-fb.1", + .enable = exynos5_clksrc_mask_disp1_0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1213,16 +1223,6 @@ static struct clksrc_clk exynos5_clksrcs[] = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, }, { .clk = { - .name = "sclk_fimd", - .devname = "s3cfb.1", - .enable = exynos5_clksrc_mask_disp1_0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, - }, { - .clk = { .name = "aclk_266_gscl", }, .sources = &clk_src_gscl_266, @@ -1326,12 +1326,14 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_mdout_spi0, &exynos5_clk_mdout_spi1, &exynos5_clk_mdout_spi2, + &exynos5_clk_sclk_fimd1, }; static struct clk *exynos5_clk_cdev[] = { &exynos5_clk_pdma0, &exynos5_clk_pdma1, &exynos5_clk_mdma1, + &exynos5_clk_fimd1, }; static struct clksrc_clk *exynos5_clksrc_cdev[] = { @@ -1360,6 +1362,7 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), + CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1), }; static unsigned long exynos5_epll_get_rate(struct clk *clk) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 0300d7adc151..5aa77f996e59 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -89,7 +89,7 @@ #define EXYNOS4_PA_L2CC 0x10502000 #define EXYNOS4_PA_MDMA0 0x10810000 -#define EXYNOS4_PA_MDMA1 0x12840000 +#define EXYNOS4_PA_MDMA1 0x12850000 #define EXYNOS4_PA_PDMA0 0x12680000 #define EXYNOS4_PA_PDMA1 0x12690000 #define EXYNOS5_PA_MDMA0 0x10800000 @@ -136,7 +136,6 @@ #define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 #define EXYNOS5_PA_SYSMMU_IOP 0x12360000 #define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_GPS 0x12630000 #define EXYNOS5_PA_SYSMMU_ISP 0x13260000 #define EXYNOS5_PA_SYSMMU_DRC 0x12370000 #define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h index 998daf2add92..88a4543b0001 100644 --- a/arch/arm/mach-exynos/include/mach/sysmmu.h +++ b/arch/arm/mach-exynos/include/mach/sysmmu.h @@ -58,7 +58,7 @@ static inline void platform_set_sysmmu( #endif #else /* !CONFIG_EXYNOS_DEV_SYSMMU */ -#define platform_set_sysmmu(dev, sysmmu) do { } while (0) +#define platform_set_sysmmu(sysmmu, dev) do { } while (0) #endif #define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id) diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 3e6aaa6361da..a42b369bc439 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/spinlock.h> - + #include <asm/pgtable.h> #include <asm/page.h> #include <asm/irq.h> @@ -26,6 +26,7 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "common.h" @@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_PCI_IACK), .length = PCIIACK_SIZE, .type = MT_DEVICE, - }, { - .virtual = PCIO_BASE, - .pfn = __phys_to_pfn(DC21285_PCI_IO), - .length = PCIO_SIZE, - .type = MT_DEVICE, }, #endif }; @@ -196,8 +192,10 @@ void __init footbridge_map_io(void) * Now, work out what we've got to map in addition on this * platform. */ - if (footbridge_cfn_mode()) + if (footbridge_cfn_mode()) { iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); + pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); + } } void footbridge_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 9d62e3381024..a7cd2cf5e08d 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); + pci_ioremap_io(0, DC21285_PCI_IO); + pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,14 +350,6 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { - static struct resource csrio; - - csrio.flags = IORESOURCE_IO; - csrio.name = "Footbridge"; - - allocate_resource(&ioport_resource, &csrio, 128, - 0xff00, 0xffff, 128, NULL, NULL); - /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -365,7 +357,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = csrio.start; + *CSR_PCICSRIOBASE = 0; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index e5acde25ffc5..c169f0c99b2a 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -17,7 +17,8 @@ /* For NetWinder debugging */ .macro addruart, rp, rv, tmp mov \rp, #0x000003f8 - orr \rv, \rp, #0xff000000 @ virtual + orr \rv, \rp, #0xfe000000 @ virtual + orr \rv, \rv, #0x00e00000 @ virtual orr \rp, \rp, #0x7c000000 @ physical .endm diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index aba531eebbc6..aba46388cc0c 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -14,18 +14,10 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#ifdef CONFIG_MMU -#define MMU_IO(a, b) (a) -#else -#define MMU_IO(a, b) (b) -#endif - -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) - /* - * Translation of various region addresses to virtual addresses + * Translation of various i/o addresses to host addresses for !CONFIG_MMU */ +#define PCIO_BASE 0x7c000000 #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) #endif diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index ca70e5fcc7ac..020852d3bdd8 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -17,6 +17,7 @@ #include <linux/sched.h> #include <asm/irq.h> #include <asm/mach/irq.h> +#include <asm/system_misc.h> #include <mach/hardware.h> #define IRQ_SOURCE(base_addr) (base_addr + 0x00) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index afd542ad6f97..7ca5fe45945f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -101,13 +101,8 @@ config SOC_IMX51 select SOC_IMX5 select ARCH_MX5 select ARCH_MX51 - -config SOC_IMX53 - bool - select SOC_IMX5 - select ARCH_MX5 - select ARCH_MX53 - select HAVE_CAN_FLEXCAN if CAN + select PINCTRL + select PINCTRL_IMX51 if ARCH_IMX_V4_V5 @@ -561,7 +556,6 @@ config MACH_BUG config MACH_IMX31_DT bool "Support i.MX31 platforms from device tree" select SOC_IMX31 - select USE_OF help Include support for Freescale i.MX31 based platforms using the device tree for discovery. @@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD endchoice -config MX51_EFIKA_COMMON - bool - select SOC_IMX51 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_PATA_IMX - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - -config MACH_MX51_EFIKAMX - bool "Support MX51 Genesi Efika MX nettop" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika MX nettop. This includes specific - configurations for the board and its peripherals. - -config MACH_MX51_EFIKASB - bool "Support MX51 Genesi Efika Smartbook" - select LEDS_GPIO_REGISTER - select MX51_EFIKA_COMMON - help - Include support for Genesi Efika Smartbook. This includes specific - configurations for the board and its peripherals. - -comment "i.MX53 machines:" - -config MACH_IMX53_DT - bool "Support i.MX53 platforms from device tree" - select SOC_IMX53 - select MACH_MX53_ARD - select MACH_MX53_EVK - select MACH_MX53_LOCO - select MACH_MX53_SMD - help - Include support for Freescale i.MX53 based platforms - using the device tree for discovery - -config MACH_MX53_EVK - bool "Support MX53 EVK platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - Include support for MX53 EVK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX53_SMD - bool "Support MX53 SMD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for MX53 SMD platform. This includes specific - configurations for the board and its peripherals. +comment "Device tree only" -config MACH_MX53_LOCO - bool "Support MX53 LOCO platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS - select LEDS_GPIO_REGISTER - help - Include support for MX53 LOCO platform. This includes specific - configurations for the board and its peripherals. +config SOC_IMX53 + bool "i.MX53 support" + select SOC_IMX5 + select ARCH_MX5 + select ARCH_MX53 + select HAVE_CAN_FLEXCAN if CAN + select PINCTRL + select PINCTRL_IMX53 -config MACH_MX53_ARD - bool "Support MX53 ARD platforms" - select SOC_IMX53 - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_GPIO_KEYS help - Include support for MX53 ARD platform. This includes specific - configurations for the board and its peripherals. - -comment "i.MX6 family:" + This enables support for Freescale i.MX53 processor. config SOC_IMX6Q bool "i.MX6 Quad support" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d004d37ad9d8..895754aeb4f3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ - clk-pfd.o clk-busy.o + clk-pfd.o clk-busy.o clk.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o @@ -83,16 +83,9 @@ endif # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o -obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o -obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o -obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o -obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o -obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o -obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o -obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o -obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o +obj-$(CONFIG_SOC_IMX53) += mach-imx53.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 05541cf4a878..c60967629e27 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb -dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ - imx53-qsb.dtb imx53-smd.dtb + +dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \ + imx53-evk.dtb \ + imx53-qsb.dtb \ + imx53-smd.dtb \ + dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index ea13e61bd5f3..cf65148bc519 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -23,7 +23,6 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/clkdev.h> #include <linux/err.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index fdd8cc87c9fe..d20d4795f4ea 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -222,10 +222,8 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0"); clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0"); clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0"); - clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1"); - clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1"); + clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0"); + clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1"); clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); @@ -243,6 +241,6 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); clk_register_clkdev(clk[iim_ipg], "iim", NULL); - mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); + mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); return 0; } diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index c6422fb10bae..177259b523cd 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -62,8 +62,8 @@ enum mx35_clks { kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, - wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate, - clk_max + wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, + gpu2d_gate, clk_max }; static struct clk *clk[clk_max]; @@ -142,6 +142,9 @@ int __init mx35_clocks_init() clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); + clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); + clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); + clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); @@ -192,7 +195,7 @@ int __init mx35_clocks_init() clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); - clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0); + clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); @@ -228,12 +231,11 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2"); clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); + clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0"); - clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1"); - clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1"); + clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); + clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); /* i.mx35 has the i.mx21 type uart */ clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); @@ -255,6 +257,7 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0"); + clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); clk_prepare_enable(clk[spba_gate]); clk_prepare_enable(clk[gpio1_gate]); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 4bdcaa97bd98..e5165a84f93f 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -39,16 +39,17 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; static const char *emi_slow_sel[] = { "main_bus", "ahb", }; static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; -static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", }; +static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; -static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", }; +static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; +static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; enum imx5_clks { dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, @@ -82,6 +83,7 @@ enum imx5_clks { ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, + can_sel, can1_serial_gate, can1_ipg_gate, clk_max }; @@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8); + clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, + mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); + clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); + clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); + clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); + clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); for (i = 0; i < ARRAY_SIZE(clk); i++) @@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi"); clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi"); + clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can"); + clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can"); + clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can"); + clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can"); /* set SDHC root clock to 200MHZ*/ clk_set_rate(clk[esdhc_a_podf], 200000000); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4233d9e3531d..3ec242f3341e 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -157,6 +157,7 @@ enum mx6q_clks { }; static struct clk *clk[clk_max]; +static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { mmdc_ch0_axi, rom, @@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void) pr_err("i.MX6q clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[twd], NULL, "smp_twd"); - clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); - clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); - clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); - clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); - clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); - clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); - clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); - clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial"); - clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial"); - clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial"); - clk_register_clkdev(clk[enet], NULL, "2188000.ethernet"); - clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc"); - clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc"); - clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc"); - clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc"); - clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c"); - clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c"); - clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c"); - clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi"); - clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi"); - clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi"); - clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi"); - clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi"); - clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma"); - clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog"); - clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog"); - clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi"); clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); + /* + * The gpmi needs 100MHz frequency in the EDO/Sync mode, + * We can not get the 100MHz from the pll2_pfd0_352m. + * So choose pll2_pfd2_396m as enfc_sel's parent. + */ + clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]); diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index 2d856f9ccf59..02be73178912 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -6,7 +6,7 @@ #include <linux/err.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/clock.h> + #include "clk.h" /** @@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv1 *pll = to_clk_pllv1(hw); + long long ll; + int mfn_abs; + unsigned int mfi, mfn, mfd, pd; + u32 reg; + unsigned long rate; + + reg = readl(pll->base); + + /* + * Get the resulting clock rate from a PLL register value and the input + * frequency. PLLs with this register layout can be found on i.MX1, + * i.MX21, i.MX27 and i,MX31 + * + * mfi + mfn / (mfd + 1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ + + mfi = (reg >> 10) & 0xf; + mfn = reg & 0x3ff; + mfd = (reg >> 16) & 0x3ff; + pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + mfn_abs = mfn; + + /* + * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit + * 2's complements number + */ + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + mfn_abs = 0x400 - mfn; + + rate = parent_rate * 2; + rate /= pd + 1; + + ll = (unsigned long long)rate * mfn_abs; + + do_div(ll, mfd + 1); + + if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) + ll = -ll; + + ll = (rate * mfi) + ll; - return mxc_decode_pll(readl(pll->base), parent_rate); + return ll; } struct clk_ops clk_pllv1_ops = { diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c new file mode 100644 index 000000000000..f5e8be8e7f11 --- /dev/null +++ b/arch/arm/mach-imx/clk.c @@ -0,0 +1,3 @@ +#include <linux/spinlock.h> + +DEFINE_SPINLOCK(imx_ccm_lock); diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 1bf64fe2523c..5f2d8acca25f 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -3,7 +3,8 @@ #include <linux/spinlock.h> #include <linux/clk-provider.h> -#include <mach/clock.h> + +extern spinlock_t imx_ccm_lock; struct clk *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h deleted file mode 100644 index 77e0db96c448..000000000000 --- a/arch/arm/mach-imx/devices-imx53.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx53.h> -#include <mach/devices-common.h> - -extern const struct imx_fec_data imx53_fec_data; -#define imx53_add_fec(pdata) \ - imx_add_fec(&imx53_fec_data, pdata) - -extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; -#define imx53_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) - - -extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; -#define imx53_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; -#define imx53_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx53_ecspi_data[]; -#define imx53_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx53_ecspi_data[id], pdata) - -extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; -#define imx53_add_imx2_wdt(id) \ - imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) - -extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; -#define imx53_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata) - -extern const struct imx_imx_keypad_data imx53_imx_keypad_data; -#define imx53_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) - -extern const struct imx_pata_imx_data imx53_pata_imx_data; -#define imx53_add_pata_imx() \ - imx_add_pata_imx(&imx53_pata_imx_data) - -extern struct platform_device *__init imx53_add_ahci_imx(void); diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h deleted file mode 100644 index 014aa985faae..000000000000 --- a/arch/arm/mach-imx/efika.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _EFIKA_H -#define _EFIKA_H - -#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16) -#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10) -#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9) - -void __init efika_board_common_init(void); - -#endif diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index d4067fe36357..f233b4bb2342 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -13,7 +13,6 @@ #include <linux/irq.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> @@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static const struct of_device_id imx51_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, }, - { /* sentinel */ } -}; - static void __init imx51_dt_init(void) { - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - pinctrl_provide_dummies(); - - node = of_find_matching_node(NULL, imx51_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx51_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - of_platform_populate(NULL, of_default_bus_match_table, imx51_auxdata_lookup, NULL); } @@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = { }; static const char *imx51_dt_board_compat[] __initdata = { - "fsl,imx51-babbage", "fsl,imx51", NULL }; diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 2c6ab3273f9e..5985ed1b8c98 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -526,7 +526,8 @@ static void __init armadillo5x0_init(void) imx31_add_mxc_nand(&armadillo5x0_nand_board_info); /* set NAND page size to 2k if not configured via boot mode pins */ - __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); + __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | + (1 << 30), mx3_ccm_base + MXC_CCM_RCSR); /* RTC */ /* Get RTC IRQ and register the chip */ diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c index 1b7a2fc36591..29711e95579f 100644 --- a/arch/arm/mach-imx/imx53-dt.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -17,7 +17,6 @@ #include <linux/irq.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> @@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static const struct of_device_id imx53_iomuxc_of_match[] __initconst = { - { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, }, - { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, }, - { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, }, - { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, }, - { /* sentinel */ } -}; - static void __init imx53_qsb_init(void) { struct clk *clk; @@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void) static void __init imx53_dt_init(void) { - struct device_node *node; - const struct of_device_id *of_id; - void (*func)(void); - - pinctrl_provide_dummies(); - - node = of_find_matching_node(NULL, imx53_iomuxc_of_match); - if (node) { - of_id = of_match_node(imx53_iomuxc_of_match, node); - func = of_id->data; - func(); - of_node_put(node); - } - if (of_machine_is_compatible("fsl,imx53-qsb")) imx53_qsb_init(); @@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = { }; static const char *imx53_dt_board_compat[] __initdata = { - "fsl,imx53-ard", - "fsl,imx53-evk", - "fsl,imx53-qsb", - "fsl,imx53-smd", "fsl,imx53", NULL }; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 045b3f6a387d..692b4b143bb1 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -22,7 +22,6 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> #include <linux/phy.h> #include <linux/micrel_phy.h> #include <linux/mfd/anatop.h> @@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void) clk_set_parent(cko1_sel, ahb); rate = clk_round_rate(cko1, 16000000); clk_set_rate(cko1, rate); - clk_register_clkdev(cko1, NULL, "0-000a"); put_clk: if (!IS_ERR(cko1_sel)) clk_put(cko1_sel); @@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void) static void __init imx6q_init_machine(void) { - /* - * This should be removed when all imx6q boards have pinctrl - * states for devices defined in device tree. - */ - pinctrl_provide_dummies(); - if (of_machine_is_compatible("fsl,imx6q-sabrelite")) imx6q_sabrelite_init(); @@ -218,9 +210,6 @@ static struct sys_timer imx6q_timer = { }; static const char *imx6q_dt_compat[] __initdata = { - "fsl,imx6q-arm2", - "fsl,imx6q-sabrelite", - "fsl,imx6q-sabresd", "fsl,imx6q", NULL, }; diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index 5d08533ab2c7..0330078ff788 100644 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -36,7 +36,6 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/clock.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx3.h> @@ -259,13 +258,13 @@ static void __init kzm_board_init(void) */ static struct map_desc kzm_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE }, { - .virtual = MX31_CS5_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), .length = MX31_CS5_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index d37f4809c556..e774b07f48d3 100644 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c @@ -540,7 +540,7 @@ static void __init mxc_init_audio(void) */ static struct map_desc mx31ads_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = CS4_CS8900_MMIO_START, .type = MT_DEVICE diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index c8785b39eaed..ef57cff5abfb 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = { */ static struct map_desc mx31lite_io_desc[] __initdata = { { - .virtual = MX31_CS4_BASE_ADDR_VIRT, + .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c deleted file mode 100644 index 8d09c0126cab..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikamx.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/system_info.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) -#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) -#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) - -#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) -#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) -#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) - -#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) - -/* board 1.1 doesn't have same reset gpio */ -#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) -#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) - -#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -/* the pci ids pin have pull up. they're driven low according to board id */ -#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) - -static iomux_v3_cfg_t mx51efikamx_pads[] = { - /* board id */ - MX51_PAD_PCBID0, - MX51_PAD_PCBID1, - MX51_PAD_PCBID2, - - /* leds */ - MX51_PAD_CSI1_D9__GPIO3_13, - MX51_PAD_CSI1_VSYNC__GPIO3_14, - MX51_PAD_CSI1_HSYNC__GPIO3_15, - - /* power key */ - MX51_PAD_PWRKEY, - - /* reset */ - MX51_PAD_DI1_PIN13__GPIO3_2, - MX51_PAD_GPIO1_4__GPIO1_4, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, -}; - -/* PCBID2 PCBID1 PCBID0 STATE - 1 1 1 ER1:rev1.1 - 1 1 0 ER2:rev1.2 - 1 0 1 ER3:rev1.3 - 1 0 0 ER4:rev1.4 -*/ -static void __init mx51_efikamx_board_id(void) -{ - int id; - - /* things are taking time to settle */ - msleep(150); - - gpio_request(EFIKAMX_PCBID0, "pcbid0"); - gpio_direction_input(EFIKAMX_PCBID0); - gpio_request(EFIKAMX_PCBID1, "pcbid1"); - gpio_direction_input(EFIKAMX_PCBID1); - gpio_request(EFIKAMX_PCBID2, "pcbid2"); - gpio_direction_input(EFIKAMX_PCBID2); - - id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1; - id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2; - - switch (id) { - case 7: - system_rev = 0x11; - break; - case 6: - system_rev = 0x12; - break; - case 5: - system_rev = 0x13; - break; - case 4: - system_rev = 0x14; - break; - default: - system_rev = 0x10; - break; - } - - if ((system_rev == 0x10) - || (system_rev == 0x12) - || (system_rev == 0x14)) { - printk(KERN_WARNING - "EfikaMX: Unsupported board revision 1.%u!\n", - system_rev & 0xf); - } -} - -static struct gpio_led mx51_efikamx_leds[] __initdata = { - { - .name = "efikamx:green", - .default_trigger = "default-on", - .gpio = EFIKAMX_GREEN_LED, - }, - { - .name = "efikamx:red", - .default_trigger = "ide-disk", - .gpio = EFIKAMX_RED_LED, - }, - { - .name = "efikamx:blue", - .default_trigger = "mmc0", - .gpio = EFIKAMX_BLUE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikamx_leds_data __initconst = { - .leds = mx51_efikamx_leds, - .num_leds = ARRAY_SIZE(mx51_efikamx_leds), -}; - -static struct esdhc_platform_data sd_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct gpio_keys_button mx51_efikamx_powerkey[] = { - { - .code = KEY_POWER, - .gpio = EFIKAMX_POWER_KEY, - .type = EV_PWR, - .desc = "Power Button (CM)", - .wakeup = 1, - .debounce_interval = 10, /* ms */ - }, -}; - -static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { - .buttons = mx51_efikamx_powerkey, - .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), -}; - -static void mx51_efikamx_restart(char mode, const char *cmd) -{ - if (system_rev == 0x11) - gpio_direction_output(EFIKAMX_RESET1_1, 0); - else - gpio_direction_output(EFIKAMX_RESET, 0); -} - -static struct regulator *pwgt1, *pwgt2, *coincell; - -static void mx51_efikamx_power_off(void) -{ - if (!IS_ERR(coincell)) - regulator_disable(coincell); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKAMX_POWEROFF, 1); -} - -static int __init mx51_efikamx_power_init(void) -{ - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKAMX_POWEROFF, "poweroff"); - pm_power_off = mx51_efikamx_power_off; - - /* enable coincell charger. maybe need a small power driver ? */ - coincell = regulator_get(NULL, "coincell"); - if (!IS_ERR(coincell)) { - regulator_set_voltage(coincell, 3000000, 3000000); - regulator_enable(coincell); - } - - regulator_has_full_constraints(); - - return 0; -} - -static void __init mx51_efikamx_init_late(void) -{ - imx51_init_late(); - mx51_efikamx_power_init(); -} - -static void __init mx51_efikamx_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, - ARRAY_SIZE(mx51efikamx_pads)); - efika_board_common_init(); - - mx51_efikamx_board_id(); - - /* on < 1.2 boards both SD controllers are used */ - if (system_rev < 0x12) { - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_sdhci_esdhc_imx(1, &sd_pdata); - mx51_efikamx_leds[2].default_trigger = "mmc1"; - } else - imx51_add_sdhci_esdhc_imx(0, &sd_pdata); - - gpio_led_register_device(-1, &mx51_efikamx_leds_data); - imx_add_gpio_keys(&mx51_efikamx_powerkey_data); - - if (system_rev == 0x11) { - gpio_request(EFIKAMX_RESET1_1, "reset"); - gpio_direction_output(EFIKAMX_RESET1_1, 1); - } else { - gpio_request(EFIKAMX_RESET, "reset"); - gpio_direction_output(EFIKAMX_RESET, 1); - } - - /* - * enable wifi by default only on mx - * sb and mx have same wlan pin but the value to enable it are - * different :/ - */ - gpio_request(EFIKA_WLAN_EN, "wlan_en"); - gpio_direction_output(EFIKA_WLAN_EN, 0); - msleep(10); - - gpio_request(EFIKA_WLAN_RESET, "wlan_rst"); - gpio_direction_output(EFIKA_WLAN_RESET, 0); - msleep(10); - gpio_set_value(EFIKA_WLAN_RESET, 1); -} - -static void __init mx51_efikamx_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikamx_timer = { - .init = mx51_efikamx_timer_init, -}; - -MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_efikamx_timer, - .init_machine = mx51_efikamx_init, - .init_late = mx51_efikamx_init_late, - .restart = mx51_efikamx_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c deleted file mode 100644 index fdbd181b97ef..000000000000 --- a/arch/arm/mach-imx/mach-mx51_efikasb.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org> - * - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <mach/ulpi.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <asm/setup.h> -#include <asm/system_info.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" - -#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) -#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3) -#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25) -#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28) -#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29) -#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31) -#define EFIKASB_LID IMX_GPIO_NR(3, 14) -#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13) -#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) - -#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) -#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) - -static iomux_v3_cfg_t mx51efikasb_pads[] = { - /* USB HOST2 */ - MX51_PAD_EIM_D16__USBH2_DATA0, - MX51_PAD_EIM_D17__USBH2_DATA1, - MX51_PAD_EIM_D18__USBH2_DATA2, - MX51_PAD_EIM_D19__USBH2_DATA3, - MX51_PAD_EIM_D20__USBH2_DATA4, - MX51_PAD_EIM_D21__USBH2_DATA5, - MX51_PAD_EIM_D22__USBH2_DATA6, - MX51_PAD_EIM_D23__USBH2_DATA7, - MX51_PAD_EIM_A24__USBH2_CLK, - MX51_PAD_EIM_A25__USBH2_DIR, - MX51_PAD_EIM_A26__USBH2_STP, - MX51_PAD_EIM_A27__USBH2_NXT, - - /* leds */ - MX51_PAD_EIM_CS0__GPIO2_25, - MX51_PAD_GPIO1_3__GPIO1_3, - - /* pcb id */ - MX51_PAD_EIM_CS3__GPIO2_28, - MX51_PAD_EIM_CS4__GPIO2_29, - - /* lid */ - MX51_PAD_CSI1_VSYNC__GPIO3_14, - - /* power key*/ - MX51_PAD_PWRKEY, - - /* wifi/bt button */ - MX51_PAD_DI1_PIN12__GPIO3_1, - - /* power off */ - MX51_PAD_CSI2_VSYNC__GPIO4_13, - - /* wdog reset */ - MX51_PAD_GPIO1_4__WDOG1_WDOG_B, - - /* BT */ - MX51_PAD_EIM_A17__GPIO2_11, - - MX51_PAD_SD1_CD, -}; - -static int initialize_usbh2_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; - iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; - - mxc_iomux_v3_setup_pad(usbh2gpio); - gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); - gpio_direction_output(EFIKASB_USBH2_STP, 0); - msleep(1); - gpio_set_value(EFIKASB_USBH2_STP, 1); - msleep(1); - - gpio_free(EFIKASB_USBH2_STP); - mxc_iomux_v3_setup_pad(usbh2stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh2_config __initdata = { - .init = initialize_usbh2_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void __init mx51_efikasb_usb(void) -{ - usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - if (usbh2_config.otg) - imx51_add_mxc_ehci_hs(2, &usbh2_config); -} - -static const struct gpio_led mx51_efikasb_leds[] __initconst = { - { - .name = "efikasb:green", - .default_trigger = "default-on", - .gpio = EFIKASB_GREEN_LED, - .active_low = 1, - }, - { - .name = "efikasb:white", - .default_trigger = "caps", - .gpio = EFIKASB_WHITE_LED, - }, -}; - -static const struct gpio_led_platform_data - mx51_efikasb_leds_data __initconst = { - .leds = mx51_efikasb_leds, - .num_leds = ARRAY_SIZE(mx51_efikasb_leds), -}; - -static struct gpio_keys_button mx51_efikasb_keys[] = { - { - .code = KEY_POWER, - .gpio = EFIKASB_PWRKEY, - .type = EV_KEY, - .desc = "Power Button", - .wakeup = 1, - .active_low = 1, - }, - { - .code = SW_LID, - .gpio = EFIKASB_LID, - .type = EV_SW, - .desc = "Lid Switch", - .active_low = 1, - }, - { - .code = KEY_RFKILL, - .gpio = EFIKASB_RFKILL, - .type = EV_KEY, - .desc = "rfkill", - .active_low = 1, - }, -}; - -static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = { - .buttons = mx51_efikasb_keys, - .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), -}; - -static struct esdhc_platform_data sd0_pdata = { -#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) - .cd_gpio = EFIKASB_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static struct regulator *pwgt1, *pwgt2; - -static void mx51_efikasb_power_off(void) -{ - gpio_set_value(EFIKA_USB_PHY_RESET, 0); - - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_disable(pwgt2); - regulator_disable(pwgt1); - } - gpio_direction_output(EFIKASB_POWEROFF, 1); -} - -static int __init mx51_efikasb_power_init(void) -{ - pwgt1 = regulator_get(NULL, "pwgt1"); - pwgt2 = regulator_get(NULL, "pwgt2"); - if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) { - regulator_enable(pwgt1); - regulator_enable(pwgt2); - } - gpio_request(EFIKASB_POWEROFF, "poweroff"); - pm_power_off = mx51_efikasb_power_off; - - regulator_has_full_constraints(); - - return 0; -} - -static void __init mx51_efikasb_init_late(void) -{ - imx51_init_late(); - mx51_efikasb_power_init(); -} - -/* 01 R1.3 board - 10 R2.0 board */ -static void __init mx51_efikasb_board_id(void) -{ - int id; - - gpio_request(EFIKASB_PCBID0, "pcb id0"); - gpio_direction_input(EFIKASB_PCBID0); - gpio_request(EFIKASB_PCBID1, "pcb id1"); - gpio_direction_input(EFIKASB_PCBID1); - - id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0; - id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1; - - switch (id) { - default: - break; - case 1: - system_rev = 0x13; - break; - case 2: - system_rev = 0x20; - break; - } -} - -static void __init efikasb_board_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads, - ARRAY_SIZE(mx51efikasb_pads)); - efika_board_common_init(); - - mx51_efikasb_board_id(); - mx51_efikasb_usb(); - imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); - imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); - - gpio_led_register_device(-1, &mx51_efikasb_leds_data); - imx_add_gpio_keys(&mx51_efikasb_keys_data); -} - -static void __init mx51_efikasb_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 24576000); -} - -static struct sys_timer mx51_efikasb_timer = { - .init = mx51_efikasb_timer_init, -}; - -MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_machine = efikasb_board_init, - .init_late = mx51_efikasb_init_late, - .timer = &mx51_efikasb_timer, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c deleted file mode 100644 index 6c28e65f424d..000000000000 --- a/arch/arm/mach-imx/mach-mx53_ard.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31) -#define ARD_SD1_CD IMX_GPIO_NR(1, 1) -#define ARD_SD1_WP IMX_GPIO_NR(1, 9) -#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3) -#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0) -#define ARD_HOME IMX_GPIO_NR(5, 10) -#define ARD_BACK IMX_GPIO_NR(5, 11) -#define ARD_PROG IMX_GPIO_NR(5, 12) -#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13) - -static iomux_v3_cfg_t mx53_ard_pads[] = { - /* UART1 */ - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - /* WEIM for CS1 */ - MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */ - MX53_PAD_EIM_D16__EMI_WEIM_D_16, - MX53_PAD_EIM_D17__EMI_WEIM_D_17, - MX53_PAD_EIM_D18__EMI_WEIM_D_18, - MX53_PAD_EIM_D19__EMI_WEIM_D_19, - MX53_PAD_EIM_D20__EMI_WEIM_D_20, - MX53_PAD_EIM_D21__EMI_WEIM_D_21, - MX53_PAD_EIM_D22__EMI_WEIM_D_22, - MX53_PAD_EIM_D23__EMI_WEIM_D_23, - MX53_PAD_EIM_D24__EMI_WEIM_D_24, - MX53_PAD_EIM_D25__EMI_WEIM_D_25, - MX53_PAD_EIM_D26__EMI_WEIM_D_26, - MX53_PAD_EIM_D27__EMI_WEIM_D_27, - MX53_PAD_EIM_D28__EMI_WEIM_D_28, - MX53_PAD_EIM_D29__EMI_WEIM_D_29, - MX53_PAD_EIM_D30__EMI_WEIM_D_30, - MX53_PAD_EIM_D31__EMI_WEIM_D_31, - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - MX53_PAD_EIM_OE__EMI_WEIM_OE, - MX53_PAD_EIM_RW__EMI_WEIM_RW, - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1, - /* SDHC1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - MX53_PAD_PATA_DATA8__ESDHC1_DAT4, - MX53_PAD_PATA_DATA9__ESDHC1_DAT5, - MX53_PAD_PATA_DATA10__ESDHC1_DAT6, - MX53_PAD_PATA_DATA11__ESDHC1_DAT7, - MX53_PAD_GPIO_1__GPIO1_1, - MX53_PAD_GPIO_9__GPIO1_9, - /* I2C2 */ - MX53_PAD_EIM_EB2__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* I2C3 */ - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_16__I2C3_SDA, - /* GPIO */ - MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */ - MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */ - MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */ - MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */ - MX53_PAD_GPIO_10__GPIO4_0, /* vol down */ -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button ard_buttons[] = { - GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0), - GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0), - GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0), - GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data ard_button_data __initconst = { - .buttons = ard_buttons, - .nbuttons = ARRAY_SIZE(ard_buttons), -}; - -static struct resource ard_smsc911x_resources[] = { - { - .start = MX53_CS1_64MB_BASE_ADDR, - .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -struct smsc911x_platform_config ard_smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT, -}; - -static struct platform_device ard_smsc_lan9220_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(ard_smsc911x_resources), - .resource = ard_smsc911x_resources, - .dev = { - .platform_data = &ard_smsc911x_config, - }, -}; - -static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = { - .cd_gpio = ARD_SD1_CD, - .wp_gpio = ARD_SD1_WP, -}; - -static struct imxi2c_platform_data mx53_ard_i2c2_data = { - .bitrate = 50000, -}; - -static struct imxi2c_platform_data mx53_ard_i2c3_data = { - .bitrate = 400000, -}; - -static void __init mx53_ard_io_init(void) -{ - gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); - gpio_direction_input(ARD_ETHERNET_INT_B); - - gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); - gpio_direction_output(ARD_I2CPORTEXP_B, 1); -} - -/* Config CS1 settings for ethernet controller */ -static int weim_cs_config(void) -{ - u32 reg; - void __iomem *weim_base, *iomuxc_base; - - weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K); - if (!weim_base) - return -ENOMEM; - - iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K); - if (!iomuxc_base) { - iounmap(weim_base); - return -ENOMEM; - } - - /* CS1 timings for LAN9220 */ - writel(0x20001, (weim_base + 0x18)); - writel(0x0, (weim_base + 0x1C)); - writel(0x16000202, (weim_base + 0x20)); - writel(0x00000002, (weim_base + 0x24)); - writel(0x16002082, (weim_base + 0x28)); - writel(0x00000000, (weim_base + 0x2C)); - writel(0x00000000, (weim_base + 0x90)); - - /* specify 64 MB on CS1 and CS0 on GPR1 */ - reg = readl(iomuxc_base + 0x4); - reg &= ~0x3F; - reg |= 0x1B; - writel(reg, (iomuxc_base + 0x4)); - - iounmap(iomuxc_base); - iounmap(weim_base); - - return 0; -} - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -void __init imx53_ard_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads, - ARRAY_SIZE(mx53_ard_pads)); - weim_cs_config(); -} - -static struct platform_device *devices[] __initdata = { - &ard_smsc_lan9220_device, -}; - -static void __init mx53_ard_board_init(void) -{ - imx53_soc_init(); - imx53_add_imx_uart(0, NULL); - - imx53_ard_common_init(); - mx53_ard_io_init(); - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B); - ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); - imx53_add_imx2_wdt(0); - imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); - imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); - imx_add_gpio_keys(&ard_button_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_ard_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_ard_timer = { - .init = mx53_ard_timer_init, -}; - -MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_ard_timer, - .init_machine = mx53_ard_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c deleted file mode 100644 index 09fe2197b491..000000000000 --- a/arch/arm/mach-imx/mach-mx53_evk.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <mach/common.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <mach/iomux-mx53.h> - -#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) -#define MX53EVK_LED IMX_GPIO_NR(7, 7) - -#include "devices-imx53.h" - -static iomux_v3_cfg_t mx53_evk_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_INTRQ__UART2_CTS, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, - - /* ecspi chip select lines */ - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, - /* LED */ - MX53_PAD_PATA_DA_1__GPIO7_7, -}; - -static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct gpio_led mx53evk_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = MX53EVK_LED, - }, -}; - -static const struct gpio_led_platform_data mx53evk_leds_data __initconst = { - .leds = mx53evk_leds, - .num_leds = ARRAY_SIZE(mx53evk_leds), -}; - -static inline void mx53_evk_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, &mx53_evk_uart_pdata); - imx53_add_imx_uart(2, NULL); -} - -static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_evk_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, - "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_evk_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static struct spi_board_info mx53_evk_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx53_evk_spi_cs[] = { - EVK_ECSPI1_CS0, - EVK_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx53_evk_spi_data __initconst = { - .chipselect = mx53_evk_spi_cs, - .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), -}; - -void __init imx53_evk_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, - ARRAY_SIZE(mx53_evk_pads)); -} - -static void __init mx53_evk_board_init(void) -{ - imx53_soc_init(); - imx53_evk_common_init(); - - mx53_evk_init_uart(); - mx53_evk_fec_reset(); - imx53_add_fec(&mx53_evk_fec_pdata); - - imx53_add_imx_i2c(0, &mx53_evk_i2c_data); - imx53_add_imx_i2c(1, &mx53_evk_i2c_data); - - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - - spi_register_board_info(mx53_evk_spi_board_info, - ARRAY_SIZE(mx53_evk_spi_board_info)); - imx53_add_ecspi(0, &mx53_evk_spi_data); - imx53_add_imx2_wdt(0); - gpio_led_register_device(-1, &mx53evk_leds_data); -} - -static void __init mx53_evk_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_evk_timer = { - .init = mx53_evk_timer_init, -}; - -MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_evk_timer, - .init_machine = mx53_evk_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c deleted file mode 100644 index 8abe23c1d3c8..000000000000 --- a/arch/arm/mach-imx/mach-mx53_loco.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/i2c.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) -#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) -#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) -#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define LOCO_LED IMX_GPIO_NR(7, 7) -#define LOCO_SD3_CD IMX_GPIO_NR(3, 11) -#define LOCO_SD3_WP IMX_GPIO_NR(3, 12) -#define LOCO_SD1_CD IMX_GPIO_NR(3, 13) -#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) - -static iomux_v3_cfg_t mx53_loco_pads[] = { - /* FEC */ - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - /* FEC_nRST */ - MX53_PAD_PATA_DA_0__GPIO7_6, - /* FEC_nINT */ - MX53_PAD_PATA_DATA4__GPIO2_4, - /* AUDMUX5 */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ - /* I2C2 */ - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - /* SD3_CD */ - MX53_PAD_EIM_DA11__GPIO3_11, - /* SD3_WP */ - MX53_PAD_EIM_DA12__GPIO3_12, - /* VGA */ - MX53_PAD_EIM_OE__IPU_DI1_PIN7, - MX53_PAD_EIM_RW__IPU_DI1_PIN8, - /* DISPLB */ - MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, - MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, - MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, - MX53_PAD_EIM_D23__IPU_DI0_D0_CS, - /* DISP0_POWER_EN */ - MX53_PAD_EIM_D24__GPIO3_24, - /* DISP0 DET INT */ - MX53_PAD_EIM_D31__GPIO3_31, - /* LVDS */ - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* UART1 */ - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - /* CSI0 */ - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, - /* DISPLAY */ - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - /* Audio CLK*/ - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, - /* PWM */ - MX53_PAD_GPIO_1__PWM2_PWMO, - /* SPDIF */ - MX53_PAD_GPIO_7__SPDIF_PLOCK, - MX53_PAD_GPIO_17__SPDIF_OUT1, - /* GPIO */ - MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */ - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_PATA_INTRQ__GPIO7_2, - MX53_PAD_EIM_WAIT__GPIO5_0, - MX53_PAD_NANDF_WP_B__GPIO6_9, - MX53_PAD_NANDF_RB0__GPIO6_10, - MX53_PAD_NANDF_CS1__GPIO6_14, - MX53_PAD_NANDF_CS2__GPIO6_15, - MX53_PAD_NANDF_CS3__GPIO6_16, - MX53_PAD_GPIO_5__GPIO1_5, - MX53_PAD_GPIO_16__GPIO7_11, - MX53_PAD_GPIO_8__GPIO1_8, -}; - -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ -{ \ - .gpio = gpio_num, \ - .type = EV_KEY, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ - .wakeup = wake, \ -} - -static struct gpio_keys_button loco_buttons[] = { - GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), - GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), -}; - -static const struct gpio_keys_platform_data loco_button_data __initconst = { - .buttons = loco_buttons, - .nbuttons = ARRAY_SIZE(loco_buttons), -}; - -static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = { - .cd_gpio = LOCO_SD1_CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = { - .cd_gpio = LOCO_SD3_CD, - .wp_gpio = LOCO_SD3_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -static inline void mx53_loco_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(LOCO_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(LOCO_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_loco_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct gpio_led mx53loco_leds[] __initconst = { - { - .name = "green", - .default_trigger = "heartbeat", - .gpio = LOCO_LED, - }, -}; - -static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { - .leds = mx53loco_leds, - .num_leds = ARRAY_SIZE(mx53loco_leds), -}; - -void __init imx53_qsb_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, - ARRAY_SIZE(mx53_loco_pads)); -} - -static struct i2c_board_info mx53loco_i2c_devices[] = { - { - I2C_BOARD_INFO("mma8450", 0x1C), - }, -}; - -static void __init mx53_loco_board_init(void) -{ - int ret; - imx53_soc_init(); - imx53_qsb_common_init(); - - imx53_add_imx_uart(0, NULL); - mx53_loco_fec_reset(); - imx53_add_fec(&mx53_loco_fec_data); - imx53_add_imx2_wdt(0); - - ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); - if (ret) - pr_err("Cannot request ACCEL_EN pin: %d\n", ret); - - i2c_register_board_info(0, mx53loco_i2c_devices, - ARRAY_SIZE(mx53loco_i2c_devices)); - imx53_add_imx_i2c(0, &mx53_loco_i2c_data); - imx53_add_imx_i2c(1, &mx53_loco_i2c_data); - imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); - imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); - imx_add_gpio_keys(&loco_button_data); - gpio_led_register_device(-1, &mx53loco_leds_data); - imx53_add_ahci_imx(); -} - -static void __init mx53_loco_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 0, 0); -} - -static struct sys_timer mx53_loco_timer = { - .init = mx53_loco_timer_init, -}; - -MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_loco_timer, - .init_machine = mx53_loco_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c deleted file mode 100644 index b15d6a6d3b68..000000000000 --- a/arch/arm/mach-imx/mach-mx53_smd.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx53.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx53.h" - -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) - -static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD2 */ - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, -}; - -static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static inline void mx53_smd_init_uart(void) -{ - imx53_add_imx_uart(0, NULL); - imx53_add_imx_uart(1, NULL); - imx53_add_imx_uart(2, &mx53_smd_uart_data); -} - -static inline void mx53_smd_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - gpio_direction_output(SMD_FEC_PHY_RST, 0); - msleep(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); -} - -static const struct fec_platform_data mx53_smd_fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { - .bitrate = 100000, -}; - -static inline void mx53_smd_ahci_pwr_on(void) -{ - int ret; - - /* Enable SATA PWR */ - ret = gpio_request_one(MX53_SMD_SATA_PWR_EN, - GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr"); - if (ret) { - pr_err("failed to enable SATA_PWR_EN: %d\n", ret); - return; - } -} - -void __init imx53_smd_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, - ARRAY_SIZE(mx53_smd_pads)); -} - -static void __init mx53_smd_board_init(void) -{ - imx53_soc_init(); - imx53_smd_common_init(); - - mx53_smd_init_uart(); - mx53_smd_fec_reset(); - imx53_add_fec(&mx53_smd_fec_data); - imx53_add_imx2_wdt(0); - imx53_add_imx_i2c(0, &mx53_smd_i2c_data); - imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); - imx53_add_sdhci_esdhc_imx(2, NULL); - mx53_smd_ahci_pwr_on(); - imx53_add_ahci_imx(); -} - -static void __init mx53_smd_timer_init(void) -{ - mx53_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx53_smd_timer = { - .init = mx53_smd_timer_init, -}; - -MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") - .map_io = mx53_map_io, - .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .timer = &mx53_smd_timer, - .init_machine = mx53_smd_board_init, - .init_late = imx53_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 52d8f534be10..acb0aadb4255 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { .script_addrs = &imx51_sdma_script, }; -static struct sdma_script_start_addrs imx53_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .app_2_mcu_addr = 683, - .mcu_2_app_addr = 747, - .uart_2_mcu_addr = 817, - .shp_2_mcu_addr = 891, - .mcu_2_shp_addr = 960, - .uartsh_2_mcu_addr = 1032, - .spdif_2_mcu_addr = 1100, - .mcu_2_spdif_addr = 1134, - .firi_2_mcu_addr = 1193, - .mcu_2_firi_addr = 1290, -}; - -static struct sdma_platform_data imx53_sdma_pdata __initdata = { - .fw_name = "sdma-imx53.bin", - .script_addrs = &imx53_sdma_script, -}; - static const struct resource imx50_audmux_res[] __initconst = { DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), }; @@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = { DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), }; -static const struct resource imx53_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), -}; - void __init imx50_soc_init(void) { /* i.mx50 has the i.mx35 type gpio */ @@ -196,30 +173,6 @@ void __init imx51_soc_init(void) ARRAY_SIZE(imx51_audmux_res)); } -void __init imx53_soc_init(void) -{ - /* i.mx53 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); - mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); - mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); - mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); - mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); - mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); - mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); - - pinctrl_provide_dummies(); - /* i.mx53 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR)); - imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR)); - - /* i.mx53 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res, - ARRAY_SIZE(imx53_audmux_res)); -} - void __init imx51_init_late(void) { mx51_neon_fixup(); diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c deleted file mode 100644 index ee870c49bc63..000000000000 --- a/arch/arm/mach-imx/mx51_efika.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * based on code from the following - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved. - * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/consumer.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <mach/ulpi.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "devices-imx51.h" -#include "efika.h" -#include "cpu_op-mx51.h" - -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 - -#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5) -#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27) - -#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) -#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) - -#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6) - -static iomux_v3_cfg_t mx51efika_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - /* SD/MMC WP/CD */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - MX51_PAD_GPIO1_7__SD2_WP, - MX51_PAD_GPIO1_8__SD2_CD, - - /* spi */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_GPIO1_6__GPIO1_6, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB RESET */ - MX51_PAD_GPIO1_5__GPIO1_5, - - /* WLAN */ - MX51_PAD_EIM_A22__GPIO2_16, - MX51_PAD_EIM_A16__GPIO2_10, - - /* USB PHY RESET */ - MX51_PAD_EIM_D27__GPIO2_9, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* This function is board specific as the bit mask for the plldiv will also - * be different for other Freescale SoCs, thus a common bitmask is not - * possible and cannot get place in /plat-mxc/ehci.c. - */ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; - u32 v; - void __iomem *usb_base; - void __iomem *socregs_base; - - mxc_iomux_v3_setup_pad(usbh1gpio); - gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); - gpio_direction_output(EFIKAMX_USBH1_STP, 0); - msleep(1); - gpio_set_value(EFIKAMX_USBH1_STP, 1); - msleep(1); - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); - - /* The clock for the USBH1 ULPI port will come externally */ - /* from the PHY. */ - v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, - socregs_base + MX51_USB_CTRL_1_OFFSET); - - iounmap(usb_base); - - gpio_free(EFIKAMX_USBH1_STP); - mxc_iomux_v3_setup_pad(usbh1stp); - - mdelay(10); - - return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); -} - -static struct mxc_usbh_platform_data usbh1_config __initdata = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void mx51_efika_hubreset(void) -{ - gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst"); - gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); - msleep(1); - gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); -} - -static void __init mx51_efika_usb(void) -{ - mx51_efika_hubreset(); - - /* pulling it low, means no USB at all... */ - gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset"); - gpio_direction_output(EFIKA_USB_PHY_RESET, 0); - msleep(1); - gpio_set_value(EFIKA_USB_PHY_RESET, 1); - - usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); - - imx51_add_mxc_ehci_otg(&dr_utmi_config); - if (usbh1_config.otg) - imx51_add_mxc_ehci_hs(1, &usbh1_config); -} - -static struct mtd_partition mx51_efika_spi_nor_partitions[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_256K, - }, - { - .name = "config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - }, -}; - -static struct flash_platform_data mx51_efika_spi_flash_data = { - .name = "spi_flash", - .parts = mx51_efika_spi_nor_partitions, - .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions), - .type = "sst25vf032b", -}; - -static struct regulator_consumer_supply sw1_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_consumer_supply vdig_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDA", "1-000a"), - REGULATOR_SUPPLY("VDDD", "1-000a"), -}; - -static struct regulator_consumer_supply vvideo_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDIO", "1-000a"), -}; - -static struct regulator_consumer_supply vsd_consumers[] = { - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"), - REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"), -}; - -static struct regulator_consumer_supply pwgt1_consumer[] = { - { - .supply = "pwgt1", - } -}; - -static struct regulator_consumer_supply pwgt2_consumer[] = { - { - .supply = "pwgt2", - } -}; - -static struct regulator_consumer_supply coincell_consumer[] = { - { - .supply = "coincell", - } -}; - -static struct regulator_init_data sw1_init = { - .constraints = { - .name = "SW1", - .min_uV = 600000, - .max_uV = 1375000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .valid_modes_mask = 0, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 850000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), - .consumer_supplies = sw1_consumers, -}; - -static struct regulator_init_data sw2_init = { - .constraints = { - .name = "SW2", - .min_uV = 900000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - .state_mem = { - .uV = 950000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - } -}; - -static struct regulator_init_data sw3_init = { - .constraints = { - .name = "SW3", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw4_init = { - .constraints = { - .name = "SW4", - .min_uV = 1100000, - .max_uV = 1850000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data viohi_init = { - .constraints = { - .name = "VIOHI", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb_init = { - .constraints = { - .name = "VUSB", - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data swbst_init = { - .constraints = { - .name = "SWBST", - } -}; - -static struct regulator_init_data vdig_init = { - .constraints = { - .name = "VDIG", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), - .consumer_supplies = vdig_consumers, -}; - -static struct regulator_init_data vpll_init = { - .constraints = { - .name = "VPLL", - .min_uV = 1050000, - .max_uV = 1800000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vusb2_init = { - .constraints = { - .name = "VUSB2", - .min_uV = 2400000, - .max_uV = 2775000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vvideo_init = { - .constraints = { - .name = "VVIDEO", - .min_uV = 2775000, - .max_uV = 2775000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), - .consumer_supplies = vvideo_consumers, -}; - -static struct regulator_init_data vaudio_init = { - .constraints = { - .name = "VAUDIO", - .min_uV = 2300000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - } -}; - -static struct regulator_init_data vsd_init = { - .constraints = { - .name = "VSD", - .min_uV = 1800000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), - .consumer_supplies = vsd_consumers, -}; - -static struct regulator_init_data vcam_init = { - .constraints = { - .name = "VCAM", - .min_uV = 2500000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, - .boot_on = 1, - } -}; - -static struct regulator_init_data vgen1_init = { - .constraints = { - .name = "VGEN1", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen2_init = { - .constraints = { - .name = "VGEN2", - .min_uV = 1200000, - .max_uV = 3150000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data vgen3_init = { - .constraints = { - .name = "VGEN3", - .min_uV = 1800000, - .max_uV = 2900000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_init_data gpo1_init = { - .constraints = { - .name = "GPO1", - } -}; - -static struct regulator_init_data gpo2_init = { - .constraints = { - .name = "GPO2", - } -}; - -static struct regulator_init_data gpo3_init = { - .constraints = { - .name = "GPO3", - } -}; - -static struct regulator_init_data gpo4_init = { - .constraints = { - .name = "GPO4", - } -}; - -static struct regulator_init_data pwgt1_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer), - .consumer_supplies = pwgt1_consumer, -}; - -static struct regulator_init_data pwgt2_init = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer), - .consumer_supplies = pwgt2_consumer, -}; - -static struct regulator_init_data vcoincell_init = { - .constraints = { - .name = "COINCELL", - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(coincell_consumer), - .consumer_supplies = coincell_consumer, -}; - -static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { - { .id = MC13892_SW1, .init_data = &sw1_init }, - { .id = MC13892_SW2, .init_data = &sw2_init }, - { .id = MC13892_SW3, .init_data = &sw3_init }, - { .id = MC13892_SW4, .init_data = &sw4_init }, - { .id = MC13892_SWBST, .init_data = &swbst_init }, - { .id = MC13892_VIOHI, .init_data = &viohi_init }, - { .id = MC13892_VPLL, .init_data = &vpll_init }, - { .id = MC13892_VDIG, .init_data = &vdig_init }, - { .id = MC13892_VSD, .init_data = &vsd_init }, - { .id = MC13892_VUSB2, .init_data = &vusb2_init }, - { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, - { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, - { .id = MC13892_VCAM, .init_data = &vcam_init }, - { .id = MC13892_VGEN1, .init_data = &vgen1_init }, - { .id = MC13892_VGEN2, .init_data = &vgen2_init }, - { .id = MC13892_VGEN3, .init_data = &vgen3_init }, - { .id = MC13892_VUSB, .init_data = &vusb_init }, - { .id = MC13892_GPO1, .init_data = &gpo1_init }, - { .id = MC13892_GPO2, .init_data = &gpo2_init }, - { .id = MC13892_GPO3, .init_data = &gpo3_init }, - { .id = MC13892_GPO4, .init_data = &gpo4_init }, - { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init }, - { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init }, - { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init }, -}; - -static struct mc13xxx_platform_data mx51_efika_mc13892_data = { - .flags = MC13XXX_USE_RTC, - .regulators = { - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, - }, -}; - -static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &mx51_efika_spi_flash_data, - .irq = -1, - }, - { - .modalias = "mc13892", - .max_speed_hz = 1000000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &mx51_efika_mc13892_data, - /* irq number is run-time assigned */ - }, -}; - -static int mx51_efika_spi_cs[] = { - EFIKAMX_SPI_CS0, - EFIKAMX_SPI_CS1, -}; - -static const struct spi_imx_master mx51_efika_spi_pdata __initconst = { - .chipselect = mx51_efika_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs), -}; - -void __init efika_board_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51efika_pads, - ARRAY_SIZE(mx51efika_pads)); - imx51_add_imx_uart(0, &uart_pdata); - mx51_efika_usb(); - - /* FIXME: comes from original code. check this. */ - if (mx51_revision() < IMX_CHIP_REVISION_2_0) - sw2_init.constraints.state_mem.uV = 1100000; - else if (mx51_revision() == IMX_CHIP_REVISION_2_0) { - sw2_init.constraints.state_mem.uV = 1250000; - sw1_init.constraints.state_mem.uV = 1000000; - } - if (machine_is_mx51_efikasb()) - vgen1_init.constraints.max_uV = 1200000; - - gpio_request(EFIKAMX_PMIC, "pmic irq"); - gpio_direction_input(EFIKAMX_PMIC); - mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC); - spi_register_board_info(mx51_efika_spi_board_info, - ARRAY_SIZE(mx51_efika_spi_board_info)); - imx51_add_ecspi(0, &mx51_efika_spi_pdata); - - imx51_add_pata_imx(); - -#if defined(CONFIG_CPU_FREQ_IMX) - get_cpu_op = mx51_get_cpu_op; -#endif -} diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 2af5034ea29e..dad3cb74ed31 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -94,8 +94,8 @@ arch_initcall(integrator_init); * UART0 7 6 * UART1 5 4 */ -#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC) -#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS) +#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC) +#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS) static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) { diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c index fbb457779895..590c192cdf4d 100644 --- a/arch/arm/mach-integrator/cpu.c +++ b/arch/arm/mach-integrator/cpu.c @@ -25,10 +25,10 @@ static struct cpufreq_driver integrator_driver; -#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID) -#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC) -#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT) -#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK) +#define CM_ID __io_address(INTEGRATOR_HDR_ID) +#define CM_OSC __io_address(INTEGRATOR_HDR_OSC) +#define CM_STAT __io_address(INTEGRATOR_HDR_STAT) +#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK) static const struct icst_params lclk_params = { .ref = 24000000, diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h deleted file mode 100644 index 8de70de3dd0a..000000000000 --- a/arch/arm/mach-integrator/include/mach/io.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-integrator/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* - * WARNING: this has to mirror definitions in platform.h - */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) - -#endif diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index ec467baade09..4c0347526851 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -324,6 +324,10 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 + /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 3b2267529f5e..2215d96cd735 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -50,6 +50,7 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include <asm/mach/time.h> #include <plat/fpga-irq.h> @@ -73,7 +74,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -133,25 +134,20 @@ static struct map_desc ap_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = PCI_MEMORY_VADDR, + .virtual = (unsigned long)PCI_MEMORY_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = PCI_CONFIG_VADDR, + .virtual = (unsigned long)PCI_CONFIG_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = PCI_V3_VADDR, + .virtual = (unsigned long)PCI_V3_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE - }, { - .virtual = PCI_IO_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; @@ -159,6 +155,7 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff @@ -317,9 +314,9 @@ static void __init ap_init(void) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) -#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) -#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) +#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) static unsigned long timer_reload; diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 82d5c837cc74..3df5fc369361 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -59,7 +59,7 @@ #define INTCP_ETH_SIZE 0x10 -#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE) +#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE) #define INTCP_FLASHPROG 0x04 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) @@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = { */ static unsigned int mmc_status(struct device *dev) { - unsigned int status = readl(IO_ADDRESS(0xca000000 + 4)); - writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8)); + unsigned int status = readl(__io_address(0xca000000 + 4)); + writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8)); return status & 8; } diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index b866880e82ac..bbeca59df66b 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); @@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock); #undef V3_LB_BASE_PREFETCH #define V3_LB_BASE_PREFETCH 0 -static unsigned long v3_open_config_window(struct pci_bus *bus, +static void __iomem *v3_open_config_window(struct pci_bus *bus, unsigned int devfn, int offset) { unsigned int address, mapaddress, busnr; @@ -280,7 +280,7 @@ static void v3_close_config_window(void) static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - unsigned long addr; + void __iomem *addr; unsigned long flags; u32 v; @@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - unsigned long addr; + void __iomem *addr; unsigned long flags; raw_spin_lock_irqsave(&v3_lock, flags); @@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -391,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) * means I can't get additional information on the reason for the pm2fb * problems. I suppose I'll just have to mind-meld with the machine. ;) */ -#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE) -#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20) -#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24) +#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE) +#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20) +#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24) static int v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -498,7 +495,6 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; - pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h deleted file mode 100644 index f13188518025..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/io.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * iop13xx custom ioremap implementation - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __iop13xx_io(a) - -extern void __iomem * __iop13xx_io(unsigned long io_addr); - -#endif diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h index e190dcd7d72d..7480f58267aa 100644 --- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void); * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP - * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window - * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window + * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window + * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window */ -#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL -#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIX_LOWER_IO_PA\ - - IOP13XX_PCIX_LOWER_IO_VA)) #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL @@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void); IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ -#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIE_LOWER_IO_PA\ - - IOP13XX_PCIE_LOWER_IO_VA)) +#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL @@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void); * IOP13XX chipset registers */ #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ +#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) -#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) +#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ + + IOP13XX_PMMR_PHYS_MEM_BASE) +#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ + + IOP13XX_PMMR_VIRT_MEM_BASE) #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) @@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void); #define IOP13XX_PMMR_SIZE 0x00080000 /*=================== Defines for Platform Devices =====================*/ -#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) -#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) +#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) +#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) +#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 1afa99ef97fa..7c032d0ab24a 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -16,12 +16,12 @@ #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) -static inline dma_addr_t __virt_to_lbus(unsigned long x) +static inline dma_addr_t __virt_to_lbus(void __iomem *x) { return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; } -static inline unsigned long __lbus_to_virt(dma_addr_t x) +static inline void __iomem *__lbus_to_virt(dma_addr_t x) { return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; } @@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) #define __arch_dma_to_virt(dev, addr) \ ({ \ - unsigned long __virt; \ + void * __virt; \ dma_addr_t __dma = addr; \ if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ __virt = __lbus_to_virt(__dma); \ else \ - __virt = __phys_to_virt(__dma); \ - (void *)__virt; \ + __virt = (void *)__phys_to_virt(__dma); \ + __virt; \ }) #define __arch_virt_to_dma(dev, addr) \ ({ \ - unsigned long __virt = (unsigned long)addr; \ + void * __virt = addr; \ dma_addr_t __dma; \ if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ __dma = __virt_to_lbus(__virt); \ else \ - __dma = __virt_to_phys(__virt); \ + __dma = __virt_to_phys((unsigned long)__virt); \ __dma; \ }) diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c index 3c364198db9c..183dc8b5511b 100644 --- a/arch/arm/mach-iop13xx/io.c +++ b/arch/arm/mach-iop13xx/io.c @@ -23,25 +23,6 @@ #include "pci.h" -void * __iomem __iop13xx_io(unsigned long io_addr) -{ - void __iomem * io_virt; - - switch (io_addr) { - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); - break; - default: - BUG(); - } - - return io_virt; -} -EXPORT_SYMBOL(__iop13xx_io); - static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, size_t size, unsigned int mtype, void *caller) { @@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, if (unlikely(!iop13xx_atux_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atux_mem_base + + retval = (iop13xx_atux_mem_base + (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); break; case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: if (unlikely(!iop13xx_atue_mem_base)) retval = NULL; else - retval = (void *)(iop13xx_atue_mem_base + + retval = (iop13xx_atue_mem_base + (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); break; case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: @@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, (cookie - IOP13XX_PBI_LOWER_MEM_RA), size, mtype, __builtin_return_address(0)); break; - case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); - break; - case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: - retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); - break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: - retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); + retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; default: retval = __arm_ioremap_caller(cookie, size, mtype, @@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) goto skip; switch ((u32) addr) { - case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: - case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: - case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: + case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } __iounmap(addr); diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 861cb12ef436..9082b84aeebb 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ static struct pci_bus *pci_bus_atux = 0; static struct pci_bus *pci_bus_atue = 0; -u32 iop13xx_atue_mem_base; -u32 iop13xx_atux_mem_base; +void __iomem *iop13xx_atue_mem_base; +void __iomem *iop13xx_atux_mem_base; size_t iop13xx_atue_mem_size; size_t iop13xx_atux_mem_size; @@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atux_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atux_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) , 0, iop13xx_atux_mem_size, MT_DEVICE); if (!iop13xx_atux_mem_base) { @@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atux_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atux_mem_size, iop13xx_atux_mem_base); break; @@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atue_mem_base = - (u32) __arm_ioremap_pfn( + iop13xx_atue_mem_base = __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) , 0, iop13xx_atue_mem_size, MT_DEVICE); if (!iop13xx_atue_mem_base) { @@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atue_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", __func__, atu, iop13xx_atue_mem_size, iop13xx_atue_mem_base); break; } - printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", + printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", atu ? "ATUE" : "ATUX", (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / SZ_1M, @@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ - pcibios_min_io = 0; pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU @@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIX_UPPER_IO_PA; - res[0].name = "IQ81340 ATUX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); - res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIX_LOWER_MEM_RA; + res->end = IOP13XX_PCIX_UPPER_MEM_RA; + res->name = "IQ81340 ATUX PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; - res[0].end = IOP13XX_PCIE_UPPER_IO_PA; - res[0].name = "IQ81340 ATUE PCI I/O Space"; - res[0].flags = IORESOURCE_IO; + pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); - res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; - res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; - res[1].name = "IQ81340 ATUE PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; + res->start = IOP13XX_PCIE_LOWER_MEM_RA; + res->end = IOP13XX_PCIE_UPPER_MEM_RA; + res->name = "IQ81340 ATUE PCI Memory Space"; + res->flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; - sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: @@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) return 0; } - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); + request_resource(&iomem_resource, res); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h index c70cf5b41e31..d45a80b3080e 100644 --- a/arch/arm/mach-iop13xx/pci.h +++ b/arch/arm/mach-iop13xx/pci.h @@ -1,6 +1,6 @@ #include <linux/types.h> -extern u32 iop13xx_atue_mem_base; -extern u32 iop13xx_atux_mem_base; +extern void __iomem *iop13xx_atue_mem_base; +extern void __iomem *iop13xx_atux_mem_base; extern size_t iop13xx_atue_mem_size; extern size_t iop13xx_atux_mem_size; diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index daabb1fa6c2c..3181f61ea63e 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c @@ -36,20 +36,10 @@ */ static struct map_desc iop13xx_std_desc[] __initdata = { { /* mem mapped registers */ - .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, + .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, - }, { /* PCIE IO space */ - .virtual = IOP13XX_PCIE_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, - }, { /* PCIX IO space */ - .virtual = IOP13XX_PCIX_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), - .length = IOP13XX_PCIX_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; @@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = { static struct plat_serial8250_port iop13xx_uart0_data[] = { { - .membase = (char*)(IOP13XX_UART0_VIRT), - .mapbase = (IOP13XX_UART0_PHYS), + .membase = IOP13XX_UART0_VIRT, + .mapbase = IOP13XX_UART0_PHYS, .irq = IRQ_IOP13XX_UART0, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, @@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { static struct plat_serial8250_port iop13xx_uart1_data[] = { { - .membase = (char*)(IOP13XX_UART1_VIRT), - .mapbase = (IOP13XX_UART1_PHYS), + .membase = IOP13XX_UART1_VIRT, + .mapbase = IOP13XX_UART1_PHYS, .irq = IRQ_IOP13XX_UART1, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index c15a100ba779..02e20c3912ba 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = { static void glantank_power_off(void) { - __raw_writeb(0x01, 0xfe8d0004); + __raw_writeb(0x01, IOMEM(0xfe8d0004)); while (1) ; diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h deleted file mode 100644 index e2ada265bb8d..000000000000 --- a/arch/arm/mach-iop32x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include <asm/hardware/iop3xx.h> - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h deleted file mode 100644 index f7c1b6595660..000000000000 --- a/arch/arm/mach-iop33x/include/mach/io.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/io.h - * - * Copyright (C) 2001 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __IO_H -#define __IO_H - -#include <asm/hardware/iop3xx.h> - -#define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) - -#endif diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index a9f80943d01f..fdf91a160884 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx; *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ - .virtual = IXP4XX_EXP_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ - .virtual = IXP4XX_PCI_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE }, #ifdef CONFIG_DEBUG_LL { /* Debug UART mapping */ - .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), .length = IXP4XX_DEBUG_UART_REGION_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index b2ef65db0e91..ebc0ba31ce85 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -14,6 +14,7 @@ #ifndef __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__ +#include <linux/io.h> #include <asm/cputype.h> /* Processor id value in CP15 Register 0 */ @@ -37,7 +38,7 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~*IXP4XX_EXP_CFG2; + u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); if (cpu_is_ixp42x_rev_a0()) return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | @@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { - *IXP4XX_EXP_CFG2 = ~value; + __raw_writel(~value, IXP4XX_EXP_CFG2); } #endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index 97c530f66e78..eb68b61ce975 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -49,21 +49,21 @@ * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000) +#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000) #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000) +#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000) #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) /* * Peripheral space */ #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000) +#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000) #define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000) /* @@ -73,7 +73,7 @@ * aligned so that it * can be used with the low-level debug code. */ #define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) -#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) +#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000) #define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) #define IXP4XX_EXP_CS0_OFFSET 0x00 @@ -92,7 +92,7 @@ /* * Expansion Bus Controller registers. */ -#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) +#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 3226077735b1..3f7b05f30b46 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -42,16 +42,6 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { - .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, - .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), - .length = KIRKWOOD_PCIE1_IO_SIZE, - .type = MT_DEVICE, - }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, @@ -517,6 +507,13 @@ void __init kirkwood_wdt_init(void) void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); + + /* + * Some Kirkwood devices allocate their coherent buffers from atomic + * context. Increase size of atomic coherent pool to make sure such + * the allocations won't fail. + */ + init_dma_coherent_pool_size(SZ_1M); } int kirkwood_tclk; diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index d93359379598..be90b7d0e10b 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/sizes.h> #include <linux/platform_device.h> #include <linux/mtd/partitions.h> #include <linux/ata_platform.h> diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h deleted file mode 100644 index 5d0ab61700d2..000000000000 --- a/arch/arm/mach-kirkwood/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "kirkwood.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE) - + KIRKWOOD_PCIE_IO_VIRT_BASE); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776b..af4f0000dcef 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,14 +37,12 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE_IO_SIZE SZ_64K #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 6e8b2efa3c35..532d8acb38f9 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -56,7 +56,7 @@ struct pcie_port { void __iomem *base; spinlock_t conf_lock; int irq; - struct resource res[2]; + struct resource res; }; static int pcie_port_map[2]; @@ -137,20 +137,12 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) pp->irq = IRQ_KIRKWOOD_PCIE; /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 0 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 0 MEM"; - pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 0 MEM"; + pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static void __init pcie1_ioresources_init(struct pcie_port *pp) @@ -159,20 +151,12 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) pp->irq = IRQ_KIRKWOOD_PCIE1; /* - * IORESOURCE_IO - */ - pp->res[0].name = "PCIe 1 I/O Space"; - pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; - pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - - /* * IORESOURCE_MEM */ - pp->res[1].name = "PCIe 1 MEM"; - pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res[1].flags = IORESOURCE_MEM; + pp->res.name = "PCIe 1 MEM"; + pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res.flags = IORESOURCE_MEM; } static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) @@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) case 0: kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE); break; case 1: kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); + pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE); break; default: panic("PCIe setup: invalid controller %d", index); } - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe%d IO resource failed\n", index); - if (request_resource(&iomem_resource, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("Request PCIe%d Memory resource failed\n", index); - sys->io_offset = 0; - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); /* * Generic PCIe unit setup. diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c index 7f3f24053a00..ddb24222918e 100644 --- a/arch/arm/mach-ks8695/cpu.c +++ b/arch/arm/mach-ks8695/cpu.c @@ -36,7 +36,7 @@ static struct __initdata map_desc ks8695_io_desc[] = { { - .virtual = KS8695_IO_VA, + .virtual = (unsigned long)KS8695_IO_VA, .pfn = __phys_to_pfn(KS8695_IO_PA), .length = KS8695_IO_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h index 5e0c388143da..5090338c0db2 100644 --- a/arch/arm/mach-ks8695/include/mach/hardware.h +++ b/arch/arm/mach-ks8695/include/mach/hardware.h @@ -33,7 +33,7 @@ * head debug code as the initial MMU setup only deals in L1 sections. */ #define KS8695_IO_PA 0x03F00000 -#define KS8695_IO_VA 0xF0000000 +#define KS8695_IO_VA IOMEM(0xF0000000) #define KS8695_IO_SIZE SZ_1M #define KS8695_PCIMEM_PA 0x60000000 diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h deleted file mode 100644 index e620cda99d2d..000000000000 --- a/arch/arm/mach-ks8695/include/mach/regs-timer.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/regs-timer.h - * - * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> - * Copyright (C) 2006 Simtec Electronics - * - * KS8695 - Timer registers and bit definitions. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef KS8695_TIMER_H -#define KS8695_TIMER_H - -#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) -#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) -#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) - - -/* - * Timer registers - */ -#define KS8695_TMCON (0x00) /* Timer Control Register */ -#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ -#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ -#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ -#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ - - -/* Timer Control Register */ -#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ -#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ - -/* Timer0 Timeout Counter Register */ -#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ - - -#endif diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h index 9495cb4d701a..8879d610308a 100644 --- a/arch/arm/mach-ks8695/include/mach/uncompress.h +++ b/arch/arm/mach-ks8695/include/mach/uncompress.h @@ -19,15 +19,15 @@ static void putc(char c) { - while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) + while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) barrier(); - __raw_writel(c, KS8695_UART_PA + KS8695_URTH); + __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH); } static inline void flush(void) { - while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) + while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) barrier(); } diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c index ec783a3070ae..46c84bc7792c 100644 --- a/arch/arm/mach-ks8695/time.c +++ b/arch/arm/mach-ks8695/time.c @@ -25,53 +25,98 @@ #include <linux/kernel.h> #include <linux/sched.h> #include <linux/io.h> +#include <linux/clockchips.h> #include <asm/mach/time.h> #include <asm/system_misc.h> -#include <mach/regs-timer.h> #include <mach/regs-irq.h> #include "generic.h" +#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) +#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) +#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) + /* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() + * Timer registers */ -static unsigned long ks8695_gettimeoffset (void) +#define KS8695_TMCON (0x00) /* Timer Control Register */ +#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ +#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ +#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ +#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ + +/* Timer Control Register */ +#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ +#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ + +/* Timer0 Timeout Counter Register */ +#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ + +static void ks8695_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) { - unsigned long elapsed, tick2, intpending; + u32 tmcon; - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for an - * interrupt. We solve this by ensuring that the counter has not - * reloaded between our two reads. - */ - elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); - do { - tick2 = elapsed; - intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1); - elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); - } while (elapsed > tick2); - - /* Convert to number of ticks expired (not remaining) */ - elapsed = (CLOCK_TICK_RATE / HZ) - elapsed; - - /* Is interrupt pending? If so, then timer has been reloaded already. */ - if (intpending) - elapsed += (CLOCK_TICK_RATE / HZ); - - /* Convert ticks to usecs */ - return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; + if (mode == CLOCK_EVT_FEAT_PERIODIC) { + u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); + u32 half = DIV_ROUND_CLOSEST(rate, 2); + + /* Disable timer 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + /* Both registers need to count down */ + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); + + /* Re-enable timer1 */ + tmcon |= TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + } } +static int ks8695_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + +{ + u32 half = DIV_ROUND_CLOSEST(cycles, 2); + u32 tmcon; + + /* Disable timer 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + /* Both registers need to count down */ + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); + writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); + + /* Re-enable timer1 */ + tmcon |= TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + + return 0; +} + +static struct clock_event_device clockevent_ks8695 = { + .name = "ks8695_t1tc", + .rating = 300, /* Reasonably fast and accurate clock event */ + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = ks8695_set_next_event, + .set_mode = ks8695_set_mode, +}; + /* * IRQ handler for the timer. */ static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *evt = &clockevent_ks8695; + + evt->event_handler(evt); return IRQ_HANDLED; } @@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = { static void ks8695_timer_setup(void) { - unsigned long tmout = CLOCK_TICK_RATE / HZ; unsigned long tmcon; - /* disable timer1 */ - tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); - __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); - - __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC); - __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD); + /* Disable timer 0 and 1 */ + tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + tmcon &= ~TMCON_T0EN; + tmcon &= ~TMCON_T1EN; + writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - /* re-enable timer1 */ - __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); + /* + * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles + * (one on each counter) maximum 2*2^32, but the API will only + * accept up to a 32bit full word (0xFFFFFFFFU). + */ + clockevents_config_and_register(&clockevent_ks8695, + KS8695_CLOCK_RATE, 2, + 0xFFFFFFFFU); } static void __init ks8695_timer_init (void) @@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void) struct sys_timer ks8695_timer = { .init = ks8695_timer_init, - .offset = ks8695_gettimeoffset, - .resume = ks8695_timer_setup, }; void ks8695_restart(char mode, const char *cmd) @@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd) soft_restart(0); /* disable timer0 */ - reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); - __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); + writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); /* enable watchdog mode */ - __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); + writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); /* re-enable timer0 */ - __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); } diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index a48dc2dec485..0d4db8c544b5 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void) static struct map_desc lpc32xx_io_desc[] __initdata = { { - .virtual = IO_ADDRESS(LPC32XX_AHB0_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), .pfn = __phys_to_pfn(LPC32XX_AHB0_START), .length = LPC32XX_AHB0_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_AHB1_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START), .pfn = __phys_to_pfn(LPC32XX_AHB1_START), .length = LPC32XX_AHB1_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_FABAPB_START), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START), .pfn = __phys_to_pfn(LPC32XX_FABAPB_START), .length = LPC32XX_FABAPB_SIZE, .type = MT_DEVICE }, { - .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE), + .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE), .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE), .length = (LPC32XX_IRAM_BANK_SIZE * 2), .type = MT_DEVICE diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h index 1816e22a3479..a544e962a818 100644 --- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h +++ b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h @@ -30,7 +30,7 @@ #define LPC32XX_GPIO_P1_MAX 24 #define LPC32XX_GPIO_P2_MAX 13 #define LPC32XX_GPIO_P3_MAX 6 -#define LPC32XX_GPI_P3_MAX 28 +#define LPC32XX_GPI_P3_MAX 29 #define LPC32XX_GPO_P3_MAX 24 #define LPC32XX_GPIO_P0_GRP 0 diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h index 33e1dde37bd9..69065de97a3d 100644 --- a/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h @@ -25,7 +25,7 @@ /* * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ -#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ +#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ IO_BASE) #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 5b1cc35e6fba..3c6332753358 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -283,21 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: /* Rising edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 1); + __irq_set_handler_locked(d->hwirq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: /* Falling edge sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 1); + __irq_set_handler_locked(d->hwirq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: /* Low level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 0, 0); + __irq_set_handler_locked(d->hwirq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: /* High level sensitive */ __lpc32xx_set_irq_type(d->hwirq, 1, 0); + __irq_set_handler_locked(d->hwirq, handle_level_irq); break; /* Other modes are not supported */ @@ -305,9 +309,6 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) return -EINVAL; } - /* Ok to use the level handler for all types */ - irq_set_handler(d->hwirq, handle_level_irq); - return 0; } diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index b07dcc90829d..e8ff4c3f0566 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -24,12 +24,9 @@ #include <linux/irq.h> #include <linux/dma-mapping.h> #include <linux/device.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> #include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> -#include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> #include <linux/amba/mmci.h> #include <linux/of.h> @@ -37,6 +34,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/clk.h> +#include <linux/mtd/lpc32xx_slc.h> +#include <linux/mtd/lpc32xx_mlc.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -156,21 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = { .remove = lpc32xx_clcd_remove, }; -/* - * AMBA SSP (SPI) - */ -static struct pl022_ssp_controller lpc32xx_ssp0_data = { - .bus_id = 0, - .num_chipselect = 1, - .enable_dma = 0, -}; - -static struct pl022_ssp_controller lpc32xx_ssp1_data = { - .bus_id = 1, - .num_chipselect = 1, - .enable_dma = 0, -}; - static struct pl08x_channel_data pl08x_slave_channels[] = { { .bus_id = "nand-slc", @@ -223,13 +207,25 @@ static struct mmci_platform_data lpc32xx_mmci_data = { * gather, and the MMCI driver doesn't do it this way */ }; +static struct lpc32xx_slc_platform_data lpc32xx_slc_data = { + .dma_filter = pl08x_filter_id, +}; + +static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { + .dma_filter = pl08x_filter_id, +}; + static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data), - OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), + OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL), + OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", &lpc32xx_mmci_data), + OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", + &lpc32xx_slc_data), + OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", + &lpc32xx_mlc_data), { } }; @@ -253,12 +249,6 @@ static void __init lpc3250_machine_init(void) of_platform_populate(NULL, of_default_bus_match_table, lpc32xx_auxdata_lookup, NULL); - - /* Register GPIOs used on this board */ - if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) - pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); - else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) - pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); } static char const *lpc32xx_dt_compat[] __initdata = { diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 7fddd01b85b9..d697d07a1bf0 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -108,18 +108,21 @@ endmenu config CPU_PXA168 bool select CPU_MOHAWK + select COMMON_CLK help Select code specific to PXA168 config CPU_PXA910 bool select CPU_MOHAWK + select COMMON_CLK help Select code specific to PXA910 config CPU_MMP2 bool select CPU_PJ4 + select COMMON_CLK help Select code specific to MMP2. MMP2 is ARMv7 compatible. diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index b786f7e6cd1f..095c155d6fb8 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,13 +2,19 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o time.o irq.o +obj-y += common.o devices.o time.o irq.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o +ifeq ($(CONFIG_COMMON_CLK), ) +obj-y += clock.o +obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o +obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o +obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o +endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c new file mode 100644 index 000000000000..21d22002cd19 --- /dev/null +++ b/arch/arm/mach-mmp/clock-mmp2.c @@ -0,0 +1,111 @@ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <mach/addr-map.h> + +#include "common.h" +#include "clock.h" + +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_RTC APBC_REG(0x000) +#define APBC_TWSI1 APBC_REG(0x004) +#define APBC_TWSI2 APBC_REG(0x008) +#define APBC_TWSI3 APBC_REG(0x00c) +#define APBC_TWSI4 APBC_REG(0x010) +#define APBC_KPC APBC_REG(0x018) +#define APBC_UART1 APBC_REG(0x02c) +#define APBC_UART2 APBC_REG(0x030) +#define APBC_UART3 APBC_REG(0x034) +#define APBC_GPIO APBC_REG(0x038) +#define APBC_PWM0 APBC_REG(0x03c) +#define APBC_PWM1 APBC_REG(0x040) +#define APBC_PWM2 APBC_REG(0x044) +#define APBC_PWM3 APBC_REG(0x048) +#define APBC_SSP0 APBC_REG(0x04c) +#define APBC_SSP1 APBC_REG(0x050) +#define APBC_SSP2 APBC_REG(0x054) +#define APBC_SSP3 APBC_REG(0x058) +#define APBC_SSP4 APBC_REG(0x05c) +#define APBC_SSP5 APBC_REG(0x060) +#define APBC_TWSI5 APBC_REG(0x07c) +#define APBC_TWSI6 APBC_REG(0x080) +#define APBC_UART4 APBC_REG(0x088) + +#define APMU_USB APMU_REG(0x05c) +#define APMU_NAND APMU_REG(0x060) +#define APMU_SDH0 APMU_REG(0x054) +#define APMU_SDH1 APMU_REG(0x058) +#define APMU_SDH2 APMU_REG(0x0e8) +#define APMU_SDH3 APMU_REG(0x0ec) + +static void sdhc_clk_enable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst |= clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +static void sdhc_clk_disable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst &= ~clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +struct clkops sdhc_clk_ops = { + .enable = sdhc_clk_enable, + .disable = sdhc_clk_disable, +}; + +/* APB peripheral clocks */ +static APBC_CLK(uart1, UART1, 1, 26000000); +static APBC_CLK(uart2, UART2, 1, 26000000); +static APBC_CLK(uart3, UART3, 1, 26000000); +static APBC_CLK(uart4, UART4, 1, 26000000); +static APBC_CLK(twsi1, TWSI1, 0, 26000000); +static APBC_CLK(twsi2, TWSI2, 0, 26000000); +static APBC_CLK(twsi3, TWSI3, 0, 26000000); +static APBC_CLK(twsi4, TWSI4, 0, 26000000); +static APBC_CLK(twsi5, TWSI5, 0, 26000000); +static APBC_CLK(twsi6, TWSI6, 0, 26000000); +static APBC_CLK(gpio, GPIO, 0, 26000000); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); +static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), +}; + +void __init mmp2_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); +} diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c new file mode 100644 index 000000000000..5e6c18ccebd4 --- /dev/null +++ b/arch/arm/mach-mmp/clock-pxa168.c @@ -0,0 +1,91 @@ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <mach/addr-map.h> + +#include "common.h" +#include "clock.h" + +/* + * APB clock register offsets for PXA168 + */ +#define APBC_UART1 APBC_REG(0x000) +#define APBC_UART2 APBC_REG(0x004) +#define APBC_GPIO APBC_REG(0x008) +#define APBC_PWM1 APBC_REG(0x00c) +#define APBC_PWM2 APBC_REG(0x010) +#define APBC_PWM3 APBC_REG(0x014) +#define APBC_PWM4 APBC_REG(0x018) +#define APBC_RTC APBC_REG(0x028) +#define APBC_TWSI0 APBC_REG(0x02c) +#define APBC_KPC APBC_REG(0x030) +#define APBC_TWSI1 APBC_REG(0x06c) +#define APBC_UART3 APBC_REG(0x070) +#define APBC_SSP1 APBC_REG(0x81c) +#define APBC_SSP2 APBC_REG(0x820) +#define APBC_SSP3 APBC_REG(0x84c) +#define APBC_SSP4 APBC_REG(0x858) +#define APBC_SSP5 APBC_REG(0x85c) + +#define APMU_NAND APMU_REG(0x060) +#define APMU_LCD APMU_REG(0x04c) +#define APMU_ETH APMU_REG(0x0fc) +#define APMU_USB APMU_REG(0x05c) + +/* APB peripheral clocks */ +static APBC_CLK(uart1, UART1, 1, 14745600); +static APBC_CLK(uart2, UART2, 1, 14745600); +static APBC_CLK(uart3, UART3, 1, 14745600); +static APBC_CLK(twsi0, TWSI0, 1, 33000000); +static APBC_CLK(twsi1, TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PWM1, 1, 13000000); +static APBC_CLK(pwm2, PWM2, 1, 13000000); +static APBC_CLK(pwm3, PWM3, 1, 13000000); +static APBC_CLK(pwm4, PWM4, 1, 13000000); +static APBC_CLK(ssp1, SSP1, 4, 0); +static APBC_CLK(ssp2, SSP2, 4, 0); +static APBC_CLK(ssp3, SSP3, 4, 0); +static APBC_CLK(ssp4, SSP4, 4, 0); +static APBC_CLK(ssp5, SSP5, 4, 0); +static APBC_CLK(gpio, GPIO, 0, 13000000); +static APBC_CLK(keypad, KPC, 0, 32000); +static APBC_CLK(rtc, RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(lcd, LCD, 0x7f, 312000000); +static APMU_CLK(eth, ETH, 0x09, 0); +static APMU_CLK(usb, USB, 0x12, 0); + +/* device and clock bindings */ +static struct clk_lookup pxa168_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), + INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), + INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), + INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), + INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), + INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + +void __init pxa168_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); +} diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c new file mode 100644 index 000000000000..933ea71d0b56 --- /dev/null +++ b/arch/arm/mach-mmp/clock-pxa910.c @@ -0,0 +1,67 @@ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <mach/addr-map.h> + +#include "common.h" +#include "clock.h" + +/* + * APB Clock register offsets for PXA910 + */ +#define APBC_UART0 APBC_REG(0x000) +#define APBC_UART1 APBC_REG(0x004) +#define APBC_GPIO APBC_REG(0x008) +#define APBC_PWM1 APBC_REG(0x00c) +#define APBC_PWM2 APBC_REG(0x010) +#define APBC_PWM3 APBC_REG(0x014) +#define APBC_PWM4 APBC_REG(0x018) +#define APBC_SSP1 APBC_REG(0x01c) +#define APBC_SSP2 APBC_REG(0x020) +#define APBC_RTC APBC_REG(0x028) +#define APBC_TWSI0 APBC_REG(0x02c) +#define APBC_KPC APBC_REG(0x030) +#define APBC_SSP3 APBC_REG(0x04c) +#define APBC_TWSI1 APBC_REG(0x06c) + +#define APMU_NAND APMU_REG(0x060) +#define APMU_USB APMU_REG(0x05c) + +static APBC_CLK(uart1, UART0, 1, 14745600); +static APBC_CLK(uart2, UART1, 1, 14745600); +static APBC_CLK(twsi0, TWSI0, 1, 33000000); +static APBC_CLK(twsi1, TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PWM1, 1, 13000000); +static APBC_CLK(pwm2, PWM2, 1, 13000000); +static APBC_CLK(pwm3, PWM3, 1, 13000000); +static APBC_CLK(pwm4, PWM4, 1, 13000000); +static APBC_CLK(gpio, GPIO, 0, 13000000); +static APBC_CLK(rtc, RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(u2o, USB, 0x1b, 480000000); + +/* device and clock bindings */ +static struct clk_lookup pxa910_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + +void __init pxa910_clk_init(void) +{ + clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); +} diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index 1c9d6c1ea97a..bd453274fca2 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -7,3 +7,6 @@ extern void timer_init(int irq); extern void __init icu_init_irq(void); extern void __init mmp_map_io(void); extern void mmp_restart(char, const char *); +extern void __init pxa168_clk_init(void); +extern void __init pxa910_clk_init(void); +extern void __init mmp2_clk_init(void); diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 68b0c93ec6a1..ddc812f40341 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -13,101 +13,6 @@ #include <mach/addr-map.h> -/* - * APB clock register offsets for PXA168 - */ -#define APBC_PXA168_UART1 APBC_REG(0x000) -#define APBC_PXA168_UART2 APBC_REG(0x004) -#define APBC_PXA168_GPIO APBC_REG(0x008) -#define APBC_PXA168_PWM1 APBC_REG(0x00c) -#define APBC_PXA168_PWM2 APBC_REG(0x010) -#define APBC_PXA168_PWM3 APBC_REG(0x014) -#define APBC_PXA168_PWM4 APBC_REG(0x018) -#define APBC_PXA168_RTC APBC_REG(0x028) -#define APBC_PXA168_TWSI0 APBC_REG(0x02c) -#define APBC_PXA168_KPC APBC_REG(0x030) -#define APBC_PXA168_TIMERS APBC_REG(0x034) -#define APBC_PXA168_AIB APBC_REG(0x03c) -#define APBC_PXA168_SW_JTAG APBC_REG(0x040) -#define APBC_PXA168_ONEWIRE APBC_REG(0x048) -#define APBC_PXA168_ASFAR APBC_REG(0x050) -#define APBC_PXA168_ASSAR APBC_REG(0x054) -#define APBC_PXA168_TWSI1 APBC_REG(0x06c) -#define APBC_PXA168_UART3 APBC_REG(0x070) -#define APBC_PXA168_AC97 APBC_REG(0x084) -#define APBC_PXA168_SSP1 APBC_REG(0x81c) -#define APBC_PXA168_SSP2 APBC_REG(0x820) -#define APBC_PXA168_SSP3 APBC_REG(0x84c) -#define APBC_PXA168_SSP4 APBC_REG(0x858) -#define APBC_PXA168_SSP5 APBC_REG(0x85c) - -/* - * APB Clock register offsets for PXA910 - */ -#define APBC_PXA910_UART0 APBC_REG(0x000) -#define APBC_PXA910_UART1 APBC_REG(0x004) -#define APBC_PXA910_GPIO APBC_REG(0x008) -#define APBC_PXA910_PWM1 APBC_REG(0x00c) -#define APBC_PXA910_PWM2 APBC_REG(0x010) -#define APBC_PXA910_PWM3 APBC_REG(0x014) -#define APBC_PXA910_PWM4 APBC_REG(0x018) -#define APBC_PXA910_SSP1 APBC_REG(0x01c) -#define APBC_PXA910_SSP2 APBC_REG(0x020) -#define APBC_PXA910_IPC APBC_REG(0x024) -#define APBC_PXA910_RTC APBC_REG(0x028) -#define APBC_PXA910_TWSI0 APBC_REG(0x02c) -#define APBC_PXA910_KPC APBC_REG(0x030) -#define APBC_PXA910_TIMERS APBC_REG(0x034) -#define APBC_PXA910_TBROT APBC_REG(0x038) -#define APBC_PXA910_AIB APBC_REG(0x03c) -#define APBC_PXA910_SW_JTAG APBC_REG(0x040) -#define APBC_PXA910_TIMERS1 APBC_REG(0x044) -#define APBC_PXA910_ONEWIRE APBC_REG(0x048) -#define APBC_PXA910_SSP3 APBC_REG(0x04c) -#define APBC_PXA910_ASFAR APBC_REG(0x050) -#define APBC_PXA910_ASSAR APBC_REG(0x054) - -/* - * APB Clock register offsets for MMP2 - */ -#define APBC_MMP2_RTC APBC_REG(0x000) -#define APBC_MMP2_TWSI1 APBC_REG(0x004) -#define APBC_MMP2_TWSI2 APBC_REG(0x008) -#define APBC_MMP2_TWSI3 APBC_REG(0x00c) -#define APBC_MMP2_TWSI4 APBC_REG(0x010) -#define APBC_MMP2_ONEWIRE APBC_REG(0x014) -#define APBC_MMP2_KPC APBC_REG(0x018) -#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) -#define APBC_MMP2_SW_JTAG APBC_REG(0x020) -#define APBC_MMP2_TIMERS APBC_REG(0x024) -#define APBC_MMP2_UART1 APBC_REG(0x02c) -#define APBC_MMP2_UART2 APBC_REG(0x030) -#define APBC_MMP2_UART3 APBC_REG(0x034) -#define APBC_MMP2_GPIO APBC_REG(0x038) -#define APBC_MMP2_PWM0 APBC_REG(0x03c) -#define APBC_MMP2_PWM1 APBC_REG(0x040) -#define APBC_MMP2_PWM2 APBC_REG(0x044) -#define APBC_MMP2_PWM3 APBC_REG(0x048) -#define APBC_MMP2_SSP0 APBC_REG(0x04c) -#define APBC_MMP2_SSP1 APBC_REG(0x050) -#define APBC_MMP2_SSP2 APBC_REG(0x054) -#define APBC_MMP2_SSP3 APBC_REG(0x058) -#define APBC_MMP2_SSP4 APBC_REG(0x05c) -#define APBC_MMP2_SSP5 APBC_REG(0x060) -#define APBC_MMP2_AIB APBC_REG(0x064) -#define APBC_MMP2_ASFAR APBC_REG(0x068) -#define APBC_MMP2_ASSAR APBC_REG(0x06c) -#define APBC_MMP2_USIM APBC_REG(0x070) -#define APBC_MMP2_MPMU APBC_REG(0x074) -#define APBC_MMP2_IPC APBC_REG(0x078) -#define APBC_MMP2_TWSI5 APBC_REG(0x07c) -#define APBC_MMP2_TWSI6 APBC_REG(0x080) -#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) -#define APBC_MMP2_UART4 APBC_REG(0x088) -#define APBC_MMP2_RIPC APBC_REG(0x08c) -#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ -#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) - /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index 7af8deb63e83..93c8d0e29bb9 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -13,21 +13,6 @@ #include <mach/addr-map.h> -/* Clock Reset Control */ -#define APMU_IRE APMU_REG(0x048) -#define APMU_LCD APMU_REG(0x04c) -#define APMU_CCIC APMU_REG(0x050) -#define APMU_SDH0 APMU_REG(0x054) -#define APMU_SDH1 APMU_REG(0x058) -#define APMU_USB APMU_REG(0x05c) -#define APMU_NAND APMU_REG(0x060) -#define APMU_DMA APMU_REG(0x064) -#define APMU_GEU APMU_REG(0x068) -#define APMU_BUS APMU_REG(0x06c) -#define APMU_SDH2 APMU_REG(0x0e8) -#define APMU_SDH3 APMU_REG(0x0ec) -#define APMU_ETH APMU_REG(0x0fc) - #define APMU_FNCLK_EN (1 << 4) #define APMU_AXICLK_EN (1 << 3) #define APMU_FNRST_DIS (1 << 1) diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c index e60c7d98922b..3c71246cd994 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq.c @@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) status = readl_relaxed(data->reg_status) & ~mask; if (status == 0) break; - n = find_first_bit(&status, BITS_PER_LONG); - while (n < BITS_PER_LONG) { + for_each_set_bit(n, &status, BITS_PER_LONG) { generic_handle_irq(icu_data[i].virq_base + n); - n = find_next_bit(&status, BITS_PER_LONG, n + 1); } } } diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index c709a24a9d25..3a3768c7a191 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -20,7 +20,6 @@ #include <asm/mach/time.h> #include <mach/addr-map.h> #include <mach/regs-apbc.h> -#include <mach/regs-apmu.h> #include <mach/cputype.h> #include <mach/irqs.h> #include <mach/dma.h> @@ -29,7 +28,6 @@ #include <mach/mmp2.h> #include "common.h" -#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -98,95 +96,36 @@ void __init mmp2_init_irq(void) mmp2_init_icu(); } -static void sdhc_clk_enable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst |= clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -static void sdhc_clk_disable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst &= ~clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -struct clkops sdhc_clk_ops = { - .enable = sdhc_clk_enable, - .disable = sdhc_clk_disable, -}; - -/* APB peripheral clocks */ -static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); -static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); -static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); -static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); -static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); -static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); -static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); -static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); -static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); -static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); -static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000); - -static APMU_CLK(nand, NAND, 0xbf, 100000000); -static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); - -static struct clk_lookup mmp2_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), - INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), - INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), - INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), -}; - static int __init mmp2_init(void) { if (cpu_is_mmp2()) { #ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(); + tauros2_init(0); #endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(mmp2_addr_map); pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); - clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); + mmp2_clk_init(); } return 0; } postcore_initcall(mmp2_init); +#define APBC_TIMERS APBC_REG(0x024) + static void __init mmp2_timer_init(void) { unsigned long clk_rst; - __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); /* * enable bus/functional clock, enable 6.5MHz (divider 4), * release reset */ clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_MMP2_TIMERS); + __raw_writel(clk_rst, APBC_TIMERS); timer_init(IRQ_MMP2_TIMER1); } diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 62d787c34475..b7f074f15498 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -18,8 +18,8 @@ #include <asm/mach/time.h> #include <asm/system_misc.h> -#include <mach/addr-map.h> #include <mach/cputype.h> +#include <mach/addr-map.h> #include <mach/regs-apbc.h> #include <mach/regs-apmu.h> #include <mach/irqs.h> @@ -50,62 +50,13 @@ void __init pxa168_init_irq(void) icu_init_irq(); } -/* APB peripheral clocks */ -static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); -static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); -static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); -static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); -static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); -static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); -static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); -static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); -static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); -static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); -static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); -static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); -static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); -static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000); -static APBC_CLK(keypad, PXA168_KPC, 0, 32000); -static APBC_CLK(rtc, PXA168_RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(lcd, LCD, 0x7f, 312000000); -static APMU_CLK(eth, ETH, 0x09, 0); -static APMU_CLK(usb, USB, 0x12, 0); - -/* device and clock bindings */ -static struct clk_lookup pxa168_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), - INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), - INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), - INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), - INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), - INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), - INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), - INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); - clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); + pxa168_clk_init(); } return 0; @@ -114,6 +65,7 @@ postcore_initcall(pxa168_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) +#define APBC_TIMERS APBC_REG(0x34) static void __init pxa168_timer_init(void) { @@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void) * ourselves instead of using clk_* API. Clock rate is defined * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); /* 3.25MHz, bus/functional clock enabled, release reset */ - __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_TIMERS); timer_init(IRQ_PXA168_TIMER1); } diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 6da52e9f2bdc..8b1e16fbb7a5 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -14,10 +14,10 @@ #include <linux/io.h> #include <linux/platform_device.h> +#include <asm/hardware/cache-tauros2.h> #include <asm/mach/time.h> #include <mach/addr-map.h> #include <mach/regs-apbc.h> -#include <mach/regs-apmu.h> #include <mach/cputype.h> #include <mach/irqs.h> #include <mach/dma.h> @@ -25,7 +25,6 @@ #include <mach/devices.h> #include "common.h" -#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -82,44 +81,16 @@ void __init pxa910_init_irq(void) icu_init_irq(); } -/* APB peripheral clocks */ -static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); -static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); -static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); -static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); -static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); -static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); -static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); -static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); -static APBC_CLK(rtc, PXA910_RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(u2o, USB, 0x1b, 480000000); - -/* device and clock bindings */ -static struct clk_lookup pxa910_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - static int __init pxa910_init(void) { if (cpu_is_pxa910()) { +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); - clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); + pxa910_clk_init(); } return 0; @@ -128,12 +99,13 @@ postcore_initcall(pxa910_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) +#define APBC_TIMERS APBC_REG(0x34) static void __init pxa910_timer_init(void) { /* reset and configure */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); - __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_TIMERS); timer_init(IRQ_PXA910_AP1_TIMER1); } diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 1cd40ad301d3..b2740c800e8c 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -38,8 +38,6 @@ config ARCH_QSD8X50 config ARCH_MSM8X60 bool "MSM8X60" - select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ - && !MACH_MSM8X60_FFA) select ARCH_MSM_SCORPIONMP select ARM_GIC select CPU_V7 @@ -47,16 +45,17 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP + select USE_OF config ARCH_MSM8960 bool "MSM8960" select ARCH_MSM_SCORPIONMP - select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) select ARM_GIC select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX select MSM_SCM if SMP + select USE_OF endchoice @@ -112,42 +111,6 @@ config MACH_QSD8X50A_ST1_5 help Support for the Qualcomm ST1.5. -config MACH_MSM8X60_RUMI3 - depends on ARCH_MSM8X60 - bool "MSM8x60 RUMI3" - help - Support for the Qualcomm MSM8x60 RUMI3 emulator. - -config MACH_MSM8X60_SURF - depends on ARCH_MSM8X60 - bool "MSM8x60 SURF" - help - Support for the Qualcomm MSM8x60 SURF eval board. - -config MACH_MSM8X60_SIM - depends on ARCH_MSM8X60 - bool "MSM8x60 Simulator" - help - Support for the Qualcomm MSM8x60 simulator. - -config MACH_MSM8X60_FFA - depends on ARCH_MSM8X60 - bool "MSM8x60 FFA" - help - Support for the Qualcomm MSM8x60 FFA eval board. - -config MACH_MSM8960_SIM - depends on ARCH_MSM8960 - bool "MSM8960 Simulator" - help - Support for the Qualcomm MSM8960 simulator. - -config MACH_MSM8960_RUMI3 - depends on ARCH_MSM8960 - bool "MSM8960 RUMI3" - help - Support for the Qualcomm MSM8960 RUMI3 emulator. - endmenu config MSM_SMD_PKG3 diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 4ad3969b9881..17519faf082f 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,11 +1,11 @@ -obj-y += io.o idle.o timer.o +obj-y += io.o timer.o obj-y += clock.o obj-$(CONFIG_DEBUG_FS) += clock-debug.o obj-$(CONFIG_MSM_VIC) += irq-vic.o obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o -obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o @@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o -obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o +obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o +obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot index 9b803a578b4d..f7d6ae9c3487 100644 --- a/arch/arm/mach-msm/Makefile.boot +++ b/arch/arm/mach-msm/Makefile.boot @@ -1,3 +1,6 @@ zreladdr-y += 0x10008000 params_phys-y := 0x10000100 initrd_phys-y := 0x10800000 + +dtb-$(CONFIG_ARCH_MSM8X60) += msm8660-surf.dtb +dtb-$(CONFIG_ARCH_MSM8960) += msm8960-cdp.dtb diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c deleted file mode 100644 index 805d4ee53f7e..000000000000 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ /dev/null @@ -1,525 +0,0 @@ -/* arch/arm/mach-msm/acpuclock.c - * - * MSM architecture clock driver - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated - * Author: San Mehat <san@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/cpufreq.h> -#include <linux/mutex.h> -#include <linux/io.h> -#include <mach/board.h> -#include <mach/msm_iomap.h> - -#include "proc_comm.h" -#include "acpuclock.h" - - -#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) -#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) -#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) - -/* - * ARM11 clock configuration for specific ACPU speeds - */ - -#define ACPU_PLL_TCXO -1 -#define ACPU_PLL_0 0 -#define ACPU_PLL_1 1 -#define ACPU_PLL_2 2 -#define ACPU_PLL_3 3 - -#define PERF_SWITCH_DEBUG 0 -#define PERF_SWITCH_STEP_DEBUG 0 - -struct clock_state -{ - struct clkctl_acpu_speed *current_speed; - struct mutex lock; - uint32_t acpu_switch_time_us; - uint32_t max_speed_delta_khz; - uint32_t vdd_switch_time_us; - unsigned long power_collapse_khz; - unsigned long wait_for_irq_khz; -}; - -static struct clk *ebi1_clk; -static struct clock_state drv_state = { 0 }; - -static void __init acpuclk_init(void); - -/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ -enum { - VDD_0 = 0, - VDD_1 = 1, - VDD_2 = 2, - VDD_3 = 3, - VDD_4 = 3, - VDD_5 = 3, - VDD_6 = 3, - VDD_7 = 7, - VDD_END -}; - -struct clkctl_acpu_speed { - unsigned int a11clk_khz; - int pll; - unsigned int a11clk_src_sel; - unsigned int a11clk_src_div; - unsigned int ahbclk_khz; - unsigned int ahbclk_div; - int vdd; - unsigned int axiclk_khz; - unsigned long lpj; /* loops_per_jiffy */ -/* Index in acpu_freq_tbl[] for steppings. */ - short down; - short up; -}; - -/* - * ACPU speed table. Complete table is shown but certain speeds are commented - * out to optimized speed switching. Initialize loops_per_jiffy to 0. - * - * Table stepping up/down is optimized for 256mhz jumps while staying on the - * same PLL. - */ -#if (0) -static struct clkctl_acpu_speed acpu_freq_tbl[] = { - { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, - { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, - { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, - { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, - { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, - { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, - { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, - { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, - { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, - { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, - { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, - { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, - { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, - { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, -}; -#else /* Table of freq we currently use. */ -static struct clkctl_acpu_speed acpu_freq_tbl[] = { - { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, - { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, - { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, - { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, - { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, - { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, - { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, - { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, -}; -#endif - - -#ifdef CONFIG_CPU_FREQ_TABLE -static struct cpufreq_frequency_table freq_table[] = { - { 0, 122880 }, - { 1, 128000 }, - { 2, 245760 }, - { 3, 384000 }, - { 4, 528000 }, - { 5, CPUFREQ_TABLE_END }, -}; -#endif - -static int pc_pll_request(unsigned id, unsigned on) -{ - int res; - on = !!on; - -#if PERF_SWITCH_DEBUG - if (on) - printk(KERN_DEBUG "Enabling PLL %d\n", id); - else - printk(KERN_DEBUG "Disabling PLL %d\n", id); -#endif - - res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); - if (res < 0) - return res; - -#if PERF_SWITCH_DEBUG - if (on) - printk(KERN_DEBUG "PLL %d enabled\n", id); - else - printk(KERN_DEBUG "PLL %d disabled\n", id); -#endif - return res; -} - - -/*---------------------------------------------------------------------------- - * ARM11 'owned' clock control - *---------------------------------------------------------------------------*/ - -unsigned long acpuclk_power_collapse(void) { - int ret = acpuclk_get_rate(); - ret *= 1000; - if (ret > drv_state.power_collapse_khz) - acpuclk_set_rate(drv_state.power_collapse_khz, 1); - return ret; -} - -unsigned long acpuclk_get_wfi_rate(void) -{ - return drv_state.wait_for_irq_khz; -} - -unsigned long acpuclk_wait_for_irq(void) { - int ret = acpuclk_get_rate(); - ret *= 1000; - if (ret > drv_state.wait_for_irq_khz) - acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); - return ret; -} - -static int acpuclk_set_vdd_level(int vdd) -{ - uint32_t current_vdd; - - current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", - current_vdd, vdd); -#endif - writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); - udelay(drv_state.vdd_switch_time_us); - if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { -#if PERF_SWITCH_DEBUG - printk(KERN_ERR "acpuclock: VDD set failed\n"); -#endif - return -EIO; - } - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "acpuclock: VDD switched\n"); -#endif - return 0; -} - -/* Set proper dividers for the given clock speed. */ -static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { - uint32_t reg_clkctl, reg_clksel, clk_div; - - /* AHB_CLK_DIV */ - clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; - /* - * If the new clock divider is higher than the previous, then - * program the divider before switching the clock - */ - if (hunt_s->ahbclk_div > clk_div) { - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~(0x3 << 1); - reg_clksel |= (hunt_s->ahbclk_div << 1); - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } - if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { - /* SRC0 */ - - /* Program clock source */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0x07 << 4); - reg_clkctl |= (hunt_s->a11clk_src_sel << 4); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock divider */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~0xf; - reg_clkctl |= hunt_s->a11clk_src_div; - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock source selection */ - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } else { - /* SRC1 */ - - /* Program clock source */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0x07 << 12); - reg_clkctl |= (hunt_s->a11clk_src_sel << 12); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock divider */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl &= ~(0xf << 8); - reg_clkctl |= (hunt_s->a11clk_src_div << 8); - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - - /* Program clock source selection */ - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } - - /* - * If the new clock divider is lower than the previous, then - * program the divider after switching the clock - */ - if (hunt_s->ahbclk_div < clk_div) { - reg_clksel = readl(A11S_CLK_SEL_ADDR); - reg_clksel &= ~(0x3 << 1); - reg_clksel |= (hunt_s->ahbclk_div << 1); - writel(reg_clksel, A11S_CLK_SEL_ADDR); - } -} - -int acpuclk_set_rate(unsigned long rate, int for_power_collapse) -{ - uint32_t reg_clkctl; - struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; - int rc = 0; - unsigned int plls_enabled = 0, pll; - - strt_s = cur_s = drv_state.current_speed; - - WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); - if (cur_s == NULL) - return -ENOENT; - - if (rate == (cur_s->a11clk_khz * 1000)) - return 0; - - for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { - if (tgt_s->a11clk_khz == (rate / 1000)) - break; - } - - if (tgt_s->a11clk_khz == 0) - return -EINVAL; - - /* Choose the highest speed speed at or below 'rate' with same PLL. */ - if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { - while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) - tgt_s--; - } - - if (strt_s->pll != ACPU_PLL_TCXO) - plls_enabled |= 1 << strt_s->pll; - - if (!for_power_collapse) { - mutex_lock(&drv_state.lock); - if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { - rc = pc_pll_request(tgt_s->pll, 1); - if (rc < 0) { - pr_err("PLL%d enable failed (%d)\n", - tgt_s->pll, rc); - goto out; - } - plls_enabled |= 1 << tgt_s->pll; - } - /* Increase VDD if needed. */ - if (tgt_s->vdd > cur_s->vdd) { - if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { - printk(KERN_ERR "Unable to switch ACPU vdd\n"); - goto out; - } - } - } - - /* Set wait states for CPU between frequency changes */ - reg_clkctl = readl(A11S_CLK_CNTL_ADDR); - reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ - writel(reg_clkctl, A11S_CLK_CNTL_ADDR); - -#if PERF_SWITCH_DEBUG - printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", - strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); -#endif - - while (cur_s != tgt_s) { - /* - * Always jump to target freq if within 256mhz, regulardless of - * PLL. If differnece is greater, use the predefinied - * steppings in the table. - */ - int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); - if (d > drv_state.max_speed_delta_khz) { - /* Step up or down depending on target vs current. */ - int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? - cur_s->up : cur_s->down; - if (clk_index < 0) { /* This should not happen. */ - printk(KERN_ERR "cur:%u target: %u\n", - cur_s->a11clk_khz, tgt_s->a11clk_khz); - rc = -EINVAL; - goto out; - } - cur_s = &acpu_freq_tbl[clk_index]; - } else { - cur_s = tgt_s; - } -#if PERF_SWITCH_STEP_DEBUG - printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", - __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); -#endif - if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO - && !(plls_enabled & (1 << cur_s->pll))) { - rc = pc_pll_request(cur_s->pll, 1); - if (rc < 0) { - pr_err("PLL%d enable failed (%d)\n", - cur_s->pll, rc); - goto out; - } - plls_enabled |= 1 << cur_s->pll; - } - - acpuclk_set_div(cur_s); - drv_state.current_speed = cur_s; - /* Re-adjust lpj for the new clock speed. */ - loops_per_jiffy = cur_s->lpj; - udelay(drv_state.acpu_switch_time_us); - } - - /* Nothing else to do for power collapse. */ - if (for_power_collapse) - return 0; - - /* Disable PLLs we are not using anymore. */ - plls_enabled &= ~(1 << tgt_s->pll); - for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) - if (plls_enabled & (1 << pll)) { - rc = pc_pll_request(pll, 0); - if (rc < 0) { - pr_err("PLL%d disable failed (%d)\n", pll, rc); - goto out; - } - } - - /* Change the AXI bus frequency if we can. */ - if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { - rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); - if (rc < 0) - pr_err("Setting AXI min rate failed!\n"); - } - - /* Drop VDD level if we can. */ - if (tgt_s->vdd < strt_s->vdd) { - if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) - printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); - } - -#if PERF_SWITCH_DEBUG - printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); -#endif -out: - if (!for_power_collapse) - mutex_unlock(&drv_state.lock); - return rc; -} - -static void __init acpuclk_init(void) -{ - struct clkctl_acpu_speed *speed; - uint32_t div, sel; - int rc; - - /* - * Determine the rate of ACPU clock - */ - - if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ - /* CLK_SRC0_SEL */ - sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; - /* CLK_SRC0_DIV */ - div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; - } else { - /* CLK_SRC1_SEL */ - sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; - /* CLK_SRC1_DIV */ - div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; - } - - for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { - if (speed->a11clk_src_sel == sel - && (speed->a11clk_src_div == div)) - break; - } - if (speed->a11clk_khz == 0) { - printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); - return; - } - - drv_state.current_speed = speed; - - rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); - if (rc < 0) - pr_err("Setting AXI min rate failed!\n"); - - printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); -} - -unsigned long acpuclk_get_rate(void) -{ - WARN_ONCE(drv_state.current_speed == NULL, - "acpuclk_get_rate: not initialized\n"); - if (drv_state.current_speed) - return drv_state.current_speed->a11clk_khz; - else - return 0; -} - -uint32_t acpuclk_get_switch_time(void) -{ - return drv_state.acpu_switch_time_us; -} - -/*---------------------------------------------------------------------------- - * Clock driver initialization - *---------------------------------------------------------------------------*/ - -/* Initialize the lpj field in the acpu_freq_tbl. */ -static void __init lpj_init(void) -{ - int i; - const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; - for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { - acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, - base_clk->a11clk_khz, - acpu_freq_tbl[i].a11clk_khz); - } -} - -void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) -{ - pr_info("acpu_clock_init()\n"); - - ebi1_clk = clk_get(NULL, "ebi1_clk"); - - mutex_init(&drv_state.lock); - drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; - drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; - drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; - drv_state.power_collapse_khz = clkdata->power_collapse_khz; - drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; - acpuclk_init(); - lpj_init(); -#ifdef CONFIG_CPU_FREQ_TABLE - cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); -#endif -} diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h deleted file mode 100644 index 415de2eb9a5e..000000000000 --- a/arch/arm/mach-msm/acpuclock.h +++ /dev/null @@ -1,32 +0,0 @@ -/* arch/arm/mach-msm/acpuclock.h - * - * MSM architecture clock driver header - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007 QUALCOMM Incorporated - * Author: San Mehat <san@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H -#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H - -int acpuclk_set_rate(unsigned long rate, int for_power_collapse); -unsigned long acpuclk_get_rate(void); -uint32_t acpuclk_get_switch_time(void); -unsigned long acpuclk_wait_for_irq(void); -unsigned long acpuclk_power_collapse(void); -unsigned long acpuclk_get_wfi_rate(void); - - -#endif - diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c new file mode 100644 index 000000000000..f77f57f39104 --- /dev/null +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -0,0 +1,63 @@ +/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> +#include <asm/hardware/gic.h> + +#include <mach/board.h> +#include "common.h" + +static const struct of_device_id msm_dt_gic_match[] __initconst = { + { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, + {} +}; + +static void __init msm8x60_init_irq(void) +{ + of_irq_init(msm_dt_gic_match); +} + +static void __init msm8x60_init_late(void) +{ + smd_debugfs_init(); +} + +static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { + {} +}; + +static void __init msm8x60_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + msm_auxdata_lookup, NULL); +} + +static const char *msm8x60_fluid_match[] __initdata = { + "qcom,msm8660-fluid", + "qcom,msm8660-surf", + NULL +}; + +DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") + .map_io = msm_map_msm8x60_io, + .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, + .init_machine = msm8x60_dt_init, + .init_late = msm8x60_init_late, + .timer = &msm_dt_timer, + .dt_compat = msm8x60_fluid_match, +MACHINE_END diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c new file mode 100644 index 000000000000..8df99b8f3c92 --- /dev/null +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -0,0 +1,49 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +#include <asm/hardware/gic.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static const struct of_device_id msm_dt_gic_match[] __initconst = { + { .compatible = "qcom,msm-qgic2", .data = gic_of_init }, + { } +}; + +static void __init msm_dt_init_irq(void) +{ + of_irq_init(msm_dt_gic_match); +} + +static void __init msm_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const msm8960_dt_match[] __initconst = { + "qcom,msm8960-cdp", + NULL +}; + +DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") + .map_io = msm_map_msm8960_io, + .init_irq = msm_dt_init_irq, + .timer = &msm_dt_timer, + .init_machine = msm_dt_init, + .dt_compat = msm8960_dt_match, + .handle_irq = gic_handle_irq, +MACHINE_END diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 4fa3e99d9a62..6ce542e2e21c 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -36,6 +36,7 @@ #include <linux/mtd/partitions.h> #include "devices.h" +#include "common.h" static struct resource smc91x_resources[] = { [0] = { @@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = { &smc91x_device, }; -extern struct sys_timer msm_timer; - static void __init halibut_init_early(void) { arch_ioremap_caller = __msm_ioremap_caller; @@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") .init_irq = halibut_init_irq, .init_machine = halibut_init, .init_late = halibut_init_late, - .timer = &msm_timer, + .timer = &msm7x01_timer, MACHINE_END diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index cf1f89a5dc62..df00bc03ce74 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -30,7 +30,6 @@ #include <mach/board.h> #include <mach/hardware.h> -#include <mach/system.h> #include "board-mahimahi.h" #include "devices.h" diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c deleted file mode 100644 index 451ab1d43c92..000000000000 --- a/arch/arm/mach-msm/board-msm7x27.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. - * Author: Brian Swetland <swetland@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/power_supply.h> - -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/flash.h> -#include <asm/setup.h> -#ifdef CONFIG_CACHE_L2X0 -#include <asm/hardware/cache-l2x0.h> -#endif - -#include <mach/vreg.h> -#include <mach/mpp.h> -#include <mach/board.h> -#include <mach/msm_iomap.h> - -#include <linux/mtd/nand.h> -#include <linux/mtd/partitions.h> - -#include "devices.h" -#include "socinfo.h" -#include "clock.h" - -static struct resource smc91x_resources[] = { - [0] = { - .start = 0x9C004300, - .end = 0x9C0043ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MSM_GPIO_TO_INT(132), - .end = MSM_GPIO_TO_INT(132), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct platform_device *devices[] __initdata = { - &msm_device_uart3, - &msm_device_smd, - &msm_device_dmov, - &msm_device_nand, - &smc91x_device, -}; - -extern struct sys_timer msm_timer; - -static void __init msm7x2x_init_irq(void) -{ - msm_init_irq(); -} - -static void __init msm7x2x_init(void) -{ - if (socinfo_init() < 0) - BUG(); - - if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) { - smc91x_resources[0].start = 0x98000300; - smc91x_resources[0].end = 0x980003ff; - smc91x_resources[1].start = MSM_GPIO_TO_INT(85); - smc91x_resources[1].end = MSM_GPIO_TO_INT(85); - if (gpio_tlmm_config(GPIO_CFG(85, 0, - GPIO_INPUT, - GPIO_PULL_DOWN, - GPIO_2MA), - GPIO_ENABLE)) { - printk(KERN_ERR - "%s: Err: Config GPIO-85 INT\n", - __func__); - } - } - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init msm7x2x_map_io(void) -{ - msm_map_common_io(); - /* Technically dependent on the SoC but using machine_is - * macros since socinfo is not available this early and there - * are plans to restructure the code which will eliminate the - * need for socinfo. - */ - if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) - msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27); - - if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa()) - msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25); - -#ifdef CONFIG_CACHE_L2X0 - if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) { - /* 7x27 has 256KB L2 cache: - 64Kb/Way and 4-Way Associativity; - R/W latency: 3 cycles; - evmon/parity/share disabled. */ - l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000); - } -#endif -} - -static void __init msm7x2x_init_late(void) -{ - smd_debugfs_init(); -} - -MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") - .atag_offset = 0x100, - .map_io = msm7x2x_map_io, - .init_irq = msm7x2x_init_irq, - .init_machine = msm7x2x_init, - .init_late = msm7x2x_init_late, - .timer = &msm_timer, -MACHINE_END diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index a5001378135d..effa6f4336c7 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -38,8 +38,7 @@ #include "devices.h" #include "gpiomux.h" #include "proc_comm.h" - -extern struct sys_timer msm_timer; +#include "common.h" static void __init msm7x30_fixup(struct tag *tag, char **cmdline, struct meminfo *mi) @@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") @@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") @@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm_timer, + .timer = &msm7x30_timer, MACHINE_END diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c deleted file mode 100644 index 65f4a1daa2e5..000000000000 --- a/arch/arm/mach-msm/board-msm8960.c +++ /dev/null @@ -1,122 +0,0 @@ -/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/clkdev.h> -#include <linux/memblock.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/hardware/gic.h> -#include <asm/setup.h> - -#include <mach/board.h> -#include <mach/msm_iomap.h> - -#include "devices.h" - -static void __init msm8960_fixup(struct tag *tag, char **cmdline, - struct meminfo *mi) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM && - tag->u.mem.start == 0x40200000) { - tag->u.mem.start = 0x40000000; - tag->u.mem.size += SZ_2M; - } -} - -static void __init msm8960_reserve(void) -{ - memblock_remove(0x40000000, SZ_2M); -} - -static void __init msm8960_map_io(void) -{ - msm_map_msm8960_io(); -} - -static void __init msm8960_init_irq(void) -{ - unsigned int i; - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); - - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - - if (machine_is_msm8960_rumi3()) - writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); - - /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet - * as they are configured as level, which does not play nice with - * handle_percpu_irq. - */ - for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { - if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - irq_set_handler(i, handle_percpu_irq); - } -} - -static struct platform_device *sim_devices[] __initdata = { - &msm8960_device_uart_gsbi2, -}; - -static struct platform_device *rumi3_devices[] __initdata = { - &msm8960_device_uart_gsbi5, -}; - -static void __init msm8960_sim_init(void) -{ - platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices)); -} - -static void __init msm8960_rumi3_init(void) -{ - platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices)); -} - -static void __init msm8960_init_late(void) -{ - smd_debugfs_init(); -} - -MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") - .fixup = msm8960_fixup, - .reserve = msm8960_reserve, - .map_io = msm8960_map_io, - .init_irq = msm8960_init_irq, - .timer = &msm_timer, - .handle_irq = gic_handle_irq, - .init_machine = msm8960_sim_init, - .init_late = msm8960_init_late, -MACHINE_END - -MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") - .fixup = msm8960_fixup, - .reserve = msm8960_reserve, - .map_io = msm8960_map_io, - .init_irq = msm8960_init_irq, - .timer = &msm_timer, - .handle_irq = gic_handle_irq, - .init_machine = msm8960_rumi3_init, - .init_late = msm8960_init_late, -MACHINE_END - diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c deleted file mode 100644 index e37a724cd1eb..000000000000 --- a/arch/arm/mach-msm/board-msm8x60.c +++ /dev/null @@ -1,166 +0,0 @@ -/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/memblock.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/hardware/gic.h> -#include <asm/setup.h> - -#include <mach/board.h> -#include <mach/msm_iomap.h> - -static void __init msm8x60_fixup(struct tag *tag, char **cmdline, - struct meminfo *mi) -{ - for (; tag->hdr.size; tag = tag_next(tag)) - if (tag->hdr.tag == ATAG_MEM && - tag->u.mem.start == 0x40200000) { - tag->u.mem.start = 0x40000000; - tag->u.mem.size += SZ_2M; - } -} - -static void __init msm8x60_reserve(void) -{ - memblock_remove(0x40000000, SZ_2M); -} - -static void __init msm8x60_map_io(void) -{ - msm_map_msm8x60_io(); -} - -#ifdef CONFIG_OF -static struct of_device_id msm_dt_gic_match[] __initdata = { - { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, - {} -}; -#endif - -static void __init msm8x60_init_irq(void) -{ - if (!of_have_populated_dt()) - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); -#ifdef CONFIG_OF - else - of_irq_init(msm_dt_gic_match); -#endif - - /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ - writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - - /* RUMI does not adhere to GIC spec by enabling STIs by default. - * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. - */ - if (!machine_is_msm8x60_sim()) - writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); -} - -static void __init msm8x60_init(void) -{ -} - -static void __init msm8x60_init_late(void) -{ - smd_debugfs_init(); -} - -#ifdef CONFIG_OF -static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { - {} -}; - -static void __init msm8x60_dt_init(void) -{ - if (of_machine_is_compatible("qcom,msm8660-surf")) { - printk(KERN_INFO "Init surf UART registers\n"); - msm8x60_init_uart12dm(); - } - - of_platform_populate(NULL, of_default_bus_match_table, - msm_auxdata_lookup, NULL); -} - -static const char *msm8x60_fluid_match[] __initdata = { - "qcom,msm8660-fluid", - "qcom,msm8660-surf", - NULL -}; -#endif /* CONFIG_OF */ - -MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") - .fixup = msm8x60_fixup, - .reserve = msm8x60_reserve, - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, - .init_machine = msm8x60_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, -MACHINE_END - -#ifdef CONFIG_OF -/* TODO: General device tree support for all MSM. */ -DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") - .map_io = msm8x60_map_io, - .init_irq = msm8x60_init_irq, - .init_machine = msm8x60_dt_init, - .init_late = msm8x60_init_late, - .timer = &msm_timer, - .dt_compat = msm8x60_fluid_match, -MACHINE_END -#endif /* CONFIG_OF */ diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index c8fe0edb9761..b16b71abf5f6 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -35,8 +35,7 @@ #include <mach/mmc.h> #include "devices.h" - -extern struct sys_timer msm_timer; +#include "common.h" static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; @@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &msm_timer, + .timer = &qsd8x50_timer, MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") @@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &msm_timer, + .timer = &qsd8x50_timer, MACHINE_END diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 2e569ab10eef..b7b0fc7e3278 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -27,7 +27,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <mach/system.h> #include <mach/vreg.h> #include <mach/board.h> diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index bbe13f12fa01..4ba0800e243e 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -31,6 +31,7 @@ #include "devices.h" #include "board-trout.h" +#include "common.h" extern int trout_init_mmc(unsigned int); @@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = { &msm_device_i2c, }; -extern struct sys_timer msm_timer; - static void __init trout_init_early(void) { arch_ioremap_caller = __msm_ioremap_caller; @@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream") .init_irq = trout_init_irq, .init_machine = trout_init, .init_late = trout_init_late, - .timer = &msm_timer, + .timer = &msm7x01_timer, MACHINE_END diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c index 63b711311086..a52c970df157 100644 --- a/arch/arm/mach-msm/clock-pcom.c +++ b/arch/arm/mach-msm/clock-pcom.c @@ -25,7 +25,7 @@ /* * glue for the proc_comm interface */ -int pc_clk_enable(unsigned id) +static int pc_clk_enable(unsigned id) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); if (rc < 0) @@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id) return (int)id < 0 ? -EINVAL : 0; } -void pc_clk_disable(unsigned id) +static void pc_clk_disable(unsigned id) { msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); } @@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_rate(unsigned id, unsigned rate) +static int pc_clk_set_rate(unsigned id, unsigned rate) { /* The rate _might_ be rounded off to the nearest KHz value by the * remote function. So a return value of 0 doesn't necessarily mean @@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_min_rate(unsigned id, unsigned rate) +static int pc_clk_set_min_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); if (rc < 0) @@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_max_rate(unsigned id, unsigned rate) +static int pc_clk_set_max_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); if (rc < 0) @@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -int pc_clk_set_flags(unsigned id, unsigned flags) +static int pc_clk_set_flags(unsigned id, unsigned flags) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); if (rc < 0) @@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags) return (int)id < 0 ? -EINVAL : 0; } -unsigned pc_clk_get_rate(unsigned id) +static unsigned pc_clk_get_rate(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) return 0; @@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id) return id; } -unsigned pc_clk_is_enabled(unsigned id) +static unsigned pc_clk_is_enabled(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) return 0; @@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id) return id; } -long pc_clk_round_rate(unsigned id, unsigned rate) +static long pc_clk_round_rate(unsigned id, unsigned rate) { /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h new file mode 100644 index 000000000000..d68e5d7854f5 --- /dev/null +++ b/arch/arm/mach-msm/common.h @@ -0,0 +1,30 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_COMMON_H +#define __MACH_COMMON_H + +extern struct sys_timer msm7x01_timer; +extern struct sys_timer msm7x30_timer; +extern struct sys_timer msm_dt_timer; +extern struct sys_timer qsd8x50_timer; + +extern void msm_map_common_io(void); +extern void msm_map_msm7x30_io(void); +extern void msm_map_msm8x60_io(void); +extern void msm_map_msm8960_io(void); +extern void msm_map_qsd8x50_io(void); + +extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, + unsigned int mtype, void *caller); + + +#endif diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c deleted file mode 100644 index d9e1f26475de..000000000000 --- a/arch/arm/mach-msm/devices-msm8960.c +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <linux/dma-mapping.h> -#include <mach/irqs-8960.h> -#include <mach/board.h> - -#include "devices.h" - -#define MSM_GSBI2_PHYS 0x16100000 -#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000) - -#define MSM_GSBI5_PHYS 0x16400000 -#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000) - -static struct resource resources_uart_gsbi2[] = { - { - .start = GSBI2_UARTDM_IRQ, - .end = GSBI2_UARTDM_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .start = MSM_UART2DM_PHYS, - .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, - .name = "uart_resource", - .flags = IORESOURCE_MEM, - }, - { - .start = MSM_GSBI2_PHYS, - .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1, - .name = "gsbi_resource", - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device msm8960_device_uart_gsbi2 = { - .name = "msm_serial", - .id = 0, - .num_resources = ARRAY_SIZE(resources_uart_gsbi2), - .resource = resources_uart_gsbi2, -}; - -static struct resource resources_uart_gsbi5[] = { - { - .start = GSBI5_UARTDM_IRQ, - .end = GSBI5_UARTDM_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .start = MSM_UART5DM_PHYS, - .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1, - .name = "uart_resource", - .flags = IORESOURCE_MEM, - }, - { - .start = MSM_GSBI5_PHYS, - .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1, - .name = "gsbi_resource", - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device msm8960_device_uart_gsbi5 = { - .name = "msm_serial", - .id = 0, - .num_resources = ARRAY_SIZE(resources_uart_gsbi5), - .resource = resources_uart_gsbi5, -}; diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c index 02cae5e2951c..354b91d4c3ac 100644 --- a/arch/arm/mach-msm/dma.c +++ b/arch/arm/mach-msm/dma.c @@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); - list_del(&cmd->list); - list_add_tail(&cmd->list, &active_commands[id]); + list_move_tail(&cmd->list, &active_commands[id]); if (cmd->execute_func) cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c deleted file mode 100644 index 0c9e13c65743..000000000000 --- a/arch/arm/mach-msm/idle.c +++ /dev/null @@ -1,49 +0,0 @@ -/* arch/arm/mach-msm/idle.c - * - * Idle processing for MSM7K - work around bugs with SWFI. - * - * Copyright (c) 2007 QUALCOMM Incorporated. - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/init.h> -#include <asm/system.h> - -static void msm_idle(void) -{ -#ifdef CONFIG_MSM7X00A_IDLE - asm volatile ( - - "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t" - "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t" - "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t" - "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t" - - "mov r0, #0 /* prepare wfi value */ \n\t" - "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t" - "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t" - "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t" - - "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t" - - : : : "r0","r1" ); -#endif -} - -static int __init msm_idle_init(void) -{ - arm_pm_idle = msm_idle; - return 0; -} - -arch_initcall(msm_idle_init); diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index 435f8edfafd1..0a0c393d8e31 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h @@ -22,27 +22,14 @@ /* platform device data structures */ -struct msm_acpu_clock_platform_data -{ - uint32_t acpu_switch_time_us; - uint32_t max_speed_delta_khz; - uint32_t vdd_switch_time_us; - unsigned long power_collapse_khz; - unsigned long wait_for_irq_khz; -}; - struct clk_lookup; -extern struct sys_timer msm_timer; - /* common init routines for use by arch/arm/mach-msm/board-*.c */ void __init msm_add_devices(void); -void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); -void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); int __init msm_add_sdcc(unsigned int controller, struct msm_mmc_platform_data *plat, unsigned int stat_irq, unsigned long stat_irq_flags); diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 6c4046c21296..67dc0e98b958 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -105,11 +105,4 @@ #define MSM_AD5_PHYS 0xAC000000 #define MSM_AD5_SIZE (SZ_1M*13) -#ifndef __ASSEMBLY__ - -extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, - unsigned int mtype, void *caller); - -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index f944fe65a657..198202c267c8 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -100,8 +100,4 @@ #define MSM_HSUSB_PHYS 0xA3600000 #define MSM_HSUSB_SIZE SZ_1K -#ifndef __ASSEMBLY__ -extern void msm_map_msm7x30_io(void); -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index a1752c0284fc..9819a556acae 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -46,12 +46,8 @@ #define MSM8960_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8960_UART -#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_BASE 0xF0040000 #define MSM_DEBUG_UART_PHYS 0x16440000 #endif -#ifndef __ASSEMBLY__ -extern void msm_map_msm8960_io(void); -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index da77cc1d545d..0faa894729b7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -122,8 +122,4 @@ #define MSM_SDC4_PHYS 0xA0600000 #define MSM_SDC4_SIZE SZ_4K -#ifndef __ASSEMBLY__ -extern void msm_map_qsd8x50_io(void); -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 5aed57dc808c..c6d38f1d0c98 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -63,12 +63,8 @@ #define MSM8X60_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8660_UART -#define MSM_DEBUG_UART_BASE 0xE1040000 +#define MSM_DEBUG_UART_BASE 0xF0040000 #define MSM_DEBUG_UART_PHYS 0x19C40000 #endif -#ifndef __ASSEMBLY__ -extern void msm_map_msm8x60_io(void); -#endif - #endif diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h deleted file mode 100644 index f5fb2ec87ffe..000000000000 --- a/arch/arm/mach-msm/include/mach/system.h +++ /dev/null @@ -1,19 +0,0 @@ -/* arch/arm/mach-msm/include/mach/system.h - * - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* low level hardware reset hook -- for example, hitting the - * PSHOLD line on the PMIC to hard reset the system - */ -extern void (*msm_hw_reset_hook)(void); diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index a1e7b1168850..3854f6f20ce2 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -29,30 +29,32 @@ #include <mach/board.h> -#define MSM_CHIP_DEVICE(name, chip) { \ +#include "common.h" + +#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ .virtual = (unsigned long) MSM_##name##_BASE, \ .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ .length = chip##_##name##_SIZE, \ - .type = MT_DEVICE_NONSHARED, \ + .type = mem_type, \ } +#define MSM_DEVICE_TYPE(name, mem_type) \ + MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type) +#define MSM_CHIP_DEVICE(name, chip) \ + MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE) #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) -#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ - || defined(CONFIG_ARCH_MSM7X25) +#if defined(CONFIG_ARCH_MSM7X00A) static struct map_desc msm_io_desc[] __initdata = { - MSM_DEVICE(VIC), - MSM_CHIP_DEVICE(CSR, MSM7X00), - MSM_DEVICE(DMOV), - MSM_CHIP_DEVICE(GPIO1, MSM7X00), - MSM_CHIP_DEVICE(GPIO2, MSM7X00), - MSM_DEVICE(CLK_CTL), + MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED), + MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), + MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), + MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE(DEBUG_UART), -#endif -#ifdef CONFIG_ARCH_MSM7X30 - MSM_DEVICE(GCC), + MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), #endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index e012dc8391cf..2d791e6b4ad1 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -22,17 +22,12 @@ #include <asm/mach-types.h> #include <asm/smp_plat.h> -#include <mach/msm_iomap.h> - #include "scm-boot.h" #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 #define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 -/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ -#define GIC_PPI_EDGE_MASK 0xFFFFD7FF - extern void msm_secondary_startup(void); /* * control for which core is the next to come out of the secondary @@ -50,9 +45,6 @@ static inline int get_core_count(void) void __cpuinit platform_secondary_init(unsigned int cpu) { - /* Configure edge-triggered PPIs */ - writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); - /* * if any interrupts are already enabled for the primary * core (e.g. timer irq), then they will not have been enabled diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c index 9980dc736e7b..8f1eecd88186 100644 --- a/arch/arm/mach-msm/proc_comm.c +++ b/arch/arm/mach-msm/proc_comm.c @@ -19,7 +19,6 @@ #include <linux/io.h> #include <linux/spinlock.h> #include <mach/msm_iomap.h> -#include <mach/system.h> #include "proc_comm.h" diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index 657be73297db..c5a2eddc6cdc 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c @@ -30,7 +30,6 @@ #include <linux/delay.h> #include <mach/msm_smd.h> -#include <mach/system.h> #include "smd_private.h" #include "proc_comm.h" @@ -39,8 +38,6 @@ #define CONFIG_QDSP6 1 #endif -void (*msm_hw_reset_hook)(void); - #define MODULE_NAME "msm_smd" enum { @@ -52,13 +49,14 @@ static int msm_smd_debug_mask; struct shared_info { int ready; - unsigned state; + void __iomem *state; }; static unsigned dummy_state[SMSM_STATE_COUNT]; static struct shared_info smd_info = { - .state = (unsigned) &dummy_state, + /* FIXME: not a real __iomem pointer */ + .state = &dummy_state, }; module_param_named(debug_mask, msm_smd_debug_mask, @@ -101,10 +99,6 @@ static void handle_modem_crash(void) pr_err("ARM9 has CRASHED\n"); smd_diag(); - /* hard reboot if possible */ - if (msm_hw_reset_hook) - msm_hw_reset_hook(); - /* in this case the modem or watchdog should reboot us */ for (;;) ; @@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size) return smem_find(id, size); } -void *smem_item(unsigned id, unsigned *size) +void __iomem *smem_item(unsigned id, unsigned *size) { struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; struct smem_heap_entry *toc = shared->heap_toc; if (id >= SMEM_NUM_ITEMS) - return 0; + return NULL; if (toc[id].allocated) { *size = toc[id].size; - return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset); + return (MSM_SHARED_RAM_BASE + toc[id].offset); } else { *size = 0; } - return 0; + return NULL; } void *smem_find(unsigned id, unsigned size_in) @@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data) int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask) { - unsigned long addr = smd_info.state + item * 4; + void __iomem *addr = smd_info.state + item * 4; unsigned long flags; unsigned state; @@ -943,10 +937,10 @@ int smd_core_init(void) /* wait for essential items to be initialized */ for (;;) { unsigned size; - void *state; + void __iomem *state; state = smem_item(SMEM_SMSM_SHARED_STATE, &size); if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) { - smd_info.state = (unsigned)state; + smd_info.state = state; break; } } diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 812808254936..476549a8a709 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -1,7 +1,7 @@ /* * * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -20,15 +20,16 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <asm/mach/time.h> #include <asm/hardware/gic.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> -#include <mach/msm_iomap.h> -#include <mach/cpu.h> -#include <mach/board.h> +#include "common.h" #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0004 @@ -36,7 +37,6 @@ #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) #define TIMER_ENABLE_EN BIT(0) #define TIMER_CLEAR 0x000C -#define DGT_CLK_CTL 0x0034 #define DGT_CLK_CTL_DIV_4 0x3 #define GPT_HZ 32768 @@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = { static union { struct clock_event_device *evt; - struct clock_event_device __percpu **percpu_evt; + struct clock_event_device * __percpu *percpu_evt; } msm_evt; static void __iomem *source_base; @@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) *__this_cpu_ptr(msm_evt.percpu_evt) = evt; clockevents_register_device(evt); - enable_percpu_irq(evt->irq, 0); + enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } @@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void) return msm_clocksource.read(&msm_clocksource); } -static void __init msm_timer_init(void) +static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, + bool percpu) { struct clock_event_device *ce = &msm_clockevent; struct clocksource *cs = &msm_clocksource; int res; - u32 dgt_hz; - - if (cpu_is_msm7x01()) { - event_base = MSM_CSR_BASE; - source_base = MSM_CSR_BASE + 0x10; - dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */ - cs->read = msm_read_timer_count_shift; - cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); - } else if (cpu_is_msm7x30()) { - event_base = MSM_CSR_BASE + 0x04; - source_base = MSM_CSR_BASE + 0x24; - dgt_hz = 24576000 / 4; - } else if (cpu_is_qsd8x50()) { - event_base = MSM_CSR_BASE; - source_base = MSM_CSR_BASE + 0x10; - dgt_hz = 19200000 / 4; - } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { - event_base = MSM_TMR_BASE + 0x04; - /* Use CPU0's timer as the global clock source. */ - source_base = MSM_TMR0_BASE + 0x24; - dgt_hz = 27000000 / 4; - writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); - } else - BUG(); writel_relaxed(0, event_base + TIMER_ENABLE); writel_relaxed(0, event_base + TIMER_CLEAR); writel_relaxed(~0, event_base + TIMER_MATCH_VAL); ce->cpumask = cpumask_of(0); + ce->irq = irq; - ce->irq = INT_GP_TIMER_EXP; clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); - if (cpu_is_msm8x60() || cpu_is_msm8960()) { + if (percpu) { msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); if (!msm_evt.percpu_evt) { pr_err("memory allocation failed for %s\n", ce->name); @@ -219,7 +196,7 @@ static void __init msm_timer_init(void) res = request_percpu_irq(ce->irq, msm_timer_interrupt, ce->name, msm_evt.percpu_evt); if (!res) { - enable_percpu_irq(ce->irq, 0); + enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_LOCAL_TIMERS local_timer_register(&msm_local_timer_ops); #endif @@ -238,10 +215,143 @@ err: res = clocksource_register_hz(cs, dgt_hz); if (res) pr_err("clocksource_register failed\n"); - setup_sched_clock(msm_sched_clock_read, - cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz); + setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); } -struct sys_timer msm_timer = { - .init = msm_timer_init +#ifdef CONFIG_OF +static const struct of_device_id msm_dgt_match[] __initconst = { + { .compatible = "qcom,msm-dgt" }, + { }, +}; + +static const struct of_device_id msm_gpt_match[] __initconst = { + { .compatible = "qcom,msm-gpt" }, + { }, +}; + +static void __init msm_dt_timer_init(void) +{ + struct device_node *np; + u32 freq; + int irq; + struct resource res; + u32 percpu_offset; + void __iomem *dgt_clk_ctl; + + np = of_find_matching_node(NULL, msm_gpt_match); + if (!np) { + pr_err("Can't find GPT DT node\n"); + return; + } + + event_base = of_iomap(np, 0); + if (!event_base) { + pr_err("Failed to map event base\n"); + return; + } + + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) { + pr_err("Can't get irq\n"); + return; + } + of_node_put(np); + + np = of_find_matching_node(NULL, msm_dgt_match); + if (!np) { + pr_err("Can't find DGT DT node\n"); + return; + } + + if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) + percpu_offset = 0; + + if (of_address_to_resource(np, 0, &res)) { + pr_err("Failed to parse DGT resource\n"); + return; + } + + source_base = ioremap(res.start + percpu_offset, resource_size(&res)); + if (!source_base) { + pr_err("Failed to map source base\n"); + return; + } + + if (!of_address_to_resource(np, 1, &res)) { + dgt_clk_ctl = ioremap(res.start + percpu_offset, + resource_size(&res)); + if (!dgt_clk_ctl) { + pr_err("Failed to map DGT control base\n"); + return; + } + writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl); + iounmap(dgt_clk_ctl); + } + + if (of_property_read_u32(np, "clock-frequency", &freq)) { + pr_err("Unknown frequency\n"); + return; + } + of_node_put(np); + + msm_timer_init(freq, 32, irq, !!percpu_offset); +} + +struct sys_timer msm_dt_timer = { + .init = msm_dt_timer_init +}; +#endif + +static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) +{ + event_base = ioremap(event, SZ_64); + if (!event_base) { + pr_err("Failed to map event base\n"); + return 1; + } + source_base = ioremap(source, SZ_64); + if (!source_base) { + pr_err("Failed to map source base\n"); + return 1; + } + return 0; +} + +static void __init msm7x01_timer_init(void) +{ + struct clocksource *cs = &msm_clocksource; + + if (msm_timer_map(0xc0100000, 0xc0100010)) + return; + cs->read = msm_read_timer_count_shift; + cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); + /* 600 KHz */ + msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7, + false); +} + +struct sys_timer msm7x01_timer = { + .init = msm7x01_timer_init +}; + +static void __init msm7x30_timer_init(void) +{ + if (msm_timer_map(0xc0100004, 0xc0100024)) + return; + msm_timer_init(24576000 / 4, 32, 1, false); +} + +struct sys_timer msm7x30_timer = { + .init = msm7x30_timer_init +}; + +static void __init qsd8x50_timer_init(void) +{ + if (msm_timer_map(0xAC100000, 0xAC100010)) + return; + msm_timer_init(19200000 / 4, 32, 7, false); +} + +struct sys_timer qsd8x50_timer = { + .init = qsd8x50_timer_init }; diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d21..137e479d15a0 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <linux/io.h> #include <plat/addr-map.h> +#include <mach/mv78xx0.h> #include "common.h" /* @@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); + TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 3057f7d4329a..6b0c38735527 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -135,11 +135,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, - }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00d8fc1..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..bd03fed1128e 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,11 +46,10 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE 0xfd000000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d68..26a059b4f472 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -15,6 +15,7 @@ #include <asm/mach/pci.h> #include <plat/pcie.h> #include <plat/addr-map.h> +#include <mach/mv78xx0.h> #include "common.h" struct pcie_port { @@ -23,16 +24,13 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; - char io_space_name[16]; char mem_space_name[16]; - struct resource res[2]; + struct resource res; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; -static struct resource pcie_mem_space; - void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); } +u32 pcie_port_size[8] = { + 0, + 0x30000000, + 0x10000000, + 0x10000000, + 0x08000000, + 0x08000000, + 0x08000000, + 0x04000000, +}; + static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win; + int win = 0; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; + pcie_io_space.flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); + if (num_pcie_ports > 7) + panic("invalid number of PCIe ports"); + + size_each = pcie_port_size[num_pcie_ports]; + start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d.%d I/O", pp->maj, pp->min); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - pp->res[1].flags = IORESOURCE_MEM; - } - - switch (num_pcie_ports) { - case 0: - size_each = 0; - break; - - case 1: - size_each = 0x30000000; - break; - - case 2 ... 3: - size_each = 0x10000000; - break; - - case 4 ... 6: - size_each = 0x08000000; - break; - - case 7: - size_each = 0x04000000; - break; - - default: - panic("invalid number of PCIe ports"); - } - - start = MV78XX0_PCIE_MEM_PHYS_BASE; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - pp->res[1].start = start; - pp->res[1].end = start + size_each - 1; + pp->res.name = pp->mem_space_name; + pp->res.flags = IORESOURCE_MEM; + pp->res.start = start; + pp->res.end = start + size_each - 1; start += size_each; - } - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - if (request_resource(&pcie_io_space, &pp->res[0])) - panic("can't allocate PCIe I/O sub-space"); - - if (request_resource(&pcie_mem_space, &pp->res[1])) + if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - } - win = 0; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; + mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, + resource_size(&pp->res), + pp->maj, pp->min); - mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, - resource_size(&pp->res[0]), + mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, pp->maj, pp->min); - - mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, - resource_size(&pp->res[1]), - pp->maj, pp->min); } } @@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); + + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); return 1; } @@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); + memset(&pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 9a8bbda195b2..ecc431909d6f 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -1,7 +1,5 @@ if ARCH_MXS -source "arch/arm/mach-mxs/devices/Kconfig" - config SOC_IMX23 bool select ARM_AMBA @@ -27,91 +25,4 @@ config MACH_MXS_DT Include support for Freescale MXS platforms(i.MX23 and i.MX28) using the device tree for discovery -config MACH_STMP378X_DEVB - bool "Support STMP378x_devb Platform" - select SOC_IMX23 - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for STMP378x-devb platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX23EVK - bool "Support MX23EVK Platform" - select SOC_IMX23 - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for MX23EVK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX28EVK - bool "Support MX28EVK Platform" - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_FLEXCAN - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - select MXS_HAVE_PLATFORM_MXS_SAIF - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - help - Include support for MX28EVK platform. This includes specific - configurations for the board and its peripherals. - -config MODULE_TX28 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXS_PWM - select MXS_HAVE_PLATFORM_RTC_STMP3XXX - -config MODULE_M28 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_FLEXCAN - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXSFB - -config MODULE_APX4 - bool - select SOC_IMX28 - select LEDS_GPIO_REGISTER - select MXS_HAVE_AMBA_DUART - select MXS_HAVE_PLATFORM_AUART - select MXS_HAVE_PLATFORM_FEC - select MXS_HAVE_PLATFORM_MXS_I2C - select MXS_HAVE_PLATFORM_MXS_MMC - select MXS_HAVE_PLATFORM_MXS_SAIF - -config MACH_TX28 - bool "Ka-Ro TX28 module" - select MODULE_TX28 - -config MACH_M28EVK - bool "Support DENX M28EVK Platform" - select MODULE_M28 - -config MACH_APX4DEVKIT - bool "Support Bluegiga APX4 Development Kit" - select MODULE_APX4 - endif diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index fed3695a1339..3d3c8a973062 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -1,15 +1,6 @@ # Common support -obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o +obj-y := icoll.o ocotp.o system.o timer.o mm.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o -obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o -obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o -obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o -obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o -obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o -obj-$(CONFIG_MODULE_TX28) += module-tx28.o -obj-$(CONFIG_MACH_TX28) += mach-tx28.o - -obj-y += devices/ diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 4582999cf080..8bd23a8558db 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot @@ -5,6 +5,7 @@ dtb-y += imx23-evk.dtb \ imx23-stmp378x_devb.dtb \ imx28-apx4devkit.dtb \ imx28-cfa10036.dtb \ + imx28-cfa10049.dtb \ imx28-evk.dtb \ imx28-m28evk.dtb \ imx28-tx28.dtb \ diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h deleted file mode 100644 index 9ee5cede3d42..000000000000 --- a/arch/arm/mach-mxs/devices-mx23.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx23.h> -#include <mach/devices-common.h> -#include <linux/mxsfb.h> -#include <linux/amba/bus.h> - -static inline int mx23_add_duart(void) -{ - struct amba_device *d; - - d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K, - MX23_INT_DUART, 0, 0, 0); - return IS_ERR(d) ? PTR_ERR(d) : 0; -} - -extern const struct mxs_auart_data mx23_auart_data[] __initconst; -#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id]) -#define mx23_add_auart0() mx23_add_auart(0) -#define mx23_add_auart1() mx23_add_auart(1) - -extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst; -#define mx23_add_gpmi_nand(pdata) \ - mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data) - -extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; -#define mx23_add_mxs_mmc(id, pdata) \ - mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) - -#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) - -struct platform_device *__init mx23_add_mxsfb( - const struct mxsfb_platform_data *pdata); - -struct platform_device *__init mx23_add_rtc_stmp3xxx(void); diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h deleted file mode 100644 index fcab431060f4..000000000000 --- a/arch/arm/mach-mxs/devices-mx28.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <mach/mx28.h> -#include <mach/devices-common.h> -#include <linux/mxsfb.h> -#include <linux/amba/bus.h> - -static inline int mx28_add_duart(void) -{ - struct amba_device *d; - - d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K, - MX28_INT_DUART, 0, 0, 0); - return IS_ERR(d) ? PTR_ERR(d) : 0; -} - -extern const struct mxs_auart_data mx28_auart_data[] __initconst; -#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id]) -#define mx28_add_auart0() mx28_add_auart(0) -#define mx28_add_auart1() mx28_add_auart(1) -#define mx28_add_auart2() mx28_add_auart(2) -#define mx28_add_auart3() mx28_add_auart(3) -#define mx28_add_auart4() mx28_add_auart(4) - -extern const struct mxs_fec_data mx28_fec_data[] __initconst; -#define mx28_add_fec(id, pdata) \ - mxs_add_fec(&mx28_fec_data[id], pdata) - -extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; -#define mx28_add_flexcan(id, pdata) \ - mxs_add_flexcan(&mx28_flexcan_data[id], pdata) -#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) -#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) - -extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst; -#define mx28_add_gpmi_nand(pdata) \ - mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data) - -extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst; -#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) - -extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; -#define mx28_add_mxs_mmc(id, pdata) \ - mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) - -#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) - -struct platform_device *__init mx28_add_mxsfb( - const struct mxsfb_platform_data *pdata); - -extern const struct mxs_saif_data mx28_saif_data[] __initconst; -#define mx28_add_saif(id, pdata) \ - mxs_add_saif(&mx28_saif_data[id], pdata) - -struct platform_device *__init mx28_add_rtc_stmp3xxx(void); diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c deleted file mode 100644 index cf50b5a66dda..000000000000 --- a/arch/arm/mach-mxs/devices.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> - -struct platform_device *__init mxs_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask) -{ - int ret = -ENOMEM; - struct platform_device *pdev; - - pdev = platform_device_alloc(name, id); - if (!pdev) - goto err; - - if (dmamask) { - /* - * This memory isn't freed when the device is put, - * I don't have a nice idea for that though. Conceptually - * dma_mask in struct device should not be a pointer. - * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 - */ - pdev->dev.dma_mask = - kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); - if (!pdev->dev.dma_mask) - /* ret is still -ENOMEM; */ - goto err; - - *pdev->dev.dma_mask = dmamask; - pdev->dev.coherent_dma_mask = dmamask; - } - - if (res) { - ret = platform_device_add_resources(pdev, res, num_resources); - if (ret) - goto err; - } - - if (data) { - ret = platform_device_add_data(pdev, data, size_data); - if (ret) - goto err; - } - - ret = platform_device_add(pdev); - if (ret) { -err: - if (dmamask) - kfree(pdev->dev.dma_mask); - platform_device_put(pdev); - return ERR_PTR(ret); - } - - return pdev; -} - -struct device mxs_apbh_bus = { - .init_name = "mxs_apbh", - .parent = &platform_bus, -}; - -static int __init mxs_device_init(void) -{ - return device_register(&mxs_apbh_bus); -} -core_initcall(mxs_device_init); diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig deleted file mode 100644 index 19659de1c4e8..000000000000 --- a/arch/arm/mach-mxs/devices/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -config MXS_HAVE_AMBA_DUART - bool - -config MXS_HAVE_PLATFORM_AUART - bool - -config MXS_HAVE_PLATFORM_FEC - bool - -config MXS_HAVE_PLATFORM_FLEXCAN - select HAVE_CAN_FLEXCAN if CAN - bool - -config MXS_HAVE_PLATFORM_GPMI_NAND - bool - -config MXS_HAVE_PLATFORM_MXS_I2C - bool - -config MXS_HAVE_PLATFORM_MXS_MMC - bool - -config MXS_HAVE_PLATFORM_MXS_PWM - bool - -config MXS_HAVE_PLATFORM_MXSFB - bool - -config MXS_HAVE_PLATFORM_MXS_SAIF - bool - -config MXS_HAVE_PLATFORM_RTC_STMP3XXX - bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile deleted file mode 100644 index 5f72d9787444..000000000000 --- a/arch/arm/mach-mxs/devices/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o -obj-y += platform-dma.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o -obj-y += platform-gpio-mxs.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o -obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c deleted file mode 100644 index 27608f5d2ac8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-auart.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> -#include <asm/sizes.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_auart_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_AUART ## hwid, \ - } - -#define mxs_auart_data_entry(soc, _id, hwid) \ - [_id] = mxs_auart_data_entry_single(soc, _id, hwid) - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_auart_data mx23_auart_data[] __initconst = { -#define mx23_auart_data_entry(_id, hwid) \ - mxs_auart_data_entry(MX23, _id, hwid) - mx23_auart_data_entry(0, 1), - mx23_auart_data_entry(1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_auart_data mx28_auart_data[] __initconst = { -#define mx28_auart_data_entry(_id) \ - mxs_auart_data_entry(MX28, _id, _id) - mx28_auart_data_entry(0), - mx28_auart_data_entry(1), - mx28_auart_data_entry(2), - mx28_auart_data_entry(3), - mx28_auart_data_entry(4), -}; -#endif - -struct platform_device *__init mxs_add_auart( - const struct mxs_auart_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device_dmamask("mxs-auart", data->id, - res, ARRAY_SIZE(res), NULL, 0, - DMA_BIT_MASK(32)); -} - diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c deleted file mode 100644 index 46824501de00..000000000000 --- a/arch/arm/mach-mxs/devices/platform-dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/compiler.h> -#include <linux/dma-mapping.h> -#include <linux/err.h> -#include <linux/init.h> - -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -struct platform_device *__init mxs_add_dma(const char *devid, - resource_size_t base) -{ - struct resource res[] = { - { - .start = base, - .end = base + SZ_8K - 1, - .flags = IORESOURCE_MEM, - } - }; - - return mxs_add_platform_device_dmamask(devid, -1, - res, ARRAY_SIZE(res), NULL, 0, - DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c deleted file mode 100644 index ae96a4fd8f14..000000000000 --- a/arch/arm/mach-mxs/devices/platform-fec.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> -#include <asm/sizes.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_fec_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ - .irq = soc ## _INT_ENET_MAC ## _id, \ - } - -#define mxs_fec_data_entry(soc, _id) \ - [_id] = mxs_fec_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_fec_data mx28_fec_data[] __initconst = { -#define mx28_fec_data_entry(_id) \ - mxs_fec_data_entry(MX28, _id) - mx28_fec_data_entry(0), - mx28_fec_data_entry(1), -}; -#endif - -struct platform_device *__init mxs_add_fec( - const struct mxs_fec_data *data, - const struct fec_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device_dmamask("imx28-fec", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), - DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c deleted file mode 100644 index 43a6b4bae6fe..000000000000 --- a/arch/arm/mach-mxs/devices/platform-flexcan.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2010, 2011 Pengutronix, - * Marc Kleine-Budde <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_CAN ## _hwid, \ - } - -#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \ - [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = { -#define mx28_flexcan_data_entry(_id, _hwid) \ - mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K) - mx28_flexcan_data_entry(0, 0), - mx28_flexcan_data_entry(1, 1), -}; -#endif /* ifdef CONFIG_SOC_IMX28 */ - -struct platform_device *__init mxs_add_flexcan( - const struct mxs_flexcan_data *data, - const struct flexcan_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("flexcan", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c deleted file mode 100644 index cd99f19ec637..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/compiler.h> -#include <linux/err.h> -#include <linux/init.h> - -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -struct platform_device *__init mxs_add_gpio( - char *name, int id, resource_size_t iobase, int irq) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxs_apbh_bus, - name, id, res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c deleted file mode 100644 index 3e22df5944a8..000000000000 --- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -#include <asm/sizes.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> -#include <linux/dma-mapping.h> - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = { - .devid = "imx23-gpmi-nand", - .res = { - /* GPMI */ - DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K, - GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION, - GPMI_NAND_GPMI_INTERRUPT_RES_NAME), - /* BCH */ - DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K, - GPMI_NAND_BCH_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX23_INT_BCH, - GPMI_NAND_BCH_INTERRUPT_RES_NAME), - /* DMA */ - DEFINE_RES_NAMED(MX23_DMA_GPMI0, - MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1, - GPMI_NAND_DMA_CHANNELS_RES_NAME, - IORESOURCE_DMA), - DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA, - GPMI_NAND_DMA_INTERRUPT_RES_NAME), - }, -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = { - .devid = "imx28-gpmi-nand", - .res = { - /* GPMI */ - DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K, - GPMI_NAND_GPMI_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI, - GPMI_NAND_GPMI_INTERRUPT_RES_NAME), - /* BCH */ - DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K, - GPMI_NAND_BCH_REGS_ADDR_RES_NAME), - DEFINE_RES_IRQ_NAMED(MX28_INT_BCH, - GPMI_NAND_BCH_INTERRUPT_RES_NAME), - /* DMA */ - DEFINE_RES_NAMED(MX28_DMA_GPMI0, - MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1, - GPMI_NAND_DMA_CHANNELS_RES_NAME, - IORESOURCE_DMA), - DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA, - GPMI_NAND_DMA_INTERRUPT_RES_NAME), - }, -}; -#endif - -struct platform_device *__init -mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, - const struct mxs_gpmi_nand_data *data) -{ - return mxs_add_platform_device_dmamask(data->devid, -1, - data->res, GPMI_NAND_RES_SIZE, - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c deleted file mode 100644 index 79222ec8ede1..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix - * Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_i2c_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \ - .errirq = soc ## _INT_I2C ## _id ## _ERROR, \ - .dmairq = soc ## _INT_I2C ## _id ## _DMA, \ - } - -#define mxs_i2c_data_entry(soc, _id) \ - [_id] = mxs_i2c_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { - mxs_i2c_data_entry(MX28, 0), - mxs_i2c_data_entry(MX28, 1), -}; -#endif - -struct platform_device *__init mxs_add_mxs_i2c( - const struct mxs_mxs_i2c_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->errirq, - .end = data->errirq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dmairq, - .end = data->dmairq, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("mxs-i2c", data->id, res, - ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c deleted file mode 100644 index b33c9d05c552..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/compiler.h> -#include <linux/err.h> -#include <linux/init.h> - -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ - .dma = soc ## _DMA_SSP ## hwid, \ - .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ - .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ - } - -#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid) \ - [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) - - -#ifdef CONFIG_SOC_IMX23 -const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { - mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1), - mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2), - mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3), -}; -#endif - -struct platform_device *__init mxs_add_mxs_mmc( - const struct mxs_mxs_mmc_data *data, - const struct mxs_mmc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->dma, - .end = data->dma, - .flags = IORESOURCE_DMA, - }, { - .start = data->irq_err, - .end = data->irq_err, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq_dma, - .end = data->irq_dma, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c deleted file mode 100644 index 680f5a902936..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> -#include <mach/devices-common.h> - -struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id) -{ - struct resource res = { - .flags = IORESOURCE_MEM, - }; - - res.start = iobase + 0x10 + 0x20 * id; - res.end = res.start + 0x1f; - - return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0); -} diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c deleted file mode 100644 index f6e3a60b4201..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/compiler.h> -#include <linux/err.h> -#include <linux/init.h> - -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#define mxs_saif_data_entry_single(soc, _id) \ - { \ - .id = _id, \ - .iobase = soc ## _SAIF ## _id ## _BASE_ADDR, \ - .irq = soc ## _INT_SAIF ## _id, \ - .dma = soc ## _DMA_SAIF ## _id, \ - .dmairq = soc ## _INT_SAIF ## _id ##_DMA, \ - } - -#define mxs_saif_data_entry(soc, _id) \ - [_id] = mxs_saif_data_entry_single(soc, _id) - -#ifdef CONFIG_SOC_IMX28 -const struct mxs_saif_data mx28_saif_data[] __initconst = { - mxs_saif_data_entry(MX28, 0), - mxs_saif_data_entry(MX28, 1), -}; -#endif - -struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data, - const struct mxs_saif_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dma, - .end = data->dma, - .flags = IORESOURCE_DMA, - }, { - .start = data->dmairq, - .end = data->dmairq, - .flags = IORESOURCE_IRQ, - }, - - }; - - return mxs_add_platform_device("mxs-saif", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c deleted file mode 100644 index 76b53f73418e..000000000000 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> -#include <asm/sizes.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> -#include <linux/mxsfb.h> - -#ifdef CONFIG_SOC_IMX23 -struct platform_device *__init mx23_add_mxsfb( - const struct mxsfb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX23_LCDIF_BASE_ADDR, - .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return mxs_add_platform_device_dmamask("imx23-fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} -#endif /* ifdef CONFIG_SOC_IMX23 */ - -#ifdef CONFIG_SOC_IMX28 -struct platform_device *__init mx28_add_mxsfb( - const struct mxsfb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = MX28_LCDIF_BASE_ADDR, - .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return mxs_add_platform_device_dmamask("imx28-fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} -#endif /* ifdef CONFIG_SOC_IMX28 */ diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c deleted file mode 100644 index 639eaee15553..000000000000 --- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> -#include <mach/mx23.h> -#include <mach/mx28.h> -#include <mach/devices-common.h> - -#ifdef CONFIG_SOC_IMX23 -struct platform_device *__init mx23_add_rtc_stmp3xxx(void) -{ - struct resource res[] = { - { - .start = MX23_RTC_BASE_ADDR, - .end = MX23_RTC_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX23_INT_RTC_ALARM, - .end = MX23_INT_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), - NULL, 0); -} -#endif /* CONFIG_SOC_IMX23 */ - -#ifdef CONFIG_SOC_IMX28 -struct platform_device *__init mx28_add_rtc_stmp3xxx(void) -{ - struct resource res[] = { - { - .start = MX28_RTC_BASE_ADDR, - .end = MX28_RTC_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX28_INT_RTC_ALARM, - .end = MX28_INT_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, - }; - - return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), - NULL, 0); -} -#endif /* CONFIG_SOC_IMX28 */ diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 23ca9d083b2c..8fb23af154b3 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c @@ -19,20 +19,27 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/irq.h> +#include <linux/irqdomain.h> #include <linux/io.h> - +#include <linux/of.h> +#include <linux/of_irq.h> +#include <asm/exception.h> #include <mach/mxs.h> #include <mach/common.h> #define HW_ICOLL_VECTOR 0x0000 #define HW_ICOLL_LEVELACK 0x0010 #define HW_ICOLL_CTRL 0x0020 +#define HW_ICOLL_STAT_OFFSET 0x0070 #define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) #define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define ICOLL_NUM_IRQS 128 + static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); +static struct irq_domain *icoll_domain; static void icoll_ack_irq(struct irq_data *d) { @@ -48,13 +55,13 @@ static void icoll_ack_irq(struct irq_data *d) static void icoll_mask_irq(struct irq_data *d) { __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->irq)); + icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); } static void icoll_unmask_irq(struct irq_data *d) { __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_SET(d->irq)); + icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); } static struct irq_chip mxs_icoll_chip = { @@ -63,18 +70,56 @@ static struct irq_chip mxs_icoll_chip = { .irq_unmask = icoll_unmask_irq, }; -void __init icoll_init_irq(void) +asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) { - int i; + u32 irqnr; + + do { + irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET); + if (irqnr != 0x7f) { + __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); + irqnr = irq_find_mapping(icoll_domain, irqnr); + handle_IRQ(irqnr, regs); + continue; + } + break; + } while (1); +} + +static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + + return 0; +} +static struct irq_domain_ops icoll_irq_domain_ops = { + .map = icoll_irq_domain_map, + .xlate = irq_domain_xlate_onecell, +}; + +void __init icoll_of_init(struct device_node *np, + struct device_node *interrupt_parent) +{ /* * Interrupt Collector reset, which initializes the priority * for each irq to level 0. */ mxs_reset_block(icoll_base + HW_ICOLL_CTRL); - for (i = 0; i < MXS_INTERNAL_IRQS; i++) { - irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } + icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, + &icoll_irq_domain_ops, NULL); + WARN_ON(!icoll_domain); +} + +static const struct of_device_id icoll_of_match[] __initconst = { + {.compatible = "fsl,icoll", .data = icoll_of_init}, + { /* sentinel */ } +}; + +void __init icoll_init_irq(void) +{ + of_irq_init(icoll_of_match); } diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h index de6c7ba42544..be5a9c93cb2a 100644 --- a/arch/arm/mach-mxs/include/mach/common.h +++ b/arch/arm/mach-mxs/include/mach/common.h @@ -13,25 +13,17 @@ extern const u32 *mxs_get_ocotp(void); extern int mxs_reset_block(void __iomem *); -extern void mxs_timer_init(int); +extern void mxs_timer_init(void); extern void mxs_restart(char, const char *); extern int mxs_saif_clkmux_select(unsigned int clkmux); -extern void mx23_soc_init(void); extern int mx23_clocks_init(void); extern void mx23_map_io(void); -extern void mx23_init_irq(void); -extern void mx28_soc_init(void); extern int mx28_clocks_init(void); extern void mx28_map_io(void); -extern void mx28_init_irq(void); extern void icoll_init_irq(void); - -extern struct platform_device *mxs_add_dma(const char *devid, - resource_size_t base); -extern struct platform_device *mxs_add_gpio(char *name, int id, - resource_size_t iobase, int irq); +extern void icoll_handle_irq(struct pt_regs *); #endif /* __MACH_MXS_COMMON_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h deleted file mode 100644 index e8b1d958240b..000000000000 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/amba/bus.h> - -extern struct device mxs_apbh_bus; - -struct platform_device *mxs_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask); - -static inline struct platform_device *mxs_add_platform_device( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) -{ - return mxs_add_platform_device_dmamask( - name, id, res, num_resources, data, size_data, 0); -} - -/* auart */ -struct mxs_auart_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_auart( - const struct mxs_auart_data *data); - -/* fec */ -#include <linux/fec.h> -struct mxs_fec_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_fec( - const struct mxs_fec_data *data, - const struct fec_platform_data *pdata); - -/* flexcan */ -#include <linux/can/platform/flexcan.h> -struct mxs_flexcan_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init mxs_add_flexcan( - const struct mxs_flexcan_data *data, - const struct flexcan_platform_data *pdata); - -/* gpmi-nand */ -#include <linux/mtd/gpmi-nand.h> -struct mxs_gpmi_nand_data { - const char *devid; - const struct resource res[GPMI_NAND_RES_SIZE]; -}; -struct platform_device *__init -mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata, - const struct mxs_gpmi_nand_data *data); - -/* i2c */ -struct mxs_mxs_i2c_data { - int id; - resource_size_t iobase; - resource_size_t errirq; - resource_size_t dmairq; -}; -struct platform_device * __init mxs_add_mxs_i2c( - const struct mxs_mxs_i2c_data *data); - -/* mmc */ -#include <linux/mmc/mxs-mmc.h> -struct mxs_mxs_mmc_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t dma; - resource_size_t irq_err; - resource_size_t irq_dma; -}; -struct platform_device *__init mxs_add_mxs_mmc( - const struct mxs_mxs_mmc_data *data, - const struct mxs_mmc_platform_data *pdata); - -/* pwm */ -struct platform_device *__init mxs_add_mxs_pwm( - resource_size_t iobase, int id); - -/* saif */ -#include <sound/saif.h> -struct mxs_saif_data { - int id; - resource_size_t iobase; - resource_size_t irq; - resource_size_t dma; - resource_size_t dmairq; -}; - -struct platform_device *__init mxs_add_saif( - const struct mxs_saif_data *data, - const struct mxs_saif_platform_data *pdata); diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S deleted file mode 100644 index 0c14259705b9..000000000000 --- a/arch/arm/mach-mxs/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale MXS-based - * - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <mach/mxs.h> - -#define MXS_ICOLL_VBASE MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR) -#define HW_ICOLL_STAT_OFFSET 0x70 - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, [\base, #HW_ICOLL_STAT_OFFSET] - cmp \irqnr, #0x7F - strne \irqnr, [\base] - moveqs \irqnr, #0 - .endm - - .macro get_irqnr_preamble, base, tmp - ldr \base, =MXS_ICOLL_VBASE - .endm diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h deleted file mode 100644 index b0190a4822f2..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include <mach/iomux.h> - -/* - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h deleted file mode 100644 index f50fefd10520..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include <mach/iomux.h> - -/* - * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h deleted file mode 100644 index 7abdf58b8bb7..000000000000 --- a/arch/arm/mach-mxs/include/mach/iomux.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#define PAD_3V3 1 - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h deleted file mode 100644 index f771039b814a..000000000000 --- a/arch/arm/mach-mxs/include/mach/irqs.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_MXS_IRQS_H__ -#define __MACH_MXS_IRQS_H__ - -#define MXS_INTERNAL_IRQS 128 - -#define MXS_GPIO_IRQ_START MXS_INTERNAL_IRQS - -/* the maximum for MXS-based */ -#define MXS_GPIO_IRQS (32 * 5) - -/* - * The next 16 interrupts are for board specific purposes. Since - * the kernel can only run on one machine at a time, we can re-use - * these. If you need more, increase MXS_BOARD_IRQS, but keep it - * within sensible limits. - */ -#define MXS_BOARD_IRQ_START (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS) -#define MXS_BOARD_IRQS 16 - -#define NR_IRQS (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS) - -#endif /* __MACH_MXS_IRQS_H__ */ diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c deleted file mode 100644 index 0e804e2f11f4..000000000000 --- a/arch/arm/mach-mxs/iomux.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <asm/mach/map.h> - -#include <mach/mxs.h> -#include <mach/iomux.h> - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad) -{ - u32 reg, ofs, bp, bm; - void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); - - /* muxsel */ - ofs = 0x100; - ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; - bp = PAD_PIN(pad) % 16 * 2; - bm = 0x3 << bp; - reg = __raw_readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MUXSEL(pad) << bp; - __raw_writel(reg, iomux_base + ofs); - - /* drive */ - ofs = cpu_is_mx23() ? 0x200 : 0x300; - ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; - /* mA */ - if (PAD_MA_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4; - bm = 0x3 << bp; - reg = __raw_readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MA(pad) << bp; - __raw_writel(reg, iomux_base + ofs); - } - /* vol */ - if (PAD_VOL_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4 + 2; - if (PAD_VOL(pad)) - __mxs_setl(1 << bp, iomux_base + ofs); - else - __mxs_clrl(1 << bp, iomux_base + ofs); - } - - /* pull */ - if (PAD_PULL_VALID(pad)) { - ofs = cpu_is_mx23() ? 0x400 : 0x600; - ofs += PAD_BANK(pad) * 0x10; - bp = PAD_PIN(pad); - if (PAD_PULL(pad)) - __mxs_setl(1 << bp, iomux_base + ofs); - else - __mxs_clrl(1 << bp, iomux_base + ofs); - } - - return 0; -} - -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) -{ - const iomux_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxs_iomux_setup_pad(*p); - if (ret) - return ret; - p++; - } - - return 0; -} diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c deleted file mode 100644 index f5f061757deb..000000000000 --- a/arch/arm/mach-mxs/mach-apx4devkit.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (C) 2011-2012 - * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com> - * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com> - * - * based on: mach-mx28evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/clk.h> -#include <linux/i2c.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/micrel_phy.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/digctl.h> -#include <mach/iomux-mx28.h> - -#include "devices-mx28.h" - -#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28) - -static const iomux_cfg_t apx4devkit_pads[] __initconst = { - /* duart */ - MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, - - /* auart1 */ - MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, - MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, - - /* auart2 */ - MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL, - MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL, - - /* auart3 */ - MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - - /* i2c */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, - - /* saif0 & saif1 */ - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), -}; - -/* led */ -static const struct gpio_led apx4devkit_leds[] __initconst = { - { - .name = "user-led", - .default_trigger = "heartbeat", - .gpio = APX4DEVKIT_GPIO_USERLED, - }, -}; - -static const struct gpio_led_platform_data apx4devkit_led_data __initconst = { - .leds = apx4devkit_leds, - .num_leds = ARRAY_SIZE(apx4devkit_leds), -}; - -static const struct fec_platform_data mx28_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = { - .wp_gpio = -EINVAL, - .flags = SLOTF_4_BIT_CAPABLE, -}; - -static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = { - { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */ - { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */ -}; - -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \ - defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("VDDA", "0-000a"), - REGULATOR_SUPPLY("VDDIO", "0-000a"), -}; - -static struct regulator_init_data apx4devkit_vdd_reg_init_data = { - .constraints = { - .name = "3V3", - .always_on = 1, - }, - .consumer_supplies = apx4devkit_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies), -}; - -static struct fixed_voltage_config apx4devkit_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 1, - .init_data = &apx4devkit_vdd_reg_init_data, -}; - -static struct platform_device apx4devkit_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &apx4devkit_vdd_pdata, - }, -}; - -static void __init apx4devkit_add_regulators(void) -{ - platform_device_register(&apx4devkit_voltage_regulator); -} -#else -static void __init apx4devkit_add_regulators(void) {} -#endif - -static const struct mxs_saif_platform_data - apx4devkit_mxs_saif_pdata[] __initconst = { - /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ - { - .master_mode = 1, - .master_id = 0, - }, { - .master_mode = 0, - .master_id = 0, - }, -}; - -static int apx4devkit_phy_fixup(struct phy_device *phy) -{ - phy->dev_flags |= MICREL_PHY_50MHZ_CLK; - return 0; -} - -static void __init apx4devkit_fec_phy_clk_enable(void) -{ - struct clk *clk; - - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); -} - -static void __init apx4devkit_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(apx4devkit_pads, - ARRAY_SIZE(apx4devkit_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart1(); - mx28_add_auart2(); - mx28_add_auart3(); - - /* - * Register fixup for the Micrel KS8031 PHY clock - * (shares same ID with KS8051) - */ - phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, - apx4devkit_phy_fixup); - - apx4devkit_fec_phy_clk_enable(); - mx28_add_fec(0, &mx28_fec_pdata); - - mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata); - - gpio_led_register_device(0, &apx4devkit_led_data); - - mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); - mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]); - mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]); - - apx4devkit_add_regulators(); - - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, apx4devkit_i2c_boardinfo, - ARRAY_SIZE(apx4devkit_i2c_boardinfo)); - - mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0); -} - -static void __init apx4devkit_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer apx4devkit_timer = { - .init = apx4devkit_timer_init, -}; - -MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &apx4devkit_timer, - .init_machine = apx4devkit_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c deleted file mode 100644 index 4c00c879b893..000000000000 --- a/arch/arm/mach-mxs/mach-m28evk.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * based on: mach-mx28_evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/irq.h> -#include <linux/clk.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/iomux-mx28.h> - -#include "devices-mx28.h" - -#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16) -#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17) - -#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) -#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28) - -#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) -#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) - -static const iomux_cfg_t m28evk_pads[] __initconst = { - /* duart */ - MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - - /* auart3 */ - MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, - MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - /* fec1 */ - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, - - /* flexcan0 */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* flexcan1 */ - MX28_PAD_GPMI_CE2N__CAN1_TX, - MX28_PAD_GPMI_CE3N__CAN1_RX, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* mxsfb (lcdif) */ - MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, - MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, - MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, - MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, - MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, - MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, - MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, - MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, - MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, - MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, - MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, - MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, - MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, - MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, - MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, - MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, - - MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, - - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* mmc1 */ - MX28_PAD_GPMI_D00__SSP1_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D01__SSP1_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D02__SSP1_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D03__SSP1_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D04__SSP1_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D05__SSP1_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D06__SSP1_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D07__SSP1_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY1__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_WRN__SSP1_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_GPMI_RESETN__GPIO_0_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM4__GPIO_3_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, - MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL, - - /* nand */ - MX28_PAD_GPMI_D00__GPMI_D0 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D01__GPMI_D1 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D02__GPMI_D2 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D03__GPMI_D3 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D04__GPMI_D4 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D05__GPMI_D5 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D06__GPMI_D6 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_D07__GPMI_D7 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_CE0N__GPMI_CE0N | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_RDY0__GPMI_READY0 | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_ALE__GPMI_ALE | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_CLE__GPMI_CLE | - (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RESETN__GPMI_RESETN | - (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP), - - /* Backlight */ - MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL, -}; - -/* led */ -static const struct gpio_led m28evk_leds[] __initconst = { - { - .name = "user-led1", - .default_trigger = "heartbeat", - .gpio = M28EVK_GPIO_USERLED1, - }, - { - .name = "user-led2", - .default_trigger = "heartbeat", - .gpio = M28EVK_GPIO_USERLED2, - }, -}; - -static const struct gpio_led_platform_data m28evk_led_data __initconst = { - .leds = m28evk_leds, - .num_leds = ARRAY_SIZE(m28evk_leds), -}; - -static struct fec_platform_data mx28_fec_pdata[] __initdata = { - { - /* fec0 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, { - /* fec1 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, -}; - -static int __init m28evk_fec_get_mac(void) -{ - int i; - u32 val; - const u32 *ocotp = mxs_get_ocotp(); - - if (!ocotp) - return -ETIMEDOUT; - - /* - * OCOTP only stores the last 4 octets for each mac address, - * so hard-code DENX OUI (C0:E5:4E) here. - */ - for (i = 0; i < 2; i++) { - val = ocotp[i]; - mx28_fec_pdata[i].mac[0] = 0xC0; - mx28_fec_pdata[i].mac[1] = 0xE5; - mx28_fec_pdata[i].mac[2] = 0x4E; - mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; - mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; - mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; - } - - return 0; -} - -/* mxsfb (lcdif) */ -static struct fb_videomode m28evk_video_modes[] = { - { - .name = "Ampire AM-800480R2TMQW-T01H", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 30066, /* picosecond (33.26 MHz) */ - .left_margin = 0, - .right_margin = 256, - .upper_margin = 0, - .lower_margin = 45, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, - }, -}; - -static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = { - .mode_list = m28evk_video_modes, - .mode_count = ARRAY_SIZE(m28evk_video_modes), - .default_bpp = 16, - .ld_intf_width = STMLCDIF_18BIT, -}; - -static struct at24_platform_data m28evk_eeprom = { - .byte_len = 16384, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = { - { - I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */ - .platform_data = &m28evk_eeprom, - }, -}; - -static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = { - { - /* mmc0 */ - .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, { - /* mmc1 */ - .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, -}; - -static void __init m28evk_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart3(); - - if (!m28evk_fec_get_mac()) { - mx28_add_fec(0, &mx28_fec_pdata[0]); - mx28_add_fec(1, &mx28_fec_pdata[1]); - } - - mx28_add_flexcan(0, NULL); - mx28_add_flexcan(1, NULL); - - mx28_add_mxsfb(&m28evk_mxsfb_pdata); - - mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]); - mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]); - - gpio_led_register_device(0, &m28evk_led_data); - - /* I2C */ - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo, - ARRAY_SIZE(m28_stk5v3_i2c_boardinfo)); -} - -static void __init m28evk_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer m28evk_timer = { - .init = m28evk_timer_init, -}; - -MACHINE_START(M28EVK, "DENX M28 EVK") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &m28evk_timer, - .init_machine = m28evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c deleted file mode 100644 index e7272a41939d..000000000000 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/iomux-mx23.h> - -#include "devices-mx23.h" - -#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) -#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) -#define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) -#define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) - -static const iomux_cfg_t mx23evk_pads[] __initconst = { - /* duart */ - MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart */ - MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL, - MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL, - MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL, - MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL, - - /* mxsfb (lcdif) */ - MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL, - MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL, - MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL, - MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL, - MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL, - MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL, - MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL, - MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL, - MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL, - MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL, - MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL, - MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, - MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, - MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL, - /* LCD panel enable */ - MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, - /* backlight control */ - MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, - - /* mmc */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D08__SSP1_DATA4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D09__SSP1_DATA5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D10__SSP1_DATA6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_GPMI_D11__SSP1_DATA7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_CMD__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DETECT__SSP1_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX23_PAD_PWM4__GPIO_1_30 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX23_PAD_PWM3__GPIO_1_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), -}; - -/* mxsfb (lcdif) */ -static struct fb_videomode mx23evk_video_modes[] = { - { - .name = "Samsung-LMS430HF02", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 108096, /* picosecond (9.2 MHz) */ - .left_margin = 15, - .right_margin = 8, - .upper_margin = 12, - .lower_margin = 4, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | - FB_SYNC_DOTCLK_FAILING_ACT, - }, -}; - -static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { - .mode_list = mx23evk_video_modes, - .mode_count = ARRAY_SIZE(mx23evk_video_modes), - .default_bpp = 32, - .ld_intf_width = STMLCDIF_24BIT, -}; - -static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { - .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, -}; - -static void __init mx23evk_init(void) -{ - int ret; - - mx23_soc_init(); - - mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); - - mx23_add_duart(); - mx23_add_auart0(); - - /* power on mmc slot by writing 0 to the gpio */ - ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, - "mmc0-slot-power"); - if (ret) - pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); - mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); - - ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); - if (ret) - pr_warn("failed to request gpio lcd-enable: %d\n", ret); - else - gpio_set_value(MX23EVK_LCD_ENABLE, 1); - - ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); - if (ret) - pr_warn("failed to request gpio bl-enable: %d\n", ret); - else - gpio_set_value(MX23EVK_BL_ENABLE, 1); - - mx23_add_mxsfb(&mx23evk_mxsfb_pdata); - mx23_add_rtc_stmp3xxx(); -} - -static void __init mx23evk_timer_init(void) -{ - mx23_clocks_init(); -} - -static struct sys_timer mx23evk_timer = { - .init = mx23evk_timer_init, -}; - -MACHINE_START(MX23EVK, "Freescale MX23 EVK") - /* Maintainer: Freescale Semiconductor, Inc. */ - .map_io = mx23_map_io, - .init_irq = mx23_init_irq, - .timer = &mx23evk_timer, - .init_machine = mx23evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c deleted file mode 100644 index dafd48e86c8c..000000000000 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/clk.h> -#include <linux/i2c.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/iomux-mx28.h> -#include <mach/digctl.h> - -#include "devices-mx28.h" - -#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) -#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) -#define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5) -#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18) -#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) -#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) - -#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) -#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) -#define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) -#define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) - -static const iomux_cfg_t mx28evk_pads[] __initconst = { - /* duart */ - MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, - MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL, - - /* auart0 */ - MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL, - MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL, - MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL, - /* auart3 */ - MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL, - MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL, - MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL, - MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL, - -#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP) - /* fec0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC, - /* fec1 */ - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC, - MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC, - /* phy power line */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL, - /* phy reset line */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL, - - /* flexcan0 */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - /* flexcan1 */ - MX28_PAD_GPMI_CE2N__CAN1_TX, - MX28_PAD_GPMI_CE3N__CAN1_RX, - /* transceiver power control */ - MX28_PAD_SSP1_CMD__GPIO_2_13, - - /* mxsfb (lcdif) */ - MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, - MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, - MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, - MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, - MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, - MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, - MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, - MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, - MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, - MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, - MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, - MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, - MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, - MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, - MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, - MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, - MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, - MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, - MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, - MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, - MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, - MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, - MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, - MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, - MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, - MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL, - /* LCD panel enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, - /* backlight control */ - MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, - /* mmc0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA4__SSP0_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA5__SSP0_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA6__SSP0_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA7__SSP0_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_SSP1_SCK__GPIO_2_12 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* mmc1 */ - MX28_PAD_GPMI_D00__SSP1_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D01__SSP1_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D02__SSP1_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D03__SSP1_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D04__SSP1_D4 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D05__SSP1_D5 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D06__SSP1_D6 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_D07__SSP1_D7 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY1__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_GPMI_WRN__SSP1_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_GPMI_RESETN__GPIO_0_28 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* slot power enable */ - MX28_PAD_PWM4__GPIO_3_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - - /* led */ - MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_I2C0_SDA__I2C0_SDA | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* saif0 & saif1 */ - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), -}; - -/* led */ -static const struct gpio_led mx28evk_leds[] __initconst = { - { - .name = "GPIO-LED", - .default_trigger = "heartbeat", - .gpio = MX28EVK_GPIO_LED, - }, -}; - -static const struct gpio_led_platform_data mx28evk_led_data __initconst = { - .leds = mx28evk_leds, - .num_leds = ARRAY_SIZE(mx28evk_leds), -}; - -/* fec */ -static void __init mx28evk_fec_reset(void) -{ - struct clk *clk; - - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - - gpio_set_value(MX28EVK_FEC_PHY_RESET, 0); - mdelay(1); - gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); -} - -static struct fec_platform_data mx28_fec_pdata[] __initdata = { - { - /* fec0 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, { - /* fec1 */ - .phy = PHY_INTERFACE_MODE_RMII, - }, -}; - -static int __init mx28evk_fec_get_mac(void) -{ - int i; - u32 val; - const u32 *ocotp = mxs_get_ocotp(); - - if (!ocotp) - return -ETIMEDOUT; - - /* - * OCOTP only stores the last 4 octets for each mac address, - * so hard-code Freescale OUI (00:04:9f) here. - */ - for (i = 0; i < 2; i++) { - val = ocotp[i]; - mx28_fec_pdata[i].mac[0] = 0x00; - mx28_fec_pdata[i].mac[1] = 0x04; - mx28_fec_pdata[i].mac[2] = 0x9f; - mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff; - mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff; - mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff; - } - - return 0; -} - -/* - * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers - */ -static int flexcan0_en, flexcan1_en; - -static void mx28evk_flexcan_switch(void) -{ - if (flexcan0_en || flexcan1_en) - gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); - else - gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); -} - -static void mx28evk_flexcan0_switch(int enable) -{ - flexcan0_en = enable; - mx28evk_flexcan_switch(); -} - -static void mx28evk_flexcan1_switch(int enable) -{ - flexcan1_en = enable; - mx28evk_flexcan_switch(); -} - -static const struct flexcan_platform_data - mx28evk_flexcan_pdata[] __initconst = { - { - .transceiver_switch = mx28evk_flexcan0_switch, - }, { - .transceiver_switch = mx28evk_flexcan1_switch, - } -}; - -/* mxsfb (lcdif) */ -static struct fb_videomode mx28evk_video_modes[] = { - { - .name = "Seiko-43WVF1G", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 29851, /* picosecond (33.5 MHz) */ - .left_margin = 89, - .right_margin = 164, - .upper_margin = 23, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 10, - .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | - FB_SYNC_DOTCLK_FAILING_ACT, - }, -}; - -static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { - .mode_list = mx28evk_video_modes, - .mode_count = ARRAY_SIZE(mx28evk_video_modes), - .default_bpp = 32, - .ld_intf_width = STMLCDIF_24BIT, -}; - -static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { - { - /* mmc0 */ - .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, { - /* mmc1 */ - .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, - .flags = SLOTF_8_BIT_CAPABLE, - }, -}; - -static struct i2c_board_info mxs_i2c0_board_info[] __initdata = { - { - I2C_BOARD_INFO("sgtl5000", 0x0a), - }, -}; - -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("VDDA", "0-000a"), - REGULATOR_SUPPLY("VDDIO", "0-000a"), -}; - -static struct regulator_init_data mx28evk_vdd_reg_init_data = { - .constraints = { - .name = "3V3", - .always_on = 1, - }, - .consumer_supplies = mx28evk_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies), -}; - -static struct fixed_voltage_config mx28evk_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 1, - .init_data = &mx28evk_vdd_reg_init_data, -}; -static struct platform_device mx28evk_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &mx28evk_vdd_pdata, - }, -}; -static void __init mx28evk_add_regulators(void) -{ - platform_device_register(&mx28evk_voltage_regulator); -} -#else -static void __init mx28evk_add_regulators(void) {} -#endif - -static const struct gpio mx28evk_gpios[] __initconst = { - { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, - { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, - { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" }, - { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" }, - { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" }, - { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, - { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" }, -}; - -static const struct mxs_saif_platform_data - mx28evk_mxs_saif_pdata[] __initconst = { - /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */ - { - .master_mode = 1, - .master_id = 0, - }, { - .master_mode = 0, - .master_id = 0, - }, -}; - -static void __init mx28evk_init(void) -{ - int ret; - - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); - - mx28_add_duart(); - mx28_add_auart0(); - mx28_add_auart3(); - - if (mx28evk_fec_get_mac()) - pr_warn("%s: failed on fec mac setup\n", __func__); - - ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios)); - if (ret) - pr_err("One or more GPIOs failed to be requested: %d\n", ret); - - mx28evk_fec_reset(); - mx28_add_fec(0, &mx28_fec_pdata[0]); - mx28_add_fec(1, &mx28_fec_pdata[1]); - - mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]); - mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); - - mx28_add_mxsfb(&mx28evk_mxsfb_pdata); - - mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); - mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]); - mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]); - - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, mxs_i2c0_board_info, - ARRAY_SIZE(mxs_i2c0_board_info)); - - mx28evk_add_regulators(); - - mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, - NULL, 0); - - mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); - mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); - - mx28_add_rtc_stmp3xxx(); - - gpio_led_register_device(0, &mx28evk_led_data); -} - -static void __init mx28evk_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer mx28evk_timer = { - .init = mx28evk_timer_init, -}; - -MACHINE_START(MX28EVK, "Freescale MX28 EVK") - /* Maintainer: Freescale Semiconductor, Inc. */ - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &mx28evk_timer, - .init_machine = mx28evk_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8dabfe81d07c..4748ec551a68 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -12,18 +12,21 @@ #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/can/platform/flexcan.h> +#include <linux/delay.h> #include <linux/err.h> +#include <linux/gpio.h> #include <linux/init.h> -#include <linux/init.h> -#include <linux/irqdomain.h> #include <linux/micrel_phy.h> #include <linux/mxsfb.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/phy.h> +#include <linux/pinctrl/consumer.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> +#include <mach/digctl.h> +#include <mach/mxs.h> static struct fb_videomode mx23evk_video_modes[] = { { @@ -99,43 +102,43 @@ static struct fb_videomode apx4devkit_video_modes[] = { static struct mxsfb_platform_data mxsfb_pdata __initdata; -static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), - OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), - { /* sentinel */ } -}; +/* + * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers + */ +#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) -static int __init mxs_icoll_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL); +static int flexcan0_en, flexcan1_en; - return 0; +static void mx28evk_flexcan_switch(void) +{ + if (flexcan0_en || flexcan1_en) + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); + else + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); } -static int __init mxs_gpio_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) +static void mx28evk_flexcan0_switch(int enable) { - static int gpio_irq_base = MXS_GPIO_IRQ_START; - - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL); - gpio_irq_base += 32; + flexcan0_en = enable; + mx28evk_flexcan_switch(); +} - return 0; +static void mx28evk_flexcan1_switch(int enable) +{ + flexcan1_en = enable; + mx28evk_flexcan_switch(); } -static const struct of_device_id mxs_irq_match[] __initconst = { - { .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, }, - { .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, }, +static struct flexcan_platform_data flexcan_pdata[2]; + +static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), + OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), { /* sentinel */ } }; -static void __init mxs_dt_init_irq(void) -{ - icoll_init_irq(); - of_irq_init(mxs_irq_match); -} - static void __init imx23_timer_init(void) { mx23_clocks_init(); @@ -237,13 +240,21 @@ static void __init imx28_evk_init(void) mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); mxsfb_pdata.default_bpp = 32; mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; + + mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); } -static void __init m28evk_init(void) +static void __init imx28_evk_post_init(void) { - enable_clk_enet_out(); - update_fec_mac_prop(OUI_DENX); + if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, + "flexcan-switch")) { + flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch; + flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch; + } +} +static void __init m28evk_init(void) +{ mxsfb_pdata.mode_list = m28evk_video_modes; mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); mxsfb_pdata.default_bpp = 16; @@ -261,7 +272,7 @@ static void __init apx4devkit_init(void) enable_clk_enet_out(); if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, + phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, apx4devkit_phy_fixup); mxsfb_pdata.mode_list = apx4devkit_video_modes; @@ -270,6 +281,80 @@ static void __init apx4devkit_init(void) mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } +#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) +#define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1) +#define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2) +#define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3) +#define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4) +#define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6) +#define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7) +#define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8) +#define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16) + +#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) +#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) +#define TX28_FEC_nINT MXS_GPIO_NR(4, 5) + +static const struct gpio tx28_gpios[] __initconst = { + { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, + { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, + { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, + { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" }, + { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" }, + { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" }, + { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" }, + { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" }, + { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" }, + { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, + { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" }, + { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" }, +}; + +static void __init tx28_post_init(void) +{ + struct device_node *np; + struct platform_device *pdev; + struct pinctrl *pctl; + int ret; + + enable_clk_enet_out(); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec"); + pdev = of_find_device_by_node(np); + if (!pdev) { + pr_err("%s: failed to find fec device\n", __func__); + return; + } + + pctl = pinctrl_get_select(&pdev->dev, "gpio_mode"); + if (IS_ERR(pctl)) { + pr_err("%s: failed to get pinctrl state\n", __func__); + return; + } + + ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); + if (ret) { + pr_err("%s: failed to request gpios: %d\n", __func__, ret); + return; + } + + /* Power up fec phy */ + gpio_set_value(TX28_FEC_PHY_POWER, 1); + msleep(26); /* 25ms according to data sheet */ + + /* Mode strap pins */ + gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1); + gpio_set_value(ENET0_RXD0__GPIO_4_3, 1); + gpio_set_value(ENET0_RXD1__GPIO_4_4, 1); + + udelay(100); /* minimum assertion time for nRST */ + + /* Deasserting FEC PHY RESET */ + gpio_set_value(TX28_FEC_PHY_RESET, 1); + + pinctrl_put(pctl); +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) @@ -283,29 +368,28 @@ static void __init mxs_machine_init(void) of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); + + if (of_machine_is_compatible("karo,tx28")) + tx28_post_init(); + + if (of_machine_is_compatible("fsl,imx28-evk")) + imx28_evk_post_init(); } static const char *imx23_dt_compat[] __initdata = { - "fsl,imx23-evk", - "fsl,stmp378x_devb" - "olimex,imx23-olinuxino", "fsl,imx23", NULL, }; static const char *imx28_dt_compat[] __initdata = { - "bluegiga,apx4devkit", - "crystalfontz,cfa10036", - "denx,m28evk", - "fsl,imx28-evk", - "karo,tx28", "fsl,imx28", NULL, }; DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)") .map_io = mx23_map_io, - .init_irq = mxs_dt_init_irq, + .init_irq = icoll_init_irq, + .handle_irq = icoll_handle_irq, .timer = &imx23_timer, .init_machine = mxs_machine_init, .dt_compat = imx23_dt_compat, @@ -314,7 +398,8 @@ MACHINE_END DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)") .map_io = mx28_map_io, - .init_irq = mxs_dt_init_irq, + .init_irq = icoll_init_irq, + .handle_irq = icoll_handle_irq, .timer = &imx28_timer, .init_machine = mxs_machine_init, .dt_compat = imx28_dt_compat, diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c deleted file mode 100644 index 6548965e4a76..000000000000 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * board setup for STMP378x-Development-Board - * - * based on mx23evk board setup and information gained form the original - * plat-stmp based board setup, now converted to mach-mxs. - * - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/spi/spi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/iomux-mx23.h> - -#include "devices-mx23.h" - -#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) -#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) - -#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) - -static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { - /* duart (extended setup missing in old boardcode, too */ - MX23_PAD_PWM0__DUART_RX, - MX23_PAD_PWM1__DUART_TX, - - /* auart */ - MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, - MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, - - /* mmc */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_CMD__SSP1_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX23_PAD_SSP1_DETECT__SSP1_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ - MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ -}; - -static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { - .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, -}; - -static struct spi_board_info spi_board_info[] __initdata = { -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - { - .modalias = "enc28j60", - .max_speed_hz = 6 * 1000 * 1000, - .bus_num = 1, - .chip_select = 0, - .platform_data = NULL, - }, -#endif -}; - -static void __init stmp378x_dvb_init(void) -{ - int ret; - - mx23_soc_init(); - - mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, - ARRAY_SIZE(stmp378x_dvb_pads)); - - mx23_add_duart(); - mx23_add_auart0(); - mx23_add_rtc_stmp3xxx(); - - /* power on mmc slot */ - ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, - GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); - if (ret) - pr_warn("could not power mmc (%d)\n", ret); - - mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); - - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); -} - -static void __init stmp378x_dvb_timer_init(void) -{ - mx23_clocks_init(); -} - -static struct sys_timer stmp378x_dvb_timer = { - .init = stmp378x_dvb_timer_init, -}; - -MACHINE_START(STMP378X, "STMP378X") - .map_io = mx23_map_io, - .init_irq = mx23_init_irq, - .timer = &stmp378x_dvb_timer, - .init_machine = stmp378x_dvb_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c deleted file mode 100644 index 8837029de1a4..000000000000 --- a/arch/arm/mach-mxs/mach-tx28.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (C) 2010 <LW@KARO-electronics.de> - * - * based on: mach-mx28_evk.c - * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation - */ -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_gpio.h> -#include <linux/i2c.h> - -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <mach/common.h> -#include <mach/iomux-mx28.h> - -#include "devices-mx28.h" -#include "module-tx28.h" - -#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10) - -static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = { - /* LED */ - MX28_PAD_ENET0_RXD3__GPIO_4_10 | - MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL, - - /* framebuffer */ -#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA) - MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE, - MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE, - MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE, - MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE, - MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE, - MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE, - MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE, - MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE, - MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE, - MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE, - MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE, - MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE, - MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE, - MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE, - MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE, - MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE, - MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE, - MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE, - MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE, - MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE, - MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE, - MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE, - MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE, - MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE, - MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE, - MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE, - MX28_PAD_LCD_CS__LCD_CS | LCD_MODE, - MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE, - MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE, - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE, - MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE, - MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE, - MX28_PAD_PWM0__PWM_0 | LCD_MODE, - - /* UART1 */ - MX28_PAD_AUART0_CTS__DUART_RX, - MX28_PAD_AUART0_RTS__DUART_TX, - MX28_PAD_AUART0_TX__DUART_RTS, - MX28_PAD_AUART0_RX__DUART_CTS, - - /* UART2 */ - MX28_PAD_AUART1_RX__AUART1_RX, - MX28_PAD_AUART1_TX__AUART1_TX, - MX28_PAD_AUART1_RTS__AUART1_RTS, - MX28_PAD_AUART1_CTS__AUART1_CTS, - - /* CAN */ - MX28_PAD_GPMI_RDY2__CAN0_TX, - MX28_PAD_GPMI_RDY3__CAN0_RX, - - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* TSC2007 */ - MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA1__SSP0_D1 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA2__SSP0_D2 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DATA3__SSP0_D3 | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_CMD__SSP0_CMD | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), -}; - -static const struct gpio_led tx28_stk5v3_leds[] __initconst = { - { - .name = "GPIO-LED", - .default_trigger = "heartbeat", - .gpio = TX28_STK5_GPIO_LED, - }, -}; - -static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = { - .leds = tx28_stk5v3_leds, - .num_leds = ARRAY_SIZE(tx28_stk5v3_leds), -}; - -static struct spi_board_info tx28_spi_board_info[] = { - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 1, - .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT, - .mode = SPI_MODE_0, - }, -}; - -static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = { - { - I2C_BOARD_INFO("ds1339", 0x68), - }, -}; - -static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = { - .wp_gpio = -EINVAL, - .flags = SLOTF_4_BIT_CAPABLE, -}; - -static void __init tx28_stk5v3_init(void) -{ - mx28_soc_init(); - - mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads, - ARRAY_SIZE(tx28_stk5v3_pads)); - - mx28_add_duart(); /* UART1 */ - mx28_add_auart(1); /* UART2 */ - - tx28_add_fec0(); - /* spi via ssp will be added when available */ - spi_register_board_info(tx28_spi_board_info, - ARRAY_SIZE(tx28_spi_board_info)); - gpio_led_register_device(0, &tx28_stk5v3_led_data); - mx28_add_mxs_i2c(0); - i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, - ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); - mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); - mx28_add_rtc_stmp3xxx(); -} - -static void __init tx28_timer_init(void) -{ - mx28_clocks_init(); -} - -static struct sys_timer tx28_timer = { - .init = tx28_timer_init, -}; - -MACHINE_START(TX28, "Ka-Ro electronics TX28 module") - .map_io = mx28_map_io, - .init_irq = mx28_init_irq, - .timer = &tx28_timer, - .init_machine = tx28_stk5v3_init, - .restart = mxs_restart, -MACHINE_END diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c index dccb67a9e7c4..a4294aa9f301 100644 --- a/arch/arm/mach-mxs/mm.c +++ b/arch/arm/mach-mxs/mm.c @@ -13,14 +13,11 @@ #include <linux/mm.h> #include <linux/init.h> -#include <linux/pinctrl/machine.h> #include <asm/mach/map.h> #include <mach/mx23.h> #include <mach/mx28.h> -#include <mach/common.h> -#include <mach/iomux.h> /* * Define the MX23 memory map. @@ -48,43 +45,7 @@ void __init mx23_map_io(void) iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); } -void __init mx23_init_irq(void) -{ - icoll_init_irq(); -} - void __init mx28_map_io(void) { iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); } - -void __init mx28_init_irq(void) -{ - icoll_init_irq(); -} - -void __init mx23_soc_init(void) -{ - pinctrl_provide_dummies(); - - mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR); - mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR); - - mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0); - mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1); - mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2); -} - -void __init mx28_soc_init(void) -{ - pinctrl_provide_dummies(); - - mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR); - mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR); - - mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0); - mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1); - mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2); - mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3); - mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4); -} diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c deleted file mode 100644 index 0f71f82101cc..000000000000 --- a/arch/arm/mach-mxs/module-tx28.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2010 <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/delay.h> -#include <linux/fec.h> -#include <linux/gpio.h> - -#include <mach/iomux-mx28.h> -#include "devices-mx28.h" - -#include "module-tx28.h" - -#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) -#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) - -static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { - /* PHY POWER */ - MX28_PAD_PWM4__GPIO_3_29 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - /* PHY RESET */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - /* Mode strap pins 0-2 */ - MX28_PAD_ENET0_RXD0__GPIO_4_3 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - MX28_PAD_ENET0_RXD1__GPIO_4_4 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - MX28_PAD_ENET0_RX_EN__GPIO_4_2 | - MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3, - /* nINT */ - MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | - MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3, - - MX28_PAD_ENET0_MDC__GPIO_4_0, - MX28_PAD_ENET0_MDIO__GPIO_4_1, - MX28_PAD_ENET0_TX_EN__GPIO_4_6, - MX28_PAD_ENET0_TXD0__GPIO_4_7, - MX28_PAD_ENET0_TXD1__GPIO_4_8, - MX28_PAD_ENET_CLK__GPIO_4_16, -}; - -#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) -static const iomux_cfg_t tx28_fec0_pads[] __initconst = { - MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, -}; - -static const iomux_cfg_t tx28_fec1_pads[] __initconst = { - MX28_PAD_ENET0_RXD2__ENET1_RXD0, - MX28_PAD_ENET0_RXD3__ENET1_RXD1, - MX28_PAD_ENET0_TXD2__ENET1_TXD0, - MX28_PAD_ENET0_TXD3__ENET1_TXD1, - MX28_PAD_ENET0_COL__ENET1_TX_EN, - MX28_PAD_ENET0_CRS__ENET1_RX_EN, -}; - -static const struct fec_platform_data tx28_fec0_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct fec_platform_data tx28_fec1_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -int __init tx28_add_fec0(void) -{ - int i, ret; - - pr_debug("%s: Switching FEC PHY power off\n", __func__); - ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads, - ARRAY_SIZE(tx28_fec_gpio_pads)); - for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) { - unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i])); - - ret = gpio_request(gpio, "FEC"); - if (ret) { - pr_err("Failed to request GPIO_%d_%d: %d\n", - PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i]), ret); - goto free_gpios; - } - ret = gpio_direction_output(gpio, 0); - if (ret) { - pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n", - gpio / 32 + 1, gpio % 32, ret); - goto free_gpios; - } - } - - /* Power up fec phy */ - pr_debug("%s: Switching FEC PHY power on\n", __func__); - ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1); - if (ret) { - pr_err("Failed to power on PHY: %d\n", ret); - goto free_gpios; - } - mdelay(26); /* 25ms according to data sheet */ - - /* nINT */ - gpio_direction_input(MXS_GPIO_NR(4, 5)); - /* Mode strap pins */ - gpio_direction_output(MXS_GPIO_NR(4, 2), 1); - gpio_direction_output(MXS_GPIO_NR(4, 3), 1); - gpio_direction_output(MXS_GPIO_NR(4, 4), 1); - - udelay(100); /* minimum assertion time for nRST */ - - pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); - gpio_set_value(TX28_FEC_PHY_RESET, 1); - - ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, - ARRAY_SIZE(tx28_fec0_pads)); - if (ret) { - pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", - __func__, ret); - goto free_gpios; - } - pr_debug("%s: Registering FEC0 device\n", __func__); - mx28_add_fec(0, &tx28_fec0_data); - return 0; - -free_gpios: - while (--i >= 0) { - unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]), - PAD_PIN(tx28_fec_gpio_pads[i])); - - gpio_free(gpio); - } - - return ret; -} - -int __init tx28_add_fec1(void) -{ - int ret; - - ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, - ARRAY_SIZE(tx28_fec1_pads)); - if (ret) { - pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", - __func__, ret); - return ret; - } - pr_debug("%s: Registering FEC1 device\n", __func__); - mx28_add_fec(1, &tx28_fec1_data); - return 0; -} diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h deleted file mode 100644 index 8ed425457d30..000000000000 --- a/arch/arm/mach-mxs/module-tx28.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -int __init tx28_add_fec0(void); -int __init tx28_add_fec1(void); diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 02d36de9c4e8..7c3792613392 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -25,6 +25,8 @@ #include <linux/irq.h> #include <linux/clockchips.h> #include <linux/clk.h> +#include <linux/of.h> +#include <linux/of_irq.h> #include <asm/mach/time.h> #include <mach/mxs.h> @@ -244,9 +246,17 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) return 0; } -void __init mxs_timer_init(int irq) +void __init mxs_timer_init(void) { + struct device_node *np; struct clk *timer_clk; + int irq; + + np = of_find_compatible_node(NULL, NULL, "fsl,timrot"); + if (!np) { + pr_err("%s: failed find timrot node\n", __func__); + return; + } timer_clk = clk_get_sys("timrot", NULL); if (IS_ERR(timer_clk)) { @@ -295,5 +305,6 @@ void __init mxs_timer_init(int irq) mxs_clockevent_init(timer_clk); /* Make irqs happen */ + irq = irq_of_parse_and_map(np, 0); setup_irq(irq, &mxs_timer_irq); } diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index f4535a7dadf5..c3841a9a8fa8 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -112,8 +112,7 @@ static struct mtd_partition nhk8815_partitions[] = { static struct nomadik_nand_platform_data nhk8815_nand_data = { .parts = nhk8815_partitions, .nparts = ARRAY_SIZE(nhk8815_partitions), - .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \ - | NAND_NO_READRDY, + .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING, .init = nhk8815_nand_init, }; diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h index 6316dba3bfc8..02035e459f50 100644 --- a/arch/arm/mach-nomadik/include/mach/hardware.h +++ b/arch/arm/mach-nomadik/include/mach/hardware.h @@ -30,7 +30,7 @@ - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL) /* used in asm code, so no casts */ -#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) +#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) /* * Base address defination for Nomadik Onchip Logic Block diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h index 071003bc8456..7d4687e9cbdf 100644 --- a/arch/arm/mach-nomadik/include/mach/uncompress.h +++ b/arch/arm/mach-nomadik/include/mach/uncompress.h @@ -27,10 +27,10 @@ struct amba_device; #include <linux/amba/serial.h> -#define NOMADIK_UART_DR 0x101FB000 -#define NOMADIK_UART_LCRH 0x101FB02c -#define NOMADIK_UART_CR 0x101FB030 -#define NOMADIK_UART_FR 0x101FB018 +#define NOMADIK_UART_DR (void __iomem *)0x101FB000 +#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c +#define NOMADIK_UART_CR (void __iomem *)0x101FB030 +#define NOMADIK_UART_FR (void __iomem *)0x101FB018 static void putc(const char c) { diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index a051cb8ae57f..3d1e1c250a1a 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -16,8 +16,9 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <plat/board-ams-delta.h> +#include <mach/board-ams-delta.h> +#include <mach/irqs.h> #include <mach/ams-delta-fiq.h> #include "iomap.h" diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index 68e8e5654c0a..f12a12af3523 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -19,7 +19,7 @@ #include <linux/module.h> #include <linux/io.h> -#include <plat/board-ams-delta.h> +#include <mach/board-ams-delta.h> #include <asm/fiq.h> diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index c53469802c03..9518bf5996dc 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -26,6 +26,7 @@ #include <linux/export.h> #include <linux/omapfb.h> #include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> #include <media/soc_camera.h> @@ -34,10 +35,9 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board-ams-delta.h> -#include <plat/keypad.h> -#include <plat/mux.h> -#include <plat/board.h> +#include <mach/board-ams-delta.h> +#include <linux/platform_data/keypad-omap.h> +#include <mach/mux.h> #include <mach/hardware.h> #include <mach/ams-delta-fiq.h> diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 6872f3fd400f..4b6de70c47a6 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -28,11 +28,10 @@ #include <asm/mach/map.h> #include <plat/tc.h> -#include <plat/mux.h> -#include <plat/flash.h> +#include <mach/mux.h> +#include <mach/flash.h> #include <plat/fpga.h> -#include <plat/keypad.h> -#include <plat/board.h> +#include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 6ec385e2b98e..4ec579fdd366 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -22,8 +22,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mux.h> -#include <plat/board.h> +#include <mach/mux.h> #include <mach/usb.h> @@ -52,9 +51,6 @@ static struct omap_usb_config generic1610_usb_config __initdata = { }; #endif -static struct omap_board_config_kernel generic_config[] __initdata = { -}; - static void __init omap_generic_init(void) { #ifdef CONFIG_ARCH_OMAP15XX @@ -76,8 +72,6 @@ static void __init omap_generic_init(void) } #endif - omap_board_config = generic_config; - omap_board_config_size = ARRAY_SIZE(generic_config); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); } diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index cd8836f43f01..376f7f29ef77 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -31,18 +31,19 @@ #include <linux/i2c/tps65010.h> #include <linux/smc91x.h> #include <linux/omapfb.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/leds.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/dma.h> #include <plat/tc.h> -#include <plat/irda.h> -#include <plat/keypad.h> -#include <plat/flash.h> +#include <mach/irda.h> +#include <linux/platform_data/keypad-omap.h> +#include <mach/flash.h> #include <mach/hardware.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 1fa9c45c1ae5..ededdb7ef28c 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -31,6 +31,7 @@ #include <linux/i2c/tps65010.h> #include <linux/smc91x.h> #include <linux/omapfb.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/leds.h> #include <asm/setup.h> @@ -39,11 +40,11 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/tc.h> -#include <plat/keypad.h> +#include <linux/platform_data/keypad-omap.h> #include <plat/dma.h> -#include <plat/flash.h> +#include <mach/flash.h> #include <mach/hardware.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index b3f6e943e661..87ab2086ef96 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -37,13 +37,12 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/omapfb.h> +#include <linux/platform_data/keypad-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <plat/omap7xx.h> -#include <plat/board.h> -#include <plat/keypad.h> +#include <mach/omap7xx.h> #include <plat/mmc.h> #include <mach/irqs.h> @@ -476,8 +475,7 @@ static void __init htcherald_lcd_init(void) break; } if (!tries) - printk(KERN_WARNING "Timeout waiting for end of frame " - "-- LCD may not be available\n"); + pr_err("Timeout waiting for end of frame -- LCD may not be available\n"); /* turn off DMA */ reg = omap_readw(OMAP_DMA_LCD_CCR); diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index f21c2966daad..db5f7d2976e7 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -31,11 +31,11 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mux.h> -#include <plat/flash.h> +#include <mach/mux.h> +#include <mach/flash.h> #include <plat/fpga.h> #include <plat/tc.h> -#include <plat/keypad.h> +#include <linux/platform_data/keypad-omap.h> #include <plat/mmc.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 2c0ca8fc3380..7d5c06d6a52a 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -21,14 +21,14 @@ #include <linux/workqueue.h> #include <linux/delay.h> +#include <linux/platform_data/keypad-omap.h> +#include <linux/platform_data/lcd-mipid.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mux.h> -#include <plat/board.h> -#include <plat/keypad.h> -#include <plat/lcd_mipid.h> +#include <mach/mux.h> #include <plat/mmc.h> #include <plat/clock.h> diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7ee1c1eac356..5973945a8741 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -39,13 +39,15 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/i2c/tps65010.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/omap1_bl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/tc.h> #include <mach/hardware.h> @@ -302,7 +304,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> -#include <plat/keypad.h> +#include <linux/platform_data/keypad-omap.h> static struct at24_platform_data at24c04 = { .byte_len = SZ_4K / 8, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 26bcb9defcdc..1c578d58923a 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -28,18 +28,18 @@ #include <linux/interrupt.h> #include <linux/apm-emulation.h> #include <linux/omapfb.h> +#include <linux/platform_data/omap1_bl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/tc.h> #include <plat/dma.h> -#include <plat/board.h> -#include <plat/irda.h> -#include <plat/keypad.h> +#include <mach/irda.h> +#include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 4d099446dfa8..97158095083c 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -27,19 +27,19 @@ #include <linux/omapfb.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/platform_data/omap1_bl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <plat/led.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/dma.h> #include <plat/tc.h> -#include <plat/board.h> -#include <plat/irda.h> -#include <plat/keypad.h> +#include <mach/irda.h> +#include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 355980321c2d..e311032e7eeb 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -30,18 +30,18 @@ #include <linux/omapfb.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/platform_data/omap1_bl.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/dma.h> #include <plat/tc.h> -#include <plat/board.h> -#include <plat/irda.h> -#include <plat/keypad.h> +#include <mach/irda.h> +#include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 703d55ecffe2..198b05417bfc 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -22,17 +22,16 @@ #include <linux/input.h> #include <linux/smc91x.h> #include <linux/omapfb.h> +#include <linux/platform_data/keypad-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <plat/tc.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/fpga.h> -#include <plat/flash.h> -#include <plat/keypad.h> -#include <plat/board.h> +#include <mach/flash.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index b59f78850e69..5932d56e17bf 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -17,7 +17,7 @@ #include <mach/hardware.h> #include <plat/mmc.h> -#include <plat/board-sx1.h> +#include <mach/board-sx1.h> #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 8c665bd16ac2..13bf2cc56814 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -28,19 +28,18 @@ #include <linux/errno.h> #include <linux/export.h> #include <linux/omapfb.h> +#include <linux/platform_data/keypad-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/dma.h> -#include <plat/irda.h> +#include <mach/irda.h> #include <plat/tc.h> -#include <plat/board.h> -#include <plat/keypad.h> -#include <plat/board-sx1.h> +#include <mach/board-sx1.h> #include <mach/hardware.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 3497769eb353..ad75e3411d46 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -31,11 +31,10 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board-voiceblue.h> -#include <plat/flash.h> -#include <plat/mux.h> +#include <mach/board-voiceblue.h> +#include <mach/flash.h> +#include <mach/mux.h> #include <plat/tc.h> -#include <plat/board.h> #include <mach/hardware.h> #include <mach/usb.h> @@ -155,9 +154,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { .pins[2] = 6, }; -static struct omap_board_config_kernel voiceblue_config[] = { -}; - #define MACHINE_PANICED 1 #define MACHINE_REBOOTING 2 #define MACHINE_REBOOT 4 @@ -275,8 +271,6 @@ static void __init voiceblue_init(void) voiceblue_smc91x_resources[1].start = gpio_to_irq(8); voiceblue_smc91x_resources[1].end = gpio_to_irq(8); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); - omap_board_config = voiceblue_config; - omap_board_config_size = ARRAY_SIZE(voiceblue_config); omap_serial_init(); omap1_usb_init(&voiceblue_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index a9ee06b6cb42..638f4070fc70 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk) /* Clocks in the DSP domain need api_ck. Just assume bootloader * has not enabled any DSP clocks */ if (clk->enable_reg == DSP_IDLECT2) { - printk(KERN_INFO "Skipping reset check for DSP domain " - "clock \"%s\"\n", clk->name); + pr_info("Skipping reset check for DSP domain clock \"%s\"\n", + clk->name); return; } diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c007d80dfb62..9b45f4b0ee22 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -25,7 +25,6 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/clkdev_omap.h> -#include <plat/board.h> #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ #include <mach/hardware.h> @@ -776,11 +775,10 @@ static struct clk_functions omap1_clk_functions = { static void __init omap1_show_rates(void) { - pr_notice("Clocking rate (xtal/DPLL1/MPU): " - "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); + pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } u32 cpu_mask; @@ -788,7 +786,6 @@ u32 cpu_mask; int __init omap1_clk_init(void) { struct omap_clk *c; - const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ u32 reg; @@ -837,19 +834,13 @@ int __init omap1_clk_init(void) ck_dpll1_p = clk_get(NULL, "ck_dpll1"); ck_ref_p = clk_get(NULL, "ck_ref"); - info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); - if (info != NULL) { - if (!cpu_is_omap15xx()) - crystal_type = info->system_clock_type; - } - if (cpu_is_omap7xx()) ck_ref.rate = 13000000; if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " - "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", + omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index fa1fa4deb6aa..0cc54dd553e3 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -20,12 +20,11 @@ #include <asm/mach/map.h> #include <plat/tc.h> -#include <plat/board.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/dma.h> #include <plat/mmc.h> -#include <plat/omap7xx.h> +#include <mach/omap7xx.h> #include <mach/camera.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 3ef7d52316b4..29007fef84cd 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -27,7 +27,8 @@ #include <plat/dma.h> #include <plat/tc.h> -#include <plat/irqs.h> + +#include <mach/irqs.h> #define OMAP1_DMA_BASE (0xfffed800) #define OMAP1_LOGICAL_DMA_CH_COUNT 17 @@ -330,8 +331,9 @@ static int __init omap1_system_dma_init(void) d->chan = kzalloc(sizeof(struct omap_dma_lch) * (d->lch_count), GFP_KERNEL); if (!d->chan) { - dev_err(&pdev->dev, "%s: Memory allocation failed" - "for d->chan!!!\n", __func__); + dev_err(&pdev->dev, + "%s: Memory allocation failed for d->chan!\n", + __func__); goto exit_release_d; } diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index 401eb3c080c2..73ae6169aa4a 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -11,7 +11,7 @@ #include <linux/mtd/map.h> #include <plat/tc.h> -#include <plat/flash.h> +#include <mach/flash.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index ebef15e5e7b7..98e6f39224a4 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c @@ -17,6 +17,7 @@ */ #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE #define OMAP1510_GPIO_BASE 0xFFFCE000 diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 2a48cd2e1754..33f419236b17 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -17,6 +17,7 @@ */ #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #define OMAP1610_GPIO1_BASE 0xfffbe400 #define OMAP1610_GPIO2_BASE 0xfffbec00 diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index acf12b73eace..958ce9acee95 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c @@ -17,6 +17,7 @@ */ #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #define OMAP7XX_GPIO1_BASE 0xfffbc000 #define OMAP7XX_GPIO2_BASE 0xfffbc800 diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 5446c9912641..a0551a6d7451 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -20,7 +20,7 @@ */ #include <plat/i2c.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/cpu.h> void __init omap1_i2c_mux_pins(int bus_id) diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index 23eed0035ed8..adb5e7649659 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -14,8 +14,6 @@ #ifndef __AMS_DELTA_FIQ_H #define __AMS_DELTA_FIQ_H -#include <plat/irqs.h> - /* * Interrupt number used for passing control from FIQ to IRQ. * IRQ12, described as reserved, has been selected. diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/mach-omap1/include/mach/board-ams-delta.h index ad6f865d1f16..ad6f865d1f16 100644 --- a/arch/arm/plat-omap/include/plat/board-ams-delta.h +++ b/arch/arm/mach-omap1/include/mach/board-ams-delta.h diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/mach-omap1/include/mach/board-sx1.h index 355adbdaae33..355adbdaae33 100644 --- a/arch/arm/plat-omap/include/plat/board-sx1.h +++ b/arch/arm/mach-omap1/include/mach/board-sx1.h diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/mach-omap1/include/mach/board-voiceblue.h index 27916b210f57..27916b210f57 100644 --- a/arch/arm/plat-omap/include/plat/board-voiceblue.h +++ b/arch/arm/mach-omap1/include/mach/board-voiceblue.h diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/mach-omap1/include/mach/flash.h index 0d88499b79e9..0d88499b79e9 100644 --- a/arch/arm/plat-omap/include/plat/flash.h +++ b/arch/arm/mach-omap1/include/mach/flash.h diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h index e737706a8fe1..ebf86c0f4f46 100644 --- a/arch/arm/mach-omap1/include/mach/gpio.h +++ b/arch/arm/mach-omap1/include/mach/gpio.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap1/include/mach/gpio.h */ - -#include <plat/gpio.h> diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h index 01e35fa106b8..84248d250adb 100644 --- a/arch/arm/mach-omap1/include/mach/hardware.h +++ b/arch/arm/mach-omap1/include/mach/hardware.h @@ -1,11 +1,46 @@ /* * arch/arm/mach-omap1/include/mach/hardware.h + * + * Hardware definitions for TI OMAP processors and boards + * + * NOTE: Please put device driver specific defines into a separate header + * file for each driver. + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> + * + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> + * and Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H +#ifndef __ASM_ARCH_OMAP_HARDWARE_H +#define __ASM_ARCH_OMAP_HARDWARE_H +#include <asm/sizes.h> #ifndef __ASSEMBLER__ +#include <asm/types.h> +#include <plat/cpu.h> + /* * NOTE: Please use ioremap + __raw_read/write where possible instead of these */ @@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void) ? 0 : OMAP_CS3_PHYS; } +#endif /* ifndef __ASSEMBLER__ */ + +#include <plat/serial.h> + +/* + * --------------------------------------------------------------------------- + * Common definitions for all OMAP processors + * NOTE: Put all processor or board specific parts to the special header + * files. + * --------------------------------------------------------------------------- + */ + +/* + * ---------------------------------------------------------------------------- + * Timers + * ---------------------------------------------------------------------------- + */ +#define OMAP_MPU_TIMER1_BASE (0xfffec500) +#define OMAP_MPU_TIMER2_BASE (0xfffec600) +#define OMAP_MPU_TIMER3_BASE (0xfffec700) +#define MPU_TIMER_FREE (1 << 6) +#define MPU_TIMER_CLOCK_ENABLE (1 << 5) +#define MPU_TIMER_AR (1 << 1) +#define MPU_TIMER_ST (1 << 0) + +/* + * ---------------------------------------------------------------------------- + * Clocks + * ---------------------------------------------------------------------------- + */ +#define CLKGEN_REG_BASE (0xfffece00) +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) + +#define CK_RATEF 1 +#define CK_IDLEF 2 +#define CK_ENABLEF 4 +#define CK_SELECTF 8 +#define SETARM_IDLE_SHIFT + +/* DPLL control registers */ +#define DPLL_CTL (0xfffecf00) + +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) + +/* + * --------------------------------------------------------------------------- + * UPLD + * --------------------------------------------------------------------------- + */ +#define ULPD_REG_BASE (0xfffe0800) +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) +# define SOFT_UDC_REQ (1 << 4) +# define SOFT_USB_CLK_REQ (1 << 3) +# define SOFT_DPLL_REQ (1 << 0) +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) +# define DIS_MMC2_DPLL_REQ (1 << 11) +# define DIS_MMC1_DPLL_REQ (1 << 10) +# define DIS_UART3_DPLL_REQ (1 << 9) +# define DIS_UART2_DPLL_REQ (1 << 8) +# define DIS_UART1_DPLL_REQ (1 << 7) +# define DIS_USB_HOST_DPLL_REQ (1 << 6) +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) + +/* + * --------------------------------------------------------------------------- + * Watchdog timer + * --------------------------------------------------------------------------- + */ + +/* Watchdog timer within the OMAP3.2 gigacell */ +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) + +/* + * --------------------------------------------------------------------------- + * Interrupts + * --------------------------------------------------------------------------- + */ +#ifdef CONFIG_ARCH_OMAP1 + +/* + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c + * or something similar.. -- PFM. + */ + +#define OMAP_IH1_BASE 0xfffecb00 +#define OMAP_IH2_BASE 0xfffe0000 + +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) + +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) + +#define IRQ_ITR_REG_OFFSET 0x00 +#define IRQ_MIR_REG_OFFSET 0x04 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14 +#define IRQ_CONTROL_REG_OFFSET 0x18 +#define IRQ_ISR_REG_OFFSET 0x9c +#define IRQ_ILR0_REG_OFFSET 0x1c +#define IRQ_GMR_REG_OFFSET 0xa0 + #endif -#endif -#include <plat/hardware.h> +/* + * ---------------------------------------------------------------------------- + * System control registers + * ---------------------------------------------------------------------------- + */ +#define MOD_CONF_CTRL_0 0xfffe1080 +#define MOD_CONF_CTRL_1 0xfffe1110 + +/* + * ---------------------------------------------------------------------------- + * Pin multiplexing registers + * ---------------------------------------------------------------------------- + */ +#define FUNC_MUX_CTRL_0 0xfffe1000 +#define FUNC_MUX_CTRL_1 0xfffe1004 +#define FUNC_MUX_CTRL_2 0xfffe1008 +#define COMP_MODE_CTRL_0 0xfffe100c +#define FUNC_MUX_CTRL_3 0xfffe1010 +#define FUNC_MUX_CTRL_4 0xfffe1014 +#define FUNC_MUX_CTRL_5 0xfffe1018 +#define FUNC_MUX_CTRL_6 0xfffe101C +#define FUNC_MUX_CTRL_7 0xfffe1020 +#define FUNC_MUX_CTRL_8 0xfffe1024 +#define FUNC_MUX_CTRL_9 0xfffe1028 +#define FUNC_MUX_CTRL_A 0xfffe102C +#define FUNC_MUX_CTRL_B 0xfffe1030 +#define FUNC_MUX_CTRL_C 0xfffe1034 +#define FUNC_MUX_CTRL_D 0xfffe1038 +#define PULL_DWN_CTRL_0 0xfffe1040 +#define PULL_DWN_CTRL_1 0xfffe1044 +#define PULL_DWN_CTRL_2 0xfffe1048 +#define PULL_DWN_CTRL_3 0xfffe104c +#define PULL_DWN_CTRL_4 0xfffe10ac + +/* OMAP-1610 specific multiplexing registers */ +#define FUNC_MUX_CTRL_E 0xfffe1090 +#define FUNC_MUX_CTRL_F 0xfffe1094 +#define FUNC_MUX_CTRL_10 0xfffe1098 +#define FUNC_MUX_CTRL_11 0xfffe109c +#define FUNC_MUX_CTRL_12 0xfffe10a0 +#define PU_PD_SEL_0 0xfffe10b4 +#define PU_PD_SEL_1 0xfffe10b8 +#define PU_PD_SEL_2 0xfffe10bc +#define PU_PD_SEL_3 0xfffe10c0 +#define PU_PD_SEL_4 0xfffe10c4 + +/* Timer32K for 1610 and 1710*/ +#define OMAP_TIMER32K_BASE 0xFFFBC400 + +/* + * --------------------------------------------------------------------------- + * TIPB bus interface + * --------------------------------------------------------------------------- + */ +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) + +/* + * ---------------------------------------------------------------------------- + * MPUI interface + * ---------------------------------------------------------------------------- + */ +#define MPUI_BASE (0xfffec900) +#define MPUI_CTRL (MPUI_BASE + 0x0) +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) +#define MPUI_STATUS_REG (MPUI_BASE + 0x10) +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) + +/* + * ---------------------------------------------------------------------------- + * LED Pulse Generator + * ---------------------------------------------------------------------------- + */ +#define OMAP_LPG1_BASE 0xfffbd000 +#define OMAP_LPG2_BASE 0xfffbd800 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) + +/* + * ---------------------------------------------------------------------------- + * Pulse-Width Light + * ---------------------------------------------------------------------------- + */ +#define OMAP_PWL_BASE 0xfffb5800 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) + +/* + * --------------------------------------------------------------------------- + * Processor specific defines + * --------------------------------------------------------------------------- + */ + +#include "omap7xx.h" +#include "omap1510.h" +#include "omap16xx.h" + +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/mach-omap1/include/mach/irda.h index 40f60339d1c6..40f60339d1c6 100644 --- a/arch/arm/plat-omap/include/plat/irda.h +++ b/arch/arm/mach-omap1/include/mach/irda.h diff --git a/arch/arm/mach-omap1/include/mach/irqs.h b/arch/arm/mach-omap1/include/mach/irqs.h index 9292fdc1cb0b..729992d7d26a 100644 --- a/arch/arm/mach-omap1/include/mach/irqs.h +++ b/arch/arm/mach-omap1/include/mach/irqs.h @@ -1,5 +1,268 @@ /* - * arch/arm/mach-omap1/include/mach/irqs.h + * arch/arm/plat-omap/include/mach/irqs.h + * + * Copyright (C) Greg Lonnon 2001 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 + * are different. */ -#include <plat/irqs.h> +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H +#define __ASM_ARCH_OMAP15XX_IRQS_H + +/* + * IRQ numbers for interrupt handler 1 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + * + */ +#define INT_CAMERA 1 +#define INT_FIQ 3 +#define INT_RTDX 6 +#define INT_DSP_MMU_ABORT 7 +#define INT_HOST 8 +#define INT_ABORT 9 +#define INT_BRIDGE_PRIV 13 +#define INT_GPIO_BANK1 14 +#define INT_UART3 15 +#define INT_TIMER3 16 +#define INT_DMA_CH0_6 19 +#define INT_DMA_CH1_7 20 +#define INT_DMA_CH2_8 21 +#define INT_DMA_CH3 22 +#define INT_DMA_CH4 23 +#define INT_DMA_CH5 24 +#define INT_TIMER1 26 +#define INT_WD_TIMER 27 +#define INT_BRIDGE_PUB 28 +#define INT_TIMER2 30 +#define INT_LCD_CTRL 31 + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1510_IH2_IRQ 0 +#define INT_1510_RES2 2 +#define INT_1510_SPI_TX 4 +#define INT_1510_SPI_RX 5 +#define INT_1510_DSP_MAILBOX1 10 +#define INT_1510_DSP_MAILBOX2 11 +#define INT_1510_RES12 12 +#define INT_1510_LB_MMU 17 +#define INT_1510_RES18 18 +#define INT_1510_LOCAL_BUS 29 + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 1 + */ +#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ +#define INT_1610_IH2_FIQ 2 +#define INT_1610_McBSP2_TX 4 +#define INT_1610_McBSP2_RX 5 +#define INT_1610_DSP_MAILBOX1 10 +#define INT_1610_DSP_MAILBOX2 11 +#define INT_1610_LCD_LINE 12 +#define INT_1610_GPTIMER1 17 +#define INT_1610_GPTIMER2 18 +#define INT_1610_SSR_FIFO_0 29 + +/* + * OMAP-7xx specific IRQ numbers for interrupt handler 1 + */ +#define INT_7XX_IH2_FIQ 0 +#define INT_7XX_IH2_IRQ 1 +#define INT_7XX_USB_NON_ISO 2 +#define INT_7XX_USB_ISO 3 +#define INT_7XX_ICR 4 +#define INT_7XX_EAC 5 +#define INT_7XX_GPIO_BANK1 6 +#define INT_7XX_GPIO_BANK2 7 +#define INT_7XX_GPIO_BANK3 8 +#define INT_7XX_McBSP2TX 10 +#define INT_7XX_McBSP2RX 11 +#define INT_7XX_McBSP2RX_OVF 12 +#define INT_7XX_LCD_LINE 14 +#define INT_7XX_GSM_PROTECT 15 +#define INT_7XX_TIMER3 16 +#define INT_7XX_GPIO_BANK5 17 +#define INT_7XX_GPIO_BANK6 18 +#define INT_7XX_SPGIO_WR 29 + +/* + * IRQ numbers for interrupt handler 2 + * + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below + */ +#define IH2_BASE 32 + +#define INT_KEYBOARD (1 + IH2_BASE) +#define INT_uWireTX (2 + IH2_BASE) +#define INT_uWireRX (3 + IH2_BASE) +#define INT_I2C (4 + IH2_BASE) +#define INT_MPUIO (5 + IH2_BASE) +#define INT_USB_HHC_1 (6 + IH2_BASE) +#define INT_McBSP3TX (10 + IH2_BASE) +#define INT_McBSP3RX (11 + IH2_BASE) +#define INT_McBSP1TX (12 + IH2_BASE) +#define INT_McBSP1RX (13 + IH2_BASE) +#define INT_UART1 (14 + IH2_BASE) +#define INT_UART2 (15 + IH2_BASE) +#define INT_BT_MCSI1TX (16 + IH2_BASE) +#define INT_BT_MCSI1RX (17 + IH2_BASE) +#define INT_SOSSI_MATCH (19 + IH2_BASE) +#define INT_USB_W2FC (20 + IH2_BASE) +#define INT_1WIRE (21 + IH2_BASE) +#define INT_OS_TIMER (22 + IH2_BASE) +#define INT_MMC (23 + IH2_BASE) +#define INT_GAUGE_32K (24 + IH2_BASE) +#define INT_RTC_TIMER (25 + IH2_BASE) +#define INT_RTC_ALARM (26 + IH2_BASE) +#define INT_MEM_STICK (27 + IH2_BASE) + +/* + * OMAP-1510 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1510_DSP_MMU (28 + IH2_BASE) +#define INT_1510_COM_SPI_RO (31 + IH2_BASE) + +/* + * OMAP-1610 specific IRQ numbers for interrupt handler 2 + */ +#define INT_1610_FAC (0 + IH2_BASE) +#define INT_1610_USB_HHC_2 (7 + IH2_BASE) +#define INT_1610_USB_OTG (8 + IH2_BASE) +#define INT_1610_SoSSI (9 + IH2_BASE) +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) +#define INT_1610_DSP_MMU (28 + IH2_BASE) +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) +#define INT_1610_STI (32 + IH2_BASE) +#define INT_1610_STI_WAKEUP (33 + IH2_BASE) +#define INT_1610_GPTIMER3 (34 + IH2_BASE) +#define INT_1610_GPTIMER4 (35 + IH2_BASE) +#define INT_1610_GPTIMER5 (36 + IH2_BASE) +#define INT_1610_GPTIMER6 (37 + IH2_BASE) +#define INT_1610_GPTIMER7 (38 + IH2_BASE) +#define INT_1610_GPTIMER8 (39 + IH2_BASE) +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) +#define INT_1610_MMC2 (42 + IH2_BASE) +#define INT_1610_CF (43 + IH2_BASE) +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) +#define INT_1610_SPI (49 + IH2_BASE) +#define INT_1610_DMA_CH6 (53 + IH2_BASE) +#define INT_1610_DMA_CH7 (54 + IH2_BASE) +#define INT_1610_DMA_CH8 (55 + IH2_BASE) +#define INT_1610_DMA_CH9 (56 + IH2_BASE) +#define INT_1610_DMA_CH10 (57 + IH2_BASE) +#define INT_1610_DMA_CH11 (58 + IH2_BASE) +#define INT_1610_DMA_CH12 (59 + IH2_BASE) +#define INT_1610_DMA_CH13 (60 + IH2_BASE) +#define INT_1610_DMA_CH14 (61 + IH2_BASE) +#define INT_1610_DMA_CH15 (62 + IH2_BASE) +#define INT_1610_NAND (63 + IH2_BASE) +#define INT_1610_SHA1MD5 (91 + IH2_BASE) + +/* + * OMAP-7xx specific IRQ numbers for interrupt handler 2 + */ +#define INT_7XX_HW_ERRORS (0 + IH2_BASE) +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) +#define INT_7XX_CFCD (2 + IH2_BASE) +#define INT_7XX_CFIREQ (3 + IH2_BASE) +#define INT_7XX_I2C (4 + IH2_BASE) +#define INT_7XX_PCC (5 + IH2_BASE) +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) +#define INT_7XX_SYREN_SPI (8 + IH2_BASE) +#define INT_7XX_VLYNQ (9 + IH2_BASE) +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) +#define INT_7XX_McBSP1TX (11 + IH2_BASE) +#define INT_7XX_McBSP1RX (12 + IH2_BASE) +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) +#define INT_7XX_MCSI (16 + IH2_BASE) +#define INT_7XX_uWireTX (17 + IH2_BASE) +#define INT_7XX_uWireRX (18 + IH2_BASE) +#define INT_7XX_SMC_CD (19 + IH2_BASE) +#define INT_7XX_SMC_IREQ (20 + IH2_BASE) +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) +#define INT_7XX_TIMER32K (22 + IH2_BASE) +#define INT_7XX_MMC_SDIO (23 + IH2_BASE) +#define INT_7XX_UPLD (24 + IH2_BASE) +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) +#define INT_7XX_USB_GENI (29 + IH2_BASE) +#define INT_7XX_USB_OTG (30 + IH2_BASE) +#define INT_7XX_CAMERA_IF (31 + IH2_BASE) +#define INT_7XX_RNG (32 + IH2_BASE) +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) +#define INT_7XX_RNG_IDLE (38 + IH2_BASE) +#define INT_7XX_MPUIO (39 + IH2_BASE) +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) +#define INT_7XX_DMA_CH6 (53 + IH2_BASE) +#define INT_7XX_DMA_CH7 (54 + IH2_BASE) +#define INT_7XX_DMA_CH8 (55 + IH2_BASE) +#define INT_7XX_DMA_CH9 (56 + IH2_BASE) +#define INT_7XX_DMA_CH10 (57 + IH2_BASE) +#define INT_7XX_DMA_CH11 (58 + IH2_BASE) +#define INT_7XX_DMA_CH12 (59 + IH2_BASE) +#define INT_7XX_DMA_CH13 (60 + IH2_BASE) +#define INT_7XX_DMA_CH14 (61 + IH2_BASE) +#define INT_7XX_DMA_CH15 (62 + IH2_BASE) +#define INT_7XX_NAND (63 + IH2_BASE) + +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and + * 16 MPUIO lines */ +#define OMAP_MAX_GPIO_LINES 192 +#define IH_GPIO_BASE (128 + IH2_BASE) +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) + +/* External FPGA handles interrupts on Innovator boards */ +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) +#ifdef CONFIG_MACH_OMAP_INNOVATOR +#define OMAP_FPGA_NR_IRQS 24 +#else +#define OMAP_FPGA_NR_IRQS 0 +#endif +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) + +#define NR_IRQS OMAP_FPGA_IRQ_END + +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) + +#include <mach/hardware.h> + +#ifdef CONFIG_FIQ +#define FIQ_START 1024 +#endif + +#endif diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/mach-omap1/include/mach/mux.h index 323948959200..323948959200 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/mach-omap1/include/mach/mux.h diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h index d24004668138..8fe05d6137c0 100644 --- a/arch/arm/plat-omap/include/plat/omap1510.h +++ b/arch/arm/mach-omap1/include/mach/omap1510.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-omap/include/mach/omap1510.h - * +/* * Hardware definitions for TI OMAP1510 processor. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/mach-omap1/include/mach/omap16xx.h index e69e1d857b45..cd1c724869c7 100644 --- a/arch/arm/plat-omap/include/plat/omap16xx.h +++ b/arch/arm/mach-omap1/include/mach/omap16xx.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-omap/include/mach/omap16xx.h - * +/* * Hardware definitions for TI OMAP1610/5912/1710 processors. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/mach-omap1/include/mach/omap7xx.h index 48e4757e1e30..63da994bc609 100644 --- a/arch/arm/plat-omap/include/plat/omap7xx.h +++ b/arch/arm/mach-omap1/include/mach/omap7xx.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-omap/include/mach/omap7xx.h - * +/* * Hardware definitions for TI OMAP7XX processor. * * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> diff --git a/arch/arm/mach-omap1/include/mach/smp.h b/arch/arm/mach-omap1/include/mach/smp.h deleted file mode 100644 index 80a371c06e59..000000000000 --- a/arch/arm/mach-omap1/include/mach/smp.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-omap1/include/mach/smp.h - */ - -#include <plat/smp.h> diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 6c95a59f0f16..6a5baab1f4cb 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -16,7 +16,7 @@ #include <asm/tlb.h> #include <asm/mach/map.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/tc.h> #include <plat/dma.h> diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index 5769c71815b2..ed42628611bc 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c @@ -113,8 +113,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); void omap_set_lcd_dma_b1_vxres(unsigned long vxres) { if (cpu_is_omap15xx()) { - printk(KERN_ERR "DMA virtual resolution is not supported " - "in 1510 mode\n"); + pr_err("DMA virtual resolution is not supported in 1510 mode\n"); BUG(); } lcd_dma.vxres = vxres; @@ -437,8 +436,7 @@ static int __init omap_init_lcd_dma(void) r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL); if (r != 0) - printk(KERN_ERR "unable to request IRQ for LCD DMA " - "(error %d)\n", r); + pr_err("unable to request IRQ for LCD DMA (error %d)\n", r); return r; } diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index adf00975b9bb..bdc2e7541adb 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -20,9 +20,9 @@ #include <linux/slab.h> #include <plat/dma.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/cpu.h> -#include <plat/mcbsp.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index e9cc52d4cb28..667ce5027f63 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -29,7 +29,7 @@ #include <mach/hardware.h> -#include <plat/mux.h> +#include <mach/mux.h> #ifdef CONFIG_OMAP_MUX @@ -451,6 +451,56 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) #endif } +static struct omap_mux_cfg *mux_cfg; + +int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) +{ + if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 + || !arch_mux_cfg->cfg_reg) { + printk(KERN_ERR "Invalid pin table\n"); + return -EINVAL; + } + + mux_cfg = arch_mux_cfg; + + return 0; +} + +/* + * Sets the Omap MUX and PULL_DWN registers based on the table + */ +int __init_or_module omap_cfg_reg(const unsigned long index) +{ + struct pin_config *reg; + + if (!cpu_class_is_omap1()) { + printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", + index); + WARN_ON(1); + return -EINVAL; + } + + if (mux_cfg == NULL) { + printk(KERN_ERR "Pin mux table not initialized\n"); + return -ENODEV; + } + + if (index >= mux_cfg->size) { + printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", + index, mux_cfg->size); + dump_stack(); + return -ENODEV; + } + + reg = &mux_cfg->pins[index]; + + if (!mux_cfg->cfg_reg) + return -ENODEV; + + return mux_cfg->cfg_reg(reg); +} +EXPORT_SYMBOL(omap_cfg_reg); + int __init omap1_mux_init(void) { if (cpu_is_omap7xx()) { @@ -468,4 +518,8 @@ int __init omap1_mux_init(void) return omap_mux_register(&arch_mux_cfg); } -#endif +#else +#define omap_mux_init() do {} while(0) +#define omap_cfg_reg(x) do {} while(0) +#endif /* CONFIG_OMAP_MUX */ + diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index b2560d32b3a0..47ec16155483 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -53,7 +53,7 @@ #include <plat/clock.h> #include <plat/sram.h> #include <plat/tc.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/dma.h> #include <plat/dmtimer.h> diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 6809c9e56c93..b9d6834af835 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -22,8 +22,7 @@ #include <asm/mach-types.h> -#include <plat/board.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <plat/fpga.h> #include "pm.h" diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 65f88176fba8..84267edd9421 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -26,7 +26,7 @@ #include <asm/irq.h> -#include <plat/mux.h> +#include <mach/mux.h> #include <mach/usb.h> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 728b05eb2964..a6219eaf1f68 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 select HIGHMEM + select PINCTRL help Compile a kernel suitable for booting most boards config SOC_HAS_OMAP2_SDRC bool "OMAP2 SDRAM Controller support" +config SOC_HAS_REALTIME_COUNTER + bool "Real time free running counter" + config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS @@ -72,6 +76,8 @@ config SOC_OMAP5 select ARM_GIC select HAVE_SMP select ARM_CPU_SUSPEND if PM + select SOC_HAS_REALTIME_COUNTER + select ARM_ARCH_TIMER comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -234,10 +240,11 @@ config MACH_OMAP3_PANDORA select OMAP_PACKAGE_CBB select REGULATOR_FIXED_VOLTAGE if REGULATOR -config MACH_OMAP3_TOUCHBOOK +config MACH_TOUCHBOOK bool "OMAP3 Touch Book" depends on ARCH_OMAP3 default y + select OMAP_PACKAGE_CBB config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 7fed980acb93..7d6abda3b74e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,36 +4,30 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o -omap-2-3-common = irq.o -hwmod-common = omap_hwmod.o \ - omap_hwmod_common_data.o -clock-common = clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o -secure-common = omap-smc.o omap-secure.o +# INTCPS IP block support - XXX should be moved to drivers/ +obj-$(CONFIG_ARCH_OMAP2) += irq.o +obj-$(CONFIG_ARCH_OMAP3) += irq.o +obj-$(CONFIG_SOC_AM33XX) += irq.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) -obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) +# Secure monitor API support +obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o +obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o +obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o endif -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -omap-4-5-common = omap4-common.o omap-wakeupgen.o \ - sleep44xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) -obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) +obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o +obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) @@ -68,15 +63,15 @@ endif # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o +obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) @@ -88,92 +83,76 @@ endif endif ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o endif # PRCM -omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ - prcm_mpu44xx.o prminst44xx.o \ - vc44xx_data.o vp44xx_data.o -obj-y += prm_common.o -obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-y += prcm.o prm_common.o +obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o +obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ + prcm_mpu44xx.o prminst44xx.o \ + vc44xx_data.o vp44xx_data.o \ + prm44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains -voltagedomain-common := voltage.o vc.o vp.o -obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) +obj-y += voltage.o vc.o vp.o obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework -powerdomain-common += powerdomain.o powerdomain-common.o -obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) +obj-y += powerdomain.o powerdomain-common.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control -clockdomain-common += clockdomain.o -obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) +obj-y += clockdomain.o obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework -obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o +obj-y += clock.o clock_common_data.o \ + clkt_dpll.o clkt_clksel.o +obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) @@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data +obj-y += omap_hwmod_common_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -194,6 +174,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o +obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals @@ -224,10 +205,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o @@ -250,7 +231,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o -obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o +obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot index b03e562acc60..be0fe9226d67 100644 --- a/arch/arm/mach-omap2/Makefile.boot +++ b/arch/arm/mach-omap2/Makefile.boot @@ -1,3 +1,9 @@ zreladdr-y += 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 + +dtb-$(CONFIG_SOC_OMAP2420) += omap2420-h4.dtb +dtb-$(CONFIG_ARCH_OMAP3) += omap3-beagle-xm.dtb omap3-evm.dtb omap3-tobi.dtb +dtb-$(CONFIG_ARCH_OMAP4) += omap4-panda.dtb omap4-pandaES.dtb +dtb-$(CONFIG_ARCH_OMAP4) += omap4-var_som.dtb omap4-sdp.dtb +dtb-$(CONFIG_SOC_OMAP5) += omap5-evm.dtb diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 06c19bb7bca6..06c19bb7bca6 100644 --- a/arch/arm/plat-omap/include/plat/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 2c90ac686686..d0c54c573d34 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -19,7 +19,7 @@ #include <linux/davinci_emac.h> #include <asm/system.h> #include <plat/omap_device.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include "control.h" #include "am35xx-emac.h" diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/am35xx.h index 95594495fcf6..95594495fcf6 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/am35xx.h diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 9511584fdc4f..95b384d54f8a 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -33,11 +33,10 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <plat/usb.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> @@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = { }; static struct twl4030_gpio_platform_data sdp2430_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, }; static struct twl4030_platform_data sdp2430_twldata = { @@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void) sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ, + omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, &sdp2430_twldata); return 0; } diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index a98c688058a9..96cd3693e1ae 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -24,14 +24,12 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/mmc/host.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include <plat/usb.h> #include "common.h" #include <plat/dma.h> @@ -39,7 +37,7 @@ #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include "board-flash.h" #include "mux.h" @@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = { .default_device = &sdp3430_lcd_device, }; -static struct omap_board_config_kernel sdp3430_config[] __initdata = { -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data sdp3430_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | BIT(16) | BIT(17), .setup = sdp3430_twl_gpio_setup, @@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void) int gpio_pendown; omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_board_config = sdp3430_config; - omap_board_config_size = ARRAY_SIZE(sdp3430_config); omap_hsmmc_init(mmc); omap3430_i2c_init(); omap_display_init(&sdp3430_dss_data); diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 2dc9ba523c7a..fc224ad86747 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -17,8 +17,7 @@ #include <asm/mach/arch.h> #include "common.h" -#include <plat/board.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" #include <plat/usb.h> #include <mach/board-zoom.h> @@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -static struct omap_board_config_kernel sdp_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - omap_board_config = sdp_config; - omap_board_config_size = ARRAY_SIZE(sdp_config); zoom_peripherals_init(); omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index ad8a7d94afcd..749ce9634e8e 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -28,23 +28,22 @@ #include <linux/leds_pwm.h> #include <linux/platform_data/omap4-keypad.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> -#include <plat/omap4-keypad.h> +#include "omap4-keypad.h" #include <video/omapdss.h> #include <video/omap-panel-nokia-dsi.h> #include <video/omap-panel-picodlp.h> #include <linux/wl12xx.h> #include <linux/platform_data/omap-abe-twl6040.h> +#include "soc.h" #include "mux.h" #include "hsmmc.h" #include "control.h" @@ -544,7 +543,14 @@ static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .vibra = &twl6040_vibra, .audpwron_gpio = 127, - .irq_base = TWL6040_CODEC_IRQ_BASE, +}; + +static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = { + { + I2C_BOARD_INFO("twl6040", 0x4b), + .irq = 119 + OMAP44XX_IRQ_GIC_START, + .platform_data = &twl6040_data, + }, }; static struct twl4030_platform_data sdp4430_twldata = { @@ -580,8 +586,8 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_CLK32KG | TWL_COMMON_REGULATOR_V1V8 | TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &sdp4430_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo, + ARRAY_SIZE(sdp4430_i2c_1_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 92432c28673d..318feadb1d6e 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -21,12 +21,10 @@ #include <linux/init.h> #include <linux/gpio.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> @@ -37,11 +35,6 @@ #define GPIO_USB_POWER 35 #define GPIO_USB_NRESET 38 - -/* Board initialization */ -static struct omap_board_config_kernel am3517_crane_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { { .reg_offset = OMAP_MUX_TERMINATOR }, @@ -67,9 +60,6 @@ static void __init am3517_crane_init(void) omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = am3517_crane_config; - omap_board_config_size = ARRAY_SIZE(am3517_crane_config); - /* Configure GPIO for EHCI port */ if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 18f601096ce1..0d99c9110d01 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -25,14 +25,13 @@ #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> #include <linux/mmc/host.h> +#include <linux/platform_data/gpio-omap.h> -#include <mach/hardware.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <video/omapdss.h> @@ -296,8 +295,7 @@ static struct resource am3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; @@ -324,9 +322,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) platform_device_register(&am3517_hecc_device); } -static struct omap_board_config_kernel am3517_evm_config[] __initdata = { -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -346,8 +341,6 @@ static struct omap2_hsmmc_info mmc[] = { static void __init am3517_evm_init(void) { - omap_board_config = am3517_evm_config; - omap_board_config_size = ARRAY_SIZE(am3517_evm_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index e5fa46bfde2f..3e2d76f05af4 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -29,13 +29,11 @@ #include <linux/smc91x.h> #include <linux/gpio.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <plat/led.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 97d719047af3..8ffd612c5e07 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -23,6 +23,7 @@ #include <linux/input/matrix_keypad.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/i2c/at24.h> #include <linux/i2c/twl.h> @@ -37,15 +38,14 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/gpmc.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <mach/hardware.h> @@ -64,7 +64,7 @@ #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = { .id = 0, @@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, } static struct twl4030_gpio_platform_data cm_t35_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = cm_t35_twl_gpio_setup, }; @@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {} static inline void cm_t3730_init_mux(void) {} #endif -static struct omap_board_config_kernel cm_t35_config[] __initdata = { -}; - static void __init cm_t3x_common_init(void) { - omap_board_config = cm_t35_config; - omap_board_config_size = ARRAY_SIZE(cm_t35_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index a33ad4641d9a..59c0a45f75b0 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -38,13 +38,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/gpmc.h> -#include <mach/am35xx.h> +#include "am35xx.h" #include "mux.h" #include "control.h" @@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; @@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void) static inline void cm_t3517_init_nand(void) {} #endif -static struct omap_board_config_kernel cm_t3517_config[] __initdata = { -}; - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* GPIO186 - Green LED */ @@ -285,8 +280,6 @@ static void __init cm_t3517_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = cm_t3517_config; - omap_board_config_size = ARRAY_SIZE(cm_t3517_config); cm_t3517_init_leds(); cm_t3517_init_nand(); cm_t3517_init_rtc(); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 6567c1cd5572..7bb8056d4388 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -32,31 +32,27 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> - -#include <mach/hardware.h> -#include <mach/id.h> +#include "id.h" #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/dm9000.h> #include <linux/interrupt.h> #include "sdram-micron-mt46h32m32lf-6.h" - #include "mux.h" #include "hsmmc.h" #include "common-board-devices.h" @@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data devkit8000_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pulldowns = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13) | BIT(15) | BIT(16) | BIT(17), diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 53c39d239d6e..0cabe61cd507 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -16,13 +16,14 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> #include <linux/io.h> -#include <plat/irqs.h> +#include <plat/cpu.h> #include <plat/gpmc.h> -#include <plat/nand.h> -#include <plat/onenand.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <plat/tc.h> +#include "common.h" #include "board-flash.h" #define REG_FPGA_REV 0x10 @@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.devsize = nand_type; board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; - board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 6f93a20536ea..2ea7c577b295 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -16,11 +16,9 @@ #include <linux/of_platform.h> #include <linux/irqdomain.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach/arch.h> -#include <plat/board.h> #include "common.h" #include "common-board-devices.h" diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index ace20482e3e1..f6c48dd764fe 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -27,20 +27,19 @@ #include <linux/io.h> #include <linux/input/matrix_keypad.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> -#include "common.h" #include <plat/menelaus.h> #include <plat/dma.h> #include <plat/gpmc.h> +#include "debug-devices.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> +#include "common.h" #include "mux.h" #include "control.h" diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 28214483aaba..fb8bd837dd13 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -29,13 +29,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <plat/usb.h> + #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> -#include <plat/onenand.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include "mux.h" #include "hsmmc.h" @@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {} #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .cs = IGEP2_SMSC911X_CS, @@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev, }; static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = igep_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index ef9e82977499..ee8c3cfb95b3 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -28,21 +28,17 @@ #include <linux/io.h> #include <linux/smsc911x.h> #include <linux/mmc/host.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> #include <mach/board-zoom.h> - -#include <asm/delay.h> #include <plat/usb.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> @@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) } static struct twl4030_gpio_platform_data ldp_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = ldp_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 677357ff61ac..d95f727ca39a 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,19 +20,16 @@ #include <linux/i2c.h> #include <linux/spi/spi.h> #include <linux/usb/musb.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <sound/tlv320aic3x.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <plat/board.h> #include "common.h" #include <plat/menelaus.h> -#include <mach/irqs.h> -#include <plat/mcspi.h> -#include <plat/onenand.h> #include <plat/mmc.h> -#include <plat/serial.h> #include "mux.h" @@ -553,8 +550,8 @@ static int n8x0_auto_sleep_regulators(void) ret = menelaus_set_regulator_sleep(1, val); if (ret < 0) { - printk(KERN_ERR "Could not set regulators to sleep on " - "menelaus: %u\n", ret); + pr_err("Could not set regulators to sleep on menelaus: %u\n", + ret); return ret; } return 0; @@ -566,8 +563,7 @@ static int n8x0_auto_voltage_scale(void) ret = menelaus_set_vcore_hw(1400, 1050); if (ret < 0) { - printk(KERN_ERR "Could not set VCORE voltage on " - "menelaus: %u\n", ret); + pr_err("Could not set VCORE voltage on menelaus: %u\n", ret); return ret; } return 0; @@ -600,7 +596,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { { I2C_BOARD_INFO("menelaus", 0x72), - .irq = INT_24XX_SYS_NIRQ, + .irq = 7 + OMAP_INTC_START, .platform_data = &n8x0_menelaus_platform_data, }, }; diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 6202fc76e490..68ff8d51973c 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,18 +33,16 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <plat/omap_device.h> @@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data beagle_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 0d362e9f9cb9..c64e565bdef5 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -32,6 +32,7 @@ #include <linux/spi/ads7846.h> #include <linux/i2c/twl.h> #include <linux/usb/otg.h> +#include <linux/usb/nop-usb-xceiv.h> #include <linux/smsc911x.h> #include <linux/wl12xx.h> @@ -40,16 +41,14 @@ #include <linux/mmc/host.h> #include <linux/export.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include <plat/usb.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include "common.h" -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> @@ -75,6 +74,18 @@ #define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 #define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 +/* + * OMAP35x EVM revision + * Run time detection of EVM revision is done by reading Ethernet + * PHY ID - + * GEN_1 = 0x01150000 + * GEN_2 = 0x92200000 + */ +enum { + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ +}; + static u8 omap3_evm_version; u8 get_omap3_evm_rev(void) @@ -108,7 +119,7 @@ static void __init omap3_evm_get_revision(void) } #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .cs = OMAP3EVM_SMSC911X_CS, @@ -377,9 +388,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3evm_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = omap3evm_twl_gpio_setup, }; @@ -526,9 +534,6 @@ static int __init omap3_evm_i2c_init(void) return 0; } -static struct omap_board_config_kernel omap3_evm_config[] __initdata = { -}; - static struct usbhs_omap_board_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -688,9 +693,6 @@ static void __init omap3_evm_init(void) obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; omap3_mux_init(obm, OMAP_PACKAGE_CBB); - omap_board_config = omap3_evm_config; - omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - omap_mux_init_gpio(63, OMAP_PIN_INPUT); omap_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index fca93d1afd43..7bd8253b5d1d 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -30,24 +30,21 @@ #include <linux/i2c/twl.h> #include <linux/mmc/host.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include "gpmc-smsc911x.h" +#include <plat/gpmc.h> +#include <plat/sdrc.h> +#include <plat/usb.h> + +#include "common.h" #include "mux.h" #include "hsmmc.h" #include "control.h" #include "common-board-devices.h" -#include <plat/mux.h> -#include <plat/board.h> -#include "common.h" -#include <plat/gpmc-smsc911x.h> -#include <plat/gpmc.h> -#include <plat/sdrc.h> -#include <plat/usb.h> - #define OMAP3LOGIC_SMSC911X_CS 1 #define OMAP3530_LV_SOM_MMC_GPIO_CD 110 @@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = { }; static struct twl4030_gpio_platform_data omap3logic_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 57aebee44fd0..00a1f4ae6e44 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -35,18 +35,16 @@ #include <linux/mmc/host.h> #include <linux/mmc/card.h> #include <linux/regulator/fixed.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" -#include <mach/hardware.h> -#include <plat/mcspi.h> #include <plat/usb.h> #include <video/omapdss.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = omap3pandora_twl_gpio_setup, }; diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index b318f5602e36..c7f3d026e6d4 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -28,23 +28,26 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> #include <linux/mmc/host.h> +#include <linux/input/matrix_keypad.h> +#include <linux/spi/spi.h> +#include <linux/interrupt.h> +#include <linux/smsc911x.h> +#include <linux/i2c/at24.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/interrupt.h> @@ -57,7 +60,7 @@ #include "common-board-devices.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #define OMAP3STALKER_ETHR_START 0x2c000000 #define OMAP3STALKER_ETHR_SIZE 1024 @@ -279,9 +282,6 @@ omap3stalker_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data omap3stalker_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = omap3stalker_twl_gpio_setup, }; @@ -362,9 +362,6 @@ static int __init omap3_stalker_i2c_init(void) #define OMAP3_STALKER_TS_GPIO 175 -static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { -}; - static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; @@ -399,8 +396,6 @@ static void __init omap3_stalker_init(void) { regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); - omap_board_config = omap3_stalker_config; - omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); omap_mux_init_gpio(23, OMAP_PIN_INPUT); omap_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 485d14d6a8cd..944ffc436577 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -29,7 +29,7 @@ #include <linux/mtd/nand.h> #include <linux/mmc/host.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -37,17 +37,15 @@ #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> #include <asm/system_info.h> -#include <plat/board.h> #include "common.h" #include <plat/gpmc.h> -#include <plat/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <plat/usb.h> #include "mux.h" @@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data touchbook_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .pullups = BIT(1), .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 70f6d1d25463..7b592d3d7797 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -32,19 +32,18 @@ #include <linux/wl12xx.h> #include <linux/platform_data/omap-abe-twl6040.h> -#include <mach/hardware.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <video/omapdss.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> #include <video/omap-panel-tfp410.h> +#include "soc.h" #include "hsmmc.h" #include "control.h" #include "mux.h" @@ -263,7 +262,14 @@ static struct twl6040_codec_data twl6040_codec = { static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .audpwron_gpio = 127, - .irq_base = TWL6040_CODEC_IRQ_BASE, +}; + +static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = { + { + I2C_BOARD_INFO("twl6040", 0x4b), + .irq = 119 + OMAP44XX_IRQ_GIC_START, + .platform_data = &twl6040_data, + }, }; /* Panda board uses the common PMIC configuration */ @@ -293,8 +299,8 @@ static int __init omap4_panda_i2c_init(void) TWL_COMMON_REGULATOR_CLK32KG | TWL_COMMON_REGULATOR_V1V8 | TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &omap4_panda_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo, + ARRAY_SIZE(panda_i2c_1_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); /* * Bus 3 is attached to the DVI port where devices like the pico DLP diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 779734d8ba37..2e7f24030fc9 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -37,21 +37,19 @@ #include <linux/mtd/partitions.h> #include <linux/mmc/host.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <plat/board.h> #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> -#include <mach/hardware.h> -#include <plat/nand.h> -#include <plat/mcspi.h> -#include <plat/mux.h> #include <plat/usb.h> #include "mux.h" @@ -116,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; } #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct omap_smsc911x_platform_data smsc911x_cfg = { .id = 0, @@ -399,9 +397,6 @@ static int overo_twl_gpio_setup(struct device *dev, } static struct twl4030_gpio_platform_data overo_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .use_leds = true, .setup = overo_twl_gpio_setup, }; @@ -522,8 +517,7 @@ static void __init overo_init(void) udelay(10); gpio_set_value(OVERO_GPIO_W2W_NRESET, 1); } else { - printk(KERN_ERR "could not obtain gpio for " - "OVERO_GPIO_W2W_NRESET\n"); + pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n"); } ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios)); @@ -542,8 +536,7 @@ static void __init overo_init(void) if (ret == 0) gpio_export(OVERO_GPIO_USBH_CPEN, 0); else - printk(KERN_ERR "could not obtain gpio for " - "OVERO_GPIO_USBH_CPEN\n"); + pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n"); } MACHINE_START(OVERO, "Gumstix Overo") diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 0ad1bb3bdb98..45997bfbcbd2 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -17,6 +17,7 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -26,7 +27,7 @@ #include <plat/usb.h> #include <plat/gpmc.h> #include "common.h" -#include <plat/onenand.h> +#include <plat/serial.h> #include "mux.h" #include "hsmmc.h" @@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = { /* TWL */ static struct twl4030_gpio_platform_data rm680_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pullups = BIT(0), .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), }; @@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = { static void __init rm680_i2c_init(void) { omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0); - omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data); + omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, NULL, 0); } diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index df2534de3361..3945c5017085 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -25,17 +25,17 @@ #include <linux/gpio_keys.h> #include <linux/mmc/host.h> #include <linux/power/isp1704_charger.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-onenand-omap2.h> + #include <asm/system_info.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/dma.h> #include <plat/gpmc.h> -#include <plat/onenand.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" -#include <mach/board-rx51.h> +#include "board-rx51.h" #include <sound/tlv320aic3x.h> #include <sound/tpa6130a2-plat.h> @@ -774,9 +774,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) } static struct twl4030_gpio_platform_data rx51_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(8) | BIT(9) | BIT(10) | BIT(11) @@ -1051,7 +1048,7 @@ static int __init rx51_i2c_init(void) rx51_twldata.vdac->constraints.apply_uV = true; rx51_twldata.vdac->constraints.name = "VDAC"; - omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); + omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata); omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE) diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 2c1289bd5e6a..c22e111bcd00 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -17,9 +17,9 @@ #include <asm/mach-types.h> #include <video/omapdss.h> #include <plat/vram.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/board-rx51.h> +#include "board-rx51.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 345dd931f76f..7bbb05d9689b 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -17,14 +17,12 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/platform_data/spi-omap2-mcspi.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/mcspi.h> -#include <plat/board.h> #include "common.h" #include <plat/dma.h> #include <plat/gpmc.h> diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/board-rx51.h index b76f49e7eed5..b76f49e7eed5 100644 --- a/arch/arm/mach-omap2/include/mach/board-rx51.h +++ b/arch/arm/mach-omap2/board-rx51.h diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index d4c8392cadb6..c4f8833b4c3c 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -15,13 +15,10 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/irqs.h> -#include <plat/board.h> #include "common.h" #include <plat/usb.h> @@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = { .power = 500, }; -static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = { -}; - static void __init ti81xx_evm_init(void) { omap_serial_init(); omap_sdrc_init(NULL, NULL); - omap_board_config = ti81xx_evm_config; - omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config); usb_musb_init(&musb_board_data); } diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index f64f44173061..afb2278a29f6 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -18,10 +18,13 @@ #include <linux/regulator/machine.h> #include <plat/gpmc.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" #include <mach/board-zoom.h> +#include "soc.h" +#include "common.h" + #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 @@ -81,8 +84,7 @@ static inline void __init zoom_init_quaduart(void) quart_cs = ZOOM_QUADUART_CS; if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed to request GPMC mem" - "for Quad UART(TL16CP754C)\n"); + pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n"); return; } @@ -104,8 +106,8 @@ static inline int omap_zoom_debugboard_detect(void) if (gpio_request_one(debug_board_detect, GPIOF_IN, "Zoom debug board detect") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for Zoom debug" - "board detect\n", debug_board_detect); + pr_err("Failed to request GPIO%d for Zoom debug board detect\n", + debug_board_detect); return 0; } diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index 28187f134fff..b940ab2259fb 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -14,10 +14,12 @@ #include <linux/gpio.h> #include <linux/i2c/twl.h> #include <linux/spi/spi.h> -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> #include <mach/board-zoom.h> +#include "common.h" + #define LCD_PANEL_RESET_GPIO_PROD 96 #define LCD_PANEL_RESET_GPIO_PILOT 55 #define LCD_PANEL_QVGA_GPIO 56 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index b797cb279618..6bcc107b9fc3 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -19,6 +19,7 @@ #include <linux/regulator/fixed.h> #include <linux/wl12xx.h> #include <linux/mmc/host.h> +#include <linux/platform_data/gpio-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -251,9 +252,6 @@ static void zoom2_set_hs_extmute(int mute) } static struct twl4030_gpio_platform_data zoom_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, - .irq_end = TWL4030_GPIO_IRQ_END, .setup = zoom_twl_gpio_setup, }; @@ -281,7 +279,7 @@ static int __init omap_i2c_init(void) codec_data->hs_extmute = 1; codec_data->set_hs_extmute = zoom2_set_hs_extmute; } - omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata); + omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, NULL, 0); return 0; diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 4e7e56142e6f..4994438e1f46 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -22,7 +22,6 @@ #include <asm/mach/arch.h> #include "common.h" -#include <plat/board.h> #include <plat/usb.h> #include <mach/board-zoom.h> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 3d9d746b221a..cabcfdba5246 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -33,11 +33,11 @@ #include <linux/cpufreq.h> #include <linux/slab.h> -#include <plat/cpu.h> #include <plat/clock.h> #include <plat/sram.h> #include <plat/sdrc.h> +#include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index d6e34dd9e7e7..298887b5bf66 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -92,15 +92,13 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); - pr_debug("clock: SDRC CS0 timing params used:" - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); if (sdrc_cs1) - pr_debug("clock: SDRC CS1 timing params used: " - " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", - sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, - sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); + pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); if (sdrc_cs1) omap3_configure_core_dpll( diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 04d551b1f7f7..19a980956d44 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ - WARN(1, "clock: Could not find parent clock %s in clksel array " - "of clock %s\n", src_clk->name, clk->name); + WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", + clk->name, src_clk->name); return NULL; } @@ -126,8 +126,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, if (max_div == 0) { /* This indicates an error in the clksel data */ - WARN(1, "clock: Could not find divisor for clock %s parent %s" - "\n", clk->name, src_clk->parent->name); + WARN(1, "clock: %s: could not find divisor for parent %s\n", + clk->name, src_clk->parent->name); return 0; } @@ -191,8 +191,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ - WARN(1, "clock: Could not find fieldval %d for clock %s parent " - "%s\n", field_val, clk->name, clk->parent->name); + WARN(1, "clock: %s: could not find fieldval %d parent %s\n", + clk->name, field_val, clk->parent->name); return 0; } @@ -230,8 +230,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) } if (!clkr->div) { - pr_err("clock: Could not find divisor %d for clock %s parent " - "%s\n", div, clk->name, clk->parent->name); + pr_err("clock: %s: could not find divisor %d parent %s\n", + clk->name, div, clk->parent->name); return ~0; } @@ -300,8 +300,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - pr_err("clock: clksel_rate table not sorted " - "for clock %s", clk->name); + pr_err("clock: %s: clksel_rate table not sorted", + clk->name); last_div = clkr->div; @@ -312,9 +312,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, } if (!clkr->div) { - pr_err("clock: Could not find divisor for target " - "rate %ld for clock %s parent %s\n", target_rate, - clk->name, clk->parent->name); + pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n", + clk->name, target_rate, clk->parent->name); return ~0; } @@ -359,8 +358,7 @@ void omap2_init_clksel_parent(struct clk *clk) if (clkr->val == r) { if (clk->parent != clks->parent) { - pr_debug("clock: inited %s parent " - "to %s (was %s)\n", + pr_debug("clock: %s: inited parent to %s (was %s)\n", clk->name, clks->parent->name, ((clk->parent) ? clk->parent->name : "NULL")); diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index cd7fd0f91149..83b658bf385a 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -22,8 +22,8 @@ #include <asm/div64.h> #include <plat/clock.h> -#include <plat/cpu.h> +#include "soc.h" #include "clock.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" @@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n) } if (fint < fint_min) { - pr_debug("rejecting n=%d due to Fint failure, " - "lowering max_divider\n", n); + pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", + n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; } else if (fint > fint_max) { - pr_debug("rejecting n=%d due to Fint failure, " - "boosting min_divider\n", n); + pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", + n); dd->min_divider = n; ret = DPLL_FINT_INVALID; } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && @@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) clk_reparent(clk, dd->clk_bypass); - } else if (cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) @@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return dd->clk_bypass->rate; - } else if (cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ea3f565ba1a4..e97f98ffe8b2 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -22,14 +22,16 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/bitops.h> -#include <trace/events/power.h> #include <asm/cpu.h> + #include <plat/clock.h> -#include "clockdomain.h" -#include <plat/cpu.h> #include <plat/prcm.h> +#include <trace/events/power.h> + +#include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" @@ -102,8 +104,8 @@ void omap2_init_clk_clkdm(struct clk *clk) clk->name, clk->clkdm_name); clk->clkdm = clkdm; } else { - pr_debug("clock: could not associate clk %s to " - "clkdm %s\n", clk->name, clk->clkdm_name); + pr_debug("clock: could not associate clk %s to clkdm %s\n", + clk->name, clk->clkdm_name); } } @@ -226,8 +228,7 @@ void omap2_dflt_clk_disable(struct clk *clk) * 'Independent' here refers to a clock which is not * controlled by its parent. */ - printk(KERN_ERR "clock: clk_disable called on independent " - "clock %s which has no enable_reg\n", clk->name); + pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); return; } @@ -270,8 +271,7 @@ const struct clkops clkops_omap2_dflt = { void omap2_clk_disable(struct clk *clk) { if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " - "already 0?", clk->name); + WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); return; } @@ -332,8 +332,8 @@ int omap2_clk_enable(struct clk *clk) if (clkdm_control && clk->clkdm) { ret = clkdm_clk_enable(clk->clkdm, clk); if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: " - "%d\n", clk->name, clk->clkdm->name, ret); + WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", + clk->name, clk->clkdm->name, ret); goto oce_err2; } } @@ -501,10 +501,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, hfclkin_rate = clk_get_rate(hfclkin_ck); - pr_info("Switched to new clocking rate (Crystal/Core/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (hfclkin_rate / 1000000), - ((hfclkin_rate / 100000) % 10), + pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 002745181ad6..12c178dbc9f5 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -18,9 +18,9 @@ #include <linux/clk.h> #include <linux/list.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index dfda9a3f2cb2..a8e326177466 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -21,9 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index cacabb070e22..7ea91398217a 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -17,9 +17,9 @@ #include <linux/clk.h> #include <linux/list.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" @@ -1856,6 +1856,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), CLK(NULL, "osc_ck", &osc_ck, CK_243X), + CLK("twl", "fck", &osc_ck, CK_243X), CLK(NULL, "sys_ck", &sys_ck, CK_243X), CLK(NULL, "alt_ck", &alt_ck, CK_243X), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 12500097378d..e92be1fc1a00 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -22,9 +22,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "cm.h" diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c index 25bbcc7ca4dc..2026311a4ff6 100644 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -18,8 +18,8 @@ #include <linux/list.h> #include <linux/clk.h> #include <plat/clkdev_omap.h> -#include <plat/am33xx.h> +#include "am33xx.h" #include "iomap.h" #include "control.h" #include "clock.h" @@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), @@ -1036,13 +1038,13 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), - CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX), - CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX), - CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX), - CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX), - CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX), - CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX), - CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX), + CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), + CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), + CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), + CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), + CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), + CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), + CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 794d82702c85..15cdc6471737 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -21,9 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock3xxx.h" #include "prm2xxx_3xxx.h" @@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) * on DPLL4. */ if (omap_rev() == OMAP3430_REV_ES1_0) { - pr_err("clock: DPLL4 cannot change rate due to " - "silicon 'Limitation 2.5' on 3430ES1.\n"); + pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 83bed9ad3017..700317a1bd16 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -21,9 +21,9 @@ #include <linux/list.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock3xxx.h" @@ -3226,6 +3226,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), + CLK("twl", "fck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index d7f55e43b761..500682c051c1 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -28,9 +28,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clkdev_omap.h> +#include "soc.h" #include "iomap.h" #include "clock.h" #include "clock44xx.h" diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 8664f5a8bfb6..a1555627ad97 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - pr_debug("clockdomain: adding %s sleepdep/wkdep for " - "clkdm %s\n", autodep->clkdm.ptr->name, - clkdm->name); + pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); @@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm) if (IS_ERR(autodep->clkdm.ptr)) continue; - pr_debug("clockdomain: removing %s sleepdep/wkdep for " - "clkdm %s\n", autodep->clkdm.ptr->name, - clkdm->name); + pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); @@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_inc_return(&cd->wkdep_usecount) == 1) { - pr_debug("clockdomain: hardware will wake up %s when %s wakes " - "up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2); } @@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_dec_return(&cd->wkdep_usecount) == 0) { - pr_debug("clockdomain: hardware will no longer wake up %s " - "after %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2); } @@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of " - "%s when %s wakes up\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); return ret; } @@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { - pr_debug("clockdomain: will prevent %s from sleeping if %s " - "is active\n", clkdm1->name, clkdm2->name); + pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2); } @@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { - pr_debug("clockdomain: will no longer prevent %s from " - "sleeping if %s is active\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2); } @@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) ret = -EINVAL; if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep " - "dependency affecting %s from %s\n", clkdm1->name, - clkdm2->name); + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); return ret; } @@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm) return -EINVAL; if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { - pr_debug("clockdomain: %s does not support forcing " - "sleep via software\n", clkdm->name); + pr_debug("clockdomain: %s does not support forcing sleep via software\n", + clkdm->name); return -EINVAL; } @@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm) return -EINVAL; if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { - pr_debug("clockdomain: %s does not support forcing " - "wakeup via software\n", clkdm->name); + pr_debug("clockdomain: %s does not support forcing wakeup via software\n", + clkdm->name); return -EINVAL; } @@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm) return; if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) { - pr_debug("clock: automatic idle transitions cannot be enabled " - "on clockdomain %s\n", clkdm->name); + pr_debug("clock: %s: automatic idle transitions cannot be enabled\n", + clkdm->name); return; } @@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm) return; if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) { - pr_debug("clockdomain: automatic idle transitions cannot be " - "disabled on %s\n", clkdm->name); + pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n", + clkdm->name); return; } @@ -927,7 +921,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); - pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); + pr_debug("clockdomain: %s: enabled\n", clkdm->name); return 0; } @@ -952,7 +946,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) pwrdm_state_switch(clkdm->pwrdm.ptr); spin_unlock_irqrestore(&clkdm->lock, flags); - pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); + pr_debug("clockdomain: %s: disabled\n", clkdm->name); return 0; } diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index a0d68dbecfa3..f99e65cfb862 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -241,6 +241,52 @@ static void omap3_clkdm_deny_idle(struct clockdomain *clkdm) _clkdm_del_autodeps(clkdm); } +static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + _disable_hwsup(clkdm); + _clkdm_add_autodeps(clkdm); + _enable_hwsup(clkdm); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap3_clkdm_wakeup(clkdm); + } + + return 0; +} + +static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + _disable_hwsup(clkdm); + _clkdm_del_autodeps(clkdm); + _enable_hwsup(clkdm); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) + omap3_clkdm_sleep(clkdm); + } + + return 0; +} + struct clkdm_ops omap2_clkdm_operations = { .clkdm_add_wkdep = omap2_clkdm_add_wkdep, .clkdm_del_wkdep = omap2_clkdm_del_wkdep, @@ -267,6 +313,6 @@ struct clkdm_ops omap3_clkdm_operations = { .clkdm_wakeup = omap3_clkdm_wakeup, .clkdm_allow_idle = omap3_clkdm_allow_idle, .clkdm_deny_idle = omap3_clkdm_deny_idle, - .clkdm_clk_enable = omap2_clkdm_clk_enable, - .clkdm_clk_disable = omap2_clkdm_clk_disable, + .clkdm_clk_enable = omap3xxx_clkdm_clk_enable, + .clkdm_clk_disable = omap3xxx_clkdm_clk_disable, }; diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 766338fe4d34..975f6bda0e0b 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -67,6 +67,7 @@ #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) /* CM_IDLEST_IVA2 */ +#define OMAP3430_ST_IVA2_SHIFT 0 #define OMAP3430_ST_IVA2_MASK (1 << 0) /* CM_IDLEST_PLL_IVA2 */ diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 389f9f8b570c..a911e76b4ecf 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -18,8 +18,7 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/hardware.h> - +#include "soc.h" #include "iomap.h" #include "common.h" #include "cm.h" diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index c1875862679f..48daac2581b4 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c @@ -24,9 +24,10 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> -#include <plat/mcspi.h> -#include <plat/nand.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/mtd-nand-omap2.h> +#include "common.h" #include "common-board-devices.h" #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ @@ -119,8 +120,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts, } if (nandcs > GPMC_CS_NUM) { - printk(KERN_INFO "NAND: Unable to find configuration " - "in GPMC\n "); + pr_info("NAND: Unable to find configuration in GPMC\n"); return; } diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 069f9725b1c3..17950c6e130b 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -17,11 +17,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> -#include <plat/board.h> -#include <plat/mux.h> #include <plat/clock.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 1f65b1871c23..da0f5c187353 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -26,11 +26,18 @@ #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H #ifndef __ASSEMBLER__ +#include <linux/irq.h> #include <linux/delay.h> #include <linux/i2c/twl.h> -#include <plat/common.h> + #include <asm/proc-fns.h> +#include <plat/cpu.h> +#include <plat/serial.h> +#include <plat/common.h> + +#define OMAP_INTC_START NR_IRQS + #ifdef CONFIG_SOC_OMAP2420 extern void omap242x_map_common_io(void); #else diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 3223b81e7532..d1ff8399a222 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -15,9 +15,9 @@ #include <linux/kernel.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/sdrc.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b8cdc8531b60..123186ac7d2e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -16,12 +16,12 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H #define __ARCH_ARM_MACH_OMAP2_CONTROL_H -#include <mach/ctrl_module_core_44xx.h> -#include <mach/ctrl_module_wkup_44xx.h> -#include <mach/ctrl_module_pad_core_44xx.h> -#include <mach/ctrl_module_pad_wkup_44xx.h> +#include "ctrl_module_core_44xx.h" +#include "ctrl_module_wkup_44xx.h" +#include "ctrl_module_pad_core_44xx.h" +#include "ctrl_module_pad_wkup_44xx.h" -#include <plat/am33xx.h> +#include "am33xx.h" #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f2a49a48ef59..bc2756959be5 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -28,7 +28,6 @@ #include <linux/cpu_pm.h> #include <plat/prcm.h> -#include <plat/irqs.h> #include "powerdomain.h" #include "clockdomain.h" diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h index 01970824e0e5..01970824e0e5 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_core_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h index c88420de1151..c88420de1151 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h index 17c9b37042c0..17c9b37042c0 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h index a0af9baec3f7..a0af9baec3f7 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h +++ b/arch/arm/mach-omap2/ctrl_module_wkup_44xx.h diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h new file mode 100644 index 000000000000..a4edbd2f7484 --- /dev/null +++ b/arch/arm/mach-omap2/debug-devices.h @@ -0,0 +1,9 @@ +#ifndef _OMAP_DEBUG_DEVICES_H +#define _OMAP_DEBUG_DEVICES_H + +#include <linux/types.h> + +/* for TI reference platforms sharing the same debug card */ +extern int debug_card_init(u32 addr, unsigned gpio); + +#endif diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c00c68961bb8..d092d2a89ee0 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -17,21 +17,20 @@ #include <linux/err.h> #include <linux/slab.h> #include <linux/of.h> +#include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> -#include <mach/hardware.h> -#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/map.h> -#include <asm/pmu.h> #include "iomap.h" -#include <plat/board.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> -#include <plat/omap4-keypad.h> +#include "omap4-keypad.h" +#include "soc.h" +#include "common.h" #include "mux.h" #include "control.h" #include "devices.h" @@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_24XX_CAM_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_34XX_CAM_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {} #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) -#include <plat/mcspi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused) { @@ -435,20 +434,18 @@ static inline void omap_init_mcspi(void) {} #endif static struct resource omap2_pmu_resource = { - .start = 3, - .end = 3, + .start = 3 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }; static struct resource omap3_pmu_resource = { - .start = INT_34XX_BENCH_MPU_EMUL, - .end = INT_34XX_BENCH_MPU_EMUL, + .start = 3 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }; static struct platform_device omap_pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = 1, }; @@ -475,7 +472,7 @@ static struct resource omap2_sham_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_24XX_SHA1MD5, + .start = 51 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, } }; @@ -493,7 +490,7 @@ static struct resource omap3_sham_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_34XX_SHA1MD52_IRQ, + .start = 49 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, { @@ -631,6 +628,10 @@ static inline void omap_init_vout(void) {} static int __init omap2_init_devices(void) { + /* Enable dummy states for those platforms without pinctrl support */ + if (!of_have_populated_dt()) + pinctrl_provide_dummies(); + /* * please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index b9c8d2f6a81f..27d79deb4ba2 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -28,9 +28,9 @@ #include <linux/bitops.h> #include <linux/clkdev.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * Set jitter correction. No jitter correction for OMAP4 and 3630 * since freqsel field is no longer present */ - if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; /* No freqsel on OMAP4 and OMAP3630 */ - if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); if (!freqsel) @@ -623,8 +623,11 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) while (pclk && !pclk->dpll_data) pclk = pclk->parent; - /* clk does not have a DPLL as a parent? */ - WARN_ON(!pclk); + /* clk does not have a DPLL as a parent? error in the clock data */ + if (!pclk) { + WARN_ON(1); + return 0; + } dd = pclk->dpll_data; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 9c6a296b3dc3..09d0ccccb861 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -15,9 +15,9 @@ #include <linux/io.h> #include <linux/bitops.h> -#include <plat/cpu.h> #include <plat/clock.h> +#include "soc.h" #include "clock.h" #include "clock44xx.h" #include "cm-regbits-44xx.h" diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index a636ebc16b39..98388109f22a 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -30,7 +30,7 @@ #include <plat/omap-pm.h> #endif -#include <plat/dsp.h> +#include <linux/platform_data/dsp-omap.h> static struct platform_device *omap_dsp_pdev; diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c index e28e761b7ab9..b3566f68a559 100644 --- a/arch/arm/mach-omap2/emu.c +++ b/arch/arm/mach-omap2/emu.c @@ -21,8 +21,7 @@ #include <linux/clk.h> #include <linux/err.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 9ad7d489b0de..d1058f16fb40 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -21,6 +21,7 @@ #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/of.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> @@ -60,6 +61,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); if (!pdata->regs) { pr_err("gpio%d: Memory allocation failed\n", id); + kfree(pdata); return -ENOMEM; } @@ -121,6 +123,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) break; default: WARN(1, "Invalid gpio bank_type\n"); + kfree(pdata->regs); kfree(pdata); return -EINVAL; } diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 386dec8d2351..4acf497faeb3 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -13,23 +13,31 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/mtd/nand.h> +#include <linux/platform_data/mtd-nand-omap2.h> #include <asm/mach/flash.h> -#include <plat/cpu.h> -#include <plat/nand.h> -#include <plat/board.h> #include <plat/gpmc.h> -static struct resource gpmc_nand_resource = { - .flags = IORESOURCE_MEM, +#include "soc.h" + +static struct resource gpmc_nand_resource[] = { + { + .flags = IORESOURCE_MEM, + }, + { + .flags = IORESOURCE_IRQ, + }, + { + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device gpmc_nand_device = { .name = "omap2-nand", .id = 0, - .num_resources = 1, - .resource = &gpmc_nand_resource, + .num_resources = ARRAY_SIZE(gpmc_nand_resource), + .resource = gpmc_nand_resource, }; static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) @@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, - &gpmc_nand_data->phys_base); + (unsigned long *)&gpmc_nand_resource[0].start); if (err < 0) { dev_err(dev, "Cannot request GPMC CS\n"); return err; } + gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + + NAND_IO_SIZE - 1; + + gpmc_nand_resource[1].start = + gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); + gpmc_nand_resource[2].start = + gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); /* Set timings in GPMC */ err = omap2_nand_gpmc_retime(gpmc_nand_data); if (err < 0) { @@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); } + gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); + err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n"); diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index a0fa9bb2bda5..916716e1da3b 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -15,19 +15,27 @@ #include <linux/platform_device.h> #include <linux/mtd/onenand_regs.h> #include <linux/io.h> +#include <linux/platform_data/mtd-onenand-omap2.h> #include <asm/mach/flash.h> -#include <plat/cpu.h> -#include <plat/onenand.h> -#include <plat/board.h> #include <plat/gpmc.h> +#include "soc.h" + +#define ONENAND_IO_SIZE SZ_128K + static struct omap_onenand_platform_data *gpmc_onenand_data; +static struct resource gpmc_onenand_resource = { + .flags = IORESOURCE_MEM, +}; + static struct platform_device gpmc_onenand_device = { .name = "omap2-onenand", .id = -1, + .num_resources = 1, + .resource = &gpmc_onenand_resource, }; static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) @@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) { + int err; + gpmc_onenand_data = _onenand_data; gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; @@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) gpmc_onenand_data->flags |= ONENAND_SYNC_READ; } + err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, + (unsigned long *)&gpmc_onenand_resource.start); + if (err < 0) { + pr_err("%s: Cannot request GPMC CS\n", __func__); + return; + } + + gpmc_onenand_resource.end = gpmc_onenand_resource.start + + ONENAND_IO_SIZE - 1; + if (platform_device_register(&gpmc_onenand_device) < 0) { - printk(KERN_ERR "Unable to register OneNAND device\n"); + pr_err("%s: Unable to register OneNAND device\n", __func__); + gpmc_cs_free(gpmc_onenand_data->cs); return; } } diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index ba10c24f3d8d..565475310374 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c @@ -17,9 +17,10 @@ #include <linux/io.h> #include <linux/smc91x.h> -#include <plat/board.h> #include <plat/gpmc.h> -#include <plat/gpmc-smc91x.h> +#include "gpmc-smc91x.h" + +#include "soc.h" static struct omap_smc91x_platform_data *gpmc_cfg; diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h index b64fbee4d567..b64fbee4d567 100644 --- a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h +++ b/arch/arm/mach-omap2/gpmc-smc91x.h diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c index b6c77be3e8f7..249a0b440cd6 100644 --- a/arch/arm/mach-omap2/gpmc-smsc911x.c +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -20,9 +20,8 @@ #include <linux/io.h> #include <linux/smsc911x.h> -#include <plat/board.h> #include <plat/gpmc.h> -#include <plat/gpmc-smsc911x.h> +#include "gpmc-smsc911x.h" static struct resource gpmc_smsc911x_resources[] = { [0] = { diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h index ea6c9c88c725..ea6c9c88c725 100644 --- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h +++ b/arch/arm/mach-omap2/gpmc-smsc911x.h diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index b2b5759ab0fe..72428bd45efc 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -28,8 +28,13 @@ #include <asm/mach-types.h> #include <plat/gpmc.h> +#include <plat/cpu.h> +#include <plat/gpmc.h> #include <plat/sdrc.h> +#include "soc.h" +#include "common.h" + /* GPMC register offsets */ #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 @@ -78,6 +83,15 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +/* XXX: Only NAND irq has been considered,currently these are the only ones used + */ +#define GPMC_NR_IRQ 2 + +struct gpmc_client_irq { + unsigned irq; + u32 bitmask; +}; + /* Structure to save gpmc cs context */ struct gpmc_cs_config { u32 config1; @@ -105,6 +119,10 @@ struct omap3_gpmc_regs { struct gpmc_cs_config cs_context[GPMC_CS_NUM]; }; +static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; +static struct irq_chip gpmc_irq_chip; +static unsigned gpmc_irq_start; + static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); @@ -279,7 +297,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) div = gpmc_cs_calc_divider(cs, t->sync_clk); if (div < 0) - return -1; + return div; GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); @@ -682,6 +700,117 @@ int gpmc_prefetch_reset(int cs) } EXPORT_SYMBOL(gpmc_prefetch_reset); +void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) +{ + reg->gpmc_status = gpmc_base + GPMC_STATUS; + reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; + reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; + reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; + reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; + reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; + reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; + reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; + reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; + reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; + reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; + reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; + reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; +} + +int gpmc_get_client_irq(unsigned irq_config) +{ + int i; + + if (hweight32(irq_config) > 1) + return 0; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (gpmc_client_irq[i].bitmask & irq_config) + return gpmc_client_irq[i].irq; + + return 0; +} + +static int gpmc_irq_endis(unsigned irq, bool endis) +{ + int i; + u32 regval; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (irq == gpmc_client_irq[i].irq) { + regval = gpmc_read_reg(GPMC_IRQENABLE); + if (endis) + regval |= gpmc_client_irq[i].bitmask; + else + regval &= ~gpmc_client_irq[i].bitmask; + gpmc_write_reg(GPMC_IRQENABLE, regval); + break; + } + + return 0; +} + +static void gpmc_irq_disable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, false); +} + +static void gpmc_irq_enable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, true); +} + +static void gpmc_irq_noop(struct irq_data *data) { } + +static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } + +static int gpmc_setup_irq(int gpmc_irq) +{ + int i; + u32 regval; + + if (!gpmc_irq) + return -EINVAL; + + gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); + if (IS_ERR_VALUE(gpmc_irq_start)) { + pr_err("irq_alloc_descs failed\n"); + return gpmc_irq_start; + } + + gpmc_irq_chip.name = "gpmc"; + gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; + gpmc_irq_chip.irq_enable = gpmc_irq_enable; + gpmc_irq_chip.irq_disable = gpmc_irq_disable; + gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; + gpmc_irq_chip.irq_ack = gpmc_irq_noop; + gpmc_irq_chip.irq_mask = gpmc_irq_noop; + gpmc_irq_chip.irq_unmask = gpmc_irq_noop; + + gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; + gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; + + for (i = 0; i < GPMC_NR_IRQ; i++) { + gpmc_client_irq[i].irq = gpmc_irq_start + i; + irq_set_chip_and_handler(gpmc_client_irq[i].irq, + &gpmc_irq_chip, handle_simple_irq); + set_irq_flags(gpmc_client_irq[i].irq, + IRQF_VALID | IRQF_NOAUTOEN); + } + + /* Disable interrupts */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + + /* clear interrupts */ + regval = gpmc_read_reg(GPMC_IRQSTATUS); + gpmc_write_reg(GPMC_IRQSTATUS, regval); + + return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); +} + static void __init gpmc_mem_init(void) { int cs; @@ -711,8 +840,8 @@ static void __init gpmc_mem_init(void) static int __init gpmc_init(void) { - u32 l, irq; - int cs, ret = -EINVAL; + u32 l; + int ret = -EINVAL; int gpmc_irq; char *ck = NULL; @@ -722,16 +851,16 @@ static int __init gpmc_init(void) l = OMAP2420_GPMC_BASE; else l = OMAP34XX_GPMC_BASE; - gpmc_irq = INT_34XX_GPMC_IRQ; + gpmc_irq = 20 + OMAP_INTC_START; } else if (cpu_is_omap34xx()) { ck = "gpmc_fck"; l = OMAP34XX_GPMC_BASE; - gpmc_irq = INT_34XX_GPMC_IRQ; + gpmc_irq = 20 + OMAP_INTC_START; } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { /* Base address and irq number are same for OMAP4/5 */ ck = "gpmc_ck"; l = OMAP44XX_GPMC_BASE; - gpmc_irq = OMAP44XX_IRQ_GPMC; + gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START; } if (WARN_ON(!ck)) @@ -761,16 +890,7 @@ static int __init gpmc_init(void) gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); - /* initalize the irq_chained */ - irq = OMAP_GPMC_IRQ_BASE; - for (cs = 0; cs < GPMC_CS_NUM; cs++) { - irq_set_chip_and_handler(irq, &dummy_irq_chip, - handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - irq++; - } - - ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); + ret = gpmc_setup_irq(gpmc_irq); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", gpmc_irq, ret); @@ -780,12 +900,19 @@ postcore_initcall(gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { - u8 cs; + int i; + u32 regval; + + regval = gpmc_read_reg(GPMC_IRQSTATUS); + + if (!regval) + return IRQ_NONE; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (regval & gpmc_client_irq[i].bitmask) + generic_handle_irq(gpmc_client_irq[i].irq); - /* check cs to invoke the irq */ - cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; - if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) - generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); + gpmc_write_reg(GPMC_IRQSTATUS, regval); return IRQ_HANDLED; } diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index cdd6dda03828..e003f2bba30c 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -29,7 +29,7 @@ #include <plat/omap_hwmod.h> #include <plat/omap_device.h> -#include <plat/hdq1w.h> +#include "hdq1w.h" #include "common.h" diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h index 0c1efc846d8d..0c1efc846d8d 100644 --- a/arch/arm/plat-omap/include/plat/hdq1w.h +++ b/arch/arm/mach-omap2/hdq1w.h diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index a9675d8d1822..03ebf47cfa9a 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -15,9 +15,10 @@ #include <linux/delay.h> #include <linux/gpio.h> #include <mach/hardware.h> +#include <linux/platform_data/gpio-omap.h> + #include <plat/mmc.h> #include <plat/omap-pm.h> -#include <plat/mux.h> #include <plat/omap_device.h> #include "mux.h" diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index a12e224eb97d..fc57e67b321f 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -19,7 +19,6 @@ * */ -#include <plat/cpu.h> #include <plat/i2c.h> #include "common.h" #include <plat/omap_hwmod.h> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 40373db649aa..cf2362ccb234 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,10 +22,10 @@ #include <asm/cputype.h> #include "common.h" -#include <plat/cpu.h> -#include <mach/id.h> +#include "id.h" +#include "soc.h" #include "control.h" static unsigned int omap_revision; @@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void) } if (j == ARRAY_SIZE(omap_ids)) { - printk(KERN_ERR "Unknown OMAP device type. " - "Handling it as OMAP%04x\n", - omap_ids[i].type >> 16); + pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", + omap_ids[i].type >> 16); j = i; } diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/id.h index 02ed3aa56f1e..02ed3aa56f1e 100644 --- a/arch/arm/mach-omap2/include/mach/id.h +++ b/arch/arm/mach-omap2/id.h diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h index be4d290d57ee..5621cc59c9f4 100644 --- a/arch/arm/mach-omap2/include/mach/gpio.h +++ b/arch/arm/mach-omap2/include/mach/gpio.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/gpio.h */ - -#include <plat/gpio.h> diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h index 78edf9d33f71..54492dbf6973 100644 --- a/arch/arm/mach-omap2/include/mach/hardware.h +++ b/arch/arm/mach-omap2/include/mach/hardware.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/hardware.h */ - -#include <plat/hardware.h> diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h index 44dab7725696..ba5282cafa42 100644 --- a/arch/arm/mach-omap2/include/mach/irqs.h +++ b/arch/arm/mach-omap2/include/mach/irqs.h @@ -1,5 +1,3 @@ /* * arch/arm/mach-omap2/include/mach/irqs.h */ - -#include <plat/irqs.h> diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h deleted file mode 100644 index 323675f21b69..000000000000 --- a/arch/arm/mach-omap2/include/mach/smp.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-omap2/include/mach/smp.h - */ - -#include <plat/smp.h> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4d2d981ff5c5..4234d28dc171 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -33,6 +33,7 @@ #include <plat/multi.h> #include <plat/dma.h> +#include "soc.h" #include "iomap.h" #include "voltage.h" #include "powerdomain.h" @@ -523,6 +524,8 @@ void __init am33xx_init_early(void) am33xx_voltagedomains_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); + am33xx_hwmod_init(); + omap_hwmod_init_postsetup(); am33xx_clk_init(); } #endif diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bcd83db41bbc..3926f370448f 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -23,8 +23,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "common.h" @@ -49,6 +48,8 @@ #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ +#define INTCPS_NR_MIR_REGS 3 +#define INTCPS_NR_IRQS 96 /* * OMAP2 has a number of different interrupt controllers, each interrupt @@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) unsigned long tmp; tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; - printk(KERN_INFO "IRQ: Found an INTC at 0x%p " - "(revision %ld.%ld) with %d interrupts\n", - bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); + pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", + bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h index b8b5641379b0..b8b5641379b0 100644 --- a/arch/arm/plat-omap/include/plat/l3_2xxx.h +++ b/arch/arm/mach-omap2/l3_2xxx.h diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h index cde1938c5f82..cde1938c5f82 100644 --- a/arch/arm/plat-omap/include/plat/l3_3xxx.h +++ b/arch/arm/mach-omap2/l3_3xxx.h diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h index 3f39cf8a35c6..3f39cf8a35c6 100644 --- a/arch/arm/plat-omap/include/plat/l4_2xxx.h +++ b/arch/arm/mach-omap2/l4_2xxx.h diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/mach-omap2/l4_3xxx.h index 881a858b1ffc..881a858b1ffc 100644 --- a/arch/arm/plat-omap/include/plat/l4_3xxx.h +++ b/arch/arm/mach-omap2/l4_3xxx.h diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 6875be837d9f..0d974565f8ca 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -16,8 +16,10 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/pm_runtime.h> + #include <plat/mailbox.h> -#include <mach/irqs.h> + +#include "soc.h" #define MAILBOX_REVISION 0x000 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 577cb77db26c..7d47407d6d46 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -17,11 +17,9 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/slab.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> -#include <mach/irqs.h> #include <plat/dma.h> -#include <plat/cpu.h> -#include <plat/mcbsp.h> #include <plat/omap_device.h> #include <linux/pm_runtime.h> diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index fb5bc6cf3773..9e57b4aadb06 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -23,6 +23,7 @@ #include <linux/kernel.h> #include <linux/err.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 414083b427df..765a2aceb665 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -20,7 +20,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> -#include <mach/omap-wakeupgen.h> +#include "omap-wakeupgen.h" #include "common.h" diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 1be8bcb52e93..df298d46707c 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -14,7 +14,9 @@ #include <linux/platform_device.h> #include <plat/iommu.h> -#include <plat/irqs.h> + +#include "soc.h" +#include "common.h" struct iommu_device { resource_size_t base; @@ -29,7 +31,7 @@ static int num_iommu_devices; static struct iommu_device omap3_devices[] = { { .base = 0x480bd400, - .irq = 24, + .irq = 24 + OMAP_INTC_START, .pdata = { .name = "isp", .nr_tlb_entries = 8, @@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = { #if defined(CONFIG_OMAP_IOMMU_IVA2) { .base = 0x5d000000, - .irq = 28, + .irq = 28 + OMAP_INTC_START, .pdata = { .name = "iva2", .nr_tlb_entries = 32, @@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; static struct iommu_device omap4_devices[] = { { .base = OMAP4_MMU1_BASE, - .irq = OMAP44XX_IRQ_DUCATI_MMU, + .irq = 100 + OMAP44XX_IRQ_GIC_START, .pdata = { .name = "ducati", .nr_tlb_entries = 32, @@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = { }, { .base = OMAP4_MMU2_BASE, - .irq = OMAP44XX_IRQ_TESLA_MMU, + .irq = 28 + OMAP44XX_IRQ_GIC_START, .pdata = { .name = "tesla", .nr_tlb_entries = 32, diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 637a1bdf2ac4..ff4e6a0e9c7c 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -50,9 +50,8 @@ #include <asm/suspend.h> #include <asm/hardware/cache-l2x0.h> -#include <plat/omap44xx.h> - #include "common.h" +#include "omap44xx.h" #include "omap4-sar-layout.h" #include "pm.h" #include "prcm_mpu44xx.h" diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index d9ae4a53d818..a004cb9acf52 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -19,7 +19,7 @@ #include <asm/memblock.h> #include <plat/omap-secure.h> -#include <mach/omap-secure.h> +#include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index c90a43589abe..c90a43589abe 100644 --- a/arch/arm/mach-omap2/include/mach/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 9a35adf91232..06d8bc3a8886 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -24,11 +24,11 @@ #include <asm/hardware/gic.h> #include <asm/smp_scu.h> -#include <mach/hardware.h> -#include <mach/omap-secure.h> -#include <mach/omap-wakeupgen.h> +#include "omap-secure.h" +#include "omap-wakeupgen.h" #include <asm/cputype.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "clockdomain.h" diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 05fdebfaa195..5d3b4f4f81ae 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -27,9 +27,10 @@ #include <asm/hardware/gic.h> -#include <mach/omap-wakeupgen.h> -#include <mach/omap-secure.h> +#include "omap-wakeupgen.h" +#include "omap-secure.h" +#include "soc.h" #include "omap4-sar-layout.h" #include "common.h" @@ -46,7 +47,7 @@ static void __iomem *wakeupgen_base; static void __iomem *sar_base; static DEFINE_SPINLOCK(wakeupgen_lock); -static unsigned int irq_target_cpu[NR_IRQS]; +static unsigned int irq_target_cpu[MAX_IRQS]; static unsigned int irq_banks = MAX_NR_REG_BANKS; static unsigned int max_irqs = MAX_IRQS; static unsigned int omap_secure_apis; @@ -229,13 +230,7 @@ static inline void omap4_irq_save_context(void) /* Save AuxBoot* registers */ val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); - - /* Save SyncReq generation logic */ - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); - __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); - val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); + val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); /* Save SyncReq generation logic */ diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/omap-wakeupgen.h index b0fd16f5c391..b0fd16f5c391 100644 --- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +++ b/arch/arm/mach-omap2/omap-wakeupgen.h diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/mach-omap2/omap24xx.h index 92df9e27cc5c..641a2c8d2eee 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/mach-omap2/omap24xx.h @@ -1,6 +1,4 @@ /* - * arch/arm/plat-omap/include/mach/omap24xx.h - * * This file contains the processor specific definitions * of the TI OMAP24XX. * diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h index 0d818acf3917..c0d1b4b1653f 100644 --- a/arch/arm/plat-omap/include/plat/omap34xx.h +++ b/arch/arm/mach-omap2/omap34xx.h @@ -1,6 +1,4 @@ /* - * arch/arm/plat-omap/include/mach/omap34xx.h - * * This file contains the processor specific definitions of the TI OMAP34XX. * * Copyright (C) 2007 Texas Instruments. diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c29dee998a79..e1f289748c5d 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -16,26 +16,25 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/memblock.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/export.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> #include <asm/memblock.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <plat/irqs.h> #include <plat/sram.h> #include <plat/omap-secure.h> #include <plat/mmc.h> -#include <mach/hardware.h> -#include <mach/omap-wakeupgen.h> +#include "omap-wakeupgen.h" +#include "soc.h" #include "common.h" #include "hsmmc.h" #include "omap4-sar-layout.h" -#include <linux/export.h> #ifdef CONFIG_CACHE_L2X0 static void __iomem *l2cache_base; @@ -171,7 +170,10 @@ static int __init omap_l2_cache_init(void) /* Enable PL310 L2 Cache controller */ omap_smc1(0x102, 0x1); - l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); + if (of_have_populated_dt()) + l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); + else + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); /* * Override default outer_cache.disable with a OMAP4 diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/mach-omap2/omap4-keypad.h index 8ad0a377a54b..20de0d5a7e77 100644 --- a/arch/arm/plat-omap/include/plat/omap4-keypad.h +++ b/arch/arm/mach-omap2/omap4-keypad.h @@ -1,6 +1,8 @@ #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H +struct omap_board_data; + extern int omap4_keyboard_init(struct omap4_keypad_platform_data *, struct omap_board_data *); #endif diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h index c0d478e55c84..43b927b2e2e8 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/mach-omap2/omap44xx.h @@ -39,12 +39,12 @@ #define IRQ_SIR_IRQ 0x0040 #define OMAP44XX_GIC_DIST_BASE 0x48241000 #define OMAP44XX_GIC_CPU_BASE 0x48240100 +#define OMAP44XX_IRQ_GIC_START 32 #define OMAP44XX_SCU_BASE 0x48240000 #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 #define OMAP44XX_L2CACHE_BASE 0x48242000 #define OMAP44XX_WKUPGEN_BASE 0x48281000 #define OMAP44XX_MCPDM_BASE 0x40132000 -#define OMAP44XX_MCPDM_L3_BASE 0x49032000 #define OMAP44XX_SAR_RAM_BASE 0x4a326000 #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a2582bb3cab3..a2582bb3cab3 100644 --- a/arch/arm/plat-omap/include/plat/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 6ca8e519968d..00c006686b0d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -139,18 +139,20 @@ #include <linux/slab.h> #include <linux/bootmem.h> -#include "common.h" -#include <plat/cpu.h> -#include "clockdomain.h" -#include "powerdomain.h" #include <plat/clock.h> #include <plat/omap_hwmod.h> #include <plat/prcm.h> +#include "soc.h" +#include "common.h" +#include "clockdomain.h" +#include "powerdomain.h" #include "cm2xxx_3xxx.h" #include "cminst44xx.h" +#include "cm33xx.h" #include "prm2xxx_3xxx.h" #include "prm44xx.h" +#include "prm33xx.h" #include "prminst44xx.h" #include "mux.h" #include "pm.h" @@ -868,6 +870,26 @@ static void _omap4_enable_module(struct omap_hwmod *oh) } /** + * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX + * @oh: struct omap_hwmod * + * + * Enables the PRCM module mode related to the hwmod @oh. + * No return value. + */ +static void _am33xx_enable_module(struct omap_hwmod *oh) +{ + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return; + + pr_debug("omap_hwmod: %s: %s: %d\n", + oh->name, __func__, oh->prcm.omap4.modulemode); + + am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 * @oh: struct omap_hwmod * * @@ -894,6 +916,31 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) } /** + * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to enter slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully enters + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_idle() function. + */ +static int _am33xx_wait_target_disable(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh * @oh: struct omap_hwmod *oh * @@ -1438,8 +1485,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) * Return the bit position of the reset line that match the * input name. Return -ENOENT if not found. */ -static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, - struct omap_hwmod_rst_info *ohri) +static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, + struct omap_hwmod_rst_info *ohri) { int i; @@ -1475,7 +1522,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, static int _assert_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; - u8 ret = -EINVAL; + int ret = -EINVAL; if (!oh) return -EINVAL; @@ -1484,7 +1531,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; ret = soc_ops.assert_hardreset(oh, &ohri); @@ -1542,7 +1589,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) static int _read_hardreset(struct omap_hwmod *oh, const char *name) { struct omap_hwmod_rst_info ohri; - u8 ret = -EINVAL; + int ret = -EINVAL; if (!oh) return -EINVAL; @@ -1551,7 +1598,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) return -ENOSYS; ret = _lookup_hardreset(oh, name, &ohri); - if (IS_ERR_VALUE(ret)) + if (ret < 0) return ret; return soc_ops.is_hardreset_asserted(oh, &ohri); @@ -1614,6 +1661,36 @@ static int _omap4_disable_module(struct omap_hwmod *oh) } /** + * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX + * @oh: struct omap_hwmod * + * + * Disable the PRCM module mode related to the hwmod @oh. + * Return EINVAL if the modulemode is not supported and 0 in case of success. + */ +static int _am33xx_disable_module(struct omap_hwmod *oh) +{ + int v; + + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return -EINVAL; + + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + + v = _am33xx_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; +} + +/** * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * @@ -1641,8 +1718,8 @@ static int _ocp_softreset(struct omap_hwmod *oh) /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - pr_warning("omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", + oh->name); return -EINVAL; } @@ -1889,6 +1966,7 @@ static int _enable(struct omap_hwmod *oh) _enable_sysc(oh); } } else { + _omap4_disable_module(oh); _disable_clocks(oh); pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", oh->name, r); @@ -2548,6 +2626,33 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh) } /** + * _am33xx_wait_target_ready - wait for a module to leave slave idle + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to leave slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully leaves + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_ready() function. + */ +static int _am33xx_wait_target_ready(struct omap_hwmod *oh) +{ + if (!oh || !oh->clkdm) + return -EINVAL; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + if (!_find_mpu_rt_port(oh)) + return 0; + + /* XXX check module SIDLEMODE, hardreset status */ + + return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); +} + +/** * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args * @oh: struct omap_hwmod * to assert hardreset * @ohri: hardreset line data @@ -2678,6 +2783,72 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, oh->prcm.omap4.rstctrl_offs); } +/** + * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to assert hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_assert_hardreset() with parameters extracted + * from the hwmod @oh and the hardreset line data @ohri. Only + * intended for use as an soc_ops function pointer. Passes along the + * return value from am33xx_prminst_assert_hardreset(). XXX This + * function is scheduled for removal when the PRM code is moved into + * drivers/. + */ +static int _am33xx_assert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) + +{ + return am33xx_prm_assert_hardreset(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs); +} + +/** + * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to deassert hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_deassert_hardreset() with parameters extracted + * from the hwmod @oh and the hardreset line data @ohri. Only + * intended for use as an soc_ops function pointer. Passes along the + * return value from am33xx_prminst_deassert_hardreset(). XXX This + * function is scheduled for removal when the PRM code is moved into + * drivers/. + */ +static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + if (ohri->st_shift) + pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", + oh->name, ohri->name); + + return am33xx_prm_deassert_hardreset(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs, + oh->prcm.omap4.rstst_offs); +} + +/** + * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args + * @oh: struct omap_hwmod * to test hardreset + * @ohri: hardreset line data + * + * Call am33xx_prminst_is_hardreset_asserted() with parameters + * extracted from the hwmod @oh and the hardreset line data @ohri. + * Only intended for use as an soc_ops function pointer. Passes along + * the return value from am33xx_prminst_is_hardreset_asserted(). XXX + * This function is scheduled for removal when the PRM code is moved + * into drivers/. + */ +static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, + struct omap_hwmod_rst_info *ohri) +{ + return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, + oh->clkdm->pwrdm.ptr->prcm_offs, + oh->prcm.omap4.rstctrl_offs); +} + /* Public functions */ u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) @@ -3158,6 +3329,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) } /** + * omap_hwmod_fill_dma_resources - fill struct resource array with dma data + * @oh: struct omap_hwmod * + * @res: pointer to the array of struct resource to fill + * + * Fill the struct resource array @res with dma resource data from the + * omap_hwmod @oh. Intended to be called by code that registers + * omap_devices. See also omap_hwmod_count_resources(). Returns the + * number of array elements filled. + */ +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) +{ + int i, sdma_reqs_cnt; + int r = 0; + + sdma_reqs_cnt = _count_sdma_reqs(oh); + for (i = 0; i < sdma_reqs_cnt; i++) { + (res + r)->name = (oh->sdma_reqs + i)->name; + (res + r)->start = (oh->sdma_reqs + i)->dma_req; + (res + r)->end = (oh->sdma_reqs + i)->dma_req; + (res + r)->flags = IORESOURCE_DMA; + r++; + } + + return r; +} + +/** * omap_hwmod_get_resource_byname - fetch IP block integration data by name * @oh: struct omap_hwmod * to operate on * @type: one of the IORESOURCE_* constants from include/linux/ioport.h @@ -3677,6 +3875,14 @@ void __init omap_hwmod_init(void) soc_ops.deassert_hardreset = _omap4_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; soc_ops.init_clkdm = _init_clkdm; + } else if (soc_is_am33xx()) { + soc_ops.enable_module = _am33xx_enable_module; + soc_ops.disable_module = _am33xx_disable_module; + soc_ops.wait_target_ready = _am33xx_wait_target_ready; + soc_ops.assert_hardreset = _am33xx_assert_hardreset; + soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; + soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; + soc_ops.init_clkdm = _init_clkdm; } else { WARN(1, "omap_hwmod: unknown SoC type\n"); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 50cfab61b0e2..10575a1bc1f1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -12,17 +12,15 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> #include <plat/i2c.h> -#include <plat/gpio.h> -#include <plat/mcspi.h> #include <plat/dmtimer.h> -#include <plat/l3_2xxx.h> -#include <plat/l4_2xxx.h> +#include "l3_2xxx.h" +#include "l4_2xxx.h" #include <plat/mmc.h> #include "omap_hwmod_common_data.h" @@ -162,9 +160,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { /* mailbox */ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 }, - { .name = "iva", .irq = 34 }, - { .irq = -1 } + { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, + { .name = "iva", .irq = 34 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mailbox_hwmod = { @@ -199,9 +197,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mcbsp1_hwmod = { @@ -225,9 +223,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2420_mcbsp2_hwmod = { @@ -265,8 +263,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = { /* msdi1 */ static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { - { .irq = 83 }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 58b5bc196d32..60de70feeae5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -12,21 +12,19 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> + #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> #include <plat/i2c.h> -#include <plat/gpio.h> -#include <plat/mcbsp.h> -#include <plat/mcspi.h> #include <plat/dmtimer.h> #include <plat/mmc.h> -#include <plat/l3_2xxx.h> +#include "l3_2xxx.h" +#include "soc.h" #include "omap_hwmod_common_data.h" - #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "wd_timer.h" @@ -133,8 +131,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { /* gpio5 */ static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { - { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ - { .irq = -1 } + { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ + { .irq = -1 }, }; static struct omap_hwmod omap2430_gpio5_hwmod = { @@ -173,8 +171,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { /* mailbox */ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } + { .irq = 26 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mailbox_hwmod = { @@ -195,8 +193,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { /* mcspi3 */ static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { - { .irq = 91 }, - { .irq = -1 } + { .irq = 91 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { @@ -250,9 +248,9 @@ static struct omap_hwmod_class usbotg_class = { /* usb_otg_hs */ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } + { .name = "mc", .irq = 92 + OMAP_INTC_START, }, + { .name = "dma", .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_usbhsotg_hwmod = { @@ -303,11 +301,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .name = "ovr", .irq = 61 }, - { .name = "common", .irq = 64 }, - { .irq = -1 } + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, + { .name = "common", .irq = 64 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp1_hwmod = { @@ -331,10 +329,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .name = "common", .irq = 16 }, - { .irq = -1 } + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .name = "common", .irq = 16 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp2_hwmod = { @@ -358,10 +356,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .name = "common", .irq = 17 }, - { .irq = -1 } + { .name = "tx", .irq = 89 + OMAP_INTC_START, }, + { .name = "rx", .irq = 90 + OMAP_INTC_START, }, + { .name = "common", .irq = 17 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap2430_mcbsp3_hwmod = { @@ -385,10 +383,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .name = "common", .irq = 18 }, - { .irq = -1 } + { .name = "tx", .irq = 54 + OMAP_INTC_START, }, + { .name = "rx", .irq = 55 + OMAP_INTC_START, }, + { .name = "common", .irq = 18 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { @@ -418,10 +416,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { /* mcbsp5 */ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .name = "common", .irq = 19 }, - { .irq = -1 } + { .name = "tx", .irq = 81 + OMAP_INTC_START, }, + { .name = "rx", .irq = 82 + OMAP_INTC_START, }, + { .name = "common", .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { @@ -468,8 +466,8 @@ static struct omap_hwmod_class omap2430_mmc_class = { /* MMC/SD/SDIO1 */ static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { - { .irq = 83 }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { @@ -509,8 +507,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { /* MMC/SD/SDIO2 */ static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { - { .irq = 86 }, - { .irq = -1 } + { .irq = 86 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 102d76e9e9ea..8851bbb6bb24 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -13,9 +13,7 @@ #include <plat/serial.h> #include <plat/dma.h> #include <plat/common.h> -#include <plat/hdq1w.h> - -#include <mach/irqs.h> +#include "hdq1w.h" #include "omap_hwmod_common_data.h" @@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = { /* Common MPU IRQ line data */ struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { - { .irq = 37, }, - { .irq = -1 } + { .irq = 37 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { - { .irq = 38, }, - { .irq = -1 } + { .irq = 38 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { - { .irq = 39, }, - { .irq = -1 } + { .irq = 39 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { - { .irq = 40, }, - { .irq = -1 } + { .irq = 40 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { - { .irq = 41, }, - { .irq = -1 } + { .irq = 41 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { - { .irq = 42, }, - { .irq = -1 } + { .irq = 42 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { - { .irq = 43, }, - { .irq = -1 } + { .irq = 43 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { - { .irq = 44, }, - { .irq = -1 } + { .irq = 44 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { - { .irq = 45, }, - { .irq = -1 } + { .irq = 45 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { - { .irq = 46, }, - { .irq = -1 } + { .irq = 46 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { - { .irq = 47, }, - { .irq = -1 } + { .irq = 47 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { - { .irq = INT_24XX_UART1_IRQ, }, - { .irq = -1 } + { .irq = 72 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { - { .irq = INT_24XX_UART2_IRQ, }, - { .irq = -1 } + { .irq = 73 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { - { .irq = INT_24XX_UART3_IRQ, }, - { .irq = -1 } + { .irq = 74 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_dispc_irqs[] = { - { .irq = 25 }, - { .irq = -1 } + { .irq = 25 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { - { .irq = INT_24XX_I2C1_IRQ, }, - { .irq = -1 } + { .irq = 56 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { - { .irq = INT_24XX_I2C2_IRQ, }, - { .irq = -1 } + { .irq = 57 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { - { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ - { .irq = -1 } + { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { - { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ - { .irq = -1 } + { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { - { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ - { .irq = -1 } + { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { - { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ - { .irq = -1 } + { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { - { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ - { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ - { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ - { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ - { .irq = -1 } + { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ + { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ + { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ + { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { - { .irq = 65 }, - { .irq = -1 } + { .irq = 65 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { - { .irq = 66 }, - { .irq = -1 } + { .irq = 66 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { @@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = { }; struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { - { .irq = 58, }, - { .irq = -1 } + { .irq = 58 + OMAP_INTC_START, }, + { .irq = -1 }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 5178e40e84f9..f853a0b1d5ca 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -15,8 +15,8 @@ #include <plat/omap_hwmod.h> #include <plat/serial.h> -#include <plat/l3_2xxx.h> -#include <plat/l4_2xxx.h> +#include "l3_2xxx.h" +#include "l4_2xxx.h" #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index afad69c6ba6e..feeb401cf87e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,12 +10,10 @@ */ #include <plat/omap_hwmod.h> #include <plat/serial.h> -#include <plat/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/dma.h> #include <plat/dmtimer.h> -#include <plat/mcspi.h> - -#include <mach/irqs.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" @@ -23,8 +21,8 @@ #include "wd_timer.h" struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { - { .irq = 48, }, - { .irq = -1 } + { .irq = 48 + OMAP_INTC_START, }, + { .irq = -1 }, }; struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c new file mode 100644 index 000000000000..59d5c1cd316d --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -0,0 +1,3381 @@ +/* + * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips + * + * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is automatically generated from the AM33XX hardware databases. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <plat/omap_hwmod.h> +#include <plat/cpu.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <plat/dma.h> +#include <plat/mmc.h> +#include <plat/i2c.h> + +#include "omap_hwmod_common_data.h" + +#include "control.h" +#include "cm33xx.h" +#include "prm33xx.h" +#include "prm-regbits-33xx.h" + +/* + * IP blocks + */ + +/* + * 'emif_fw' class + * instance(s): emif_fw + */ +static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { + .name = "emif_fw", +}; + +/* emif_fw */ +static struct omap_hwmod am33xx_emif_fw_hwmod = { + .name = "emif_fw", + .class = &am33xx_emif_fw_hwmod_class, + .clkdm_name = "l4fw_clkdm", + .main_clk = "l4fw_gclk", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'emif' class + * instance(s): emif + */ +static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { + .rev_offs = 0x0000, +}; + +static struct omap_hwmod_class am33xx_emif_hwmod_class = { + .name = "emif", + .sysc = &am33xx_emif_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_emif_irqs[] = { + { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* emif */ +static struct omap_hwmod am33xx_emif_hwmod = { + .name = "emif", + .class = &am33xx_emif_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_emif_irqs, + .main_clk = "dpll_ddr_m2_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'l3' class + * instance(s): l3_main, l3_s, l3_instr + */ +static struct omap_hwmod_class am33xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_main (l3_fast) */ +static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = { + { .name = "l3debug", .irq = 9 + OMAP_INTC_START, }, + { .name = "l3appint", .irq = 10 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_l3_main_hwmod = { + .name = "l3_main", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_l3_main_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l3_s */ +static struct omap_hwmod am33xx_l3_s_hwmod = { + .name = "l3_s", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3s_clkdm", +}; + +/* l3_instr */ +static struct omap_hwmod am33xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw + */ +static struct omap_hwmod_class am33xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_ls */ +static struct omap_hwmod am33xx_l4_ls_hwmod = { + .name = "l4_ls", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l4_hs */ +static struct omap_hwmod am33xx_l4_hs_hwmod = { + .name = "l4_hs", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4hs_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l4hs_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* l4_wkup */ +static struct omap_hwmod am33xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l4_fw */ +static struct omap_hwmod am33xx_l4_fw_hwmod = { + .name = "l4_fw", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4fw_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mpu' class + */ +static struct omap_hwmod_class am33xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = { + { .name = "emuint", .irq = 0 + OMAP_INTC_START, }, + { .name = "commtx", .irq = 1 + OMAP_INTC_START, }, + { .name = "commrx", .irq = 2 + OMAP_INTC_START, }, + { .name = "bench", .irq = 3 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_mpu_hwmod = { + .name = "mpu", + .class = &am33xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_mpu_irqs, + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'wakeup m3' class + * Wakeup controller sub-system under wakeup domain + */ +static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { + .name = "wkup_m3", +}; + +static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { + { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, +}; + +static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = { + { .name = "txev", .irq = 78 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* wkup_m3 */ +static struct omap_hwmod am33xx_wkup_m3_hwmod = { + .name = "wkup_m3", + .class = &am33xx_wkup_m3_hwmod_class, + .clkdm_name = "l4_wkup_aon_clkdm", + .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ + .mpu_irqs = am33xx_wkup_m3_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_wkup_m3_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), +}; + +/* + * 'pru-icss' class + * Programmable Real-Time Unit and Industrial Communication Subsystem + */ +static struct omap_hwmod_class am33xx_pruss_hwmod_class = { + .name = "pruss", +}; + +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { + { .name = "pruss", .rst_shift = 1 }, +}; + +static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = { + { .name = "evtout0", .irq = 20 + OMAP_INTC_START, }, + { .name = "evtout1", .irq = 21 + OMAP_INTC_START, }, + { .name = "evtout2", .irq = 22 + OMAP_INTC_START, }, + { .name = "evtout3", .irq = 23 + OMAP_INTC_START, }, + { .name = "evtout4", .irq = 24 + OMAP_INTC_START, }, + { .name = "evtout5", .irq = 25 + OMAP_INTC_START, }, + { .name = "evtout6", .irq = 26 + OMAP_INTC_START, }, + { .name = "evtout7", .irq = 27 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +/* pru-icss */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod am33xx_pruss_hwmod = { + .name = "pruss", + .class = &am33xx_pruss_hwmod_class, + .clkdm_name = "pruss_ocp_clkdm", + .mpu_irqs = am33xx_pruss_irqs, + .main_clk = "pruss_ocp_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_pruss_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), +}; + +/* gfx */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod_class am33xx_gfx_hwmod_class = { + .name = "gfx", +}; + +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { + { .name = "gfx", .rst_shift = 0 }, +}; + +static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { + { .name = "gfxint", .irq = 37 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gfx_hwmod = { + .name = "gfx", + .class = &am33xx_gfx_hwmod_class, + .clkdm_name = "gfx_l3_clkdm", + .mpu_irqs = am33xx_gfx_irqs, + .main_clk = "gfx_fck_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_gfx_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), +}; + +/* + * 'prcm' class + * power and reset manager (whole prcm infrastructure) + */ +static struct omap_hwmod_class am33xx_prcm_hwmod_class = { + .name = "prcm", +}; + +/* prcm */ +static struct omap_hwmod am33xx_prcm_hwmod = { + .name = "prcm", + .class = &am33xx_prcm_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* + * 'adc/tsc' class + * TouchScreen Controller (Anolog-To-Digital Converter) + */ +static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x10, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { + .name = "adc_tsc", + .sysc = &am33xx_adc_tsc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { + { .irq = 16 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_adc_tsc_hwmod = { + .name = "adc_tsc", + .class = &am33xx_adc_tsc_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_adc_tsc_irqs, + .main_clk = "adc_tsc_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * Modules omap_hwmod structures + * + * The following IPs are excluded for the moment because: + * - They do not need an explicit SW control using omap_hwmod API. + * - They still need to be validated with the driver + * properly adapted to omap_hwmod / omap_device + * + * - cEFUSE (doesn't fall under any ocp_if) + * - clkdiv32k + * - debugss + * - ocmc ram + * - ocp watch point + * - aes0 + * - sha0 + */ +#if 0 +/* + * 'cefuse' class + */ +static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { + .name = "cefuse", +}; + +static struct omap_hwmod am33xx_cefuse_hwmod = { + .name = "cefuse", + .class = &am33xx_cefuse_hwmod_class, + .clkdm_name = "l4_cefuse_clkdm", + .main_clk = "cefuse_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'clkdiv32k' class + */ +static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { + .name = "clkdiv32k", +}; + +static struct omap_hwmod am33xx_clkdiv32k_hwmod = { + .name = "clkdiv32k", + .class = &am33xx_clkdiv32k_hwmod_class, + .clkdm_name = "clk_24mhz_clkdm", + .main_clk = "clkdiv32k_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'debugss' class + * debug sub system + */ +static struct omap_hwmod_class am33xx_debugss_hwmod_class = { + .name = "debugss", +}; + +static struct omap_hwmod am33xx_debugss_hwmod = { + .name = "debugss", + .class = &am33xx_debugss_hwmod_class, + .clkdm_name = "l3_aon_clkdm", + .main_clk = "debugss_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ocmcram */ +static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { + .name = "ocmcram", +}; + +static struct omap_hwmod am33xx_ocmcram_hwmod = { + .name = "ocmcram", + .class = &am33xx_ocmcram_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ocpwp */ +static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { + .name = "ocpwp", +}; + +static struct omap_hwmod am33xx_ocpwp_hwmod = { + .name = "ocpwp", + .class = &am33xx_ocpwp_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'aes' class + */ +static struct omap_hwmod_class am33xx_aes_hwmod_class = { + .name = "aes", +}; + +static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { + { .irq = 102 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_aes0_hwmod = { + .name = "aes0", + .class = &am33xx_aes_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_aes0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* sha0 */ +static struct omap_hwmod_class am33xx_sha0_hwmod_class = { + .name = "sha0", +}; + +static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { + { .irq = 108 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_sha0_hwmod = { + .name = "sha0", + .class = &am33xx_sha0_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_sha0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +#endif + +/* 'smartreflex' class */ +static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { + .name = "smartreflex", +}; + +/* smartreflex0 */ +static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { + { .irq = 120 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_smartreflex0_hwmod = { + .name = "smartreflex0", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_smartreflex0_irqs, + .main_clk = "smartreflex0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* smartreflex1 */ +static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { + { .irq = 121 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_smartreflex1_hwmod = { + .name = "smartreflex1", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_smartreflex1_irqs, + .main_clk = "smartreflex1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'control' module class + */ +static struct omap_hwmod_class am33xx_control_hwmod_class = { + .name = "control", +}; + +static struct omap_hwmod_irq_info am33xx_control_irqs[] = { + { .irq = 8 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_control_hwmod = { + .name = "control", + .class = &am33xx_control_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_control_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'cpgmac' class + * cpsw/cpgmac sub system + */ +static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { + .name = "cpgmac0", + .sysc = &am33xx_cpgmac_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = { + { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, }, + { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, }, + { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, }, + { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_cpgmac0_hwmod = { + .name = "cpgmac0", + .class = &am33xx_cpgmac0_hwmod_class, + .clkdm_name = "cpsw_125mhz_clkdm", + .mpu_irqs = am33xx_cpgmac0_irqs, + .main_clk = "cpsw_125mhz_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * dcan class + */ +static struct omap_hwmod_class am33xx_dcan_hwmod_class = { + .name = "d_can", +}; + +/* dcan0 */ +static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { + { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, }, + { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_dcan0_hwmod = { + .name = "d_can0", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_dcan0_irqs, + .main_clk = "dcan0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dcan1 */ +static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { + { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, }, + { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, }, + { .irq = -1 }, +}; +static struct omap_hwmod am33xx_dcan1_hwmod = { + .name = "d_can1", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_dcan1_irqs, + .main_clk = "dcan1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* elm */ +static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_elm_hwmod_class = { + .name = "elm", + .sysc = &am33xx_elm_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { + { .irq = 4 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_elm_hwmod = { + .name = "elm", + .class = &am33xx_elm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_elm_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2 + */ +static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &am33xx_epwmss_sysc, +}; + +/* ehrpwm0 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { + { .name = "int", .irq = 86 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 58 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm0_hwmod = { + .name = "ehrpwm0", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm0_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ehrpwm1 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { + { .name = "int", .irq = 87 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 59 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm1_hwmod = { + .name = "ehrpwm1", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ehrpwm2 */ +static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { + { .name = "int", .irq = 39 + OMAP_INTC_START, }, + { .name = "tzint", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ehrpwm2_hwmod = { + .name = "ehrpwm2", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ehrpwm2_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap0 */ +static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { + { .irq = 31 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap0_hwmod = { + .name = "ecap0", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ecap0_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap1 */ +static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { + { .irq = 47 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap1_hwmod = { + .name = "ecap1", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_ecap1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap2 */ +static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = { + { .irq = 61 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_ecap2_hwmod = { + .name = "ecap2", + .mpu_irqs = am33xx_ecap2_irqs, + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'gpio' class: for gpio 0,1,2,3 + */ +static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &am33xx_gpio_sysc, + .rev = 2, +}; + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio0 */ +static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { + { .role = "dbclk", .clk = "gpio0_dbclk" }, +}; + +static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { + { .irq = 96 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gpio0_hwmod = { + .name = "gpio1", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio0_irqs, + .main_clk = "dpll_core_m4_div2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio0_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio1 */ +static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { + { .irq = 98 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio1_hwmod = { + .name = "gpio2", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio1_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { + { .irq = 32 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio2_hwmod = { + .name = "gpio3", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio2_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { + { .irq = 62 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio3_hwmod = { + .name = "gpio4", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = am33xx_gpio3_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpmc */ +static struct omap_hwmod_class_sysconfig gpmc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &gpmc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = { + { .irq = 100 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_gpmc_hwmod = { + .name = "gpmc", + .class = &am33xx_gpmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = am33xx_gpmc_irqs, + .main_clk = "l3s_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'i2c' class */ +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &am33xx_i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_2, + .reset = &omap_i2c_reset, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | + OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, +}; + +/* i2c1 */ +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = 70 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_i2c1_hwmod = { + .name = "i2c1", + .class = &i2c_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = i2c1_mpu_irqs, + .sdma_reqs = i2c1_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c1 */ +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = 71 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_i2c2_hwmod = { + .name = "i2c2", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = i2c2_mpu_irqs, + .sdma_reqs = i2c2_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod_dma_info i2c3_edma_reqs[] = { + { .name = "tx", .dma_req = 0, }, + { .name = "rx", .dma_req = 0, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = 30 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_i2c3_hwmod = { + .name = "i2c3", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = i2c3_mpu_irqs, + .sdma_reqs = i2c3_edma_reqs, + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + + +/* lcdc */ +static struct omap_hwmod_class_sysconfig lcdc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x54, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { + .name = "lcdc", + .sysc = &lcdc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { + { .irq = 36 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_lcdc_hwmod = { + .name = "lcdc", + .class = &am33xx_lcdc_hwmod_class, + .clkdm_name = "lcdc_clkdm", + .mpu_irqs = am33xx_lcdc_irqs, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "lcd_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors using a + * queued mailbox-interrupt mechanism. + */ +static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &am33xx_mailbox_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = { + { .irq = 77 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_mailbox_hwmod = { + .name = "mailbox", + .class = &am33xx_mailbox_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mailbox_irqs, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcasp' class + */ +static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { + .name = "mcasp", + .sysc = &am33xx_mcasp_sysc, +}; + +/* mcasp0 */ +static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { + { .name = "ax", .irq = 80 + OMAP_INTC_START, }, + { .name = "ar", .irq = 81 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = { + { .name = "tx", .dma_req = 8, }, + { .name = "rx", .dma_req = 9, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_mcasp0_hwmod = { + .name = "mcasp0", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mcasp0_irqs, + .sdma_reqs = am33xx_mcasp0_edma_reqs, + .main_clk = "mcasp0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mcasp1 */ +static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = { + { .name = "ax", .irq = 82 + OMAP_INTC_START, }, + { .name = "ar", .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = { + { .name = "tx", .dma_req = 10, }, + { .name = "rx", .dma_req = 11, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mcasp1_irqs, + .sdma_reqs = am33xx_mcasp1_edma_reqs, + .main_clk = "mcasp1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'mmc' class */ +static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &am33xx_mmc_sysc, +}; + +/* mmc0 */ +static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { + { .irq = 64 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { + { .name = "tx", .dma_req = 24, }, + { .name = "rx", .dma_req = 25, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc0_hwmod = { + .name = "mmc1", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mmc0_irqs, + .sdma_reqs = am33xx_mmc0_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc0_dev_attr, +}; + +/* mmc1 */ +static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { + { .irq = 28 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { + { .name = "tx", .dma_req = 2, }, + { .name = "rx", .dma_req = 3, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc1_hwmod = { + .name = "mmc2", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_mmc1_irqs, + .sdma_reqs = am33xx_mmc1_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { + { .irq = 29 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { + { .name = "tx", .dma_req = 64, }, + { .name = "rx", .dma_req = 65, }, + { .dma_req = -1 } +}; + +static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; +static struct omap_hwmod am33xx_mmc2_hwmod = { + .name = "mmc3", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_mmc2_irqs, + .sdma_reqs = am33xx_mmc2_edma_reqs, + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc2_dev_attr, +}; + +/* + * 'rtc' class + * rtc subsystem + */ +static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { + .rev_offs = 0x0074, + .sysc_offs = 0x0078, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | + SIDLE_SMART | SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_rtc_hwmod_class = { + .name = "rtc", + .sysc = &am33xx_rtc_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { + { .name = "rtcint", .irq = 75 + OMAP_INTC_START, }, + { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_rtc_hwmod = { + .name = "rtc", + .class = &am33xx_rtc_hwmod_class, + .clkdm_name = "l4_rtc_clkdm", + .mpu_irqs = am33xx_rtc_irqs, + .main_clk = "clk_32768_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'spi' class */ +static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0110, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_spi_hwmod_class = { + .name = "mcspi", + .sysc = &am33xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* spi0 */ +static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { + { .irq = 65 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = { + { .name = "rx0", .dma_req = 17 }, + { .name = "tx0", .dma_req = 16 }, + { .name = "rx1", .dma_req = 19 }, + { .name = "tx1", .dma_req = 18 }, + { .dma_req = -1 } +}; + +static struct omap2_mcspi_dev_attr mcspi_attrib = { + .num_chipselect = 2, +}; +static struct omap_hwmod am33xx_spi0_hwmod = { + .name = "spi0", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_spi0_irqs, + .sdma_reqs = am33xx_mcspi0_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* spi1 */ +static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { + { .irq = 125 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = { + { .name = "rx0", .dma_req = 43 }, + { .name = "tx0", .dma_req = 42 }, + { .name = "rx1", .dma_req = 45 }, + { .name = "tx1", .dma_req = 44 }, + { .dma_req = -1 } +}; + +static struct omap_hwmod am33xx_spi1_hwmod = { + .name = "spi1", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_spi1_irqs, + .sdma_reqs = am33xx_mcspi1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* + * 'spinlock' class + * spinlock provides hardware assistance for synchronizing the + * processes running on multiple processors + */ +static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { + .name = "spinlock", +}; + +static struct omap_hwmod am33xx_spinlock_hwmod = { + .name = "spinlock", + .class = &am33xx_spinlock_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'timer 2-7' class */ +static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_timer_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer_sysc, +}; + +/* timer1 1ms */ +static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer1ms_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { + { .irq = 67 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer1_hwmod = { + .name = "timer1", + .class = &am33xx_timer1ms_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_timer1_irqs, + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { + { .irq = 68 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer2_hwmod = { + .name = "timer2", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer2_irqs, + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { + { .irq = 69 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer3_hwmod = { + .name = "timer3", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer3_irqs, + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { + { .irq = 92 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer4_hwmod = { + .name = "timer4", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer4_irqs, + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { + { .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer5_hwmod = { + .name = "timer5", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer5_irqs, + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { + { .irq = 94 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer6_hwmod = { + .name = "timer6", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer6_irqs, + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { + { .irq = 95 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_timer7_hwmod = { + .name = "timer7", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_timer7_irqs, + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tpcc */ +static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { + .name = "tpcc", +}; + +static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { + { .name = "edma0", .irq = 12 + OMAP_INTC_START, }, + { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, }, + { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tpcc_hwmod = { + .name = "tpcc", + .class = &am33xx_tpcc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tpcc_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* 'tptc' class */ +static struct omap_hwmod_class am33xx_tptc_hwmod_class = { + .name = "tptc", + .sysc = &am33xx_tptc_sysc, +}; + +/* tptc0 */ +static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { + { .irq = 112 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc0_hwmod = { + .name = "tptc0", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc0_irqs, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc1 */ +static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { + { .irq = 113 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc1_hwmod = { + .name = "tptc1", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc1_irqs, + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc2 */ +static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { + { .irq = 114 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_tptc2_hwmod = { + .name = "tptc2", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .mpu_irqs = am33xx_tptc2_irqs, + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'uart' class */ +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod_dma_info uart1_edma_reqs[] = { + { .name = "tx", .dma_req = 26, }, + { .name = "rx", .dma_req = 27, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { + { .irq = 72 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart1_hwmod = { + .name = "uart1", + .class = &uart_class, + .clkdm_name = "l4_wkup_clkdm", + .mpu_irqs = am33xx_uart1_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { + { .irq = 73 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart2_hwmod = { + .name = "uart2", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart2_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod_dma_info uart3_edma_reqs[] = { + { .name = "tx", .dma_req = 30, }, + { .name = "rx", .dma_req = 31, }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { + { .irq = 74 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart3_hwmod = { + .name = "uart3", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart3_irqs, + .sdma_reqs = uart3_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { + { .irq = 44 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart4_hwmod = { + .name = "uart4", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart4_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { + { .irq = 45 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart5_hwmod = { + .name = "uart5", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart5_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { + { .irq = 46 + OMAP_INTC_START, }, + { .irq = -1 }, +}; + +static struct omap_hwmod am33xx_uart6_hwmod = { + .name = "uart6", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .mpu_irqs = am33xx_uart6_irqs, + .sdma_reqs = uart1_edma_reqs, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'wd_timer' class */ +static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { + .name = "wd_timer", +}; + +/* + * XXX: device.c file uses hardcoded name for watchdog timer + * driver "wd_timer2, so we are also using same name as of now... + */ +static struct omap_hwmod am33xx_wd_timer1_hwmod = { + .name = "wd_timer2", + .class = &am33xx_wd_timer_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .main_clk = "wdt1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'usb_otg' class + * high-speed on-the-go universal serial bus (usb_otg) controller + */ +static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_usbotg_class = { + .name = "usbotg", + .sysc = &am33xx_usbhsotg_sysc, +}; + +static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { + { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, + { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, + { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 + OMAP_INTC_START, }, +}; + +static struct omap_hwmod am33xx_usbss_hwmod = { + .name = "usb_otg_hs", + .class = &am33xx_usbotg_class, + .clkdm_name = "l3s_clkdm", + .mpu_irqs = am33xx_usbss_mpu_irqs, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "usbotg_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * Interfaces + */ + +/* l4 fw -> emif fw */ +static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = { + .master = &am33xx_l4_fw_hwmod, + .slave = &am33xx_emif_fw_hwmod, + .clk = "l4fw_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { + { + .pa_start = 0x4c000000, + .pa_end = 0x4c000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; +/* l3 main -> emif */ +static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_emif_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_emif_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU, +}; + +/* l3 main -> l4 hs */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l4_hs_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> l3 s */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_s_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 per/ls */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_ls_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 wkup */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_wkup_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 fw */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_fw_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> l3 instr */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_instr_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> prcm */ +static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_prcm_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l3 main*/ +static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* pru-icss -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { + .master = &am33xx_pruss_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wkup m3 -> l4 wkup */ +static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { + .master = &am33xx_wkup_m3_hwmod, + .slave = &am33xx_l4_wkup_hwmod, + .clk = "dpll_core_m4_div2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gfx -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { + .master = &am33xx_gfx_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_core_m4_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 wkup -> wkup m3 */ +static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = { + { + .name = "umem", + .pa_start = 0x44d00000, + .pa_end = 0x44d00000 + SZ_16K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "dmem", + .pa_start = 0x44d80000, + .pa_end = 0x44d80000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_wkup_m3_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_wkup_m3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 hs -> pru-icss */ +static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = { + { + .pa_start = 0x4a300000, + .pa_end = 0x4a300000 + SZ_512K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { + .master = &am33xx_l4_hs_hwmod, + .slave = &am33xx_pruss_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_pruss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> gfx */ +static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = { + { + .pa_start = 0x56000000, + .pa_end = 0x56000000 + SZ_16M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_gfx_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_gfx_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 wkup -> smartreflex0 */ +static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = { + { + .pa_start = 0x44e37000, + .pa_end = 0x44e37000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_smartreflex0_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_smartreflex0_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> smartreflex1 */ +static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = { + { + .pa_start = 0x44e39000, + .pa_end = 0x44e39000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_smartreflex1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_smartreflex1_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> control */ +static struct omap_hwmod_addr_space am33xx_control_addrs[] = { + { + .pa_start = 0x44e10000, + .pa_end = 0x44e10000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_control_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_control_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> rtc */ +static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = { + { + .pa_start = 0x44e3e000, + .pa_end = 0x44e3e000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_rtc_hwmod, + .clk = "clkdiv32k_ick", + .addr = am33xx_rtc_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 per/ls -> DCAN0 */ +static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = { + { + .pa_start = 0x481CC000, + .pa_end = 0x481CC000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_dcan0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> DCAN1 */ +static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = { + { + .pa_start = 0x481D0000, + .pa_end = 0x481D0000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_dcan1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> GPIO2 */ +static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { + { + .pa_start = 0x4804C000, + .pa_end = 0x4804C000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio3 */ +static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { + { + .pa_start = 0x481AC000, + .pa_end = 0x481AC000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio4 */ +static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { + { + .pa_start = 0x481AE000, + .pa_end = 0x481AE000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> I2C1 */ +static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { + { + .pa_start = 0x44E0B000, + .pa_end = 0x44E0B000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_i2c1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_i2c1_addr_space, + .user = OCP_USER_MPU, +}; + +/* L4 WKUP -> GPIO1 */ +static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { + { + .pa_start = 0x44E07000, + .pa_end = 0x44E07000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_gpio0_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_gpio0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 WKUP -> ADC_TSC */ +static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { + { + .pa_start = 0x44E0D000, + .pa_end = 0x44E0D000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_adc_tsc_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_adc_tsc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = { + /* cpsw ss */ + { + .pa_start = 0x4a100000, + .pa_end = 0x4a100000 + SZ_2K - 1, + .flags = ADDR_TYPE_RT, + }, + /* cpsw wr */ + { + .pa_start = 0x4a101200, + .pa_end = 0x4a101200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { + .master = &am33xx_l4_hs_hwmod, + .slave = &am33xx_cpgmac0_hwmod, + .clk = "cpsw_125mhz_gclk", + .addr = am33xx_cpgmac0_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_elm_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_elm_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { + { + .pa_start = 0x48300000, + .pa_end = 0x48300000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48300200, + .pa_end = 0x48300200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm0_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { + { + .pa_start = 0x48302000, + .pa_end = 0x48302000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48302200, + .pa_end = 0x48302200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm1_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48304200, + .pa_end = 0x48304200 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ehrpwm2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ehrpwm2_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { + { + .pa_start = 0x48300000, + .pa_end = 0x48300000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48300100, + .pa_end = 0x48300100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap0_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { + { + .pa_start = 0x48302000, + .pa_end = 0x48302000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48302100, + .pa_end = 0x48302100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap1_addr_space, + .user = OCP_USER_MPU, +}; + +/* + * Splitting the resources to handle access of PWMSS config space + * and module specific part independently + */ +static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { + .pa_start = 0x48304100, + .pa_end = 0x48304100 + SZ_256 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_ecap2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_ecap2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3s cfg -> gpmc */ +static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x50000000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_gpmc_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_gpmc_addr_space, + .user = OCP_USER_MPU, +}; + +/* i2c2 */ +static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { + { + .pa_start = 0x4802A000, + .pa_end = 0x4802A000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_i2c2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = { + { + .pa_start = 0x4819C000, + .pa_end = 0x4819C000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_i2c3_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { + { + .pa_start = 0x4830E000, + .pa_end = 0x4830E000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_lcdc_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_lcdc_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { + { + .pa_start = 0x480C8000, + .pa_end = 0x480C8000 + (SZ_4K - 1), + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4 ls -> mailbox */ +static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mailbox_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mailbox_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> spinlock */ +static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = { + { + .pa_start = 0x480Ca000, + .pa_end = 0x480Ca000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spinlock_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_spinlock_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcasp0 */ +static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { + { + .pa_start = 0x48038000, + .pa_end = 0x48038000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mcasp0 data */ +static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = { + { + .pa_start = 0x46000000, + .pa_end = 0x46000000 + SZ_4M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mcasp0_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mcasp0_data_addr_space, + .user = OCP_USER_SDMA, +}; + +/* l4 ls -> mcasp1 */ +static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { + { + .pa_start = 0x4803C000, + .pa_end = 0x4803C000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mcasp1 data */ +static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = { + { + .pa_start = 0x46400000, + .pa_end = 0x46400000 + SZ_4M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mcasp1_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mcasp1_data_addr_space, + .user = OCP_USER_SDMA, +}; + +/* l4 ls -> mmc0 */ +static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { + { + .pa_start = 0x48060100, + .pa_end = 0x48060100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mmc1 */ +static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { + { + .pa_start = 0x481d8100, + .pa_end = 0x481d8100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mmc2 */ +static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { + { + .pa_start = 0x47810100, + .pa_end = 0x47810100 + SZ_64K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mmc2_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mmc2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi0 */ +static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { + { + .pa_start = 0x48030000, + .pa_end = 0x48030000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcspi0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi1 */ +static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { + { + .pa_start = 0x481A0000, + .pa_end = 0x481A0000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcspi1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> timer1 */ +static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { + { + .pa_start = 0x44E31000, + .pa_end = 0x44E31000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_timer1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_timer1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer2 */ +static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x48040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer3 */ +static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x48042000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer3_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer4 */ +static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x48044000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer4_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer4_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer5 */ +static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer5_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer5_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer6 */ +static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { + { + .pa_start = 0x48048000, + .pa_end = 0x48048000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer6_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer6_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer7 */ +static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { + { + .pa_start = 0x4804A000, + .pa_end = 0x4804A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer7_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_timer7_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc */ +static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = { + { + .pa_start = 0x49000000, + .pa_end = 0x49000000 + SZ_32K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tpcc_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tpcc_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc0 */ +static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { + { + .pa_start = 0x49800000, + .pa_end = 0x49800000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc0_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc1 */ +static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { + { + .pa_start = 0x49900000, + .pa_end = 0x49900000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc1_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc2 */ +static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { + { + .pa_start = 0x49a00000, + .pa_end = 0x49a00000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc2_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> uart1 */ +static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { + { + .pa_start = 0x44E09000, + .pa_end = 0x44E09000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_uart1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_uart1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart2 */ +static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { + { + .pa_start = 0x48022000, + .pa_end = 0x48022000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart3 */ +static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { + { + .pa_start = 0x48024000, + .pa_end = 0x48024000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart3_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart3_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart4 */ +static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { + { + .pa_start = 0x481A6000, + .pa_end = 0x481A6000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart4_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart4_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart5 */ +static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { + { + .pa_start = 0x481A8000, + .pa_end = 0x481A8000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart5_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart5_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart6 */ +static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { + { + .pa_start = 0x481aa000, + .pa_end = 0x481aa000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart6_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_uart6_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 wkup -> wd_timer1 */ +static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { + { + .pa_start = 0x44e35000, + .pa_end = 0x44e35000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_wd_timer1_hwmod, + .clk = "dpll_core_m4_div2_ck", + .addr = am33xx_wd_timer1_addrs, + .user = OCP_USER_MPU, +}; + +/* usbss */ +/* l3 s -> USBSS interface */ +static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { + { + .name = "usbss", + .pa_start = 0x47400000, + .pa_end = 0x47400000 + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "musb0", + .pa_start = 0x47401000, + .pa_end = 0x47401000 + SZ_2K - 1, + .flags = ADDR_TYPE_RT + }, + { + .name = "musb1", + .pa_start = 0x47401800, + .pa_end = 0x47401800 + SZ_2K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_usbss_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_usbss_addr_space, + .user = OCP_USER_MPU, + .flags = OCPIF_SWSUP_IDLE, +}; + +static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { + &am33xx_l4_fw__emif_fw, + &am33xx_l3_main__emif, + &am33xx_mpu__l3_main, + &am33xx_mpu__prcm, + &am33xx_l3_s__l4_ls, + &am33xx_l3_s__l4_wkup, + &am33xx_l3_s__l4_fw, + &am33xx_l3_main__l4_hs, + &am33xx_l3_main__l3_s, + &am33xx_l3_main__l3_instr, + &am33xx_l3_main__gfx, + &am33xx_l3_s__l3_main, + &am33xx_pruss__l3_main, + &am33xx_wkup_m3__l4_wkup, + &am33xx_gfx__l3_main, + &am33xx_l4_wkup__wkup_m3, + &am33xx_l4_wkup__control, + &am33xx_l4_wkup__smartreflex0, + &am33xx_l4_wkup__smartreflex1, + &am33xx_l4_wkup__uart1, + &am33xx_l4_wkup__timer1, + &am33xx_l4_wkup__rtc, + &am33xx_l4_wkup__i2c1, + &am33xx_l4_wkup__gpio0, + &am33xx_l4_wkup__adc_tsc, + &am33xx_l4_wkup__wd_timer1, + &am33xx_l4_hs__pruss, + &am33xx_l4_per__dcan0, + &am33xx_l4_per__dcan1, + &am33xx_l4_per__gpio1, + &am33xx_l4_per__gpio2, + &am33xx_l4_per__gpio3, + &am33xx_l4_per__i2c2, + &am33xx_l4_per__i2c3, + &am33xx_l4_per__mailbox, + &am33xx_l4_ls__mcasp0, + &am33xx_l3_s__mcasp0_data, + &am33xx_l4_ls__mcasp1, + &am33xx_l3_s__mcasp1_data, + &am33xx_l4_ls__mmc0, + &am33xx_l4_ls__mmc1, + &am33xx_l3_s__mmc2, + &am33xx_l4_ls__timer2, + &am33xx_l4_ls__timer3, + &am33xx_l4_ls__timer4, + &am33xx_l4_ls__timer5, + &am33xx_l4_ls__timer6, + &am33xx_l4_ls__timer7, + &am33xx_l3_main__tpcc, + &am33xx_l4_ls__uart2, + &am33xx_l4_ls__uart3, + &am33xx_l4_ls__uart4, + &am33xx_l4_ls__uart5, + &am33xx_l4_ls__uart6, + &am33xx_l4_ls__spinlock, + &am33xx_l4_ls__elm, + &am33xx_l4_ls__ehrpwm0, + &am33xx_l4_ls__ehrpwm1, + &am33xx_l4_ls__ehrpwm2, + &am33xx_l4_ls__ecap0, + &am33xx_l4_ls__ecap1, + &am33xx_l4_ls__ecap2, + &am33xx_l3_s__gpmc, + &am33xx_l3_main__lcdc, + &am33xx_l4_ls__mcspi0, + &am33xx_l4_ls__mcspi1, + &am33xx_l3_main__tptc0, + &am33xx_l3_main__tptc1, + &am33xx_l3_main__tptc2, + &am33xx_l3_s__usbss, + &am33xx_l4_hs__cpgmac0, + NULL, +}; + +int __init am33xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); +} diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c9e38200216b..94b38af17055 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -15,26 +15,26 @@ * XXX these should be marked initdata for multi-OMAP kernels */ #include <linux/power/smartreflex.h> +#include <linux/platform_data/gpio-omap.h> #include <plat/omap_hwmod.h> -#include <mach/irqs.h> -#include <plat/cpu.h> #include <plat/dma.h> #include <plat/serial.h> -#include <plat/l3_3xxx.h> -#include <plat/l4_3xxx.h> +#include "l3_3xxx.h" +#include "l4_3xxx.h" #include <plat/i2c.h> -#include <plat/gpio.h> #include <plat/mmc.h> -#include <plat/mcbsp.h> -#include <plat/mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> #include <plat/dmtimer.h> +#include "am35xx.h" + +#include "soc.h" #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" #include "wd_timer.h" -#include <mach/am35xx.h> /* * OMAP3xxx hardware module integration data @@ -51,9 +51,9 @@ /* L3 */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { - { .irq = INT_34XX_L3_DBG_IRQ }, - { .irq = INT_34XX_L3_APP_IRQ }, - { .irq = -1 } + { .irq = 9 + OMAP_INTC_START, }, + { .irq = 10 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_l3_main_hwmod = { @@ -100,9 +100,9 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { /* IVA2 (IVA2) */ static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { - { .name = "logic", .rst_shift = 0 }, - { .name = "seq0", .rst_shift = 1 }, - { .name = "seq1", .rst_shift = 2 }, + { .name = "logic", .rst_shift = 0, .st_shift = 8 }, + { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, + { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, }; static struct omap_hwmod omap3xxx_iva_hwmod = { @@ -112,6 +112,15 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .rst_lines = omap3xxx_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), .main_clk = "iva2_ck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_IVA2_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, + } + }, }; /* timer class */ @@ -355,8 +364,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { /* timer12 */ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { - { .irq = 95, }, - { .irq = -1 } + { .irq = 95 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_timer12_hwmod = { @@ -490,8 +499,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { /* UART4 */ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { - { .irq = INT_36XX_UART4_IRQ, }, - { .irq = -1 } + { .irq = 80 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { @@ -518,8 +527,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { }; static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { - { .irq = INT_35XX_UART4_IRQ, }, - { .irq = -1 } + { .irq = 84 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { @@ -674,8 +683,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { - { .irq = 25 }, - { .irq = -1 } + { .irq = 25 + OMAP_INTC_START, }, + { .irq = -1 }, }; /* dss_dsi1 */ @@ -804,8 +813,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = { }; static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { - { .irq = INT_34XX_I2C3_IRQ, }, - { .irq = -1 } + { .irq = 61 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { @@ -963,8 +972,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { /* gpio5 */ static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { - { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ - { .irq = -1 } + { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ + { .irq = -1 }, }; static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { @@ -993,8 +1002,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { /* gpio6 */ static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { - { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ - { .irq = -1 } + { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ + { .irq = -1 }, }; static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { @@ -1098,10 +1107,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { /* mcbsp1 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { - { .name = "common", .irq = 16 }, - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } + { .name = "common", .irq = 16 + OMAP_INTC_START, }, + { .name = "tx", .irq = 59 + OMAP_INTC_START, }, + { .name = "rx", .irq = 60 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { @@ -1125,10 +1134,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { /* mcbsp2 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { - { .name = "common", .irq = 17 }, - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } + { .name = "common", .irq = 17 + OMAP_INTC_START, }, + { .name = "tx", .irq = 62 + OMAP_INTC_START, }, + { .name = "rx", .irq = 63 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { @@ -1157,10 +1166,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { /* mcbsp3 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { - { .name = "common", .irq = 22 }, - { .name = "tx", .irq = 89 }, - { .name = "rx", .irq = 90 }, - { .irq = -1 } + { .name = "common", .irq = 22 + OMAP_INTC_START, }, + { .name = "tx", .irq = 89 + OMAP_INTC_START, }, + { .name = "rx", .irq = 90 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { @@ -1189,10 +1198,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { /* mcbsp4 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { - { .name = "common", .irq = 23 }, - { .name = "tx", .irq = 54 }, - { .name = "rx", .irq = 55 }, - { .irq = -1 } + { .name = "common", .irq = 23 + OMAP_INTC_START, }, + { .name = "tx", .irq = 54 + OMAP_INTC_START, }, + { .name = "rx", .irq = 55 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { @@ -1222,10 +1231,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { /* mcbsp5 */ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { - { .name = "common", .irq = 27 }, - { .name = "tx", .irq = 81 }, - { .name = "rx", .irq = 82 }, - { .irq = -1 } + { .name = "common", .irq = 27 + OMAP_INTC_START, }, + { .name = "tx", .irq = 81 + OMAP_INTC_START, }, + { .name = "rx", .irq = 82 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { @@ -1267,8 +1276,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { /* mcbsp2_sidetone */ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { - { .name = "irq", .irq = 4 }, - { .irq = -1 } + { .name = "irq", .irq = 4 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { @@ -1289,8 +1298,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { /* mcbsp3_sidetone */ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { - { .name = "irq", .irq = 5 }, - { .irq = -1 } + { .name = "irq", .irq = 5 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { @@ -1352,8 +1361,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { }; static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18 }, - { .irq = -1 } + { .irq = 18 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap34xx_sr1_hwmod = { @@ -1397,8 +1406,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { }; static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19 }, - { .irq = -1 } + { .irq = 19 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap34xx_sr2_hwmod = { @@ -1458,8 +1467,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { - { .irq = 26 }, - { .irq = -1 } + { .irq = 26 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_mailbox_hwmod = { @@ -1549,8 +1558,8 @@ static struct omap_hwmod omap34xx_mcspi2 = { /* mcspi3 */ static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { - { .name = "irq", .irq = 91 }, /* 91 */ - { .irq = -1 } + { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { @@ -1585,8 +1594,8 @@ static struct omap_hwmod omap34xx_mcspi3 = { /* mcspi4 */ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { - { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ - { .irq = -1 } + { .name = "irq", .irq = 48 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { @@ -1638,9 +1647,9 @@ static struct omap_hwmod_class usbotg_class = { /* usb_otg_hs */ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 92 }, - { .name = "dma", .irq = 93 }, - { .irq = -1 } + { .name = "mc", .irq = 92 + OMAP_INTC_START, }, + { .name = "dma", .irq = 93 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { @@ -1670,8 +1679,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { /* usb_otg_hs */ static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { - { .name = "mc", .irq = 71 }, - { .irq = -1 } + { .name = "mc", .irq = 71 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_class am35xx_usbotg_class = { @@ -1706,8 +1715,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = { /* MMC/SD/SDIO1 */ static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { - { .irq = 83, }, - { .irq = -1 } + { .irq = 83 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { @@ -1773,8 +1782,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { /* MMC/SD/SDIO2 */ static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { - { .irq = INT_24XX_MMC2_IRQ, }, - { .irq = -1 } + { .irq = 86 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { @@ -1834,8 +1843,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { /* MMC/SD/SDIO3 */ static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { - { .irq = 94, }, - { .irq = -1 } + { .irq = 94 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { @@ -1893,9 +1902,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { }; static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 }, - { .name = "ehci-irq", .irq = 77 }, - { .irq = -1 } + { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, + { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { @@ -1987,8 +1996,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { }; static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 }, - { .irq = -1 } + { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, + { .irq = -1 }, }; static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { @@ -3214,11 +3223,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { }; static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { - { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, - { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, - { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, - { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, - { .irq = -1 } + { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, + { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, + { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, + { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, + { .irq = -1 }, }; static struct omap_hwmod_class am35xx_emac_class = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 242aee498ceb..c7dcb606cd0c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -19,15 +19,14 @@ */ #include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/power/smartreflex.h> #include <plat/omap_hwmod.h> -#include <plat/cpu.h> #include <plat/i2c.h> -#include <plat/gpio.h> #include <plat/dma.h> -#include <plat/mcspi.h> -#include <plat/mcbsp.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> #include <plat/mmc.h> #include <plat/dmtimer.h> #include <plat/common.h> @@ -4210,7 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { }; /* dsp -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { +static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { .master = &omap44xx_dsp_hwmod, .slave = &omap44xx_sl2if_hwmod, .clk = "dpll_iva_m5x2_ck", @@ -4828,7 +4827,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { }; /* iva -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { +static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { .master = &omap44xx_iva_hwmod, .slave = &omap44xx_sl2if_hwmod, .clk = "dpll_iva_m5x2_ck", @@ -5362,7 +5361,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { }; /* l3_main_2 -> sl2if */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { +static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_sl2if_hwmod, .clk = "l3_div_ck", @@ -5890,6 +5889,12 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { .pa_end = 0x4a0ab003, .flags = ADDR_TYPE_RT }, + { + /* XXX: Remove this once control module driver is in place */ + .pa_start = 0x4a00233c, + .pa_end = 0x4a00233f, + .flags = ADDR_TYPE_RT + }, { } }; @@ -6032,7 +6037,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_abe__dmic, &omap44xx_l4_abe__dmic_dma, &omap44xx_dsp__iva, - &omap44xx_dsp__sl2if, + /* &omap44xx_dsp__sl2if, */ &omap44xx_l4_cfg__dsp, &omap44xx_l3_main_2__dss, &omap44xx_l4_per__dss, @@ -6068,7 +6073,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__i2c4, &omap44xx_l3_main_2__ipu, &omap44xx_l3_main_2__iss, - &omap44xx_iva__sl2if, + /* &omap44xx_iva__sl2if, */ &omap44xx_l3_main_2__iva, &omap44xx_l4_wkup__kbd, &omap44xx_l4_cfg__mailbox, @@ -6099,7 +6104,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__cm_core, &omap44xx_l4_wkup__prm, &omap44xx_l4_wkup__scrm, - &omap44xx_l3_main_2__sl2if, + /* &omap44xx_l3_main_2__sl2if, */ &omap44xx_l4_abe__slimbus1, &omap44xx_l4_abe__slimbus1_dma, &omap44xx_l4_per__slimbus2, diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index e7e8eeae95e5..dddb677fed68 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -16,6 +16,7 @@ #include <plat/omap_hwmod.h> +#include "common.h" #include "display.h" /* Common address space across OMAP2xxx */ diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index d52651a05daa..d992db8ff0b0 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -29,145 +29,9 @@ #include <linux/usb.h> #include <plat/usb.h> -#include "control.h" - -/* OMAP control module register for UTMI PHY */ -#define CONTROL_DEV_CONF 0x300 -#define PHY_PD 0x1 - -#define USBOTGHS_CONTROL 0x33c -#define AVALID BIT(0) -#define BVALID BIT(1) -#define VBUSVALID BIT(2) -#define SESSEND BIT(3) -#define IDDIG BIT(4) - -static struct clk *phyclk, *clk48m, *clk32k; -static void __iomem *ctrl_base; -static int usbotghs_control; - -int omap4430_phy_init(struct device *dev) -{ - ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); - if (!ctrl_base) { - pr_err("control module ioremap failed\n"); - return -ENOMEM; - } - /* Power down the phy */ - __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); - - if (!dev) { - iounmap(ctrl_base); - return 0; - } - - phyclk = clk_get(dev, "ocp2scp_usb_phy_ick"); - if (IS_ERR(phyclk)) { - dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n"); - iounmap(ctrl_base); - return PTR_ERR(phyclk); - } - - clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m"); - if (IS_ERR(clk48m)) { - dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n"); - clk_put(phyclk); - iounmap(ctrl_base); - return PTR_ERR(clk48m); - } - - clk32k = clk_get(dev, "usb_phy_cm_clk32k"); - if (IS_ERR(clk32k)) { - dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n"); - clk_put(phyclk); - clk_put(clk48m); - iounmap(ctrl_base); - return PTR_ERR(clk32k); - } - return 0; -} - -int omap4430_phy_set_clk(struct device *dev, int on) -{ - static int state; - - if (on && !state) { - /* Enable the phy clocks */ - clk_enable(phyclk); - clk_enable(clk48m); - clk_enable(clk32k); - state = 1; - } else if (state) { - /* Disable the phy clocks */ - clk_disable(phyclk); - clk_disable(clk48m); - clk_disable(clk32k); - state = 0; - } - return 0; -} - -int omap4430_phy_power(struct device *dev, int ID, int on) -{ - if (on) { - if (ID) - /* enable VBUS valid, IDDIG groung */ - __raw_writel(AVALID | VBUSVALID, ctrl_base + - USBOTGHS_CONTROL); - else - /* - * Enable VBUS Valid, AValid and IDDIG - * high impedance - */ - __raw_writel(IDDIG | AVALID | VBUSVALID, - ctrl_base + USBOTGHS_CONTROL); - } else { - /* Enable session END and IDIG to high impedance. */ - __raw_writel(SESSEND | IDDIG, ctrl_base + - USBOTGHS_CONTROL); - } - return 0; -} - -int omap4430_phy_suspend(struct device *dev, int suspend) -{ - if (suspend) { - /* Disable the clocks */ - omap4430_phy_set_clk(dev, 0); - /* Power down the phy */ - __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); - - /* save the context */ - usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL); - } else { - /* Enable the internel phy clcoks */ - omap4430_phy_set_clk(dev, 1); - /* power on the phy */ - if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { - __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); - mdelay(200); - } - - /* restore the context */ - __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL); - } - - return 0; -} - -int omap4430_phy_exit(struct device *dev) -{ - if (ctrl_base) - iounmap(ctrl_base); - if (phyclk) - clk_put(phyclk); - if (clk48m) - clk_put(clk48m); - if (clk32k) - clk_put(clk32k); - return 0; -} +#include "soc.h" +#include "control.h" void am35x_musb_reset(void) { diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index d8f6dbf45d16..45ad7f74f356 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -64,25 +64,22 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, } oh = omap_hwmod_lookup(opp_def->hwmod_name); if (!oh || !oh->od) { - pr_debug("%s: no hwmod or odev for %s, [%d] " - "cannot add OPPs.\n", __func__, - opp_def->hwmod_name, i); + pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n", + __func__, opp_def->hwmod_name, i); continue; } dev = &oh->od->pdev->dev; r = opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { - dev_err(dev, "%s: add OPP %ld failed for %s [%d] " - "result=%d\n", - __func__, opp_def->freq, - opp_def->hwmod_name, i, r); + dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n", + __func__, opp_def->freq, + opp_def->hwmod_name, i, r); } else { if (!opp_def->default_available) r = opp_disable(dev, opp_def->freq); if (r) - dev_err(dev, "%s: disable %ld failed for %s " - "[%d] result=%d\n", + dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, opp_def->hwmod_name, i, r); } diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c index 5037e76e4e23..a9e8cf21705d 100644 --- a/arch/arm/mach-omap2/opp2420_data.c +++ b/arch/arm/mach-omap2/opp2420_data.c @@ -28,7 +28,7 @@ * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/ */ -#include <plat/hardware.h> +#include <linux/kernel.h> #include "opp2xxx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c index 750805c528d8..0e75ec3e114b 100644 --- a/arch/arm/mach-omap2/opp2430_data.c +++ b/arch/arm/mach-omap2/opp2430_data.c @@ -26,7 +26,7 @@ * This is technically part of the OMAP2xxx clock code. */ -#include <plat/hardware.h> +#include <linux/kernel.h> #include "opp2xxx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index d95f3f945d4a..75cef5f67a8a 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -19,8 +19,6 @@ */ #include <linux/module.h> -#include <plat/cpu.h> - #include "control.h" #include "omap_opp_data.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index c95415da23c2..a9fd6d5fe79e 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -20,8 +20,7 @@ */ #include <linux/module.h> -#include <plat/cpu.h> - +#include "soc.h" #include "control.h" #include "omap_opp_data.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 814bcd901596..3e1345fc0713 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -28,7 +28,6 @@ #include <linux/slab.h> #include <plat/clock.h> -#include <plat/board.h> #include "powerdomain.h" #include "clockdomain.h" #include <plat/dmtimer.h> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 9cb5cede0f50..939bd6f70b51 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -203,8 +203,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, bootup_volt = opp_get_voltage(opp); rcu_read_unlock(); if (!bootup_volt) { - pr_err("%s: unable to find voltage corresponding " - "to the bootup OPP for vdd_%s\n", __func__, vdd_name); + pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", + __func__, vdd_name); goto exit; } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 2edeffc923a6..8af6cd6ac331 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -29,6 +29,7 @@ #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> +#include <linux/platform_data/gpio-omap.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> @@ -38,9 +39,6 @@ #include <plat/clock.h> #include <plat/sram.h> #include <plat/dma.h> -#include <plat/board.h> - -#include <mach/irqs.h> #include "common.h" #include "prm2xxx_3xxx.h" @@ -352,16 +350,6 @@ int __init omap2_pm_init(void) prcm_setup_regs(); - /* Hack to prevent MPU retention when STI console is enabled. */ - { - const struct omap_sti_console_config *sti; - - sti = omap_get_config(OMAP_TAG_STI_CONSOLE, - struct omap_sti_console_config); - if (sti != NULL && sti->enable) - sti_console_enabled = 1; - } - /* * We copy the assembler sleep/wakeup routines to SRAM. * These routines need to be in SRAM as that's the only diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 05bd8f02723f..ba670db1fd37 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -28,6 +28,8 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/platform_data/gpio-omap.h> + #include <trace/events/power.h> #include <asm/suspend.h> @@ -389,9 +391,8 @@ restore: list_for_each_entry(pwrst, &pwrst_list, node) { state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { - pr_info("Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); + pr_info("Powerdomain (%s) didn't enter target state %d\n", + pwrst->pwrdm->name, pwrst->next_state); ret = -1; } omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); @@ -731,8 +732,7 @@ int __init omap3_pm_init(void) omap3_secure_ram_storage = kmalloc(0x803F, GFP_KERNEL); if (!omap3_secure_ram_storage) - pr_err("Memory allocation failed when " - "allocating for secure sram context\n"); + pr_err("Memory allocation failed when allocating for secure sram context\n"); local_irq_disable(); local_fiq_disable(); diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index ea24174f5707..04922d149068 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -69,9 +69,8 @@ static int omap4_pm_suspend(void) list_for_each_entry(pwrst, &pwrst_list, node) { state = pwrdm_read_prev_pwrst(pwrst->pwrdm); if (state > pwrst->next_state) { - pr_info("Powerdomain (%s) didn't enter " - "target state %d\n", - pwrst->pwrdm->name, pwrst->next_state); + pr_info("Powerdomain (%s) didn't enter target state %d\n", + pwrst->pwrdm->name, pwrst->next_state); ret = -1; } omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); @@ -189,8 +188,7 @@ int __init omap4_pm_init(void) ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); if (ret) { - pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 " - "wakeup dependency\n"); + pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); goto err2; } diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 69b36e185e9b..1678a3284233 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -28,11 +28,13 @@ #include "prm44xx.h" #include <asm/cpu.h> -#include <plat/cpu.h> + +#include <plat/prcm.h> + #include "powerdomain.h" #include "clockdomain.h" -#include <plat/prcm.h> +#include "soc.h" #include "pm.h" #define PWRDM_TRACE_STATES_FLAG (1<<31) @@ -339,8 +341,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) if (!pwrdm || !clkdm) return -EINVAL; - pr_debug("powerdomain: associating clockdomain %s with powerdomain " - "%s\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: associating clockdomain %s\n", + pwrdm->name, clkdm->name); for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { if (!pwrdm->pwrdm_clkdms[i]) @@ -354,8 +356,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) } if (i == PWRDM_MAX_CLKDMS) { - pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for " - "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name); + pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n", + pwrdm->name, clkdm->name); WARN_ON(1); ret = -ENOMEM; goto pac_exit; @@ -387,16 +389,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) if (!pwrdm || !clkdm) return -EINVAL; - pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " - "%s\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: dissociating clockdomain %s\n", + pwrdm->name, clkdm->name); for (i = 0; i < PWRDM_MAX_CLKDMS; i++) if (pwrdm->pwrdm_clkdms[i] == clkdm) break; if (i == PWRDM_MAX_CLKDMS) { - pr_debug("powerdomain: clkdm %s not associated with pwrdm " - "%s ?!\n", clkdm->name, pwrdm->name); + pr_debug("powerdomain: %s: clkdm %s not associated?!\n", + pwrdm->name, clkdm->name); ret = -ENOENT; goto pdc_exit; } @@ -485,7 +487,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) if (!(pwrdm->pwrsts & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next powerstate for %s to %0x\n", + pr_debug("powerdomain: %s: setting next powerstate to %0x\n", pwrdm->name, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) { @@ -587,7 +589,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", + pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n", pwrdm->name, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst) @@ -624,8 +626,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next memory powerstate for domain %s " - "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); + pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n", + pwrdm->name, bank, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst) ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); @@ -662,8 +664,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) return -EINVAL; - pr_debug("powerdomain: setting next memory powerstate for domain %s " - "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); + pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n", + pwrdm->name, bank, pwrst); if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst) ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); @@ -841,7 +843,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) * warn & fail if it is not ON. */ - pr_debug("powerdomain: clearing previous power state reg for %s\n", + pr_debug("powerdomain: %s: clearing previous power state reg\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst) @@ -871,8 +873,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) return ret; - pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", - pwrdm->name); + pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar) ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm); @@ -901,8 +902,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) return ret; - pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", - pwrdm->name); + pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name); if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar) ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm); diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index 0f0a9f1592fe..3950ccfe5f4a 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { - printk(KERN_ERR "powerdomain: waited too long for " - "powerdomain %s to complete transition\n", pwrdm->name); + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); return -EAGAIN; } diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 601325b852a4..aeac6f35ca10 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -198,8 +198,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) udelay(1); if (c > PWRDM_TRANSITION_BAILOUT) { - printk(KERN_ERR "powerdomain: waited too long for " - "powerdomain %s to complete transition\n", pwrdm->name); + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); return -EAGAIN; } diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index bb883e463078..8b23d234fb55 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -15,11 +15,9 @@ #include <linux/init.h> #include <linux/bug.h> -#include <plat/cpu.h> - +#include "soc.h" #include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" - #include "prcm-common.h" #include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 053e24ed3c48..0f51e034e0aa 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -27,7 +27,6 @@ #include "common.h" #include <plat/prcm.h> -#include <plat/irqs.h> #include "clock.h" #include "clock2xxx.h" @@ -140,11 +139,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, MAX_MODULE_ENABLE_WAIT, i); if (i < MAX_MODULE_ENABLE_WAIT) - pr_debug("cm: Module associated with clock %s ready after %d " - "loops\n", name, i); + pr_debug("cm: Module associated with clock %s ready after %d loops\n", + name, i); else - pr_err("cm: Module associated with clock %s didn't enable in " - "%d tries\n", name, MAX_MODULE_ENABLE_WAIT); + pr_err("cm: Module associated with clock %s didn't enable in %d tries\n", + name, MAX_MODULE_ENABLE_WAIT); return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; }; diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index a0309dea6794..9529984d8d2b 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -17,11 +17,10 @@ #include <linux/io.h> #include <linux/irq.h> -#include "common.h" -#include <plat/cpu.h> #include <plat/prcm.h> -#include <plat/irqs.h> +#include "soc.h" +#include "common.h" #include "vp.h" #include "prm2xxx_3xxx.h" @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { .nr_regs = 1, .irqs = omap3_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), - .irq = INT_34XX_PRCM_MPU_IRQ, + .irq = 11 + OMAP_INTC_START, .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, .ocp_barrier = &omap3xxx_prm_ocp_barrier, .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index bb727c2d9337..f0c4d5f4a174 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -17,10 +17,9 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/cpu.h> -#include <plat/irqs.h> #include <plat/prcm.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "vp.h" @@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .nr_regs = 2, .irqs = omap4_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), - .irq = OMAP44XX_IRQ_PRCM, + .irq = 11 + OMAP44XX_IRQ_GIC_START, .read_pending_irqs = &omap44xx_prm_read_pending_irqs, .ocp_barrier = &omap44xx_prm_ocp_barrier, .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 03b126d9ad94..6b4d332be2f6 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -26,7 +26,6 @@ #include <plat/common.h> #include <plat/prcm.h> -#include <plat/irqs.h> #include "prm2xxx_3xxx.h" #include "prm44xx.h" diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 1133bb2f632b..73e55e485329 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -24,11 +24,11 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/hardware.h> #include <plat/clock.h> #include <plat/sram.h> #include <plat/sdrc.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index c1b93c752d70..0405c8190803 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -29,11 +29,11 @@ #include <plat/omap-serial.h> #include "common.h" -#include <plat/board.h> #include <plat/dma.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> #include <plat/omap-pm.h> +#include <plat/serial.h> #include "prm2xxx_3xxx.h" #include "pm.h" @@ -81,8 +81,9 @@ static struct omap_uart_port_info omap_serial_default_info[] __initdata = { }; #ifdef CONFIG_PM -static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) +static void omap_uart_enable_wakeup(struct device *dev, bool enable) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); if (!od) @@ -99,15 +100,17 @@ static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) * in Smartidle Mode When Configured for DMA Operations. * WA: configure uart in force idle mode. */ -static void omap_uart_set_noidle(struct platform_device *pdev) +static void omap_uart_set_noidle(struct device *dev) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); } -static void omap_uart_set_smartidle(struct platform_device *pdev) +static void omap_uart_set_smartidle(struct device *dev) { + struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); u8 idlemode; @@ -120,10 +123,10 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) } #else -static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) +static void omap_uart_enable_wakeup(struct device *dev, bool enable) {} -static void omap_uart_set_noidle(struct platform_device *pdev) {} -static void omap_uart_set_smartidle(struct platform_device *pdev) {} +static void omap_uart_set_noidle(struct device *dev) {} +static void omap_uart_set_smartidle(struct device *dev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX @@ -229,9 +232,8 @@ static int __init omap_serial_early_init(void) if (console_loglevel >= 10) { uart_debug = true; - pr_info("%s used as console in debug mode" - " uart%d clocks will not be" - " gated", uart_name, uart->num); + pr_info("%s used as console in debug mode: uart%d clocks will not be gated", + uart_name, uart->num); } if (cmdline_find_option("no_console_suspend")) @@ -304,6 +306,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, omap_up.dma_rx_timeout = info->dma_rx_timeout; omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; omap_up.autosuspend_timeout = info->autosuspend_timeout; + omap_up.DTR_gpio = info->DTR_gpio; + omap_up.DTR_inverted = info->DTR_inverted; + omap_up.DTR_present = info->DTR_present; pdata = &omap_up; pdata_size = sizeof(struct omap_uart_port_info); @@ -313,8 +318,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, NULL, 0, false); - WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", - name, oh->name); + if (IS_ERR(pdev)) { + WARN(1, "Could not build omap_device for %s: %s.\n", name, + oh->name); + return; + } if ((console_uart_id == bdata->id) && no_console_suspend) omap_device_disable_idle_on_suspend(pdev); diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index d4bf904d84ab..ce0ccd26efbd 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S @@ -28,8 +28,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <plat/omap24xx.h> - +#include "omap24xx.h" #include "sdrc.h" /* First address of reserved address space? apparently valid for OMAP2 & 3 */ diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 1f62f23673fb..506987979c1c 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -26,9 +26,9 @@ #include <asm/assembler.h> -#include <plat/hardware.h> #include <plat/sram.h> +#include "omap34xx.h" #include "iomap.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S index 91e71d8f46f0..88ff83a0942e 100644 --- a/arch/arm/mach-omap2/sleep44xx.S +++ b/arch/arm/mach-omap2/sleep44xx.S @@ -14,10 +14,10 @@ #include <asm/memory.h> #include <asm/hardware/cache-l2x0.h> -#include <plat/omap44xx.h> -#include <mach/omap-secure.h> +#include "omap-secure.h" #include "common.h" +#include "omap44xx.h" #include "omap4-sar-layout.h" #if defined(CONFIG_SMP) && defined(CONFIG_PM) diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h new file mode 100644 index 000000000000..fc9b96daf851 --- /dev/null +++ b/arch/arm/mach-omap2/soc.h @@ -0,0 +1,7 @@ +#include <plat/cpu.h> +#include "omap24xx.h" +#include "omap34xx.h" +#include "omap44xx.h" +#include "ti81xx.h" +#include "am33xx.h" +#include "omap54xx.h" diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index d033a65f4e4e..cbeae56b56a9 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); if (!sr_data) { - pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n", - __func__, oh->name); + pr_err("%s: Unable to allocate memory for %s sr_data\n", + __func__, oh->name); return -ENOMEM; } sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { - pr_err("%s: No voltage domain specified for %s." - "Cannot initialize\n", __func__, - oh->name); + pr_err("%s: No voltage domain specified for %s. Cannot initialize\n", + __func__, oh->name); goto exit; } @@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) omap_voltage_get_volttable(sr_data->voltdm, &volt_data); if (!volt_data) { - pr_warning("%s: No Voltage table registered fo VDD%d." - "Something really wrong\n\n", __func__, i + 1); + pr_err("%s: No Voltage table registered for VDD%d\n", + __func__, i + 1); goto exit; } diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index ee0bfcc1410f..8f7326cd435b 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -32,8 +32,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index d4d39ef04769..b140d6578529 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -32,8 +32,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index df5a21322b0a..2d0ceaa23fb8 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -29,8 +29,7 @@ #include <asm/assembler.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "sdrc.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h index 8f9843f78422..8f9843f78422 100644 --- a/arch/arm/plat-omap/include/plat/ti81xx.h +++ b/arch/arm/mach-omap2/ti81xx.h diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ff6d41ec6c6..8847d6eb2313 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -36,16 +36,20 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/slab.h> +#include <linux/of.h> #include <asm/mach/time.h> -#include <plat/dmtimer.h> #include <asm/smp_twd.h> #include <asm/sched_clock.h> -#include "common.h" + +#include <asm/arch_timer.h> #include <plat/omap_hwmod.h> #include <plat/omap_device.h> +#include <plat/dmtimer.h> #include <plat/omap-pm.h> +#include "soc.h" +#include "common.h" #include "powerdomain.h" /* Parent clocks, eventually these will come from the clock framework */ @@ -69,6 +73,11 @@ #define OMAP3_SECURE_TIMER 1 #endif +#define REALTIME_COUNTER_BASE 0x48243200 +#define INCREMENTER_NUMERATOR_OFFSET 0x10 +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 + /* Clockevent code */ static struct omap_dm_timer clkev; @@ -211,7 +220,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); BUG_ON(res); - omap2_gp_timer_irq.dev_id = (void *)&clkev; + omap2_gp_timer_irq.dev_id = &clkev; setup_irq(clkev.irq, &omap2_gp_timer_irq); __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); @@ -260,6 +269,7 @@ static u32 notrace dmtimer_read_sched_clock(void) return 0; } +#ifdef CONFIG_OMAP_32K_TIMER /* Setup free-running counter for clocksource */ static int __init omap2_sync32k_clocksource_init(void) { @@ -299,6 +309,12 @@ static int __init omap2_sync32k_clocksource_init(void) return ret; } +#else +static inline int omap2_sync32k_clocksource_init(void) +{ + return -ENODEV; +} +#endif static void __init omap2_gptimer_clocksource_init(int gptimer_id, const char *fck_source) @@ -339,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id, omap2_gptimer_clocksource_init(gptimer_id, fck_source); } +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER +/* + * The realtime counter also called master counter, is a free-running + * counter, which is related to real time. It produces the count used + * by the CPU local timer peripherals in the MPU cluster. The timer counts + * at a rate of 6.144 MHz. Because the device operates on different clocks + * in different power modes, the master counter shifts operation between + * clocks, adjusting the increment per clock in hardware accordingly to + * maintain a constant count rate. + */ +static void __init realtime_counter_init(void) +{ + void __iomem *base; + static struct clk *sys_clk; + unsigned long rate; + unsigned int reg, num, den; + + base = ioremap(REALTIME_COUNTER_BASE, SZ_32); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + sys_clk = clk_get(NULL, "sys_clkin_ck"); + if (!sys_clk) { + pr_err("%s: failed to get system clock handle\n", __func__); + iounmap(base); + return; + } + + rate = clk_get_rate(sys_clk); + /* Numerator/denumerator values refer TRM Realtime Counter section */ + switch (rate) { + case 1200000: + num = 64; + den = 125; + break; + case 1300000: + num = 768; + den = 1625; + break; + case 19200000: + num = 8; + den = 25; + break; + case 2600000: + num = 384; + den = 1625; + break; + case 2700000: + num = 256; + den = 1125; + break; + case 38400000: + default: + /* Program it for 38.4 MHz */ + num = 4; + den = 25; + break; + } + + /* Program numerator and denumerator registers */ + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= num; + __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); + + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= den; + __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + + iounmap(base); +} +#else +static inline void __init realtime_counter_init(void) +{} +#endif + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ @@ -373,8 +467,7 @@ OMAP_SYS_TIMER(3_am33xx) #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, - OMAP44XX_LOCAL_TWD_BASE, - OMAP44XX_IRQ_LOCALTIMER); + OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START); #endif static void __init omap4_timer_init(void) @@ -386,6 +479,11 @@ static void __init omap4_timer_init(void) if (omap_rev() != OMAP4430_REV_ES1_0) { int err; + if (of_have_populated_dt()) { + twd_local_timer_of_register(); + return; + } + err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); @@ -396,7 +494,18 @@ OMAP_SYS_TIMER(4) #endif #ifdef CONFIG_SOC_OMAP5 -OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) +static void __init omap5_timer_init(void) +{ + int err; + + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_clocksource_init(2, OMAP4_MPU_SOURCE); + realtime_counter_init(); + + err = arch_timer_of_register(); + if (err) + pr_err("%s: arch_timer_register failed %d\n", __func__, err); +} OMAP_SYS_TIMER(5) #endif diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index db5ff6642375..45f77413c21d 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -29,6 +29,7 @@ #include <plat/i2c.h> #include <plat/usb.h> +#include "soc.h" #include "twl-common.h" #include "pm.h" #include "voltage.h" @@ -39,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = { .flags = I2C_CLIENT_WAKE, }; -static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { - { - .addr = 0x48, - .flags = I2C_CLIENT_WAKE, - }, - { - I2C_BOARD_INFO("twl6040", 0x4b), - }, -}; - #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) static int twl_set_voltage(void *data, int target_uV) { @@ -78,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate, void __init omap4_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *twl6040_data, int twl6040_irq) + struct i2c_board_info *devices, int nr_devices) { /* PMIC part*/ omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); - strncpy(omap4_i2c1_board_info[0].type, pmic_type, - sizeof(omap4_i2c1_board_info[0].type)); - omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; - omap4_i2c1_board_info[0].platform_data = pmic_data; - - /* TWL6040 audio IC part */ - omap4_i2c1_board_info[1].irq = twl6040_irq; - omap4_i2c1_board_info[1].platform_data = twl6040_data; - - omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2); + omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data); + /* Register additional devices on i2c1 bus if needed */ + if (devices) + i2c_register_board_info(1, devices, nr_devices); } void __init omap_pmic_late_init(void) { - /* Init the OMAP TWL parameters (if PMIC has been registered) */ - if (pmic_i2c_board_info.irq) - omap3_twl_init(); - if (omap4_i2c1_board_info[0].irq) - omap4_twl_init(); + /* Init the OMAP TWL parameters (if PMIC has been registerd) */ + if (!pmic_i2c_board_info.irq) + return; + + omap3_twl_init(); + omap4_twl_init(); } #if defined(CONFIG_ARCH_OMAP3) @@ -251,11 +237,6 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, #if defined(CONFIG_ARCH_OMAP4) static struct twl4030_usb_data omap4_usb_pdata = { - .phy_init = omap4430_phy_init, - .phy_exit = omap4430_phy_exit, - .phy_power = omap4430_phy_power, - .phy_set_clock = omap4430_phy_set_clk, - .phy_suspend = omap4430_phy_suspend, }; static struct regulator_init_data omap4_vdac_idata = { diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 8fe71cfd002c..2256efe90cf1 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h @@ -1,7 +1,7 @@ #ifndef __OMAP_PMIC_COMMON__ #define __OMAP_PMIC_COMMON__ -#include <plat/irqs.h> +#include "common.h" #define TWL_COMMON_PDATA_USB (1 << 0) #define TWL_COMMON_PDATA_BCI (1 << 1) @@ -32,6 +32,7 @@ struct twl4030_platform_data; struct twl6040_platform_data; +struct i2c_board_info; void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data); @@ -40,18 +41,18 @@ void omap_pmic_late_init(void); static inline void omap2_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data) { - omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data); + omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); } static inline void omap3_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data) { - omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); + omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data); } void omap4_pmic_init(const char *pmic_type, struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *audio_data, int twl6040_irq); + struct i2c_board_info *devices, int nr_devices); void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index dde8a11f47d5..ac95daaa4702 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -25,8 +25,6 @@ #include <asm/io.h> -#include <mach/hardware.h> -#include <mach/irqs.h> #include <plat/usb.h> #include <plat/omap_device.h> diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index c4a576856661..51da21cb78f1 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -23,14 +23,13 @@ #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/io.h> - #include <linux/usb/musb.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/am35xx.h> #include <plat/usb.h> #include <plat/omap_device.h> + +#include "am35xx.h" + #include "mux.h" static struct musb_hdrc_config musb_config = { @@ -117,7 +116,4 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) dev->dma_mask = &musb_dmamask; dev->coherent_dma_mask = musb_dmamask; put_device(dev); - - if (cpu_is_omap44xx()) - omap4430_phy_init(dev); } diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 84da34f9a7cf..880249b17012 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -12,8 +12,7 @@ #include <linux/init.h> #include <linux/bug.h> -#include <plat/cpu.h> - +#include "soc.h" #include "voltage.h" #include "vc.h" #include "prm-regbits-34xx.h" @@ -116,9 +115,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm, } if (!voltdm->pmic->uv_to_vsel) { - pr_err("%s: PMIC function to convert voltage in uV to" - "vsel not registered. Hence unable to scale voltage" - "for vdd_%s\n", __func__, voltdm->name); + pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", + __func__, voltdm->name); return -ENODATA; } diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 4dc60e83e00d..3ac8fe1d8213 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, return &voltdm->volt_data[i]; } - pr_notice("%s: Unable to match the current voltage with the voltage" - "table for vdd_%s\n", __func__, voltdm->name); + pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n", + __func__, voltdm->name); return ERR_PTR(-ENODATA); } @@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm, voltdm->scale = omap_vc_bypass_scale; return; default: - pr_warning("%s: Trying to change the method of voltage scaling" - "to an unsupported one!\n", __func__); + pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n", + __func__); } } @@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm) if (!voltdm || !pwrdm) return -EINVAL; - pr_debug("voltagedomain: associating powerdomain %s with voltagedomain " - "%s\n", pwrdm->name, voltdm->name); + pr_debug("voltagedomain: %s: associating powerdomain %s\n", + voltdm->name, pwrdm->name); list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list); diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 0ac2caf15941..7283b7ed7de8 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -16,7 +16,7 @@ #include <linux/err.h> -#include <plat/voltage.h> +#include <linux/platform_data/voltage-omap.h> #include "vc.h" #include "vp.h" diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c index d0103c80d040..63afbfed3cbc 100644 --- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -18,9 +18,8 @@ #include <linux/err.h> #include <linux/init.h> +#include "soc.h" #include "common.h" -#include <plat/cpu.h> - #include "prm-regbits-34xx.h" #include "omap_opp_data.h" #include "voltage.h" diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c index f95c1bad9dc6..85241b828c02 100644 --- a/arch/arm/mach-omap2/vp.c +++ b/arch/arm/mach-omap2/vp.c @@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, udelay(1); } if (timeout >= VP_TRANXDONE_TIMEOUT) { - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." - "Voltage change aborted", __func__, voltdm->name); + pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted", + __func__, voltdm->name); return -ETIMEDOUT; } @@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, omap_test_timeout(vp->common->ops->check_txdone(vp->id), VP_TRANXDONE_TIMEOUT, timeout); if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_err("%s: vdd_%s TRANXDONE timeout exceeded." - "TRANXDONE never got set after the voltage update\n", - __func__, voltdm->name); + pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n", + __func__, voltdm->name); omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); @@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm, } if (timeout >= VP_TRANXDONE_TIMEOUT) - pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" - "to clear the TRANXDONE status\n", + pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n", __func__, voltdm->name); /* Clear force bit */ @@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm) /* If VP is already disabled, do nothing. Return */ if (!vp->enabled) { - pr_warning("%s: Trying to disable VP for vdd_%s when" - "it is already disabled\n", __func__, voltdm->name); + pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n", + __func__, voltdm->name); return; } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 410291c67666..2fdd4e4f559a 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -47,16 +47,6 @@ static struct map_desc orion5x_io_desc[] __initdata = { .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), - .length = ORION5X_PCIE_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), - .length = ORION5X_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { .virtual = ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, @@ -204,6 +194,13 @@ void __init orion5x_wdt_init(void) void __init orion5x_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); + + /* + * Some Orion5x devices allocate their coherent buffers from atomic + * context. Increase size of atomic coherent pool to make sure such + * the allocations won't fail. + */ + init_dma_coherent_pool_size(SZ_1M); } int orion5x_tclk; diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h deleted file mode 100644 index 1aa5d0a50a0b..000000000000 --- a/arch/arm/mach-orion5x/include/mach/io.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include <mach/orion5x.h> -#include <asm/sizes.h> - -#define IO_SPACE_LIMIT SZ_2M -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE); -} - -#define __io(a) __io(a) -#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 683e085ce162..1b60131b7f60 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -31,31 +31,29 @@ * fc000000 device bus mappings (cs0/cs1) * * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + * fe000000 f1000000 1M on-chip peripheral registers + * fee00000 f2000000 64K PCIe I/O space + * fee10000 f2100000 64K PCI I/O space + * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_VIRT_BASE 0xfe000000 #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_1M +#define ORION5X_PCIE_IO_SIZE SZ_64K #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION5X_PCI_IO_BUS_BASE 0x00100000 -#define ORION5X_PCI_IO_SIZE SZ_1M +#define ORION5X_PCI_IO_BUS_BASE 0x00010000 +#define ORION5X_PCI_IO_SIZE SZ_64K #define ORION5X_SRAM_PHYS_BASE (0xf2200000) #define ORION5X_SRAM_SIZE SZ_8K /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000 #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index cb19e1661bb3..6921d49b988d 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys) pcie_ops.read = pcie_rd_conf_wa; } + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); + /* * Request resources. */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pcie_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - sys->io_offset = 0; - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - - /* * IORESOURCE_MEM */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCIe Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCIE_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } @@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys) */ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); + /* * Request resources */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("pci_setup unable to alloc resources"); /* - * IORESOURCE_IO - */ - sys->io_offset = 0; - res[0].name = "PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCI IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - - /* * IORESOURCE_MEM */ - res[1].name = "PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) + res->name = "PCI Memory Space"; + res->flags = IORESOURCE_MEM; + res->start = ORION5X_PCI_MEM_PHYS_BASE; + res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, res)) panic("Request PCI Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); return 1; } diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index b4203277f3cd..b0727dcd1ef9 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -36,7 +36,7 @@ * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE */ #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000 -#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 +#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000) #define TS78XX_FPGA_REGS_SIZE SZ_1M static struct ts78xx_fpga_data ts78xx_fpga = { @@ -50,7 +50,7 @@ static struct ts78xx_fpga_data ts78xx_fpga = { ****************************************************************************/ static struct map_desc ts78xx_io_desc[] __initdata = { { - .virtual = TS78XX_FPGA_REGS_VIRT_BASE, + .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE, .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE), .length = TS78XX_FPGA_REGS_SIZE, .type = MT_DEVICE, @@ -80,8 +80,8 @@ static struct mv_sata_platform_data ts78xx_sata_data = { /***************************************************************************** * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c ****************************************************************************/ -#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) -#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) +#define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x808) +#define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE + 0x80c) static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr) { @@ -162,8 +162,8 @@ static void ts78xx_ts_rtc_unload(void) /***************************************************************************** * NAND Flash ****************************************************************************/ -#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */ -#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */ +#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */ +#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */ /* * hardware specific access to control-lines diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile deleted file mode 100644 index 777564c90a12..000000000000 --- a/arch/arm/mach-pnx4008/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o -obj-m := -obj-n := -obj- := - -# Power Management -obj-$(CONFIG_PM) += pm.o sleep.o - diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot deleted file mode 100644 index 9fa19baa7f2e..000000000000 --- a/arch/arm/mach-pnx4008/Makefile.boot +++ /dev/null @@ -1,4 +0,0 @@ - zreladdr-y += 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 - diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c deleted file mode 100644 index a4a3819c96cb..000000000000 --- a/arch/arm/mach-pnx4008/clock.c +++ /dev/null @@ -1,1001 +0,0 @@ -/* - * arch/arm/mach-pnx4008/clock.c - * - * Clock control driver for PNX4008 - * - * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> - * Generic clock management functions are partially based on: - * linux/arch/arm/mach-omap/clock.c - * - * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/device.h> -#include <linux/err.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <mach/hardware.h> -#include <mach/clock.h> -#include "clock.h" - -/*forward declaration*/ -static struct clk per_ck; -static struct clk hclk_ck; -static struct clk ck_1MHz; -static struct clk ck_13MHz; -static struct clk ck_pll1; -static int local_set_rate(struct clk *clk, u32 rate); - -static inline void clock_lock(void) -{ - local_irq_disable(); -} - -static inline void clock_unlock(void) -{ - local_irq_enable(); -} - -static void propagate_rate(struct clk *clk) -{ - struct clk *tmp_clk; - - tmp_clk = clk; - while (tmp_clk->propagate_next) { - tmp_clk = tmp_clk->propagate_next; - local_set_rate(tmp_clk, tmp_clk->user_rate); - } -} - -static void clk_reg_disable(struct clk *clk) -{ - if (clk->enable_reg) - __raw_writel(__raw_readl(clk->enable_reg) & - ~(1 << clk->enable_shift), clk->enable_reg); -} - -static int clk_reg_enable(struct clk *clk) -{ - if (clk->enable_reg) - __raw_writel(__raw_readl(clk->enable_reg) | - (1 << clk->enable_shift), clk->enable_reg); - return 0; -} - -static inline void clk_reg_disable1(struct clk *clk) -{ - if (clk->enable_reg1) - __raw_writel(__raw_readl(clk->enable_reg1) & - ~(1 << clk->enable_shift1), clk->enable_reg1); -} - -static inline void clk_reg_enable1(struct clk *clk) -{ - if (clk->enable_reg1) - __raw_writel(__raw_readl(clk->enable_reg1) | - (1 << clk->enable_shift1), clk->enable_reg1); -} - -static int clk_wait_for_pll_lock(struct clk *clk) -{ - int i; - i = 0; - while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */ - - if (!(__raw_readl(clk->scale_reg) & 1)) { - printk(KERN_ERR - "%s ERROR: failed to lock, scale reg data: %x\n", - clk->name, __raw_readl(clk->scale_reg)); - return -1; - } - return 0; -} - -static int switch_to_dirty_13mhz(struct clk *clk) -{ - int i; - int ret; - u32 tmp_reg; - - ret = 0; - - if (!clk->rate) - clk_reg_enable1(clk); - - tmp_reg = __raw_readl(clk->parent_switch_reg); - /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */ - if (!(tmp_reg & 1)) { - tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */ - __raw_writel(tmp_reg, clk->parent_switch_reg); - i = 0; - while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */ - - if (!(__raw_readl(clk->parent_switch_reg) & 1)) { - printk(KERN_ERR - "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n", - clk->name, __raw_readl(clk->parent_switch_reg)); - ret = -1; - } - } - - if (!clk->rate) - clk_reg_disable1(clk); - - return ret; -} - -static int switch_to_clean_13mhz(struct clk *clk) -{ - int i; - int ret; - u32 tmp_reg; - - ret = 0; - - if (!clk->rate) - clk_reg_enable1(clk); - - tmp_reg = __raw_readl(clk->parent_switch_reg); - /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */ - if (tmp_reg & 1) { - tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */ - __raw_writel(tmp_reg, clk->parent_switch_reg); - i = 0; - while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */ - - if (__raw_readl(clk->parent_switch_reg) & 1) { - printk(KERN_ERR - "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n", - clk->name, __raw_readl(clk->parent_switch_reg)); - ret = -1; - } - } - - if (!clk->rate) - clk_reg_disable1(clk); - - return ret; -} - -static int set_13MHz_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - - if (parent == &ck_13MHz) - ret = switch_to_clean_13mhz(clk); - else if (parent == &ck_pll1) - ret = switch_to_dirty_13mhz(clk); - - return ret; -} - -#define PLL160_MIN_FCCO 156000 -#define PLL160_MAX_FCCO 320000 - -/* - * Calculate pll160 settings. - * Possible input: up to 320MHz with step of clk->parent->rate. - * In PNX4008 parent rate for pll160s may be either 1 or 13MHz. - * Ignored paths: "feedback" (bit 13 set), "div-by-N". - * Setting ARM PLL4 rate to 0 will put CPU into direct run mode. - * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input. - * Please refer to PNX4008 IC manual for details. - */ - -static int pll160_set_rate(struct clk *clk, u32 rate) -{ - u32 tmp_reg, tmp_m, tmp_2p, i; - u32 parent_rate; - int ret = -EINVAL; - - parent_rate = clk->parent->rate; - - if (!parent_rate) - goto out; - - /* set direct run for ARM or disable output for others */ - clk_reg_disable(clk); - - /* disable source input as well (ignored for ARM) */ - clk_reg_disable1(clk); - - tmp_reg = __raw_readl(clk->scale_reg); - tmp_reg &= ~0x1ffff; /*clear all settings, power down */ - __raw_writel(tmp_reg, clk->scale_reg); - - rate -= rate % parent_rate; /*round down the input */ - - if (rate > PLL160_MAX_FCCO) - rate = PLL160_MAX_FCCO; - - if (!rate) { - clk->rate = 0; - ret = 0; - goto out; - } - - clk_reg_enable1(clk); - tmp_reg = __raw_readl(clk->scale_reg); - - if (rate == parent_rate) { - /*enter direct bypass mode */ - tmp_reg |= ((1 << 14) | (1 << 15)); - __raw_writel(tmp_reg, clk->scale_reg); - clk->rate = parent_rate; - clk_reg_enable(clk); - ret = 0; - goto out; - } - - i = 0; - for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) { - if (rate * tmp_2p >= PLL160_MIN_FCCO) - break; - i++; - } - - if (tmp_2p > 1) - tmp_reg |= ((i - 1) << 11); - else - tmp_reg |= (1 << 14); /*direct mode, no divide */ - - tmp_m = rate * tmp_2p; - tmp_m /= parent_rate; - - tmp_reg |= (tmp_m - 1) << 1; /*calculate M */ - tmp_reg |= (1 << 16); /*power up PLL */ - __raw_writel(tmp_reg, clk->scale_reg); - - if (clk_wait_for_pll_lock(clk) < 0) { - clk_reg_disable(clk); - clk_reg_disable1(clk); - - tmp_reg = __raw_readl(clk->scale_reg); - tmp_reg &= ~0x1ffff; /*clear all settings, power down */ - __raw_writel(tmp_reg, clk->scale_reg); - clk->rate = 0; - ret = -EFAULT; - goto out; - } - - clk->rate = (tmp_m * parent_rate) / tmp_2p; - - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); - - clk_reg_enable(clk); - ret = 0; - -out: - return ret; -} - -/*configure PER_CLK*/ -static int per_clk_set_rate(struct clk *clk, u32 rate) -{ - u32 tmp; - - tmp = __raw_readl(clk->scale_reg); - tmp &= ~(0x1f << 2); - tmp |= ((clk->parent->rate / clk->rate) - 1) << 2; - __raw_writel(tmp, clk->scale_reg); - clk->rate = rate; - return 0; -} - -/*configure HCLK*/ -static int hclk_set_rate(struct clk *clk, u32 rate) -{ - u32 tmp; - tmp = __raw_readl(clk->scale_reg); - tmp = tmp & ~0x3; - switch (rate) { - case 1: - break; - case 2: - tmp |= 1; - break; - case 4: - tmp |= 2; - break; - } - - __raw_writel(tmp, clk->scale_reg); - clk->rate = rate; - return 0; -} - -static u32 hclk_round_rate(struct clk *clk, u32 rate) -{ - switch (rate) { - case 1: - case 4: - return rate; - } - return 2; -} - -static u32 per_clk_round_rate(struct clk *clk, u32 rate) -{ - return CLK_RATE_13MHZ; -} - -static int on_off_set_rate(struct clk *clk, u32 rate) -{ - if (rate) { - clk_reg_enable(clk); - clk->rate = 1; - } else { - clk_reg_disable(clk); - clk->rate = 0; - } - return 0; -} - -static int on_off_inv_set_rate(struct clk *clk, u32 rate) -{ - if (rate) { - clk_reg_disable(clk); /*enable bit is inverted */ - clk->rate = 1; - } else { - clk_reg_enable(clk); - clk->rate = 0; - } - return 0; -} - -static u32 on_off_round_rate(struct clk *clk, u32 rate) -{ - return (rate ? 1 : 0); -} - -static u32 pll4_round_rate(struct clk *clk, u32 rate) -{ - if (rate > CLK_RATE_208MHZ) - rate = CLK_RATE_208MHZ; - if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1) - rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ; - return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ))); -} - -static u32 pll3_round_rate(struct clk *clk, u32 rate) -{ - if (rate > CLK_RATE_208MHZ) - rate = CLK_RATE_208MHZ; - return (rate - rate % CLK_RATE_13MHZ); -} - -static u32 pll5_round_rate(struct clk *clk, u32 rate) -{ - return (rate ? CLK_RATE_48MHZ : 0); -} - -static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate) -{ - return (rate ? CLK_RATE_13MHZ : 0); -} - -static int ck_13MHz_set_rate(struct clk *clk, u32 rate) -{ - if (rate) { - clk_reg_disable(clk); /*enable bit is inverted */ - udelay(500); - clk->rate = CLK_RATE_13MHZ; - ck_1MHz.rate = CLK_RATE_1MHZ; - } else { - clk_reg_enable(clk); - clk->rate = 0; - ck_1MHz.rate = 0; - } - return 0; -} - -static int pll1_set_rate(struct clk *clk, u32 rate) -{ -#if 0 /* doesn't work on some boards, probably a HW BUG */ - if (rate) { - clk_reg_disable(clk); /*enable bit is inverted */ - if (!clk_wait_for_pll_lock(clk)) { - clk->rate = CLK_RATE_13MHZ; - } else { - clk_reg_enable(clk); - clk->rate = 0; - } - - } else { - clk_reg_enable(clk); - clk->rate = 0; - } -#endif - return 0; -} - -/* Clock sources */ - -static struct clk osc_13MHz = { - .name = "osc_13MHz", - .flags = FIXED_RATE, - .rate = CLK_RATE_13MHZ, -}; - -static struct clk ck_13MHz = { - .name = "ck_13MHz", - .parent = &osc_13MHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &ck_13MHz_round_rate, - .set_rate = &ck_13MHz_set_rate, - .enable_reg = OSC13CTRL_REG, - .enable_shift = 0, - .rate = CLK_RATE_13MHZ, -}; - -static struct clk osc_32KHz = { - .name = "osc_32KHz", - .flags = FIXED_RATE, - .rate = CLK_RATE_32KHZ, -}; - -/*attached to PLL5*/ -static struct clk ck_1MHz = { - .name = "ck_1MHz", - .flags = FIXED_RATE | PARENT_SET_RATE, - .parent = &ck_13MHz, -}; - -/* PLL1 (397) - provides 13' MHz clock */ -static struct clk ck_pll1 = { - .name = "ck_pll1", - .parent = &osc_32KHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &ck_13MHz_round_rate, - .set_rate = &pll1_set_rate, - .enable_reg = PLLCTRL_REG, - .enable_shift = 1, - .scale_reg = PLLCTRL_REG, - .rate = CLK_RATE_13MHZ, -}; - -/* CPU/Bus PLL */ -static struct clk ck_pll4 = { - .name = "ck_pll4", - .parent = &ck_pll1, - .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION, - .propagate_next = &per_ck, - .round_rate = &pll4_round_rate, - .set_rate = &pll160_set_rate, - .rate = CLK_RATE_208MHZ, - .scale_reg = HCLKPLLCTRL_REG, - .enable_reg = PWRCTRL_REG, - .enable_shift = 2, - .parent_switch_reg = SYSCLKCTRL_REG, - .set_parent = &set_13MHz_parent, -}; - -/* USB PLL */ -static struct clk ck_pll5 = { - .name = "ck_pll5", - .parent = &ck_1MHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &pll5_round_rate, - .set_rate = &pll160_set_rate, - .scale_reg = USBCTRL_REG, - .enable_reg = USBCTRL_REG, - .enable_shift = 18, - .enable_reg1 = USBCTRL_REG, - .enable_shift1 = 17, -}; - -/* XPERTTeak DSP PLL */ -static struct clk ck_pll3 = { - .name = "ck_pll3", - .parent = &ck_pll1, - .flags = NEEDS_INITIALIZATION, - .round_rate = &pll3_round_rate, - .set_rate = &pll160_set_rate, - .scale_reg = DSPPLLCTRL_REG, - .enable_reg = DSPCLKCTRL_REG, - .enable_shift = 3, - .enable_reg1 = DSPCLKCTRL_REG, - .enable_shift1 = 2, - .parent_switch_reg = DSPCLKCTRL_REG, - .set_parent = &set_13MHz_parent, -}; - -static struct clk hclk_ck = { - .name = "hclk_ck", - .parent = &ck_pll4, - .flags = PARENT_SET_RATE, - .set_rate = &hclk_set_rate, - .round_rate = &hclk_round_rate, - .scale_reg = HCLKDIVCTRL_REG, - .rate = 2, - .user_rate = 2, -}; - -static struct clk per_ck = { - .name = "per_ck", - .parent = &ck_pll4, - .flags = FIXED_RATE, - .propagate_next = &hclk_ck, - .set_rate = &per_clk_set_rate, - .round_rate = &per_clk_round_rate, - .scale_reg = HCLKDIVCTRL_REG, - .rate = CLK_RATE_13MHZ, - .user_rate = CLK_RATE_13MHZ, -}; - -static struct clk m2hclk_ck = { - .name = "m2hclk_ck", - .parent = &hclk_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_inv_set_rate, - .rate = 1, - .enable_shift = 6, - .enable_reg = PWRCTRL_REG, -}; - -static struct clk vfp9_ck = { - .name = "vfp9_ck", - .parent = &ck_pll4, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .rate = 1, - .enable_shift = 4, - .enable_reg = VFP9CLKCTRL_REG, -}; - -static struct clk keyscan_ck = { - .name = "keyscan_ck", - .parent = &osc_32KHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = KEYCLKCTRL_REG, -}; - -static struct clk touch_ck = { - .name = "touch_ck", - .parent = &osc_32KHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = TSCLKCTRL_REG, -}; - -static struct clk pwm1_ck = { - .name = "pwm1_ck", - .parent = &osc_32KHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = PWMCLKCTRL_REG, -}; - -static struct clk pwm2_ck = { - .name = "pwm2_ck", - .parent = &osc_32KHz, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 2, - .enable_reg = PWMCLKCTRL_REG, -}; - -static struct clk jpeg_ck = { - .name = "jpeg_ck", - .parent = &hclk_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = JPEGCLKCTRL_REG, -}; - -static struct clk ms_ck = { - .name = "ms_ck", - .parent = &ck_pll4, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 5, - .enable_reg = MSCTRL_REG, -}; - -static struct clk dum_ck = { - .name = "dum_ck", - .parent = &hclk_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = DUMCLKCTRL_REG, -}; - -static struct clk flash_ck = { - .name = "flash_ck", - .parent = &hclk_ck, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 1, /* Only MLC clock supported */ - .enable_reg = FLASHCLKCTRL_REG, -}; - -static struct clk i2c0_ck = { - .name = "i2c0_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION | FIXED_RATE, - .enable_shift = 0, - .enable_reg = I2CCLKCTRL_REG, - .rate = 13000000, - .enable = clk_reg_enable, - .disable = clk_reg_disable, -}; - -static struct clk i2c1_ck = { - .name = "i2c1_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION | FIXED_RATE, - .enable_shift = 1, - .enable_reg = I2CCLKCTRL_REG, - .rate = 13000000, - .enable = clk_reg_enable, - .disable = clk_reg_disable, -}; - -static struct clk i2c2_ck = { - .name = "i2c2_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION | FIXED_RATE, - .enable_shift = 2, - .enable_reg = USB_OTG_CLKCTRL_REG, - .rate = 13000000, - .enable = clk_reg_enable, - .disable = clk_reg_disable, -}; - -static struct clk spi0_ck = { - .name = "spi0_ck", - .parent = &hclk_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = SPICTRL_REG, -}; - -static struct clk spi1_ck = { - .name = "spi1_ck", - .parent = &hclk_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 4, - .enable_reg = SPICTRL_REG, -}; - -static struct clk dma_ck = { - .name = "dma_ck", - .parent = &hclk_ck, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 0, - .enable_reg = DMACLKCTRL_REG, -}; - -static struct clk uart3_ck = { - .name = "uart3_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .rate = 1, - .enable_shift = 0, - .enable_reg = UARTCLKCTRL_REG, -}; - -static struct clk uart4_ck = { - .name = "uart4_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 1, - .enable_reg = UARTCLKCTRL_REG, -}; - -static struct clk uart5_ck = { - .name = "uart5_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .rate = 1, - .enable_shift = 2, - .enable_reg = UARTCLKCTRL_REG, -}; - -static struct clk uart6_ck = { - .name = "uart6_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION, - .round_rate = &on_off_round_rate, - .set_rate = &on_off_set_rate, - .enable_shift = 3, - .enable_reg = UARTCLKCTRL_REG, -}; - -static struct clk wdt_ck = { - .name = "wdt_ck", - .parent = &per_ck, - .flags = NEEDS_INITIALIZATION, - .enable_shift = 0, - .enable_reg = TIMCLKCTRL_REG, - .enable = clk_reg_enable, - .disable = clk_reg_disable, -}; - -/* These clocks are visible outside this module - * and can be initialized - */ -static struct clk *onchip_clks[] __initdata = { - &ck_13MHz, - &ck_pll1, - &ck_pll4, - &ck_pll5, - &ck_pll3, - &vfp9_ck, - &m2hclk_ck, - &hclk_ck, - &dma_ck, - &flash_ck, - &dum_ck, - &keyscan_ck, - &pwm1_ck, - &pwm2_ck, - &jpeg_ck, - &ms_ck, - &touch_ck, - &i2c0_ck, - &i2c1_ck, - &i2c2_ck, - &spi0_ck, - &spi1_ck, - &uart3_ck, - &uart4_ck, - &uart5_ck, - &uart6_ck, - &wdt_ck, -}; - -static struct clk_lookup onchip_clkreg[] = { - { .clk = &ck_13MHz, .con_id = "ck_13MHz" }, - { .clk = &ck_pll1, .con_id = "ck_pll1" }, - { .clk = &ck_pll4, .con_id = "ck_pll4" }, - { .clk = &ck_pll5, .con_id = "ck_pll5" }, - { .clk = &ck_pll3, .con_id = "ck_pll3" }, - { .clk = &vfp9_ck, .con_id = "vfp9_ck" }, - { .clk = &m2hclk_ck, .con_id = "m2hclk_ck" }, - { .clk = &hclk_ck, .con_id = "hclk_ck" }, - { .clk = &dma_ck, .con_id = "dma_ck" }, - { .clk = &flash_ck, .con_id = "flash_ck" }, - { .clk = &dum_ck, .con_id = "dum_ck" }, - { .clk = &keyscan_ck, .con_id = "keyscan_ck" }, - { .clk = &pwm1_ck, .con_id = "pwm1_ck" }, - { .clk = &pwm2_ck, .con_id = "pwm2_ck" }, - { .clk = &jpeg_ck, .con_id = "jpeg_ck" }, - { .clk = &ms_ck, .con_id = "ms_ck" }, - { .clk = &touch_ck, .con_id = "touch_ck" }, - { .clk = &i2c0_ck, .dev_id = "pnx-i2c.0" }, - { .clk = &i2c1_ck, .dev_id = "pnx-i2c.1" }, - { .clk = &i2c2_ck, .dev_id = "pnx-i2c.2" }, - { .clk = &spi0_ck, .con_id = "spi0_ck" }, - { .clk = &spi1_ck, .con_id = "spi1_ck" }, - { .clk = &uart3_ck, .con_id = "uart3_ck" }, - { .clk = &uart4_ck, .con_id = "uart4_ck" }, - { .clk = &uart5_ck, .con_id = "uart5_ck" }, - { .clk = &uart6_ck, .con_id = "uart6_ck" }, - { .clk = &wdt_ck, .dev_id = "pnx4008-watchdog" }, -}; - -static void local_clk_disable(struct clk *clk) -{ - if (WARN_ON(clk->usecount == 0)) - return; - - if (!(--clk->usecount)) { - if (clk->disable) - clk->disable(clk); - else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate) - clk->set_rate(clk, 0); - if (clk->parent) - local_clk_disable(clk->parent); - } -} - -static int local_clk_enable(struct clk *clk) -{ - int ret = 0; - - if (clk->usecount == 0) { - if (clk->parent) { - ret = local_clk_enable(clk->parent); - if (ret != 0) - goto out; - } - - if (clk->enable) - ret = clk->enable(clk); - else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate - && clk->user_rate) - ret = clk->set_rate(clk, clk->user_rate); - - if (ret != 0 && clk->parent) { - local_clk_disable(clk->parent); - goto out; - } - - clk->usecount++; - } -out: - return ret; -} - -static int local_set_rate(struct clk *clk, u32 rate) -{ - int ret = -EINVAL; - if (clk->set_rate) { - - if (clk->user_rate == clk->rate && clk->parent->rate) { - /* if clock enabled or rate not set */ - clk->user_rate = clk->round_rate(clk, rate); - ret = clk->set_rate(clk, clk->user_rate); - } else - clk->user_rate = clk->round_rate(clk, rate); - ret = 0; - } - return ret; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (clk->flags & FIXED_RATE) - goto out; - - clock_lock(); - if ((clk->flags & PARENT_SET_RATE) && clk->parent) { - - clk->user_rate = clk->round_rate(clk, rate); - /* parent clock needs to be refreshed - for the setting to take effect */ - } else { - ret = local_set_rate(clk, rate); - } - ret = 0; - clock_unlock(); - -out: - return ret; -} - -EXPORT_SYMBOL(clk_set_rate); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long ret; - clock_lock(); - ret = clk->rate; - clock_unlock(); - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_enable(struct clk *clk) -{ - int ret; - - clock_lock(); - ret = local_clk_enable(clk); - clock_unlock(); - return ret; -} - -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - clock_lock(); - local_clk_disable(clk); - clock_unlock(); -} - -EXPORT_SYMBOL(clk_disable); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - long ret; - clock_lock(); - if (clk->round_rate) - ret = clk->round_rate(clk, rate); - else - ret = clk->rate; - clock_unlock(); - return ret; -} - -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -ENODEV; - if (!clk->set_parent) - goto out; - - clock_lock(); - ret = clk->set_parent(clk, parent); - if (!ret) - clk->parent = parent; - clock_unlock(); - -out: - return ret; -} - -EXPORT_SYMBOL(clk_set_parent); - -static int __init clk_init(void) -{ - struct clk **clkp; - - /* Disable autoclocking, as it doesn't seem to work */ - __raw_writel(0xff, AUTOCLK_CTRL); - - for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); - clkp++) { - struct clk *clk = *clkp; - if (clk->flags & NEEDS_INITIALIZATION) { - if (clk->set_rate) { - clk->user_rate = clk->rate; - local_set_rate(clk, clk->user_rate); - if (clk->set_parent) - clk->set_parent(clk, clk->parent); - } - if (clk->enable && clk->usecount) - clk->enable(clk); - if (clk->disable && !clk->usecount) - clk->disable(clk); - } - pr_debug("%s: clock %s, rate %ld\n", - __func__, clk->name, clk->rate); - } - - local_clk_enable(&ck_pll4); - - /* if ck_13MHz is not used, disable it. */ - if (ck_13MHz.usecount == 0) - local_clk_disable(&ck_13MHz); - - /* Disable autoclocking */ - __raw_writeb(0xff, AUTOCLK_CTRL); - - clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg)); - - return 0; -} - -arch_initcall(clk_init); diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h deleted file mode 100644 index 39720d6c0d01..000000000000 --- a/arch/arm/mach-pnx4008/clock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-pnx4008/clock.h - * - * Clock control driver for PNX4008 - internal header file - * - * Author: Vitaly Wool <source@mvista.com> - * - * 2006 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ARCH_ARM_PNX4008_CLOCK_H__ -#define __ARCH_ARM_PNX4008_CLOCK_H__ - -struct clk { - const char *name; - struct clk *parent; - struct clk *propagate_next; - u32 rate; - u32 user_rate; - s8 usecount; - u32 flags; - u32 scale_reg; - u8 enable_shift; - u32 enable_reg; - u8 enable_shift1; - u32 enable_reg1; - u32 parent_switch_reg; - u32(*round_rate) (struct clk *, u32); - int (*set_rate) (struct clk *, u32); - int (*set_parent) (struct clk * clk, struct clk * parent); - int (*enable)(struct clk *); - void (*disable)(struct clk *); -}; - -/* Flags */ -#define RATE_PROPAGATES (1<<0) -#define NEEDS_INITIALIZATION (1<<1) -#define PARENT_SET_RATE (1<<2) -#define FIXED_RATE (1<<3) - -#endif diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c deleted file mode 100644 index a00d2f1254ed..000000000000 --- a/arch/arm/mach-pnx4008/core.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * arch/arm/mach-pnx4008/core.c - * - * PNX4008 core startup code - * - * Authors: Vitaly Wool, Dmitry Chigirev, - * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com> - * - * Based on reference code received from Philips: - * Copyright (C) 2003 Philips Semiconductors - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/device.h> -#include <linux/spi/spi.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/system_misc.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/irq.h> -#include <mach/clock.h> -#include <mach/dma.h> - -struct resource spipnx_0_resources[] = { - { - .start = PNX4008_SPI1_BASE, - .end = PNX4008_SPI1_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = PER_SPI1_REC_XMIT, - .flags = IORESOURCE_DMA, - }, { - .start = SPI1_INT, - .flags = IORESOURCE_IRQ, - }, { - .flags = 0, - }, -}; - -struct resource spipnx_1_resources[] = { - { - .start = PNX4008_SPI2_BASE, - .end = PNX4008_SPI2_BASE + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = PER_SPI2_REC_XMIT, - .flags = IORESOURCE_DMA, - }, { - .start = SPI2_INT, - .flags = IORESOURCE_IRQ, - }, { - .flags = 0, - } -}; - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "m25p80", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static struct platform_device spipnx_1 = { - .name = "spipnx", - .id = 1, - .num_resources = ARRAY_SIZE(spipnx_0_resources), - .resource = spipnx_0_resources, - .dev = { - .coherent_dma_mask = 0xFFFFFFFF, - }, -}; - -static struct platform_device spipnx_2 = { - .name = "spipnx", - .id = 2, - .num_resources = ARRAY_SIZE(spipnx_1_resources), - .resource = spipnx_1_resources, - .dev = { - .coherent_dma_mask = 0xFFFFFFFF, - }, -}; - -static struct plat_serial8250_port platform_serial_ports[] = { - { - .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)), - .mapbase = (unsigned long)PNX4008_UART5_BASE, - .irq = IIR5_INT, - .uartclk = PNX4008_UART_CLK, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST, - }, - { - .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)), - .mapbase = (unsigned long)PNX4008_UART3_BASE, - .irq = IIR3_INT, - .uartclk = PNX4008_UART_CLK, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST, - }, - {} -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = &platform_serial_ports, - }, -}; - -static struct platform_device nand_flash_device = { - .name = "pnx4008-flash", - .id = -1, - .dev = { - .coherent_dma_mask = 0xFFFFFFFF, - }, -}; - -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32) 0; - -static struct resource ohci_resources[] = { - { - .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE), - .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100), - .flags = IORESOURCE_MEM, - }, { - .start = USB_HOST_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci_device = { - .name = "pnx4008-usb-ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(ohci_resources), - .resource = ohci_resources, -}; - -static struct platform_device sdum_device = { - .name = "pnx4008-sdum", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - -static struct platform_device rgbfb_device = { - .name = "pnx4008-rgbfb", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - } -}; - -struct resource watchdog_resources[] = { - { - .start = PNX4008_WDOG_BASE, - .end = PNX4008_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device watchdog_device = { - .name = "pnx4008-watchdog", - .id = -1, - .num_resources = ARRAY_SIZE(watchdog_resources), - .resource = watchdog_resources, -}; - -static struct platform_device *devices[] __initdata = { - &spipnx_1, - &spipnx_2, - &serial_device, - &ohci_device, - &nand_flash_device, - &sdum_device, - &rgbfb_device, - &watchdog_device, -}; - - -extern void pnx4008_uart_init(void); - -static void __init pnx4008_init(void) -{ - /*disable all START interrupt sources, - and clear all START interrupt flags */ - __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT)); - __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT)); - __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT)); - __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - /* Switch on the UART clocks */ - pnx4008_uart_init(); -} - -static struct map_desc pnx4008_io_desc[] __initdata = { - { - .virtual = IO_ADDRESS(PNX4008_IRAM_BASE), - .pfn = __phys_to_pfn(PNX4008_IRAM_BASE), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(PNX4008_NDF_FLASH_BASE), - .pfn = __phys_to_pfn(PNX4008_NDF_FLASH_BASE), - .length = SZ_1M - SZ_128K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE), - .pfn = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE), - .length = SZ_128K * 3, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE), - .pfn = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(PNX4008_AHB2FAB_BASE), - .pfn = __phys_to_pfn(PNX4008_AHB2FAB_BASE), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -void __init pnx4008_map_io(void) -{ - iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc)); -} - -static void pnx4008_restart(char mode, const char *cmd) -{ - soft_restart(0); -} - -#ifdef CONFIG_PM -extern int pnx4008_pm_init(void); -#else -static inline int pnx4008_pm_init(void) { return 0; } -#endif - -void __init pnx4008_init_late(void) -{ - pnx4008_pm_init(); -} - -extern struct sys_timer pnx4008_timer; - -MACHINE_START(PNX4008, "Philips PNX4008") - /* Maintainer: MontaVista Software Inc. */ - .atag_offset = 0x100, - .map_io = pnx4008_map_io, - .init_irq = pnx4008_init_irq, - .init_machine = pnx4008_init, - .init_late = pnx4008_init_late, - .timer = &pnx4008_timer, - .restart = pnx4008_restart, -MACHINE_END diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c deleted file mode 100644 index a4739e9fb2fb..000000000000 --- a/arch/arm/mach-pnx4008/dma.c +++ /dev/null @@ -1,1105 +0,0 @@ -/* - * linux/arch/arm/mach-pnx4008/dma.c - * - * PNX4008 DMA registration and IRQ dispatching - * - * Author: Vitaly Wool - * Copyright: MontaVista Software Inc. (c) 2005 - * - * Based on the code from Nicolas Pitre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/dma-mapping.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/gfp.h> - -#include <mach/hardware.h> -#include <mach/dma.h> -#include <asm/dma-mapping.h> -#include <mach/clock.h> - -static struct dma_channel { - char *name; - void (*irq_handler) (int, int, void *); - void *data; - struct pnx4008_dma_ll *ll; - u32 ll_dma; - void *target_addr; - int target_id; -} dma_channels[MAX_DMA_CHANNELS]; - -static struct ll_pool { - void *vaddr; - void *cur; - dma_addr_t dma_addr; - int count; -} ll_pool; - -static DEFINE_SPINLOCK(ll_lock); - -struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma) -{ - struct pnx4008_dma_ll *ll = NULL; - unsigned long flags; - - spin_lock_irqsave(&ll_lock, flags); - if (ll_pool.count > 4) { /* can give one more */ - ll = *(struct pnx4008_dma_ll **) ll_pool.cur; - *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr); - *(void **)ll_pool.cur = **(void ***)ll_pool.cur; - memset(ll, 0, sizeof(*ll)); - ll_pool.count--; - } - spin_unlock_irqrestore(&ll_lock, flags); - - return ll; -} - -EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry); - -void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma) -{ - unsigned long flags; - - if (ll) { - if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) { - printk(KERN_ERR "Trying to free entry not allocated by DMA\n"); - BUG(); - } - - if (ll->flags & DMA_BUFFER_ALLOCATED) - ll->free(ll->alloc_data); - - spin_lock_irqsave(&ll_lock, flags); - *(long *)ll = *(long *)ll_pool.cur; - *(long *)ll_pool.cur = (long)ll; - ll_pool.count++; - spin_unlock_irqrestore(&ll_lock, flags); - } -} - -EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry); - -void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll) -{ - struct pnx4008_dma_ll *ptr; - u32 dma; - - while (ll) { - dma = ll->next_dma; - ptr = ll->next; - pnx4008_free_ll_entry(ll, ll_dma); - - ll_dma = dma; - ll = ptr; - } -} - -EXPORT_SYMBOL_GPL(pnx4008_free_ll); - -static int dma_channels_requested = 0; - -static inline void dma_increment_usage(void) -{ - if (!dma_channels_requested++) { - struct clk *clk = clk_get(0, "dma_ck"); - if (!IS_ERR(clk)) { - clk_set_rate(clk, 1); - clk_put(clk); - } - pnx4008_config_dma(-1, -1, 1); - } -} -static inline void dma_decrement_usage(void) -{ - if (!--dma_channels_requested) { - struct clk *clk = clk_get(0, "dma_ck"); - if (!IS_ERR(clk)) { - clk_set_rate(clk, 0); - clk_put(clk); - } - pnx4008_config_dma(-1, -1, 0); - - } -} - -static DEFINE_SPINLOCK(dma_lock); - -static inline void pnx4008_dma_lock(void) -{ - spin_lock_irq(&dma_lock); -} - -static inline void pnx4008_dma_unlock(void) -{ - spin_unlock_irq(&dma_lock); -} - -#define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS)) - -int pnx4008_request_channel(char *name, int ch, - void (*irq_handler) (int, int, void *), void *data) -{ - int i, found = 0; - - /* basic sanity checks */ - if (!name || (ch != -1 && !VALID_CHANNEL(ch))) - return -EINVAL; - - pnx4008_dma_lock(); - - /* try grabbing a DMA channel with the requested priority */ - for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) { - if (!dma_channels[i].name && (ch == -1 || ch == i)) { - found = 1; - break; - } - } - - if (found) { - dma_increment_usage(); - dma_channels[i].name = name; - dma_channels[i].irq_handler = irq_handler; - dma_channels[i].data = data; - dma_channels[i].ll = NULL; - dma_channels[i].ll_dma = 0; - } else { - printk(KERN_WARNING "No more available DMA channels for %s\n", - name); - i = -ENODEV; - } - - pnx4008_dma_unlock(); - return i; -} - -EXPORT_SYMBOL_GPL(pnx4008_request_channel); - -void pnx4008_free_channel(int ch) -{ - if (!dma_channels[ch].name) { - printk(KERN_CRIT - "%s: trying to free channel %d which is already freed\n", - __func__, ch); - return; - } - - pnx4008_dma_lock(); - pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll); - dma_channels[ch].ll = NULL; - dma_decrement_usage(); - - dma_channels[ch].name = NULL; - pnx4008_dma_unlock(); -} - -EXPORT_SYMBOL_GPL(pnx4008_free_channel); - -int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable) -{ - unsigned long dma_cfg = __raw_readl(DMAC_CONFIG); - - switch (ahb_m1_be) { - case 0: - dma_cfg &= ~(1 << 1); - break; - case 1: - dma_cfg |= (1 << 1); - break; - default: - break; - } - - switch (ahb_m2_be) { - case 0: - dma_cfg &= ~(1 << 2); - break; - case 1: - dma_cfg |= (1 << 2); - break; - default: - break; - } - - switch (enable) { - case 0: - dma_cfg &= ~(1 << 0); - break; - case 1: - dma_cfg |= (1 << 0); - break; - default: - break; - } - - pnx4008_dma_lock(); - __raw_writel(dma_cfg, DMAC_CONFIG); - pnx4008_dma_unlock(); - - return 0; -} - -EXPORT_SYMBOL_GPL(pnx4008_config_dma); - -int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl, - unsigned long *ctrl) -{ - int i = 0, dbsize, sbsize, err = 0; - - if (!ctrl || !ch_ctrl) { - err = -EINVAL; - goto out; - } - - *ctrl = 0; - - switch (ch_ctrl->tc_mask) { - case 0: - break; - case 1: - *ctrl |= (1 << 31); - break; - - default: - err = -EINVAL; - goto out; - } - - switch (ch_ctrl->cacheable) { - case 0: - break; - case 1: - *ctrl |= (1 << 30); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->bufferable) { - case 0: - break; - case 1: - *ctrl |= (1 << 29); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->priv_mode) { - case 0: - break; - case 1: - *ctrl |= (1 << 28); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->di) { - case 0: - break; - case 1: - *ctrl |= (1 << 27); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->si) { - case 0: - break; - case 1: - *ctrl |= (1 << 26); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->dest_ahb1) { - case 0: - break; - case 1: - *ctrl |= (1 << 25); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->src_ahb1) { - case 0: - break; - case 1: - *ctrl |= (1 << 24); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->dwidth) { - case WIDTH_BYTE: - *ctrl &= ~(7 << 21); - break; - case WIDTH_HWORD: - *ctrl &= ~(7 << 21); - *ctrl |= (1 << 21); - break; - case WIDTH_WORD: - *ctrl &= ~(7 << 21); - *ctrl |= (2 << 21); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_ctrl->swidth) { - case WIDTH_BYTE: - *ctrl &= ~(7 << 18); - break; - case WIDTH_HWORD: - *ctrl &= ~(7 << 18); - *ctrl |= (1 << 18); - break; - case WIDTH_WORD: - *ctrl &= ~(7 << 18); - *ctrl |= (2 << 18); - break; - - default: - err = -EINVAL; - goto out; - } - dbsize = ch_ctrl->dbsize; - while (!(dbsize & 1)) { - i++; - dbsize >>= 1; - } - if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) { - err = -EINVAL; - goto out; - } else if (i > 1) - i--; - *ctrl &= ~(7 << 15); - *ctrl |= (i << 15); - - sbsize = ch_ctrl->sbsize; - while (!(sbsize & 1)) { - i++; - sbsize >>= 1; - } - if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) { - err = -EINVAL; - goto out; - } else if (i > 1) - i--; - *ctrl &= ~(7 << 12); - *ctrl |= (i << 12); - - if (ch_ctrl->tr_size > 0x7ff) { - err = -E2BIG; - goto out; - } - *ctrl &= ~0x7ff; - *ctrl |= ch_ctrl->tr_size & 0x7ff; - -out: - return err; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control); - -int pnx4008_dma_parse_control(unsigned long ctrl, - struct pnx4008_dma_ch_ctrl * ch_ctrl) -{ - int err = 0; - - if (!ch_ctrl) { - err = -EINVAL; - goto out; - } - - ch_ctrl->tr_size = ctrl & 0x7ff; - ctrl >>= 12; - - ch_ctrl->sbsize = 1 << (ctrl & 7); - if (ch_ctrl->sbsize > 1) - ch_ctrl->sbsize <<= 1; - ctrl >>= 3; - - ch_ctrl->dbsize = 1 << (ctrl & 7); - if (ch_ctrl->dbsize > 1) - ch_ctrl->dbsize <<= 1; - ctrl >>= 3; - - switch (ctrl & 7) { - case 0: - ch_ctrl->swidth = WIDTH_BYTE; - break; - case 1: - ch_ctrl->swidth = WIDTH_HWORD; - break; - case 2: - ch_ctrl->swidth = WIDTH_WORD; - break; - default: - err = -EINVAL; - goto out; - } - ctrl >>= 3; - - switch (ctrl & 7) { - case 0: - ch_ctrl->dwidth = WIDTH_BYTE; - break; - case 1: - ch_ctrl->dwidth = WIDTH_HWORD; - break; - case 2: - ch_ctrl->dwidth = WIDTH_WORD; - break; - default: - err = -EINVAL; - goto out; - } - ctrl >>= 3; - - ch_ctrl->src_ahb1 = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->dest_ahb1 = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->si = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->di = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->priv_mode = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->bufferable = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->cacheable = ctrl & 1; - ctrl >>= 1; - - ch_ctrl->tc_mask = ctrl & 1; - -out: - return err; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control); - -int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg, - unsigned long *cfg) -{ - int err = 0; - - if (!cfg || !ch_cfg) { - err = -EINVAL; - goto out; - } - - *cfg = 0; - - switch (ch_cfg->halt) { - case 0: - break; - case 1: - *cfg |= (1 << 18); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_cfg->active) { - case 0: - break; - case 1: - *cfg |= (1 << 17); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_cfg->lock) { - case 0: - break; - case 1: - *cfg |= (1 << 16); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_cfg->itc) { - case 0: - break; - case 1: - *cfg |= (1 << 15); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_cfg->ie) { - case 0: - break; - case 1: - *cfg |= (1 << 14); - break; - - default: - err = -EINVAL; - goto out; - } - switch (ch_cfg->flow_cntrl) { - case FC_MEM2MEM_DMA: - *cfg &= ~(7 << 11); - break; - case FC_MEM2PER_DMA: - *cfg &= ~(7 << 11); - *cfg |= (1 << 11); - break; - case FC_PER2MEM_DMA: - *cfg &= ~(7 << 11); - *cfg |= (2 << 11); - break; - case FC_PER2PER_DMA: - *cfg &= ~(7 << 11); - *cfg |= (3 << 11); - break; - case FC_PER2PER_DPER: - *cfg &= ~(7 << 11); - *cfg |= (4 << 11); - break; - case FC_MEM2PER_PER: - *cfg &= ~(7 << 11); - *cfg |= (5 << 11); - break; - case FC_PER2MEM_PER: - *cfg &= ~(7 << 11); - *cfg |= (6 << 11); - break; - case FC_PER2PER_SPER: - *cfg |= (7 << 11); - break; - - default: - err = -EINVAL; - goto out; - } - *cfg &= ~(0x1f << 6); - *cfg |= ((ch_cfg->dest_per & 0x1f) << 6); - - *cfg &= ~(0x1f << 1); - *cfg |= ((ch_cfg->src_per & 0x1f) << 1); - -out: - return err; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config); - -int pnx4008_dma_parse_config(unsigned long cfg, - struct pnx4008_dma_ch_config * ch_cfg) -{ - int err = 0; - - if (!ch_cfg) { - err = -EINVAL; - goto out; - } - - cfg >>= 1; - - ch_cfg->src_per = cfg & 0x1f; - cfg >>= 5; - - ch_cfg->dest_per = cfg & 0x1f; - cfg >>= 5; - - switch (cfg & 7) { - case 0: - ch_cfg->flow_cntrl = FC_MEM2MEM_DMA; - break; - case 1: - ch_cfg->flow_cntrl = FC_MEM2PER_DMA; - break; - case 2: - ch_cfg->flow_cntrl = FC_PER2MEM_DMA; - break; - case 3: - ch_cfg->flow_cntrl = FC_PER2PER_DMA; - break; - case 4: - ch_cfg->flow_cntrl = FC_PER2PER_DPER; - break; - case 5: - ch_cfg->flow_cntrl = FC_MEM2PER_PER; - break; - case 6: - ch_cfg->flow_cntrl = FC_PER2MEM_PER; - break; - case 7: - ch_cfg->flow_cntrl = FC_PER2PER_SPER; - } - cfg >>= 3; - - ch_cfg->ie = cfg & 1; - cfg >>= 1; - - ch_cfg->itc = cfg & 1; - cfg >>= 1; - - ch_cfg->lock = cfg & 1; - cfg >>= 1; - - ch_cfg->active = cfg & 1; - cfg >>= 1; - - ch_cfg->halt = cfg & 1; - -out: - return err; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config); - -void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config, - struct pnx4008_dma_ch_ctrl * ctrl) -{ - int new_len = ctrl->tr_size, num_entries = 0; - int old_len = new_len; - int src_width, dest_width, count = 1; - - switch (ctrl->swidth) { - case WIDTH_BYTE: - src_width = 1; - break; - case WIDTH_HWORD: - src_width = 2; - break; - case WIDTH_WORD: - src_width = 4; - break; - default: - return; - } - - switch (ctrl->dwidth) { - case WIDTH_BYTE: - dest_width = 1; - break; - case WIDTH_HWORD: - dest_width = 2; - break; - case WIDTH_WORD: - dest_width = 4; - break; - default: - return; - } - - while (new_len > 0x7FF) { - num_entries++; - new_len = (ctrl->tr_size + num_entries) / (num_entries + 1); - } - if (num_entries != 0) { - struct pnx4008_dma_ll *ll = NULL; - config->ch_ctrl &= ~0x7ff; - config->ch_ctrl |= new_len; - if (!config->is_ll) { - config->is_ll = 1; - while (num_entries) { - if (!ll) { - config->ll = - pnx4008_alloc_ll_entry(&config-> - ll_dma); - ll = config->ll; - } else { - ll->next = - pnx4008_alloc_ll_entry(&ll-> - next_dma); - ll = ll->next; - } - - if (ctrl->si) - ll->src_addr = - config->src_addr + - src_width * new_len * count; - else - ll->src_addr = config->src_addr; - if (ctrl->di) - ll->dest_addr = - config->dest_addr + - dest_width * new_len * count; - else - ll->dest_addr = config->dest_addr; - ll->ch_ctrl = config->ch_ctrl & 0x7fffffff; - ll->next_dma = 0; - ll->next = NULL; - num_entries--; - count++; - } - } else { - struct pnx4008_dma_ll *ll_old = config->ll; - unsigned long ll_dma_old = config->ll_dma; - while (num_entries) { - if (!ll) { - config->ll = - pnx4008_alloc_ll_entry(&config-> - ll_dma); - ll = config->ll; - } else { - ll->next = - pnx4008_alloc_ll_entry(&ll-> - next_dma); - ll = ll->next; - } - - if (ctrl->si) - ll->src_addr = - config->src_addr + - src_width * new_len * count; - else - ll->src_addr = config->src_addr; - if (ctrl->di) - ll->dest_addr = - config->dest_addr + - dest_width * new_len * count; - else - ll->dest_addr = config->dest_addr; - ll->ch_ctrl = config->ch_ctrl & 0x7fffffff; - ll->next_dma = 0; - ll->next = NULL; - num_entries--; - count++; - } - ll->next_dma = ll_dma_old; - ll->next = ll_old; - } - /* adjust last length/tc */ - ll->ch_ctrl = config->ch_ctrl & (~0x7ff); - ll->ch_ctrl |= old_len - new_len * (count - 1); - config->ch_ctrl &= 0x7fffffff; - } -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry); - -void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll, - struct pnx4008_dma_ch_ctrl * ctrl) -{ - int new_len = ctrl->tr_size, num_entries = 0; - int old_len = new_len; - int src_width, dest_width, count = 1; - - switch (ctrl->swidth) { - case WIDTH_BYTE: - src_width = 1; - break; - case WIDTH_HWORD: - src_width = 2; - break; - case WIDTH_WORD: - src_width = 4; - break; - default: - return; - } - - switch (ctrl->dwidth) { - case WIDTH_BYTE: - dest_width = 1; - break; - case WIDTH_HWORD: - dest_width = 2; - break; - case WIDTH_WORD: - dest_width = 4; - break; - default: - return; - } - - while (new_len > 0x7FF) { - num_entries++; - new_len = (ctrl->tr_size + num_entries) / (num_entries + 1); - } - if (num_entries != 0) { - struct pnx4008_dma_ll *ll = NULL; - cur_ll->ch_ctrl &= ~0x7ff; - cur_ll->ch_ctrl |= new_len; - if (!cur_ll->next) { - while (num_entries) { - if (!ll) { - cur_ll->next = - pnx4008_alloc_ll_entry(&cur_ll-> - next_dma); - ll = cur_ll->next; - } else { - ll->next = - pnx4008_alloc_ll_entry(&ll-> - next_dma); - ll = ll->next; - } - - if (ctrl->si) - ll->src_addr = - cur_ll->src_addr + - src_width * new_len * count; - else - ll->src_addr = cur_ll->src_addr; - if (ctrl->di) - ll->dest_addr = - cur_ll->dest_addr + - dest_width * new_len * count; - else - ll->dest_addr = cur_ll->dest_addr; - ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff; - ll->next_dma = 0; - ll->next = NULL; - num_entries--; - count++; - } - } else { - struct pnx4008_dma_ll *ll_old = cur_ll->next; - unsigned long ll_dma_old = cur_ll->next_dma; - while (num_entries) { - if (!ll) { - cur_ll->next = - pnx4008_alloc_ll_entry(&cur_ll-> - next_dma); - ll = cur_ll->next; - } else { - ll->next = - pnx4008_alloc_ll_entry(&ll-> - next_dma); - ll = ll->next; - } - - if (ctrl->si) - ll->src_addr = - cur_ll->src_addr + - src_width * new_len * count; - else - ll->src_addr = cur_ll->src_addr; - if (ctrl->di) - ll->dest_addr = - cur_ll->dest_addr + - dest_width * new_len * count; - else - ll->dest_addr = cur_ll->dest_addr; - ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff; - ll->next_dma = 0; - ll->next = NULL; - num_entries--; - count++; - } - - ll->next_dma = ll_dma_old; - ll->next = ll_old; - } - /* adjust last length/tc */ - ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff); - ll->ch_ctrl |= old_len - new_len * (count - 1); - cur_ll->ch_ctrl &= 0x7fffffff; - } -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry); - -int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config) -{ - if (!VALID_CHANNEL(ch) || !dma_channels[ch].name) - return -EINVAL; - - pnx4008_dma_lock(); - __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch)); - __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch)); - - if (config->is_ll) - __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch)); - else - __raw_writel(0, DMAC_Cx_LLI(ch)); - - __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch)); - __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch)); - pnx4008_dma_unlock(); - - return 0; - -} - -EXPORT_SYMBOL_GPL(pnx4008_config_channel); - -int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config) -{ - if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config) - return -EINVAL; - - pnx4008_dma_lock(); - config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch)); - config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch)); - - config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch)); - config->is_ll = config->ll_dma ? 1 : 0; - - config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch)); - config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch)); - pnx4008_dma_unlock(); - - return 0; -} - -EXPORT_SYMBOL_GPL(pnx4008_channel_get_config); - -int pnx4008_dma_ch_enable(int ch) -{ - unsigned long ch_cfg; - - if (!VALID_CHANNEL(ch) || !dma_channels[ch].name) - return -EINVAL; - - pnx4008_dma_lock(); - ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch)); - ch_cfg |= 1; - __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch)); - pnx4008_dma_unlock(); - - return 0; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable); - -int pnx4008_dma_ch_disable(int ch) -{ - unsigned long ch_cfg; - - if (!VALID_CHANNEL(ch) || !dma_channels[ch].name) - return -EINVAL; - - pnx4008_dma_lock(); - ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch)); - ch_cfg &= ~1; - __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch)); - pnx4008_dma_unlock(); - - return 0; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable); - -int pnx4008_dma_ch_enabled(int ch) -{ - unsigned long ch_cfg; - - if (!VALID_CHANNEL(ch) || !dma_channels[ch].name) - return -EINVAL; - - pnx4008_dma_lock(); - ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch)); - pnx4008_dma_unlock(); - - return ch_cfg & 1; -} - -EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled); - -static irqreturn_t dma_irq_handler(int irq, void *dev_id) -{ - int i; - unsigned long dint = __raw_readl(DMAC_INT_STAT); - unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT); - unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT); - unsigned long i_bit; - - for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) { - i_bit = 1 << i; - if (dint & i_bit) { - struct dma_channel *channel = &dma_channels[i]; - - if (channel->name && channel->irq_handler) { - int cause = 0; - - if (eint & i_bit) - cause |= DMA_ERR_INT; - if (tcint & i_bit) - cause |= DMA_TC_INT; - channel->irq_handler(i, cause, channel->data); - } else { - /* - * IRQ for an unregistered DMA channel - */ - printk(KERN_WARNING - "spurious IRQ for DMA channel %d\n", i); - } - if (tcint & i_bit) - __raw_writel(i_bit, DMAC_INT_TC_CLEAR); - if (eint & i_bit) - __raw_writel(i_bit, DMAC_INT_ERR_CLEAR); - } - } - return IRQ_HANDLED; -} - -static int __init pnx4008_dma_init(void) -{ - int ret, i; - - ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); - goto out; - } - - ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll); - ll_pool.cur = ll_pool.vaddr = - dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll), - &ll_pool.dma_addr, GFP_KERNEL); - - if (!ll_pool.vaddr) { - ret = -ENOMEM; - free_irq(DMA_INT, NULL); - goto out; - } - - for (i = 0; i < ll_pool.count - 1; i++) { - void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll); - *addr = (void *)addr + sizeof(struct pnx4008_dma_ll); - } - *(long *)(ll_pool.vaddr + - (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) = - (long)ll_pool.vaddr; - - __raw_writel(1, DMAC_CONFIG); - -out: - return ret; -} -arch_initcall(pnx4008_dma_init); diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c deleted file mode 100644 index d3e71d3847b4..000000000000 --- a/arch/arm/mach-pnx4008/gpio.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - * arch/arm/mach-pnx4008/gpio.c - * - * PNX4008 GPIO driver - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: - * Copyright (c) 2005 Koninklijke Philips Electronics N.V. - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/gpio-pnx4008.h> - -/* register definitions */ -#define PIO_VA_BASE IO_ADDRESS(PNX4008_PIO_BASE) - -#define PIO_INP_STATE (0x00U) -#define PIO_OUTP_SET (0x04U) -#define PIO_OUTP_CLR (0x08U) -#define PIO_OUTP_STATE (0x0CU) -#define PIO_DRV_SET (0x10U) -#define PIO_DRV_CLR (0x14U) -#define PIO_DRV_STATE (0x18U) -#define PIO_SDINP_STATE (0x1CU) -#define PIO_SDOUTP_SET (0x20U) -#define PIO_SDOUTP_CLR (0x24U) -#define PIO_MUX_SET (0x28U) -#define PIO_MUX_CLR (0x2CU) -#define PIO_MUX_STATE (0x30U) - -static inline void gpio_lock(void) -{ - local_irq_disable(); -} - -static inline void gpio_unlock(void) -{ - local_irq_enable(); -} - -/* Inline functions */ -static inline int gpio_read_bit(u32 reg, int gpio) -{ - u32 bit, val; - int ret = -EFAULT; - - if (gpio < 0) - goto out; - - bit = GPIO_BIT(gpio); - if (bit) { - val = __raw_readl(PIO_VA_BASE + reg); - ret = (val & bit) ? 1 : 0; - } -out: - return ret; -} - -static inline int gpio_set_bit(u32 reg, int gpio) -{ - u32 bit, val; - int ret = -EFAULT; - - if (gpio < 0) - goto out; - - bit = GPIO_BIT(gpio); - if (bit) { - val = __raw_readl(PIO_VA_BASE + reg); - val |= bit; - __raw_writel(val, PIO_VA_BASE + reg); - ret = 0; - } -out: - return ret; -} - -/* Very simple access control, bitmap for allocated/free */ -static unsigned long access_map[4]; -#define INP_INDEX 0 -#define OUTP_INDEX 1 -#define GPIO_INDEX 2 -#define MUX_INDEX 3 - -/*GPIO to Input Mapping */ -static short gpio_to_inp_map[32] = { - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, 10, 11, 12, 13, 14, 24, -1 -}; - -/*GPIO to Mux Mapping */ -static short gpio_to_mux_map[32] = { - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 0, 1, 4, 5, -1 -}; - -/*Output to Mux Mapping */ -static short outp_to_mux_map[32] = { - -1, -1, -1, 6, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 2, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1 -}; - -int pnx4008_gpio_register_pin(unsigned short pin) -{ - unsigned long bit = GPIO_BIT(pin); - int ret = -EBUSY; /* Already in use */ - - gpio_lock(); - - if (GPIO_ISBID(pin)) { - if (access_map[GPIO_INDEX] & bit) - goto out; - access_map[GPIO_INDEX] |= bit; - - } else if (GPIO_ISRAM(pin)) { - if (access_map[GPIO_INDEX] & bit) - goto out; - access_map[GPIO_INDEX] |= bit; - - } else if (GPIO_ISMUX(pin)) { - if (access_map[MUX_INDEX] & bit) - goto out; - access_map[MUX_INDEX] |= bit; - - } else if (GPIO_ISOUT(pin)) { - if (access_map[OUTP_INDEX] & bit) - goto out; - access_map[OUTP_INDEX] |= bit; - - } else if (GPIO_ISIN(pin)) { - if (access_map[INP_INDEX] & bit) - goto out; - access_map[INP_INDEX] |= bit; - } else - goto out; - ret = 0; - -out: - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_register_pin); - -int pnx4008_gpio_unregister_pin(unsigned short pin) -{ - unsigned long bit = GPIO_BIT(pin); - int ret = -EFAULT; /* Not registered */ - - gpio_lock(); - - if (GPIO_ISBID(pin)) { - if (~access_map[GPIO_INDEX] & bit) - goto out; - access_map[GPIO_INDEX] &= ~bit; - } else if (GPIO_ISRAM(pin)) { - if (~access_map[GPIO_INDEX] & bit) - goto out; - access_map[GPIO_INDEX] &= ~bit; - } else if (GPIO_ISMUX(pin)) { - if (~access_map[MUX_INDEX] & bit) - goto out; - access_map[MUX_INDEX] &= ~bit; - } else if (GPIO_ISOUT(pin)) { - if (~access_map[OUTP_INDEX] & bit) - goto out; - access_map[OUTP_INDEX] &= ~bit; - } else if (GPIO_ISIN(pin)) { - if (~access_map[INP_INDEX] & bit) - goto out; - access_map[INP_INDEX] &= ~bit; - } else - goto out; - ret = 0; - -out: - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_unregister_pin); - -unsigned long pnx4008_gpio_read_pin(unsigned short pin) -{ - unsigned long ret = -EFAULT; - int gpio = GPIO_BIT_MASK(pin); - gpio_lock(); - if (GPIO_ISOUT(pin)) { - ret = gpio_read_bit(PIO_OUTP_STATE, gpio); - } else if (GPIO_ISRAM(pin)) { - if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) { - ret = gpio_read_bit(PIO_SDINP_STATE, gpio); - } - } else if (GPIO_ISBID(pin)) { - ret = gpio_read_bit(PIO_DRV_STATE, gpio); - if (ret > 0) - ret = gpio_read_bit(PIO_OUTP_STATE, gpio); - else if (ret == 0) - ret = - gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]); - } else if (GPIO_ISIN(pin)) { - ret = gpio_read_bit(PIO_INP_STATE, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_read_pin); - -/* Write Value to output */ -int pnx4008_gpio_write_pin(unsigned short pin, int output) -{ - int gpio = GPIO_BIT_MASK(pin); - int ret = -EFAULT; - - gpio_lock(); - if (GPIO_ISOUT(pin)) { - printk( "writing '%x' to '%x'\n", - gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR ); - ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio); - } else if (GPIO_ISRAM(pin)) { - if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0) - ret = gpio_set_bit(output ? PIO_SDOUTP_SET : - PIO_SDOUTP_CLR, gpio); - } else if (GPIO_ISBID(pin)) { - if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0) - ret = gpio_set_bit(output ? PIO_OUTP_SET : - PIO_OUTP_CLR, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_write_pin); - -/* Value = 1 : Set GPIO pin as output */ -/* Value = 0 : Set GPIO pin as input */ -int pnx4008_gpio_set_pin_direction(unsigned short pin, int output) -{ - int gpio = GPIO_BIT_MASK(pin); - int ret = -EFAULT; - - gpio_lock(); - if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) { - ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction); - -/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/ -int pnx4008_gpio_read_pin_direction(unsigned short pin) -{ - int gpio = GPIO_BIT_MASK(pin); - int ret = -EFAULT; - - gpio_lock(); - if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) { - ret = gpio_read_bit(PIO_DRV_STATE, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction); - -/* Value = 1 : Set pin to muxed function */ -/* Value = 0 : Set pin as GPIO */ -int pnx4008_gpio_set_pin_mux(unsigned short pin, int output) -{ - int gpio = GPIO_BIT_MASK(pin); - int ret = -EFAULT; - - gpio_lock(); - if (GPIO_ISBID(pin)) { - ret = - gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, - gpio_to_mux_map[gpio]); - } else if (GPIO_ISOUT(pin)) { - ret = - gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, - outp_to_mux_map[gpio]); - } else if (GPIO_ISMUX(pin)) { - ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux); - -/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/ -int pnx4008_gpio_read_pin_mux(unsigned short pin) -{ - int gpio = GPIO_BIT_MASK(pin); - int ret = -EFAULT; - - gpio_lock(); - if (GPIO_ISBID(pin)) { - ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]); - } else if (GPIO_ISOUT(pin)) { - ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]); - } else if (GPIO_ISMUX(pin)) { - ret = gpio_read_bit(PIO_MUX_STATE, gpio); - } - gpio_unlock(); - return ret; -} - -EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux); diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c deleted file mode 100644 index 550cfc2a1f2e..000000000000 --- a/arch/arm/mach-pnx4008/i2c.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * I2C initialization for PNX4008. - * - * Author: Vitaly Wool <vitalywool@gmail.com> - * - * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/clk.h> -#include <linux/i2c.h> -#include <linux/i2c-pnx.h> -#include <linux/platform_device.h> -#include <linux/err.h> -#include <mach/platform.h> -#include <mach/irqs.h> - -static struct resource i2c0_resources[] = { - { - .start = PNX4008_I2C1_BASE, - .end = PNX4008_I2C1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = I2C_1_INT, - .end = I2C_1_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - { - .start = PNX4008_I2C2_BASE, - .end = PNX4008_I2C2_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = I2C_2_INT, - .end = I2C_2_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c2_resources[] = { - { - .start = PNX4008_USB_CONFIG_BASE + 0x300, - .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = USB_I2C_INT, - .end = USB_I2C_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device i2c0_device = { - .name = "pnx-i2c.0", - .id = 0, - .resource = i2c0_resources, - .num_resources = ARRAY_SIZE(i2c0_resources), -}; - -static struct platform_device i2c1_device = { - .name = "pnx-i2c.1", - .id = 1, - .resource = i2c1_resources, - .num_resources = ARRAY_SIZE(i2c1_resources), -}; - -static struct platform_device i2c2_device = { - .name = "pnx-i2c.2", - .id = 2, - .resource = i2c2_resources, - .num_resources = ARRAY_SIZE(i2c2_resources), -}; - -static struct platform_device *devices[] __initdata = { - &i2c0_device, - &i2c1_device, - &i2c2_device, -}; - -void __init pnx4008_register_i2c_devices(void) -{ - platform_add_devices(devices, ARRAY_SIZE(devices)); -} diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h deleted file mode 100644 index 8d2a5ef52c90..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/clock.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/clock.h - * - * Clock control driver for PNX4008 - header file - * - * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __PNX4008_CLOCK_H__ -#define __PNX4008_CLOCK_H__ - -struct module; -struct clk; - -#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE) -#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40) -#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44) -#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48) -#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c) -#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50) -#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58) -#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64) -#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68) -#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80) -#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84) -#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90) -#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac) -#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0) -#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4) -#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8) -#define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc) -#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4) -#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8) -#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0) -#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4) -#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8) -#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec) -#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc) - -#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE) -#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60) -#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64) -#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68) -#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C) - -#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4) - -#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE) - -#define CLK_RATE_13MHZ 13000 -#define CLK_RATE_1MHZ 1000 -#define CLK_RATE_208MHZ 208000 -#define CLK_RATE_48MHZ 48000 -#define CLK_RATE_32KHZ 32 - -#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */ - -#endif diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S deleted file mode 100644 index 469d60d97f5c..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-pnx4008/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00090000 - add \rv, \rp, #0xf4000000 @ virtual - add \rp, \rp, #0x40000000 @ physical - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h deleted file mode 100644 index f094bf8bfb18..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/dma.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/dma.h - * - * PNX4008 DMA header file - * - * Author: Vitaly Wool - * Copyright: MontaVista Software Inc. (c) 2005 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include "platform.h" - -#define MAX_DMA_CHANNELS 8 - -#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE) -#define DMAC_INT_STAT (DMAC_BASE + 0x0000) -#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004) -#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008) -#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c) -#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010) -#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024) -#define DMAC_CONFIG (DMAC_BASE + 0x0030) -#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20) -#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20) -#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20) -#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20) -#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20) - -enum { - WIDTH_BYTE = 0, - WIDTH_HWORD, - WIDTH_WORD -}; - -enum { - FC_MEM2MEM_DMA, - FC_MEM2PER_DMA, - FC_PER2MEM_DMA, - FC_PER2PER_DMA, - FC_PER2PER_DPER, - FC_MEM2PER_PER, - FC_PER2MEM_PER, - FC_PER2PER_SPER -}; - -enum { - DMA_INT_UNKNOWN = 0, - DMA_ERR_INT = 1, - DMA_TC_INT = 2, -}; - -enum { - DMA_BUFFER_ALLOCATED = 1, - DMA_HAS_LL = 2, -}; - -enum { - PER_CAM_DMA_1 = 0, - PER_NDF_FLASH = 1, - PER_MBX_SLAVE_FIFO = 2, - PER_SPI2_REC_XMIT = 3, - PER_MS_SD_RX_XMIT = 4, - PER_HS_UART_1_XMIT = 5, - PER_HS_UART_1_RX = 6, - PER_HS_UART_2_XMIT = 7, - PER_HS_UART_2_RX = 8, - PER_HS_UART_7_XMIT = 9, - PER_HS_UART_7_RX = 10, - PER_SPI1_REC_XMIT = 11, - PER_MLC_NDF_SREC = 12, - PER_CAM_DMA_2 = 13, - PER_PRNG_INFIFO = 14, - PER_PRNG_OUTFIFO = 15, -}; - -struct pnx4008_dma_ch_ctrl { - int tc_mask; - int cacheable; - int bufferable; - int priv_mode; - int di; - int si; - int dest_ahb1; - int src_ahb1; - int dwidth; - int swidth; - int dbsize; - int sbsize; - int tr_size; -}; - -struct pnx4008_dma_ch_config { - int halt; - int active; - int lock; - int itc; - int ie; - int flow_cntrl; - int dest_per; - int src_per; -}; - -struct pnx4008_dma_ll { - unsigned long src_addr; - unsigned long dest_addr; - u32 next_dma; - unsigned long ch_ctrl; - struct pnx4008_dma_ll *next; - int flags; - void *alloc_data; - int (*free) (void *); -}; - -struct pnx4008_dma_config { - int is_ll; - unsigned long src_addr; - unsigned long dest_addr; - unsigned long ch_ctrl; - unsigned long ch_cfg; - struct pnx4008_dma_ll *ll; - u32 ll_dma; - int flags; - void *alloc_data; - int (*free) (void *); -}; - -extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *); -extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t); -extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *); - -extern int pnx4008_request_channel(char *, int, - void (*)(int, int, void *), - void *); -extern void pnx4008_free_channel(int); -extern int pnx4008_config_dma(int, int, int); -extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *, - unsigned long *); -extern int pnx4008_dma_parse_control(unsigned long, - struct pnx4008_dma_ch_ctrl *); -extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *, - unsigned long *); -extern int pnx4008_dma_parse_config(unsigned long, - struct pnx4008_dma_ch_config *); -extern int pnx4008_config_channel(int, struct pnx4008_dma_config *); -extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *); -extern int pnx4008_dma_ch_enable(int); -extern int pnx4008_dma_ch_disable(int); -extern int pnx4008_dma_ch_enabled(int); -extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *, - struct pnx4008_dma_ch_ctrl *); -extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *, - struct pnx4008_dma_ch_ctrl *); - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S deleted file mode 100644 index 77a555846719..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S +++ /dev/null @@ -1,116 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for PNX4008-based platforms - * - * 2005-2006 (c) MontaVista Software, Inc. - * Author: Vitaly Wool <vwool@ru.mvista.com> - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include "platform.h" - -#define IO_BASE 0xF0000000 -#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) - -#define INTRC_MASK 0x00 -#define INTRC_RAW_STAT 0x04 -#define INTRC_STAT 0x08 -#define INTRC_POLAR 0x0C -#define INTRC_ACT_TYPE 0x10 -#define INTRC_TYPE 0x14 - -#define SIC1_BASE_INT 32 -#define SIC2_BASE_INT 64 - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -/* decode the MIC interrupt numbers */ - ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) - ldr \irqstat, [\base, #INTRC_STAT] - - cmp \irqstat,#1<<16 - movhs \irqnr,#16 - movlo \irqnr,#0 - movhs \irqstat,\irqstat,lsr#16 - cmp \irqstat,#1<<8 - addhs \irqnr,\irqnr,#8 - movhs \irqstat,\irqstat,lsr#8 - cmp \irqstat,#1<<4 - addhs \irqnr,\irqnr,#4 - movhs \irqstat,\irqstat,lsr#4 - cmp \irqstat,#1<<2 - addhs \irqnr,\irqnr,#2 - movhs \irqstat,\irqstat,lsr#2 - cmp \irqstat,#1<<1 - addhs \irqnr,\irqnr,#1 - -/* was there an interrupt ? if not then drop out with EQ status */ - teq \irqstat,#0 - beq 1003f - -/* and now check for extended IRQ reasons */ - cmp \irqnr,#1 - bls 1003f - cmp \irqnr,#30 - blo 1002f - -/* IRQ 31,30 : High priority cascade IRQ handle */ -/* read the correct SIC */ -/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */ -/* set the base IRQ number */ - ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) - moveq \irqnr,#SIC1_BASE_INT - ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) - movne \irqnr,#SIC2_BASE_INT - ldr \irqstat, [\base, #INTRC_STAT] - ldr \tmp, [\base, #INTRC_TYPE] -/* and with inverted mask : low priority interrupts */ - and \irqstat,\irqstat,\tmp - b 1004f - -1003: -/* IRQ 1,0 : Low priority cascade IRQ handle */ -/* read the correct SIC */ -/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/ -/* read the correct SIC */ -/* set the base IRQ number */ - ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) - movne \irqnr,#SIC1_BASE_INT - ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) - moveq \irqnr,#SIC2_BASE_INT - ldr \irqstat, [\base, #INTRC_STAT] - ldr \tmp, [\base, #INTRC_TYPE] -/* and with inverted mask : low priority interrupts */ - bic \irqstat,\irqstat,\tmp - -1004: - - cmp \irqstat,#1<<16 - addhs \irqnr,\irqnr,#16 - movhs \irqstat,\irqstat,lsr#16 - cmp \irqstat,#1<<8 - addhs \irqnr,\irqnr,#8 - movhs \irqstat,\irqstat,lsr#8 - cmp \irqstat,#1<<4 - addhs \irqnr,\irqnr,#4 - movhs \irqstat,\irqstat,lsr#4 - cmp \irqstat,#1<<2 - addhs \irqnr,\irqnr,#2 - movhs \irqstat,\irqstat,lsr#2 - cmp \irqstat,#1<<1 - addhs \irqnr,\irqnr,#1 - - -/* is irqstat not zero */ - -1002: -/* we assert that irqstat is not equal to zero and return ne status if true*/ - teq \irqstat,#0 -1003: - .endm - diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h deleted file mode 100644 index 41027dd7cf74..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h - * - * PNX4008 GPIO driver - header file - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: - * Copyright (c) 2005 Koninklijke Philips Electronics N.V. - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef _PNX4008_GPIO_H_ -#define _PNX4008_GPIO_H_ - - -/* Block numbers */ -#define GPIO_IN (0) -#define GPIO_OUT (0x100) -#define GPIO_BID (0x200) -#define GPIO_RAM (0x300) -#define GPIO_MUX (0x400) - -#define GPIO_TYPE_MASK(K) ((K) & 0x700) - -/* INPUT GPIOs */ -/* GPI */ -#define GPI_00 (GPIO_IN | 0) -#define GPI_01 (GPIO_IN | 1) -#define GPI_02 (GPIO_IN | 2) -#define GPI_03 (GPIO_IN | 3) -#define GPI_04 (GPIO_IN | 4) -#define GPI_05 (GPIO_IN | 5) -#define GPI_06 (GPIO_IN | 6) -#define GPI_07 (GPIO_IN | 7) -#define GPI_08 (GPIO_IN | 8) -#define GPI_09 (GPIO_IN | 9) -#define U1_RX (GPIO_IN | 15) -#define U2_HTCS (GPIO_IN | 16) -#define U2_RX (GPIO_IN | 17) -#define U3_RX (GPIO_IN | 18) -#define U4_RX (GPIO_IN | 19) -#define U5_RX (GPIO_IN | 20) -#define U6_IRRX (GPIO_IN | 21) -#define U7_HCTS (GPIO_IN | 22) -#define U7_RX (GPIO_IN | 23) -/* MISC IN */ -#define SPI1_DATIN (GPIO_IN | 25) -#define DISP_SYNC (GPIO_IN | 26) -#define SPI2_DATIN (GPIO_IN | 27) -#define GPI_11 (GPIO_IN | 28) - -#define GPIO_IN_MASK 0x1eff83ff - -/* OUTPUT GPIOs */ -/* GPO */ -#define GPO_00 (GPIO_OUT | 0) -#define GPO_01 (GPIO_OUT | 1) -#define GPO_02 (GPIO_OUT | 2) -#define GPO_03 (GPIO_OUT | 3) -#define GPO_04 (GPIO_OUT | 4) -#define GPO_05 (GPIO_OUT | 5) -#define GPO_06 (GPIO_OUT | 6) -#define GPO_07 (GPIO_OUT | 7) -#define GPO_08 (GPIO_OUT | 8) -#define GPO_09 (GPIO_OUT | 9) -#define GPO_10 (GPIO_OUT | 10) -#define GPO_11 (GPIO_OUT | 11) -#define GPO_12 (GPIO_OUT | 12) -#define GPO_13 (GPIO_OUT | 13) -#define GPO_14 (GPIO_OUT | 14) -#define GPO_15 (GPIO_OUT | 15) -#define GPO_16 (GPIO_OUT | 16) -#define GPO_17 (GPIO_OUT | 17) -#define GPO_18 (GPIO_OUT | 18) -#define GPO_19 (GPIO_OUT | 19) -#define GPO_20 (GPIO_OUT | 20) -#define GPO_21 (GPIO_OUT | 21) -#define GPO_22 (GPIO_OUT | 22) -#define GPO_23 (GPIO_OUT | 23) - -#define GPIO_OUT_MASK 0xffffff - -/* BIDIRECTIONAL GPIOs */ -/* RAM pins */ -#define RAM_D19 (GPIO_RAM | 0) -#define RAM_D20 (GPIO_RAM | 1) -#define RAM_D21 (GPIO_RAM | 2) -#define RAM_D22 (GPIO_RAM | 3) -#define RAM_D23 (GPIO_RAM | 4) -#define RAM_D24 (GPIO_RAM | 5) -#define RAM_D25 (GPIO_RAM | 6) -#define RAM_D26 (GPIO_RAM | 7) -#define RAM_D27 (GPIO_RAM | 8) -#define RAM_D28 (GPIO_RAM | 9) -#define RAM_D29 (GPIO_RAM | 10) -#define RAM_D30 (GPIO_RAM | 11) -#define RAM_D31 (GPIO_RAM | 12) - -#define GPIO_RAM_MASK 0x1fff - -/* I/O pins */ -#define GPIO_00 (GPIO_BID | 25) -#define GPIO_01 (GPIO_BID | 26) -#define GPIO_02 (GPIO_BID | 27) -#define GPIO_03 (GPIO_BID | 28) -#define GPIO_04 (GPIO_BID | 29) -#define GPIO_05 (GPIO_BID | 30) - -#define GPIO_BID_MASK 0x7e000000 - -/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */ -#define GPIO_SDRAM_SEL (GPIO_MUX | 3) - -#define GPIO_MUX_MASK 0x8 - -/* Extraction/assembly macros */ -#define GPIO_BIT_MASK(K) ((K) & 0x1F) -#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K)) -#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK)) -#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK)) -#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK)) -#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK)) -#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK)) - -/* Start Enable Pin Interrupts - table 58 page 66 */ - -#define SE_PIN_BASE_INT 32 - -#define SE_U7_RX_INT 63 -#define SE_U7_HCTS_INT 62 -#define SE_BT_CLKREQ_INT 61 -#define SE_U6_IRRX_INT 60 -/*59 unused*/ -#define SE_U5_RX_INT 58 -#define SE_GPI_11_INT 57 -#define SE_U3_RX_INT 56 -#define SE_U2_HCTS_INT 55 -#define SE_U2_RX_INT 54 -#define SE_U1_RX_INT 53 -#define SE_DISP_SYNC_INT 52 -/*51 unused*/ -#define SE_SDIO_INT_N 50 -#define SE_MSDIO_START_INT 49 -#define SE_GPI_06_INT 48 -#define SE_GPI_05_INT 47 -#define SE_GPI_04_INT 46 -#define SE_GPI_03_INT 45 -#define SE_GPI_02_INT 44 -#define SE_GPI_01_INT 43 -#define SE_GPI_00_INT 42 -#define SE_SYSCLKEN_PIN_INT 41 -#define SE_SPI1_DATAIN_INT 40 -#define SE_GPI_07_INT 39 -#define SE_SPI2_DATAIN_INT 38 -#define SE_GPI_10_INT 37 -#define SE_GPI_09_INT 36 -#define SE_GPI_08_INT 35 -/*34-32 unused*/ - -/* Start Enable Internal Interrupts - table 57 page 65 */ - -#define SE_INT_BASE_INT 0 - -#define SE_TS_IRQ 31 -#define SE_TS_P_INT 30 -#define SE_TS_AUX_INT 29 -/*27-28 unused*/ -#define SE_USB_AHB_NEED_CLK_INT 26 -#define SE_MSTIMER_INT 25 -#define SE_RTC_INT 24 -#define SE_USB_NEED_CLK_INT 23 -#define SE_USB_INT 22 -#define SE_USB_I2C_INT 21 -#define SE_USB_OTG_TIMER_INT 20 -#define SE_USB_OTG_ATX_INT_N 19 -/*18 unused*/ -#define SE_DSP_GPIO4_INT 17 -#define SE_KEY_IRQ 16 -#define SE_DSP_SLAVEPORT_INT 15 -#define SE_DSP_GPIO1_INT 14 -#define SE_DSP_GPIO0_INT 13 -#define SE_DSP_AHB_INT 12 -/*11-6 unused*/ -#define SE_GPIO_05_INT 5 -#define SE_GPIO_04_INT 4 -#define SE_GPIO_03_INT 3 -#define SE_GPIO_02_INT 2 -#define SE_GPIO_01_INT 1 -#define SE_GPIO_00_INT 0 - -#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) - -#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) -#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) -#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) -#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) - -extern int pnx4008_gpio_register_pin(unsigned short pin); -extern int pnx4008_gpio_unregister_pin(unsigned short pin); -extern unsigned long pnx4008_gpio_read_pin(unsigned short pin); -extern int pnx4008_gpio_write_pin(unsigned short pin, int output); -extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output); -extern int pnx4008_gpio_read_pin_direction(unsigned short pin); -extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output); -extern int pnx4008_gpio_read_pin_mux(unsigned short pin); - -static inline void start_int_umask(u8 irq) -{ - __raw_writel(__raw_readl(START_INT_ER_REG(irq)) | - START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); -} - -static inline void start_int_mask(u8 irq) -{ - __raw_writel(__raw_readl(START_INT_ER_REG(irq)) & - ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); -} - -static inline void start_int_ack(u8 irq) -{ - __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq)); -} - -static inline void start_int_set_falling_edge(u8 irq) -{ - __raw_writel(__raw_readl(START_INT_APR_REG(irq)) & - ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); -} - -static inline void start_int_set_rising_edge(u8 irq) -{ - __raw_writel(__raw_readl(START_INT_APR_REG(irq)) | - START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); -} - -#endif /* _PNX4008_GPIO_H_ */ diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h deleted file mode 100644 index 7b98b828d368..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/hardware.h - * - * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> -#include <mach/platform.h> - -/* Start of virtual addresses for IO devices */ -#define IO_BASE 0xF0000000 - -/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ -#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) - -#endif diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h deleted file mode 100644 index 2a690ca33870..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/irq.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/irq.h - * - * PNX4008 IRQ controller driver - header file - * this one is used in entry-arnv.S as well so it cannot contain C code - * - * Copyright (c) 2005 Philips Semiconductors - * Copyright (c) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef __PNX4008_IRQ_H__ -#define __PNX4008_IRQ_H__ - -#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) -#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) -#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) - -/* Manual: Chapter 20, page 195 */ - -#define INTC_BIT(irq) (1<< ((irq) & 0x1F)) - -#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9))) -#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9))) -#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9))) -#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9))) -#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9))) -#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9))) - -#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) - -#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) -#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) -#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) -#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) - -extern void __init pnx4008_init_irq(void); - -#endif /* __PNX4008_IRQ_H__ */ diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h deleted file mode 100644 index f6b33cf23ae2..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/irqs.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/irqs.h - * - * PNX4008 IRQ controller driver - header file - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __PNX4008_IRQS_h__ -#define __PNX4008_IRQS_h__ - -#define NR_IRQS 96 - -/*Manual: table 259, page 199*/ - -/*SUB2 Interrupt Routing (SIC2)*/ - -#define SIC2_BASE_INT 64 - -#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */ -#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */ -#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */ -#define GPI_06_INT 92 -#define GPI_05_INT 91 -#define GPI_04_INT 90 -#define GPI_03_INT 89 -#define GPI_02_INT 88 -#define GPI_01_INT 87 -#define GPI_00_INT 86 -#define BT_CLKREQ_INT 85 -#define SPI1_DATIN_INT 84 -#define U5_RX_INT 83 -#define SDIO_INT_N 82 -#define CAM_HS_INT 81 -#define CAM_VS_INT 80 -#define GPI_07_INT 79 -#define DISP_SYNC_INT 78 -#define DSP_INT8 77 -#define U7_HCTS_INT 76 -#define GPI_10_INT 75 -#define GPI_09_INT 74 -#define GPI_08_INT 73 -#define DSP_INT7 72 -#define U2_HCTS_INT 71 -#define SPI2_DATIN_INT 70 -#define GPIO_05_INT 69 -#define GPIO_04_INT 68 -#define GPIO_03_INT 67 -#define GPIO_02_INT 66 -#define GPIO_01_INT 65 -#define GPIO_00_INT 64 - -/*Manual: table 258, page 198*/ - -/*SUB1 Interrupt Routing (SIC1)*/ - -#define SIC1_BASE_INT 32 - -#define USB_I2C_INT 63 -#define USB_DEV_HP_INT 62 -#define USB_DEV_LP_INT 61 -#define USB_DEV_DMA_INT 60 -#define USB_HOST_INT 59 -#define USB_OTG_ATX_INT_N 58 -#define USB_OTG_TIMER_INT 57 -#define SW_INT 56 -#define SPI1_INT 55 -#define KEY_IRQ 54 -#define DSP_M_INT 53 -#define RTC_INT 52 -#define I2C_1_INT 51 -#define I2C_2_INT 50 -#define PLL1_LOCK_INT 49 -#define PLL2_LOCK_INT 48 -#define PLL3_LOCK_INT 47 -#define PLL4_LOCK_INT 46 -#define PLL5_LOCK_INT 45 -#define SPI2_INT 44 -#define DSP_INT1 43 -#define DSP_INT2 42 -#define DSP_TDM_INT2 41 -#define TS_AUX_INT 40 -#define TS_IRQ 39 -#define TS_P_INT 38 -#define UOUT1_TO_PAD_INT 37 -#define GPI_11_INT 36 -#define DSP_INT4 35 -#define JTAG_COMM_RX_INT 34 -#define JTAG_COMM_TX_INT 33 -#define DSP_INT3 32 - -/*Manual: table 257, page 197*/ - -/*MAIN Interrupt Routing*/ - -#define MAIN_BASE_INT 0 - -#define SUB2_FIQ_N 31 /*active low */ -#define SUB1_FIQ_N 30 /*active low */ -#define JPEG_INT 29 -#define DMA_INT 28 -#define MSTIMER_INT 27 -#define IIR1_INT 26 -#define IIR2_INT 25 -#define IIR7_INT 24 -#define DSP_TDM_INT0 23 -#define DSP_TDM_INT1 22 -#define DSP_P_INT 21 -#define DSP_INT0 20 -#define DUM_INT 19 -#define UOUT0_TO_PAD_INT 18 -#define MP4_ENC_INT 17 -#define MP4_DEC_INT 16 -#define SD0_INT 15 -#define MBX_INT 14 -#define SD1_INT 13 -#define MS_INT_N 12 -#define FLASH_INT 11 /*NAND*/ -#define IIR6_INT 10 -#define IIR5_INT 9 -#define IIR4_INT 8 -#define IIR3_INT 7 -#define WATCH_INT 6 -#define HSTIMER_INT 5 -#define ARCH_TIMER_IRQ HSTIMER_INT -#define CAM_INT 4 -#define PRNG_INT 3 -#define CRYPTO_INT 2 -#define SUB2_IRQ_N 1 /*active low */ -#define SUB1_IRQ_N 0 /*active low */ - -#define PNX4008_IRQ_TYPES \ -{ /*IRQ #'s: */ \ -IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \ -IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \ -IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \ -IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \ -} - -/* Start Enable Pin Interrupts - table 58 page 66 */ - -#define SE_PIN_BASE_INT 32 - -#define SE_U7_RX_INT 63 -#define SE_U7_HCTS_INT 62 -#define SE_BT_CLKREQ_INT 61 -#define SE_U6_IRRX_INT 60 -/*59 unused*/ -#define SE_U5_RX_INT 58 -#define SE_GPI_11_INT 57 -#define SE_U3_RX_INT 56 -#define SE_U2_HCTS_INT 55 -#define SE_U2_RX_INT 54 -#define SE_U1_RX_INT 53 -#define SE_DISP_SYNC_INT 52 -/*51 unused*/ -#define SE_SDIO_INT_N 50 -#define SE_MSDIO_START_INT 49 -#define SE_GPI_06_INT 48 -#define SE_GPI_05_INT 47 -#define SE_GPI_04_INT 46 -#define SE_GPI_03_INT 45 -#define SE_GPI_02_INT 44 -#define SE_GPI_01_INT 43 -#define SE_GPI_00_INT 42 -#define SE_SYSCLKEN_PIN_INT 41 -#define SE_SPI1_DATAIN_INT 40 -#define SE_GPI_07_INT 39 -#define SE_SPI2_DATAIN_INT 38 -#define SE_GPI_10_INT 37 -#define SE_GPI_09_INT 36 -#define SE_GPI_08_INT 35 -/*34-32 unused*/ - -/* Start Enable Internal Interrupts - table 57 page 65 */ - -#define SE_INT_BASE_INT 0 - -#define SE_TS_IRQ 31 -#define SE_TS_P_INT 30 -#define SE_TS_AUX_INT 29 -/*27-28 unused*/ -#define SE_USB_AHB_NEED_CLK_INT 26 -#define SE_MSTIMER_INT 25 -#define SE_RTC_INT 24 -#define SE_USB_NEED_CLK_INT 23 -#define SE_USB_INT 22 -#define SE_USB_I2C_INT 21 -#define SE_USB_OTG_TIMER_INT 20 - -#endif /* __PNX4008_IRQS_h__ */ diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h deleted file mode 100644 index 368c2c10a308..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/platform.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/platform.h - * - * PNX4008 Base addresses - header file - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * Based on reference code received from Philips: - * Copyright (C) 2003 Philips Semiconductors - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - - -#ifndef __ASM_ARCH_PLATFORM_H__ -#define __ASM_ARCH_PLATFORM_H__ - -#define PNX4008_IRAM_BASE 0x08000000 -#define PNX4008_IRAM_SIZE 0x00010000 -#define PNX4008_YUV_SLAVE_BASE 0x10000000 -#define PNX4008_DUM_SLAVE_BASE 0x18000000 -#define PNX4008_NDF_FLASH_BASE 0x20020000 -#define PNX4008_SPI1_BASE 0x20088000 -#define PNX4008_SPI2_BASE 0x20090000 -#define PNX4008_SD_CONFIG_BASE 0x20098000 -#define PNX4008_FLASH_DATA 0x200B0000 -#define PNX4008_MLC_FLASH_BASE 0x200B8000 -#define PNX4008_JPEG_CONFIG_BASE 0x300A0000 -#define PNX4008_DMA_CONFIG_BASE 0x31000000 -#define PNX4008_USB_CONFIG_BASE 0x31020000 -#define PNX4008_SDRAM_CFG_BASE 0x31080000 -#define PNX4008_AHB2FAB_BASE 0x40000000 -#define PNX4008_PWRMAN_BASE 0x40004000 -#define PNX4008_INTCTRLMIC_BASE 0x40008000 -#define PNX4008_INTCTRLSIC1_BASE 0x4000C000 -#define PNX4008_INTCTRLSIC2_BASE 0x40010000 -#define PNX4008_HSUART1_BASE 0x40014000 -#define PNX4008_HSUART2_BASE 0x40018000 -#define PNX4008_HSUART7_BASE 0x4001C000 -#define PNX4008_RTC_BASE 0x40024000 -#define PNX4008_PIO_BASE 0x40028000 -#define PNX4008_MSTIMER_BASE 0x40034000 -#define PNX4008_HSTIMER_BASE 0x40038000 -#define PNX4008_WDOG_BASE 0x4003C000 -#define PNX4008_DEBUG_BASE 0x40040000 -#define PNX4008_TOUCH1_BASE 0x40048000 -#define PNX4008_KEYSCAN_BASE 0x40050000 -#define PNX4008_UARTCTRL_BASE 0x40054000 -#define PNX4008_PWM_BASE 0x4005C000 -#define PNX4008_UART3_BASE 0x40080000 -#define PNX4008_UART4_BASE 0x40088000 -#define PNX4008_UART5_BASE 0x40090000 -#define PNX4008_UART6_BASE 0x40098000 -#define PNX4008_I2C1_BASE 0x400A0000 -#define PNX4008_I2C2_BASE 0x400A8000 -#define PNX4008_MAGICGATE_BASE 0x400B0000 -#define PNX4008_DUMCONF_BASE 0x400B8000 -#define PNX4008_DUM_MAINCFG_BASE 0x400BC000 -#define PNX4008_DSP_BASE 0x400C0000 -#define PNX4008_PROFCOUNTER_BASE 0x400C8000 -#define PNX4008_CRYPTO_BASE 0x400D0000 -#define PNX4008_CAMIFCONF_BASE 0x400D8000 -#define PNX4008_YUV2RGB_BASE 0x400E0000 -#define PNX4008_AUDIOCONFIG_BASE 0x400E8000 - -#endif diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h deleted file mode 100644 index 2fa685bff858..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/pm.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/pm.h - * - * PNX4008 Power Management Routiness - header file - * - * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __ASM_ARCH_PNX4008_PM_H -#define __ASM_ARCH_PNX4008_PM_H - -#ifndef __ASSEMBLER__ -#include "irq.h" -#include "irqs.h" -#include "clock.h" - -extern void pnx4008_pm_idle(void); -extern void pnx4008_pm_suspend(void); -extern unsigned int pnx4008_cpu_suspend_sz; -extern void pnx4008_cpu_suspend(void); -extern unsigned int pnx4008_cpu_standby_sz; -extern void pnx4008_cpu_standby(void); - -extern int pnx4008_startup_pll(struct clk *); -extern int pnx4008_shutdown_pll(struct clk *); - -#endif /* ASSEMBLER */ -#endif /* __ASM_ARCH_PNX4008_PM_H */ diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h deleted file mode 100644 index b383c7de7ab4..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/timex.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/timex.h - * - * PNX4008 timers header file - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __PNX4008_TIMEX_H -#define __PNX4008_TIMEX_H - -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h deleted file mode 100644 index bb4751ee2539..000000000000 --- a/arch/arm/mach-pnx4008/include/mach/uncompress.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/uncompress.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2006 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define UART5_BASE 0x40090000 - -#define UART5_DR (*(volatile unsigned char *) (UART5_BASE)) -#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18)) - -static __inline__ void putc(char c) -{ - while (UART5_FR & (1 << 5)) - barrier(); - - UART5_DR = c; -} - -/* - * This does not append a newline - */ -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c deleted file mode 100644 index 41e4201972d5..000000000000 --- a/arch/arm/mach-pnx4008/irq.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/arm/mach-pnx4008/irq.c - * - * PNX4008 IRQ controller driver - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * Based on reference code received from Philips: - * Copyright (C) 2003 Philips Semiconductors - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/mm.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/setup.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <mach/irq.h> - -static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES; - -static void pnx4008_mask_irq(struct irq_data *d) -{ - __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ -} - -static void pnx4008_unmask_irq(struct irq_data *d) -{ - __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */ -} - -static void pnx4008_mask_ack_irq(struct irq_data *d) -{ - __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */ - __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */ -} - -static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) -{ - switch (type) { - case IRQ_TYPE_EDGE_RISING: - __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ - __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ - irq_set_handler(d->irq, handle_edge_irq); - break; - case IRQ_TYPE_EDGE_FALLING: - __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ - __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ - irq_set_handler(d->irq, handle_edge_irq); - break; - case IRQ_TYPE_LEVEL_LOW: - __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ - __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ - irq_set_handler(d->irq, handle_level_irq); - break; - case IRQ_TYPE_LEVEL_HIGH: - __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ - __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ - irq_set_handler(d->irq, handle_level_irq); - break; - - /* IRQ_TYPE_EDGE_BOTH is not supported */ - default: - printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type); - return -1; - } - return 0; -} - -static struct irq_chip pnx4008_irq_chip = { - .irq_ack = pnx4008_mask_ack_irq, - .irq_mask = pnx4008_mask_irq, - .irq_unmask = pnx4008_unmask_irq, - .irq_set_type = pnx4008_set_irq_type, -}; - -void __init pnx4008_init_irq(void) -{ - unsigned int i; - - /* configure IRQ's */ - for (i = 0; i < NR_IRQS; i++) { - set_irq_flags(i, IRQF_VALID); - irq_set_chip(i, &pnx4008_irq_chip); - pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); - } - - /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */ - pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N), - pnx4008_irq_type[SUB1_IRQ_N]); - pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N), - pnx4008_irq_type[SUB2_IRQ_N]); - pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N), - pnx4008_irq_type[SUB1_FIQ_N]); - pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N), - pnx4008_irq_type[SUB2_FIQ_N]); - - /* mask all others */ - __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | - (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N), - INTC_ER(MAIN_BASE_INT)); - __raw_writel(0, INTC_ER(SIC1_BASE_INT)); - __raw_writel(0, INTC_ER(SIC2_BASE_INT)); -} - diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c deleted file mode 100644 index 26f8d06b142a..000000000000 --- a/arch/arm/mach-pnx4008/pm.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/arm/mach-pnx4008/pm.c - * - * Power Management driver for PNX4008 - * - * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/pm.h> -#include <linux/rtc.h> -#include <linux/sched.h> -#include <linux/proc_fs.h> -#include <linux/suspend.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/slab.h> - -#include <asm/cacheflush.h> - -#include <mach/hardware.h> -#include <mach/pm.h> -#include <mach/clock.h> - -#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE) - -static void *saved_sram; - -static struct clk *pll4_clk; - -static inline void pnx4008_standby(void) -{ - void (*pnx4008_cpu_standby_ptr) (void); - - local_irq_disable(); - local_fiq_disable(); - - clk_disable(pll4_clk); - - /*saving portion of SRAM to be used by suspend function. */ - memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz); - - /*make sure SRAM copy gets physically written into SDRAM. - SDRAM will be placed into self-refresh during power down */ - flush_cache_all(); - - /*copy suspend function into SRAM */ - memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz); - - /*do suspend */ - pnx4008_cpu_standby_ptr = (void *)SRAM_VA; - pnx4008_cpu_standby_ptr(); - - /*restoring portion of SRAM that was used by suspend function */ - memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz); - - clk_enable(pll4_clk); - - local_fiq_enable(); - local_irq_enable(); -} - -static inline void pnx4008_suspend(void) -{ - void (*pnx4008_cpu_suspend_ptr) (void); - - local_irq_disable(); - local_fiq_disable(); - - clk_disable(pll4_clk); - - __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT)); - __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT)); - - /*saving portion of SRAM to be used by suspend function. */ - memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz); - - /*make sure SRAM copy gets physically written into SDRAM. - SDRAM will be placed into self-refresh during power down */ - flush_cache_all(); - - /*copy suspend function into SRAM */ - memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz); - - /*do suspend */ - pnx4008_cpu_suspend_ptr = (void *)SRAM_VA; - pnx4008_cpu_suspend_ptr(); - - /*restoring portion of SRAM that was used by suspend function */ - memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz); - - clk_enable(pll4_clk); - - local_fiq_enable(); - local_irq_enable(); -} - -static int pnx4008_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_STANDBY: - pnx4008_standby(); - break; - case PM_SUSPEND_MEM: - pnx4008_suspend(); - break; - } - return 0; -} - -static int pnx4008_pm_valid(suspend_state_t state) -{ - return (state == PM_SUSPEND_STANDBY) || - (state == PM_SUSPEND_MEM); -} - -static const struct platform_suspend_ops pnx4008_pm_ops = { - .enter = pnx4008_pm_enter, - .valid = pnx4008_pm_valid, -}; - -int __init pnx4008_pm_init(void) -{ - u32 sram_size_to_allocate; - - pll4_clk = clk_get(0, "ck_pll4"); - if (IS_ERR(pll4_clk)) { - printk(KERN_ERR - "PM Suspend cannot acquire ARM(PLL4) clock control\n"); - return PTR_ERR(pll4_clk); - } - - if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz) - sram_size_to_allocate = pnx4008_cpu_standby_sz; - else - sram_size_to_allocate = pnx4008_cpu_suspend_sz; - - saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC); - if (!saved_sram) { - printk(KERN_ERR - "PM Suspend: cannot allocate memory to save portion of SRAM\n"); - clk_put(pll4_clk); - return -ENOMEM; - } - - suspend_set_ops(&pnx4008_pm_ops); - return 0; -} diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c deleted file mode 100644 index 374c138ac1ac..000000000000 --- a/arch/arm/mach-pnx4008/serial.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * linux/arch/arm/mach-pnx4008/serial.c - * - * PNX4008 UART initialization - * - * Copyright: MontaVista Software Inc. (c) 2005 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/io.h> - -#include <mach/platform.h> -#include <mach/hardware.h> - -#include <linux/serial_core.h> -#include <linux/serial_reg.h> - -#include <mach/gpio-pnx4008.h> -#include <mach/clock.h> - -#define UART_3 0 -#define UART_4 1 -#define UART_5 2 -#define UART_6 3 -#define UART_UNKNOWN (-1) - -#define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE) -#define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE) -#define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE) -#define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE) - -#define UART_FCR_OFFSET 8 -#define UART_FIFO_SIZE 64 - -void pnx4008_uart_init(void) -{ - u32 tmp; - int i = UART_FIFO_SIZE; - - __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET); - __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET); - - /* Send a NULL to fix the UART HW bug */ - __raw_writel(0x00, UART5_BASE_VA); - __raw_writel(0x00, UART3_BASE_VA); - - while (i--) { - tmp = __raw_readl(UART5_BASE_VA); - tmp = __raw_readl(UART3_BASE_VA); - } - __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET); - __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET); - - /* setup wakeup interrupt */ - start_int_set_rising_edge(SE_U3_RX_INT); - start_int_ack(SE_U3_RX_INT); - start_int_umask(SE_U3_RX_INT); - - start_int_set_rising_edge(SE_U5_RX_INT); - start_int_ack(SE_U5_RX_INT); - start_int_umask(SE_U5_RX_INT); -} - diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S deleted file mode 100644 index f4eed495d295..000000000000 --- a/arch/arm/mach-pnx4008/sleep.S +++ /dev/null @@ -1,195 +0,0 @@ -/* - * linux/arch/arm/mach-pnx4008/sleep.S - * - * PNX4008 support for STOP mode and SDRAM self-refresh - * - * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <mach/hardware.h> - -#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE) -#define PWR_CTRL_REG_OFFS 0x44 - -#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE) -#define MPMC_STATUS_REG_OFFS 0x4 - - .text - -ENTRY(pnx4008_cpu_suspend) - @this function should be entered in Direct run mode. - - @ save registers on stack - stmfd sp!, {r0 - r6, lr} - - @ setup Power Manager base address in r4 - @ and put it's value in r5 - mov r4, #(PWRMAN_VA_BASE & 0xff000000) - orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000) - orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00) - orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff) - ldr r5, [r4, #PWR_CTRL_REG_OFFS] - - @ setup SDRAM controller base address in r2 - @ and put it's value in r3 - mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff) - ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround - - @ clear SDRAM self-refresh bit latch - and r5, r5, #(~(1 << 8)) - @ clear SDRAM self-refresh bit - and r5, r5, #(~(1 << 9)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ do save current bit settings in r1 - mov r1, r5 - - @ set SDRAM self-refresh bit - orr r5, r5, #(1 << 9) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ set SDRAM self-refresh bit latch - orr r5, r5, #(1 << 8) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ clear SDRAM self-refresh bit latch - and r5, r5, #(~(1 << 8)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ clear SDRAM self-refresh bit - and r5, r5, #(~(1 << 9)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ wait for SDRAM to get into self-refresh mode -2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS] - tst r3, #(1 << 2) - beq 2b - - @ to prepare SDRAM to get out of self-refresh mode after wakeup - orr r5, r5, #(1 << 7) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ do enter stop mode - orr r5, r5, #(1 << 0) - str r5, [r4, #PWR_CTRL_REG_OFFS] - nop - nop - nop - nop - nop - nop - nop - nop - nop - - @ sleeping now... - - @ coming out of STOP mode into Direct Run mode - @ clear STOP mode and SDRAM self-refresh bits - str r1, [r4, #PWR_CTRL_REG_OFFS] - - @ wait for SDRAM to get out self-refresh mode -3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS] - tst r3, #5 - bne 3b - - @ restore regs and return - ldmfd sp!, {r0 - r6, pc} - -ENTRY(pnx4008_cpu_suspend_sz) - .word . - pnx4008_cpu_suspend - -ENTRY(pnx4008_cpu_standby) - @ save registers on stack - stmfd sp!, {r0 - r6, lr} - - @ setup Power Manager base address in r4 - @ and put it's value in r5 - mov r4, #(PWRMAN_VA_BASE & 0xff000000) - orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000) - orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00) - orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff) - ldr r5, [r4, #PWR_CTRL_REG_OFFS] - - @ setup SDRAM controller base address in r2 - @ and put it's value in r3 - mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00) - orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff) - ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround - - @ clear SDRAM self-refresh bit latch - and r5, r5, #(~(1 << 8)) - @ clear SDRAM self-refresh bit - and r5, r5, #(~(1 << 9)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ do save current bit settings in r1 - mov r1, r5 - - @ set SDRAM self-refresh bit - orr r5, r5, #(1 << 9) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ set SDRAM self-refresh bit latch - orr r5, r5, #(1 << 8) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ clear SDRAM self-refresh bit latch - and r5, r5, #(~(1 << 8)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ clear SDRAM self-refresh bit - and r5, r5, #(~(1 << 9)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ wait for SDRAM to get into self-refresh mode -2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS] - tst r3, #(1 << 2) - beq 2b - - @ set 'get out of self-refresh mode after wakeup' bit - orr r5, r5, #(1 << 7) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now... - - @ set SDRAM self-refresh bit latch - orr r5, r5, #(1 << 8) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ clear SDRAM self-refresh bit latch - and r5, r5, #(~(1 << 8)) - str r5, [r4, #PWR_CTRL_REG_OFFS] - - @ wait for SDRAM to get out self-refresh mode -3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS] - tst r3, #5 - bne 3b - - @ restore regs and return - ldmfd sp!, {r0 - r6, pc} - -ENTRY(pnx4008_cpu_standby_sz) - .word . - pnx4008_cpu_standby - -ENTRY(pnx4008_cache_clean_invalidate) - stmfd sp!, {r0 - r6, lr} -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache -#else -1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate - bne 1b -#endif - ldmfd sp!, {r0 - r6, pc} diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c deleted file mode 100644 index 47a7ae96156a..000000000000 --- a/arch/arm/mach-pnx4008/time.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * arch/arm/mach-pnx4008/time.c - * - * PNX4008 Timers - * - * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/sched.h> -#include <linux/spinlock.h> -#include <linux/module.h> -#include <linux/kallsyms.h> -#include <linux/time.h> -#include <linux/timex.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/mach/time.h> -#include <asm/errno.h> - -#include "time.h" - -/*! Note: all timers are UPCOUNTING */ - -/*! - * Returns number of us since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - */ -static unsigned long pnx4008_gettimeoffset(void) -{ - u32 ticks_to_match = - __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER); - u32 elapsed = LATCH - ticks_to_match; - return (elapsed * (tick_nsec / 1000)) / LATCH; -} - -/*! - * IRQ handler for the timer - */ -static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id) -{ - if (__raw_readl(HSTIM_INT) & MATCH0_INT) { - - do { - timer_tick(); - - /* - * this algorithm takes care of possible delay - * for this interrupt handling longer than a normal - * timer period - */ - __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH, - HSTIM_MATCH0); - __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */ - - /* - * The goal is to keep incrementing HSTIM_MATCH0 - * register until HSTIM_MATCH0 indicates time after - * what HSTIM_COUNTER indicates. - */ - } while ((signed) - (__raw_readl(HSTIM_MATCH0) - - __raw_readl(HSTIM_COUNTER)) < 0); - } - - return IRQ_HANDLED; -} - -static struct irqaction pnx4008_timer_irq = { - .name = "PNX4008 Tick Timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = pnx4008_timer_interrupt -}; - -/*! - * Set up timer and timer interrupt. - */ -static __init void pnx4008_setup_timer(void) -{ - __raw_writel(RESET_COUNT, MSTIM_CTRL); - while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ - __raw_writel(0, MSTIM_CTRL); /* stop the timer */ - __raw_writel(0, MSTIM_MCTRL); - - __raw_writel(RESET_COUNT, HSTIM_CTRL); - while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ - __raw_writel(0, HSTIM_CTRL); - __raw_writel(0, HSTIM_MCTRL); - __raw_writel(0, HSTIM_CCR); - __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */ - __raw_writel(LATCH, HSTIM_MATCH0); - __raw_writel(MR0_INT, HSTIM_MCTRL); - - setup_irq(HSTIMER_INT, &pnx4008_timer_irq); - - __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */ -} - -/* Timer Clock Control in PM register */ -#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC)) -#define WATCHDOG_CLK_EN 1 -#define TIMER_CLK_EN 2 /* HS and MS timers? */ - -static u32 timclk_ctrl_reg_save; - -void pnx4008_timer_suspend(void) -{ - timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG); - __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */ -} - -void pnx4008_timer_resume(void) -{ - __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */ -} - -struct sys_timer pnx4008_timer = { - .init = pnx4008_setup_timer, - .offset = pnx4008_gettimeoffset, - .suspend = pnx4008_timer_suspend, - .resume = pnx4008_timer_resume, -}; - diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h deleted file mode 100644 index 75e88c570aa7..000000000000 --- a/arch/arm/mach-pnx4008/time.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * arch/arm/mach-pnx4008/include/mach/timex.h - * - * PNX4008 timers header file - * - * Author: Dmitry Chigirev <source@mvista.com> - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef PNX_TIME_H -#define PNX_TIME_H - -#include <linux/io.h> -#include <mach/hardware.h> - -#define TICKS2USECS(x) (x) - -/* MilliSecond Timer - Chapter 21 Page 202 */ - -#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0)) -#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4)) -#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8)) -#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14)) -#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18)) -#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c)) - -/* High Speed Timer - Chpater 22, Page 205 */ - -#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0)) -#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4)) -#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8)) -#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC)) -#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10)) -#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14)) -#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18)) -#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c)) -#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20)) -#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28)) -#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C)) -#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30)) - -/* IMPORTANT: both timers are UPCOUNTING */ - -/* xSTIM_MCTRL bit definitions */ -#define MR0_INT 1 -#define RESET_COUNT0 (1<<1) -#define STOP_COUNT0 (1<<2) -#define MR1_INT (1<<3) -#define RESET_COUNT1 (1<<4) -#define STOP_COUNT1 (1<<5) -#define MR2_INT (1<<6) -#define RESET_COUNT2 (1<<7) -#define STOP_COUNT2 (1<<8) - -/* xSTIM_CTRL bit definitions */ -#define COUNT_ENAB 1 -#define RESET_COUNT (1<<1) -#define DEBUG_EN (1<<2) - -/* xSTIM_INT bit definitions */ -#define MATCH0_INT 1 -#define MATCH1_INT (1<<1) -#define MATCH2_INT (1<<2) -#define RTC_TICK0 (1<<4) -#define RTC_TICK1 (1<<5) - -#endif diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig new file mode 100644 index 000000000000..41fc85327673 --- /dev/null +++ b/arch/arm/mach-prima2/Kconfig @@ -0,0 +1,19 @@ +if ARCH_SIRF + +menu "CSR SiRF primaII/Marco/Polo Specific Features" + +config ARCH_PRIMA2 + bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" + default y + select CPU_V7 + select ZONE_DMA + select SIRF_IRQ + help + Support for CSR SiRFSoC ARM Cortex A9 Platform + +endmenu + +config SIRF_IRQ + bool + +endif diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 13dd1604d951..fc9ce22e2b5a 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -1,9 +1,8 @@ obj-y := timer.o -obj-y += irq.o -obj-y += clock.o obj-y += rstc.o -obj-y += prima2.o +obj-y += common.o obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o +obj-$(CONFIG_SIRF_IRQ) += irq.o diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot index c77a4883a4ee..98167da874c9 100644 --- a/arch/arm/mach-prima2/Makefile.boot +++ b/arch/arm/mach-prima2/Makefile.boot @@ -1,3 +1,5 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 + +dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c deleted file mode 100644 index aebad7e565cf..000000000000 --- a/arch/arm/mach-prima2/clock.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Clock tree for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include <linux/module.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <asm/mach/map.h> -#include <mach/map.h> - -#define SIRFSOC_CLKC_CLK_EN0 0x0000 -#define SIRFSOC_CLKC_CLK_EN1 0x0004 -#define SIRFSOC_CLKC_REF_CFG 0x0014 -#define SIRFSOC_CLKC_CPU_CFG 0x0018 -#define SIRFSOC_CLKC_MEM_CFG 0x001c -#define SIRFSOC_CLKC_SYS_CFG 0x0020 -#define SIRFSOC_CLKC_IO_CFG 0x0024 -#define SIRFSOC_CLKC_DSP_CFG 0x0028 -#define SIRFSOC_CLKC_GFX_CFG 0x002c -#define SIRFSOC_CLKC_MM_CFG 0x0030 -#define SIRFSOC_LKC_LCD_CFG 0x0034 -#define SIRFSOC_CLKC_MMC_CFG 0x0038 -#define SIRFSOC_CLKC_PLL1_CFG0 0x0040 -#define SIRFSOC_CLKC_PLL2_CFG0 0x0044 -#define SIRFSOC_CLKC_PLL3_CFG0 0x0048 -#define SIRFSOC_CLKC_PLL1_CFG1 0x004c -#define SIRFSOC_CLKC_PLL2_CFG1 0x0050 -#define SIRFSOC_CLKC_PLL3_CFG1 0x0054 -#define SIRFSOC_CLKC_PLL1_CFG2 0x0058 -#define SIRFSOC_CLKC_PLL2_CFG2 0x005c -#define SIRFSOC_CLKC_PLL3_CFG2 0x0060 - -#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000) - -#define KHZ 1000 -#define MHZ (KHZ * KHZ) - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); - struct clk *(*get_parent)(struct clk *clk); - int (*set_parent)(struct clk *clk, struct clk *parent); -}; - -struct clk { - struct clk *parent; /* parent clk */ - unsigned long rate; /* clock rate in Hz */ - signed char usage; /* clock enable count */ - signed char enable_bit; /* enable bit: 0 ~ 63 */ - unsigned short regofs; /* register offset */ - struct clk_ops *ops; /* clock operation */ -}; - -static DEFINE_SPINLOCK(clocks_lock); - -static inline unsigned long clkc_readl(unsigned reg) -{ - return readl(SIRFSOC_CLOCK_VA_BASE + reg); -} - -static inline void clkc_writel(u32 val, unsigned reg) -{ - writel(val, SIRFSOC_CLOCK_VA_BASE + reg); -} - -/* - * osc_rtc - real time oscillator - 32.768KHz - * osc_sys - high speed oscillator - 26MHz - */ - -static struct clk clk_rtc = { - .rate = 32768, -}; - -static struct clk clk_osc = { - .rate = 26 * MHZ, -}; - -/* - * std pll - */ -static unsigned long std_pll_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - - SIRFSOC_CLKC_PLL1_CFG0; - - if (clkc_readl(regcfg2) & BIT(2)) { - /* pll bypass mode */ - clk->rate = fin; - } else { - /* fout = fin * nf / nr / od */ - u32 cfg0 = clkc_readl(clk->regofs); - u32 nf = (cfg0 & (BIT(13) - 1)) + 1; - u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; - u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; - WARN_ON(fin % MHZ); - clk->rate = fin / MHZ * nf / nr / od * MHZ; - } - - return clk->rate; -} - -static int std_pll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin, nf, nr, od, reg; - - /* - * fout = fin * nf / (nr * od); - * set od = 1, nr = fin/MHz, so fout = nf * MHz - */ - - nf = rate / MHZ; - if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) - return -EINVAL; - - fin = clk_get_rate(clk->parent); - BUG_ON(fin < MHZ); - - nr = fin / MHZ; - BUG_ON((fin % MHZ) || nr > BIT(6)); - - od = 1; - - reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); - clkc_writel(reg, clk->regofs); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; - clkc_writel((nf >> 1) - 1, reg); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; - while (!(clkc_readl(reg) & BIT(6))) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - return 0; -} - -static struct clk_ops std_pll_ops = { - .get_rate = std_pll_get_rate, - .set_rate = std_pll_set_rate, -}; - -static struct clk clk_pll1 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL1_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll2 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL2_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll3 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL3_CFG0, - .ops = &std_pll_ops, -}; - -/* - * clock domains - cpu, mem, sys/io - */ - -static struct clk clk_mem; - -static struct clk *dmn_get_parent(struct clk *clk) -{ - struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - WARN_ON((cfg & (BIT(3) - 1)) > 4); - return clks[cfg & (BIT(3) - 1)]; -} - -static int dmn_set_parent(struct clk *clk, struct clk *parent) -{ - const struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - int i; - for (i = 0; i < ARRAY_SIZE(clks); i++) { - if (clks[i] == parent) { - cfg &= ~(BIT(3) - 1); - clkc_writel(cfg | i, clk->regofs); - /* BIT(3) - switching status: 1 - busy, 0 - done */ - while (clkc_readl(clk->regofs) & BIT(3)) - cpu_relax(); - return 0; - } - } - return -EINVAL; -} - -static unsigned long dmn_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 cfg = clkc_readl(clk->regofs); - if (cfg & BIT(24)) { - /* fcd bypass mode */ - clk->rate = fin; - } else { - /* - * wait count: bit[19:16], hold count: bit[23:20] - */ - u32 wait = (cfg >> 16) & (BIT(4) - 1); - u32 hold = (cfg >> 20) & (BIT(4) - 1); - - clk->rate = fin / (wait + hold + 2); - } - - return clk->rate; -} - -static int dmn_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin; - unsigned ratio, wait, hold, reg; - unsigned bits = (clk == &clk_mem) ? 3 : 4; - - fin = clk_get_rate(clk->parent); - ratio = fin / rate; - - if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) - return -EINVAL; - - WARN_ON(fin % rate); - - wait = (ratio >> 1) - 1; - hold = ratio - wait - 2; - - reg = clkc_readl(clk->regofs); - reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); - reg |= (wait << 16) | (hold << 20) | BIT(25); - clkc_writel(reg, clk->regofs); - - /* waiting FCD been effective */ - while (clkc_readl(clk->regofs) & BIT(25)) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - - return 0; -} - -/* - * cpu clock has no FCD register in Prima2, can only change pll - */ -static int cpu_set_rate(struct clk *clk, unsigned long rate) -{ - int ret1, ret2; - struct clk *cur_parent, *tmp_parent; - - cur_parent = dmn_get_parent(clk); - BUG_ON(cur_parent == NULL || cur_parent->usage > 1); - - /* switch to tmp pll before setting parent clock's rate */ - tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1; - ret1 = dmn_set_parent(clk, tmp_parent); - BUG_ON(ret1); - - ret2 = clk_set_rate(cur_parent, rate); - - ret1 = dmn_set_parent(clk, cur_parent); - - clk->rate = 0; /* set to zero will force recalculation */ - - return ret2 ? ret2 : ret1; -} - -static struct clk_ops cpu_ops = { - .get_parent = dmn_get_parent, - .set_parent = dmn_set_parent, - .set_rate = cpu_set_rate, -}; - -static struct clk clk_cpu = { - .parent = &clk_pll1, - .regofs = SIRFSOC_CLKC_CPU_CFG, - .ops = &cpu_ops, -}; - - -static struct clk_ops msi_ops = { - .set_rate = dmn_set_rate, - .get_rate = dmn_get_rate, - .set_parent = dmn_set_parent, - .get_parent = dmn_get_parent, -}; - -static struct clk clk_mem = { - .parent = &clk_pll2, - .regofs = SIRFSOC_CLKC_MEM_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_sys = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_SYS_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_io = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_IO_CFG, - .ops = &msi_ops, -}; - -/* - * on-chip clock sets - */ -static struct clk_lookup onchip_clks[] = { - { - .dev_id = "rtc", - .clk = &clk_rtc, - }, { - .dev_id = "osc", - .clk = &clk_osc, - }, { - .dev_id = "pll1", - .clk = &clk_pll1, - }, { - .dev_id = "pll2", - .clk = &clk_pll2, - }, { - .dev_id = "pll3", - .clk = &clk_pll3, - }, { - .dev_id = "cpu", - .clk = &clk_cpu, - }, { - .dev_id = "mem", - .clk = &clk_mem, - }, { - .dev_id = "sys", - .clk = &clk_sys, - }, { - .dev_id = "io", - .clk = &clk_io, - }, -}; - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, flags); - if (!clk->usage++ && clk->ops && clk->ops->enable) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return; - - WARN_ON(!clk->usage); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->usage == 0 && clk->ops && clk->ops->disable) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->rate) - return clk->rate; - - if (clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->ops && clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_rate) - return -EINVAL; - - return clk->ops->set_rate(clk, rate); -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret; - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_parent) - return -EINVAL; - - spin_lock_irqsave(&clocks_lock, flags); - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - BUG_ON(clk->parent->usage < 0); - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, flags); - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return NULL; - - if (!clk->ops || !clk->ops->get_parent) - return clk->parent; - - spin_lock_irqsave(&clocks_lock, flags); - clk->parent = clk->ops->get_parent(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static void __init sirfsoc_clk_init(void) -{ - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); -} - -static struct of_device_id clkc_ids[] = { - { .compatible = "sirf,prima2-clkc" }, - {}, -}; - -void __init sirfsoc_of_clk_init(void) -{ - struct device_node *np; - struct resource res; - struct map_desc sirfsoc_clkc_iodesc = { - .virtual = SIRFSOC_CLOCK_VA_BASE, - .type = MT_DEVICE, - }; - - np = of_find_matching_node(NULL, clkc_ids); - if (!np) - panic("unable to find compatible clkc node in dtb\n"); - - if (of_address_to_resource(np, 0, &res)) - panic("unable to find clkc range in dtb"); - of_node_put(np); - - sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start); - sirfsoc_clkc_iodesc.length = 1 + res.end - res.start; - - iotable_init(&sirfsoc_clkc_iodesc, 1); - - sirfsoc_clk_init(); -} diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c index 8f0429d4b79f..f25a54194639 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/common.c @@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } -static const char *prima2cb_dt_match[] __initdata = { - "sirf,prima2-cb", +#ifdef CONFIG_ARCH_PRIMA2 +static const char *prima2_dt_match[] __initdata = { + "sirf,prima2", NULL }; -MACHINE_START(PRIMA2_EVB, "prima2cb") +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ - .atag_offset = 0x100, - .init_early = sirfsoc_of_clk_init, .map_io = sirfsoc_map_lluart, .init_irq = sirfsoc_of_irq_init, .timer = &sirfsoc_timer, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, - .dt_compat = prima2cb_dt_match, + .dt_compat = prima2_dt_match, .restart = sirfsoc_restart, MACHINE_END +#endif diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h index 83125c6a30b3..0c898fcf909c 100644 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ b/arch/arm/mach-prima2/include/mach/uncompress.h @@ -25,11 +25,11 @@ static __inline__ void putc(char c) * during kernel decompression, all mappings are flat: * virt_addr == phys_addr */ - while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) + while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) & SIRFSOC_UART1_TXFIFO_FULL) barrier(); - __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); + __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); } static inline void flush(void) diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index a7b9415d30f8..7dee9176e77a 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void) np = of_find_matching_node(NULL, intc_ids); if (!np) - panic("unable to find compatible intc node in dtb\n"); + return; sirfsoc_intc_base = of_iomap(np, 0); if (!sirfsoc_intc_base) diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index f224107de7bc..d95bf252f694 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c @@ -21,6 +21,8 @@ #include <asm/sched_clock.h> #include <asm/mach/time.h> +#include "common.h" + #define SIRFSOC_TIMER_COUNTER_LO 0x0000 #define SIRFSOC_TIMER_COUNTER_HI 0x0004 #define SIRFSOC_TIMER_MATCH_0 0x0008 @@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void) static void __init sirfsoc_timer_init(void) { unsigned long rate; + struct clk *clk; + + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); /* timer's input clock is io clock */ - struct clk *clk = clk_get_sys("io", NULL); + clk = clk_get_sys("io", NULL); BUG_ON(IS_ERR(clk)); diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index fe2d1f80ef50..8e6288de69b9 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO if !ARCH_PXA_V7 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" +config MACH_PXA3XX_DT + bool "Support PXA3xx platforms from device tree" + select PXA3xx + select CPU_PXA300 + select POWER_SUPPLY + select HAVE_PWM + select USE_OF + help + Include support for Marvell PXA3xx based platforms using + the device tree. Needn't select any other machine while + MACH_PXA3XX_DT is enabled. + config ARCH_LUBBOCK bool "Intel DBPXA250 Development Platform (aka Lubbock)" select PXA25x diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d4337e300ada..ee88d6eae648 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o # NOTE: keep the order of boards in accordance to their order in Kconfig +# Device Tree support +obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o + # Intel/Marvell Dev Platforms obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 2a37a9a8f621..d4e9499832dc 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk) if (clk->cken < 32) CKENA |= mask; - else + else if (clk->cken < 64) CKENB |= mask; + else + CKENC |= mask; } void clk_pxa3xx_cken_disable(struct clk *clk) @@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk) if (clk->cken < 32) CKENA &= ~mask; - else + else if (clk->cken < 64) CKENB &= ~mask; + else + CKENC &= ~mask; } const struct clkops clk_pxa3xx_cken_ops = { diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 166eee5b8a70..c1f3b1279d97 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -6,7 +6,6 @@ #include <linux/spi/pxa2xx_spi.h> #include <linux/i2c/pxa-i2c.h> -#include <asm/pmu.h> #include <mach/udc.h> #include <mach/pxa3xx-u2d.h> #include <mach/pxafb.h> @@ -42,7 +41,7 @@ static struct resource pxa_resource_pmu = { struct platform_device pxa_device_pmu = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .resource = &pxa_resource_pmu, .num_resources = 1, }; diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 207ecb49a61b..f4d48d20754e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -131,6 +131,7 @@ #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ #define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 5dae15ea6718..b6cc1816463e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -17,6 +17,8 @@ #include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <asm/exception.h> @@ -25,8 +27,6 @@ #include "generic.h" -#define IRQ_BASE io_p2v(0x40d00000) - #define ICIP (0x000) #define ICMR (0x004) #define ICLR (0x008) @@ -48,22 +48,19 @@ * This is for peripheral IRQs internal to the PXA chip. */ +static void __iomem *pxa_irq_base; static int pxa_internal_irq_nr; - -static inline int cpu_has_ipr(void) -{ - return !cpu_is_pxa25x(); -} +static bool cpu_has_ipr; static inline void __iomem *irq_base(int i) { - static unsigned long phys_base[] = { - 0x40d00000, - 0x40d0009c, - 0x40d00130, + static unsigned long phys_base_offset[] = { + 0x0, + 0x9c, + 0x130, }; - return io_p2v(phys_base[i]); + return pxa_irq_base + phys_base_offset[i]; } void pxa_mask_irq(struct irq_data *d) @@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) uint32_t icip, icmr, mask; do { - icip = __raw_readl(IRQ_BASE + ICIP); - icmr = __raw_readl(IRQ_BASE + ICMR); + icip = __raw_readl(pxa_irq_base + ICIP); + icmr = __raw_readl(pxa_irq_base + ICMR); mask = icip & icmr; if (mask == 0) @@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; + cpu_has_ipr = !cpu_is_pxa25x(); + pxa_irq_base = io_p2v(0x40d00000); for (n = 0; n < irq_nr; n += 32) { void __iomem *base = irq_base(n >> 5); @@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { /* initialize interrupt priority */ - if (cpu_has_ipr()) - __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); + if (cpu_has_ipr) + __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i)); irq = PXA_IRQ(i); irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, @@ -168,9 +167,9 @@ static int pxa_irq_suspend(void) __raw_writel(0, base + ICMR); } - if (cpu_has_ipr()) { + if (cpu_has_ipr) { for (i = 0; i < pxa_internal_irq_nr; i++) - saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); + saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); } return 0; @@ -187,11 +186,11 @@ static void pxa_irq_resume(void) __raw_writel(0, base + ICLR); } - if (cpu_has_ipr()) + if (cpu_has_ipr) for (i = 0; i < pxa_internal_irq_nr; i++) - __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); + __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); - __raw_writel(1, IRQ_BASE + ICCR); + __raw_writel(1, pxa_irq_base + ICCR); } #else #define pxa_irq_suspend NULL @@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = { .suspend = pxa_irq_suspend, .resume = pxa_irq_resume, }; + +#ifdef CONFIG_OF +static struct irq_domain *pxa_irq_domain; + +static int pxa_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + void __iomem *base = irq_base(hw / 32); + + /* initialize interrupt priority */ + if (cpu_has_ipr) + __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); + + irq_set_chip_and_handler(hw, &pxa_internal_irq_chip, + handle_level_irq); + irq_set_chip_data(hw, base); + set_irq_flags(hw, IRQF_VALID); + + return 0; +} + +static struct irq_domain_ops pxa_irq_ops = { + .map = pxa_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static const struct of_device_id intc_ids[] __initconst = { + { .compatible = "marvell,pxa-intc", }, + {} +}; + +void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) +{ + struct device_node *node; + const struct of_device_id *of_id; + struct pxa_intc_conf *conf; + struct resource res; + int n, ret; + + node = of_find_matching_node(NULL, intc_ids); + if (!node) { + pr_err("Failed to find interrupt controller in arch-pxa\n"); + return; + } + of_id = of_match_node(intc_ids, node); + conf = of_id->data; + + ret = of_property_read_u32(node, "marvell,intc-nr-irqs", + &pxa_internal_irq_nr); + if (ret) { + pr_err("Not found marvell,intc-nr-irqs property\n"); + return; + } + + ret = of_address_to_resource(node, 0, &res); + if (ret < 0) { + pr_err("No registers defined for node\n"); + return; + } + pxa_irq_base = io_p2v(res.start); + + if (of_find_property(node, "marvell,intc-priority", NULL)) + cpu_has_ipr = 1; + + ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0); + if (ret < 0) { + pr_err("Failed to allocate IRQ numbers\n"); + return; + } + + pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, + &pxa_irq_ops, NULL); + if (!pxa_irq_domain) + panic("Unable to add PXA IRQ domain\n"); + + irq_set_default_host(pxa_irq_domain); + + for (n = 0; n < pxa_internal_irq_nr; n += 32) { + void __iomem *base = irq_base(n >> 5); + + __raw_writel(0, base + ICMR); /* disable all IRQs */ + __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ + } + + /* only unmasked interrupts kick us out of idle */ + __raw_writel(1, irq_base(0) + ICCR); + + pxa_internal_irq_chip.irq_set_wake = fn; +} +#endif /* CONFIG_OF */ diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c new file mode 100644 index 000000000000..c9192cea0033 --- /dev/null +++ b/arch/arm/mach-pxa/pxa-dt.c @@ -0,0 +1,63 @@ +/* + * linux/arch/arm/mach-pxa/pxa-dt.c + * + * Copyright (C) 2012 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/irqs.h> +#include <mach/pxa3xx.h> + +#include "generic.h" + +#ifdef CONFIG_PXA3xx +extern void __init pxa3xx_dt_init_irq(void); + +static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40100000, "pxa2xx-uart.0", NULL), + OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40200000, "pxa2xx-uart.1", NULL), + OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), + OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL), + OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL), + OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL), + OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL), + OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL), + OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL), + OF_DEV_AUXDATA("marvell,pxa3xx-nand", 0x43100000, "pxa3xx-nand", NULL), + {} +}; + +static void __init pxa3xx_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + pxa3xx_auxdata_lookup, NULL); +} + +static const char *pxa3xx_dt_board_compat[] __initdata = { + "marvell,pxa300", + "marvell,pxa310", + "marvell,pxa320", + NULL, +}; +#endif + +#ifdef CONFIG_PXA3xx +DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") + .map_io = pxa3xx_map_io, + .init_irq = pxa3xx_dt_init_irq, + .handle_irq = pxa3xx_handle_irq, + .timer = &pxa_timer, + .restart = pxa_restart, + .init_machine = pxa3xx_dt_init, + .dt_compat = pxa3xx_dt_board_compat, +MACHINE_END +#endif diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index dffb7e813d98..ff9c9574ec3e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/syscore_ops.h> #include <linux/i2c/pxa-i2c.h> @@ -40,6 +41,8 @@ #define PECR_IE(n) ((1 << ((n) * 2)) << 28) #define PECR_IS(n) ((1 << ((n) * 2)) << 29) +extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); + static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); @@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, pxa_ext_wakeup_chip.irq_set_wake = fn; } -void __init pxa3xx_init_irq(void) +static void __init __pxa3xx_init_irq(void) { /* enable CP6 access */ u32 value; @@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void) value |= (1 << 6); __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); - pxa_init_irq(56, pxa3xx_set_wake); pxa_init_ext_wakeup_irq(pxa3xx_set_wake); } +void __init pxa3xx_init_irq(void) +{ + __pxa3xx_init_irq(); + pxa_init_irq(56, pxa3xx_set_wake); +} + +#ifdef CONFIG_OF +void __init pxa3xx_dt_init_irq(void) +{ + __pxa3xx_init_irq(); + pxa_dt_irq_init(pxa3xx_set_wake); +} +#endif /* CONFIG_OF */ + static struct map_desc pxa3xx_io_desc[] __initdata = { { /* Mem Ctl */ .virtual = (unsigned long)SMEMC_VIRT, @@ -466,7 +482,8 @@ static int __init pxa3xx_init(void) register_syscore_ops(&pxa3xx_mfp_syscore_ops); register_syscore_ops(&pxa3xx_clock_syscore_ops); - ret = platform_add_devices(devices, ARRAY_SIZE(devices)); + if (!of_have_populated_dt()) + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } return ret; diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 30b1b0b3c7f7..0701ca79e7d3 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -52,7 +52,7 @@ #include <linux/spi/spi.h> #include <linux/spi/pxa2xx_spi.h> #include <linux/mfd/da903x.h> -#include <linux/sht15.h> +#include <linux/platform_data/sht15.h> #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index d22dee96484d..682467480588 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -30,7 +30,6 @@ #include <linux/ata_platform.h> #include <linux/amba/mmci.h> #include <linux/gfp.h> -#include <linux/clkdev.h> #include <linux/mtd/physmap.h> #include <mach/hardware.h> @@ -225,115 +224,10 @@ struct mmci_platform_data realview_mmc1_plat_data = { .cd_invert = true, }; -/* - * Clock handling - */ -static const struct icst_params realview_oscvco_params = { - .ref = 24000000, - .vco_max = ICST307_VCO_MAX, - .vco_min = ICST307_VCO_MIN, - .vd_min = 4 + 8, - .vd_max = 511 + 8, - .rd_min = 1 + 2, - .rd_max = 127 + 2, - .s2div = icst307_s2div, - .idx2s = icst307_idx2s, -}; - -static void realview_oscvco_set(struct clk *clk, struct icst_vco vco) -{ - void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; - u32 val; - - val = readl(clk->vcoreg) & ~0x7ffff; - val |= vco.v | (vco.r << 9) | (vco.s << 16); - - writel(0xa05f, sys_lock); - writel(val, clk->vcoreg); - writel(0, sys_lock); -} - -static const struct clk_ops oscvco_clk_ops = { - .round = icst_clk_round, - .set = icst_clk_set, - .setvco = realview_oscvco_set, -}; - -static struct clk oscvco_clk = { - .ops = &oscvco_clk_ops, - .params = &realview_oscvco_params, -}; - -/* - * These are fixed clocks. - */ -static struct clk ref24_clk = { - .rate = 24000000, -}; - -static struct clk sp804_clk = { - .rate = 1000000, -}; - -static struct clk dummy_apb_pclk; - -static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, { /* UART0 */ - .dev_id = "dev:uart0", - .clk = &ref24_clk, - }, { /* UART1 */ - .dev_id = "dev:uart1", - .clk = &ref24_clk, - }, { /* UART2 */ - .dev_id = "dev:uart2", - .clk = &ref24_clk, - }, { /* UART3 */ - .dev_id = "fpga:uart3", - .clk = &ref24_clk, - }, { /* UART3 is on the dev chip in PB1176 */ - .dev_id = "dev:uart3", - .clk = &ref24_clk, - }, { /* UART4 only exists in PB1176 */ - .dev_id = "fpga:uart4", - .clk = &ref24_clk, - }, { /* KMI0 */ - .dev_id = "fpga:kmi0", - .clk = &ref24_clk, - }, { /* KMI1 */ - .dev_id = "fpga:kmi1", - .clk = &ref24_clk, - }, { /* MMC0 */ - .dev_id = "fpga:mmc0", - .clk = &ref24_clk, - }, { /* CLCD is in the PB1176 and EB DevChip */ - .dev_id = "dev:clcd", - .clk = &oscvco_clk, - }, { /* PB:CLCD */ - .dev_id = "issp:clcd", - .clk = &oscvco_clk, - }, { /* SSP */ - .dev_id = "dev:ssp0", - .clk = &ref24_clk, - }, { /* SP804 timers */ - .dev_id = "sp804", - .clk = &sp804_clk, - }, -}; - void __init realview_init_early(void) { void __iomem *sys = __io_address(REALVIEW_SYS_BASE); - if (machine_is_realview_pb1176()) - oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET; - else - oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET; - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); } diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h deleted file mode 100644 index e58d0771b64e..000000000000 --- a/arch/arm/mach-realview/include/mach/clkdev.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -#include <plat/clock.h> - -struct clk { - unsigned long rate; - const struct clk_ops *ops; - const struct icst_params *params; - void __iomem *vcoreg; -}; - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 21661ade885f..d3b3cd216d64 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -27,11 +27,11 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/pmu.h> #include <asm/pgtable.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> @@ -296,7 +296,7 @@ static struct resource pmu_resources[] = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(pmu_resources), .resource = pmu_resources, }; @@ -413,6 +413,7 @@ static void __init realview_eb_timer_init(void) else timer_irq = IRQ_EB_TIMER0_1; + realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); realview_timer_init(timer_irq); realview_eb_twd_init(); } diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index c0ff882c5cb8..07d6672ddae7 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -29,11 +29,11 @@ #include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> #include <linux/io.h> +#include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/pmu.h> #include <asm/pgtable.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> @@ -279,7 +279,7 @@ static struct resource pmu_resource = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = 1, .resource = &pmu_resource, }; @@ -325,6 +325,7 @@ static void __init realview_pb1176_timer_init(void) timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20; + realview_clk_init(__io_address(REALVIEW_SYS_BASE), true); realview_timer_init(IRQ_DC1176_TIMER0); } diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 30779ae40c04..ec4fcd9a7e9c 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -27,11 +27,11 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/pmu.h> #include <asm/pgtable.h> #include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> @@ -262,7 +262,7 @@ static struct resource pmu_resources[] = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(pmu_resources), .resource = pmu_resources, }; @@ -311,6 +311,7 @@ static void __init realview_pb11mp_timer_init(void) timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; + realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); realview_timer_init(IRQ_TC11MP_TIMER0_1); realview_pb11mp_twd_init(); } diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 081cd72c090e..9992431b8a15 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -27,10 +27,10 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/platform_data/clk-realview.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/pmu.h> #include <asm/pgtable.h> #include <asm/hardware/gic.h> @@ -240,7 +240,7 @@ static struct resource pmu_resource = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = 1, .resource = &pmu_resource, }; @@ -260,6 +260,7 @@ static void __init realview_pba8_timer_init(void) timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; + realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); realview_timer_init(IRQ_PBA8_TIMER0_1); } diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 1ce62b9f846c..17954a327e1b 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -26,10 +26,10 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/platform_data/clk-realview.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <asm/pmu.h> #include <asm/smp_twd.h> #include <asm/pgtable.h> #include <asm/hardware/gic.h> @@ -279,7 +279,7 @@ static struct resource pmu_resources[] = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(pmu_resources), .resource = pmu_resources, }; @@ -319,6 +319,7 @@ static void __init realview_pbx_timer_init(void) timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20; + realview_clk_init(__io_address(REALVIEW_SYS_BASE), false); realview_timer_init(IRQ_PBX_TIMER0_1); realview_pbx_twd_init(); } diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index cb2883d553b5..749220f91a70 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c @@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) return 0; } +static unsigned long s3c2440_camif_upll_getrate(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); + + if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL)) + return parent_rate; + + camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK; + + return parent_rate / (camdivn + 1) / 2; +} + /* Extra S3C2440 clocks */ static struct clk s3c2440_clk_cam = { @@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = { .name = "camif-upll", .ops = &(struct clk_ops) { .set_rate = s3c2440_camif_upll_setrate, + .get_rate = s3c2440_camif_upll_getrate, .round_rate = s3c2440_camif_upll_round, }, }; diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c index a5eeb62ce1c2..57aee916bdb1 100644 --- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c +++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c @@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = { .remove = h1940bt_remove, }; - -static int __init h1940bt_init(void) -{ - return platform_driver_register(&h1940bt_driver); -} - -static void __exit h1940bt_exit(void) -{ - platform_driver_unregister(&h1940bt_driver); -} - -module_init(h1940bt_init); -module_exit(h1940bt_exit); +module_platform_driver(h1940bt_driver); MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip"); diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c index 5a7d0c0010f7..0c7ed7a2b0cd 100644 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/arch/arm/mach-s3c24xx/mach-anubis.c @@ -424,7 +424,8 @@ static void __init anubis_map_io(void) anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); } else { /* ensure that the GPIO is setup */ - s3c2410_gpio_setpin(S3C2410_GPA(0), 1); + gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPA(0)); } } diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index bb8d008d5a5c..7e15cc430688 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -380,7 +380,7 @@ int h1940_led_blink_set(unsigned gpio, int state, default: blink_gpio = S3C2410_GPA(3); check_gpio1 = S3C2410_GPA(1); - check_gpio1 = S3C2410_GPA(7); + check_gpio2 = S3C2410_GPA(7); break; } @@ -460,7 +460,7 @@ static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd) break; default: break; - }; + } } static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index ae73ba34ecc6..471334715c37 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -512,8 +512,8 @@ static void jive_power_off(void) { printk(KERN_INFO "powering system down...\n"); - s3c2410_gpio_setpin(S3C2410_GPC(5), 1); - s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); + gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPC(5)); } static void __init jive_machine_init(void) @@ -623,11 +623,11 @@ static void __init jive_machine_init(void) gpio_request(S3C2410_GPB(7), "jive spi"); gpio_direction_output(S3C2410_GPB(7), 1); - s3c2410_gpio_setpin(S3C2410_GPB(6), 0); - s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); + gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL); + gpio_free(S3C2410_GPB(6)); - s3c2410_gpio_setpin(S3C2410_GPG(8), 1); - s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); + gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPG(8)); /* initialise the WM8750 spi */ diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index bd6d2525debe..734bbfe5ea22 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -638,9 +638,9 @@ static void __init mini2440_init(void) gpio_free(S3C2410_GPG(4)); /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ + gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL); s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); - s3c2410_gpio_setpin(S3C2410_GPB(1), 0); - s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); + gpio_free(S3C2410_GPB(1)); /* mark the key as input, without pullups (there is one on the board) */ for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c index 5c05ba1c330f..a71a551094ef 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = { static void __init nexcoder_sensorboard_init(void) { - // Initialize SCCB bus - s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL - s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA - s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); - - // Power up the sensor board - s3c2410_gpio_setpin(S3C2410_GPF(1), 1); - s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN + /* Initialize SCCB bus */ + gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPE(14)); /* IICSCL */ + gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPE(15)); /* IICSDA */ + + /* Power up the sensor board */ + gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */ + gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL); + gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */ } static void __init nexcoder_map_io(void) diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c index ad2792dfbee1..5876c6ba7500 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c +++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c @@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = { }, }; -static int __init osiris_dvs_init(void) -{ - return platform_driver_register(&osiris_dvs_driver); -} - -static void __exit osiris_dvs_exit(void) -{ - platform_driver_unregister(&osiris_dvs_driver); -} - -module_init(osiris_dvs_init); -module_exit(osiris_dvs_exit); +module_platform_driver(osiris_dvs_driver); MODULE_DESCRIPTION("Simtec OSIRIS DVS support"); MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c index 95d077255024..c0fb3c1bc548 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c24xx/mach-osiris.c @@ -274,8 +274,8 @@ static int osiris_pm_suspend(void) __raw_writeb(tmp, OSIRIS_VA_CTRL0); /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA(21), 1); - s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); + gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPA(21)); return 0; } @@ -396,7 +396,8 @@ static void __init osiris_map_io(void) osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); } else { /* write-protect line to the NAND */ - s3c2410_gpio_setpin(S3C2410_GPA(0), 1); + gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL); + gpio_free(S3C2410_GPA(0)); } /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h index cdea671e8931..ac2ea767215d 100644 --- a/arch/arm/mach-sa1100/include/mach/simpad.h +++ b/arch/arm/mach-sa1100/include/mach/simpad.h @@ -87,7 +87,7 @@ #define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22) #define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23) -#define CS3_BASE 0xf1000000 +#define CS3_BASE IOMEM(0xf1000000) long simpad_get_cs3_ro(void); long simpad_get_cs3_shadow(void); diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index fbd53593be54..6ca92d0d32b2 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = { .length = 0x00800000, .type = MT_DEVICE }, { /* Simpad CS3 */ - .virtual = CS3_BASE, + .virtual = (unsigned long)CS3_BASE, .pfn = __phys_to_pfn(SA1100_CS3_PHYS), .length = 0x00100000, .type = MT_DEVICE diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index c709979ee751..9ad2e9737fb5 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -20,9 +20,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> -#define IO_BASE 0xe0000000 -#define IO_SIZE 0x08000000 -#define IO_START 0x40000000 #define ROMCARD_SIZE 0x08000000 #define ROMCARD_START 0x10000000 @@ -103,20 +100,6 @@ arch_initcall(shark_init); extern void shark_init_irq(void); -static struct map_desc shark_io_desc[] __initdata = { - { - .virtual = IO_BASE, - .pfn = __phys_to_pfn(IO_START), - .length = IO_SIZE, - .type = MT_DEVICE - } -}; - -static void __init shark_map_io(void) -{ - iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc)); -} - #define IRQ_TIMER 0 #define HZ_TIME ((1193180 + HZ/2) / HZ) @@ -157,7 +140,6 @@ static void shark_init_early(void) MACHINE_START(SHARK, "Shark") /* Maintainer: Alexander Schulz */ .atag_offset = 0x3000, - .map_io = shark_map_io, .init_early = shark_init_early, .init_irq = shark_init_irq, .timer = &shark_timer, diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index 20eb2bf2a42b..d129119a3f69 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S @@ -12,9 +12,10 @@ */ .macro addruart, rp, rv, tmp - mov \rp, #0xe0000000 - orr \rp, \rp, #0x000003f8 - mov \rv, \rp + mov \rp, #0x3f8 + orr \rv, \rp, #0xfe000000 + orr \rv, \rv, #0x00e00000 + orr \rp, \rp, #0x40000000 .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S index 5901b09fc96a..c9e49f049532 100644 --- a/arch/arm/mach-shark/include/mach/entry-macro.S +++ b/arch/arm/mach-shark/include/mach/entry-macro.S @@ -8,7 +8,8 @@ * warranty of any kind, whether express or implied. */ .macro get_irqnr_preamble, base, tmp - mov \base, #0xe0000000 + mov \base, #0xfe000000 + orr \base, \base, #0x00e00000 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h deleted file mode 100644 index 1a45fc01ff1d..000000000000 --- a/arch/arm/mach-shark/include/mach/io.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * arch/arm/mach-shark/include/mach/io.h - * - * by Alexander Schulz - * - * derived from: - * arch/arm/mach-ebsa110/include/mach/io.h - * Copyright (C) 1997,1998 Russell King - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) ((void __iomem *)(0xe0000000 + (a))) - -#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 9089407d5326..b8b4ab323a3e 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c @@ -8,12 +8,15 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/init.h> +#include <linux/io.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <asm/mach-types.h> +#define IO_START 0x40000000 + static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (dev->bus->number == 0) @@ -44,6 +47,8 @@ static int __init shark_pci_init(void) pcibios_min_mem = 0x50000000; vga_base = 0xe8000000; + pci_ioremap_io(0, IO_START); + pci_common_init(&shark_pci); return 0; diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 498efd99338d..5e410192ffb8 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -7,3 +7,7 @@ __ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ # #params_phys-y (Instead: Pass atags pointer in r2) #initrd_phys-y (Instead: Use compiled-in initramfs) + +dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb +dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb +dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index d82c010fdfc6..cfc3b5c43ba8 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -40,7 +40,6 @@ #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/sh_clk.h> -#include <linux/videodev2.h> #include <video/sh_mobile_lcdc.h> #include <video/sh_mipi_dsi.h> #include <sound/sh_fsi.h> diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index f172ca85905c..1089ee5472eb 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -432,7 +432,7 @@ static void usb1_host_port_power(int port, int power) return; /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ - __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); + __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008)); } static struct r8a66597_platdata usb1_host_data = { @@ -1224,9 +1224,9 @@ static struct i2c_board_info i2c1_devices[] = { }; -#define GPIO_PORT9CR 0xE6051009 -#define GPIO_PORT10CR 0xE605100A -#define USCCR1 0xE6058144 +#define GPIO_PORT9CR IOMEM(0xE6051009) +#define GPIO_PORT10CR IOMEM(0xE605100A) +#define USCCR1 IOMEM(0xE6058144) static void __init ap4evb_init(void) { u32 srcr4; @@ -1304,7 +1304,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_OVCN2_1, NULL); /* setup USB phy */ - __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ + __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ /* enable FSI2 port A (ak4643) */ gpio_request(GPIO_FN_FSIAIBT, NULL); @@ -1453,7 +1453,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_HDMI_CEC, NULL); /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ -#define SRCR4 0xe61580bc +#define SRCR4 IOMEM(0xe61580bc) srcr4 = __raw_readl(SRCR4); __raw_writel(srcr4 | (1 << 13), SRCR4); udelay(50); diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index cf10f92856dc..45b33e02dff5 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -135,7 +135,7 @@ * usbhsf_power_ctrl() */ #define IRQ7 evt2irq(0x02e0) -#define USBCR1 0xe605810a +#define USBCR1 IOMEM(0xe605810a) #define USBH 0xC6700000 #define USBH_USBCTR 0x10834 @@ -520,13 +520,14 @@ static struct platform_device hdmi_lcdc_device = { }; /* GPIO KEY */ -#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } +#define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW1"), - GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW2"), - GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW3"), - GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW4"), + GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), + GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), + GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), + GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), }; static struct gpio_keys_platform_data gpio_key_info = { @@ -901,8 +902,8 @@ static struct platform_device *eva_devices[] __initdata = { &camera_device, &ceu0_device, &fsi_device, - &fsi_hdmi_device, &fsi_wm8978_device, + &fsi_hdmi_device, }; static void __init eva_clock_init(void) @@ -949,8 +950,8 @@ clock_error: /* * board init */ -#define GPIO_PORT7CR 0xe6050007 -#define GPIO_PORT8CR 0xe6050008 +#define GPIO_PORT7CR IOMEM(0xe6050007) +#define GPIO_PORT8CR IOMEM(0xe6050008) static void __init eva_init(void) { struct platform_device *usb = NULL; diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index 4129008eae29..cb8c994e1430 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = { #define FPGA_ETH_IRQ (FPGA_IRQ0 + 15) static u16 bonito_fpga_read(u32 offset) { - return __raw_readw(0xf0003000 + offset); + return __raw_readw(IOMEM(0xf0003000) + offset); } static void bonito_fpga_write(u32 offset, u16 val) { - __raw_writew(val, 0xf0003000 + offset); + __raw_writew(val, IOMEM(0xf0003000) + offset); } static void bonito_fpga_irq_disable(struct irq_data *data) @@ -361,8 +361,8 @@ static void __init bonito_map_io(void) #define BIT_ON(sw, bit) (sw & (1 << bit)) #define BIT_OFF(sw, bit) (!(sw & (1 << bit))) -#define VCCQ1CR 0xE6058140 -#define VCCQ1LCDCR 0xE6058186 +#define VCCQ1CR IOMEM(0xE6058140) +#define VCCQ1LCDCR IOMEM(0xE6058186) static void __init bonito_init(void) { diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 796fa00ad3c4..b179d4c213bb 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power) return; /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ - __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); + __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008)); } static struct r8a66597_platdata usb_host_data = { @@ -279,10 +279,10 @@ static void __init g3evm_init(void) gpio_request(GPIO_FN_IDIN, NULL); /* setup USB phy */ - __raw_writew(0x0300, 0xe605810a); /* USBCR1 */ - __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ - __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ - __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + __raw_writew(0x0300, IOMEM(0xe605810a)); /* USBCR1 */ + __raw_writew(0x00e0, IOMEM(0xe60581c0)); /* CPFCH */ + __raw_writew(0x6010, IOMEM(0xe60581c6)); /* CGPOSR */ + __raw_writew(0x8a0a, IOMEM(0xe605810c)); /* USBCR2 */ /* KEYSC @ CN7 */ gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL); @@ -320,7 +320,7 @@ static void __init g3evm_init(void) gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL); gpio_request(GPIO_FN_FRB, NULL); /* FOE, FCDE, FSC on dedicated pins */ - __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048); + __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048)); /* IrDA */ gpio_request(GPIO_FN_IRDA_OUT, NULL); diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index fa5dfc5c8ed6..22d689322533 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -126,7 +126,7 @@ static void usb_host_port_power(int port, int power) return; /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */ - __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008); + __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008)); } static struct r8a66597_platdata usb_host_data = { @@ -270,17 +270,17 @@ static struct platform_device *g4evm_devices[] __initdata = { &sdhi1_device, }; -#define GPIO_SDHID0_D0 0xe60520fc -#define GPIO_SDHID0_D1 0xe60520fd -#define GPIO_SDHID0_D2 0xe60520fe -#define GPIO_SDHID0_D3 0xe60520ff -#define GPIO_SDHICMD0 0xe6052100 +#define GPIO_SDHID0_D0 IOMEM(0xe60520fc) +#define GPIO_SDHID0_D1 IOMEM(0xe60520fd) +#define GPIO_SDHID0_D2 IOMEM(0xe60520fe) +#define GPIO_SDHID0_D3 IOMEM(0xe60520ff) +#define GPIO_SDHICMD0 IOMEM(0xe6052100) -#define GPIO_SDHID1_D0 0xe6052103 -#define GPIO_SDHID1_D1 0xe6052104 -#define GPIO_SDHID1_D2 0xe6052105 -#define GPIO_SDHID1_D3 0xe6052106 -#define GPIO_SDHICMD1 0xe6052107 +#define GPIO_SDHID1_D0 IOMEM(0xe6052103) +#define GPIO_SDHID1_D1 IOMEM(0xe6052104) +#define GPIO_SDHID1_D2 IOMEM(0xe6052105) +#define GPIO_SDHID1_D3 IOMEM(0xe6052106) +#define GPIO_SDHICMD1 IOMEM(0xe6052107) static void __init g4evm_init(void) { @@ -318,10 +318,10 @@ static void __init g4evm_init(void) gpio_request(GPIO_FN_IDIN, NULL); /* setup USB phy */ - __raw_writew(0x0200, 0xe605810a); /* USBCR1 */ - __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ - __raw_writew(0x6010, 0xe60581c6); /* CGPOSR */ - __raw_writew(0x8a0a, 0xe605810c); /* USBCR2 */ + __raw_writew(0x0200, IOMEM(0xe605810a)); /* USBCR1 */ + __raw_writew(0x00e0, IOMEM(0xe60581c0)); /* CPFCH */ + __raw_writew(0x6010, IOMEM(0xe60581c6)); /* CGPOSR */ + __raw_writew(0x8a0a, IOMEM(0xe605810c)); /* USBCR2 */ /* KEYSC @ CN31 */ gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL); diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 53b7ea92c32c..1a413f07c8c4 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -133,8 +133,8 @@ static struct platform_device usb_host_device = { /* USB Func CN17 */ struct usbhs_private { - unsigned int phy; - unsigned int cr2; + void __iomem *phy; + void __iomem *cr2; struct renesas_usbhs_platform_info info; }; @@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = { }; static struct usbhs_private usbhs_private = { - .phy = 0xe60781e0, /* USBPHYINT */ - .cr2 = 0xe605810c, /* USBCR2 */ + .phy = IOMEM(0xe60781e0), /* USBPHYINT */ + .cr2 = IOMEM(0xe605810c), /* USBCR2 */ .info = { .platform_callback = { .hardware_init = usbhs_hardware_init, @@ -346,11 +346,11 @@ static struct resource sh_mmcif_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(141), + .start = gic_spi(140), .flags = IORESOURCE_IRQ, }, [2] = { - .start = gic_spi(140), + .start = gic_spi(141), .flags = IORESOURCE_IRQ, }, }; @@ -763,6 +763,13 @@ static void __init kzm_init(void) platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices)); } +static void kzm9g_restart(char mode, const char *cmd) +{ +#define RESCNT2 IOMEM(0xe6188020) + /* Do soft power on reset */ + writel((1 << 31), RESCNT2); +} + static const char *kzm9g_boards_compat_dt[] __initdata = { "renesas,kzm9g", NULL, @@ -777,5 +784,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g") .init_machine = kzm_init, .init_late = shmobile_init_late, .timer = &shmobile_timer, + .restart = kzm9g_restart, .dt_compat = kzm9g_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 7ea2b31e3199..0dce90ee6cf2 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -583,8 +583,8 @@ out: #define USBHS0_POLL_INTERVAL (HZ * 5) struct usbhs_private { - unsigned int usbphyaddr; - unsigned int usbcrcaddr; + void __iomem *usbphyaddr; + void __iomem *usbcrcaddr; struct renesas_usbhs_platform_info info; struct delayed_work work; struct platform_device *pdev; @@ -642,7 +642,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev) } static struct usbhs_private usbhs0_private = { - .usbcrcaddr = 0xe605810c, /* USBCR2 */ + .usbcrcaddr = IOMEM(0xe605810c), /* USBCR2 */ .info = { .platform_callback = { .hardware_init = usbhs0_hardware_init, @@ -695,6 +695,7 @@ static struct platform_device usbhs0_device = { * - J30 "open" * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET * - add .get_vbus = usbhs_get_vbus in usbhs1_private + * - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices. */ #define IRQ8 evt2irq(0x0300) #define USB_PHY_MODE (1 << 4) @@ -775,8 +776,8 @@ static u32 usbhs1_pipe_cfg[] = { }; static struct usbhs_private usbhs1_private = { - .usbphyaddr = 0xe60581e2, /* USBPHY1INTAP */ - .usbcrcaddr = 0xe6058130, /* USBCR4 */ + .usbphyaddr = IOMEM(0xe60581e2), /* USBPHY1INTAP */ + .usbcrcaddr = IOMEM(0xe6058130), /* USBCR4 */ .info = { .platform_callback = { .hardware_init = usbhs1_hardware_init, @@ -1325,8 +1326,8 @@ static struct platform_device *mackerel_devices[] __initdata = { &nor_flash_device, &smc911x_device, &lcdc_device, - &usbhs1_device, &usbhs0_device, + &usbhs1_device, &leds_device, &fsi_device, &fsi_ak4643_device, @@ -1401,12 +1402,12 @@ static struct i2c_board_info i2c1_devices[] = { }, }; -#define GPIO_PORT9CR 0xE6051009 -#define GPIO_PORT10CR 0xE605100A -#define GPIO_PORT167CR 0xE60520A7 -#define GPIO_PORT168CR 0xE60520A8 -#define SRCR4 0xe61580bc -#define USCCR1 0xE6058144 +#define GPIO_PORT9CR IOMEM(0xE6051009) +#define GPIO_PORT10CR IOMEM(0xE605100A) +#define GPIO_PORT167CR IOMEM(0xE60520A7) +#define GPIO_PORT168CR IOMEM(0xE60520A8) +#define SRCR4 IOMEM(0xe61580bc) +#define USCCR1 IOMEM(0xE6058144) static void __init mackerel_init(void) { u32 srcr4; diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 3a528cf4366c..fcf5a47f4772 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -67,7 +67,7 @@ static struct smsc911x_platform_config smsc911x_platdata = { static struct platform_device eth_device = { .name = "smsc911x", - .id = 0, + .id = -1, .dev = { .platform_data = &smsc911x_platdata, }, diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index ad5fccc7b5e7..6729e0032180 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -41,29 +41,29 @@ */ /* CPG registers */ -#define FRQCRA 0xe6150000 -#define FRQCRB 0xe6150004 -#define VCLKCR1 0xE6150008 -#define VCLKCR2 0xE615000c -#define FRQCRC 0xe61500e0 -#define FSIACKCR 0xe6150018 -#define PLLC01CR 0xe6150028 - -#define SUBCKCR 0xe6150080 -#define USBCKCR 0xe615008c - -#define MSTPSR0 0xe6150030 -#define MSTPSR1 0xe6150038 -#define MSTPSR2 0xe6150040 -#define MSTPSR3 0xe6150048 -#define MSTPSR4 0xe615004c -#define FSIBCKCR 0xe6150090 -#define HDMICKCR 0xe6150094 -#define SMSTPCR0 0xe6150130 -#define SMSTPCR1 0xe6150134 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xe615013c -#define SMSTPCR4 0xe6150140 +#define FRQCRA IOMEM(0xe6150000) +#define FRQCRB IOMEM(0xe6150004) +#define VCLKCR1 IOMEM(0xE6150008) +#define VCLKCR2 IOMEM(0xE615000c) +#define FRQCRC IOMEM(0xe61500e0) +#define FSIACKCR IOMEM(0xe6150018) +#define PLLC01CR IOMEM(0xe6150028) + +#define SUBCKCR IOMEM(0xe6150080) +#define USBCKCR IOMEM(0xe615008c) + +#define MSTPSR0 IOMEM(0xe6150030) +#define MSTPSR1 IOMEM(0xe6150038) +#define MSTPSR2 IOMEM(0xe6150040) +#define MSTPSR3 IOMEM(0xe6150048) +#define MSTPSR4 IOMEM(0xe615004c) +#define FSIBCKCR IOMEM(0xe6150090) +#define HDMICKCR IOMEM(0xe6150094) +#define SMSTPCR0 IOMEM(0xe6150130) +#define SMSTPCR1 IOMEM(0xe6150134) +#define SMSTPCR2 IOMEM(0xe6150138) +#define SMSTPCR3 IOMEM(0xe615013c) +#define SMSTPCR4 IOMEM(0xe6150140) /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk extalr_clk = { diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 339c62c824d5..3cafb6ab5e9a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = { 0x0300, CLK_ENABLE_ON_INIT), }; -enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, +enum { MSTP323, MSTP322, MSTP321, MSTP320, + MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP014, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ @@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ }; void __init r8a7779_clock_init(void) diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 162b791b8984..ef0a95e592c4 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -24,28 +24,28 @@ #include <mach/common.h> /* SH7367 registers */ -#define RTFRQCR 0xe6150000 -#define SYFRQCR 0xe6150004 -#define CMFRQCR 0xe61500E0 -#define VCLKCR1 0xe6150008 -#define VCLKCR2 0xe615000C -#define VCLKCR3 0xe615001C -#define SCLKACR 0xe6150010 -#define SCLKBCR 0xe6150014 -#define SUBUSBCKCR 0xe6158080 -#define SPUCKCR 0xe6150084 -#define MSUCKCR 0xe6150088 -#define MVI3CKCR 0xe6150090 -#define VOUCKCR 0xe6150094 -#define MFCK1CR 0xe6150098 -#define MFCK2CR 0xe615009C -#define PLLC1CR 0xe6150028 -#define PLLC2CR 0xe615002C -#define RTMSTPCR0 0xe6158030 -#define RTMSTPCR2 0xe6158038 -#define SYMSTPCR0 0xe6158040 -#define SYMSTPCR2 0xe6158048 -#define CMMSTPCR0 0xe615804c +#define RTFRQCR IOMEM(0xe6150000) +#define SYFRQCR IOMEM(0xe6150004) +#define CMFRQCR IOMEM(0xe61500E0) +#define VCLKCR1 IOMEM(0xe6150008) +#define VCLKCR2 IOMEM(0xe615000C) +#define VCLKCR3 IOMEM(0xe615001C) +#define SCLKACR IOMEM(0xe6150010) +#define SCLKBCR IOMEM(0xe6150014) +#define SUBUSBCKCR IOMEM(0xe6158080) +#define SPUCKCR IOMEM(0xe6150084) +#define MSUCKCR IOMEM(0xe6150088) +#define MVI3CKCR IOMEM(0xe6150090) +#define VOUCKCR IOMEM(0xe6150094) +#define MFCK1CR IOMEM(0xe6150098) +#define MFCK2CR IOMEM(0xe615009C) +#define PLLC1CR IOMEM(0xe6150028) +#define PLLC2CR IOMEM(0xe615002C) +#define RTMSTPCR0 IOMEM(0xe6158030) +#define RTMSTPCR2 IOMEM(0xe6158038) +#define SYMSTPCR0 IOMEM(0xe6158040) +#define SYMSTPCR2 IOMEM(0xe6158048) +#define CMMSTPCR0 IOMEM(0xe615804c) /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 5a2894b1c965..430a90ffa120 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -24,36 +24,36 @@ #include <mach/common.h> /* SH7372 registers */ -#define FRQCRA 0xe6150000 -#define FRQCRB 0xe6150004 -#define FRQCRC 0xe61500e0 -#define FRQCRD 0xe61500e4 -#define VCLKCR1 0xe6150008 -#define VCLKCR2 0xe615000c -#define VCLKCR3 0xe615001c -#define FMSICKCR 0xe6150010 -#define FMSOCKCR 0xe6150014 -#define FSIACKCR 0xe6150018 -#define FSIBCKCR 0xe6150090 -#define SUBCKCR 0xe6150080 -#define SPUCKCR 0xe6150084 -#define VOUCKCR 0xe6150088 -#define HDMICKCR 0xe6150094 -#define DSITCKCR 0xe6150060 -#define DSI0PCKCR 0xe6150064 -#define DSI1PCKCR 0xe6150098 -#define PLLC01CR 0xe6150028 -#define PLLC2CR 0xe615002c -#define RMSTPCR0 0xe6150110 -#define RMSTPCR1 0xe6150114 -#define RMSTPCR2 0xe6150118 -#define RMSTPCR3 0xe615011c -#define RMSTPCR4 0xe6150120 -#define SMSTPCR0 0xe6150130 -#define SMSTPCR1 0xe6150134 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xe615013c -#define SMSTPCR4 0xe6150140 +#define FRQCRA IOMEM(0xe6150000) +#define FRQCRB IOMEM(0xe6150004) +#define FRQCRC IOMEM(0xe61500e0) +#define FRQCRD IOMEM(0xe61500e4) +#define VCLKCR1 IOMEM(0xe6150008) +#define VCLKCR2 IOMEM(0xe615000c) +#define VCLKCR3 IOMEM(0xe615001c) +#define FMSICKCR IOMEM(0xe6150010) +#define FMSOCKCR IOMEM(0xe6150014) +#define FSIACKCR IOMEM(0xe6150018) +#define FSIBCKCR IOMEM(0xe6150090) +#define SUBCKCR IOMEM(0xe6150080) +#define SPUCKCR IOMEM(0xe6150084) +#define VOUCKCR IOMEM(0xe6150088) +#define HDMICKCR IOMEM(0xe6150094) +#define DSITCKCR IOMEM(0xe6150060) +#define DSI0PCKCR IOMEM(0xe6150064) +#define DSI1PCKCR IOMEM(0xe6150098) +#define PLLC01CR IOMEM(0xe6150028) +#define PLLC2CR IOMEM(0xe615002c) +#define RMSTPCR0 IOMEM(0xe6150110) +#define RMSTPCR1 IOMEM(0xe6150114) +#define RMSTPCR2 IOMEM(0xe6150118) +#define RMSTPCR3 IOMEM(0xe615011c) +#define RMSTPCR4 IOMEM(0xe6150120) +#define SMSTPCR0 IOMEM(0xe6150130) +#define SMSTPCR1 IOMEM(0xe6150134) +#define SMSTPCR2 IOMEM(0xe6150138) +#define SMSTPCR3 IOMEM(0xe615013c) +#define SMSTPCR4 IOMEM(0xe6150140) #define FSIDIVA 0xFE1F8000 #define FSIDIVB 0xFE1F8008 diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c index 85f2a3ec2c44..b8480d19e1c8 100644 --- a/arch/arm/mach-shmobile/clock-sh7377.c +++ b/arch/arm/mach-shmobile/clock-sh7377.c @@ -24,31 +24,31 @@ #include <mach/common.h> /* SH7377 registers */ -#define RTFRQCR 0xe6150000 -#define SYFRQCR 0xe6150004 -#define CMFRQCR 0xe61500E0 -#define VCLKCR1 0xe6150008 -#define VCLKCR2 0xe615000C -#define VCLKCR3 0xe615001C -#define FMSICKCR 0xe6150010 -#define FMSOCKCR 0xe6150014 -#define FSICKCR 0xe6150018 -#define PLLC1CR 0xe6150028 -#define PLLC2CR 0xe615002C -#define SUBUSBCKCR 0xe6150080 -#define SPUCKCR 0xe6150084 -#define MSUCKCR 0xe6150088 -#define MVI3CKCR 0xe6150090 -#define HDMICKCR 0xe6150094 -#define MFCK1CR 0xe6150098 -#define MFCK2CR 0xe615009C -#define DSITCKCR 0xe6150060 -#define DSIPCKCR 0xe6150064 -#define SMSTPCR0 0xe6150130 -#define SMSTPCR1 0xe6150134 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xe615013C -#define SMSTPCR4 0xe6150140 +#define RTFRQCR IOMEM(0xe6150000) +#define SYFRQCR IOMEM(0xe6150004) +#define CMFRQCR IOMEM(0xe61500E0) +#define VCLKCR1 IOMEM(0xe6150008) +#define VCLKCR2 IOMEM(0xe615000C) +#define VCLKCR3 IOMEM(0xe615001C) +#define FMSICKCR IOMEM(0xe6150010) +#define FMSOCKCR IOMEM(0xe6150014) +#define FSICKCR IOMEM(0xe6150018) +#define PLLC1CR IOMEM(0xe6150028) +#define PLLC2CR IOMEM(0xe615002C) +#define SUBUSBCKCR IOMEM(0xe6150080) +#define SPUCKCR IOMEM(0xe6150084) +#define MSUCKCR IOMEM(0xe6150088) +#define MVI3CKCR IOMEM(0xe6150090) +#define HDMICKCR IOMEM(0xe6150094) +#define MFCK1CR IOMEM(0xe6150098) +#define MFCK2CR IOMEM(0xe615009C) +#define DSITCKCR IOMEM(0xe6150060) +#define DSIPCKCR IOMEM(0xe6150064) +#define SMSTPCR0 IOMEM(0xe6150130) +#define SMSTPCR1 IOMEM(0xe6150134) +#define SMSTPCR2 IOMEM(0xe6150138) +#define SMSTPCR3 IOMEM(0xe615013C) +#define SMSTPCR4 IOMEM(0xe6150140) /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 7f8da18a8580..516ff7f3e434 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -23,43 +23,43 @@ #include <linux/clkdev.h> #include <mach/common.h> -#define FRQCRA 0xe6150000 -#define FRQCRB 0xe6150004 -#define FRQCRD 0xe61500e4 -#define VCLKCR1 0xe6150008 -#define VCLKCR2 0xe615000C -#define VCLKCR3 0xe615001C -#define ZBCKCR 0xe6150010 -#define FLCKCR 0xe6150014 -#define SD0CKCR 0xe6150074 -#define SD1CKCR 0xe6150078 -#define SD2CKCR 0xe615007C -#define FSIACKCR 0xe6150018 -#define FSIBCKCR 0xe6150090 -#define SUBCKCR 0xe6150080 -#define SPUACKCR 0xe6150084 -#define SPUVCKCR 0xe6150094 -#define MSUCKCR 0xe6150088 -#define HSICKCR 0xe615008C -#define MFCK1CR 0xe6150098 -#define MFCK2CR 0xe615009C -#define DSITCKCR 0xe6150060 -#define DSI0PCKCR 0xe6150064 -#define DSI1PCKCR 0xe6150068 +#define FRQCRA IOMEM(0xe6150000) +#define FRQCRB IOMEM(0xe6150004) +#define FRQCRD IOMEM(0xe61500e4) +#define VCLKCR1 IOMEM(0xe6150008) +#define VCLKCR2 IOMEM(0xe615000C) +#define VCLKCR3 IOMEM(0xe615001C) +#define ZBCKCR IOMEM(0xe6150010) +#define FLCKCR IOMEM(0xe6150014) +#define SD0CKCR IOMEM(0xe6150074) +#define SD1CKCR IOMEM(0xe6150078) +#define SD2CKCR IOMEM(0xe615007C) +#define FSIACKCR IOMEM(0xe6150018) +#define FSIBCKCR IOMEM(0xe6150090) +#define SUBCKCR IOMEM(0xe6150080) +#define SPUACKCR IOMEM(0xe6150084) +#define SPUVCKCR IOMEM(0xe6150094) +#define MSUCKCR IOMEM(0xe6150088) +#define HSICKCR IOMEM(0xe615008C) +#define MFCK1CR IOMEM(0xe6150098) +#define MFCK2CR IOMEM(0xe615009C) +#define DSITCKCR IOMEM(0xe6150060) +#define DSI0PCKCR IOMEM(0xe6150064) +#define DSI1PCKCR IOMEM(0xe6150068) #define DSI0PHYCR 0xe615006C #define DSI1PHYCR 0xe6150070 -#define PLLECR 0xe61500d0 -#define PLL0CR 0xe61500d8 -#define PLL1CR 0xe6150028 -#define PLL2CR 0xe615002c -#define PLL3CR 0xe61500dc -#define SMSTPCR0 0xe6150130 -#define SMSTPCR1 0xe6150134 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xe615013c -#define SMSTPCR4 0xe6150140 -#define SMSTPCR5 0xe6150144 -#define CKSCR 0xe61500c0 +#define PLLECR IOMEM(0xe61500d0) +#define PLL0CR IOMEM(0xe61500d8) +#define PLL1CR IOMEM(0xe6150028) +#define PLL2CR IOMEM(0xe615002c) +#define PLL3CR IOMEM(0xe61500dc) +#define SMSTPCR0 IOMEM(0xe6150130) +#define SMSTPCR1 IOMEM(0xe6150134) +#define SMSTPCR2 IOMEM(0xe6150138) +#define SMSTPCR3 IOMEM(0xe615013c) +#define SMSTPCR4 IOMEM(0xe6150140) +#define SMSTPCR5 IOMEM(0xe6150144) +#define CKSCR IOMEM(0xe61500c0) /* Fixed 32 KHz root clock from EXTALR pin */ static struct clk r_clk = { diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h index 844507d937cb..90a92b2c1c52 100644 --- a/arch/arm/mach-shmobile/include/mach/gpio.h +++ b/arch/arm/mach-shmobile/include/mach/gpio.h @@ -35,12 +35,12 @@ static inline int irq_to_gpio(unsigned int irq) * the method to control only pull up/down/free. * this function should be replaced by correct gpio function */ -static inline void __init gpio_direction_none(u32 addr) +static inline void __init gpio_direction_none(void __iomem * addr) { __raw_writeb(0x00, addr); } -static inline void __init gpio_request_pullup(u32 addr) +static inline void __init gpio_request_pullup(void __iomem * addr) { u8 data = __raw_readb(addr); @@ -49,7 +49,7 @@ static inline void __init gpio_request_pullup(u32 addr) __raw_writeb(data, addr); } -static inline void __init gpio_request_pulldown(u32 addr) +static inline void __init gpio_request_pulldown(void __iomem * addr) { u8 data = __raw_readb(addr); diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index f04fad4ec4fb..ef66f1a8aa2e 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -29,14 +29,14 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#define INT2SMSKCR0 0xfe7822a0 -#define INT2SMSKCR1 0xfe7822a4 -#define INT2SMSKCR2 0xfe7822a8 -#define INT2SMSKCR3 0xfe7822ac -#define INT2SMSKCR4 0xfe7822b0 +#define INT2SMSKCR0 IOMEM(0xfe7822a0) +#define INT2SMSKCR1 IOMEM(0xfe7822a4) +#define INT2SMSKCR2 IOMEM(0xfe7822a8) +#define INT2SMSKCR3 IOMEM(0xfe7822ac) +#define INT2SMSKCR4 IOMEM(0xfe7822b0) -#define INT2NTSR0 0xfe700060 -#define INT2NTSR1 0xfe700064 +#define INT2NTSR0 IOMEM(0xfe700060) +#define INT2NTSR1 IOMEM(0xfe700064) static int r8a7779_set_wake(struct irq_data *data, unsigned int on) { diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 2587a22842f2..a91caad7db7c 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -624,6 +624,9 @@ void sh7372_intcs_resume(void) __raw_writeb(ffd5[k], intcs_ffd5 + k); } +#define E694_BASE IOMEM(0xe6940000) +#define E695_BASE IOMEM(0xe6950000) + static unsigned short e694[0x200]; static unsigned short e695[0x200]; @@ -632,22 +635,22 @@ void sh7372_intca_suspend(void) int k; for (k = 0x00; k <= 0x38; k += 4) - e694[k] = __raw_readw(0xe6940000 + k); + e694[k] = __raw_readw(E694_BASE + k); for (k = 0x80; k <= 0xb4; k += 4) - e694[k] = __raw_readb(0xe6940000 + k); + e694[k] = __raw_readb(E694_BASE + k); for (k = 0x180; k <= 0x1b4; k += 4) - e694[k] = __raw_readb(0xe6940000 + k); + e694[k] = __raw_readb(E694_BASE + k); for (k = 0x00; k <= 0x50; k += 4) - e695[k] = __raw_readw(0xe6950000 + k); + e695[k] = __raw_readw(E695_BASE + k); for (k = 0x80; k <= 0xa8; k += 4) - e695[k] = __raw_readb(0xe6950000 + k); + e695[k] = __raw_readb(E695_BASE + k); for (k = 0x180; k <= 0x1a8; k += 4) - e695[k] = __raw_readb(0xe6950000 + k); + e695[k] = __raw_readb(E695_BASE + k); } void sh7372_intca_resume(void) @@ -655,20 +658,20 @@ void sh7372_intca_resume(void) int k; for (k = 0x00; k <= 0x38; k += 4) - __raw_writew(e694[k], 0xe6940000 + k); + __raw_writew(e694[k], E694_BASE + k); for (k = 0x80; k <= 0xb4; k += 4) - __raw_writeb(e694[k], 0xe6940000 + k); + __raw_writeb(e694[k], E694_BASE + k); for (k = 0x180; k <= 0x1b4; k += 4) - __raw_writeb(e694[k], 0xe6940000 + k); + __raw_writeb(e694[k], E694_BASE + k); for (k = 0x00; k <= 0x50; k += 4) - __raw_writew(e695[k], 0xe6950000 + k); + __raw_writew(e695[k], E695_BASE + k); for (k = 0x80; k <= 0xa8; k += 4) - __raw_writeb(e695[k], 0xe6950000 + k); + __raw_writeb(e695[k], E695_BASE + k); for (k = 0x180; k <= 0x1a8; k += 4) - __raw_writeb(e695[k], 0xe6950000 + k); + __raw_writeb(e695[k], E695_BASE + k); } diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index ee447404c857..f0c5e5190601 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -259,9 +259,9 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } -#define RELOC_BASE 0x1000 +#define RELOC_BASE 0x1200 -/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */ +/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */ #define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, @@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) static struct irqaction sh73a0_irq_pin_cascade[32]; -#define PINTER0 0xe69000a0 -#define PINTER1 0xe69000a4 -#define PINTRR0 0xe69000d0 -#define PINTRR1 0xe69000d4 +#define PINTER0_PHYS 0xe69000a0 +#define PINTER1_PHYS 0xe69000a4 +#define PINTER0_VIRT IOMEM(0xe69000a0) +#define PINTER1_VIRT IOMEM(0xe69000a4) +#define PINTRR0 IOMEM(0xe69000d0) +#define PINTRR1 IOMEM(0xe69000d4) #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) @@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32]; #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) -INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \ +INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); -INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \ +INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \ INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ @@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \ static struct irqaction sh73a0_pint0_cascade; static struct irqaction sh73a0_pint1_cascade; -static void pint_demux(unsigned long rr, unsigned long er, int base_irq) +static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq) { unsigned long value = ioread32(rr) & ioread32(er); int k; @@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq) static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) { - pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0)); + pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0)); return IRQ_HANDLED; } static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) { - pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0)); + pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0)); return IRQ_HANDLED; } diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index a8562540f1d6..32e177275e47 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -20,9 +20,9 @@ #include <mach/pm-rmobile.h> /* SYSC */ -#define SPDCR 0xe6180008 -#define SWUCR 0xe6180014 -#define PSTR 0xe6180080 +#define SPDCR IOMEM(0xe6180008) +#define SWUCR IOMEM(0xe6180014) +#define PSTR IOMEM(0xe6180080) #define PSTR_RETRIES 100 #define PSTR_DELAY_US 10 diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index 792037069226..162121842a2b 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c @@ -29,45 +29,46 @@ #include <mach/pm-rmobile.h> /* DBG */ -#define DBGREG1 0xe6100020 -#define DBGREG9 0xe6100040 +#define DBGREG1 IOMEM(0xe6100020) +#define DBGREG9 IOMEM(0xe6100040) /* CPGA */ -#define SYSTBCR 0xe6150024 -#define MSTPSR0 0xe6150030 -#define MSTPSR1 0xe6150038 -#define MSTPSR2 0xe6150040 -#define MSTPSR3 0xe6150048 -#define MSTPSR4 0xe615004c -#define PLLC01STPCR 0xe61500c8 +#define SYSTBCR IOMEM(0xe6150024) +#define MSTPSR0 IOMEM(0xe6150030) +#define MSTPSR1 IOMEM(0xe6150038) +#define MSTPSR2 IOMEM(0xe6150040) +#define MSTPSR3 IOMEM(0xe6150048) +#define MSTPSR4 IOMEM(0xe615004c) +#define PLLC01STPCR IOMEM(0xe61500c8) /* SYSC */ -#define SBAR 0xe6180020 -#define WUPRMSK 0xe6180028 -#define WUPSMSK 0xe618002c -#define WUPSMSK2 0xe6180048 -#define WUPSFAC 0xe6180098 -#define IRQCR 0xe618022c -#define IRQCR2 0xe6180238 -#define IRQCR3 0xe6180244 -#define IRQCR4 0xe6180248 -#define PDNSEL 0xe6180254 +#define SBAR IOMEM(0xe6180020) +#define WUPRMSK IOMEM(0xe6180028) +#define WUPSMSK IOMEM(0xe618002c) +#define WUPSMSK2 IOMEM(0xe6180048) +#define WUPSFAC IOMEM(0xe6180098) +#define IRQCR IOMEM(0xe618022c) +#define IRQCR2 IOMEM(0xe6180238) +#define IRQCR3 IOMEM(0xe6180244) +#define IRQCR4 IOMEM(0xe6180248) +#define PDNSEL IOMEM(0xe6180254) /* INTC */ -#define ICR1A 0xe6900000 -#define ICR2A 0xe6900004 -#define ICR3A 0xe6900008 -#define ICR4A 0xe690000c -#define INTMSK00A 0xe6900040 -#define INTMSK10A 0xe6900044 -#define INTMSK20A 0xe6900048 -#define INTMSK30A 0xe690004c +#define ICR1A IOMEM(0xe6900000) +#define ICR2A IOMEM(0xe6900004) +#define ICR3A IOMEM(0xe6900008) +#define ICR4A IOMEM(0xe690000c) +#define INTMSK00A IOMEM(0xe6900040) +#define INTMSK10A IOMEM(0xe6900044) +#define INTMSK20A IOMEM(0xe6900048) +#define INTMSK30A IOMEM(0xe690004c) /* MFIS */ +/* FIXME: pointing where? */ #define SMFRAM 0xe6a70000 /* AP-System Core */ -#define APARMBAREA 0xe6f10020 +#define APARMBAREA IOMEM(0xe6f10020) #ifdef CONFIG_PM diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index dae9aa68bb09..61446f30e397 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -356,6 +356,26 @@ static struct platform_device gio4_device = { }, }; +static struct resource pmu_resources[] = { + [0] = { + .start = 152, + .end = 152, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = 153, + .end = 153, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = -1, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + static struct platform_device *emev2_early_devices[] __initdata = { &uart0_device, &uart1_device, @@ -370,6 +390,7 @@ static struct platform_device *emev2_late_devices[] __initdata = { &gio2_device, &gio3_device, &gio4_device, + &pmu_device, }; void __init emev2_add_standard_devices(void) diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index 2e3074ab75b3..e647f5410879 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void) shmobile_earlytimer_init(); } -#define SYMSTPCR2 0xe6158048 +#define SYMSTPCR2 IOMEM(0xe6158048) #define SYMSTPCR2_CMT1 (1 << 29) void __init sh7367_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index 855b1506caf8..edcf98bb7012 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void) shmobile_earlytimer_init(); } -#define SMSTPCR3 0xe615013c +#define SMSTPCR3 IOMEM(0xe615013c) #define SMSTPCR3_CMT1 (1 << 29) void __init sh7377_add_early_devices(void) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index d230af656fc9..db99a4ade80c 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -734,6 +734,26 @@ static struct platform_device mpdma0_device = { }, }; +static struct resource pmu_resources[] = { + [0] = { + .start = gic_spi(55), + .end = gic_spi(55), + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = gic_spi(56), + .end = gic_spi(56), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pmu_device = { + .name = "arm-pmu", + .id = -1, + .num_resources = ARRAY_SIZE(pmu_resources), + .resource = pmu_resources, +}; + static struct platform_device *sh73a0_early_devices[] __initdata = { &scif0_device, &scif1_device, @@ -757,9 +777,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = { &i2c4_device, &dma0_device, &mpdma0_device, + &pmu_device, }; -#define SRCR2 0xe61580b0 +#define SRCR2 IOMEM(0xe61580b0) void __init sh73a0_add_standard_devices(void) { diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h index 65f27def239b..07d90acc92c8 100644 --- a/arch/arm/mach-spear13xx/include/mach/spear.h +++ b/arch/arm/mach-spear13xx/include/mach/spear.h @@ -17,26 +17,26 @@ #include <asm/memory.h> #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE UL(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) #define MCIF_SDHCI_BASE UL(0xB3000000) #define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE UL(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xFE800000) #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) #define PERIP_GRP1_BASE UL(0xE0000000) -#define VA_PERIP_GRP1_BASE UL(0xFD000000) +#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) #define UART_BASE UL(0xE0000000) -#define VA_UART_BASE UL(0xFD000000) +#define VA_UART_BASE IOMEM(0xFD000000) #define SSP_BASE UL(0xE0100000) #define MISC_BASE UL(0xE0700000) -#define VA_MISC_BASE IOMEM(UL(0xFD700000)) +#define VA_MISC_BASE IOMEM(0xFD700000) #define A9SM_AND_MPMC_BASE UL(0xEC000000) -#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000) +#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) /* A9SM peripheral offsets */ #define A9SM_PERIP_BASE UL(0xEC800000) -#define VA_A9SM_PERIP_BASE UL(0xFC800000) +#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) #define L2CC_BASE UL(0xED000000) diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index cf936b106e27..e10648801b2e 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void) */ struct map_desc spear13xx_io_desc[] __initdata = { { - .virtual = VA_PERIP_GRP2_BASE, + .virtual = (unsigned long)VA_PERIP_GRP2_BASE, .pfn = __phys_to_pfn(PERIP_GRP2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_PERIP_GRP1_BASE, + .virtual = (unsigned long)VA_PERIP_GRP1_BASE, .pfn = __phys_to_pfn(PERIP_GRP1_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_A9SM_AND_MPMC_BASE, + .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), .length = SZ_16M, .type = MT_DEVICE diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 9077aaa398d9..5f3c03b61f8e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -34,7 +34,6 @@ config ARCH_TEGRA_3x_SOC select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB select USB_ULPI_VIEWPORT if USB_SUPPORT - select USE_OF select ARM_ERRATA_743622 select ARM_ERRATA_751472 select ARM_ERRATA_754322 @@ -60,25 +59,6 @@ config TEGRA_AHB comment "Tegra board type" -config MACH_HARMONY - bool "Harmony board" - depends on ARCH_TEGRA_2x_SOC - help - Support for nVidia Harmony development platform - -config MACH_PAZ00 - bool "Paz00 board" - depends on ARCH_TEGRA_2x_SOC - help - Support for the Toshiba AC100/Dynabook AZ netbook - -config MACH_TRIMSLICE - bool "TrimSlice board" - depends on ARCH_TEGRA_2x_SOC - select TEGRA_PCI - help - Support for CompuLab TrimSlice platform - choice prompt "Default low-level debug console UART" default TEGRA_DEBUG_UART_NONE @@ -130,13 +110,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH endchoice -config TEGRA_SYSTEM_DMA - bool "Enable system DMA driver for NVIDIA Tegra SoCs" - default y - help - Adds system DMA functionality for NVIDIA Tegra SoCs, used by - several Tegra device drivers - config TEGRA_EMC_SCALING_ENABLE bool "Enable scaling the memory frequency" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f07f99452a98..9aa653b3eb32 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,6 +1,4 @@ -obj-y += board-pinmux.o obj-y += common.o -obj-y += devices.o obj-y += io.o obj-y += irq.o obj-y += clock.o @@ -15,26 +13,19 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += reset.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o -obj-$(CONFIG_USB_SUPPORT) += usb_phy.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o -obj-$(CONFIG_MACH_HARMONY) += board-harmony.o -obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o -obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o -obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o -obj-$(CONFIG_MACH_PAZ00) += board-paz00.o -obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o - -obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o -obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 7a1bb62ddcf0..54c16aade475 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -3,9 +3,13 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb -dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a02.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a04.dtb diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index dc0fe389be56..b5015d0f1912 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -28,7 +28,7 @@ #include "apbio.h" -#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) +#if defined(CONFIG_TEGRA20_APB_DMA) static DEFINE_MUTEX(tegra_apb_dma_lock); static u32 *tegra_apb_bb; static dma_addr_t tegra_apb_bb_phys; @@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait); static u32 tegra_apb_readl_direct(unsigned long offset); static void tegra_apb_writel_direct(u32 value, unsigned long offset); -#if defined(CONFIG_TEGRA_SYSTEM_DMA) -static struct tegra_dma_channel *tegra_apb_dma; - -bool tegra_apb_init(void) -{ - struct tegra_dma_channel *ch; - - mutex_lock(&tegra_apb_dma_lock); - - /* Check to see if we raced to setup */ - if (tegra_apb_dma) - goto out; - - ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT | - TEGRA_DMA_SHARED); - - if (!ch) - goto out_fail; - - tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), - &tegra_apb_bb_phys, GFP_KERNEL); - if (!tegra_apb_bb) { - pr_err("%s: can not allocate bounce buffer\n", __func__); - tegra_dma_free_channel(ch); - goto out_fail; - } - - tegra_apb_dma = ch; -out: - mutex_unlock(&tegra_apb_dma_lock); - return true; - -out_fail: - mutex_unlock(&tegra_apb_dma_lock); - return false; -} - -static void apb_dma_complete(struct tegra_dma_req *req) -{ - complete(&tegra_apb_wait); -} - -static u32 tegra_apb_readl_using_dma(unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) - return tegra_apb_readl_direct(offset); - - mutex_lock(&tegra_apb_dma_lock); - req.complete = apb_dma_complete; - req.to_memory = 1; - req.dest_addr = tegra_apb_bb_phys; - req.dest_bus_width = 32; - req.dest_wrap = 1; - req.source_addr = offset; - req.source_bus_width = 32; - req.source_wrap = 4; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb read dma timed out")) { - tegra_dma_dequeue_req(tegra_apb_dma, &req); - *(u32 *)tegra_apb_bb = 0; - } - - mutex_unlock(&tegra_apb_dma_lock); - return *((u32 *)tegra_apb_bb); -} - -static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) { - tegra_apb_writel_direct(value, offset); - return; - } - - mutex_lock(&tegra_apb_dma_lock); - *((u32 *)tegra_apb_bb) = value; - req.complete = apb_dma_complete; - req.to_memory = 0; - req.dest_addr = offset; - req.dest_wrap = 4; - req.dest_bus_width = 32; - req.source_addr = tegra_apb_bb_phys; - req.source_bus_width = 32; - req.source_wrap = 1; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb write dma timed out")) - tegra_dma_dequeue_req(tegra_apb_dma, &req); - - mutex_unlock(&tegra_apb_dma_lock); -} - -#else static struct dma_chan *tegra_apb_dma_chan; static struct dma_slave_config dma_sconfig; @@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) pr_err("error in writing offset 0x%08lx using dma\n", offset); mutex_unlock(&tegra_apb_dma_lock); } -#endif #else #define tegra_apb_readl_using_dma tegra_apb_readl_direct #define tegra_apb_writel_using_dma tegra_apb_writel_direct @@ -293,12 +177,12 @@ static apbio_write_fptr apbio_write; static u32 tegra_apb_readl_direct(unsigned long offset) { - return readl(IO_TO_VIRT(offset)); + return readl(IO_ADDRESS(offset)); } static void tegra_apb_writel_direct(u32 value, unsigned long offset) { - writel(value, IO_TO_VIRT(offset)); + writel(value, IO_ADDRESS(offset)); } void tegra_apb_io_init(void) diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index b4e7cc14713c..c3394443675e 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -28,9 +28,11 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/pda_power.h> +#include <linux/platform_data/tegra_usb.h> #include <linux/io.h> #include <linux/i2c.h> #include <linux/i2c-tegra.h> +#include <linux/usb/tegra_usb_phy.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> @@ -42,9 +44,31 @@ #include <mach/irqs.h> #include "board.h" -#include "board-harmony.h" #include "clock.h" -#include "devices.h" + +struct tegra_ehci_platform_data tegra_ehci1_pdata = { + .operating_mode = TEGRA_USB_OTG, + .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, +}; + +struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { + .reset_gpio = -1, + .clk = "cdev2", +}; + +struct tegra_ehci_platform_data tegra_ehci2_pdata = { + .phy_config = &tegra_ehci2_ulpi_phy_config, + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, +}; + +struct tegra_ehci_platform_data tegra_ehci3_pdata = { + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + .vbus_gpio = -1, +}; struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), @@ -96,54 +120,40 @@ static void __init tegra_dt_init(void) tegra20_auxdata_lookup, NULL); } -#ifdef CONFIG_MACH_TRIMSLICE static void __init trimslice_init(void) { +#ifdef CONFIG_TEGRA_PCI int ret; ret = tegra_pcie_init(true, true); if (ret) pr_err("tegra_pci_init() failed: %d\n", ret); -} #endif +} -#ifdef CONFIG_MACH_HARMONY static void __init harmony_init(void) { +#ifdef CONFIG_TEGRA_PCI int ret; - ret = harmony_regulator_init(); - if (ret) { - pr_err("harmony_regulator_init() failed: %d\n", ret); - return; - } - ret = harmony_pcie_init(); if (ret) pr_err("harmony_pcie_init() failed: %d\n", ret); -} #endif +} -#ifdef CONFIG_MACH_PAZ00 static void __init paz00_init(void) { tegra_paz00_wifikill_init(); } -#endif static struct { char *machine; void (*init)(void); } board_init_funcs[] = { -#ifdef CONFIG_MACH_TRIMSLICE { "compulab,trimslice", trimslice_init }, -#endif -#ifdef CONFIG_MACH_HARMONY { "nvidia,harmony", harmony_init }, -#endif -#ifdef CONFIG_MACH_PAZ00 { "compal,paz00", paz00_init }, -#endif }; static void __init tegra_dt_init_late(void) diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index e8c3fda9bec2..3cdc1bb8254c 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -18,35 +18,57 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <linux/err.h> +#include <linux/of_gpio.h> #include <linux/regulator/consumer.h> #include <asm/mach-types.h> #include "board.h" -#include "board-harmony.h" #ifdef CONFIG_TEGRA_PCI int __init harmony_pcie_init(void) { + struct device_node *np; + int en_vdd_1v05; struct regulator *regulator = NULL; int err; - err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05"); - if (err) + np = of_find_node_by_path("/regulators/regulator@3"); + if (!np) { + pr_err("%s: of_find_node_by_path failed\n", __func__); + return -ENODEV; + } + + en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0); + if (en_vdd_1v05 < 0) { + pr_err("%s: of_get_named_gpio failed: %d\n", __func__, + en_vdd_1v05); + return en_vdd_1v05; + } + + err = gpio_request(en_vdd_1v05, "EN_VDD_1V05"); + if (err) { + pr_err("%s: gpio_request failed: %d\n", __func__, err); return err; + } - gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1); + gpio_direction_output(en_vdd_1v05, 1); - regulator = regulator_get(NULL, "pex_clk"); - if (IS_ERR_OR_NULL(regulator)) + regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk"); + if (IS_ERR_OR_NULL(regulator)) { + pr_err("%s: regulator_get failed: %d\n", __func__, + (int)PTR_ERR(regulator)); goto err_reg; + } regulator_enable(regulator); err = tegra_pcie_init(true, true); - if (err) + if (err) { + pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err); goto err_pcie; + } return 0; @@ -54,20 +76,9 @@ err_pcie: regulator_disable(regulator); regulator_put(regulator); err_reg: - gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO); + gpio_free(en_vdd_1v05); return err; } -static int __init harmony_pcie_initcall(void) -{ - if (!machine_is_harmony()) - return 0; - - return harmony_pcie_init(); -} - -/* PCI should be initialized after I2C, mfd and regulators */ -subsys_initcall_sync(harmony_pcie_initcall); - #endif diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c deleted file mode 100644 index 83d420fbc58c..000000000000 --- a/arch/arm/mach-tegra/board-harmony-pinmux.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-tegra/board-harmony-pinmux.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> - -#include "board-harmony.h" -#include "board-pinmux.h" - -static struct pinctrl_map harmony_map[] = { - TEGRA_MAP_MUXCONF("ata", "ide", none, driven), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "nand", none, driven), - TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("ate", "gmi", none, driven), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven), - TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven), - TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), - TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate), - TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), - TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), - TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate), - TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven), - TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spia", "gmi", none, driven), - TEGRA_MAP_MUXCONF("spib", "gmi", none, driven), - TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate), - TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("uad", "irda", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), -}; - -static struct tegra_board_pinmux_conf conf = { - .maps = harmony_map, - .map_count = ARRAY_SIZE(harmony_map), -}; - -void harmony_pinmux_init(void) -{ - tegra_board_pinmux_init(&conf, NULL); -} diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c deleted file mode 100644 index b7344beec102..000000000000 --- a/arch/arm/mach-tegra/board-harmony-power.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) 2010 NVIDIA, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ -#include <linux/i2c.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/tps6586x.h> -#include <linux/of.h> -#include <linux/of_i2c.h> - -#include <asm/mach-types.h> - -#include <mach/irqs.h> - -#include "board-harmony.h" - -static struct regulator_consumer_supply tps658621_ldo0_supply[] = { - REGULATOR_SUPPLY("pex_clk", NULL), -}; - -static struct regulator_init_data ldo0_data = { - .supply_regulator = "vdd_sm2", - .constraints = { - .name = "vdd_ldo0", - .min_uV = 3300 * 1000, - .max_uV = 3300 * 1000, - .valid_modes_mask = (REGULATOR_MODE_NORMAL | - REGULATOR_MODE_STANDBY), - .valid_ops_mask = (REGULATOR_CHANGE_MODE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_VOLTAGE), - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply), - .consumer_supplies = tps658621_ldo0_supply, -}; - -#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\ - static struct regulator_init_data _id##_data = { \ - .supply_regulator = _supply, \ - .constraints = { \ - .name = _name, \ - .min_uV = (_minmv)*1000, \ - .max_uV = (_maxmv)*1000, \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _on, \ - }, \ - } - -HARMONY_REGULATOR_INIT(sm0, "vdd_sm0", "vdd_sys", 725, 1500, 1); -HARMONY_REGULATOR_INIT(sm1, "vdd_sm1", "vdd_sys", 725, 1500, 1); -HARMONY_REGULATOR_INIT(sm2, "vdd_sm2", "vdd_sys", 3000, 4550, 1); -HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1); -HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0); -HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1); -HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1); -HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL, 1250, 3300, 1); -HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0); -HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0); -HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0); -HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1); - -#define TPS_REG(_id, _data) \ - { \ - .id = TPS6586X_ID_##_id, \ - .name = "tps6586x-regulator", \ - .platform_data = _data, \ - } - -static struct tps6586x_subdev_info tps_devs[] = { - TPS_REG(SM_0, &sm0_data), - TPS_REG(SM_1, &sm1_data), - TPS_REG(SM_2, &sm2_data), - TPS_REG(LDO_0, &ldo0_data), - TPS_REG(LDO_1, &ldo1_data), - TPS_REG(LDO_2, &ldo2_data), - TPS_REG(LDO_3, &ldo3_data), - TPS_REG(LDO_4, &ldo4_data), - TPS_REG(LDO_5, &ldo5_data), - TPS_REG(LDO_6, &ldo6_data), - TPS_REG(LDO_7, &ldo7_data), - TPS_REG(LDO_8, &ldo8_data), - TPS_REG(LDO_9, &ldo9_data), -}; - -static struct tps6586x_platform_data tps_platform = { - .irq_base = TEGRA_NR_IRQS, - .num_subdevs = ARRAY_SIZE(tps_devs), - .subdevs = tps_devs, - .gpio_base = HARMONY_GPIO_TPS6586X(0), -}; - -static struct i2c_board_info __initdata harmony_regulators[] = { - { - I2C_BOARD_INFO("tps6586x", 0x34), - .irq = INT_EXTERNAL_PMU, - .platform_data = &tps_platform, - }, -}; - -int __init harmony_regulator_init(void) -{ - regulator_register_always_on(0, "vdd_sys", - NULL, 0, 5000000); - - if (machine_is_harmony()) { - i2c_register_board_info(3, harmony_regulators, 1); - } else { /* Harmony, booted using device tree */ - struct device_node *np; - struct i2c_adapter *adapter; - - np = of_find_node_by_path("/i2c@7000d000"); - if (np == NULL) { - pr_err("Could not find device_node for DVC I2C\n"); - return -ENODEV; - } - - adapter = of_find_i2c_adapter_by_node(np); - if (!adapter) { - pr_err("Could not find i2c_adapter for DVC I2C\n"); - return -ENODEV; - } - - i2c_new_device(adapter, harmony_regulators); - } - - return 0; -} diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c deleted file mode 100644 index e65e837f4013..000000000000 --- a/arch/arm/mach-tegra/board-harmony.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * arch/arm/mach-tegra/board-harmony.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2011 NVIDIA, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/of_serial.h> -#include <linux/clk.h> -#include <linux/dma-mapping.h> -#include <linux/pda_power.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/i2c.h> - -#include <sound/wm8903.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/hardware/gic.h> -#include <asm/setup.h> - -#include <mach/tegra_wm8903_pdata.h> -#include <mach/iomap.h> -#include <mach/irqs.h> -#include <mach/sdhci.h> - -#include "board.h" -#include "board-harmony.h" -#include "clock.h" -#include "devices.h" -#include "gpio-names.h" - -static struct plat_serial8250_port debug_uart_platform_data[] = { - { - .membase = IO_ADDRESS(TEGRA_UARTD_BASE), - .mapbase = TEGRA_UARTD_BASE, - .irq = INT_UARTD, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .type = PORT_TEGRA, - .handle_break = tegra_serial_handle_break, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 216000000, - }, { - .flags = 0 - } -}; - -static struct platform_device debug_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = debug_uart_platform_data, - }, -}; - -static struct tegra_wm8903_platform_data harmony_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, -}; - -static struct platform_device harmony_audio_device = { - .name = "tegra-snd-wm8903", - .id = 0, - .dev = { - .platform_data = &harmony_audio_pdata, - }, -}; - -static struct wm8903_platform_data harmony_wm8903_pdata = { - .irq_active_low = 0, - .micdet_cfg = 0, - .micdet_delay = 100, - .gpio_base = HARMONY_GPIO_WM8903(0), - .gpio_cfg = { - 0, - 0, - WM8903_GPIO_CONFIG_ZERO, - 0, - 0, - }, -}; - -static struct i2c_board_info __initdata wm8903_board_info = { - I2C_BOARD_INFO("wm8903", 0x1a), - .platform_data = &harmony_wm8903_pdata, -}; - -static void __init harmony_i2c_init(void) -{ - platform_device_register(&tegra_i2c_device1); - platform_device_register(&tegra_i2c_device2); - platform_device_register(&tegra_i2c_device3); - platform_device_register(&tegra_i2c_device4); - - wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ); - i2c_register_board_info(0, &wm8903_board_info, 1); -} - -static struct platform_device *harmony_devices[] __initdata = { - &debug_uart, - &tegra_sdhci_device1, - &tegra_sdhci_device2, - &tegra_sdhci_device4, - &tegra_ehci3_device, - &tegra_i2s_device1, - &tegra_das_device, - &harmony_audio_device, -}; - -static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline, - struct meminfo *mi) -{ - mi->nr_banks = 2; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = 448 * SZ_1M; - mi->bank[1].start = SZ_512M; - mi->bank[1].size = SZ_512M; -} - -static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = { - /* name parent rate enabled */ - { "uartd", "pll_p", 216000000, true }, - { "pll_a", "pll_p_out1", 56448000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "cdev1", NULL, 0, true }, - { "i2s1", "pll_a_out0", 11289600, false}, - { "usb3", "clk_m", 12000000, true }, - { NULL, NULL, 0, 0}, -}; - - -static struct tegra_sdhci_platform_data sdhci_pdata1 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, -}; - -static struct tegra_sdhci_platform_data sdhci_pdata2 = { - .cd_gpio = TEGRA_GPIO_SD2_CD, - .wp_gpio = TEGRA_GPIO_SD2_WP, - .power_gpio = TEGRA_GPIO_SD2_POWER, -}; - -static struct tegra_sdhci_platform_data sdhci_pdata4 = { - .cd_gpio = TEGRA_GPIO_SD4_CD, - .wp_gpio = TEGRA_GPIO_SD4_WP, - .power_gpio = TEGRA_GPIO_SD4_POWER, - .is_8bit = 1, -}; - -static void __init tegra_harmony_init(void) -{ - tegra_clk_init_from_table(harmony_clk_init_table); - - harmony_pinmux_init(); - - tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; - tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2; - tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; - - platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices)); - harmony_i2c_init(); - harmony_regulator_init(); -} - -MACHINE_START(HARMONY, "harmony") - .atag_offset = 0x100, - .fixup = tegra_harmony_fixup, - .map_io = tegra_map_common_io, - .init_early = tegra20_init_early, - .init_irq = tegra_init_irq, - .handle_irq = gic_handle_irq, - .timer = &tegra_timer, - .init_machine = tegra_harmony_init, - .init_late = tegra_init_late, - .restart = tegra_assert_system_reset, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h deleted file mode 100644 index 139d96c93843..000000000000 --- a/arch/arm/mach-tegra/board-harmony.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-tegra/board-harmony.h - * - * Copyright (C) 2010 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_BOARD_HARMONY_H -#define _MACH_TEGRA_BOARD_HARMONY_H - -#include <mach/gpio-tegra.h> - -#define HARMONY_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_)) -#define HARMONY_GPIO_WM8903(_x_) (HARMONY_GPIO_TPS6586X(4) + (_x_)) - -#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5 -#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1 -#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PT3 -#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2 -#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3 -#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6 -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3 -#define TEGRA_GPIO_SPKR_EN HARMONY_GPIO_WM8903(2) -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2 -#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PX0 -#define TEGRA_GPIO_EXT_MIC_EN TEGRA_GPIO_PX1 -#define TEGRA_GPIO_EN_VDD_1V05_GPIO HARMONY_GPIO_TPS6586X(2) - -void harmony_pinmux_init(void); -int harmony_regulator_init(void); - -#endif diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c deleted file mode 100644 index 6f1111b48e7c..000000000000 --- a/arch/arm/mach-tegra/board-paz00-pinmux.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-tegra/board-paz00-pinmux.c - * - * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> - -#include "board-paz00.h" -#include "board-pinmux.h" - -static struct pinctrl_map paz00_map[] = { - TEGRA_MAP_MUXCONF("ata", "gmi", none, driven), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "gmi", none, driven), - TEGRA_MAP_MUXCONF("atd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("ate", "gmi", none, driven), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate), - TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate), - TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven), - TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven), - TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven), - TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "owr", up, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven), - TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven), - TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate), - TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate), - TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spic", "gmi", up, driven), - TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate), - TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate), - TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven), - TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven), - TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), -}; - -static struct tegra_board_pinmux_conf conf = { - .maps = paz00_map, - .map_count = ARRAY_SIZE(paz00_map), -}; - -void paz00_pinmux_init(void) -{ - tegra_board_pinmux_init(&conf, NULL); -} diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 4b64af5cab27..59305516fadb 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -17,72 +17,10 @@ * */ -#include <linux/kernel.h> -#include <linux/init.h> #include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/of_serial.h> -#include <linux/clk.h> -#include <linux/dma-mapping.h> -#include <linux/gpio_keys.h> -#include <linux/pda_power.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/gpio.h> #include <linux/rfkill-gpio.h> -#include <asm/hardware/gic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/setup.h> - -#include <mach/iomap.h> -#include <mach/irqs.h> -#include <mach/sdhci.h> - -#include "board.h" #include "board-paz00.h" -#include "clock.h" -#include "devices.h" -#include "gpio-names.h" - -static struct plat_serial8250_port debug_uart_platform_data[] = { - { - /* serial port on JP1 */ - .membase = IO_ADDRESS(TEGRA_UARTA_BASE), - .mapbase = TEGRA_UARTA_BASE, - .irq = INT_UARTA, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .type = PORT_TEGRA, - .handle_break = tegra_serial_handle_break, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 216000000, - }, { - /* serial port on mini-pcie */ - .membase = IO_ADDRESS(TEGRA_UARTC_BASE), - .mapbase = TEGRA_UARTC_BASE, - .irq = INT_UARTC, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .type = PORT_TEGRA, - .handle_break = tegra_serial_handle_break, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 216000000, - }, { - .flags = 0 - } -}; - -static struct platform_device debug_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = debug_uart_platform_data, - }, -}; static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { .name = "wifi_rfkill", @@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = { }, }; -static struct gpio_led gpio_leds[] = { - { - .name = "wifi-led", - .default_trigger = "rfkill0", - .gpio = TEGRA_WIFI_LED, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - -static struct gpio_keys_button paz00_gpio_keys_buttons[] = { - { - .code = KEY_POWER, - .gpio = TEGRA_GPIO_POWERKEY, - .active_low = 1, - .desc = "Power", - .type = EV_KEY, - .wakeup = 1, - }, -}; - -static struct gpio_keys_platform_data paz00_gpio_keys = { - .buttons = paz00_gpio_keys_buttons, - .nbuttons = ARRAY_SIZE(paz00_gpio_keys_buttons), -}; - -static struct platform_device gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &paz00_gpio_keys, - }, -}; - -static struct platform_device *paz00_devices[] __initdata = { - &debug_uart, - &tegra_sdhci_device4, - &tegra_sdhci_device1, - &leds_gpio, - &gpio_keys_device, -}; - -static void paz00_i2c_init(void) -{ - platform_device_register(&tegra_i2c_device1); - platform_device_register(&tegra_i2c_device2); - platform_device_register(&tegra_i2c_device4); -} - -static void paz00_usb_init(void) -{ - tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST; - - platform_device_register(&tegra_ehci2_device); - platform_device_register(&tegra_ehci3_device); -} - -static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, - struct meminfo *mi) -{ - mi->nr_banks = 1; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = 448 * SZ_1M; -} - -static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 216000000, true }, - { "uartc", "pll_p", 216000000, true }, - - { "usbd", "clk_m", 12000000, false }, - { "usb2", "clk_m", 12000000, false }, - { "usb3", "clk_m", 12000000, false }, - - { NULL, NULL, 0, 0}, -}; - -static struct tegra_sdhci_platform_data sdhci_pdata1 = { - .cd_gpio = TEGRA_GPIO_SD1_CD, - .wp_gpio = TEGRA_GPIO_SD1_WP, - .power_gpio = TEGRA_GPIO_SD1_POWER, -}; - -static struct tegra_sdhci_platform_data sdhci_pdata4 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, -}; - void __init tegra_paz00_wifikill_init(void) { platform_device_register(&wifi_rfkill_device); } - -static void __init tegra_paz00_init(void) -{ - tegra_clk_init_from_table(paz00_clk_init_table); - - paz00_pinmux_init(); - - tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; - tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; - - platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices)); - tegra_paz00_wifikill_init(); - - paz00_i2c_init(); - paz00_usb_init(); -} - -MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") - .atag_offset = 0x100, - .fixup = tegra_paz00_fixup, - .map_io = tegra_map_common_io, - .init_early = tegra20_init_early, - .init_irq = tegra_init_irq, - .handle_irq = gic_handle_irq, - .timer = &tegra_timer, - .init_machine = tegra_paz00_init, - .init_late = tegra_init_late, - .restart = tegra_assert_system_reset, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h index 3c9f8da37ea3..25c08ecef52f 100644 --- a/arch/arm/mach-tegra/board-paz00.h +++ b/arch/arm/mach-tegra/board-paz00.h @@ -17,24 +17,9 @@ #ifndef _MACH_TEGRA_BOARD_PAZ00_H #define _MACH_TEGRA_BOARD_PAZ00_H -#include <mach/gpio-tegra.h> +#include "gpio-names.h" -/* SDCARD */ -#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 -#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 -#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1 - -/* ULPI */ -#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 - -/* WIFI */ #define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5 #define TEGRA_WIFI_RST TEGRA_GPIO_PD1 -#define TEGRA_WIFI_LED TEGRA_GPIO_PD0 - -/* WakeUp */ -#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PJ7 - -void paz00_pinmux_init(void); #endif diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c deleted file mode 100644 index a5574c71b931..000000000000 --- a/arch/arm/mach-tegra/board-pinmux.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/notifier.h> -#include <linux/string.h> - -#include "board-pinmux.h" -#include "devices.h" - -unsigned long tegra_pincfg_pullnone_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; - -unsigned long tegra_pincfg_pullnone_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; - -unsigned long tegra_pincfg_pullnone_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE), -}; - -unsigned long tegra_pincfg_pullup_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; - -unsigned long tegra_pincfg_pullup_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; - -unsigned long tegra_pincfg_pullup_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP), -}; - -unsigned long tegra_pincfg_pulldown_driven[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; - -unsigned long tegra_pincfg_pulldown_tristate[2] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; - -unsigned long tegra_pincfg_pulldown_na[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN), -}; - -unsigned long tegra_pincfg_pullna_driven[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN), -}; - -unsigned long tegra_pincfg_pullna_tristate[1] = { - TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE), -}; - -static struct platform_device *devices[] = { - &tegra_gpio_device, - &tegra_pinmux_device, -}; - -void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, - struct tegra_board_pinmux_conf *conf_b) -{ - if (conf_a) - pinctrl_register_mappings(conf_a->maps, conf_a->map_count); - if (conf_b) - pinctrl_register_mappings(conf_b->maps, conf_b->map_count); - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h deleted file mode 100644 index c5f3f3381e86..000000000000 --- a/arch/arm/mach-tegra/board-pinmux.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_BOARD_PINMUX_H -#define __MACH_TEGRA_BOARD_PINMUX_H - -#include <linux/pinctrl/machine.h> - -#include <mach/pinconf-tegra.h> - -#define PINMUX_DEV "tegra20-pinctrl" - -#define TEGRA_MAP_MUX(_group_, _function_) \ - PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_) - -#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \ - PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_) - -#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \ - TEGRA_MAP_MUX(_group_, _function_), \ - TEGRA_MAP_CONF(_group_, _pull_, _drive_) - -extern unsigned long tegra_pincfg_pullnone_driven[2]; -extern unsigned long tegra_pincfg_pullnone_tristate[2]; -extern unsigned long tegra_pincfg_pullnone_na[1]; -extern unsigned long tegra_pincfg_pullup_driven[2]; -extern unsigned long tegra_pincfg_pullup_tristate[2]; -extern unsigned long tegra_pincfg_pullup_na[1]; -extern unsigned long tegra_pincfg_pulldown_driven[2]; -extern unsigned long tegra_pincfg_pulldown_tristate[2]; -extern unsigned long tegra_pincfg_pulldown_na[1]; -extern unsigned long tegra_pincfg_pullna_driven[1]; -extern unsigned long tegra_pincfg_pullna_tristate[1]; - -struct tegra_board_pinmux_conf { - struct pinctrl_map *maps; - int map_count; -}; - -void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, - struct tegra_board_pinmux_conf *conf_b); - -#endif diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c deleted file mode 100644 index 7b39511c0d4d..000000000000 --- a/arch/arm/mach-tegra/board-trimslice-pinmux.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * arch/arm/mach-tegra/board-trimslice-pinmux.c - * - * Copyright (C) 2011 CompuLab, Ltd. - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <linux/kernel.h> - -#include "board-trimslice.h" -#include "board-pinmux.h" - -static struct pinctrl_map trimslice_map[] = { - TEGRA_MAP_MUXCONF("ata", "ide", none, tristate), - TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("atc", "nand", none, tristate), - TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven), - TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate), - TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate), - TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate), - TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven), - TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate), - TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate), - TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate), - TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven), - TEGRA_MAP_MUXCONF("dta", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dte", "vi", none, tristate), - TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven), - TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven), - TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate), - TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven), - TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven), - TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven), - TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven), - TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven), - TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate), - TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate), - TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate), - TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate), - TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate), - TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven), - TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate), - TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven), - TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven), - TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate), - TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate), - TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate), - TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven), - TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven), - TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven), - TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven), - TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven), - TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate), - TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate), - TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven), - TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate), - TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate), - TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate), - TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate), - TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate), - TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate), - TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate), - TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate), - TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven), - TEGRA_MAP_MUXCONF("uad", "irda", up, tristate), - TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate), - TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate), - TEGRA_MAP_CONF("ck32", none, na), - TEGRA_MAP_CONF("ddrc", none, na), - TEGRA_MAP_CONF("pmca", none, na), - TEGRA_MAP_CONF("pmcb", none, na), - TEGRA_MAP_CONF("pmcc", none, na), - TEGRA_MAP_CONF("pmcd", none, na), - TEGRA_MAP_CONF("pmce", none, na), - TEGRA_MAP_CONF("xm2c", none, na), - TEGRA_MAP_CONF("xm2d", none, na), - TEGRA_MAP_CONF("ls", up, na), - TEGRA_MAP_CONF("lc", up, na), - TEGRA_MAP_CONF("ld17_0", down, na), - TEGRA_MAP_CONF("ld19_18", down, na), - TEGRA_MAP_CONF("ld21_20", down, na), - TEGRA_MAP_CONF("ld23_22", down, na), -}; - -static struct tegra_board_pinmux_conf conf = { - .maps = trimslice_map, - .map_count = ARRAY_SIZE(trimslice_map), -}; - -void trimslice_pinmux_init(void) -{ - tegra_board_pinmux_init(&conf, NULL); -} diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c deleted file mode 100644 index 776aa9564d5d..000000000000 --- a/arch/arm/mach-tegra/board-trimslice.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * arch/arm/mach-tegra/board-trimslice.c - * - * Copyright (C) 2011 CompuLab, Ltd. - * Author: Mike Rapoport <mike@compulab.co.il> - * - * Based on board-harmony.c - * Copyright (C) 2010 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/of_serial.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/platform_data/tegra_usb.h> - -#include <asm/hardware/gic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/setup.h> - -#include <mach/iomap.h> -#include <mach/sdhci.h> - -#include "board.h" -#include "clock.h" -#include "devices.h" -#include "gpio-names.h" - -#include "board-trimslice.h" - -static struct plat_serial8250_port debug_uart_platform_data[] = { - { - .membase = IO_ADDRESS(TEGRA_UARTA_BASE), - .mapbase = TEGRA_UARTA_BASE, - .irq = INT_UARTA, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .type = PORT_TEGRA, - .handle_break = tegra_serial_handle_break, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 216000000, - }, { - .flags = 0 - } -}; - -static struct platform_device debug_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = debug_uart_platform_data, - }, -}; -static struct tegra_sdhci_platform_data sdhci_pdata1 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, -}; - -static struct tegra_sdhci_platform_data sdhci_pdata4 = { - .cd_gpio = TRIMSLICE_GPIO_SD4_CD, - .wp_gpio = TRIMSLICE_GPIO_SD4_WP, - .power_gpio = -1, -}; - -static struct platform_device trimslice_audio_device = { - .name = "tegra-snd-trimslice", - .id = 0, -}; - -static struct platform_device *trimslice_devices[] __initdata = { - &debug_uart, - &tegra_sdhci_device1, - &tegra_sdhci_device4, - &tegra_i2s_device1, - &tegra_das_device, - &trimslice_audio_device, -}; - -static struct i2c_board_info trimslice_i2c3_board_info[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, - { - I2C_BOARD_INFO("em3027", 0x56), - }, -}; - -static void trimslice_i2c_init(void) -{ - platform_device_register(&tegra_i2c_device1); - platform_device_register(&tegra_i2c_device2); - platform_device_register(&tegra_i2c_device3); - - i2c_register_board_info(2, trimslice_i2c3_board_info, - ARRAY_SIZE(trimslice_i2c3_board_info)); -} - -static void trimslice_usb_init(void) -{ - struct tegra_ehci_platform_data *pdata; - - pdata = tegra_ehci1_device.dev.platform_data; - pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE; - - tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0; - - platform_device_register(&tegra_ehci3_device); - platform_device_register(&tegra_ehci2_device); - platform_device_register(&tegra_ehci1_device); -} - -static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline, - struct meminfo *mi) -{ - mi->nr_banks = 2; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = 448 * SZ_1M; - mi->bank[1].start = SZ_512M; - mi->bank[1].size = SZ_512M; -} - -static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 216000000, true }, - { "pll_a", "pll_p_out1", 56448000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "cdev1", NULL, 0, true }, - { "i2s1", "pll_a_out0", 11289600, false}, - { NULL, NULL, 0, 0}, -}; - -static int __init tegra_trimslice_pci_init(void) -{ - if (!machine_is_trimslice()) - return 0; - - return tegra_pcie_init(true, true); -} -subsys_initcall(tegra_trimslice_pci_init); - -static void __init tegra_trimslice_init(void) -{ - tegra_clk_init_from_table(trimslice_clk_init_table); - - trimslice_pinmux_init(); - - tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; - tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; - - platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); - - trimslice_i2c_init(); - trimslice_usb_init(); -} - -MACHINE_START(TRIMSLICE, "trimslice") - .atag_offset = 0x100, - .fixup = tegra_trimslice_fixup, - .map_io = tegra_map_common_io, - .init_early = tegra20_init_early, - .init_irq = tegra_init_irq, - .handle_irq = gic_handle_irq, - .timer = &tegra_timer, - .init_machine = tegra_trimslice_init, - .init_late = tegra_init_late, - .restart = tegra_assert_system_reset, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h deleted file mode 100644 index 50f128d87779..000000000000 --- a/arch/arm/mach-tegra/board-trimslice.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * arch/arm/mach-tegra/board-trimslice.h - * - * Copyright (C) 2011 CompuLab, Ltd. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H -#define _MACH_TEGRA_BOARD_TRIMSLICE_H - -#include <mach/gpio-tegra.h> - -#define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */ -#define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */ - -#define TRIMSLICE_GPIO_USB1_MODE TEGRA_GPIO_PV2 /* USB1 mode */ -#define TRIMSLICE_GPIO_USB2_RST TEGRA_GPIO_PV0 /* USB2 PHY reset */ - -void trimslice_pinmux_init(void); - -#endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 632133fc985b..fd82085eca5d 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -31,6 +31,10 @@ #include "board.h" #include "clock.h" +#include "tegra_cpu_car.h" + +/* Global data of Tegra CPU CAR ops */ +struct tegra_cpu_car_ops *tegra_cpu_car_ops; /* * Locking: diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f3654f830991..0560538bf598 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -34,6 +34,7 @@ #include "fuse.h" #include "pmc.h" #include "apbio.h" +#include "sleep.h" /* * Storage for debug-macro.S's state. @@ -135,6 +136,7 @@ void __init tegra20_init_early(void) tegra_init_cache(0x331, 0x441); tegra_pmc_init(); tegra_powergate_init(); + tegra20_hotplug_init(); } #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC @@ -147,6 +149,7 @@ void __init tegra30_init_early(void) tegra_init_cache(0x441, 0x551); tegra_pmc_init(); tegra_powergate_init(); + tegra30_hotplug_init(); } #endif diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c deleted file mode 100644 index c70e65ffa36b..000000000000 --- a/arch/arm/mach-tegra/devices.c +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Copyright (C) 2010,2011 Google, Inc. - * - * Author: - * Colin Cross <ccross@android.com> - * Erik Gilling <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/fsl_devices.h> -#include <linux/serial_8250.h> -#include <linux/i2c-tegra.h> -#include <asm/pmu.h> -#include <mach/irqs.h> -#include <mach/iomap.h> -#include <mach/dma.h> -#include <mach/usb_phy.h> - -#include "gpio-names.h" -#include "devices.h" - -static struct resource gpio_resource[] = { - [0] = { - .start = TEGRA_GPIO_BASE, - .end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_GPIO1, - .end = INT_GPIO1, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = INT_GPIO2, - .end = INT_GPIO2, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = INT_GPIO3, - .end = INT_GPIO3, - .flags = IORESOURCE_IRQ, - }, - [4] = { - .start = INT_GPIO4, - .end = INT_GPIO4, - .flags = IORESOURCE_IRQ, - }, - [5] = { - .start = INT_GPIO5, - .end = INT_GPIO5, - .flags = IORESOURCE_IRQ, - }, - [6] = { - .start = INT_GPIO6, - .end = INT_GPIO6, - .flags = IORESOURCE_IRQ, - }, - [7] = { - .start = INT_GPIO7, - .end = INT_GPIO7, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device tegra_gpio_device = { - .name = "tegra-gpio", - .id = -1, - .resource = gpio_resource, - .num_resources = ARRAY_SIZE(gpio_resource), -}; - -static struct resource pinmux_resource[] = { - [0] = { - /* Tri-state registers */ - .start = TEGRA_APB_MISC_BASE + 0x14, - .end = TEGRA_APB_MISC_BASE + 0x20 + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* Mux registers */ - .start = TEGRA_APB_MISC_BASE + 0x80, - .end = TEGRA_APB_MISC_BASE + 0x9c + 3, - .flags = IORESOURCE_MEM, - }, - [2] = { - /* Pull-up/down registers */ - .start = TEGRA_APB_MISC_BASE + 0xa0, - .end = TEGRA_APB_MISC_BASE + 0xb0 + 3, - .flags = IORESOURCE_MEM, - }, - [3] = { - /* Pad control registers */ - .start = TEGRA_APB_MISC_BASE + 0x868, - .end = TEGRA_APB_MISC_BASE + 0x90c + 3, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device tegra_pinmux_device = { - .name = "tegra20-pinctrl", - .id = -1, - .resource = pinmux_resource, - .num_resources = ARRAY_SIZE(pinmux_resource), -}; - -static struct resource i2c_resource1[] = { - [0] = { - .start = INT_I2C, - .end = INT_I2C, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_I2C_BASE, - .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource i2c_resource2[] = { - [0] = { - .start = INT_I2C2, - .end = INT_I2C2, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_I2C2_BASE, - .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource i2c_resource3[] = { - [0] = { - .start = INT_I2C3, - .end = INT_I2C3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_I2C3_BASE, - .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource i2c_resource4[] = { - [0] = { - .start = INT_DVC, - .end = INT_DVC, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_DVC_BASE, - .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct tegra_i2c_platform_data tegra_i2c1_platform_data = { - .bus_clk_rate = 400000, -}; - -static struct tegra_i2c_platform_data tegra_i2c2_platform_data = { - .bus_clk_rate = 400000, -}; - -static struct tegra_i2c_platform_data tegra_i2c3_platform_data = { - .bus_clk_rate = 400000, -}; - -static struct tegra_i2c_platform_data tegra_dvc_platform_data = { - .bus_clk_rate = 400000, -}; - -struct platform_device tegra_i2c_device1 = { - .name = "tegra-i2c", - .id = 0, - .resource = i2c_resource1, - .num_resources = ARRAY_SIZE(i2c_resource1), - .dev = { - .platform_data = &tegra_i2c1_platform_data, - }, -}; - -struct platform_device tegra_i2c_device2 = { - .name = "tegra-i2c", - .id = 1, - .resource = i2c_resource2, - .num_resources = ARRAY_SIZE(i2c_resource2), - .dev = { - .platform_data = &tegra_i2c2_platform_data, - }, -}; - -struct platform_device tegra_i2c_device3 = { - .name = "tegra-i2c", - .id = 2, - .resource = i2c_resource3, - .num_resources = ARRAY_SIZE(i2c_resource3), - .dev = { - .platform_data = &tegra_i2c3_platform_data, - }, -}; - -struct platform_device tegra_i2c_device4 = { - .name = "tegra-i2c", - .id = 3, - .resource = i2c_resource4, - .num_resources = ARRAY_SIZE(i2c_resource4), - .dev = { - .platform_data = &tegra_dvc_platform_data, - }, -}; - -static struct resource spi_resource1[] = { - [0] = { - .start = INT_S_LINK1, - .end = INT_S_LINK1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SPI1_BASE, - .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource spi_resource2[] = { - [0] = { - .start = INT_SPI_2, - .end = INT_SPI_2, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SPI2_BASE, - .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource spi_resource3[] = { - [0] = { - .start = INT_SPI_3, - .end = INT_SPI_3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SPI3_BASE, - .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource spi_resource4[] = { - [0] = { - .start = INT_SPI_4, - .end = INT_SPI_4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SPI4_BASE, - .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device tegra_spi_device1 = { - .name = "spi_tegra", - .id = 0, - .resource = spi_resource1, - .num_resources = ARRAY_SIZE(spi_resource1), - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - -struct platform_device tegra_spi_device2 = { - .name = "spi_tegra", - .id = 1, - .resource = spi_resource2, - .num_resources = ARRAY_SIZE(spi_resource2), - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - -struct platform_device tegra_spi_device3 = { - .name = "spi_tegra", - .id = 2, - .resource = spi_resource3, - .num_resources = ARRAY_SIZE(spi_resource3), - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - -struct platform_device tegra_spi_device4 = { - .name = "spi_tegra", - .id = 3, - .resource = spi_resource4, - .num_resources = ARRAY_SIZE(spi_resource4), - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - - -static struct resource sdhci_resource1[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC2, - .end = INT_SDMMC2, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC2_BASE, - .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource4[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -/* board files should fill in platform_data register the devices themselvs. - * See board-harmony.c for an example - */ -struct platform_device tegra_sdhci_device1 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource1, - .num_resources = ARRAY_SIZE(sdhci_resource1), -}; - -struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 1, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), -}; - -struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), -}; - -struct platform_device tegra_sdhci_device4 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource4, - .num_resources = ARRAY_SIZE(sdhci_resource4), -}; - -static struct resource tegra_usb1_resources[] = { - [0] = { - .start = TEGRA_USB_BASE, - .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_USB, - .end = INT_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_usb2_resources[] = { - [0] = { - .start = TEGRA_USB2_BASE, - .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_USB2, - .end = INT_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_usb3_resources[] = { - [0] = { - .start = TEGRA_USB3_BASE, - .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_USB3, - .end = INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { - .reset_gpio = -1, - .clk = "cdev2", -}; - -struct tegra_ehci_platform_data tegra_ehci1_pdata = { - .operating_mode = TEGRA_USB_OTG, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -struct tegra_ehci_platform_data tegra_ehci2_pdata = { - .phy_config = &tegra_ehci2_ulpi_phy_config, - .operating_mode = TEGRA_USB_HOST, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -struct tegra_ehci_platform_data tegra_ehci3_pdata = { - .operating_mode = TEGRA_USB_HOST, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); - -struct platform_device tegra_ehci1_device = { - .name = "tegra-ehci", - .id = 0, - .dev = { - .dma_mask = &tegra_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &tegra_ehci1_pdata, - }, - .resource = tegra_usb1_resources, - .num_resources = ARRAY_SIZE(tegra_usb1_resources), -}; - -struct platform_device tegra_ehci2_device = { - .name = "tegra-ehci", - .id = 1, - .dev = { - .dma_mask = &tegra_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &tegra_ehci2_pdata, - }, - .resource = tegra_usb2_resources, - .num_resources = ARRAY_SIZE(tegra_usb2_resources), -}; - -struct platform_device tegra_ehci3_device = { - .name = "tegra-ehci", - .id = 2, - .dev = { - .dma_mask = &tegra_ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &tegra_ehci3_pdata, - }, - .resource = tegra_usb3_resources, - .num_resources = ARRAY_SIZE(tegra_usb3_resources), -}; - -static struct resource tegra_pmu_resources[] = { - [0] = { - .start = INT_CPU0_PMU_INTR, - .end = INT_CPU0_PMU_INTR, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = INT_CPU1_PMU_INTR, - .end = INT_CPU1_PMU_INTR, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device tegra_pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = ARRAY_SIZE(tegra_pmu_resources), - .resource = tegra_pmu_resources, -}; - -static struct resource tegra_uarta_resources[] = { - [0] = { - .start = TEGRA_UARTA_BASE, - .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_UARTA, - .end = INT_UARTA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_uartb_resources[] = { - [0] = { - .start = TEGRA_UARTB_BASE, - .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_UARTB, - .end = INT_UARTB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_uartc_resources[] = { - [0] = { - .start = TEGRA_UARTC_BASE, - .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_UARTC, - .end = INT_UARTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_uartd_resources[] = { - [0] = { - .start = TEGRA_UARTD_BASE, - .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_UARTD, - .end = INT_UARTD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource tegra_uarte_resources[] = { - [0] = { - .start = TEGRA_UARTE_BASE, - .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_UARTE, - .end = INT_UARTE, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device tegra_uarta_device = { - .name = "tegra_uart", - .id = 0, - .num_resources = ARRAY_SIZE(tegra_uarta_resources), - .resource = tegra_uarta_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device tegra_uartb_device = { - .name = "tegra_uart", - .id = 1, - .num_resources = ARRAY_SIZE(tegra_uartb_resources), - .resource = tegra_uartb_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device tegra_uartc_device = { - .name = "tegra_uart", - .id = 2, - .num_resources = ARRAY_SIZE(tegra_uartc_resources), - .resource = tegra_uartc_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device tegra_uartd_device = { - .name = "tegra_uart", - .id = 3, - .num_resources = ARRAY_SIZE(tegra_uartd_resources), - .resource = tegra_uartd_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device tegra_uarte_device = { - .name = "tegra_uart", - .id = 4, - .num_resources = ARRAY_SIZE(tegra_uarte_resources), - .resource = tegra_uarte_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource i2s_resource1[] = { - [0] = { - .start = INT_I2S1, - .end = INT_I2S1, - .flags = IORESOURCE_IRQ - }, - [1] = { - .start = TEGRA_DMA_REQ_SEL_I2S_1, - .end = TEGRA_DMA_REQ_SEL_I2S_1, - .flags = IORESOURCE_DMA - }, - [2] = { - .start = TEGRA_I2S1_BASE, - .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1, - .flags = IORESOURCE_MEM - } -}; - -static struct resource i2s_resource2[] = { - [0] = { - .start = INT_I2S2, - .end = INT_I2S2, - .flags = IORESOURCE_IRQ - }, - [1] = { - .start = TEGRA_DMA_REQ_SEL_I2S2_1, - .end = TEGRA_DMA_REQ_SEL_I2S2_1, - .flags = IORESOURCE_DMA - }, - [2] = { - .start = TEGRA_I2S2_BASE, - .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1, - .flags = IORESOURCE_MEM - } -}; - -struct platform_device tegra_i2s_device1 = { - .name = "tegra20-i2s", - .id = 0, - .resource = i2s_resource1, - .num_resources = ARRAY_SIZE(i2s_resource1), -}; - -struct platform_device tegra_i2s_device2 = { - .name = "tegra20-i2s", - .id = 1, - .resource = i2s_resource2, - .num_resources = ARRAY_SIZE(i2s_resource2), -}; - -static struct resource tegra_das_resources[] = { - [0] = { - .start = TEGRA_APB_MISC_DAS_BASE, - .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device tegra_das_device = { - .name = "tegra20-das", - .id = -1, - .num_resources = ARRAY_SIZE(tegra_das_resources), - .resource = tegra_das_resources, -}; diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h deleted file mode 100644 index 4f5052726495..000000000000 --- a/arch/arm/mach-tegra/devices.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2010,2011 Google, Inc. - * - * Author: - * Colin Cross <ccross@android.com> - * Erik Gilling <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_DEVICES_H -#define __MACH_TEGRA_DEVICES_H - -#include <linux/platform_device.h> -#include <linux/platform_data/tegra_usb.h> - -#include <mach/usb_phy.h> - -extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config; - -extern struct tegra_ehci_platform_data tegra_ehci1_pdata; -extern struct tegra_ehci_platform_data tegra_ehci2_pdata; -extern struct tegra_ehci_platform_data tegra_ehci3_pdata; - -extern struct platform_device tegra_gpio_device; -extern struct platform_device tegra_pinmux_device; -extern struct platform_device tegra_sdhci_device1; -extern struct platform_device tegra_sdhci_device2; -extern struct platform_device tegra_sdhci_device3; -extern struct platform_device tegra_sdhci_device4; -extern struct platform_device tegra_i2c_device1; -extern struct platform_device tegra_i2c_device2; -extern struct platform_device tegra_i2c_device3; -extern struct platform_device tegra_i2c_device4; -extern struct platform_device tegra_spi_device1; -extern struct platform_device tegra_spi_device2; -extern struct platform_device tegra_spi_device3; -extern struct platform_device tegra_spi_device4; -extern struct platform_device tegra_ehci1_device; -extern struct platform_device tegra_ehci2_device; -extern struct platform_device tegra_ehci3_device; -extern struct platform_device tegra_uarta_device; -extern struct platform_device tegra_uartb_device; -extern struct platform_device tegra_uartc_device; -extern struct platform_device tegra_uartd_device; -extern struct platform_device tegra_uarte_device; -extern struct platform_device tegra_pmu_device; -extern struct platform_device tegra_i2s_device1; -extern struct platform_device tegra_i2s_device2; -extern struct platform_device tegra_das_device; - -#endif diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c deleted file mode 100644 index 29c5114d607c..000000000000 --- a/arch/arm/mach-tegra/dma.c +++ /dev/null @@ -1,823 +0,0 @@ -/* - * arch/arm/mach-tegra/dma.c - * - * System DMA driver for NVIDIA Tegra SoCs - * - * Copyright (c) 2008-2009, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/err.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <mach/dma.h> -#include <mach/irqs.h> -#include <mach/iomap.h> -#include <mach/suspend.h> - -#include "apbio.h" - -#define APB_DMA_GEN 0x000 -#define GEN_ENABLE (1<<31) - -#define APB_DMA_CNTRL 0x010 - -#define APB_DMA_IRQ_MASK 0x01c - -#define APB_DMA_IRQ_MASK_SET 0x020 - -#define APB_DMA_CHAN_CSR 0x000 -#define CSR_ENB (1<<31) -#define CSR_IE_EOC (1<<30) -#define CSR_HOLD (1<<29) -#define CSR_DIR (1<<28) -#define CSR_ONCE (1<<27) -#define CSR_FLOW (1<<21) -#define CSR_REQ_SEL_SHIFT 16 -#define CSR_WCOUNT_SHIFT 2 -#define CSR_WCOUNT_MASK 0xFFFC - -#define APB_DMA_CHAN_STA 0x004 -#define STA_BUSY (1<<31) -#define STA_ISE_EOC (1<<30) -#define STA_HALT (1<<29) -#define STA_PING_PONG (1<<28) -#define STA_COUNT_SHIFT 2 -#define STA_COUNT_MASK 0xFFFC - -#define APB_DMA_CHAN_AHB_PTR 0x010 - -#define APB_DMA_CHAN_AHB_SEQ 0x014 -#define AHB_SEQ_INTR_ENB (1<<31) -#define AHB_SEQ_BUS_WIDTH_SHIFT 28 -#define AHB_SEQ_BUS_WIDTH_MASK (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_8 (0<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_16 (1<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_32 (2<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_64 (3<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_BUS_WIDTH_128 (4<<AHB_SEQ_BUS_WIDTH_SHIFT) -#define AHB_SEQ_DATA_SWAP (1<<27) -#define AHB_SEQ_BURST_MASK (0x7<<24) -#define AHB_SEQ_BURST_1 (4<<24) -#define AHB_SEQ_BURST_4 (5<<24) -#define AHB_SEQ_BURST_8 (6<<24) -#define AHB_SEQ_DBL_BUF (1<<19) -#define AHB_SEQ_WRAP_SHIFT 16 -#define AHB_SEQ_WRAP_MASK (0x7<<AHB_SEQ_WRAP_SHIFT) - -#define APB_DMA_CHAN_APB_PTR 0x018 - -#define APB_DMA_CHAN_APB_SEQ 0x01c -#define APB_SEQ_BUS_WIDTH_SHIFT 28 -#define APB_SEQ_BUS_WIDTH_MASK (0x7<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_BUS_WIDTH_8 (0<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_BUS_WIDTH_16 (1<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_BUS_WIDTH_32 (2<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_BUS_WIDTH_64 (3<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_BUS_WIDTH_128 (4<<APB_SEQ_BUS_WIDTH_SHIFT) -#define APB_SEQ_DATA_SWAP (1<<27) -#define APB_SEQ_WRAP_SHIFT 16 -#define APB_SEQ_WRAP_MASK (0x7<<APB_SEQ_WRAP_SHIFT) - -#define TEGRA_SYSTEM_DMA_CH_NR 16 -#define TEGRA_SYSTEM_DMA_AVP_CH_NUM 4 -#define TEGRA_SYSTEM_DMA_CH_MIN 0 -#define TEGRA_SYSTEM_DMA_CH_MAX \ - (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1) - -#define NV_DMA_MAX_TRASFER_SIZE 0x10000 - -static const unsigned int ahb_addr_wrap_table[8] = { - 0, 32, 64, 128, 256, 512, 1024, 2048 -}; - -static const unsigned int apb_addr_wrap_table[8] = { - 0, 1, 2, 4, 8, 16, 32, 64 -}; - -static const unsigned int bus_width_table[5] = { - 8, 16, 32, 64, 128 -}; - -#define TEGRA_DMA_NAME_SIZE 16 -struct tegra_dma_channel { - struct list_head list; - int id; - spinlock_t lock; - char name[TEGRA_DMA_NAME_SIZE]; - void __iomem *addr; - int mode; - int irq; - int req_transfer_count; -}; - -#define NV_DMA_MAX_CHANNELS 32 - -static bool tegra_dma_initialized; -static DEFINE_MUTEX(tegra_dma_lock); -static DEFINE_SPINLOCK(enable_lock); - -static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS); -static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS]; - -static void tegra_dma_update_hw(struct tegra_dma_channel *ch, - struct tegra_dma_req *req); -static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, - struct tegra_dma_req *req); -static void tegra_dma_stop(struct tegra_dma_channel *ch); - -void tegra_dma_flush(struct tegra_dma_channel *ch) -{ -} -EXPORT_SYMBOL(tegra_dma_flush); - -void tegra_dma_dequeue(struct tegra_dma_channel *ch) -{ - struct tegra_dma_req *req; - - if (tegra_dma_is_empty(ch)) - return; - - req = list_entry(ch->list.next, typeof(*req), node); - - tegra_dma_dequeue_req(ch, req); - return; -} - -static void tegra_dma_stop(struct tegra_dma_channel *ch) -{ - u32 csr; - u32 status; - - csr = readl(ch->addr + APB_DMA_CHAN_CSR); - csr &= ~CSR_IE_EOC; - writel(csr, ch->addr + APB_DMA_CHAN_CSR); - - csr &= ~CSR_ENB; - writel(csr, ch->addr + APB_DMA_CHAN_CSR); - - status = readl(ch->addr + APB_DMA_CHAN_STA); - if (status & STA_ISE_EOC) - writel(status, ch->addr + APB_DMA_CHAN_STA); -} - -static int tegra_dma_cancel(struct tegra_dma_channel *ch) -{ - unsigned long irq_flags; - - spin_lock_irqsave(&ch->lock, irq_flags); - while (!list_empty(&ch->list)) - list_del(ch->list.next); - - tegra_dma_stop(ch); - - spin_unlock_irqrestore(&ch->lock, irq_flags); - return 0; -} - -static unsigned int get_channel_status(struct tegra_dma_channel *ch, - struct tegra_dma_req *req, bool is_stop_dma) -{ - void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); - unsigned int status; - - if (is_stop_dma) { - /* - * STOP the DMA and get the transfer count. - * Getting the transfer count is tricky. - * - Globally disable DMA on all channels - * - Read the channel's status register to know the number - * of pending bytes to be transfered. - * - Stop the dma channel - * - Globally re-enable DMA to resume other transfers - */ - spin_lock(&enable_lock); - writel(0, addr + APB_DMA_GEN); - udelay(20); - status = readl(ch->addr + APB_DMA_CHAN_STA); - tegra_dma_stop(ch); - writel(GEN_ENABLE, addr + APB_DMA_GEN); - spin_unlock(&enable_lock); - if (status & STA_ISE_EOC) { - pr_err("Got Dma Int here clearing"); - writel(status, ch->addr + APB_DMA_CHAN_STA); - } - req->status = TEGRA_DMA_REQ_ERROR_ABORTED; - } else { - status = readl(ch->addr + APB_DMA_CHAN_STA); - } - return status; -} - -/* should be called with the channel lock held */ -static unsigned int dma_active_count(struct tegra_dma_channel *ch, - struct tegra_dma_req *req, unsigned int status) -{ - unsigned int to_transfer; - unsigned int req_transfer_count; - unsigned int bytes_transferred; - - to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1; - req_transfer_count = ch->req_transfer_count + 1; - bytes_transferred = req_transfer_count; - if (status & STA_BUSY) - bytes_transferred -= to_transfer; - /* - * In continuous transfer mode, DMA only tracks the count of the - * half DMA buffer. So, if the DMA already finished half the DMA - * then add the half buffer to the completed count. - */ - if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) { - if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) - bytes_transferred += req_transfer_count; - if (status & STA_ISE_EOC) - bytes_transferred += req_transfer_count; - } - bytes_transferred *= 4; - return bytes_transferred; -} - -int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, - struct tegra_dma_req *_req) -{ - unsigned int status; - struct tegra_dma_req *req = NULL; - int found = 0; - unsigned long irq_flags; - int stop = 0; - - spin_lock_irqsave(&ch->lock, irq_flags); - - if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req) - stop = 1; - - list_for_each_entry(req, &ch->list, node) { - if (req == _req) { - list_del(&req->node); - found = 1; - break; - } - } - if (!found) { - spin_unlock_irqrestore(&ch->lock, irq_flags); - return 0; - } - - if (!stop) - goto skip_stop_dma; - - status = get_channel_status(ch, req, true); - req->bytes_transferred = dma_active_count(ch, req, status); - - if (!list_empty(&ch->list)) { - /* if the list is not empty, queue the next request */ - struct tegra_dma_req *next_req; - next_req = list_entry(ch->list.next, - typeof(*next_req), node); - tegra_dma_update_hw(ch, next_req); - } - -skip_stop_dma: - req->status = -TEGRA_DMA_REQ_ERROR_ABORTED; - - spin_unlock_irqrestore(&ch->lock, irq_flags); - - /* Callback should be called without any lock */ - req->complete(req); - return 0; -} -EXPORT_SYMBOL(tegra_dma_dequeue_req); - -bool tegra_dma_is_empty(struct tegra_dma_channel *ch) -{ - unsigned long irq_flags; - bool is_empty; - - spin_lock_irqsave(&ch->lock, irq_flags); - if (list_empty(&ch->list)) - is_empty = true; - else - is_empty = false; - spin_unlock_irqrestore(&ch->lock, irq_flags); - return is_empty; -} -EXPORT_SYMBOL(tegra_dma_is_empty); - -bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch, - struct tegra_dma_req *_req) -{ - unsigned long irq_flags; - struct tegra_dma_req *req; - - spin_lock_irqsave(&ch->lock, irq_flags); - list_for_each_entry(req, &ch->list, node) { - if (req == _req) { - spin_unlock_irqrestore(&ch->lock, irq_flags); - return true; - } - } - spin_unlock_irqrestore(&ch->lock, irq_flags); - return false; -} -EXPORT_SYMBOL(tegra_dma_is_req_inflight); - -int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, - struct tegra_dma_req *req) -{ - unsigned long irq_flags; - struct tegra_dma_req *_req; - int start_dma = 0; - - if (req->size > NV_DMA_MAX_TRASFER_SIZE || - req->source_addr & 0x3 || req->dest_addr & 0x3) { - pr_err("Invalid DMA request for channel %d\n", ch->id); - return -EINVAL; - } - - spin_lock_irqsave(&ch->lock, irq_flags); - - list_for_each_entry(_req, &ch->list, node) { - if (req == _req) { - spin_unlock_irqrestore(&ch->lock, irq_flags); - return -EEXIST; - } - } - - req->bytes_transferred = 0; - req->status = 0; - req->buffer_status = 0; - if (list_empty(&ch->list)) - start_dma = 1; - - list_add_tail(&req->node, &ch->list); - - if (start_dma) - tegra_dma_update_hw(ch, req); - - spin_unlock_irqrestore(&ch->lock, irq_flags); - - return 0; -} -EXPORT_SYMBOL(tegra_dma_enqueue_req); - -struct tegra_dma_channel *tegra_dma_allocate_channel(int mode) -{ - int channel; - struct tegra_dma_channel *ch = NULL; - - if (!tegra_dma_initialized) - return NULL; - - mutex_lock(&tegra_dma_lock); - - /* first channel is the shared channel */ - if (mode & TEGRA_DMA_SHARED) { - channel = TEGRA_SYSTEM_DMA_CH_MIN; - } else { - channel = find_first_zero_bit(channel_usage, - ARRAY_SIZE(dma_channels)); - if (channel >= ARRAY_SIZE(dma_channels)) - goto out; - } - __set_bit(channel, channel_usage); - ch = &dma_channels[channel]; - ch->mode = mode; - -out: - mutex_unlock(&tegra_dma_lock); - return ch; -} -EXPORT_SYMBOL(tegra_dma_allocate_channel); - -void tegra_dma_free_channel(struct tegra_dma_channel *ch) -{ - if (ch->mode & TEGRA_DMA_SHARED) - return; - tegra_dma_cancel(ch); - mutex_lock(&tegra_dma_lock); - __clear_bit(ch->id, channel_usage); - mutex_unlock(&tegra_dma_lock); -} -EXPORT_SYMBOL(tegra_dma_free_channel); - -static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch, - struct tegra_dma_req *req) -{ - u32 apb_ptr; - u32 ahb_ptr; - - if (req->to_memory) { - apb_ptr = req->source_addr; - ahb_ptr = req->dest_addr; - } else { - apb_ptr = req->dest_addr; - ahb_ptr = req->source_addr; - } - writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); - writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); - - req->status = TEGRA_DMA_REQ_INFLIGHT; - return; -} - -static void tegra_dma_update_hw(struct tegra_dma_channel *ch, - struct tegra_dma_req *req) -{ - int ahb_addr_wrap; - int apb_addr_wrap; - int ahb_bus_width; - int apb_bus_width; - int index; - - u32 ahb_seq; - u32 apb_seq; - u32 ahb_ptr; - u32 apb_ptr; - u32 csr; - - csr = CSR_IE_EOC | CSR_FLOW; - ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1; - apb_seq = 0; - - csr |= req->req_sel << CSR_REQ_SEL_SHIFT; - - /* One shot mode is always single buffered, - * continuous mode is always double buffered - * */ - if (ch->mode & TEGRA_DMA_MODE_ONESHOT) { - csr |= CSR_ONCE; - ch->req_transfer_count = (req->size >> 2) - 1; - } else { - ahb_seq |= AHB_SEQ_DBL_BUF; - - /* In double buffered mode, we set the size to half the - * requested size and interrupt when half the buffer - * is full */ - ch->req_transfer_count = (req->size >> 3) - 1; - } - - csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT; - - if (req->to_memory) { - apb_ptr = req->source_addr; - ahb_ptr = req->dest_addr; - - apb_addr_wrap = req->source_wrap; - ahb_addr_wrap = req->dest_wrap; - apb_bus_width = req->source_bus_width; - ahb_bus_width = req->dest_bus_width; - - } else { - csr |= CSR_DIR; - apb_ptr = req->dest_addr; - ahb_ptr = req->source_addr; - - apb_addr_wrap = req->dest_wrap; - ahb_addr_wrap = req->source_wrap; - apb_bus_width = req->dest_bus_width; - ahb_bus_width = req->source_bus_width; - } - - apb_addr_wrap >>= 2; - ahb_addr_wrap >>= 2; - - /* set address wrap for APB size */ - index = 0; - do { - if (apb_addr_wrap_table[index] == apb_addr_wrap) - break; - index++; - } while (index < ARRAY_SIZE(apb_addr_wrap_table)); - BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table)); - apb_seq |= index << APB_SEQ_WRAP_SHIFT; - - /* set address wrap for AHB size */ - index = 0; - do { - if (ahb_addr_wrap_table[index] == ahb_addr_wrap) - break; - index++; - } while (index < ARRAY_SIZE(ahb_addr_wrap_table)); - BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table)); - ahb_seq |= index << AHB_SEQ_WRAP_SHIFT; - - for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { - if (bus_width_table[index] == ahb_bus_width) - break; - } - BUG_ON(index == ARRAY_SIZE(bus_width_table)); - ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT; - - for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) { - if (bus_width_table[index] == apb_bus_width) - break; - } - BUG_ON(index == ARRAY_SIZE(bus_width_table)); - apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT; - - writel(csr, ch->addr + APB_DMA_CHAN_CSR); - writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ); - writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR); - writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ); - writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR); - - csr |= CSR_ENB; - writel(csr, ch->addr + APB_DMA_CHAN_CSR); - - req->status = TEGRA_DMA_REQ_INFLIGHT; -} - -static void handle_oneshot_dma(struct tegra_dma_channel *ch) -{ - struct tegra_dma_req *req; - unsigned long irq_flags; - - spin_lock_irqsave(&ch->lock, irq_flags); - if (list_empty(&ch->list)) { - spin_unlock_irqrestore(&ch->lock, irq_flags); - return; - } - - req = list_entry(ch->list.next, typeof(*req), node); - if (req) { - int bytes_transferred; - - bytes_transferred = ch->req_transfer_count; - bytes_transferred += 1; - bytes_transferred <<= 2; - - list_del(&req->node); - req->bytes_transferred = bytes_transferred; - req->status = TEGRA_DMA_REQ_SUCCESS; - - spin_unlock_irqrestore(&ch->lock, irq_flags); - /* Callback should be called without any lock */ - pr_debug("%s: transferred %d bytes\n", __func__, - req->bytes_transferred); - req->complete(req); - spin_lock_irqsave(&ch->lock, irq_flags); - } - - if (!list_empty(&ch->list)) { - req = list_entry(ch->list.next, typeof(*req), node); - /* the complete function we just called may have enqueued - another req, in which case dma has already started */ - if (req->status != TEGRA_DMA_REQ_INFLIGHT) - tegra_dma_update_hw(ch, req); - } - spin_unlock_irqrestore(&ch->lock, irq_flags); -} - -static void handle_continuous_dma(struct tegra_dma_channel *ch) -{ - struct tegra_dma_req *req; - unsigned long irq_flags; - - spin_lock_irqsave(&ch->lock, irq_flags); - if (list_empty(&ch->list)) { - spin_unlock_irqrestore(&ch->lock, irq_flags); - return; - } - - req = list_entry(ch->list.next, typeof(*req), node); - if (req) { - if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) { - bool is_dma_ping_complete; - is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA) - & STA_PING_PONG) ? true : false; - if (req->to_memory) - is_dma_ping_complete = !is_dma_ping_complete; - /* Out of sync - Release current buffer */ - if (!is_dma_ping_complete) { - int bytes_transferred; - - bytes_transferred = ch->req_transfer_count; - bytes_transferred += 1; - bytes_transferred <<= 3; - req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL; - req->bytes_transferred = bytes_transferred; - req->status = TEGRA_DMA_REQ_SUCCESS; - tegra_dma_stop(ch); - - if (!list_is_last(&req->node, &ch->list)) { - struct tegra_dma_req *next_req; - - next_req = list_entry(req->node.next, - typeof(*next_req), node); - tegra_dma_update_hw(ch, next_req); - } - - list_del(&req->node); - - /* DMA lock is NOT held when callbak is called */ - spin_unlock_irqrestore(&ch->lock, irq_flags); - req->complete(req); - return; - } - /* Load the next request into the hardware, if available - * */ - if (!list_is_last(&req->node, &ch->list)) { - struct tegra_dma_req *next_req; - - next_req = list_entry(req->node.next, - typeof(*next_req), node); - tegra_dma_update_hw_partial(ch, next_req); - } - req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL; - req->status = TEGRA_DMA_REQ_SUCCESS; - /* DMA lock is NOT held when callback is called */ - spin_unlock_irqrestore(&ch->lock, irq_flags); - if (likely(req->threshold)) - req->threshold(req); - return; - - } else if (req->buffer_status == - TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) { - /* Callback when the buffer is completely full (i.e on - * the second interrupt */ - int bytes_transferred; - - bytes_transferred = ch->req_transfer_count; - bytes_transferred += 1; - bytes_transferred <<= 3; - - req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL; - req->bytes_transferred = bytes_transferred; - req->status = TEGRA_DMA_REQ_SUCCESS; - list_del(&req->node); - - /* DMA lock is NOT held when callbak is called */ - spin_unlock_irqrestore(&ch->lock, irq_flags); - req->complete(req); - return; - - } else { - BUG(); - } - } - spin_unlock_irqrestore(&ch->lock, irq_flags); -} - -static irqreturn_t dma_isr(int irq, void *data) -{ - struct tegra_dma_channel *ch = data; - unsigned long status; - - status = readl(ch->addr + APB_DMA_CHAN_STA); - if (status & STA_ISE_EOC) - writel(status, ch->addr + APB_DMA_CHAN_STA); - else { - pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id); - return IRQ_HANDLED; - } - return IRQ_WAKE_THREAD; -} - -static irqreturn_t dma_thread_fn(int irq, void *data) -{ - struct tegra_dma_channel *ch = data; - - if (ch->mode & TEGRA_DMA_MODE_ONESHOT) - handle_oneshot_dma(ch); - else - handle_continuous_dma(ch); - - - return IRQ_HANDLED; -} - -int __init tegra_dma_init(void) -{ - int ret = 0; - int i; - unsigned int irq; - void __iomem *addr; - struct clk *c; - - bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS); - - c = clk_get_sys("tegra-apbdma", NULL); - if (IS_ERR(c)) { - pr_err("Unable to get clock for APB DMA\n"); - ret = PTR_ERR(c); - goto fail; - } - ret = clk_prepare_enable(c); - if (ret != 0) { - pr_err("Unable to enable clock for APB DMA\n"); - goto fail; - } - - addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); - writel(GEN_ENABLE, addr + APB_DMA_GEN); - writel(0, addr + APB_DMA_CNTRL); - writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX), - addr + APB_DMA_IRQ_MASK_SET); - - for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { - struct tegra_dma_channel *ch = &dma_channels[i]; - - ch->id = i; - snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i); - - ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + - TEGRA_APB_DMA_CH0_SIZE * i); - - spin_lock_init(&ch->lock); - INIT_LIST_HEAD(&ch->list); - - irq = INT_APB_DMA_CH0 + i; - ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0, - dma_channels[i].name, ch); - if (ret) { - pr_err("Failed to register IRQ %d for DMA %d\n", - irq, i); - goto fail; - } - ch->irq = irq; - - __clear_bit(i, channel_usage); - } - /* mark the shared channel allocated */ - __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage); - - tegra_dma_initialized = true; - - return 0; -fail: - writel(0, addr + APB_DMA_GEN); - for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) { - struct tegra_dma_channel *ch = &dma_channels[i]; - if (ch->irq) - free_irq(ch->irq, ch); - } - return ret; -} -postcore_initcall(tegra_dma_init); - -#ifdef CONFIG_PM -static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3]; - -void tegra_dma_suspend(void) -{ - void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); - u32 *ctx = apb_dma; - int i; - - *ctx++ = readl(addr + APB_DMA_GEN); - *ctx++ = readl(addr + APB_DMA_CNTRL); - *ctx++ = readl(addr + APB_DMA_IRQ_MASK); - - for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) { - addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + - TEGRA_APB_DMA_CH0_SIZE * i); - - *ctx++ = readl(addr + APB_DMA_CHAN_CSR); - *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR); - *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ); - *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR); - *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ); - } -} - -void tegra_dma_resume(void) -{ - void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); - u32 *ctx = apb_dma; - int i; - - writel(*ctx++, addr + APB_DMA_GEN); - writel(*ctx++, addr + APB_DMA_CNTRL); - writel(*ctx++, addr + APB_DMA_IRQ_MASK); - - for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) { - addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE + - TEGRA_APB_DMA_CH0_SIZE * i); - - writel(*ctx++, addr + APB_DMA_CHAN_CSR); - writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR); - writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ); - writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR); - writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ); - } -} - -#endif diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index f946d129423c..0b7db174a5de 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -93,9 +93,9 @@ void tegra_init_fuse(void) { u32 id; - u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); reg |= 1 << 28; - writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); + writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); reg = tegra_fuse_readl(FUSE_SKU_INFO); tegra_sku_id = reg & 0xFF; diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index fef9c2c51370..6addc78cb6b2 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -7,17 +7,13 @@ #include "flowctrl.h" #include "reset.h" +#include "sleep.h" #define APB_MISC_GP_HIDREV 0x804 #define PMC_SCRATCH41 0x140 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - .macro mov32, reg, val - movw \reg, #:lower16:\val - movt \reg, #:upper16:\val - .endm - .section ".text.head", "ax" __CPUINIT diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index d8dc9ddd6d18..d02a35476135 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -1,91 +1,23 @@ /* - * linux/arch/arm/mach-realview/hotplug.c * * Copyright (C) 2002 ARM Ltd. * All Rights Reserved + * Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include <linux/kernel.h> -#include <linux/errno.h> #include <linux/smp.h> #include <asm/cacheflush.h> -#include <asm/cp15.h> +#include <asm/smp_plat.h> -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - flush_cache_all(); - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C) - : "cc"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); +#include "sleep.h" +#include "tegra_cpu_car.h" - /*if (pen_release == cpu) {*/ - /* - * OK, proper wakeup, we're done - */ - break; - /*}*/ - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} +static void (*tegra_hotplug_shutdown)(void); int platform_cpu_kill(unsigned int cpu) { @@ -99,22 +31,20 @@ int platform_cpu_kill(unsigned int cpu) */ void platform_cpu_die(unsigned int cpu) { - int spurious = 0; + cpu = cpu_logical_map(cpu); - /* - * we're ready for shutdown now, so do it - */ - cpu_enter_lowpower(); - platform_do_lowpower(cpu, &spurious); + /* Flush the L1 data cache. */ + flush_cache_all(); - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - cpu_leave_lowpower(); + /* Shut down the current CPU. */ + tegra_hotplug_shutdown(); - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); + /* Clock gate the CPU */ + tegra_wait_cpu_in_reset(cpu); + tegra_disable_cpu_clock(cpu); + + /* Should never return here. */ + BUG(); } int platform_cpu_disable(unsigned int cpu) @@ -125,3 +55,19 @@ int platform_cpu_disable(unsigned int cpu) */ return cpu == 0 ? -EPERM : 0; } + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +extern void tegra20_hotplug_shutdown(void); +void __init tegra20_hotplug_init(void) +{ + tegra_hotplug_shutdown = tegra20_hotplug_shutdown; +} +#endif + +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +extern void tegra30_hotplug_shutdown(void); +void __init tegra30_hotplug_init(void) +{ + tegra_hotplug_shutdown = tegra30_hotplug_shutdown; +} +#endif diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index 9077092812c0..3081cc6dda3b 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -51,101 +51,4 @@ #define TEGRA_DMA_REQ_SEL_OWR 25 #define TEGRA_DMA_REQ_SEL_INVALID 31 -struct tegra_dma_req; -struct tegra_dma_channel; - -enum tegra_dma_mode { - TEGRA_DMA_SHARED = 1, - TEGRA_DMA_MODE_CONTINOUS = 2, - TEGRA_DMA_MODE_ONESHOT = 4, -}; - -enum tegra_dma_req_error { - TEGRA_DMA_REQ_SUCCESS = 0, - TEGRA_DMA_REQ_ERROR_ABORTED, - TEGRA_DMA_REQ_INFLIGHT, -}; - -enum tegra_dma_req_buff_status { - TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0, - TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL, - TEGRA_DMA_REQ_BUF_STATUS_FULL, -}; - -struct tegra_dma_req { - struct list_head node; - unsigned int modid; - int instance; - - /* Called when the req is complete and from the DMA ISR context. - * When this is called the req structure is no longer queued by - * the DMA channel. - * - * State of the DMA depends on the number of req it has. If there are - * no DMA requests queued up, then it will STOP the DMA. It there are - * more requests in the DMA, then it will queue the next request. - */ - void (*complete)(struct tegra_dma_req *req); - - /* This is a called from the DMA ISR context when the DMA is still in - * progress and is actively filling same buffer. - * - * In case of continuous mode receive, this threshold is 1/2 the buffer - * size. In other cases, this will not even be called as there is no - * hardware support for it. - * - * In the case of continuous mode receive, if there is next req already - * queued, DMA programs the HW to use that req when this req is - * completed. If there is no "next req" queued, then DMA ISR doesn't do - * anything before calling this callback. - * - * This is mainly used by the cases, where the clients has queued - * only one req and want to get some sort of DMA threshold - * callback to program the next buffer. - * - */ - void (*threshold)(struct tegra_dma_req *req); - - /* 1 to copy to memory. - * 0 to copy from the memory to device FIFO */ - int to_memory; - - void *virt_addr; - - unsigned long source_addr; - unsigned long dest_addr; - unsigned long dest_wrap; - unsigned long source_wrap; - unsigned long source_bus_width; - unsigned long dest_bus_width; - unsigned long req_sel; - unsigned int size; - - /* Updated by the DMA driver on the conpletion of the request. */ - int bytes_transferred; - int status; - - /* DMA completion tracking information */ - int buffer_status; - - /* Client specific data */ - void *dev; -}; - -int tegra_dma_enqueue_req(struct tegra_dma_channel *ch, - struct tegra_dma_req *req); -int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, - struct tegra_dma_req *req); -void tegra_dma_dequeue(struct tegra_dma_channel *ch); -void tegra_dma_flush(struct tegra_dma_channel *ch); - -bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch, - struct tegra_dma_req *req); -bool tegra_dma_is_empty(struct tegra_dma_channel *ch); - -struct tegra_dma_channel *tegra_dma_allocate_channel(int mode); -void tegra_dma_free_channel(struct tegra_dma_channel *ch); - -int __init tegra_dma_init(void); - #endif diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h deleted file mode 100644 index fe700f9ce7dc..000000000000 --- a/arch/arm/mach-tegra/include/mach/io.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/io.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_IO_H -#define __MACH_TEGRA_IO_H - -#define IO_SPACE_LIMIT 0xffff - -#ifndef __ASSEMBLER__ - -#ifdef CONFIG_TEGRA_PCI -extern void __iomem *tegra_pcie_io_base; - -static inline void __iomem *__io(unsigned long addr) -{ - return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT); -} -#else -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#endif - -#define __io(a) __io(a) - -#endif - -#endif diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index 7e76da73121c..fee3a94c4549 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -303,6 +303,9 @@ #define IO_APB_VIRT IOMEM(0xFE300000) #define IO_APB_SIZE SZ_1M +#define TEGRA_PCIE_BASE 0x80000000 +#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) + #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h deleted file mode 100644 index 1f24d304921e..000000000000 --- a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * pinctrl configuration definitions for the NVIDIA Tegra pinmux - * - * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __PINCONF_TEGRA_H__ -#define __PINCONF_TEGRA_H__ - -enum tegra_pinconf_param { - /* argument: tegra_pinconf_pull */ - TEGRA_PINCONF_PARAM_PULL, - /* argument: tegra_pinconf_tristate */ - TEGRA_PINCONF_PARAM_TRISTATE, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_ENABLE_INPUT, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_OPEN_DRAIN, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_LOCK, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_IORESET, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_SCHMITT, - /* argument: Boolean */ - TEGRA_PINCONF_PARAM_LOW_POWER_MODE, - /* argument: Integer, range is HW-dependant */ - TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, - /* argument: Integer, range is HW-dependant */ - TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, - /* argument: Integer, range is HW-dependant */ - TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, - /* argument: Integer, range is HW-dependant */ - TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, -}; - -enum tegra_pinconf_pull { - TEGRA_PINCONFIG_PULL_NONE, - TEGRA_PINCONFIG_PULL_DOWN, - TEGRA_PINCONFIG_PULL_UP, -}; - -enum tegra_pinconf_tristate { - TEGRA_PINCONFIG_DRIVEN, - TEGRA_PINCONFIG_TRISTATE, -}; - -#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) -#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) -#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) - -#endif diff --git a/arch/arm/mach-tegra/include/mach/suspend.h b/arch/arm/mach-tegra/include/mach/suspend.h deleted file mode 100644 index 5af8715d2e1e..000000000000 --- a/arch/arm/mach-tegra/include/mach/suspend.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/suspend.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - -#ifndef _MACH_TEGRA_SUSPEND_H_ -#define _MACH_TEGRA_SUSPEND_H_ - -void tegra_pinmux_suspend(void); -void tegra_irq_suspend(void); -void tegra_gpio_suspend(void); -void tegra_clk_suspend(void); -void tegra_dma_suspend(void); -void tegra_timer_suspend(void); - -void tegra_pinmux_resume(void); -void tegra_irq_resume(void); -void tegra_gpio_resume(void); -void tegra_clk_resume(void); -void tegra_dma_resume(void); -void tegra_timer_resume(void); - -#endif /* _MACH_TEGRA_SUSPEND_H_ */ diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h deleted file mode 100644 index 935ce9f65590..000000000000 --- a/arch/arm/mach-tegra/include/mach/usb_phy.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/usb_phy.h - * - * Copyright (C) 2010 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_USB_PHY_H -#define __MACH_USB_PHY_H - -#include <linux/clk.h> -#include <linux/usb/otg.h> - -struct tegra_utmip_config { - u8 hssync_start_delay; - u8 elastic_limit; - u8 idle_wait_delay; - u8 term_range_adj; - u8 xcvr_setup; - u8 xcvr_lsfslew; - u8 xcvr_lsrslew; -}; - -struct tegra_ulpi_config { - int reset_gpio; - const char *clk; -}; - -enum tegra_usb_phy_port_speed { - TEGRA_USB_PHY_PORT_SPEED_FULL = 0, - TEGRA_USB_PHY_PORT_SPEED_LOW, - TEGRA_USB_PHY_PORT_SPEED_HIGH, -}; - -enum tegra_usb_phy_mode { - TEGRA_USB_PHY_MODE_DEVICE, - TEGRA_USB_PHY_MODE_HOST, -}; - -struct tegra_xtal_freq; - -struct tegra_usb_phy { - int instance; - const struct tegra_xtal_freq *freq; - void __iomem *regs; - void __iomem *pad_regs; - struct clk *clk; - struct clk *pll_u; - struct clk *pad_clk; - enum tegra_usb_phy_mode mode; - void *config; - struct usb_phy *ulpi; -}; - -struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, - void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode); - -int tegra_usb_phy_power_on(struct tegra_usb_phy *phy); - -void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy); - -void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy); - -void tegra_usb_phy_power_off(struct tegra_usb_phy *phy); - -void tegra_usb_phy_preresume(struct tegra_usb_phy *phy); - -void tegra_usb_phy_postresume(struct tegra_usb_phy *phy); - -void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, - enum tegra_usb_phy_port_speed port_speed); - -void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy); - -void tegra_usb_phy_close(struct tegra_usb_phy *phy); - -#endif /* __MACH_USB_PHY_H */ diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index d3ad5150d660..a8dba6489c9b 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); * 0x90000000 - 0x9fffffff - non-prefetchable memory * 0xa0000000 - 0xbfffffff - prefetchable memory */ -#define TEGRA_PCIE_BASE 0x80000000 - #define PCIE_REGS_SZ SZ_16K #define PCIE_CFG_OFF PCIE_REGS_SZ #define PCIE_CFG_SZ SZ_1M @@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); #define PCIE_EXT_CFG_SZ SZ_1M #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) -#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M) -#define MMIO_SIZE SZ_64K #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) #define MEM_SIZE_0 SZ_128M #define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) @@ -204,10 +200,9 @@ struct tegra_pcie_port { bool link_up; - char io_space_name[16]; char mem_space_name[16]; char prefetch_space_name[20]; - struct resource res[3]; + struct resource res[2]; }; struct tegra_pcie_info { @@ -223,17 +218,7 @@ struct tegra_pcie_info { struct clk *pll_e; }; -static struct tegra_pcie_info tegra_pcie = { - .res_mmio = { - .name = "PCI IO", - .start = MMIO_BASE, - .end = MMIO_BASE + MMIO_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -void __iomem *tegra_pcie_io_base; -EXPORT_SYMBOL(tegra_pcie_io_base); +static struct tegra_pcie_info tegra_pcie; static inline void afi_writel(u32 value, unsigned long offset) { @@ -367,17 +352,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); /* Tegra PCIE requires relaxed ordering */ static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) { - u16 val16; - int pos = pci_find_capability(dev, PCI_CAP_ID_EXP); - - if (pos <= 0) { - dev_err(&dev->dev, "skipping relaxed ordering fixup\n"); - return; - } - - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16); - val16 |= PCI_EXP_DEVCTL_RELAX_EN; - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16); + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); } DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); @@ -391,24 +366,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) pp = tegra_pcie.port + nr; pp->root_bus_nr = sys->busnr; - /* - * IORESOURCE_IO - */ - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d I/O", pp->index); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - if (pp->index == 0) { - pp->res[0].start = PCIBIOS_MIN_IO; - pp->res[0].end = pp->res[0].start + SZ_32K - 1; - } else { - pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K; - pp->res[0].end = IO_SPACE_LIMIT; - } - pp->res[0].flags = IORESOURCE_IO; - if (request_resource(&ioport_resource, &pp->res[0])) - panic("Request PCIe IO resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE); /* * IORESOURCE_MEM @@ -416,18 +374,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; + pp->res[0].name = pp->mem_space_name; if (pp->index == 0) { - pp->res[1].start = MEM_BASE_0; - pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; + pp->res[0].start = MEM_BASE_0; + pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1; } else { - pp->res[1].start = MEM_BASE_1; - pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; + pp->res[0].start = MEM_BASE_1; + pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1; } - pp->res[1].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[1])) + pp->res[0].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[0])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset); /* * IORESOURCE_MEM | IORESOURCE_PREFETCH @@ -435,18 +393,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), "PCIe %d PREFETCH MEM", pp->index); pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; - pp->res[2].name = pp->prefetch_space_name; + pp->res[1].name = pp->prefetch_space_name; if (pp->index == 0) { - pp->res[2].start = PREFETCH_MEM_BASE_0; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_0; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1; } else { - pp->res[2].start = PREFETCH_MEM_BASE_1; - pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; + pp->res[1].start = PREFETCH_MEM_BASE_1; + pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1; } - pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (request_resource(&iomem_resource, &pp->res[2])) + pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Prefetch Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -541,8 +499,8 @@ static void tegra_pcie_setup_translations(void) /* Bar 2: downstream IO bar */ fpci_bar = ((__u32)0xfdfc << 16); - size = MMIO_SIZE; - axi_address = MMIO_BASE; + size = SZ_128K; + axi_address = TEGRA_PCIE_IO_BASE; afi_writel(axi_address, AFI_AXI_BAR2_START); afi_writel(size >> 12, AFI_AXI_BAR2_SZ); afi_writel(fpci_bar, AFI_FPCI_BAR2); @@ -776,7 +734,6 @@ static void tegra_pcie_clocks_put(void) static int __init tegra_pcie_get_resources(void) { - struct resource *res_mmio = &tegra_pcie.res_mmio; int err; err = tegra_pcie_clocks_get(); @@ -798,34 +755,16 @@ static int __init tegra_pcie_get_resources(void) goto err_map_reg; } - err = request_resource(&iomem_resource, res_mmio); - if (err) { - pr_err("PCIE: Failed to request resources: %d\n", err); - goto err_req_io; - } - - tegra_pcie_io_base = ioremap_nocache(res_mmio->start, - resource_size(res_mmio)); - if (tegra_pcie_io_base == NULL) { - pr_err("PCIE: Failed to map IO\n"); - err = -ENOMEM; - goto err_map_io; - } - err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_irq; + goto err_req_io; } set_irq_flags(INT_PCIE_INTR, IRQF_VALID); return 0; -err_irq: - iounmap(tegra_pcie_io_base); -err_map_io: - release_resource(&tegra_pcie.res_mmio); err_req_io: iounmap(tegra_pcie.regs); err_map_reg: diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 1a208dbf682f..96ed1718eef0 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -31,6 +31,7 @@ #include "fuse.h" #include "flowctrl.h" #include "reset.h" +#include "tegra_cpu_car.h" extern void tegra_secondary_startup(void); @@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) -#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) -#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340) -#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) -#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c) - -#define CPU_CLOCK(cpu) (0x1<<(8+cpu)) -#define CPU_RESET(cpu) (0x1111ul<<(cpu)) void __cpuinit platform_secondary_init(unsigned int cpu) { @@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) static int tegra20_power_up_cpu(unsigned int cpu) { - u32 reg; - /* Enable the CPU clock. */ - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - barrier(); - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + tegra_enable_cpu_clock(cpu); /* Clear flow controller CSR. */ flowctrl_write_cpu_csr(cpu, 0); @@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu) static int tegra30_power_up_cpu(unsigned int cpu) { - u32 reg; int ret, pwrgateid; unsigned long timeout; @@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) } /* CPU partition is powered. Enable the CPU clock. */ - writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); + tegra_enable_cpu_clock(cpu); udelay(10); /* Remove I/O clamps. */ @@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * via the flow controller). This will have no effect on first boot * of the CPU since it should already be in reset. */ - writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - dmb(); + tegra_put_cpu_in_reset(cpu); /* * Unhalt the CPU. If the flow controller was used to power-gate the @@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) goto done; /* Take the CPU out of reset. */ - writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); - wmb(); + tegra_cpu_out_of_reset(cpu); done: return status; } diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 15d506501ccc..de0662de28a0 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -199,7 +199,9 @@ int __init tegra_powergate_init(void) #ifdef CONFIG_DEBUG_FS -static const char * const powergate_name[] = { +static const char * const *powergate_name; + +static const char * const powergate_name_t20[] = { [TEGRA_POWERGATE_CPU] = "cpu", [TEGRA_POWERGATE_3D] = "3d", [TEGRA_POWERGATE_VENC] = "venc", @@ -209,6 +211,23 @@ static const char * const powergate_name[] = { [TEGRA_POWERGATE_MPE] = "mpe", }; +static const char * const powergate_name_t30[] = { + [TEGRA_POWERGATE_CPU] = "cpu0", + [TEGRA_POWERGATE_3D] = "3d0", + [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_PCIE] = "pcie", + [TEGRA_POWERGATE_L2] = "l2", + [TEGRA_POWERGATE_MPE] = "mpe", + [TEGRA_POWERGATE_HEG] = "heg", + [TEGRA_POWERGATE_SATA] = "sata", + [TEGRA_POWERGATE_CPU1] = "cpu1", + [TEGRA_POWERGATE_CPU2] = "cpu2", + [TEGRA_POWERGATE_CPU3] = "cpu3", + [TEGRA_POWERGATE_CELP] = "celp", + [TEGRA_POWERGATE_3D1] = "3d1", +}; + static int powergate_show(struct seq_file *s, void *data) { int i; @@ -237,14 +256,24 @@ static const struct file_operations powergate_fops = { int __init tegra_powergate_debugfs_init(void) { struct dentry *d; - int err = -ENOMEM; - d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, - &powergate_fops); - if (!d) - return -ENOMEM; + switch (tegra_chip_id) { + case TEGRA20: + powergate_name = powergate_name_t20; + break; + case TEGRA30: + powergate_name = powergate_name_t30; + break; + } + + if (powergate_name) { + d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, + &powergate_fops); + if (!d) + return -ENOMEM; + } - return err; + return 0; } #endif diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S new file mode 100644 index 000000000000..a36ae413e2b8 --- /dev/null +++ b/arch/arm/mach-tegra/sleep-t20.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2011, Google, Inc. + * + * Author: Colin Cross <ccross@android.com> + * Gary King <gking@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> + +#include <asm/assembler.h> + +#include <mach/iomap.h> + +#include "sleep.h" +#include "flowctrl.h" + +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) +/* + * tegra20_hotplug_shutdown(void) + * + * puts the current cpu in reset + * should never return + */ +ENTRY(tegra20_hotplug_shutdown) + /* Turn off SMP coherency */ + exit_smp r4, r5 + + /* Put this CPU down */ + cpu_id r0 + bl tegra20_cpu_shutdown + mov pc, lr @ should never get here +ENDPROC(tegra20_hotplug_shutdown) + +/* + * tegra20_cpu_shutdown(int cpu) + * + * r0 is cpu to reset + * + * puts the specified CPU in wait-for-event mode on the flow controller + * and puts the CPU in reset + * can be called on the current cpu or another cpu + * if called on the current cpu, does not return + * MUST NOT BE CALLED FOR CPU 0. + * + * corrupts r0-r3, r12 + */ +ENTRY(tegra20_cpu_shutdown) + cmp r0, #0 + moveq pc, lr @ must not be called for CPU 0 + + cpu_to_halt_reg r1, r0 + ldr r3, =TEGRA_FLOW_CTRL_VIRT + mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME + str r2, [r3, r1] @ put flow controller in wait event mode + ldr r2, [r3, r1] + isb + dsb + movw r1, 0x1011 + mov r1, r1, lsl r0 + ldr r3, =TEGRA_CLK_RESET_VIRT + str r1, [r3, #0x340] @ put slave CPU in reset + isb + dsb + cpu_id r3 + cmp r3, r0 + beq . + mov pc, lr +ENDPROC(tegra20_cpu_shutdown) +#endif diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S new file mode 100644 index 000000000000..777d9cee8b90 --- /dev/null +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> + +#include <asm/assembler.h> + +#include <mach/iomap.h> + +#include "sleep.h" +#include "flowctrl.h" + +#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ + +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) +/* + * tegra30_hotplug_shutdown(void) + * + * Powergates the current CPU. + * Should never return. + */ +ENTRY(tegra30_hotplug_shutdown) + /* Turn off SMP coherency */ + exit_smp r4, r5 + + /* Powergate this CPU */ + mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN + bl tegra30_cpu_shutdown + mov pc, lr @ should never get here +ENDPROC(tegra30_hotplug_shutdown) + +/* + * tegra30_cpu_shutdown(unsigned long flags) + * + * Puts the current CPU in wait-for-event mode on the flow controller + * and powergates it -- flags (in R0) indicate the request type. + * Must never be called for CPU 0. + * + * corrupts r0-r4, r12 + */ +ENTRY(tegra30_cpu_shutdown) + cpu_id r3 + cmp r3, #0 + moveq pc, lr @ Must never be called for CPU 0 + + ldr r12, =TEGRA_FLOW_CTRL_VIRT + cpu_to_csr_reg r1, r3 + add r1, r1, r12 @ virtual CSR address for this CPU + cpu_to_halt_reg r2, r3 + add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU + + /* + * Clear this CPU's "event" and "interrupt" flags and power gate + * it when halting but not before it is in the "WFE" state. + */ + movw r12, \ + FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ + FLOW_CTRL_CSR_ENABLE + mov r4, #(1 << 4) + orr r12, r12, r4, lsl r3 + str r12, [r1] + + /* Halt this CPU. */ + mov r3, #0x400 +delay_1: + subs r3, r3, #1 @ delay as a part of wfe war. + bge delay_1; + cpsid a @ disable imprecise aborts. + ldr r3, [r1] @ read CSR + str r3, [r1] @ clear CSR + tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN + movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug + str r3, [r2] + ldr r0, [r2] + b wfe_war + +__cpu_reset_again: + dsb + .align 5 + wfe @ CPU should be power gated here +wfe_war: + b __cpu_reset_again + + /* + * 38 nop's, which fills reset of wfe cache line and + * 4 more cachelines with nop + */ + .rept 38 + nop + .endr + b . @ should never get here + +ENDPROC(tegra30_cpu_shutdown) +#endif diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index d29b156a8011..ea81554c4833 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -29,36 +29,5 @@ #include <mach/iomap.h> #include "flowctrl.h" +#include "sleep.h" -#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ - + IO_PPSB_VIRT) - -/* returns the offset of the flow controller halt register for a cpu */ -.macro cpu_to_halt_reg rd, rcpu - cmp \rcpu, #0 - subne \rd, \rcpu, #1 - movne \rd, \rd, lsl #3 - addne \rd, \rd, #0x14 - moveq \rd, #0 -.endm - -/* returns the offset of the flow controller csr register for a cpu */ -.macro cpu_to_csr_reg rd, rcpu - cmp \rcpu, #0 - subne \rd, \rcpu, #1 - movne \rd, \rd, lsl #3 - addne \rd, \rd, #0x18 - moveq \rd, #8 -.endm - -/* returns the ID of the current processor */ -.macro cpu_id, rd - mrc p15, 0, \rd, c0, c0, 5 - and \rd, \rd, #0xF -.endm - -/* loads a 32-bit value into a register without a data access */ -.macro mov32, reg, val - movw \reg, #:lower16:\val - movt \reg, #:upper16:\val -.endm diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h new file mode 100644 index 000000000000..e25a7cd703d9 --- /dev/null +++ b/arch/arm/mach-tegra/sleep.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MACH_TEGRA_SLEEP_H +#define __MACH_TEGRA_SLEEP_H + +#include <mach/iomap.h> + +#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ + + IO_CPU_VIRT) +#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ + + IO_PPSB_VIRT) +#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ + + IO_PPSB_VIRT) + +#ifdef __ASSEMBLY__ +/* returns the offset of the flow controller halt register for a cpu */ +.macro cpu_to_halt_reg rd, rcpu + cmp \rcpu, #0 + subne \rd, \rcpu, #1 + movne \rd, \rd, lsl #3 + addne \rd, \rd, #0x14 + moveq \rd, #0 +.endm + +/* returns the offset of the flow controller csr register for a cpu */ +.macro cpu_to_csr_reg rd, rcpu + cmp \rcpu, #0 + subne \rd, \rcpu, #1 + movne \rd, \rd, lsl #3 + addne \rd, \rd, #0x18 + moveq \rd, #8 +.endm + +/* returns the ID of the current processor */ +.macro cpu_id, rd + mrc p15, 0, \rd, c0, c0, 5 + and \rd, \rd, #0xF +.endm + +/* loads a 32-bit value into a register without a data access */ +.macro mov32, reg, val + movw \reg, #:lower16:\val + movt \reg, #:upper16:\val +.endm + +/* Macro to exit SMP coherency. */ +.macro exit_smp, tmp1, tmp2 + mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR + bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW + mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR + isb + cpu_id \tmp1 + mov \tmp1, \tmp1, lsl #2 + mov \tmp2, #0xf + mov \tmp2, \tmp2, lsl \tmp1 + mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC + str \tmp2, [\tmp1] @ invalidate SCU tags for CPU + dsb +.endm +#else + +#ifdef CONFIG_HOTPLUG_CPU +void tegra20_hotplug_init(void); +void tegra30_hotplug_init(void); +#else +static inline void tegra20_hotplug_init(void) {} +static inline void tegra30_hotplug_init(void) {} +#endif + +#endif +#endif diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c index 840ab262272a..deb873fb12b6 100644 --- a/arch/arm/mach-tegra/tegra20_clocks.c +++ b/arch/arm/mach-tegra/tegra20_clocks.c @@ -28,11 +28,11 @@ #include <linux/clk.h> #include <mach/iomap.h> -#include <mach/suspend.h> #include "clock.h" #include "fuse.h" #include "tegra2_emc.h" +#include "tegra_cpu_car.h" #define RST_DEVICES 0x004 #define RST_DEVICES_SET 0x300 @@ -152,6 +152,14 @@ #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff +/* Tegra CPU clock and reset control regs */ +#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c +#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 +#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 + +#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) +#define CPU_RESET(cpu) (0x1111ul << (cpu)) + static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); @@ -1553,3 +1561,64 @@ struct clk_ops tegra_cdev_clk_ops = { .disable = tegra20_cdev_clk_disable, .recalc_rate = tegra20_cdev_recalc_rate, }; + +/* Tegra20 CPU clock and reset control functions */ +static void tegra20_wait_cpu_in_reset(u32 cpu) +{ + unsigned int reg; + + do { + reg = readl(reg_clk_base + + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); + cpu_relax(); + } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ + + return; +} + +static void tegra20_put_cpu_in_reset(u32 cpu) +{ + writel(CPU_RESET(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); + dmb(); +} + +static void tegra20_cpu_out_of_reset(u32 cpu) +{ + writel(CPU_RESET(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); + wmb(); +} + +static void tegra20_enable_cpu_clock(u32 cpu) +{ + unsigned int reg; + + reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + writel(reg & ~CPU_CLOCK(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + barrier(); + reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); +} + +static void tegra20_disable_cpu_clock(u32 cpu) +{ + unsigned int reg; + + reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + writel(reg | CPU_CLOCK(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); +} + +static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { + .wait_for_reset = tegra20_wait_cpu_in_reset, + .put_in_reset = tegra20_put_cpu_in_reset, + .out_of_reset = tegra20_cpu_out_of_reset, + .enable_clock = tegra20_enable_cpu_clock, + .disable_clock = tegra20_disable_cpu_clock, +}; + +void __init tegra20_cpu_car_ops_init(void) +{ + tegra_cpu_car_ops = &tegra20_cpu_car_ops; +} diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c index 6cfe2f9840fa..cc9b5fd8c3d3 100644 --- a/arch/arm/mach-tegra/tegra20_clocks_data.c +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c @@ -28,12 +28,12 @@ #include <linux/clk.h> #include <mach/iomap.h> -#include <mach/suspend.h> #include "clock.h" #include "fuse.h" #include "tegra2_emc.h" #include "tegra20_clocks.h" +#include "tegra_cpu_car.h" /* Clock definitions */ @@ -1135,4 +1135,5 @@ void __init tegra2_init_clocks(void) } init_audio_sync_clock_mux(); + tegra20_cpu_car_ops_init(); } diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 63615dadfbb2..5cd502c27163 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -35,6 +35,7 @@ #include "clock.h" #include "fuse.h" +#include "tegra_cpu_car.h" #define USE_PLL_LOCK_BITS 0 @@ -299,6 +300,16 @@ /* FIXME: recommended safety delay after lock is detected */ #define PLL_POST_LOCK_DELAY 100 +/* Tegra CPU clock and reset control regs */ +#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c +#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 +#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 +#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c +#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 + +#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) +#define CPU_RESET(cpu) (0x1111ul << (cpu)) + /** * Structure defining the fields for USB UTMI clocks Parameters. */ @@ -2221,3 +2232,64 @@ struct clk_ops tegra_cml_clk_ops = { struct clk_ops tegra_pciex_clk_ops = { .recalc_rate = tegra30_clk_fixed_recalc_rate, }; + +/* Tegra30 CPU clock and reset control functions */ +static void tegra30_wait_cpu_in_reset(u32 cpu) +{ + unsigned int reg; + + do { + reg = readl(reg_clk_base + + TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); + cpu_relax(); + } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ + + return; +} + +static void tegra30_put_cpu_in_reset(u32 cpu) +{ + writel(CPU_RESET(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); + dmb(); +} + +static void tegra30_cpu_out_of_reset(u32 cpu) +{ + writel(CPU_RESET(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); + wmb(); +} + +static void tegra30_enable_cpu_clock(u32 cpu) +{ + unsigned int reg; + + writel(CPU_CLOCK(cpu), + reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); + reg = readl(reg_clk_base + + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); +} + +static void tegra30_disable_cpu_clock(u32 cpu) +{ + + unsigned int reg; + + reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + writel(reg | CPU_CLOCK(cpu), + reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); +} + +static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { + .wait_for_reset = tegra30_wait_cpu_in_reset, + .put_in_reset = tegra30_put_cpu_in_reset, + .out_of_reset = tegra30_cpu_out_of_reset, + .enable_clock = tegra30_enable_cpu_clock, + .disable_clock = tegra30_disable_cpu_clock, +}; + +void __init tegra30_cpu_car_ops_init(void) +{ + tegra_cpu_car_ops = &tegra30_cpu_car_ops; +} diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index 8d2dbdd59174..d92cb556ae35 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -32,6 +32,7 @@ #include "clock.h" #include "fuse.h" #include "tegra30_clocks.h" +#include "tegra_cpu_car.h" #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \ _parent_names, _parents, _parent) \ @@ -1371,4 +1372,6 @@ void __init tegra30_init_clocks(void) for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) tegra30_init_one_clock(tegra_clk_out_list[i]); + + tegra30_cpu_car_ops_init(); } diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h new file mode 100644 index 000000000000..30d063ad2bef --- /dev/null +++ b/arch/arm/mach-tegra/tegra_cpu_car.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MACH_TEGRA_CPU_CAR_H +#define __MACH_TEGRA_CPU_CAR_H + +/* + * Tegra CPU clock and reset control ops + * + * wait_for_reset: + * keep waiting until the CPU in reset state + * put_in_reset: + * put the CPU in reset state + * out_of_reset: + * release the CPU from reset state + * enable_clock: + * CPU clock un-gate + * disable_clock: + * CPU clock gate + */ +struct tegra_cpu_car_ops { + void (*wait_for_reset)(u32 cpu); + void (*put_in_reset)(u32 cpu); + void (*out_of_reset)(u32 cpu); + void (*enable_clock)(u32 cpu); + void (*disable_clock)(u32 cpu); +}; + +extern struct tegra_cpu_car_ops *tegra_cpu_car_ops; + +static inline void tegra_wait_cpu_in_reset(u32 cpu) +{ + if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset)) + return; + + tegra_cpu_car_ops->wait_for_reset(cpu); +} + +static inline void tegra_put_cpu_in_reset(u32 cpu) +{ + if (WARN_ON(!tegra_cpu_car_ops->put_in_reset)) + return; + + tegra_cpu_car_ops->put_in_reset(cpu); +} + +static inline void tegra_cpu_out_of_reset(u32 cpu) +{ + if (WARN_ON(!tegra_cpu_car_ops->out_of_reset)) + return; + + tegra_cpu_car_ops->out_of_reset(cpu); +} + +static inline void tegra_enable_cpu_clock(u32 cpu) +{ + if (WARN_ON(!tegra_cpu_car_ops->enable_clock)) + return; + + tegra_cpu_car_ops->enable_clock(cpu); +} + +static inline void tegra_disable_cpu_clock(u32 cpu) +{ + if (WARN_ON(!tegra_cpu_car_ops->disable_clock)) + return; + + tegra_cpu_car_ops->disable_clock(cpu); +} + +void tegra20_cpu_car_ops_init(void); +void tegra30_cpu_car_ops_init(void); + +#endif /* __MACH_TEGRA_CPU_CAR_H */ diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 57b5bdc13b9b..eccdce983043 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -33,7 +33,6 @@ #include <mach/iomap.h> #include <mach/irqs.h> -#include <mach/suspend.h> #include "board.h" #include "clock.h" diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c deleted file mode 100644 index 022b33a05c3a..000000000000 --- a/arch/arm/mach-tegra/usb_phy.c +++ /dev/null @@ -1,817 +0,0 @@ -/* - * arch/arm/mach-tegra/usb_phy.c - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Erik Gilling <konkers@google.com> - * Benoit Goby <benoit@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/resource.h> -#include <linux/delay.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/export.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/of_gpio.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <asm/mach-types.h> -#include <mach/gpio-tegra.h> -#include <mach/usb_phy.h> -#include <mach/iomap.h> - -#define ULPI_VIEWPORT 0x170 - -#define USB_PORTSC1 0x184 -#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) -#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26) -#define USB_PORTSC1_PHCD (1 << 23) -#define USB_PORTSC1_WKOC (1 << 22) -#define USB_PORTSC1_WKDS (1 << 21) -#define USB_PORTSC1_WKCN (1 << 20) -#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16) -#define USB_PORTSC1_PP (1 << 12) -#define USB_PORTSC1_SUSP (1 << 7) -#define USB_PORTSC1_PE (1 << 2) -#define USB_PORTSC1_CCS (1 << 0) - -#define USB_SUSP_CTRL 0x400 -#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) -#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) -#define USB_SUSP_CLR (1 << 5) -#define USB_PHY_CLK_VALID (1 << 7) -#define UTMIP_RESET (1 << 11) -#define UHSIC_RESET (1 << 11) -#define UTMIP_PHY_ENABLE (1 << 12) -#define ULPI_PHY_ENABLE (1 << 13) -#define USB_SUSP_SET (1 << 14) -#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) - -#define USB1_LEGACY_CTRL 0x410 -#define USB1_NO_LEGACY_MODE (1 << 0) -#define USB1_VBUS_SENSE_CTL_MASK (3 << 1) -#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) -#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ - (1 << 1) -#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) -#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) - -#define ULPI_TIMING_CTRL_0 0x424 -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -#define ULPI_TIMING_CTRL_1 0x428 -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -#define UTMIP_PLL_CFG1 0x804 -#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) -#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) - -#define UTMIP_XCVR_CFG0 0x808 -#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) -#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) -#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) -#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) - -#define UTMIP_BIAS_CFG0 0x80c -#define UTMIP_OTGPD (1 << 11) -#define UTMIP_BIASPD (1 << 10) - -#define UTMIP_HSRX_CFG0 0x810 -#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) -#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) - -#define UTMIP_HSRX_CFG1 0x814 -#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) - -#define UTMIP_TX_CFG0 0x820 -#define UTMIP_FS_PREABMLE_J (1 << 19) -#define UTMIP_HS_DISCON_DISABLE (1 << 8) - -#define UTMIP_MISC_CFG0 0x824 -#define UTMIP_DPDM_OBSERVE (1 << 26) -#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) -#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) -#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) -#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) -#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) -#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) - -#define UTMIP_MISC_CFG1 0x828 -#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) -#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) - -#define UTMIP_DEBOUNCE_CFG0 0x82c -#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) - -#define UTMIP_BAT_CHRG_CFG0 0x830 -#define UTMIP_PD_CHRG (1 << 0) - -#define UTMIP_SPARE_CFG0 0x834 -#define FUSE_SETUP_SEL (1 << 3) - -#define UTMIP_XCVR_CFG1 0x838 -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) -#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) - -#define UTMIP_BIAS_CFG1 0x83c -#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) - -static DEFINE_SPINLOCK(utmip_pad_lock); -static int utmip_pad_count; - -struct tegra_xtal_freq { - int freq; - u8 enable_delay; - u8 stable_count; - u8 active_delay; - u8 xtal_freq_count; - u16 debounce; -}; - -static const struct tegra_xtal_freq tegra_freq_table[] = { - { - .freq = 12000000, - .enable_delay = 0x02, - .stable_count = 0x2F, - .active_delay = 0x04, - .xtal_freq_count = 0x76, - .debounce = 0x7530, - }, - { - .freq = 13000000, - .enable_delay = 0x02, - .stable_count = 0x33, - .active_delay = 0x05, - .xtal_freq_count = 0x7F, - .debounce = 0x7EF4, - }, - { - .freq = 19200000, - .enable_delay = 0x03, - .stable_count = 0x4B, - .active_delay = 0x06, - .xtal_freq_count = 0xBB, - .debounce = 0xBB80, - }, - { - .freq = 26000000, - .enable_delay = 0x04, - .stable_count = 0x66, - .active_delay = 0x09, - .xtal_freq_count = 0xFE, - .debounce = 0xFDE8, - }, -}; - -static struct tegra_utmip_config utmip_default[] = { - [0] = { - .hssync_start_delay = 9, - .idle_wait_delay = 17, - .elastic_limit = 16, - .term_range_adj = 6, - .xcvr_setup = 9, - .xcvr_lsfslew = 1, - .xcvr_lsrslew = 1, - }, - [2] = { - .hssync_start_delay = 9, - .idle_wait_delay = 17, - .elastic_limit = 16, - .term_range_adj = 6, - .xcvr_setup = 9, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - }, -}; - -static inline bool phy_is_ulpi(struct tegra_usb_phy *phy) -{ - return (phy->instance == 1); -} - -static int utmip_pad_open(struct tegra_usb_phy *phy) -{ - phy->pad_clk = clk_get_sys("utmip-pad", NULL); - if (IS_ERR(phy->pad_clk)) { - pr_err("%s: can't get utmip pad clock\n", __func__); - return PTR_ERR(phy->pad_clk); - } - - if (phy->instance == 0) { - phy->pad_regs = phy->regs; - } else { - phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE); - if (!phy->pad_regs) { - pr_err("%s: can't remap usb registers\n", __func__); - clk_put(phy->pad_clk); - return -ENOMEM; - } - } - return 0; -} - -static void utmip_pad_close(struct tegra_usb_phy *phy) -{ - if (phy->instance != 0) - iounmap(phy->pad_regs); - clk_put(phy->pad_clk); -} - -static void utmip_pad_power_on(struct tegra_usb_phy *phy) -{ - unsigned long val, flags; - void __iomem *base = phy->pad_regs; - - clk_prepare_enable(phy->pad_clk); - - spin_lock_irqsave(&utmip_pad_lock, flags); - - if (utmip_pad_count++ == 0) { - val = readl(base + UTMIP_BIAS_CFG0); - val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); - writel(val, base + UTMIP_BIAS_CFG0); - } - - spin_unlock_irqrestore(&utmip_pad_lock, flags); - - clk_disable_unprepare(phy->pad_clk); -} - -static int utmip_pad_power_off(struct tegra_usb_phy *phy) -{ - unsigned long val, flags; - void __iomem *base = phy->pad_regs; - - if (!utmip_pad_count) { - pr_err("%s: utmip pad already powered off\n", __func__); - return -EINVAL; - } - - clk_prepare_enable(phy->pad_clk); - - spin_lock_irqsave(&utmip_pad_lock, flags); - - if (--utmip_pad_count == 0) { - val = readl(base + UTMIP_BIAS_CFG0); - val |= UTMIP_OTGPD | UTMIP_BIASPD; - writel(val, base + UTMIP_BIAS_CFG0); - } - - spin_unlock_irqrestore(&utmip_pad_lock, flags); - - clk_disable_unprepare(phy->pad_clk); - - return 0; -} - -static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) -{ - unsigned long timeout = 2000; - do { - if ((readl(reg) & mask) == result) - return 0; - udelay(1); - timeout--; - } while (timeout); - return -1; -} - -static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - if (phy->instance == 0) { - val = readl(base + USB_SUSP_CTRL); - val |= USB_SUSP_SET; - writel(val, base + USB_SUSP_CTRL); - - udelay(10); - - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_SET; - writel(val, base + USB_SUSP_CTRL); - } - - if (phy->instance == 2) { - val = readl(base + USB_PORTSC1); - val |= USB_PORTSC1_PHCD; - writel(val, base + USB_PORTSC1); - } - - if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) - pr_err("%s: timeout waiting for phy to stabilize\n", __func__); -} - -static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - if (phy->instance == 0) { - val = readl(base + USB_SUSP_CTRL); - val |= USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); - - udelay(10); - - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); - } - - if (phy->instance == 2) { - val = readl(base + USB_PORTSC1); - val &= ~USB_PORTSC1_PHCD; - writel(val, base + USB_PORTSC1); - } - - if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, - USB_PHY_CLK_VALID)) - pr_err("%s: timeout waiting for phy to stabilize\n", __func__); -} - -static int utmi_phy_power_on(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - struct tegra_utmip_config *config = phy->config; - - val = readl(base + USB_SUSP_CTRL); - val |= UTMIP_RESET; - writel(val, base + USB_SUSP_CTRL); - - if (phy->instance == 0) { - val = readl(base + USB1_LEGACY_CTRL); - val |= USB1_NO_LEGACY_MODE; - writel(val, base + USB1_LEGACY_CTRL); - } - - val = readl(base + UTMIP_TX_CFG0); - val &= ~UTMIP_FS_PREABMLE_J; - writel(val, base + UTMIP_TX_CFG0); - - val = readl(base + UTMIP_HSRX_CFG0); - val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); - val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); - val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); - writel(val, base + UTMIP_HSRX_CFG0); - - val = readl(base + UTMIP_HSRX_CFG1); - val &= ~UTMIP_HS_SYNC_START_DLY(~0); - val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); - writel(val, base + UTMIP_HSRX_CFG1); - - val = readl(base + UTMIP_DEBOUNCE_CFG0); - val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); - val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); - writel(val, base + UTMIP_DEBOUNCE_CFG0); - - val = readl(base + UTMIP_MISC_CFG0); - val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; - writel(val, base + UTMIP_MISC_CFG0); - - val = readl(base + UTMIP_MISC_CFG1); - val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); - val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | - UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); - writel(val, base + UTMIP_MISC_CFG1); - - val = readl(base + UTMIP_PLL_CFG1); - val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); - val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | - UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); - writel(val, base + UTMIP_PLL_CFG1); - - if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { - val = readl(base + USB_SUSP_CTRL); - val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); - writel(val, base + USB_SUSP_CTRL); - } - - utmip_pad_power_on(phy); - - val = readl(base + UTMIP_XCVR_CFG0); - val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | - UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | - UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | - UTMIP_XCVR_HSSLEW_MSB(~0)); - val |= UTMIP_XCVR_SETUP(config->xcvr_setup); - val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); - val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); - writel(val, base + UTMIP_XCVR_CFG0); - - val = readl(base + UTMIP_XCVR_CFG1); - val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | - UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); - val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); - writel(val, base + UTMIP_XCVR_CFG1); - - val = readl(base + UTMIP_BAT_CHRG_CFG0); - val &= ~UTMIP_PD_CHRG; - writel(val, base + UTMIP_BAT_CHRG_CFG0); - - val = readl(base + UTMIP_BIAS_CFG1); - val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); - val |= UTMIP_BIAS_PDTRK_COUNT(0x5); - writel(val, base + UTMIP_BIAS_CFG1); - - if (phy->instance == 0) { - val = readl(base + UTMIP_SPARE_CFG0); - if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) - val &= ~FUSE_SETUP_SEL; - else - val |= FUSE_SETUP_SEL; - writel(val, base + UTMIP_SPARE_CFG0); - } - - if (phy->instance == 2) { - val = readl(base + USB_SUSP_CTRL); - val |= UTMIP_PHY_ENABLE; - writel(val, base + USB_SUSP_CTRL); - } - - val = readl(base + USB_SUSP_CTRL); - val &= ~UTMIP_RESET; - writel(val, base + USB_SUSP_CTRL); - - if (phy->instance == 0) { - val = readl(base + USB1_LEGACY_CTRL); - val &= ~USB1_VBUS_SENSE_CTL_MASK; - val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; - writel(val, base + USB1_LEGACY_CTRL); - - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_SET; - writel(val, base + USB_SUSP_CTRL); - } - - utmi_phy_clk_enable(phy); - - if (phy->instance == 2) { - val = readl(base + USB_PORTSC1); - val &= ~USB_PORTSC1_PTS(~0); - writel(val, base + USB_PORTSC1); - } - - return 0; -} - -static void utmi_phy_power_off(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - utmi_phy_clk_disable(phy); - - if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); - val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); - writel(val, base + USB_SUSP_CTRL); - } - - val = readl(base + USB_SUSP_CTRL); - val |= UTMIP_RESET; - writel(val, base + USB_SUSP_CTRL); - - val = readl(base + UTMIP_BAT_CHRG_CFG0); - val |= UTMIP_PD_CHRG; - writel(val, base + UTMIP_BAT_CHRG_CFG0); - - val = readl(base + UTMIP_XCVR_CFG0); - val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | - UTMIP_FORCE_PDZI_POWERDOWN; - writel(val, base + UTMIP_XCVR_CFG0); - - val = readl(base + UTMIP_XCVR_CFG1); - val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | - UTMIP_FORCE_PDDR_POWERDOWN; - writel(val, base + UTMIP_XCVR_CFG1); - - utmip_pad_power_off(phy); -} - -static void utmi_phy_preresume(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - val = readl(base + UTMIP_TX_CFG0); - val |= UTMIP_HS_DISCON_DISABLE; - writel(val, base + UTMIP_TX_CFG0); -} - -static void utmi_phy_postresume(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - val = readl(base + UTMIP_TX_CFG0); - val &= ~UTMIP_HS_DISCON_DISABLE; - writel(val, base + UTMIP_TX_CFG0); -} - -static void utmi_phy_restore_start(struct tegra_usb_phy *phy, - enum tegra_usb_phy_port_speed port_speed) -{ - unsigned long val; - void __iomem *base = phy->regs; - - val = readl(base + UTMIP_MISC_CFG0); - val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); - if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) - val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; - else - val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; - writel(val, base + UTMIP_MISC_CFG0); - udelay(1); - - val = readl(base + UTMIP_MISC_CFG0); - val |= UTMIP_DPDM_OBSERVE; - writel(val, base + UTMIP_MISC_CFG0); - udelay(10); -} - -static void utmi_phy_restore_end(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - - val = readl(base + UTMIP_MISC_CFG0); - val &= ~UTMIP_DPDM_OBSERVE; - writel(val, base + UTMIP_MISC_CFG0); - udelay(10); -} - -static int ulpi_phy_power_on(struct tegra_usb_phy *phy) -{ - int ret; - unsigned long val; - void __iomem *base = phy->regs; - struct tegra_ulpi_config *config = phy->config; - - gpio_direction_output(config->reset_gpio, 0); - msleep(5); - gpio_direction_output(config->reset_gpio, 1); - - clk_prepare_enable(phy->clk); - msleep(1); - - val = readl(base + USB_SUSP_CTRL); - val |= UHSIC_RESET; - writel(val, base + USB_SUSP_CTRL); - - val = readl(base + ULPI_TIMING_CTRL_0); - val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; - writel(val, base + ULPI_TIMING_CTRL_0); - - val = readl(base + USB_SUSP_CTRL); - val |= ULPI_PHY_ENABLE; - writel(val, base + USB_SUSP_CTRL); - - val = 0; - writel(val, base + ULPI_TIMING_CTRL_1); - - val |= ULPI_DATA_TRIMMER_SEL(4); - val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); - val |= ULPI_DIR_TRIMMER_SEL(4); - writel(val, base + ULPI_TIMING_CTRL_1); - udelay(10); - - val |= ULPI_DATA_TRIMMER_LOAD; - val |= ULPI_STPDIRNXT_TRIMMER_LOAD; - val |= ULPI_DIR_TRIMMER_LOAD; - writel(val, base + ULPI_TIMING_CTRL_1); - - /* Fix VbusInvalid due to floating VBUS */ - ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; - } - - ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; - } - - val = readl(base + USB_PORTSC1); - val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN; - writel(val, base + USB_PORTSC1); - - val = readl(base + USB_SUSP_CTRL); - val |= USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); - udelay(100); - - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); - - return 0; -} - -static void ulpi_phy_power_off(struct tegra_usb_phy *phy) -{ - unsigned long val; - void __iomem *base = phy->regs; - struct tegra_ulpi_config *config = phy->config; - - /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB - * Controller to immediately bring the ULPI PHY out of low power - */ - val = readl(base + USB_PORTSC1); - val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN); - writel(val, base + USB_PORTSC1); - - gpio_direction_output(config->reset_gpio, 0); - clk_disable(phy->clk); -} - -struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, - void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode) -{ - struct tegra_usb_phy *phy; - struct tegra_ulpi_config *ulpi_config; - unsigned long parent_rate; - int i; - int err; - - phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); - if (!phy) - return ERR_PTR(-ENOMEM); - - phy->instance = instance; - phy->regs = regs; - phy->config = config; - phy->mode = phy_mode; - - if (!phy->config) { - if (phy_is_ulpi(phy)) { - pr_err("%s: ulpi phy configuration missing", __func__); - err = -EINVAL; - goto err0; - } else { - phy->config = &utmip_default[instance]; - } - } - - phy->pll_u = clk_get_sys(NULL, "pll_u"); - if (IS_ERR(phy->pll_u)) { - pr_err("Can't get pll_u clock\n"); - err = PTR_ERR(phy->pll_u); - goto err0; - } - clk_prepare_enable(phy->pll_u); - - parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); - for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { - if (tegra_freq_table[i].freq == parent_rate) { - phy->freq = &tegra_freq_table[i]; - break; - } - } - if (!phy->freq) { - pr_err("invalid pll_u parent rate %ld\n", parent_rate); - err = -EINVAL; - goto err1; - } - - if (phy_is_ulpi(phy)) { - ulpi_config = config; - phy->clk = clk_get_sys(NULL, ulpi_config->clk); - if (IS_ERR(phy->clk)) { - pr_err("%s: can't get ulpi clock\n", __func__); - err = -ENXIO; - goto err1; - } - if (!gpio_is_valid(ulpi_config->reset_gpio)) - ulpi_config->reset_gpio = - of_get_named_gpio(dev->of_node, - "nvidia,phy-reset-gpio", 0); - if (!gpio_is_valid(ulpi_config->reset_gpio)) { - pr_err("%s: invalid reset gpio: %d\n", __func__, - ulpi_config->reset_gpio); - err = -EINVAL; - goto err1; - } - gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); - gpio_direction_output(ulpi_config->reset_gpio, 0); - phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); - phy->ulpi->io_priv = regs + ULPI_VIEWPORT; - } else { - err = utmip_pad_open(phy); - if (err < 0) - goto err1; - } - - return phy; - -err1: - clk_disable_unprepare(phy->pll_u); - clk_put(phy->pll_u); -err0: - kfree(phy); - return ERR_PTR(err); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_open); - -int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) -{ - if (phy_is_ulpi(phy)) - return ulpi_phy_power_on(phy); - else - return utmi_phy_power_on(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on); - -void tegra_usb_phy_power_off(struct tegra_usb_phy *phy) -{ - if (phy_is_ulpi(phy)) - ulpi_phy_power_off(phy); - else - utmi_phy_power_off(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off); - -void tegra_usb_phy_preresume(struct tegra_usb_phy *phy) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_preresume(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); - -void tegra_usb_phy_postresume(struct tegra_usb_phy *phy) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_postresume(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); - -void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, - enum tegra_usb_phy_port_speed port_speed) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_restore_start(phy, port_speed); -} -EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); - -void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_restore_end(phy); -} -EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); - -void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_clk_disable(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable); - -void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy) -{ - if (!phy_is_ulpi(phy)) - utmi_phy_clk_enable(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable); - -void tegra_usb_phy_close(struct tegra_usb_phy *phy) -{ - if (phy_is_ulpi(phy)) - clk_put(phy->clk); - else - utmip_pad_close(phy); - clk_disable_unprepare(phy->pll_u); - clk_put(phy->pll_u); - kfree(phy); -} -EXPORT_SYMBOL_GPL(tegra_usb_phy_close); diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 54d8f34fdee5..f7e12ede008c 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -1,6 +1,6 @@ if ARCH_U300 -menu "ST-Ericsson AB U300/U330/U335/U365 Platform" +menu "ST-Ericsson AB U300/U335 Platform" comment "ST-Ericsson Mobile Platform Products" @@ -10,46 +10,7 @@ config MACH_U300 select PINCTRL_U300 select PINCTRL_COH901 -comment "ST-Ericsson U300/U330/U335/U365 Feature Selections" - -choice - prompt "U300/U330/U335/U365 system type" - default MACH_U300_BS2X - ---help--- - You need to select the target system, i.e. the - U300/U330/U335/U365 board that you want to compile your kernel - for. - -config MACH_U300_BS2X - bool "S26/S26/B25/B26 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S26/S25 test products. (Also works on - B26/B25 big boards.) - -config MACH_U300_BS330 - bool "S330/B330 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S330/B330 test products. - -config MACH_U300_BS335 - bool "S335/B335 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S335/B335 test products. - -config MACH_U300_BS365 - bool "S365/B365 Test Products" - depends on MACH_U300 - help - Select this if you're developing on the - S365/B365 test products. - -endchoice +comment "ST-Ericsson U300/U335 Feature Selections" config U300_DEBUG bool "Debug support for U300" diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 7e47d37aeb0e..5a86c58da396 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -7,7 +7,6 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_ARCH_U300) += u300.o obj-$(CONFIG_SPI_PL022) += spi.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o obj-$(CONFIG_I2C_STU300) += i2c.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 03acf1883ec7..ef6f602b7e48 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -3,7 +3,7 @@ * arch/arm/mach-u300/core.c * * - * Copyright (C) 2007-2010 ST-Ericsson SA + * Copyright (C) 2007-2012 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * Core platform support, IRQ handling and device definitions. * Author: Linus Walleij <linus.walleij@stericsson.com> @@ -31,23 +31,26 @@ #include <linux/pinctrl/pinconf-generic.h> #include <linux/dma-mapping.h> #include <linux/platform_data/clk-u300.h> +#include <linux/platform_data/pinctrl-coh901.h> #include <asm/types.h> #include <asm/setup.h> #include <asm/memory.h> #include <asm/hardware/vic.h> #include <asm/mach/map.h> -#include <asm/mach/irq.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> #include <mach/coh901318.h> #include <mach/hardware.h> #include <mach/syscon.h> -#include <mach/dma_channels.h> -#include <mach/gpio-u300.h> +#include <mach/irqs.h> +#include "timer.h" #include "spi.h" #include "i2c.h" #include "u300-gpio.h" +#include "dma_channels.h" /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = { }, }; -void __init u300_map_io(void) +static void __init u300_map_io(void) { iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); /* We enable a real big DMA buffer if need be. */ @@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE, { IRQ_U300_UART0 }, &uart0_plat_data); /* The U335 have an additional UART1 on the APP CPU */ -#ifdef CONFIG_MACH_U300_BS335 static struct amba_pl011_data uart1_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, @@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = { /* Fast device at 0x7000 offset */ static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE, { IRQ_U300_UART1 }, &uart1_plat_data); -#endif /* AHB device at 0x4000 offset */ static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL); @@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE, */ static struct amba_device *amba_devs[] __initdata = { &uart0_device, -#ifdef CONFIG_MACH_U300_BS335 &uart1_device, -#endif &pl022_device, &pl172_device, &mmcsd_device, @@ -188,7 +187,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT2, .flags = IORESOURCE_IRQ, }, -#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335) { .name = "gpio3", .start = IRQ_U300_GPIO_PORT3, @@ -201,8 +199,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT4, .flags = IORESOURCE_IRQ, }, -#endif -#ifdef CONFIG_MACH_U300_BS335 { .name = "gpio5", .start = IRQ_U300_GPIO_PORT5, @@ -215,7 +211,6 @@ static struct resource gpio_resources[] = { .end = IRQ_U300_GPIO_PORT6, .flags = IORESOURCE_IRQ, }, -#endif /* CONFIG_MACH_U300_BS335 */ }; static struct resource keypad_resources[] = { @@ -323,7 +318,6 @@ static struct resource dma_resource[] = { } }; -#ifdef CONFIG_MACH_U300_BS335 /* points out all dma slave channels. * Syntax is [A1, B1, A2, B2, .... ,-1,-1] * Select all channels from A to B, end of list is marked with -1,-1 @@ -336,14 +330,6 @@ static int dma_slave_channels[] = { static int dma_memcpy_channels[] = { U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; -#else /* CONFIG_MACH_U300_BS335 */ - -static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1}; -static int dma_memcpy_channels[] = { - U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1}; - -#endif - /** register dma for memory access * * active 1 means dma intends to access memory @@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .param.ctrl_lli = flags_memcpy_lli, .param.ctrl_lli_last = flags_memcpy_lli_last, }, -#ifdef CONFIG_MACH_U300_BS335 { .number = U300_DMA_UART1_TX, .name = "UART1 TX", @@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "UART1 RX", .priority_high = 0, } -#else - { - .number = U300_DMA_GENERAL_PURPOSE_9, - .name = "GENERAL 09", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - }, - { - .number = U300_DMA_GENERAL_PURPOSE_10, - .name = "GENERAL 10", - .priority_high = 0, - - .param.config = flags_memcpy_config, - .param.ctrl_lli_chained = flags_memcpy_lli_chained, - .param.ctrl_lli = flags_memcpy_lli, - .param.ctrl_lli_last = flags_memcpy_lli_last, - } -#endif }; @@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = { * GPIO block, with different number of ports. */ static struct u300_gpio_platform u300_gpio_plat = { -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) - .variant = U300_GPIO_COH901335, - .ports = 3, -#endif -#ifdef CONFIG_MACH_U300_BS335 - .variant = U300_GPIO_COH901571_3_BS335, .ports = 7, -#endif -#ifdef CONFIG_MACH_U300_BS365 - .variant = U300_GPIO_COH901571_3_BS365, - .ports = 5, -#endif .gpio_base = 0, .gpio_irq_base = IRQ_U300_GPIO_BASE, .pinctrl_device = &pinctrl_device, @@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = { * together so some interrupts are connected to the first one and some * to the second one. */ -void __init u300_init_irq(void) +static void __init u300_init_irq(void) { u32 mask[2] = {0, 0}; struct clk *clk; @@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void) printk(KERN_INFO "Initializing U300 system on %s baseband chip " \ "(chip ID 0x%04x)\n", chipname, val); -#ifdef CONFIG_MACH_U300_BS330 - if ((val & 0xFF00U) != 0xd800) { - printk(KERN_ERR "Platform configured for BS330 " \ - "with DB3200 but %s detected, expect problems!", - chipname); - } -#endif -#ifdef CONFIG_MACH_U300_BS335 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { printk(KERN_ERR "Platform configured for BS335 " \ " with DB3350 but %s detected, expect problems!", chipname); } -#endif -#ifdef CONFIG_MACH_U300_BS365 - if ((val & 0xFF00U) != 0xe800) { - printk(KERN_ERR "Platform configured for BS365 " \ - "with DB3210 but %s detected, expect problems!", - chipname); - } -#endif - - } /* @@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void) } } -void __init u300_init_devices(void) +static void __init u300_init_machine(void) { int i; u16 val; @@ -1852,7 +1786,7 @@ void __init u300_init_devices(void) /* Forward declare this function from the watchdog */ void coh901327_watchdog_reset(void); -void u300_restart(char mode, const char *cmd) +static void u300_restart(char mode, const char *cmd) { switch (mode) { case 's': @@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd) /* Wait for system do die/reset. */ while (1); } + +MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") + /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ + .atag_offset = 0x100, + .map_io = u300_map_io, + .nr_irqs = NR_IRQS_U300, + .init_irq = u300_init_irq, + .handle_irq = vic_handle_irq, + .timer = &u300_timer, + .init_machine = u300_init_machine, + .restart = u300_restart, +MACHINE_END diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h index b239149ba0d0..4e8a88fbca49 100644 --- a/arch/arm/mach-u300/include/mach/dma_channels.h +++ b/arch/arm/mach-u300/dma_channels.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/dma_channels.h * * - * Copyright (C) 2007-2009 ST-Ericsson + * Copyright (C) 2007-2012 ST-Ericsson * License terms: GNU General Public License (GPL) version 2 * Map file for the U300 dma driver. * Author: Per Friden <per.friden@stericsson.com> @@ -50,19 +50,10 @@ #define U300_DMA_GENERAL_PURPOSE_6 35 #define U300_DMA_GENERAL_PURPOSE_7 36 #define U300_DMA_GENERAL_PURPOSE_8 37 -#ifdef CONFIG_MACH_U300_BS335 #define U300_DMA_UART1_TX 38 #define U300_DMA_UART1_RX 39 -#else -#define U300_DMA_GENERAL_PURPOSE_9 38 -#define U300_DMA_GENERAL_PURPOSE_10 39 -#endif -#ifdef CONFIG_MACH_U300_BS335 #define U300_DMA_DEVICE_CHANNELS 32 -#else -#define U300_DMA_DEVICE_CHANNELS 30 -#endif #define U300_DMA_CHANNELS 40 diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index cb04bd6ab3e7..0d4620ed853c 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-u300/i2c.c * - * Copyright (C) 2009 ST-Ericsson AB + * Copyright (C) 2009-2012 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * * Register board i2c devices @@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = { }; static struct i2c_board_info __initdata bus1_i2c_board_info[] = { -#ifdef CONFIG_MACH_U300_BS335 { .type = "fwcam", .addr = 0x10, @@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = { .type = "fwcam", .addr = 0x5d, }, -#else - { }, -#endif }; void __init u300_i2c_register_board_devices(void) diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h deleted file mode 100644 index 92e3cc872c66..000000000000 --- a/arch/arm/mach-u300/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H -#define __MACH_CLKDEV_H - -int __clk_get(struct clk *clk); -void __clk_put(struct clk *clk); - -#endif diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h deleted file mode 100644 index e81400c1753a..000000000000 --- a/arch/arm/mach-u300/include/mach/gpio-u300.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2007-2011 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * GPIO block resgister definitions and inline macros for - * U300 GPIO COH 901 335 or COH 901 571/3 - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_U300_GPIO_U300_H -#define __MACH_U300_GPIO_U300_H - -/** - * enum u300_gpio_variant - the type of U300 GPIO employed - */ -enum u300_gpio_variant { - U300_GPIO_COH901335, - U300_GPIO_COH901571_3_BS335, - U300_GPIO_COH901571_3_BS365, -}; - -/** - * struct u300_gpio_platform - U300 GPIO platform data - * @variant: IP block variant - * @ports: number of GPIO block ports - * @gpio_base: first GPIO number for this block (use a free range) - * @gpio_irq_base: first GPIO IRQ number for this block (use a free range) - * @pinctrl_device: pin control device to spawn as child - */ -struct u300_gpio_platform { - enum u300_gpio_variant variant; - u8 ports; - int gpio_base; - int gpio_irq_base; - struct platform_device *pinctrl_device; -}; - -#endif /* __MACH_U300_GPIO_U300_H */ diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index ec09c1e07b1a..e27425a63fa1 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/irqs.h * * - * Copyright (C) 2006-2009 ST-Ericsson AB + * Copyright (C) 2006-2012 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * IRQ channel definitions for the U300 platforms. * Author: Linus Walleij <linus.walleij@stericsson.com> @@ -31,10 +31,6 @@ #define IRQ_U300_XGAM_GAMCON 14 #define IRQ_U300_XGAM_CDI 15 #define IRQ_U300_XGAM_CDICON 16 -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -/* MMIACC not used on the DB3210 or DB3350 chips */ -#define IRQ_U300_XGAM_MMIACC 17 -#endif #define IRQ_U300_XGAM_PDI 18 #define IRQ_U300_XGAM_PDICON 19 #define IRQ_U300_XGAM_GAMEACC 20 @@ -55,8 +51,6 @@ #define IRQ_U300_GPIO_PORT1 34 #define IRQ_U300_GPIO_PORT2 35 -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ - defined(CONFIG_MACH_U300_BS335) /* These are for DB3150, DB3200 and DB3350 */ #define IRQ_U300_WDOG 36 #define IRQ_U300_EVHIST 37 @@ -68,15 +62,8 @@ #define IRQ_U300_RTC 43 #define IRQ_U300_NFIF 44 #define IRQ_U300_NFIF2 45 -#endif - -/* DB3150 and DB3200 have only 45 IRQs */ -#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -#define U300_VIC_IRQS_END 46 -#endif /* The DB3350-specific interrupt lines */ -#ifdef CONFIG_MACH_U300_BS335 #define IRQ_U300_ISP_F0 46 #define IRQ_U300_ISP_F1 47 #define IRQ_U300_ISP_F2 48 @@ -89,25 +76,6 @@ #define IRQ_U300_GPIO_PORT5 55 #define IRQ_U300_GPIO_PORT6 56 #define U300_VIC_IRQS_END 57 -#endif - -/* The DB3210-specific interrupt lines */ -#ifdef CONFIG_MACH_U300_BS365 -#define IRQ_U300_GPIO_PORT3 36 -#define IRQ_U300_GPIO_PORT4 37 -#define IRQ_U300_WDOG 38 -#define IRQ_U300_EVHIST 39 -#define IRQ_U300_MSPRO 40 -#define IRQ_U300_MMCSD_MCIINTR0 41 -#define IRQ_U300_MMCSD_MCIINTR1 42 -#define IRQ_U300_I2C0 43 -#define IRQ_U300_I2C1 44 -#define IRQ_U300_RTC 45 -#define IRQ_U300_NFIF 46 -#define IRQ_U300_NFIF2 47 -#define IRQ_U300_SYSCON_PLL_LOCK 48 -#define U300_VIC_IRQS_END 49 -#endif /* Maximum 8*7 GPIO lines */ #ifdef CONFIG_PINCTRL_COH901 @@ -117,6 +85,6 @@ #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #endif -#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) +#define NR_IRQS_U300 (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) #endif diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h deleted file mode 100644 index 096333f32fc3..000000000000 --- a/arch/arm/mach-u300/include/mach/platform.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/platform.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Basic platform init and mapping functions. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __ASSEMBLY__ - -void u300_map_io(void); -void u300_init_irq(void); -void u300_init_devices(void); -void u300_restart(char, const char *); -extern struct sys_timer u300_timer; - -#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h index 6e84f07a7c6f..10bdd0be9774 100644 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -3,7 +3,7 @@ * arch/arm/mach-u300/include/mach/syscon.h * * - * Copyright (C) 2008 ST-Ericsson AB + * Copyright (C) 2008-2012 ST-Ericsson AB * * Author: Rickard Andersson <rickard.andersson@stericsson.com> */ @@ -36,9 +36,7 @@ #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) /* Reset lines for SLOW devices 16bit (R/W) */ #define U300_SYSCON_RSR (0x0014) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#endif #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) @@ -50,9 +48,7 @@ #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) /* Reset lines for FAST devices 16bit (R/W) */ #define U300_SYSCON_RFR (0x0018) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#endif #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) @@ -62,10 +58,8 @@ #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) /* Reset lines for the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_RRR (0x001c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#endif #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) @@ -79,9 +73,7 @@ #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) /* Clock enable for SLOW peripherals 16bit (R/W) */ #define U300_SYSCON_CESR (0x0020) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#endif #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) @@ -92,24 +84,20 @@ #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) /* Clock enable for FAST peripherals 16bit (R/W) */ #define U300_SYSCON_CEFR (0x0024) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#endif #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) +#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) +#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) +#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) +#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) /* Clock enable for the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_CERR (0x0028) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#endif #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) @@ -124,9 +112,7 @@ #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) /* Single block clock enable 16bit (-/W) */ #define U300_SYSCON_SBCER (0x002c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#endif #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) @@ -135,9 +121,7 @@ #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#endif #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) @@ -147,10 +131,8 @@ #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#endif #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) @@ -168,9 +150,7 @@ /* Same values as above for SBCER */ /* Clock force SLOW peripherals 16bit (R/W) */ #define U300_SYSCON_CFSR (0x003c) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#endif #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) @@ -184,10 +164,8 @@ /* Values not defined. Define if you want to use them. */ /* Clock force the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_CFRR (0x44) -#ifdef CONFIG_MACH_U300_BS335 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#endif #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h index 65f87c523892..1e49d901f2c9 100644 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -28,7 +28,6 @@ #define PLAT_NAND_CLE (1 << 16) #define PLAT_NAND_ALE (1 << 17) - /* AHB Peripherals */ #define U300_AHB_PER_PHYS_BASE 0xa0000000 #define U300_AHB_PER_VIRT_BASE 0xff010000 @@ -46,11 +45,7 @@ #define U300_BOOTROM_VIRT_BASE 0xffff0000 /* SEMI config base */ -#ifdef CONFIG_MACH_U300_BS335 #define U300_SEMI_CONFIG_BASE 0x2FFE0000 -#else -#define U300_SEMI_CONFIG_BASE 0x30000000 -#endif /* * AHB peripherals @@ -99,10 +94,8 @@ /* SPI controller */ #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) -#ifdef CONFIG_MACH_U300_BS335 /* Fast UART1 on U335 only */ #define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) -#endif /* * SLOW peripherals @@ -151,10 +144,8 @@ * REST peripherals */ -/* ISP (image signal processor) is only available in U335 */ -#ifdef CONFIG_MACH_U300_BS335 +/* ISP (image signal processor) */ #define U300_ISP_BASE (0xA0008000) -#endif /* DMA Controller base */ #define U300_DMAC_BASE (0xC0020000) @@ -166,17 +157,9 @@ #define U300_APEX_BASE (0xc0030000) /* Video Encoder Base */ -#ifdef CONFIG_MACH_U300_BS335 #define U300_VIDEOENC_BASE (0xc0080000) -#else -#define U300_VIDEOENC_BASE (0xc0040000) -#endif /* XGAM Base */ #define U300_XGAM_BASE (0xd0000000) -/* - * Virtual accessor macros for static devices - */ - #endif diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index a1affacfa59c..02e6659286d5 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c @@ -12,7 +12,7 @@ #include <linux/amba/pl022.h> #include <linux/err.h> #include <mach/coh901318.h> -#include <mach/dma_channels.h> +#include "dma_channels.h" /* * The following is for the actual devices on the SSP/SPI bus diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 56ac06d38ec1..1da10e20e996 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -17,14 +17,17 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/irq.h> #include <mach/hardware.h> +#include <mach/irqs.h> /* Generic stuff */ #include <asm/sched_clock.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/mach/irq.h> + +#include "timer.h" /* * APP side special timer registers diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h new file mode 100644 index 000000000000..b5e9791762e0 --- /dev/null +++ b/arch/arm/mach-u300/timer.h @@ -0,0 +1 @@ +extern struct sys_timer u300_timer; diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h index 847dc25300c6..83f50772e169 100644 --- a/arch/arm/mach-u300/u300-gpio.h +++ b/arch/arm/mach-u300/u300-gpio.h @@ -1,50 +1,11 @@ /* - * Individual pin assignments for the B26/S26. Notice that the - * actual usage of these pins depends on the PAD MUX settings, that - * is why the same number can potentially appear several times. - * In the reference design each pin is only used for one purpose. - * These were determined by inspecting the B26/S26 schematic: - * 2/1911-ROA 128 1603 - */ -#ifdef CONFIG_MACH_U300_BS2X -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */ -#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */ -#define U300_GPIO_PIN_CAM_SLEEP 4 -#define U300_GPIO_PIN_CAM_REG_EN 5 -#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */ -#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */ -#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */ -#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */ -#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */ -#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */ -#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */ -#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ -#endif - -/* - * Individual pin assignments for the B330/S330 and B365/S365. + * Individual pin assignments for the B335/S335. * Notice that the actual usage of these pins depends on the * PAD MUX settings, that is why the same number can potentially * appear several times. In the reference design each pin is only * used for one purpose. These were determined by inspecting the * S365 schematic. */ -#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \ - defined(CONFIG_MACH_U300_BS335) #define U300_GPIO_PIN_UART_RX 0 #define U300_GPIO_PIN_UART_TX 1 #define U300_GPIO_PIN_UART_CTS 2 @@ -90,8 +51,6 @@ #define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ #define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ -#ifdef CONFIG_MACH_U300_BS335 - #define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ #define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ #define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ @@ -109,6 +68,3 @@ #define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ #define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ #define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ -#endif - -#endif diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c deleted file mode 100644 index f30c69d91d99..000000000000 --- a/arch/arm/mach-u300/u300.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * - * arch/arm/mach-u300/u300.c - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Platform machine definition. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/memblock.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/platform.h> -#include <asm/hardware/vic.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/memory.h> - -static void __init u300_init_machine(void) -{ - u300_init_devices(); -} - -#ifdef CONFIG_MACH_U300_BS2X -#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS330 -#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS335 -#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board" -#endif - -#ifdef CONFIG_MACH_U300_BS365 -#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board" -#endif - -MACHINE_START(U300, MACH_U300_STRING) - /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ - .atag_offset = 0x100, - .map_io = u300_map_io, - .init_irq = u300_init_irq, - .handle_irq = vic_handle_irq, - .timer = &u300_timer, - .init_machine = u300_init_machine, - .restart = u300_restart, -MACHINE_END diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 53d3d46dec12..c77c86c47369 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -11,6 +11,7 @@ config UX500_SOC_COMMON select CACHE_L2X0 select PINCTRL select PINCTRL_NOMADIK + select COMMON_CLK config UX500_SOC_DB8500 bool @@ -28,6 +29,7 @@ config MACH_MOP500 select I2C select I2C_NOMADIK select SOC_BUS + select REGULATOR_FIXED_VOLTAGE help Include support for the MOP500 development platform. diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 026086ff9e6c..f24710dfc395 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := clock.o cpu.o devices.o devices-common.o \ +obj-y := cpu.o devices.o devices-common.o \ id.o usb.o timer.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o @@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ board-mop500-pins.o \ - board-mop500-msp.o + board-mop500-audio.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c index df15646036aa..070629a95625 100644 --- a/arch/arm/mach-ux500/board-mop500-msp.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -7,7 +7,6 @@ #include <linux/platform_device.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/pinctrl/consumer.h> #include <plat/gpio-nomadik.h> #include <plat/pincfg.h> @@ -23,53 +22,6 @@ #include "devices-db8500.h" #include "pins-db8500.h" -/* MSP1/3 Tx/Rx usage protection */ -static DEFINE_SPINLOCK(msp_rxtx_lock); - -/* Reference Count */ -static int msp_rxtx_ref; - -/* Pin modes */ -struct pinctrl *msp1_p; -struct pinctrl_state *msp1_def; -struct pinctrl_state *msp1_sleep; - -int msp13_i2s_init(void) -{ - int retval = 0; - unsigned long flags; - - spin_lock_irqsave(&msp_rxtx_lock, flags); - if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) { - retval = pinctrl_select_state(msp1_p, msp1_def); - if (retval) - pr_err("could not set MSP1 defstate\n"); - } - if (!retval) - msp_rxtx_ref++; - spin_unlock_irqrestore(&msp_rxtx_lock, flags); - - return retval; -} - -int msp13_i2s_exit(void) -{ - int retval = 0; - unsigned long flags; - - spin_lock_irqsave(&msp_rxtx_lock, flags); - WARN_ON(!msp_rxtx_ref); - msp_rxtx_ref--; - if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) { - retval = pinctrl_select_state(msp1_p, msp1_sleep); - if (retval) - pr_err("could not set MSP1 sleepstate\n"); - } - spin_unlock_irqrestore(&msp_rxtx_lock, flags); - - return retval; -} - static struct stedma40_chan_cfg msp0_dma_rx = { .high_priority = true, .dir = STEDMA40_PERIPH_TO_MEM, @@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = { /* data_width is set during configuration */ }; -static struct msp_i2s_platform_data msp0_platform_data = { +struct msp_i2s_platform_data msp0_platform_data = { .id = MSP_I2S_0, .msp_i2s_dma_rx = &msp0_dma_rx, .msp_i2s_dma_tx = &msp0_dma_tx, @@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = { /* data_width is set during configuration */ }; -static struct msp_i2s_platform_data msp1_platform_data = { +struct msp_i2s_platform_data msp1_platform_data = { .id = MSP_I2S_1, .msp_i2s_dma_rx = NULL, .msp_i2s_dma_tx = &msp1_dma_tx, - .msp_i2s_init = msp13_i2s_init, - .msp_i2s_exit = msp13_i2s_exit, }; static struct stedma40_chan_cfg msp2_dma_rx = { @@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent, /* Platform device for ASoC MOP500 machine */ static struct platform_device snd_soc_mop500 = { - .name = "snd-soc-mop500", - .id = 0, - .dev = { - .platform_data = NULL, - }, + .name = "snd-soc-mop500", + .id = 0, + .dev = { + .platform_data = NULL, + }, }; /* Platform device for Ux500-PCM */ @@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = { }, }; -static struct msp_i2s_platform_data msp2_platform_data = { +struct msp_i2s_platform_data msp2_platform_data = { .id = MSP_I2S_2, .msp_i2s_dma_rx = &msp2_dma_rx, .msp_i2s_dma_tx = &msp2_dma_tx, }; -static struct msp_i2s_platform_data msp3_platform_data = { +struct msp_i2s_platform_data msp3_platform_data = { .id = MSP_I2S_3, .msp_i2s_dma_rx = &msp1_dma_rx, .msp_i2s_dma_tx = NULL, - .msp_i2s_init = msp13_i2s_init, - .msp_i2s_exit = msp13_i2s_exit, }; -int mop500_msp_init(struct device *parent) +void mop500_audio_init(struct device *parent) { - struct platform_device *msp1; - pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); platform_device_register(&snd_soc_mop500); pr_info("Initialize MSP I2S-devices.\n"); db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, &msp0_platform_data); - msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, + db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, &msp1_platform_data); db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, &msp2_platform_data); db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, &msp3_platform_data); +} - /* Get the pinctrl handle for MSP1 */ - if (msp1) { - msp1_p = pinctrl_get(&msp1->dev); - if (IS_ERR(msp1_p)) - dev_err(&msp1->dev, "could not get MSP1 pinctrl\n"); - else { - msp1_def = pinctrl_lookup_state(msp1_p, - PINCTRL_STATE_DEFAULT); - if (IS_ERR(msp1_def)) { - dev_err(&msp1->dev, - "could not get MSP1 defstate\n"); - } - msp1_sleep = pinctrl_lookup_state(msp1_p, - PINCTRL_STATE_SLEEP); - if (IS_ERR(msp1_sleep)) - dev_err(&msp1->dev, - "could not get MSP1 idlestate\n"); - } - } - +/* Due for removal once the MSP driver has been fully DT:ed. */ +void mop500_of_audio_init(struct device *parent) +{ pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); platform_device_register(&ux500_pcm); - - return 0; } diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h deleted file mode 100644 index 6fcfb5e2cc94..000000000000 --- a/arch/arm/mach-ux500/board-mop500-msp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2012 - * - * Author: Ola Lilja <ola.o.lilja@stericsson.com>, - * for ST-Ericsson. - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -void mop500_msp_init(struct device *parent); diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 52426a425787..2a17bc506cff 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -13,6 +13,21 @@ #include <linux/regulator/ab8500.h> #include "board-mop500-regulators.h" +static struct regulator_consumer_supply gpio_en_3v3_consumers[] = { + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +struct regulator_init_data gpio_en_3v3_regulator = { + .constraints = { + .name = "EN-3V3", + .min_uV = 3300000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers), + .consumer_supplies = gpio_en_3v3_consumers, +}; + /* * TPS61052 regulator */ diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 94992158d962..78a0642a2206 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -18,5 +18,6 @@ extern struct ab8500_regulator_reg_init ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; extern struct regulator_init_data tps61052_regulator; +extern struct regulator_init_data gpio_en_3v3_regulator; #endif diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 18ff781cfbe4..9c8e4a9e83ee 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi1_data = { +struct mmci_platform_data mop500_sdi1_data = { .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA, @@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi2_data = { +struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index a534d8880de1..074791306c99 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -23,6 +23,7 @@ #include <linux/spi/spi.h> #include <linux/mfd/abx500/ab8500.h> #include <linux/regulator/ab8500.h> +#include <linux/regulator/fixed.h> #include <linux/mfd/tc3589x.h> #include <linux/mfd/tps6105x.h> #include <linux/mfd/abx500/ab8500-gpio.h> @@ -54,7 +55,6 @@ #include "devices-db8500.h" #include "board-mop500.h" #include "board-mop500-regulators.h" -#include "board-mop500-msp.h" static struct gpio_led snowball_led_array[] = { { @@ -76,6 +76,23 @@ static struct platform_device snowball_led_dev = { }, }; +static struct fixed_voltage_config snowball_gpio_en_3v3_data = { + .supply_name = "EN-3V3", + .gpio = SNOWBALL_EN_3V3_ETH_GPIO, + .microvolts = 3300000, + .enable_high = 1, + .init_data = &gpio_en_3v3_regulator, + .startup_delay = 5000, /* 1200us */ +}; + +static struct platform_device snowball_gpio_en_3v3_regulator_dev = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &snowball_gpio_en_3v3_data, + }, +}; + static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { .gpio_base = MOP500_AB8500_PIN_GPIO(1), .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, @@ -524,33 +541,12 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = { }; #endif -#define PRCC_K_SOFTRST_SET 0x18 -#define PRCC_K_SOFTRST_CLEAR 0x1C -static void ux500_uart0_reset(void) -{ - void __iomem *prcc_rst_set, *prcc_rst_clr; - - prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + - PRCC_K_SOFTRST_SET); - prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE + - PRCC_K_SOFTRST_CLEAR); - - /* Activate soft reset PRCC_K_SOFTRST_CLEAR */ - writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr); - udelay(1); - - /* Release soft reset PRCC_K_SOFTRST_SET */ - writel((readl(prcc_rst_set) | 0x1), prcc_rst_set); - udelay(1); -} - static struct amba_pl011_data uart0_plat = { #ifdef CONFIG_STE_DMA40 .dma_filter = stedma40_filter, .dma_rx_param = &uart0_dma_cfg_rx, .dma_tx_param = &uart0_dma_cfg_tx, #endif - .reset = ux500_uart0_reset, }; static struct amba_pl011_data uart1_plat = { @@ -586,6 +582,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = { &snowball_led_dev, &snowball_key_dev, &snowball_sbnet_dev, + &snowball_gpio_en_3v3_regulator_dev, }; static void __init mop500_init_machine(void) @@ -608,7 +605,7 @@ static void __init mop500_init_machine(void) mop500_i2c_init(parent); mop500_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); + mop500_audio_init(parent); mop500_uart_init(parent); u8500_cryp1_hash1_init(parent); @@ -642,7 +639,7 @@ static void __init snowball_init_machine(void) mop500_i2c_init(parent); snowball_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); + mop500_audio_init(parent); mop500_uart_init(parent); /* This board has full regulator constraints */ @@ -674,7 +671,7 @@ static void __init hrefv60_init_machine(void) mop500_i2c_init(parent); hrefv60_sdi_init(parent); mop500_spi_init(parent); - mop500_msp_init(parent); + mop500_audio_init(parent); mop500_uart_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); @@ -726,12 +723,9 @@ MACHINE_END #ifdef CONFIG_MACH_UX500_DT -static struct platform_device *snowball_of_platform_devs[] __initdata = { - &snowball_led_dev, - &snowball_key_dev, -}; - struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { + /* Requires call-back bindings. */ + OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), /* Requires DMA and call-back bindings. */ OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), @@ -739,6 +733,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), /* Requires clock name bindings. */ OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), @@ -757,6 +753,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), + /* Requires clock name and DMA bindings. */ + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, + "ux500-msp-i2s.0", &msp0_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, + "ux500-msp-i2s.1", &msp1_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, + "ux500-msp-i2s.2", &msp2_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, + "ux500-msp-i2s.3", &msp3_platform_data), {}, }; @@ -797,7 +802,7 @@ static void __init u8500_init_machine(void) ARRAY_SIZE(mop500_platform_devs)); mop500_sdi_init(parent); - mop500_msp_init(parent); + mop500_audio_init(parent); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, @@ -806,7 +811,7 @@ static void __init u8500_init_machine(void) mop500_uib_init(); } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - mop500_msp_init(parent); + mop500_of_audio_init(parent); } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { /* * The HREFv60 board removed a GPIO expander and routed @@ -817,16 +822,6 @@ static void __init u8500_init_machine(void) platform_add_devices(mop500_platform_devs, ARRAY_SIZE(mop500_platform_devs)); - hrefv60_sdi_init(parent); - mop500_msp_init(parent); - - i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); - i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; - - i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); - i2c_register_board_info(2, mop500_i2c2_devices, - ARRAY_SIZE(mop500_i2c2_devices)); - mop500_uib_init(); } diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index b5bfc1a78b1a..aca39a68712a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -9,6 +9,7 @@ /* For NOMADIK_NR_GPIO */ #include <mach/irqs.h> +#include <mach/msp.h> #include <linux/amba/mmci.h> /* Snowball specific GPIO assignments, this board has no GPIO expander */ @@ -80,7 +81,14 @@ struct device; struct i2c_board_info; extern struct mmci_platform_data mop500_sdi0_data; +extern struct mmci_platform_data mop500_sdi1_data; +extern struct mmci_platform_data mop500_sdi2_data; extern struct mmci_platform_data mop500_sdi4_data; +extern struct msp_i2s_platform_data msp0_platform_data; +extern struct msp_i2s_platform_data msp1_platform_data; +extern struct msp_i2s_platform_data msp2_platform_data; +extern struct msp_i2s_platform_data msp3_platform_data; +extern struct arm_pmu_platdata db8500_pmu_platdata; extern void mop500_sdi_init(struct device *parent); extern void snowball_sdi_init(struct device *parent); @@ -91,6 +99,9 @@ void __init mop500_stuib_init(void); void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); void __init hrefv60_pinmaps_init(void); +void mop500_audio_init(struct device *parent); +/* Due for removal once the MSP driver has been fully DT:ed. */ +void mop500_of_audio_init(struct device *parent); int __init mop500_uib_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index dc12394295d5..75d5b512a3d5 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -38,7 +38,7 @@ static int __init ux500_l2x0_init(void) { u32 aux_val = 0x3e000000; - if (cpu_is_u8500_family()) + if (cpu_is_u8500_family() || cpu_is_ux540_family()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c deleted file mode 100644 index 8d73b066a18d..000000000000 --- a/arch/arm/mach-ux500/clock.c +++ /dev/null @@ -1,715 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * Copyright (C) 2009 STMicroelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/cpufreq.h> - -#include <plat/mtu.h> -#include <mach/hardware.h> -#include "clock.h" - -#ifdef CONFIG_DEBUG_FS -#include <linux/debugfs.h> -#include <linux/uaccess.h> /* for copy_from_user */ -static LIST_HEAD(clk_list); -#endif - -#define PRCC_PCKEN 0x00 -#define PRCC_PCKDIS 0x04 -#define PRCC_KCKEN 0x08 -#define PRCC_KCKDIS 0x0C - -#define PRCM_YYCLKEN0_MGT_SET 0x510 -#define PRCM_YYCLKEN1_MGT_SET 0x514 -#define PRCM_YYCLKEN0_MGT_CLR 0x518 -#define PRCM_YYCLKEN1_MGT_CLR 0x51C -#define PRCM_YYCLKEN0_MGT_VAL 0x520 -#define PRCM_YYCLKEN1_MGT_VAL 0x524 - -#define PRCM_SVAMMDSPCLK_MGT 0x008 -#define PRCM_SIAMMDSPCLK_MGT 0x00C -#define PRCM_SGACLK_MGT 0x014 -#define PRCM_UARTCLK_MGT 0x018 -#define PRCM_MSP02CLK_MGT 0x01C -#define PRCM_MSP1CLK_MGT 0x288 -#define PRCM_I2CCLK_MGT 0x020 -#define PRCM_SDMMCCLK_MGT 0x024 -#define PRCM_SLIMCLK_MGT 0x028 -#define PRCM_PER1CLK_MGT 0x02C -#define PRCM_PER2CLK_MGT 0x030 -#define PRCM_PER3CLK_MGT 0x034 -#define PRCM_PER5CLK_MGT 0x038 -#define PRCM_PER6CLK_MGT 0x03C -#define PRCM_PER7CLK_MGT 0x040 -#define PRCM_LCDCLK_MGT 0x044 -#define PRCM_BMLCLK_MGT 0x04C -#define PRCM_HSITXCLK_MGT 0x050 -#define PRCM_HSIRXCLK_MGT 0x054 -#define PRCM_HDMICLK_MGT 0x058 -#define PRCM_APEATCLK_MGT 0x05C -#define PRCM_APETRACECLK_MGT 0x060 -#define PRCM_MCDECLK_MGT 0x064 -#define PRCM_IPI2CCLK_MGT 0x068 -#define PRCM_DSIALTCLK_MGT 0x06C -#define PRCM_DMACLK_MGT 0x074 -#define PRCM_B2R2CLK_MGT 0x078 -#define PRCM_TVCLK_MGT 0x07C -#define PRCM_TCR 0x1C8 -#define PRCM_TCR_STOPPED (1 << 16) -#define PRCM_TCR_DOZE_MODE (1 << 17) -#define PRCM_UNIPROCLK_MGT 0x278 -#define PRCM_SSPCLK_MGT 0x280 -#define PRCM_RNGCLK_MGT 0x284 -#define PRCM_UICCCLK_MGT 0x27C - -#define PRCM_MGT_ENABLE (1 << 8) - -static DEFINE_SPINLOCK(clocks_lock); - -static void __clk_enable(struct clk *clk) -{ - if (clk->enabled++ == 0) { - if (clk->parent_cluster) - __clk_enable(clk->parent_cluster); - - if (clk->parent_periph) - __clk_enable(clk->parent_periph); - - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - } -} - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - __clk_enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void __clk_disable(struct clk *clk) -{ - if (--clk->enabled == 0) { - if (clk->ops && clk->ops->disable) - clk->ops->disable(clk); - - if (clk->parent_periph) - __clk_disable(clk->parent_periph); - - if (clk->parent_cluster) - __clk_disable(clk->parent_cluster); - } -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - WARN_ON(!clk->enabled); - - spin_lock_irqsave(&clocks_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -/* - * The MTU has a separate, rather complex muxing setup - * with alternative parents (peripheral cluster or - * ULP or fixed 32768 Hz) depending on settings - */ -static unsigned long clk_mtu_get_rate(struct clk *clk) -{ - void __iomem *addr; - u32 tcr; - int mtu = (int) clk->data; - /* - * One of these is selected eventually - * TODO: Replace the constant with a reference - * to the ULP source once this is modeled. - */ - unsigned long clk32k = 32768; - unsigned long mturate; - unsigned long retclk; - - if (cpu_is_u8500_family()) - addr = __io_address(U8500_PRCMU_BASE); - else - ux500_unknown_soc(); - - /* - * On a startup, always conifgure the TCR to the doze mode; - * bootloaders do it for us. Do this in the kernel too. - */ - writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); - - tcr = readl(addr + PRCM_TCR); - - /* Get the rate from the parent as a default */ - if (clk->parent_periph) - mturate = clk_get_rate(clk->parent_periph); - else if (clk->parent_cluster) - mturate = clk_get_rate(clk->parent_cluster); - else - /* We need to be connected SOMEWHERE */ - BUG(); - - /* Return the clock selected for this MTU */ - if (tcr & (1 << mtu)) - retclk = clk32k; - else - retclk = mturate; - - pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); - return retclk; -} - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long rate; - - /* - * If there is a custom getrate callback for this clock, - * it will take precedence. - */ - if (clk->get_rate) - return clk->get_rate(clk); - - if (clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - rate = clk->rate; - if (!rate) { - if (clk->parent_periph) - rate = clk_get_rate(clk->parent_periph); - else if (clk->parent_cluster) - rate = clk_get_rate(clk->parent_cluster); - } - - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - /*TODO*/ - return rate; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - /*TODO*/ - return -ENOSYS; -} -EXPORT_SYMBOL(clk_set_parent); - -static void clk_prcmu_enable(struct clk *clk) -{ - void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) - + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; - - writel(1 << clk->prcmu_cg_bit, cg_set_reg); -} - -static void clk_prcmu_disable(struct clk *clk) -{ - void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) - + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; - - writel(1 << clk->prcmu_cg_bit, cg_clr_reg); -} - -static struct clkops clk_prcmu_ops = { - .enable = clk_prcmu_enable, - .disable = clk_prcmu_disable, -}; - -static unsigned int clkrst_base[] = { - [1] = U8500_CLKRST1_BASE, - [2] = U8500_CLKRST2_BASE, - [3] = U8500_CLKRST3_BASE, - [5] = U8500_CLKRST5_BASE, - [6] = U8500_CLKRST6_BASE, -}; - -static void clk_prcc_enable(struct clk *clk) -{ - void __iomem *addr = __io_address(clkrst_base[clk->cluster]); - - if (clk->prcc_kernel != -1) - writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); - - if (clk->prcc_bus != -1) - writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); -} - -static void clk_prcc_disable(struct clk *clk) -{ - void __iomem *addr = __io_address(clkrst_base[clk->cluster]); - - if (clk->prcc_bus != -1) - writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); - - if (clk->prcc_kernel != -1) - writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); -} - -static struct clkops clk_prcc_ops = { - .enable = clk_prcc_enable, - .disable = clk_prcc_disable, -}; - -static struct clk clk_32khz = { - .name = "clk_32khz", - .rate = 32000, -}; - -/* - * PRCMU level clock gating - */ - -/* Bank 0 */ -static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); -static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); -static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); -static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); -static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); -static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ -static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); -static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); -static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); -static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); -static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); -static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); -static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); -static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); -static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); -static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); -static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); -static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); -static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); -static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); -static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); -static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); -static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); -static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ -static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); -static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); -static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); -static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ -static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ - -/* Bank 1 */ -static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ -static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ - -/* - * PRCC level clock gating - * Format: per#, clk, PCKEN bit, KCKEN bit, parent - */ - -/* Peripheral Cluster #1 */ -static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk); -static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); -static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); -static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); -static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); -static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); - -/* Peripheral Cluster #2 */ -static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); - -/* Peripheral Cluster #3 */ -static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); -static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); -static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); -static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); -static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); - -/* Peripheral Cluster #4 is in the always on domain */ - -/* Peripheral Cluster #5 */ -static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); - -/* Peripheral Cluster #6 */ - -/* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL); -static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL); -static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL); -static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL); -static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); - -static struct clk clk_dummy_apb_pclk = { - .name = "apb_pclk", -}; - -static struct clk_lookup u8500_clks[] = { - CLK(dummy_apb_pclk, NULL, "apb_pclk"), - - /* Peripheral Cluster #1 */ - CLK(gpio0, "gpio.0", NULL), - CLK(gpio0, "gpio.1", NULL), - CLK(slimbus0, "slimbus0", NULL), - CLK(i2c2, "nmk-i2c.2", NULL), - CLK(sdi0, "sdi0", NULL), - CLK(msp0, "ux500-msp-i2s.0", NULL), - CLK(i2c1, "nmk-i2c.1", NULL), - CLK(uart1, "uart1", NULL), - CLK(uart0, "uart0", NULL), - - /* Peripheral Cluster #3 */ - CLK(gpio2, "gpio.2", NULL), - CLK(gpio2, "gpio.3", NULL), - CLK(gpio2, "gpio.4", NULL), - CLK(gpio2, "gpio.5", NULL), - CLK(sdi5, "sdi5", NULL), - CLK(uart2, "uart2", NULL), - CLK(ske, "ske", NULL), - CLK(ske, "nmk-ske-keypad", NULL), - CLK(sdi2, "sdi2", NULL), - CLK(i2c0, "nmk-i2c.0", NULL), - CLK(fsmc, "fsmc", NULL), - - /* Peripheral Cluster #5 */ - CLK(gpio3, "gpio.8", NULL), - - /* Peripheral Cluster #6 */ - CLK(hash1, "hash1", NULL), - CLK(pka, "pka", NULL), - CLK(hash0, "hash0", NULL), - CLK(cryp0, "cryp0", NULL), - CLK(cryp1, "cryp1", NULL), - - /* PRCMU level clock gating */ - - /* Bank 0 */ - CLK(svaclk, "sva", NULL), - CLK(siaclk, "sia", NULL), - CLK(sgaclk, "sga", NULL), - CLK(slimclk, "slim", NULL), - CLK(lcdclk, "lcd", NULL), - CLK(bmlclk, "bml", NULL), - CLK(hsitxclk, "stm-hsi.0", NULL), - CLK(hsirxclk, "stm-hsi.1", NULL), - CLK(hdmiclk, "hdmi", NULL), - CLK(apeatclk, "apeat", NULL), - CLK(apetraceclk, "apetrace", NULL), - CLK(mcdeclk, "mcde", NULL), - CLK(ipi2clk, "ipi2", NULL), - CLK(dmaclk, "dma40.0", NULL), - CLK(b2r2clk, "b2r2", NULL), - CLK(tvclk, "tv", NULL), - - /* Peripheral Cluster #1 */ - CLK(i2c4, "nmk-i2c.4", NULL), - CLK(spi3, "spi3", NULL), - CLK(msp1, "ux500-msp-i2s.1", NULL), - CLK(msp3, "ux500-msp-i2s.3", NULL), - - /* Peripheral Cluster #2 */ - CLK(gpio1, "gpio.6", NULL), - CLK(gpio1, "gpio.7", NULL), - CLK(ssitx, "ssitx", NULL), - CLK(ssirx, "ssirx", NULL), - CLK(spi0, "spi0", NULL), - CLK(sdi3, "sdi3", NULL), - CLK(sdi1, "sdi1", NULL), - CLK(msp2, "ux500-msp-i2s.2", NULL), - CLK(sdi4, "sdi4", NULL), - CLK(pwl, "pwl", NULL), - CLK(spi1, "spi1", NULL), - CLK(spi2, "spi2", NULL), - CLK(i2c3, "nmk-i2c.3", NULL), - - /* Peripheral Cluster #3 */ - CLK(ssp1, "ssp1", NULL), - CLK(ssp0, "ssp0", NULL), - - /* Peripheral Cluster #5 */ - CLK(usb, "musb-ux500.0", "usb"), - - /* Peripheral Cluster #6 */ - CLK(mtu1, "mtu1", NULL), - CLK(mtu0, "mtu0", NULL), - CLK(cfgreg, "cfgreg", NULL), - CLK(hash1, "hash1", NULL), - CLK(unipro, "unipro", NULL), - CLK(rng, "rng", NULL), - - /* PRCMU level clock gating */ - - /* Bank 0 */ - CLK(uniproclk, "uniproclk", NULL), - CLK(dsialtclk, "dsialt", NULL), - - /* Bank 1 */ - CLK(rngclk, "rng", NULL), - CLK(uiccclk, "uicc", NULL), -}; - -#ifdef CONFIG_DEBUG_FS -/* - * debugfs support to trace clock tree hierarchy and attributes with - * powerdebug - */ -static struct dentry *clk_debugfs_root; - -void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) -{ - while (num--) { - /* Check that the clock has not been already registered */ - if (!(cl->clk->list.prev != cl->clk->list.next)) - list_add_tail(&cl->clk->list, &clk_list); - - cl++; - } -} - -static ssize_t usecount_dbg_read(struct file *file, char __user *buf, - size_t size, loff_t *off) -{ - struct clk *clk = file->f_dentry->d_inode->i_private; - char cusecount[128]; - unsigned int len; - - len = sprintf(cusecount, "%u\n", clk->enabled); - return simple_read_from_buffer(buf, size, off, cusecount, len); -} - -static ssize_t rate_dbg_read(struct file *file, char __user *buf, - size_t size, loff_t *off) -{ - struct clk *clk = file->f_dentry->d_inode->i_private; - char crate[128]; - unsigned int rate; - unsigned int len; - - rate = clk_get_rate(clk); - len = sprintf(crate, "%u\n", rate); - return simple_read_from_buffer(buf, size, off, crate, len); -} - -static const struct file_operations usecount_fops = { - .read = usecount_dbg_read, -}; - -static const struct file_operations set_rate_fops = { - .read = rate_dbg_read, -}; - -static struct dentry *clk_debugfs_register_dir(struct clk *c, - struct dentry *p_dentry) -{ - struct dentry *d, *clk_d; - const char *p = c->name; - - if (!p) - p = "BUG"; - - clk_d = debugfs_create_dir(p, p_dentry); - if (!clk_d) - return NULL; - - d = debugfs_create_file("usecount", S_IRUGO, - clk_d, c, &usecount_fops); - if (!d) - goto err_out; - d = debugfs_create_file("rate", S_IRUGO, - clk_d, c, &set_rate_fops); - if (!d) - goto err_out; - /* - * TODO : not currently available in ux500 - * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); - * if (!d) - * goto err_out; - */ - - return clk_d; - -err_out: - debugfs_remove_recursive(clk_d); - return NULL; -} - -static int clk_debugfs_register_one(struct clk *c) -{ - struct clk *pa = c->parent_periph; - struct clk *bpa = c->parent_cluster; - - if (!(bpa && !pa)) { - c->dent = clk_debugfs_register_dir(c, - pa ? pa->dent : clk_debugfs_root); - if (!c->dent) - return -ENOMEM; - } - - if (bpa) { - c->dent_bus = clk_debugfs_register_dir(c, - bpa->dent_bus ? bpa->dent_bus : bpa->dent); - if ((!c->dent_bus) && (c->dent)) { - debugfs_remove_recursive(c->dent); - c->dent = NULL; - return -ENOMEM; - } - } - return 0; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->parent_periph; - struct clk *bpa = c->parent_cluster; - - if (pa && (!pa->dent && !pa->dent_bus)) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (bpa && (!bpa->dent && !bpa->dent_bus)) { - err = clk_debugfs_register(bpa); - if (err) - return err; - } - - if ((!c->dent) && (!c->dent_bus)) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clk_list, list) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} - -#endif /* defined(CONFIG_DEBUG_FS) */ - -unsigned long clk_smp_twd_rate = 500000000; - -unsigned long clk_smp_twd_get_rate(struct clk *clk) -{ - return clk_smp_twd_rate; -} - -static struct clk clk_smp_twd = { - .get_rate = clk_smp_twd_get_rate, - .name = "smp_twd", -}; - -static struct clk_lookup clk_smp_twd_lookup = { - .dev_id = "smp_twd", - .clk = &clk_smp_twd, -}; - -#ifdef CONFIG_CPU_FREQ - -static int clk_twd_cpufreq_transition(struct notifier_block *nb, - unsigned long state, void *data) -{ - struct cpufreq_freqs *f = data; - - if (state == CPUFREQ_PRECHANGE) { - /* Save frequency in simple Hz */ - clk_smp_twd_rate = (f->new * 1000) / 2; - } - - return NOTIFY_OK; -} - -static struct notifier_block clk_twd_cpufreq_nb = { - .notifier_call = clk_twd_cpufreq_transition, -}; - -int clk_init_smp_twd_cpufreq(void) -{ - return cpufreq_register_notifier(&clk_twd_cpufreq_nb, - CPUFREQ_TRANSITION_NOTIFIER); -} - -#endif - -int __init clk_init(void) -{ - clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); - clkdev_add(&clk_smp_twd_lookup); - -#ifdef CONFIG_DEBUG_FS - clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); -#endif - return 0; -} diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h deleted file mode 100644 index 65d27a13f46d..000000000000 --- a/arch/arm/mach-ux500/clock.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (C) 2010 ST-Ericsson - * Copyright (C) 2009 STMicroelectronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/** - * struct clkops - ux500 clock operations - * @enable: function to enable the clock - * @disable: function to disable the clock - * @get_rate: function to get the current clock rate - * - * This structure contains function pointers to functions that will be used to - * control the clock. All of these functions are optional. If get_rate is - * NULL, the rate in the struct clk will be used. - */ -struct clkops { - void (*enable) (struct clk *); - void (*disable) (struct clk *); - unsigned long (*get_rate) (struct clk *); - int (*set_parent)(struct clk *, struct clk *); -}; - -/** - * struct clk - ux500 clock structure - * @ops: pointer to clkops struct used to control this clock - * @name: name, for debugging - * @enabled: refcount. positive if enabled, zero if disabled - * @get_rate: custom callback for getting the clock rate - * @data: custom per-clock data for example for the get_rate - * callback - * @rate: fixed rate for clocks which don't implement - * ops->getrate - * @prcmu_cg_off: address offset of the combined enable/disable register - * (used on u8500v1) - * @prcmu_cg_bit: bit in the combined enable/disable register (used on - * u8500v1) - * @prcmu_cg_mgt: address of the enable/disable register (used on - * u8500ed) - * @cluster: peripheral cluster number - * @prcc_bus: bit for the bus clock in the peripheral's CLKRST - * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. - * -1 if no kernel clock exists. - * @parent_cluster: pointer to parent's cluster clk struct - * @parent_periph: pointer to parent's peripheral clk struct - * - * Peripherals are organised into clusters, and each cluster has an associated - * bus clock. Some peripherals also have a parent peripheral clock. - * - * In order to enable a clock for a peripheral, we need to enable: - * (1) the parent cluster (bus) clock at the PRCMU level - * (2) the parent peripheral clock (if any) at the PRCMU level - * (3) the peripheral's bus & kernel clock at the PRCC level - * - * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each - * of the cluster and peripheral clocks, and hooking these as the parents of - * the individual peripheral clocks. - * - * (3) is handled by specifying the bits in the PRCC control registers required - * to enable these clocks and modifying them in the ->enable and - * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). - * - * This structure describes both the PRCMU-level clocks and PRCC-level clocks. - * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, - * prcc, and parent pointers are only used for the PRCC-level clocks. - */ -struct clk { - const struct clkops *ops; - const char *name; - unsigned int enabled; - unsigned long (*get_rate)(struct clk *); - void *data; - - unsigned long rate; - struct list_head list; - - /* These three are only for PRCMU clks */ - - unsigned int prcmu_cg_off; - unsigned int prcmu_cg_bit; - unsigned int prcmu_cg_mgt; - - /* The rest are only for PRCC clks */ - - int cluster; - unsigned int prcc_bus; - unsigned int prcc_kernel; - - struct clk *parent_cluster; - struct clk *parent_periph; -#if defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ - struct dentry *dent_bus; /* For visible tree hierarchy */ -#endif -}; - -#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcmu_ops, \ - .prcmu_cg_off = _cg_off, \ - .prcmu_cg_bit = _cg_bit, \ - .prcmu_cg_mgt = PRCM_##_reg##_MGT \ - } - -#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcmu_ops, \ - .prcmu_cg_off = _cg_off, \ - .prcmu_cg_bit = _cg_bit, \ - .rate = _rate, \ - .prcmu_cg_mgt = PRCM_##_reg##_MGT \ - } - -#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcc_ops, \ - .cluster = _pclust, \ - .prcc_bus = _bus_en, \ - .prcc_kernel = _kernel_en, \ - .parent_cluster = &clk_per##_pclust##clk, \ - .parent_periph = _kernclk \ - } - -#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ -struct clk clk_##_name = { \ - .name = #_name, \ - .ops = &clk_prcc_ops, \ - .cluster = _pclust, \ - .prcc_bus = _bus_en, \ - .prcc_kernel = _kernel_en, \ - .parent_cluster = &clk_per##_pclust##clk, \ - .parent_periph = _kernclk, \ - .get_rate = _callback, \ - .data = (void *) _data \ - } - - -#define CLK(_clk, _devname, _conname) \ - { \ - .clk = &clk_##_clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - -int __init clk_db8500_ed_fixup(void); -int __init clk_init(void); - -#ifdef CONFIG_DEBUG_FS -int clk_debugfs_init(void); -#else -static inline int clk_debugfs_init(void) { return 0; } -#endif - -#ifdef CONFIG_CPU_FREQ -int clk_init_smp_twd_cpufreq(void); -#else -static inline int clk_init_smp_twd_cpufreq(void) { return 0; } -#endif diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index db3c52d56ca4..27a397f5a42c 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -18,8 +18,8 @@ #include <linux/io.h> #include <linux/mfd/abx500/ab8500.h> -#include <asm/mach/map.h> #include <asm/pmu.h> +#include <asm/mach/map.h> #include <plat/gpio-nomadik.h> #include <mach/hardware.h> #include <mach/setup.h> @@ -80,7 +80,7 @@ void __init u8500_map_io(void) iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc)); - if (cpu_is_u9540()) + if (cpu_is_ux540_family()) iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); else iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); @@ -122,7 +122,7 @@ struct arm_pmu_platdata db8500_pmu_platdata = { static struct platform_device db8500_pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(db8500_pmu_resources), .resource = db8500_pmu_resources, .dev.platform_data = &db8500_pmu_platdata, @@ -138,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = { &db8500_prcmu_device, }; -static struct platform_device *of_platform_devs[] __initdata = { - &u8500_dma40_device, -}; - static resource_size_t __initdata db8500_gpio_base[] = { U8500_GPIOBANK0_BASE, U8500_GPIOBANK1_BASE, @@ -235,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) struct device * __init u8500_of_init_devices(void) { struct device *parent; - int i; parent = db8500_soc_device_init(); @@ -244,8 +239,7 @@ struct device * __init u8500_of_init_devices(void) platform_device_register_data(parent, "cpufreq-u8500", -1, NULL, 0); - for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++) - of_platform_devs[i]->dev.parent = parent; + u8500_dma40_device.dev.parent = parent; /* * Devices to be DT:ed: @@ -253,7 +247,7 @@ struct device * __init u8500_of_init_devices(void) * db8500_pmu_device = done * db8500_prcmu_device = done */ - platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); + platform_device_register(&u8500_dma40_device); return parent; } diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e2360e7c770d..2236cbd03cd7 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -8,7 +8,6 @@ #include <linux/platform_device.h> #include <linux/io.h> -#include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> #include <linux/clksrc-dbx500-prcmu.h> #include <linux/sys_soc.h> @@ -17,6 +16,7 @@ #include <linux/stat.h> #include <linux/of.h> #include <linux/of_irq.h> +#include <linux/platform_data/clk-ux500.h> #include <asm/hardware/gic.h> #include <asm/mach/map.h> @@ -25,8 +25,6 @@ #include <mach/setup.h> #include <mach/devices.h> -#include "clock.h" - void __iomem *_PRCMU_BASE; /* @@ -51,7 +49,9 @@ void __init ux500_init_irq(void) void __iomem *dist_base; void __iomem *cpu_base; - if (cpu_is_u8500_family()) { + gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; + + if (cpu_is_u8500_family() || cpu_is_ux540_family()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else @@ -70,13 +70,17 @@ void __init ux500_init_irq(void) */ if (cpu_is_u8500_family()) db8500_prcmu_early_init(); - clk_init(); + + if (cpu_is_u8500_family()) + u8500_clk_init(); + else if (cpu_is_u9540()) + u9540_clk_init(); + else if (cpu_is_u8540()) + u8540_clk_init(); } void __init ux500_init_late(void) { - clk_debugfs_init(); - clk_init_smp_twd_cpufreq(); } static const char * __init ux500_get_machine(void) diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h index c6e2db9e9e51..9c42642ab168 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/include/mach/id.h @@ -41,43 +41,29 @@ static inline bool __attribute_const__ cpu_is_u8500(void) return dbx500_partnumber() == 0x8500; } -static inline bool __attribute_const__ cpu_is_u9540(void) +static inline bool __attribute_const__ cpu_is_u8520(void) { - return dbx500_partnumber() == 0x9540; + return dbx500_partnumber() == 0x8520; } static inline bool cpu_is_u8500_family(void) { - return cpu_is_u8500() || cpu_is_u9540(); -} - -static inline bool __attribute_const__ cpu_is_u5500(void) -{ - return dbx500_partnumber() == 0x5500; -} - -/* - * 5500 revisions - */ - -static inline bool __attribute_const__ cpu_is_u5500v1(void) -{ - return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0; + return cpu_is_u8500() || cpu_is_u8520(); } -static inline bool __attribute_const__ cpu_is_u5500v2(void) +static inline bool __attribute_const__ cpu_is_u9540(void) { - return (dbx500_id.revision & 0xf0) == 0xB0; + return dbx500_partnumber() == 0x9540; } -static inline bool __attribute_const__ cpu_is_u5500v20(void) +static inline bool __attribute_const__ cpu_is_u8540(void) { - return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0); + return dbx500_partnumber() == 0x8540; } -static inline bool __attribute_const__ cpu_is_u5500v21(void) +static inline bool cpu_is_ux540_family(void) { - return cpu_is_u5500() && (dbx500_revision() == 0xB1); + return cpu_is_u9540() || cpu_is_u8540(); } /* @@ -119,14 +105,14 @@ static inline bool cpu_is_u8500v21(void) return cpu_is_u8500() && (dbx500_revision() == 0xB1); } +static inline bool cpu_is_u8500v22(void) +{ + return cpu_is_u8500() && (dbx500_revision() == 0xB2); +} + static inline bool cpu_is_u8500v20_or_later(void) { - /* - * U9540 has so much in common with U8500 that is is considered a - * U8500 variant. - */ - return cpu_is_u9540() || - (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11()); + return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11()); } static inline bool ux500_is_svp(void) diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h index 798be19129ef..3cc7142eee02 100644 --- a/arch/arm/mach-ux500/include/mach/msp.h +++ b/arch/arm/mach-ux500/include/mach/msp.h @@ -22,8 +22,6 @@ struct msp_i2s_platform_data { enum msp_i2s_id id; struct stedma40_chan_cfg *msp_i2s_dma_rx; struct stedma40_chan_cfg *msp_i2s_dma_tx; - int (*msp_i2s_init) (void); - int (*msp_i2s_exit) (void); }; #endif diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 34775baadaea..d60ecd1753f0 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -24,7 +24,7 @@ #include <linux/amba/serial.h> #include <mach/hardware.h> -u32 ux500_uart_base; +void __iomem *ux500_uart_base; static void putc(const char c) { @@ -51,7 +51,7 @@ static void flush(void) static inline void arch_decomp_setup(void) { /* Use machine_is_foo() macro if you need to switch base someday */ - ux500_uart_base = U8500_UART2_BASE; + ux500_uart_base = (void __iomem *)U8500_UART2_BASE; } #define arch_decomp_wdog() /* nothing to do here */ diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index da1d5ad5bd45..a5dda68444db 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -48,7 +48,7 @@ static void write_pen_release(int val) static void __iomem *scu_base_addr(void) { - if (cpu_is_u8500_family()) + if (cpu_is_u8500_family() || cpu_is_ux540_family()) return __io_address(U8500_SCU_BASE); else ux500_unknown_soc(); @@ -118,7 +118,7 @@ static void __init wakeup_secondary(void) { void __iomem *backupram; - if (cpu_is_u8500_family()) + if (cpu_is_u8500_family() || cpu_is_ux540_family()) backupram = __io_address(U8500_BACKUPRAM0_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 66e7f00884ab..6f39731951b0 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -54,7 +54,7 @@ static void __init ux500_timer_init(void) void __iomem *tmp_base; struct device_node *np; - if (cpu_is_u8500_family()) { + if (cpu_is_u8500_family() || cpu_is_ux540_family()) { mtu_timer_base = __io_address(U8500_MTU0_BASE); prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); } else { diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 855ca02581e8..5b5c1eeb5b5c 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -168,11 +168,6 @@ static struct map_desc versatile_io_desc[] __initdata = { .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), .length = VERSATILE_PCI_CFG_BASE_SIZE, .type = MT_DEVICE - }, { - .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0, - .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0), - .length = IO_SPACE_LIMIT, - .type = MT_DEVICE }, #endif }; diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index 408e58da46c6..3e5d425e2a92 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -29,7 +29,6 @@ */ #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul -#define VERSATILE_PCI_VIRT_MEM_BASE0 (void __iomem *)PCIO_BASE /* macro to get at MMIO space when running virtually */ #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index e95bf84cc837..2f84f4094f13 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = { .write = versatile_write_config, }; -static struct resource io_port = { - .name = "PCI", - .start = 0, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - static struct resource io_mem = { .name = "PCI I/O space", .start = VERSATILE_PCI_MEM_BASE0, @@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) "memory region (%d)\n", ret); goto out; } - ret = request_resource(&ioport_resource, &io_port); - if (ret) { - printk(KERN_ERR "PCI: unable to allocate I/O " - "port region (%d)\n", ret); - goto out; - } ret = request_resource(&iomem_resource, &non_mem); if (ret) { printk(KERN_ERR "PCI: unable to allocate non-prefetchable " @@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys) } /* - * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ - pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) goto out; } + ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0); + if (ret) + goto out; + if (nr == 0) { - sys->mem_offset = 0; - sys->io_offset = 0; ret = pci_versatile_setup_resources(sys); if (ret < 0) { printk("pci_versatile_setup: resources... oops?\n"); @@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys) void __init pci_versatile_preinit(void) { - pcibios_min_io = 0x44000000; pcibios_min_mem = 0x50000000; __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 61c492403b05..e4073a60a864 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -13,7 +13,6 @@ #include <asm/hardware/arm_timer.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> -#include <asm/pmu.h> #include <asm/smp_scu.h> #include <asm/smp_twd.h> @@ -144,7 +143,7 @@ static struct resource pmu_resources[] = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(pmu_resources), .resource = pmu_resources, }; diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig deleted file mode 100644 index 2c20a341c11a..000000000000 --- a/arch/arm/mach-vt8500/Kconfig +++ /dev/null @@ -1,73 +0,0 @@ -if ARCH_VT8500 - -config VTWM_VERSION_VT8500 - bool - -config VTWM_VERSION_WM8505 - bool - -config MACH_BV07 - bool "Benign BV07-8500 Mini Netbook" - depends on ARCH_VT8500 - select VTWM_VERSION_VT8500 - help - Add support for the inexpensive 7-inch netbooks sold by many - Chinese distributors under various names. Note that there are - many hardware implementations in identical exterior, make sure - that yours is indeed based on a VIA VT8500 chip. - -config MACH_WM8505_7IN_NETBOOK - bool "WM8505 7-inch generic netbook" - depends on ARCH_VT8500 - select VTWM_VERSION_WM8505 - help - Add support for the inexpensive 7-inch netbooks sold by many - Chinese distributors under various names. Note that there are - many hardware implementations in identical exterior, make sure - that yours is indeed based on a WonderMedia WM8505 chip. - -comment "LCD panel size" - -config WMT_PANEL_800X480 - bool "7-inch with 800x480 resolution" - depends on (FB_VT8500 || FB_WM8505) - default y - help - These are found in most of the netbooks in generic cases, as - well as in Eken M001 tablets and possibly elsewhere. - - To select this panel at runtime, say y here and append - 'panel=800x480' to your kernel command line. Otherwise, the - largest one available will be used. - -config WMT_PANEL_800X600 - bool "8-inch with 800x600 resolution" - depends on (FB_VT8500 || FB_WM8505) - help - These are found in Eken M003 tablets and possibly elsewhere. - - To select this panel at runtime, say y here and append - 'panel=800x600' to your kernel command line. Otherwise, the - largest one available will be used. - -config WMT_PANEL_1024X576 - bool "10-inch with 1024x576 resolution" - depends on (FB_VT8500 || FB_WM8505) - help - These are found in CherryPal netbooks and possibly elsewhere. - - To select this panel at runtime, say y here and append - 'panel=1024x576' to your kernel command line. Otherwise, the - largest one available will be used. - -config WMT_PANEL_1024X600 - bool "10-inch with 1024x600 resolution" - depends on (FB_VT8500 || FB_WM8505) - help - These are found in Eken M006 tablets and possibly elsewhere. - - To select this panel at runtime, say y here and append - 'panel=1024x600' to your kernel command line. Otherwise, the - largest one available will be used. - -endif diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile index 7ce51767c99c..e035251cda48 100644 --- a/arch/arm/mach-vt8500/Makefile +++ b/arch/arm/mach-vt8500/Makefile @@ -1,7 +1 @@ -obj-y += devices.o gpio.o irq.o timer.o restart.o - -obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o -obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o - -obj-$(CONFIG_MACH_BV07) += bv07.o -obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o +obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c deleted file mode 100644 index f9fbeb2d10e9..000000000000 --- a/arch/arm/mach-vt8500/bv07.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/mach-vt8500/bv07.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/io.h> -#include <linux/pm.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/restart.h> - -#include "devices.h" - -static void __iomem *pmc_hiber; - -static struct platform_device *devices[] __initdata = { - &vt8500_device_uart0, - &vt8500_device_lcdc, - &vt8500_device_ehci, - &vt8500_device_ge_rops, - &vt8500_device_pwm, - &vt8500_device_pwmbl, - &vt8500_device_rtc, -}; - -static void vt8500_power_off(void) -{ - local_irq_disable(); - writew(5, pmc_hiber); - asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); -} - -void __init bv07_init(void) -{ -#ifdef CONFIG_FB_VT8500 - void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4); - if (gpio_mux_reg) { - writel(readl(gpio_mux_reg) | 1, gpio_mux_reg); - iounmap(gpio_mux_reg); - } else { - printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n"); - } -#endif - pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2); - if (pmc_hiber) - pm_power_off = &vt8500_power_off; - else - printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); - - wmt_setup_restart(); - vt8500_set_resources(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - vt8500_gpio_init(); -} - -MACHINE_START(BV07, "Benign BV07 Mini Netbook") - .atag_offset = 0x100, - .restart = wmt_restart, - .reserve = vt8500_reserve_mem, - .map_io = vt8500_map_io, - .init_irq = vt8500_init_irq, - .timer = &vt8500_timer, - .init_machine = bv07_init, -MACHINE_END diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-vt8500/common.h index a978b3cc3a8d..2b2419646e95 100644 --- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h +++ b/arch/arm/mach-vt8500/common.h @@ -1,10 +1,6 @@ -/* - * arch/arm/mach-tegra/include/mach/gpio.h +/* linux/arch/arm/mach-vt8500/dt_common.h * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Erik Gilling <konkers@google.com> + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,12 +13,16 @@ * */ -#ifndef __MACH_TEGRA_GPIO_TEGRA_H -#define __MACH_TEGRA_GPIO_TEGRA_H +#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H +#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H + +#include <linux/of.h> -#include <linux/types.h> -#include <mach/irqs.h> +void __init vt8500_timer_init(void); +int __init vt8500_irq_init(struct device_node *node, + struct device_node *parent); -#define TEGRA_NR_GPIOS INT_GPIO_NR +/* defined in drivers/clk/clk-vt8500.c */ +void __init vtwm_clk_init(void __iomem *pmc_base); #endif diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c deleted file mode 100644 index 19519aeecf37..000000000000 --- a/arch/arm/mach-vt8500/devices-vt8500.c +++ /dev/null @@ -1,91 +0,0 @@ -/* linux/arch/arm/mach-vt8500/devices-vt8500.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/platform_device.h> - -#include <mach/vt8500_regs.h> -#include <mach/vt8500_irqs.h> -#include <mach/i8042.h> -#include "devices.h" - -void __init vt8500_set_resources(void) -{ - struct resource tmp[3]; - - tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K); - tmp[1] = wmt_irq_res(IRQ_LCDC); - wmt_res_add(&vt8500_device_lcdc, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART0); - wmt_res_add(&vt8500_device_uart0, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART1); - wmt_res_add(&vt8500_device_uart1, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART2); - wmt_res_add(&vt8500_device_uart2, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART3); - wmt_res_add(&vt8500_device_uart3, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512); - tmp[1] = wmt_irq_res(IRQ_EHCI); - wmt_res_add(&vt8500_device_ehci, tmp, 2); - - tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256); - wmt_res_add(&vt8500_device_ge_rops, tmp, 1); - - tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44); - wmt_res_add(&vt8500_device_pwm, tmp, 1); - - tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c); - tmp[1] = wmt_irq_res(IRQ_RTC); - tmp[2] = wmt_irq_res(IRQ_RTCSM); - wmt_res_add(&vt8500_device_rtc, tmp, 3); -} - -static void __init vt8500_set_externs(void) -{ - /* Non-resource-aware stuff */ - wmt_ic_base = VT8500_IC_BASE; - wmt_gpio_base = VT8500_GPIO_BASE; - wmt_pmc_base = VT8500_PMC_BASE; - wmt_i8042_base = VT8500_PS2_BASE; - - wmt_nr_irqs = VT8500_NR_IRQS; - wmt_timer_irq = IRQ_PMCOS0; - wmt_gpio_ext_irq[0] = IRQ_EXT0; - wmt_gpio_ext_irq[1] = IRQ_EXT1; - wmt_gpio_ext_irq[2] = IRQ_EXT2; - wmt_gpio_ext_irq[3] = IRQ_EXT3; - wmt_gpio_ext_irq[4] = IRQ_EXT4; - wmt_gpio_ext_irq[5] = IRQ_EXT5; - wmt_gpio_ext_irq[6] = IRQ_EXT6; - wmt_gpio_ext_irq[7] = IRQ_EXT7; - wmt_i8042_kbd_irq = IRQ_PS2KBD; - wmt_i8042_aux_irq = IRQ_PS2MOUSE; -} - -void __init vt8500_map_io(void) -{ - iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc)); - - /* Should be done before interrupts and timers are initialized */ - vt8500_set_externs(); -} diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c deleted file mode 100644 index db4594e029f4..000000000000 --- a/arch/arm/mach-vt8500/devices-wm8505.c +++ /dev/null @@ -1,99 +0,0 @@ -/* linux/arch/arm/mach-vt8500/devices-wm8505.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/platform_device.h> - -#include <mach/wm8505_regs.h> -#include <mach/wm8505_irqs.h> -#include <mach/i8042.h> -#include "devices.h" - -void __init wm8505_set_resources(void) -{ - struct resource tmp[3]; - - tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512); - wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1); - - tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART0); - wmt_res_add(&vt8500_device_uart0, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART1); - wmt_res_add(&vt8500_device_uart1, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART2); - wmt_res_add(&vt8500_device_uart2, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART3); - wmt_res_add(&vt8500_device_uart3, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART4); - wmt_res_add(&vt8500_device_uart4, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040); - tmp[1] = wmt_irq_res(IRQ_UART5); - wmt_res_add(&vt8500_device_uart5, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512); - tmp[1] = wmt_irq_res(IRQ_EHCI); - wmt_res_add(&vt8500_device_ehci, tmp, 2); - - tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256); - wmt_res_add(&vt8500_device_ge_rops, tmp, 1); - - tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44); - wmt_res_add(&vt8500_device_pwm, tmp, 1); - - tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c); - tmp[1] = wmt_irq_res(IRQ_RTC); - tmp[2] = wmt_irq_res(IRQ_RTCSM); - wmt_res_add(&vt8500_device_rtc, tmp, 3); -} - -static void __init wm8505_set_externs(void) -{ - /* Non-resource-aware stuff */ - wmt_ic_base = WM8505_IC_BASE; - wmt_sic_base = WM8505_SIC_BASE; - wmt_gpio_base = WM8505_GPIO_BASE; - wmt_pmc_base = WM8505_PMC_BASE; - wmt_i8042_base = WM8505_PS2_BASE; - - wmt_nr_irqs = WM8505_NR_IRQS; - wmt_timer_irq = IRQ_PMCOS0; - wmt_gpio_ext_irq[0] = IRQ_EXT0; - wmt_gpio_ext_irq[1] = IRQ_EXT1; - wmt_gpio_ext_irq[2] = IRQ_EXT2; - wmt_gpio_ext_irq[3] = IRQ_EXT3; - wmt_gpio_ext_irq[4] = IRQ_EXT4; - wmt_gpio_ext_irq[5] = IRQ_EXT5; - wmt_gpio_ext_irq[6] = IRQ_EXT6; - wmt_gpio_ext_irq[7] = IRQ_EXT7; - wmt_i8042_kbd_irq = IRQ_PS2KBD; - wmt_i8042_aux_irq = IRQ_PS2MOUSE; -} - -void __init wm8505_map_io(void) -{ - iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc)); - - /* Should be done before interrupts and timers are initialized */ - wm8505_set_externs(); -} diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c deleted file mode 100644 index 1fcdc36b358d..000000000000 --- a/arch/arm/mach-vt8500/devices.c +++ /dev/null @@ -1,270 +0,0 @@ -/* linux/arch/arm/mach-vt8500/devices.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/device.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/pwm_backlight.h> -#include <linux/memblock.h> - -#include <asm/mach/arch.h> - -#include <mach/vt8500fb.h> -#include <mach/i8042.h> -#include "devices.h" - -/* These can't use resources currently */ -unsigned long wmt_ic_base __initdata; -unsigned long wmt_sic_base __initdata; -unsigned long wmt_gpio_base __initdata; -unsigned long wmt_pmc_base __initdata; -unsigned long wmt_i8042_base __initdata; - -int wmt_nr_irqs __initdata; -int wmt_timer_irq __initdata; -int wmt_gpio_ext_irq[8] __initdata; - -/* Should remain accessible after init. - * i8042 driver desperately calls for attention... - */ -int wmt_i8042_kbd_irq; -int wmt_i8042_aux_irq; - -static u64 fb_dma_mask = DMA_BIT_MASK(32); - -struct platform_device vt8500_device_lcdc = { - .name = "vt8500-lcd", - .id = 0, - .dev = { - .dma_mask = &fb_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device vt8500_device_wm8505_fb = { - .name = "wm8505-fb", - .id = 0, -}; - -/* Smallest to largest */ -static struct vt8500fb_platform_data panels[] = { -#ifdef CONFIG_WMT_PANEL_800X480 -{ - .xres_virtual = 800, - .yres_virtual = 480 * 2, - .mode = { - .name = "800x480", - .xres = 800, - .yres = 480, - .left_margin = 88, - .right_margin = 40, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 0, - .vsync_len = 1, - .vmode = FB_VMODE_NONINTERLACED, - }, -}, -#endif -#ifdef CONFIG_WMT_PANEL_800X600 -{ - .xres_virtual = 800, - .yres_virtual = 600 * 2, - .mode = { - .name = "800x600", - .xres = 800, - .yres = 600, - .left_margin = 88, - .right_margin = 40, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 0, - .vsync_len = 1, - .vmode = FB_VMODE_NONINTERLACED, - }, -}, -#endif -#ifdef CONFIG_WMT_PANEL_1024X576 -{ - .xres_virtual = 1024, - .yres_virtual = 576 * 2, - .mode = { - .name = "1024x576", - .xres = 1024, - .yres = 576, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .vmode = FB_VMODE_NONINTERLACED, - }, -}, -#endif -#ifdef CONFIG_WMT_PANEL_1024X600 -{ - .xres_virtual = 1024, - .yres_virtual = 600 * 2, - .mode = { - .name = "1024x600", - .xres = 1024, - .yres = 600, - .left_margin = 66, - .right_margin = 2, - .upper_margin = 19, - .lower_margin = 1, - .hsync_len = 23, - .vsync_len = 8, - .vmode = FB_VMODE_NONINTERLACED, - }, -}, -#endif -}; - -static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1; - -static int __init panel_setup(char *str) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(panels); i++) { - if (strcmp(panels[i].mode.name, str) == 0) { - current_panel_idx = i; - break; - } - } - return 0; -} - -early_param("panel", panel_setup); - -static inline void preallocate_fb(struct vt8500fb_platform_data *p, - unsigned long align) { - p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >> - (p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 : - (8 / p->bpp) + 1)); - p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len, - align); - p->video_mem_virt = phys_to_virt(p->video_mem_phys); -} - -struct platform_device vt8500_device_uart0 = { - .name = "vt8500_serial", - .id = 0, -}; - -struct platform_device vt8500_device_uart1 = { - .name = "vt8500_serial", - .id = 1, -}; - -struct platform_device vt8500_device_uart2 = { - .name = "vt8500_serial", - .id = 2, -}; - -struct platform_device vt8500_device_uart3 = { - .name = "vt8500_serial", - .id = 3, -}; - -struct platform_device vt8500_device_uart4 = { - .name = "vt8500_serial", - .id = 4, -}; - -struct platform_device vt8500_device_uart5 = { - .name = "vt8500_serial", - .id = 5, -}; - -static u64 ehci_dma_mask = DMA_BIT_MASK(32); - -struct platform_device vt8500_device_ehci = { - .name = "vt8500-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device vt8500_device_ge_rops = { - .name = "wmt_ge_rops", - .id = -1, -}; - -struct platform_device vt8500_device_pwm = { - .name = "vt8500-pwm", - .id = 0, -}; - -static struct platform_pwm_backlight_data vt8500_pwmbl_data = { - .pwm_id = 0, - .max_brightness = 128, - .dft_brightness = 70, - .pwm_period_ns = 250000, /* revisit when clocks are implemented */ -}; - -struct platform_device vt8500_device_pwmbl = { - .name = "pwm-backlight", - .id = 0, - .dev = { - .platform_data = &vt8500_pwmbl_data, - }, -}; - -struct platform_device vt8500_device_rtc = { - .name = "vt8500-rtc", - .id = 0, -}; - -struct map_desc wmt_io_desc[] __initdata = { - /* SoC MMIO registers */ - [0] = { - .virtual = 0xf8000000, - .pfn = __phys_to_pfn(0xd8000000), - .length = 0x00390000, /* max of all chip variants */ - .type = MT_DEVICE - }, - /* PCI I/O space, numbers tied to those in <mach/io.h> */ - [1] = { - .virtual = 0xf0000000, - .pfn = __phys_to_pfn(0xc0000000), - .length = SZ_64K, - .type = MT_DEVICE - }, -}; - -void __init vt8500_reserve_mem(void) -{ -#ifdef CONFIG_FB_VT8500 - panels[current_panel_idx].bpp = 16; /* Always use RGB565 */ - preallocate_fb(&panels[current_panel_idx], SZ_4M); - vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx]; -#endif -} - -void __init wm8505_reserve_mem(void) -{ -#if defined CONFIG_FB_WM8505 - panels[current_panel_idx].bpp = 32; /* Always use RGB888 */ - preallocate_fb(&panels[current_panel_idx], 32); - vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx]; -#endif -} diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h deleted file mode 100644 index 188d4e17f35c..000000000000 --- a/arch/arm/mach-vt8500/devices.h +++ /dev/null @@ -1,88 +0,0 @@ -/* linux/arch/arm/mach-vt8500/devices.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H -#define __ARCH_ARM_MACH_VT8500_DEVICES_H - -#include <linux/platform_device.h> -#include <asm/mach/map.h> - -void __init vt8500_init_irq(void); -void __init wm8505_init_irq(void); -void __init vt8500_map_io(void); -void __init wm8505_map_io(void); -void __init vt8500_reserve_mem(void); -void __init wm8505_reserve_mem(void); -void __init vt8500_gpio_init(void); -void __init vt8500_set_resources(void); -void __init wm8505_set_resources(void); - -extern unsigned long wmt_ic_base __initdata; -extern unsigned long wmt_sic_base __initdata; -extern unsigned long wmt_gpio_base __initdata; -extern unsigned long wmt_pmc_base __initdata; - -extern int wmt_nr_irqs __initdata; -extern int wmt_timer_irq __initdata; -extern int wmt_gpio_ext_irq[8] __initdata; - -extern struct map_desc wmt_io_desc[2] __initdata; - -static inline struct resource wmt_mmio_res(u32 start, u32 size) -{ - struct resource tmp = { - .flags = IORESOURCE_MEM, - .start = start, - .end = start + size - 1, - }; - - return tmp; -} - -static inline struct resource wmt_irq_res(int irq) -{ - struct resource tmp = { - .flags = IORESOURCE_IRQ, - .start = irq, - .end = irq, - }; - - return tmp; -} - -static inline void wmt_res_add(struct platform_device *pdev, - const struct resource *res, unsigned int num) -{ - if (unlikely(platform_device_add_resources(pdev, res, num))) - pr_err("Failed to assign resources\n"); -} - -extern struct sys_timer vt8500_timer; - -extern struct platform_device vt8500_device_uart0; -extern struct platform_device vt8500_device_uart1; -extern struct platform_device vt8500_device_uart2; -extern struct platform_device vt8500_device_uart3; -extern struct platform_device vt8500_device_uart4; -extern struct platform_device vt8500_device_uart5; - -extern struct platform_device vt8500_device_lcdc; -extern struct platform_device vt8500_device_wm8505_fb; -extern struct platform_device vt8500_device_ehci; -extern struct platform_device vt8500_device_ge_rops; -extern struct platform_device vt8500_device_pwm; -extern struct platform_device vt8500_device_pwmbl; -extern struct platform_device vt8500_device_rtc; -#endif diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c deleted file mode 100644 index 2bcc0ec783df..000000000000 --- a/arch/arm/mach-vt8500/gpio.c +++ /dev/null @@ -1,240 +0,0 @@ -/* linux/arch/arm/mach-vt8500/gpio.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include "devices.h" - -#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip) - -#define ENABLE_REGS 0x0 -#define DIRECTION_REGS 0x20 -#define OUTVALUE_REGS 0x40 -#define INVALUE_REGS 0x60 - -#define EXT_REGOFF 0x1c - -static void __iomem *regbase; - -struct vt8500_gpio_chip { - struct gpio_chip chip; - unsigned int shift; - unsigned int regoff; -}; - -static int gpio_to_irq_map[8]; - -static int vt8500_muxed_gpio_request(struct gpio_chip *chip, - unsigned offset) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff); - - val |= (1 << vt8500_chip->shift << offset); - writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff); - - return 0; -} - -static void vt8500_muxed_gpio_free(struct gpio_chip *chip, - unsigned offset) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff); - - val &= ~(1 << vt8500_chip->shift << offset); - writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff); -} - -static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff); - - val &= ~(1 << vt8500_chip->shift << offset); - writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff); - - return 0; -} - -static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff); - - val |= (1 << vt8500_chip->shift << offset); - writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff); - - if (value) { - val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff); - val |= (1 << vt8500_chip->shift << offset); - writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff); - } - return 0; -} - -static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip, - unsigned offset) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - - return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff) - >> vt8500_chip->shift >> offset) & 1; -} - -static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip); - unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff); - - if (value) - val |= (1 << vt8500_chip->shift << offset); - else - val &= ~(1 << vt8500_chip->shift << offset); - - writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff); -} - -#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num) \ -{ \ - .chip = { \ - .label = __name, \ - .request = vt8500_muxed_gpio_request, \ - .free = vt8500_muxed_gpio_free, \ - .direction_input = vt8500_muxed_gpio_direction_input, \ - .direction_output = vt8500_muxed_gpio_direction_output, \ - .get = vt8500_muxed_gpio_get_value, \ - .set = vt8500_muxed_gpio_set_value, \ - .can_sleep = 0, \ - .base = __base, \ - .ngpio = __num, \ - }, \ - .shift = __shift, \ - .regoff = __off, \ -} - -static struct vt8500_gpio_chip vt8500_muxed_gpios[] = { - VT8500_GPIO_BANK("uart0", 0, 0x0, 8, 4), - VT8500_GPIO_BANK("uart1", 4, 0x0, 12, 4), - VT8500_GPIO_BANK("spi0", 8, 0x0, 16, 4), - VT8500_GPIO_BANK("spi1", 12, 0x0, 20, 4), - VT8500_GPIO_BANK("spi2", 16, 0x0, 24, 4), - VT8500_GPIO_BANK("pwmout", 24, 0x0, 28, 2), - - VT8500_GPIO_BANK("sdmmc", 0, 0x4, 30, 11), - VT8500_GPIO_BANK("ms", 16, 0x4, 41, 7), - VT8500_GPIO_BANK("i2c0", 24, 0x4, 48, 2), - VT8500_GPIO_BANK("i2c1", 26, 0x4, 50, 2), - - VT8500_GPIO_BANK("mii", 0, 0x8, 52, 20), - VT8500_GPIO_BANK("see", 20, 0x8, 72, 4), - VT8500_GPIO_BANK("ide", 24, 0x8, 76, 7), - - VT8500_GPIO_BANK("ccir", 0, 0xc, 83, 19), - - VT8500_GPIO_BANK("ts", 8, 0x10, 102, 11), - - VT8500_GPIO_BANK("lcd", 0, 0x14, 113, 23), -}; - -static int vt8500_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF); - - val &= ~(1 << offset); - writel(val, regbase + DIRECTION_REGS + EXT_REGOFF); - return 0; -} - -static int vt8500_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF); - - val |= (1 << offset); - writel(val, regbase + DIRECTION_REGS + EXT_REGOFF); - - if (value) { - val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF); - val |= (1 << offset); - writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF); - } - return 0; -} - -static int vt8500_gpio_get_value(struct gpio_chip *chip, - unsigned offset) -{ - return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1; -} - -static void vt8500_gpio_set_value(struct gpio_chip *chip, - unsigned offset, int value) -{ - unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF); - - if (value) - val |= (1 << offset); - else - val &= ~(1 << offset); - - writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF); -} - -static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - if (offset > 7) - return -EINVAL; - - return gpio_to_irq_map[offset]; -} - -static struct gpio_chip vt8500_external_gpios = { - .label = "extgpio", - .direction_input = vt8500_gpio_direction_input, - .direction_output = vt8500_gpio_direction_output, - .get = vt8500_gpio_get_value, - .set = vt8500_gpio_set_value, - .to_irq = vt8500_gpio_to_irq, - .can_sleep = 0, - .base = 0, - .ngpio = 8, -}; - -void __init vt8500_gpio_init(void) -{ - int i; - - for (i = 0; i < 8; i++) - gpio_to_irq_map[i] = wmt_gpio_ext_irq[i]; - - regbase = ioremap(wmt_gpio_base, SZ_64K); - if (!regbase) { - printk(KERN_ERR "Failed to map MMIO registers for GPIO\n"); - return; - } - - gpiochip_add(&vt8500_external_gpios); - - for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++) - gpiochip_add(&vt8500_muxed_gpios[i].chip); -} diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h index 89f9b787d2a0..738979518acb 100644 --- a/arch/arm/mach-vt8500/include/mach/restart.h +++ b/arch/arm/mach-vt8500/include/mach/restart.h @@ -13,5 +13,5 @@ * */ -void wmt_setup_restart(void); -void wmt_restart(char mode, const char *cmd); +void vt8500_setup_restart(void); +void vt8500_restart(char mode, const char *cmd); diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h deleted file mode 100644 index ecfee9124711..000000000000 --- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * arch/arm/mach-vt8500/include/mach/vt8500_irqs.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* VT8500 Interrupt Sources */ - -#define IRQ_JPEGENC 0 /* JPEG Encoder */ -#define IRQ_JPEGDEC 1 /* JPEG Decoder */ - /* Reserved */ -#define IRQ_PATA 3 /* PATA Controller */ - /* Reserved */ -#define IRQ_DMA 5 /* DMA Controller */ -#define IRQ_EXT0 6 /* External Interrupt 0 */ -#define IRQ_EXT1 7 /* External Interrupt 1 */ -#define IRQ_GE 8 /* Graphic Engine */ -#define IRQ_GOV 9 /* Graphic Overlay Engine */ -#define IRQ_ETHER 10 /* Ethernet MAC */ -#define IRQ_MPEGTS 11 /* Transport Stream Interface */ -#define IRQ_LCDC 12 /* LCD Controller */ -#define IRQ_EXT2 13 /* External Interrupt 2 */ -#define IRQ_EXT3 14 /* External Interrupt 3 */ -#define IRQ_EXT4 15 /* External Interrupt 4 */ -#define IRQ_CIPHER 16 /* Cipher */ -#define IRQ_VPP 17 /* Video Post-Processor */ -#define IRQ_I2C1 18 /* I2C 1 */ -#define IRQ_I2C0 19 /* I2C 0 */ -#define IRQ_SDMMC 20 /* SD/MMC Controller */ -#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */ -#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */ - /* Reserved */ -#define IRQ_SPI0 24 /* SPI 0 */ -#define IRQ_SPI1 25 /* SPI 1 */ -#define IRQ_SPI2 26 /* SPI 2 */ -#define IRQ_LCDDF 27 /* LCD Data Formatter */ -#define IRQ_NAND 28 /* NAND Flash Controller */ -#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */ -#define IRQ_MS 30 /* MemoryStick Controller */ -#define IRQ_MS_DMA 31 /* MemoryStick Controller DMA */ -#define IRQ_UART0 32 /* UART 0 */ -#define IRQ_UART1 33 /* UART 1 */ -#define IRQ_I2S 34 /* I2S */ -#define IRQ_PCM 35 /* PCM */ -#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */ -#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */ -#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */ -#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */ -#define IRQ_VPU 40 /* Video Processing Unit */ -#define IRQ_VID 41 /* Video Digital Input Interface */ -#define IRQ_AC97 42 /* AC97 Interface */ -#define IRQ_EHCI 43 /* USB */ -#define IRQ_NOR 44 /* NOR Flash Controller */ -#define IRQ_PS2MOUSE 45 /* PS/2 Mouse */ -#define IRQ_PS2KBD 46 /* PS/2 Keyboard */ -#define IRQ_UART2 47 /* UART 2 */ -#define IRQ_RTC 48 /* RTC Interrupt */ -#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */ -#define IRQ_UART3 50 /* UART 3 */ -#define IRQ_ADC 51 /* ADC */ -#define IRQ_EXT5 52 /* External Interrupt 5 */ -#define IRQ_EXT6 53 /* External Interrupt 6 */ -#define IRQ_EXT7 54 /* External Interrupt 7 */ -#define IRQ_CIR 55 /* CIR */ -#define IRQ_DMA0 56 /* DMA Channel 0 */ -#define IRQ_DMA1 57 /* DMA Channel 1 */ -#define IRQ_DMA2 58 /* DMA Channel 2 */ -#define IRQ_DMA3 59 /* DMA Channel 3 */ -#define IRQ_DMA4 60 /* DMA Channel 4 */ -#define IRQ_DMA5 61 /* DMA Channel 5 */ -#define IRQ_DMA6 62 /* DMA Channel 6 */ -#define IRQ_DMA7 63 /* DMA Channel 7 */ - -#define VT8500_NR_IRQS 64 diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h deleted file mode 100644 index 29c63ecb2383..000000000000 --- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * arch/arm/mach-vt8500/include/mach/vt8500_regs.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_VT8500_REGS_H -#define __ASM_ARM_ARCH_VT8500_REGS_H - -/* VT8500 Registers Map */ - -#define VT8500_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ -#define VT8500_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ - -#define VT8500_DDR_BASE 0xd8000000 /* 1k DDR/DDR2 Memory - Controller */ -#define VT8500_DMA_BASE 0xd8001000 /* 1k DMA Controller */ -#define VT8500_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory - Controller */ -#define VT8500_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ -#define VT8500_CIPHER_BASE 0xd8006000 /* 4k Cipher */ -#define VT8500_USB_BASE 0xd8007800 /* 2k USB OTG */ -# define VT8500_EHCI_BASE 0xd8007900 /* EHCI */ -# define VT8500_UHCI_BASE 0xd8007b01 /* UHCI */ -#define VT8500_PATA_BASE 0xd8008000 /* 512 PATA */ -#define VT8500_PS2_BASE 0xd8008800 /* 1k PS/2 */ -#define VT8500_NAND_BASE 0xd8009000 /* 1k NAND Controller */ -#define VT8500_NOR_BASE 0xd8009400 /* 1k NOR Controller */ -#define VT8500_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ -#define VT8500_MS_BASE 0xd800b000 /* 1k MS/MSPRO Controller */ -#define VT8500_LCDC_BASE 0xd800e400 /* 1k LCD Controller */ -#define VT8500_VPU_BASE 0xd8050000 /* 256 VPU */ -#define VT8500_GOV_BASE 0xd8050300 /* 256 GOV */ -#define VT8500_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ -#define VT8500_LCDF_BASE 0xd8050900 /* 256 LCD Formatter */ -#define VT8500_VID_BASE 0xd8050a00 /* 256 VID */ -#define VT8500_VPP_BASE 0xd8050b00 /* 256 VPP */ -#define VT8500_TSBK_BASE 0xd80f4000 /* 4k TSBK */ -#define VT8500_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ -#define VT8500_JPEGENC_BASE 0xd80ff000 /* 4k JPEG Encoder */ -#define VT8500_RTC_BASE 0xd8100000 /* 64k RTC */ -#define VT8500_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ -#define VT8500_SCC_BASE 0xd8120000 /* 64k System Configuration*/ -#define VT8500_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ -#define VT8500_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ -#define VT8500_UART0_BASE 0xd8200000 /* 64k UART 0 */ -#define VT8500_UART2_BASE 0xd8210000 /* 64k UART 2 */ -#define VT8500_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ -#define VT8500_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ -#define VT8500_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ -#define VT8500_CIR_BASE 0xd8270000 /* 64k CIR */ -#define VT8500_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ -#define VT8500_AC97_BASE 0xd8290000 /* 64k AC97 */ -#define VT8500_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ -#define VT8500_UART1_BASE 0xd82b0000 /* 64k UART 1 */ -#define VT8500_UART3_BASE 0xd82c0000 /* 64k UART 3 */ -#define VT8500_PCM_BASE 0xd82d0000 /* 64k PCM */ -#define VT8500_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ -#define VT8500_I2S_BASE 0xd8330000 /* 64k I2S */ -#define VT8500_ADC_BASE 0xd8340000 /* 64k ADC */ - -#define VT8500_REGS_END_PHYS 0xd834ffff /* End of MMIO registers */ -#define VT8500_REGS_LENGTH (VT8500_REGS_END_PHYS \ - - VT8500_REGS_START_PHYS + 1) - -#endif diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h deleted file mode 100644 index 6128627ac753..000000000000 --- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * arch/arm/mach-vt8500/include/mach/wm8505_irqs.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* WM8505 Interrupt Sources */ - -#define IRQ_UHCI 0 /* UHC FS (UHCI?) */ -#define IRQ_EHCI 1 /* UHC HS */ -#define IRQ_UDCDMA 2 /* UDC DMA */ - /* Reserved */ -#define IRQ_PS2MOUSE 4 /* PS/2 Mouse */ -#define IRQ_UDC 5 /* UDC */ -#define IRQ_EXT0 6 /* External Interrupt 0 */ -#define IRQ_EXT1 7 /* External Interrupt 1 */ -#define IRQ_KEYPAD 8 /* Keypad */ -#define IRQ_DMA 9 /* DMA Controller */ -#define IRQ_ETHER 10 /* Ethernet MAC */ - /* Reserved */ - /* Reserved */ -#define IRQ_EXT2 13 /* External Interrupt 2 */ -#define IRQ_EXT3 14 /* External Interrupt 3 */ -#define IRQ_EXT4 15 /* External Interrupt 4 */ -#define IRQ_APB 16 /* APB Bridge */ -#define IRQ_DMA0 17 /* DMA Channel 0 */ -#define IRQ_I2C1 18 /* I2C 1 */ -#define IRQ_I2C0 19 /* I2C 0 */ -#define IRQ_SDMMC 20 /* SD/MMC Controller */ -#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */ -#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */ -#define IRQ_PS2KBD 23 /* PS/2 Keyboard */ -#define IRQ_SPI0 24 /* SPI 0 */ -#define IRQ_SPI1 25 /* SPI 1 */ -#define IRQ_SPI2 26 /* SPI 2 */ -#define IRQ_DMA1 27 /* DMA Channel 1 */ -#define IRQ_NAND 28 /* NAND Flash Controller */ -#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */ -#define IRQ_UART5 30 /* UART 5 */ -#define IRQ_UART4 31 /* UART 4 */ -#define IRQ_UART0 32 /* UART 0 */ -#define IRQ_UART1 33 /* UART 1 */ -#define IRQ_DMA2 34 /* DMA Channel 2 */ -#define IRQ_I2S 35 /* I2S */ -#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */ -#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */ -#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */ -#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */ -#define IRQ_DMA3 40 /* DMA Channel 3 */ -#define IRQ_DMA4 41 /* DMA Channel 4 */ -#define IRQ_AC97 42 /* AC97 Interface */ - /* Reserved */ -#define IRQ_NOR 44 /* NOR Flash Controller */ -#define IRQ_DMA5 45 /* DMA Channel 5 */ -#define IRQ_DMA6 46 /* DMA Channel 6 */ -#define IRQ_UART2 47 /* UART 2 */ -#define IRQ_RTC 48 /* RTC Interrupt */ -#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */ -#define IRQ_UART3 50 /* UART 3 */ -#define IRQ_DMA7 51 /* DMA Channel 7 */ -#define IRQ_EXT5 52 /* External Interrupt 5 */ -#define IRQ_EXT6 53 /* External Interrupt 6 */ -#define IRQ_EXT7 54 /* External Interrupt 7 */ -#define IRQ_CIR 55 /* CIR */ -#define IRQ_SIC0 56 /* SIC IRQ0 */ -#define IRQ_SIC1 57 /* SIC IRQ1 */ -#define IRQ_SIC2 58 /* SIC IRQ2 */ -#define IRQ_SIC3 59 /* SIC IRQ3 */ -#define IRQ_SIC4 60 /* SIC IRQ4 */ -#define IRQ_SIC5 61 /* SIC IRQ5 */ -#define IRQ_SIC6 62 /* SIC IRQ6 */ -#define IRQ_SIC7 63 /* SIC IRQ7 */ - /* Reserved */ -#define IRQ_JPEGDEC 65 /* JPEG Decoder */ -#define IRQ_SAE 66 /* SAE (?) */ - /* Reserved */ -#define IRQ_VPU 79 /* Video Processing Unit */ -#define IRQ_VPP 80 /* Video Post-Processor */ -#define IRQ_VID 81 /* Video Digital Input Interface */ -#define IRQ_SPU 82 /* SPU (?) */ -#define IRQ_PIP 83 /* PIP Error */ -#define IRQ_GE 84 /* Graphic Engine */ -#define IRQ_GOV 85 /* Graphic Overlay Engine */ -#define IRQ_DVO 86 /* Digital Video Output */ - /* Reserved */ -#define IRQ_DMA8 92 /* DMA Channel 8 */ -#define IRQ_DMA9 93 /* DMA Channel 9 */ -#define IRQ_DMA10 94 /* DMA Channel 10 */ -#define IRQ_DMA11 95 /* DMA Channel 11 */ -#define IRQ_DMA12 96 /* DMA Channel 12 */ -#define IRQ_DMA13 97 /* DMA Channel 13 */ -#define IRQ_DMA14 98 /* DMA Channel 14 */ -#define IRQ_DMA15 99 /* DMA Channel 15 */ - /* Reserved */ -#define IRQ_GOVW 111 /* GOVW (?) */ -#define IRQ_GOVRSDSCD 112 /* GOVR SDSCD (?) */ -#define IRQ_GOVRSDMIF 113 /* GOVR SDMIF (?) */ -#define IRQ_GOVRHDSCD 114 /* GOVR HDSCD (?) */ -#define IRQ_GOVRHDMIF 115 /* GOVR HDMIF (?) */ - -#define WM8505_NR_IRQS 116 diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h deleted file mode 100644 index df1550941efb..000000000000 --- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/arm/mach-vt8500/include/mach/wm8505_regs.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_WM8505_REGS_H -#define __ASM_ARM_ARCH_WM8505_REGS_H - -/* WM8505 Registers Map */ - -#define WM8505_REGS_START_PHYS 0xd8000000 /* Start of MMIO registers */ -#define WM8505_REGS_START_VIRT 0xf8000000 /* Virtual mapping start */ - -#define WM8505_DDR_BASE 0xd8000400 /* 1k DDR/DDR2 Memory - Controller */ -#define WM8505_DMA_BASE 0xd8001800 /* 1k DMA Controller */ -#define WM8505_VDMA_BASE 0xd8001c00 /* 1k VDMA */ -#define WM8505_SFLASH_BASE 0xd8002000 /* 1k Serial Flash Memory - Controller */ -#define WM8505_ETHER_BASE 0xd8004000 /* 1k Ethernet MAC 0 */ -#define WM8505_CIPHER_BASE 0xd8006000 /* 4k Cipher */ -#define WM8505_USB_BASE 0xd8007000 /* 2k USB 2.0 Host */ -# define WM8505_EHCI_BASE 0xd8007100 /* EHCI */ -# define WM8505_UHCI_BASE 0xd8007301 /* UHCI */ -#define WM8505_PS2_BASE 0xd8008800 /* 1k PS/2 */ -#define WM8505_NAND_BASE 0xd8009000 /* 1k NAND Controller */ -#define WM8505_NOR_BASE 0xd8009400 /* 1k NOR Controller */ -#define WM8505_SDMMC_BASE 0xd800a000 /* 1k SD/MMC Controller */ -#define WM8505_VPU_BASE 0xd8050000 /* 256 VPU */ -#define WM8505_GOV_BASE 0xd8050300 /* 256 GOV */ -#define WM8505_GEGEA_BASE 0xd8050400 /* 768 GE/GE Alpha Mixing */ -#define WM8505_GOVR_BASE 0xd8050800 /* 512 GOVR (frambuffer) */ -#define WM8505_VID_BASE 0xd8050a00 /* 256 VID */ -#define WM8505_SCL_BASE 0xd8050d00 /* 256 SCL */ -#define WM8505_VPP_BASE 0xd8050f00 /* 256 VPP */ -#define WM8505_JPEGDEC_BASE 0xd80fe000 /* 4k JPEG Decoder */ -#define WM8505_RTC_BASE 0xd8100000 /* 64k RTC */ -#define WM8505_GPIO_BASE 0xd8110000 /* 64k GPIO Configuration */ -#define WM8505_SCC_BASE 0xd8120000 /* 64k System Configuration*/ -#define WM8505_PMC_BASE 0xd8130000 /* 64k PMC Configuration */ -#define WM8505_IC_BASE 0xd8140000 /* 64k Interrupt Controller*/ -#define WM8505_SIC_BASE 0xd8150000 /* 64k Secondary IC */ -#define WM8505_UART0_BASE 0xd8200000 /* 64k UART 0 */ -#define WM8505_UART2_BASE 0xd8210000 /* 64k UART 2 */ -#define WM8505_PWM_BASE 0xd8220000 /* 64k PWM Configuration */ -#define WM8505_SPI0_BASE 0xd8240000 /* 64k SPI 0 */ -#define WM8505_SPI1_BASE 0xd8250000 /* 64k SPI 1 */ -#define WM8505_KEYPAD_BASE 0xd8260000 /* 64k Keypad control */ -#define WM8505_CIR_BASE 0xd8270000 /* 64k CIR */ -#define WM8505_I2C0_BASE 0xd8280000 /* 64k I2C 0 */ -#define WM8505_AC97_BASE 0xd8290000 /* 64k AC97 */ -#define WM8505_SPI2_BASE 0xd82a0000 /* 64k SPI 2 */ -#define WM8505_UART1_BASE 0xd82b0000 /* 64k UART 1 */ -#define WM8505_UART3_BASE 0xd82c0000 /* 64k UART 3 */ -#define WM8505_I2C1_BASE 0xd8320000 /* 64k I2C 1 */ -#define WM8505_I2S_BASE 0xd8330000 /* 64k I2S */ -#define WM8505_UART4_BASE 0xd8370000 /* 64k UART 4 */ -#define WM8505_UART5_BASE 0xd8380000 /* 64k UART 5 */ - -#define WM8505_REGS_END_PHYS 0xd838ffff /* End of MMIO registers */ -#define WM8505_REGS_LENGTH (WM8505_REGS_END_PHYS \ - - WM8505_REGS_START_PHYS + 1) - -#endif diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 642de0408f25..f8f9ab9bc56e 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c @@ -1,6 +1,7 @@ /* * arch/arm/mach-vt8500/irq.c * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -18,81 +19,102 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/* + * This file is copied and modified from the original irq.c provided by + * Alexey Charkov. Minor changes have been made for Device Tree Support. + */ + +#include <linux/slab.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/irqdomain.h> #include <linux/interrupt.h> +#include <linux/bitops.h> + +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> #include <asm/irq.h> -#include "devices.h" -#define VT8500_IC_DCTR 0x40 /* Destination control - register, 64*u8 */ -#define VT8500_INT_ENABLE (1 << 3) -#define VT8500_TRIGGER_HIGH (0 << 4) -#define VT8500_TRIGGER_RISING (1 << 4) -#define VT8500_TRIGGER_FALLING (2 << 4) +#define VT8500_ICPC_IRQ 0x20 +#define VT8500_ICPC_FIQ 0x24 +#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */ +#define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */ + +/* ICPC */ +#define ICPC_MASK 0x3F +#define ICPC_ROTATE BIT(6) + +/* IC_DCTR */ +#define ICDC_IRQ 0x00 +#define ICDC_FIQ 0x01 +#define ICDC_DSS0 0x02 +#define ICDC_DSS1 0x03 +#define ICDC_DSS2 0x04 +#define ICDC_DSS3 0x05 +#define ICDC_DSS4 0x06 +#define ICDC_DSS5 0x07 + +#define VT8500_INT_DISABLE 0 +#define VT8500_INT_ENABLE BIT(3) + +#define VT8500_TRIGGER_HIGH 0 +#define VT8500_TRIGGER_RISING BIT(5) +#define VT8500_TRIGGER_FALLING BIT(6) #define VT8500_EDGE ( VT8500_TRIGGER_RISING \ | VT8500_TRIGGER_FALLING) -#define VT8500_IC_STATUS 0x80 /* Interrupt status, 2*u32 */ -static void __iomem *ic_regbase; -static void __iomem *sic_regbase; +static int irq_cnt; + +struct vt8500_irq_priv { + void __iomem *base; +}; static void vt8500_irq_mask(struct irq_data *d) { - void __iomem *base = ic_regbase; - unsigned irq = d->irq; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); + void __iomem *base = priv->base; u8 edge; - if (irq >= 64) { - base = sic_regbase; - irq -= 64; - } - edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE; + edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; if (edge) { - void __iomem *stat_reg = base + VT8500_IC_STATUS - + (irq < 32 ? 0 : 4); + void __iomem *stat_reg = base + VT8500_ICIS + + (d->hwirq < 32 ? 0 : 4); unsigned status = readl(stat_reg); - status |= (1 << (irq & 0x1f)); + status |= (1 << (d->hwirq & 0x1f)); writel(status, stat_reg); } else { - u8 dctr = readb(base + VT8500_IC_DCTR + irq); + u8 dctr = readb(base + VT8500_ICDC + d->hwirq); dctr &= ~VT8500_INT_ENABLE; - writeb(dctr, base + VT8500_IC_DCTR + irq); + writeb(dctr, base + VT8500_ICDC + d->hwirq); } } static void vt8500_irq_unmask(struct irq_data *d) { - void __iomem *base = ic_regbase; - unsigned irq = d->irq; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); + void __iomem *base = priv->base; u8 dctr; - if (irq >= 64) { - base = sic_regbase; - irq -= 64; - } - dctr = readb(base + VT8500_IC_DCTR + irq); + dctr = readb(base + VT8500_ICDC + d->hwirq); dctr |= VT8500_INT_ENABLE; - writeb(dctr, base + VT8500_IC_DCTR + irq); + writeb(dctr, base + VT8500_ICDC + d->hwirq); } static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) { - void __iomem *base = ic_regbase; - unsigned irq = d->irq; - unsigned orig_irq = irq; + struct vt8500_irq_priv *priv = + (struct vt8500_irq_priv *)(d->domain->host_data); + void __iomem *base = priv->base; u8 dctr; - if (irq >= 64) { - base = sic_regbase; - irq -= 64; - } - - dctr = readb(base + VT8500_IC_DCTR + irq); + dctr = readb(base + VT8500_ICDC + d->hwirq); dctr &= ~VT8500_EDGE; switch (flow_type) { @@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) return -EINVAL; case IRQF_TRIGGER_HIGH: dctr |= VT8500_TRIGGER_HIGH; - __irq_set_handler_locked(orig_irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); break; case IRQF_TRIGGER_FALLING: dctr |= VT8500_TRIGGER_FALLING; - __irq_set_handler_locked(orig_irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); break; case IRQF_TRIGGER_RISING: dctr |= VT8500_TRIGGER_RISING; - __irq_set_handler_locked(orig_irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); break; } - writeb(dctr, base + VT8500_IC_DCTR + irq); + writeb(dctr, base + VT8500_ICDC + d->hwirq); return 0; } @@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = { .irq_set_type = vt8500_irq_set_type, }; -void __init vt8500_init_irq(void) +static void __init vt8500_init_irq_hw(void __iomem *base) { unsigned int i; - ic_regbase = ioremap(wmt_ic_base, SZ_64K); + /* Enable rotating priority for IRQ */ + writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ); + writel(0x00, base + VT8500_ICPC_FIQ); - if (ic_regbase) { - /* Enable rotating priority for IRQ */ - writel((1 << 6), ic_regbase + 0x20); - writel(0, ic_regbase + 0x24); + for (i = 0; i < 64; i++) { + /* Disable all interrupts and route them to IRQ */ + writeb(VT8500_INT_DISABLE | ICDC_IRQ, + base + VT8500_ICDC + i); + } +} - for (i = 0; i < wmt_nr_irqs; i++) { - /* Disable all interrupts and route them to IRQ */ - writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); +static int vt8500_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); - irq_set_chip_and_handler(i, &vt8500_irq_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - } else { - printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); - } + return 0; } -void __init wm8505_init_irq(void) +static struct irq_domain_ops vt8500_irq_domain_ops = { + .map = vt8500_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +int __init vt8500_irq_init(struct device_node *node, struct device_node *parent) { - unsigned int i; + struct irq_domain *vt8500_irq_domain; + struct vt8500_irq_priv *priv; + int irq, i; + struct device_node *np = node; + + priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL); + priv->base = of_iomap(np, 0); + + vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0, + &vt8500_irq_domain_ops, priv); + if (!vt8500_irq_domain) + pr_err("%s: Unable to add wmt irq domain!\n", __func__); + + irq_set_default_host(vt8500_irq_domain); + + vt8500_init_irq_hw(priv->base); - ic_regbase = ioremap(wmt_ic_base, SZ_64K); - sic_regbase = ioremap(wmt_sic_base, SZ_64K); - - if (ic_regbase && sic_regbase) { - /* Enable rotating priority for IRQ */ - writel((1 << 6), ic_regbase + 0x20); - writel(0, ic_regbase + 0x24); - writel((1 << 6), sic_regbase + 0x20); - writel(0, sic_regbase + 0x24); - - for (i = 0; i < wmt_nr_irqs; i++) { - /* Disable all interrupts and route them to IRQ */ - if (i < 64) - writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); - else - writeb(0x00, sic_regbase + VT8500_IC_DCTR - + i - 64); - - irq_set_chip_and_handler(i, &vt8500_irq_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID); + pr_info("Added IRQ Controller @ %x [virq_base = %d]\n", + (u32)(priv->base), irq_cnt); + + /* check if this is a slaved controller */ + if (of_irq_count(np) != 0) { + /* check that we have the correct number of interrupts */ + if (of_irq_count(np) != 8) { + pr_err("%s: Incorrect IRQ map for slave controller\n", + __func__); + return -EINVAL; } - } else { - printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n"); + + for (i = 0; i < 8; i++) { + irq = irq_of_parse_and_map(np, i); + enable_irq(irq); + } + + pr_info("vt8500-irq: Enabled slave->parent interrupts\n"); } + + irq_cnt += 64; + + return 0; } + diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c deleted file mode 100644 index 497e89a5e130..000000000000 --- a/arch/arm/mach-vt8500/restart.c +++ /dev/null @@ -1,54 +0,0 @@ -/* linux/arch/arm/mach-vt8500/restart.c - * - * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <asm/io.h> -#include <linux/of.h> -#include <linux/of_address.h> - -#define LEGACY_PMC_BASE 0xD8130000 -#define WMT_PRIZM_PMSR_REG 0x60 - -static void __iomem *pmc_base; - -void wmt_setup_restart(void) -{ - struct device_node *np; - - /* - * Check if Power Mgmt Controller node is present in device tree. If no - * device tree node, use the legacy PMSR value (valid for all current - * SoCs). - */ - np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc"); - if (np) { - pmc_base = of_iomap(np, 0); - - if (!pmc_base) - pr_err("%s:of_iomap(pmc) failed\n", __func__); - - of_node_put(np); - } else { - pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); - if (!pmc_base) { - pr_err("%s:ioremap(rstc) failed\n", __func__); - return; - } - } -} - -void wmt_restart(char mode, const char *cmd) -{ - if (pmc_base) - writel(1, pmc_base + WMT_PRIZM_PMSR_REG); -} diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c index d5376c592ab6..050e1833f2d0 100644 --- a/arch/arm/mach-vt8500/timer.c +++ b/arch/arm/mach-vt8500/timer.c @@ -1,6 +1,7 @@ /* - * arch/arm/mach-vt8500/timer.c + * arch/arm/mach-vt8500/timer_dt.c * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -18,18 +19,25 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/* + * This file is copied and modified from the original timer.c provided by + * Alexey Charkov. Minor changes have been made for Device Tree Support. + */ + #include <linux/io.h> #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/delay.h> - #include <asm/mach/time.h> -#include "devices.h" +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #define VT8500_TIMER_OFFSET 0x0100 +#define VT8500_TIMER_HZ 3000000 #define TIMER_MATCH_VAL 0x0000 #define TIMER_COUNT_VAL 0x0010 #define TIMER_STATUS_VAL 0x0014 @@ -39,7 +47,6 @@ #define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ #define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ #define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ -#define VT8500_TIMER_HZ 3000000 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) @@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs) return readl(regbase + TIMER_COUNT_VAL); } -struct clocksource clocksource = { +static struct clocksource clocksource = { .name = "vt8500_timer", .rating = 200, .read = vt8500_timer_read, @@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode, } } -struct clock_event_device clockevent = { +static struct clock_event_device clockevent = { .name = "vt8500_timer", .features = CLOCK_EVT_FEAT_ONESHOT, .rating = 200, @@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -struct irqaction irq = { +static struct irqaction irq = { .name = "vt8500_timer", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = vt8500_timer_interrupt, .dev_id = &clockevent, }; -static void __init vt8500_timer_init(void) +static struct of_device_id vt8500_timer_ids[] = { + { .compatible = "via,vt8500-timer" }, + { } +}; + +void __init vt8500_timer_init(void) { - regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28); - if (!regbase) - printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n"); + struct device_node *np; + int timer_irq; + + np = of_find_matching_node(NULL, vt8500_timer_ids); + if (!np) { + pr_err("%s: Timer description missing from Device Tree\n", + __func__); + return; + } + regbase = of_iomap(np, 0); + if (!regbase) { + pr_err("%s: Missing iobase description in Device Tree\n", + __func__); + of_node_put(np); + return; + } + timer_irq = irq_of_parse_and_map(np, 0); + if (!timer_irq) { + pr_err("%s: Missing irq description in Device Tree\n", + __func__); + of_node_put(np); + return; + } writel(1, regbase + TIMER_CTRL_VAL); writel(0xf, regbase + TIMER_STATUS_VAL); writel(~0, regbase + TIMER_MATCH_VAL); if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ)) - printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n", - clocksource.name); + pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", + __func__, clocksource.name); clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4); @@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void) clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent); clockevent.cpumask = cpumask_of(0); - if (setup_irq(wmt_timer_irq, &irq)) - printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n", - clockevent.name); + if (setup_irq(timer_irq, &irq)) + pr_err("%s: setup_irq failed for %s\n", __func__, + clockevent.name); clockevents_register_device(&clockevent); } -struct sys_timer vt8500_timer = { - .init = vt8500_timer_init -}; diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c new file mode 100644 index 000000000000..587ea950d08b --- /dev/null +++ b/arch/arm/mach-vt8500/vt8500.c @@ -0,0 +1,195 @@ +/* + * arch/arm/mach-vt8500/vt8500.c + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/io.h> +#include <linux/pm.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> + +#include <mach/restart.h> + +#include "common.h" + +#define LEGACY_GPIO_BASE 0xD8110000 +#define LEGACY_PMC_BASE 0xD8130000 + +/* Registers in GPIO Controller */ +#define VT8500_GPIO_MUX_REG 0x200 + +/* Registers in Power Management Controller */ +#define VT8500_HCR_REG 0x12 +#define VT8500_PMSR_REG 0x60 + +static void __iomem *pmc_base; + +void vt8500_restart(char mode, const char *cmd) +{ + if (pmc_base) + writel(1, pmc_base + VT8500_PMSR_REG); +} + +static struct map_desc vt8500_io_desc[] __initdata = { + /* SoC MMIO registers */ + [0] = { + .virtual = 0xf8000000, + .pfn = __phys_to_pfn(0xd8000000), + .length = 0x00390000, /* max of all chip variants */ + .type = MT_DEVICE + }, +}; + +void __init vt8500_map_io(void) +{ + iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc)); +} + +static void vt8500_power_off(void) +{ + local_irq_disable(); + writew(5, pmc_base + VT8500_HCR_REG); + asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); +} + +void __init vt8500_init(void) +{ + struct device_node *np, *fb; + void __iomem *gpio_base; + +#ifdef CONFIG_FB_VT8500 + fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb"); + if (fb) { + np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio"); + if (np) { + gpio_base = of_iomap(np, 0); + + if (!gpio_base) + pr_err("%s: of_iomap(gpio_mux) failed\n", + __func__); + + of_node_put(np); + } else { + gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000); + if (!gpio_base) + pr_err("%s: ioremap(legacy_gpio_mux) failed\n", + __func__); + } + if (gpio_base) { + writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1, + gpio_base + VT8500_GPIO_MUX_REG); + iounmap(gpio_base); + } else + pr_err("%s: Could not remap GPIO mux\n", __func__); + + of_node_put(fb); + } +#endif + +#ifdef CONFIG_FB_WM8505 + fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb"); + if (fb) { + np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio"); + if (!np) + np = of_find_compatible_node(NULL, NULL, + "wm,wm8650-gpio"); + if (np) { + gpio_base = of_iomap(np, 0); + + if (!gpio_base) + pr_err("%s: of_iomap(gpio_mux) failed\n", + __func__); + + of_node_put(np); + } else { + gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000); + if (!gpio_base) + pr_err("%s: ioremap(legacy_gpio_mux) failed\n", + __func__); + } + if (gpio_base) { + writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | + 0x80000000, gpio_base + VT8500_GPIO_MUX_REG); + iounmap(gpio_base); + } else + pr_err("%s: Could not remap GPIO mux\n", __func__); + + of_node_put(fb); + } +#endif + + np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc"); + if (np) { + pmc_base = of_iomap(np, 0); + + if (!pmc_base) + pr_err("%s:of_iomap(pmc) failed\n", __func__); + + of_node_put(np); + } else { + pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); + if (!pmc_base) + pr_err("%s:ioremap(power_off) failed\n", __func__); + } + if (pmc_base) + pm_power_off = &vt8500_power_off; + else + pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__); + + vtwm_clk_init(pmc_base); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const struct of_device_id vt8500_irq_match[] __initconst = { + { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, }, + { /* sentinel */ }, +}; + +static void __init vt8500_init_irq(void) +{ + of_irq_init(vt8500_irq_match); +}; + +static struct sys_timer vt8500_timer = { + .init = vt8500_timer_init, +}; + +static const char * const vt8500_dt_compat[] = { + "via,vt8500", + "wm,wm8650", + "wm,wm8505", +}; + +DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") + .dt_compat = vt8500_dt_compat, + .map_io = vt8500_map_io, + .init_irq = vt8500_init_irq, + .timer = &vt8500_timer, + .init_machine = vt8500_init, + .restart = vt8500_restart, +MACHINE_END + diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c deleted file mode 100644 index db19886caf7c..000000000000 --- a/arch/arm/mach-vt8500/wm8505_7in.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * arch/arm/mach-vt8500/wm8505_7in.c - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/io.h> -#include <linux/pm.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/restart.h> - -#include "devices.h" - -static void __iomem *pmc_hiber; - -static struct platform_device *devices[] __initdata = { - &vt8500_device_uart0, - &vt8500_device_ehci, - &vt8500_device_wm8505_fb, - &vt8500_device_ge_rops, - &vt8500_device_pwm, - &vt8500_device_pwmbl, - &vt8500_device_rtc, -}; - -static void vt8500_power_off(void) -{ - local_irq_disable(); - writew(5, pmc_hiber); - asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); -} - -void __init wm8505_7in_init(void) -{ -#ifdef CONFIG_FB_WM8505 - void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4); - if (gpio_mux_reg) { - writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg); - iounmap(gpio_mux_reg); - } else { - printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n"); - } -#endif - pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2); - if (pmc_hiber) - pm_power_off = &vt8500_power_off; - else - printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); - wmt_setup_restart(); - wm8505_set_resources(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - vt8500_gpio_init(); -} - -MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") - .atag_offset = 0x100, - .restart = wmt_restart, - .reserve = wm8505_reserve_mem, - .map_io = wm8505_map_io, - .init_irq = wm8505_init_irq, - .timer = &vt8500_timer, - .init_machine = wm8505_7in_init, -MACHINE_END diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2a8e380501e8..577baf7d0a8d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -554,7 +554,7 @@ static const struct of_device_id l2x0_ids[] __initconst = { int __init l2x0_of_init(u32 aux_val, u32 aux_mask) { struct device_node *np; - struct l2x0_of_data *data; + const struct l2x0_of_data *data; struct resource res; np = of_find_matching_node(NULL, l2x0_ids); diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 23a7643e9a87..1be0f4e5e6eb 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -15,8 +15,11 @@ */ #include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/cp15.h> +#include <asm/cputype.h> #include <asm/hardware/cache-tauros2.h> @@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u) __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); } -static void __init disable_l2_prefetch(void) -{ - u32 u; - - /* - * Read the CPU Extra Features register and verify that the - * Disable L2 Prefetch bit is set. - */ - u = read_extra_features(); - if (!(u & 0x01000000)) { - printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); - write_extra_features(u | 0x01000000); - } -} - static inline int __init cpuid_scheme(void) { - extern int processor_id; - return !!((processor_id & 0x000f0000) == 0x000f0000); } @@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr) __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); } -void __init tauros2_init(void) +static void enable_extra_feature(unsigned int features) +{ + u32 u; + + u = read_extra_features(); + + if (features & CACHE_TAUROS2_PREFETCH_ON) + u &= ~0x01000000; + else + u |= 0x01000000; + printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", + (features & CACHE_TAUROS2_PREFETCH_ON) + ? "Enabling" : "Disabling"); + + if (features & CACHE_TAUROS2_LINEFILL_BURST8) + u |= 0x00100000; + else + u &= ~0x00100000; + printk(KERN_INFO "Tauros2: %s line fill burt8.\n", + (features & CACHE_TAUROS2_LINEFILL_BURST8) + ? "Enabling" : "Disabling"); + + write_extra_features(u); +} + +static void __init tauros2_internal_init(unsigned int features) { - extern int processor_id; - char *mode; + char *mode = NULL; - disable_l2_prefetch(); + enable_extra_feature(features); #ifdef CONFIG_CPU_32v5 if ((processor_id & 0xff0f0000) == 0x56050000) { @@ -286,3 +296,34 @@ void __init tauros2_init(void) printk(KERN_INFO "Tauros2: L2 cache support initialised " "in %s mode.\n", mode); } + +#ifdef CONFIG_OF +static const struct of_device_id tauros2_ids[] __initconst = { + { .compatible = "marvell,tauros2-cache"}, + {} +}; +#endif + +void __init tauros2_init(unsigned int features) +{ +#ifdef CONFIG_OF + struct device_node *node; + int ret; + unsigned int f; + + node = of_find_matching_node(NULL, tauros2_ids); + if (!node) { + pr_info("Not found marvell,tauros2-cache, disable it\n"); + return; + } + + ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f); + if (ret) { + pr_info("Not found marvell,tauros-cache-features property, " + "disable extra features\n"); + features = 0; + } else + features = f; +#endif + tauros2_internal_init(features); +} diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 119bc52ab93e..4e07eec1270d 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, pid = task_pid_nr(thread->task) << ASID_BITS; asm volatile( " mrc p15, 0, %0, c13, c0, 1\n" - " bfi %1, %0, #0, %2\n" - " mcr p15, 0, %1, c13, c0, 1\n" + " and %0, %0, %2\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c13, c0, 1\n" : "=r" (contextidr), "+r" (pid) - : "I" (ASID_BITS)); + : "I" (~ASID_MASK)); isb(); return NOTIFY_OK; diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4e7d1182e8a3..13f555d62491 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -267,17 +267,19 @@ static void __dma_free_remap(void *cpu_addr, size_t size) vunmap(cpu_addr); } +#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K + struct dma_pool { size_t size; spinlock_t lock; unsigned long *bitmap; unsigned long nr_pages; void *vaddr; - struct page *page; + struct page **pages; }; static struct dma_pool atomic_pool = { - .size = SZ_256K, + .size = DEFAULT_DMA_COHERENT_POOL_SIZE, }; static int __init early_coherent_pool(char *p) @@ -287,6 +289,21 @@ static int __init early_coherent_pool(char *p) } early_param("coherent_pool", early_coherent_pool); +void __init init_dma_coherent_pool_size(unsigned long size) +{ + /* + * Catch any attempt to set the pool size too late. + */ + BUG_ON(atomic_pool.vaddr); + + /* + * Set architecture specific coherent pool size only if + * it has not been changed by kernel command line parameter. + */ + if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) + atomic_pool.size = size; +} + /* * Initialise the coherent pool for atomic allocations. */ @@ -297,6 +314,7 @@ static int __init atomic_pool_init(void) unsigned long nr_pages = pool->size >> PAGE_SHIFT; unsigned long *bitmap; struct page *page; + struct page **pages; void *ptr; int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); @@ -304,21 +322,33 @@ static int __init atomic_pool_init(void) if (!bitmap) goto no_bitmap; + pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); + if (!pages) + goto no_pages; + if (IS_ENABLED(CONFIG_CMA)) ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); else ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, &page, NULL); if (ptr) { + int i; + + for (i = 0; i < nr_pages; i++) + pages[i] = page + i; + spin_lock_init(&pool->lock); pool->vaddr = ptr; - pool->page = page; + pool->pages = pages; pool->bitmap = bitmap; pool->nr_pages = nr_pages; pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", (unsigned)pool->size / 1024); return 0; } + + kfree(pages); +no_pages: kfree(bitmap); no_bitmap: pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", @@ -443,27 +473,45 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page) if (pageno < pool->nr_pages) { bitmap_set(pool->bitmap, pageno, count); ptr = pool->vaddr + PAGE_SIZE * pageno; - *ret_page = pool->page + pageno; + *ret_page = pool->pages[pageno]; + } else { + pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" + "Please increase it with coherent_pool= kernel parameter!\n", + (unsigned)pool->size / 1024); } spin_unlock_irqrestore(&pool->lock, flags); return ptr; } +static bool __in_atomic_pool(void *start, size_t size) +{ + struct dma_pool *pool = &atomic_pool; + void *end = start + size; + void *pool_start = pool->vaddr; + void *pool_end = pool->vaddr + pool->size; + + if (start < pool_start || start >= pool_end) + return false; + + if (end <= pool_end) + return true; + + WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", + start, end - 1, pool_start, pool_end - 1); + + return false; +} + static int __free_from_pool(void *start, size_t size) { struct dma_pool *pool = &atomic_pool; unsigned long pageno, count; unsigned long flags; - if (start < pool->vaddr || start > pool->vaddr + pool->size) + if (!__in_atomic_pool(start, size)) return 0; - if (start + size > pool->vaddr + pool->size) { - WARN(1, "freeing wrong coherent size from pool\n"); - return 0; - } - pageno = (start - pool->vaddr) >> PAGE_SHIFT; count = size >> PAGE_SHIFT; @@ -1090,10 +1138,22 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si return 0; } +static struct page **__atomic_get_pages(void *addr) +{ + struct dma_pool *pool = &atomic_pool; + struct page **pages = pool->pages; + int offs = (addr - pool->vaddr) >> PAGE_SHIFT; + + return pages + offs; +} + static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) { struct vm_struct *area; + if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) + return __atomic_get_pages(cpu_addr); + if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) return cpu_addr; @@ -1103,6 +1163,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) return NULL; } +static void *__iommu_alloc_atomic(struct device *dev, size_t size, + dma_addr_t *handle) +{ + struct page *page; + void *addr; + + addr = __alloc_from_pool(size, &page); + if (!addr) + return NULL; + + *handle = __iommu_create_mapping(dev, &page, size); + if (*handle == DMA_ERROR_CODE) + goto err_mapping; + + return addr; + +err_mapping: + __free_from_pool(addr, size); + return NULL; +} + +static void __iommu_free_atomic(struct device *dev, struct page **pages, + dma_addr_t handle, size_t size) +{ + __iommu_remove_mapping(dev, handle, size); + __free_from_pool(page_address(pages[0]), size); +} + static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { @@ -1113,6 +1201,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, *handle = DMA_ERROR_CODE; size = PAGE_ALIGN(size); + if (gfp & GFP_ATOMIC) + return __iommu_alloc_atomic(dev, size, handle); + pages = __iommu_alloc_buffer(dev, size, gfp); if (!pages) return NULL; @@ -1179,6 +1270,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, return; } + if (__in_atomic_pool(cpu_addr, size)) { + __iommu_free_atomic(dev, pages, handle, size); + return; + } + if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { unmap_kernel_range((unsigned long)cpu_addr, size); vunmap(cpu_addr); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 566750fa57d4..9d869f93a3da 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -36,6 +36,7 @@ #include <asm/system_info.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "mm.h" int ioremap_page(unsigned long virt, unsigned long phys, @@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr) arch_iounmap(io_addr); } EXPORT_SYMBOL(__arm_iounmap); + +#ifdef CONFIG_PCI +int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) +{ + BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); + + return ioremap_page_range(PCI_IO_VIRT_BASE + offset, + PCI_IO_VIRT_BASE + offset + SZ_64K, + phys_addr, + __pgprot(get_mem_type(MT_DEVICE)->prot_pte)); +} +EXPORT_SYMBOL_GPL(pci_ioremap_io); +#endif diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 6776160618ef..a8ee92da3544 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page /* permanent static mappings from iotable_init() */ #define VM_ARM_STATIC_MAPPING 0x40000000 +/* empty mapping */ +#define VM_ARM_EMPTY_MAPPING 0x20000000 + /* mapping type (attributes) for permanent static mappings */ #define VM_ARM_MTYPE(mt) ((mt) << 20) #define VM_ARM_MTYPE_MASK (0x1f << 20) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 4c2d0451e84a..18144e6a3115 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -31,6 +31,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/pci.h> #include "mm.h" @@ -216,7 +217,7 @@ static struct mem_type mem_types[] = { .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, .domain = DOMAIN_IO, - }, + }, [MT_DEVICE_WC] = { /* ioremap_wc */ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, .prot_l1 = PMD_TYPE_TABLE, @@ -777,14 +778,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr) create_mapping(md); vm->addr = (void *)(md->virtual & PAGE_MASK); vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); - vm->phys_addr = __pfn_to_phys(md->pfn); - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; + vm->phys_addr = __pfn_to_phys(md->pfn); + vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; vm->flags |= VM_ARM_MTYPE(md->type); vm->caller = iotable_init; vm_area_add_early(vm++); } } +void __init vm_reserve_area_early(unsigned long addr, unsigned long size, + void *caller) +{ + struct vm_struct *vm; + + vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); + vm->addr = (void *)addr; + vm->size = size; + vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; + vm->caller = caller; + vm_area_add_early(vm); +} + #ifndef CONFIG_ARM_LPAE /* @@ -802,14 +816,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr) static void __init pmd_empty_section_gap(unsigned long addr) { - struct vm_struct *vm; - - vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); - vm->addr = (void *)addr; - vm->size = SECTION_SIZE; - vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; - vm->caller = pmd_empty_section_gap; - vm_area_add_early(vm); + vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); } static void __init fill_pmd_gaps(void) @@ -820,7 +827,7 @@ static void __init fill_pmd_gaps(void) /* we're still single threaded hence no lock needed here */ for (vm = vmlist; vm; vm = vm->next) { - if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))) continue; addr = (unsigned long)vm->addr; if (addr < next) @@ -858,6 +865,28 @@ static void __init fill_pmd_gaps(void) #define fill_pmd_gaps() do { } while (0) #endif +#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) +static void __init pci_reserve_io(void) +{ + struct vm_struct *vm; + unsigned long addr; + + /* we're still single threaded hence no lock needed here */ + for (vm = vmlist; vm; vm = vm->next) { + if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + continue; + addr = (unsigned long)vm->addr; + addr &= ~(SZ_2M - 1); + if (addr == PCI_IO_VIRT_BASE) + return; + + } + vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); +} +#else +#define pci_reserve_io() do { } while (0) +#endif + static void * __initdata vmalloc_min = (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); @@ -961,8 +990,8 @@ void __init sanity_check_meminfo(void) * Check whether this memory bank would partially overlap * the vmalloc area. */ - if (__va(bank->start + bank->size) > vmalloc_min || - __va(bank->start + bank->size) < __va(bank->start)) { + if (__va(bank->start + bank->size - 1) >= vmalloc_min || + __va(bank->start + bank->size - 1) <= __va(bank->start)) { unsigned long newsize = vmalloc_min - __va(bank->start); printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " "to -%.8llx (vmalloc region overlap).\n", @@ -1141,6 +1170,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc) mdesc->map_io(); fill_pmd_gaps(); + /* Reserve fixed i/o space in VMALLOC region */ + pci_reserve_io(); + /* * Finally flush the caches and tlb to ensure that we're in a * consistent state wrt the writebuffer. This also ensures that diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 8daae9b230ea..362474b5c40d 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr != 0) return 0; - res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); - res[0].start = IOP3XX_PCI_LOWER_IO_PA; - res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; - res[0].name = "IOP3XX PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - request_resource(&ioport_resource, &res[0]); - - res[1].start = IOP3XX_PCI_LOWER_MEM_PA; - res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; - res[1].name = "IOP3XX PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - request_resource(&iomem_resource, &res[1]); + res->start = IOP3XX_PCI_LOWER_MEM_PA; + res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; + res->name = "IOP3XX PCI Memory Space"; + res->flags = IORESOURCE_MEM; + request_resource(&iomem_resource, res); /* * Use whatever translation is already setup. */ sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; - sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); + pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + + pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA); return 1; } @@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void) void __init iop3xx_pci_preinit(void) { - pcibios_min_io = 0; pcibios_min_mem = 0; iop3xx_atu_disable(); diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c index a2024b8685a1..ad9f9744a82d 100644 --- a/arch/arm/plat-iop/pmu.c +++ b/arch/arm/plat-iop/pmu.c @@ -9,7 +9,6 @@ */ #include <linux/platform_device.h> -#include <asm/pmu.h> #include <mach/irqs.h> static struct resource pmu_resource = { @@ -26,7 +25,7 @@ static struct resource pmu_resource = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .resource = &pmu_resource, .num_resources = 1, }; diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c index bade586fed0f..5b217f460f18 100644 --- a/arch/arm/plat-iop/setup.c +++ b/arch/arm/plat-iop/setup.c @@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = { .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), .length = IOP3XX_PERIPHERAL_SIZE, .type = MT_UNCACHED, - }, { /* PCI IO space */ - .virtual = IOP3XX_PCI_LOWER_IO_VA, - .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), - .length = IOP3XX_PCI_IO_WINDOW_SIZE, - .type = MT_DEVICE, }, }; diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 6ac720031150..149237e24850 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o +obj-y := time.o devices.o cpu.o system.o irq-common.o obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c deleted file mode 100644 index 5079787273d2..000000000000 --- a/arch/arm/plat-mxc/clock.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Based on arch/arm/plat-omap/clock.c - * - * Copyright (C) 2004 - 2005 Nokia corporation - * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> - * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -/* #define DEBUG */ - -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/mutex.h> -#include <linux/platform_device.h> -#include <linux/proc_fs.h> -#include <linux/semaphore.h> -#include <linux/string.h> - -#include <mach/clock.h> -#include <mach/hardware.h> - -#ifndef CONFIG_COMMON_CLK -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -/*------------------------------------------------------------------------- - * Standard clock functions defined in include/linux/clk.h - *-------------------------------------------------------------------------*/ - -static void __clk_disable(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - WARN_ON(!clk->usecount); - - if (!(--clk->usecount)) { - if (clk->disable) - clk->disable(clk); - __clk_disable(clk->parent); - __clk_disable(clk->secondary); - } -} - -static int __clk_enable(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - if (clk->usecount++ == 0) { - __clk_enable(clk->parent); - __clk_enable(clk->secondary); - - if (clk->enable) - clk->enable(clk); - } - return 0; -} - -/* This function increments the reference count on the clock and enables the - * clock if not already enabled. The parent clock tree is recursively enabled - */ -int clk_enable(struct clk *clk) -{ - int ret = 0; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - ret = __clk_enable(clk); - mutex_unlock(&clocks_mutex); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -/* This function decrements the reference count on the clock and disables - * the clock when reference count is 0. The parent clock tree is - * recursively disabled - */ -void clk_disable(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - __clk_disable(clk); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_disable); - -/* Retrieve the *current* clock rate. If the clock itself - * does not provide a special calculation routine, ask - * its parent and so on, until one is able to return - * a valid clock rate - */ -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return 0UL; - - if (clk->get_rate) - return clk->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -/* Round the requested clock rate to the nearest supported - * rate that is less than or equal to the requested rate. - * This is dependent on the clock's current parent. - */ -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || IS_ERR(clk) || !clk->round_rate) - return 0; - - return clk->round_rate(clk, rate); -} -EXPORT_SYMBOL(clk_round_rate); - -/* Set the clock to the requested clock rate. The rate must - * match a supported rate exactly based on what clk_round_rate returns - */ -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) - return ret; - - mutex_lock(&clocks_mutex); - ret = clk->set_rate(clk, rate); - mutex_unlock(&clocks_mutex); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -/* Set the clock's parent to another clock source */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - struct clk *old; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || - IS_ERR(parent) || clk->set_parent == NULL) - return ret; - - if (clk->usecount) - clk_enable(parent); - - mutex_lock(&clocks_mutex); - ret = clk->set_parent(clk, parent); - if (ret == 0) { - old = clk->parent; - clk->parent = parent; - } else { - old = parent; - } - mutex_unlock(&clocks_mutex); - - if (clk->usecount) - clk_disable(old); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -/* Retrieve the clock's parent clock source */ -struct clk *clk_get_parent(struct clk *clk) -{ - struct clk *ret = NULL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -#else - -/* - * Lock to protect the clock module (ccm) registers. Used - * on all i.MXs - */ -DEFINE_SPINLOCK(imx_ccm_lock); - -#endif /* CONFIG_COMMON_CLK */ - -/* - * Get the resulting clock rate from a PLL register value and the input - * frequency. PLLs with this register layout can at least be found on - * MX1, MX21, MX27 and MX31 - * - * mfi + mfn / (mfd + 1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) -{ - long long ll; - int mfn_abs; - unsigned int mfi, mfn, mfd, pd; - - mfi = (reg_val >> 10) & 0xf; - mfn = reg_val & 0x3ff; - mfd = (reg_val >> 16) & 0x3ff; - pd = (reg_val >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - mfn_abs = mfn; - - /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit - * 2's complements number - */ - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - mfn_abs = 0x400 - mfn; - - freq *= 2; - freq /= pd + 1; - - ll = (unsigned long long)freq * mfn_abs; - - do_div(ll, mfd + 1); - - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - ll = -ll; - - ll = (freq * mfi) + ll; - - return ll; -} diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 73db34bf588a..b5b6f8083130 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -23,7 +23,6 @@ #include <linux/err.h> #include <linux/slab.h> #include <mach/hardware.h> -#include <mach/clock.h> #define CLK32_FREQ 32768 #define NANOSECOND (1000 * 1000 * 1000) diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2020d84956c3..d390f00bd294 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -87,7 +87,7 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { #ifdef CONFIG_SOC_IMX35 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { #define imx35_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) + imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K) imx35_imx_uart_data_entry(0, 1), imx35_imx_uart_data_entry(1, 2), imx35_imx_uart_data_entry(2, 3), diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h deleted file mode 100644 index bd940c795cbb..000000000000 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_CLOCK_H__ -#define __ASM_ARCH_MXC_CLOCK_H__ - -#ifndef __ASSEMBLY__ -#include <linux/list.h> - -#ifndef CONFIG_COMMON_CLK -struct module; - -struct clk { - int id; - /* Source clock this clk depends on */ - struct clk *parent; - /* Secondary clock to enable/disable with this clock */ - struct clk *secondary; - /* Reference count of clock enable/disable */ - __s8 usecount; - /* Register bit position for clock's enable/disable control. */ - u8 enable_shift; - /* Register address for clock's enable/disable control. */ - void __iomem *enable_reg; - u32 flags; - /* get the current clock rate (always a fresh value) */ - unsigned long (*get_rate) (struct clk *); - /* Function ptr to set the clock to a new rate. The rate must match a - supported rate returned from round_rate. Leave blank if clock is not - programmable */ - int (*set_rate) (struct clk *, unsigned long); - /* Function ptr to round the requested clock rate to the nearest - supported rate that is less than or equal to the requested rate. */ - unsigned long (*round_rate) (struct clk *, unsigned long); - /* Function ptr to enable the clock. Leave blank if clock can not - be gated. */ - int (*enable) (struct clk *); - /* Function ptr to disable the clock. Leave blank if clock can not - be gated. */ - void (*disable) (struct clk *); - /* Function ptr to set the parent clock of the clock. */ - int (*set_parent) (struct clk *, struct clk *); -}; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); -#endif /* CONFIG_COMMON_CLK */ - -extern spinlock_t imx_ccm_lock; - -unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7128e9710417..28ba09f4ebb9 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -52,7 +52,6 @@ extern void imx31_soc_init(void); extern void imx35_soc_init(void); extern void imx50_soc_init(void); extern void imx51_soc_init(void); -extern void imx53_soc_init(void); extern void imx51_init_late(void); extern void imx53_init_late(void); extern void epit_timer_init(void __iomem *base, int irq); @@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void); extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); extern void imx_gpc_post_resume(void); -extern void imx51_babbage_common_init(void); -extern void imx53_ard_common_init(void); -extern void imx53_evk_common_init(void); -extern void imx53_qsb_common_init(void); -extern void imx53_smd_common_init(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); extern void imx6q_clock_map_io(void); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index d8b65b51f2a9..f79f78a1c0ed 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -512,12 +512,16 @@ enum iomux_pins { #define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) #define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) #define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) #define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) @@ -721,6 +725,7 @@ enum iomux_pins { #define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) #define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h deleted file mode 100644 index 9761e003bde2..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ /dev/null @@ -1,1219 +0,0 @@ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc.. - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_IOMUX_MX53_H__ -#define __MACH_IOMUX_MX53_H__ - -#include <mach/iomux-v3.h> - -/* These 2 defines are for pins that may not have a mux register, but could - * have a pad setting register, and vice-versa. */ -#define __NA_ 0x00 - -#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) - - -#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ - IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ - IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ - IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ - IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ - IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ - IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ - IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ - IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ - IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ - IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ - IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ - IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) -#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) -#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) -#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 627d94f1b010..ec466400a200 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -98,6 +98,7 @@ #define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) #define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) #define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) +#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) #define MX25_INT_FEC (NR_IRQS_LEGACY + 57) #define MX25_DMA_REQ_SSI2_RX1 22 diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h index 3c080a32dbf5..7ded6f1f74bc 100644 --- a/arch/arm/plat-mxc/include/mach/mx2_cam.h +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h @@ -23,7 +23,6 @@ #ifndef __MACH_MX2_CAM_H_ #define __MACH_MX2_CAM_H_ -#define MX2_CAMERA_SWAP16 (1 << 0) #define MX2_CAMERA_EXT_VSYNC (1 << 1) #define MX2_CAMERA_CCIR (1 << 2) #define MX2_CAMERA_CCIR_INTERLACE (1 << 3) @@ -31,7 +30,6 @@ #define MX2_CAMERA_GATED_CLOCK (1 << 5) #define MX2_CAMERA_INV_DATA (1 << 6) #define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7) -#define MX2_CAMERA_PACK_DIR_MSB (1 << 8) /** * struct mx2_camera_platform_data - optional platform data for mx2_camera diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index dbced61d9fda..ee9b1f9215df 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -76,7 +76,7 @@ #define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) #define MX31_ROMP_BASE_ADDR 0x60000000 -#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000 +#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) #define MX31_ROMP_SIZE SZ_1M #define MX31_AVIC_BASE_ADDR 0x68000000 @@ -92,11 +92,11 @@ #define MX31_CS3_BASE_ADDR 0xb2000000 #define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) #define MX31_CS4_SIZE SZ_32M #define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 +#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) #define MX31_CS5_SIZE SZ_32M #define MX31_X_MEMC_BASE_ADDR 0xb8000000 diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S index 8397a2dd19f2..a8b93c5f29b5 100644 --- a/arch/arm/plat-mxc/ssi-fiq.S +++ b/arch/arm/plat-mxc/ssi-fiq.S @@ -34,91 +34,98 @@ .global imx_ssi_fiq_rx_buffer .global imx_ssi_fiq_tx_buffer +/* + * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol + * using ENDPROC(). imx_ssi_fiq_start and imx_ssi_fiq_end are used to + * mark the function body so that it can be copied to the FIQ vector in + * the vectors page. imx_ssi_fiq_start should only be called as the result + * of an FIQ: calling it directly will not work. + */ imx_ssi_fiq_start: - ldr r12, imx_ssi_fiq_base + ldr r12, .L_imx_ssi_fiq_base /* TX */ - ldr r11, imx_ssi_fiq_tx_buffer + ldr r13, .L_imx_ssi_fiq_tx_buffer /* shall we send? */ - ldr r13, [r12, #SSI_SIER] - tst r13, #SSI_SIER_TFE0_EN + ldr r11, [r12, #SSI_SIER] + tst r11, #SSI_SIER_TFE0_EN beq 1f /* TX FIFO empty? */ - ldr r13, [r12, #SSI_SISR] - tst r13, #SSI_SISR_TFE0 + ldr r11, [r12, #SSI_SISR] + tst r11, #SSI_SISR_TFE0 beq 1f mov r10, #0x10000 sub r10, #1 and r10, r10, r8 /* r10: current buffer offset */ - add r11, r11, r10 + add r13, r13, r10 - ldrh r13, [r11] - strh r13, [r12, #SSI_STX0] + ldrh r11, [r13] + strh r11, [r12, #SSI_STX0] - ldrh r13, [r11, #2] - strh r13, [r12, #SSI_STX0] + ldrh r11, [r13, #2] + strh r11, [r12, #SSI_STX0] - ldrh r13, [r11, #4] - strh r13, [r12, #SSI_STX0] + ldrh r11, [r13, #4] + strh r11, [r12, #SSI_STX0] - ldrh r13, [r11, #6] - strh r13, [r12, #SSI_STX0] + ldrh r11, [r13, #6] + strh r11, [r12, #SSI_STX0] add r10, #8 - lsr r13, r8, #16 /* r13: buffer size */ - cmp r10, r13 - lslgt r8, r13, #16 + lsr r11, r8, #16 /* r11: buffer size */ + cmp r10, r11 + lslgt r8, r11, #16 addle r8, #8 1: /* RX */ /* shall we receive? */ - ldr r13, [r12, #SSI_SIER] - tst r13, #SSI_SIER_RFF0_EN + ldr r11, [r12, #SSI_SIER] + tst r11, #SSI_SIER_RFF0_EN beq 1f /* RX FIFO full? */ - ldr r13, [r12, #SSI_SISR] - tst r13, #SSI_SISR_RFF0 + ldr r11, [r12, #SSI_SISR] + tst r11, #SSI_SISR_RFF0 beq 1f - ldr r11, imx_ssi_fiq_rx_buffer + ldr r13, .L_imx_ssi_fiq_rx_buffer mov r10, #0x10000 sub r10, #1 and r10, r10, r9 /* r10: current buffer offset */ - add r11, r11, r10 + add r13, r13, r10 - ldr r13, [r12, #SSI_SACNT] - tst r13, #SSI_SACNT_AC97EN + ldr r11, [r12, #SSI_SACNT] + tst r11, #SSI_SACNT_AC97EN - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11] + ldr r11, [r12, #SSI_SRX0] + strh r11, [r13] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #2] + ldr r11, [r12, #SSI_SRX0] + strh r11, [r13, #2] /* dummy read to skip slot 12 */ - ldrne r13, [r12, #SSI_SRX0] + ldrne r11, [r12, #SSI_SRX0] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #4] + ldr r11, [r12, #SSI_SRX0] + strh r11, [r13, #4] - ldr r13, [r12, #SSI_SRX0] - strh r13, [r11, #6] + ldr r11, [r12, #SSI_SRX0] + strh r11, [r13, #6] /* dummy read to skip slot 12 */ - ldrne r13, [r12, #SSI_SRX0] + ldrne r11, [r12, #SSI_SRX0] add r10, #8 - lsr r13, r9, #16 /* r13: buffer size */ - cmp r10, r13 - lslgt r9, r13, #16 + lsr r11, r9, #16 /* r11: buffer size */ + cmp r10, r11 + lslgt r9, r11, #16 addle r9, #8 1: @@ -126,11 +133,15 @@ imx_ssi_fiq_start: subs pc, lr, #4 .align +.L_imx_ssi_fiq_base: imx_ssi_fiq_base: .word 0x0 +.L_imx_ssi_fiq_rx_buffer: imx_ssi_fiq_rx_buffer: .word 0x0 +.L_imx_ssi_fiq_tx_buffer: imx_ssi_fiq_tx_buffer: .word 0x0 +.L_imx_ssi_fiq_end: imx_ssi_fiq_end: diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 1996c3e3b8fe..3da78cfc5a94 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -21,7 +21,6 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/delay.h> -#include <linux/module.h> #include <mach/hardware.h> #include <mach/common.h> @@ -29,9 +28,6 @@ #include <asm/proc-fns.h> #include <asm/mach-types.h> -void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; -EXPORT_SYMBOL_GPL(imx_ioremap); - static void __iomem *wdog_base; /* diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 13910baae228..ca83a7659aef 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP + select SPARSE_IRQ select OMAP_DM_TIMER select USE_OF select PROC_DEVICETREE if PROC_FS diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 961bf859bc0c..dacaee009a4e 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -3,8 +3,7 @@ # # Common support -obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ - fb.o counter_32k.o +obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 89a3723b3538..111315a69354 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -17,52 +17,12 @@ #include <linux/dma-mapping.h> #include <plat/common.h> -#include <plat/board.h> #include <plat/vram.h> -#include <plat/dsp.h> +#include <linux/platform_data/dsp-omap.h> #include <plat/dma.h> #include <plat/omap-secure.h> - -#define NO_LENGTH_CHECK 0xffffffff - -struct omap_board_config_kernel *omap_board_config __initdata; -int omap_board_config_size; - -static const void *__init get_config(u16 tag, size_t len, - int skip, size_t *len_out) -{ - struct omap_board_config_kernel *kinfo = NULL; - int i; - - /* Try to find the config from the board-specific structures - * in the kernel. */ - for (i = 0; i < omap_board_config_size; i++) { - if (omap_board_config[i].tag == tag) { - if (skip == 0) { - kinfo = &omap_board_config[i]; - break; - } else { - skip--; - } - } - } - if (kinfo == NULL) - return NULL; - return kinfo->data; -} - -const void *__init __omap_get_config(u16 tag, size_t len, int nr) -{ - return get_config(tag, len, nr, NULL); -} - -const void *__init omap_get_var_config(u16 tag, size_t *len) -{ - return get_config(tag, NO_LENGTH_CHECK, 0, len); -} - void __init omap_reserve(void) { omap_vram_reserve_sdram_memblock(); diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index dbf1e03029a5..2e826f1faf7b 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -22,10 +22,7 @@ #include <asm/mach/time.h> #include <asm/sched_clock.h> -#include <plat/hardware.h> #include <plat/common.h> -#include <plat/board.h> - #include <plat/clock.h> /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index caa1f7b6cc21..c7a4c0902b38 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c @@ -17,9 +17,6 @@ #include <mach/hardware.h> -#include <plat/board.h> - - /* Many OMAP development platforms reuse the same "debug board"; these * platforms include H2, H3, H4, and Perseus2. */ diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 24e23f3dd6a8..ea29bbe8e5cf 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c @@ -14,6 +14,7 @@ #include <linux/platform_device.h> #include <linux/leds.h> #include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> #include <linux/slab.h> #include <mach/hardware.h> diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c deleted file mode 100644 index 1cba9273d2cb..000000000000 --- a/arch/arm/plat-omap/devices.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * linux/arch/arm/plat-omap/devices.c - * - * Common platform device setup/initialization for OMAP1 and OMAP2 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/memblock.h> - -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> - -#include <plat/tc.h> -#include <plat/board.h> -#include <plat/mmc.h> -#include <plat/menelaus.h> -#include <plat/omap44xx.h> - -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE) - -#ifdef CONFIG_ARCH_OMAP2 -#define OMAP_RNG_BASE 0x480A0000 -#else -#define OMAP_RNG_BASE 0xfffe5000 -#endif - -static struct resource rng_resources[] = { - { - .start = OMAP_RNG_BASE, - .end = OMAP_RNG_BASE + 0x4f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap_rng_device = { - .name = "omap_rng", - .id = -1, - .num_resources = ARRAY_SIZE(rng_resources), - .resource = rng_resources, -}; - -static void omap_init_rng(void) -{ - (void) platform_device_register(&omap_rng_device); -} -#else -static inline void omap_init_rng(void) {} -#endif - -/* - * This gets called after board-specific INIT_MACHINE, and initializes most - * on-chip peripherals accessible on this board (except for few like USB): - * - * (a) Does any "standard config" pin muxing needed. Board-specific - * code will have muxed GPIO pins and done "nonstandard" setup; - * that code could live in the boot loader. - * (b) Populating board-specific platform_data with the data drivers - * rely on to handle wiring variations. - * (c) Creating platform devices as meaningful on this board and - * with this kernel configuration. - * - * Claiming GPIOs, and setting their direction and initial values, is the - * responsibility of the device drivers. So is responding to probe(). - * - * Board-specific knowledge like creating devices or pin setup is to be - * kept out of drivers as much as possible. In particular, pin setup - * may be handled by the boot loader, and drivers should expect it will - * normally have been done by the time they're probed. - */ -static int __init omap_init_devices(void) -{ - /* please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - omap_init_rng(); - return 0; -} -arch_initcall(omap_init_devices); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 7fe626761e53..c76ed8bff838 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -36,9 +36,8 @@ #include <linux/slab.h> #include <linux/delay.h> -#include <mach/hardware.h> +#include <plat/cpu.h> #include <plat/dma.h> - #include <plat/tc.h> /* @@ -969,8 +968,7 @@ void omap_stop_dma(int lch) l = p->dma_read(CCR, lch); } if (i >= 100) - printk(KERN_ERR "DMA drain did not complete on " - "lch %d\n", lch); + pr_err("DMA drain did not complete on lch %d\n", lch); /* Restore OCP_SYSCONFIG */ p->dma_write(sys_cf, OCP_SYSCONFIG, lch); } else { @@ -1154,8 +1152,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue) if ((dma_chan[lch_head].dev_id == -1) || (dma_chan[lch_queue].dev_id == -1)) { - printk(KERN_ERR "omap_dma: trying to link " - "non requested channels\n"); + pr_err("omap_dma: trying to link non requested channels\n"); dump_stack(); } @@ -1181,15 +1178,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) if (dma_chan[lch_head].next_lch != lch_queue || dma_chan[lch_head].next_lch == -1) { - printk(KERN_ERR "omap_dma: trying to unlink " - "non linked channels\n"); + pr_err("omap_dma: trying to unlink non linked channels\n"); dump_stack(); } if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { - printk(KERN_ERR "omap_dma: You need to stop the DMA channels " - "before unlinking\n"); + pr_err("omap_dma: You need to stop the DMA channels before unlinking\n"); dump_stack(); } @@ -1831,16 +1826,15 @@ static int omap1_dma_handle_ch(int ch) if ((csr & 0x3f) == 0) return 0; if (unlikely(dma_chan[ch].dev_id == -1)) { - printk(KERN_WARNING "Spurious interrupt from DMA channel " - "%d (CSR %04x)\n", ch, csr); + pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", + ch, csr); return 0; } if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) - printk(KERN_WARNING "DMA timeout with device %d\n", - dma_chan[ch].dev_id); + pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); if (unlikely(csr & OMAP_DMA_DROP_IRQ)) - printk(KERN_WARNING "DMA synchronization event drop occurred " - "with device %d\n", dma_chan[ch].dev_id); + pr_warn("DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); if (likely(csr & OMAP_DMA_BLOCK_IRQ)) dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; if (likely(dma_chan[ch].callback != NULL)) @@ -1880,21 +1874,19 @@ static int omap2_dma_handle_ch(int ch) if (!status) { if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", - ch); + pr_warn("Spurious DMA IRQ for lch %d\n", ch); p->dma_write(1 << ch, IRQSTATUS_L0, ch); return 0; } if (unlikely(dma_chan[ch].dev_id == -1)) { if (printk_ratelimit()) - printk(KERN_WARNING "IRQ %04x for non-allocated DMA" - "channel %d\n", status, ch); + pr_warn("IRQ %04x for non-allocated DMA channel %d\n", + status, ch); return 0; } if (unlikely(status & OMAP_DMA_DROP_IRQ)) - printk(KERN_INFO - "DMA synchronization event drop occurred with device " - "%d\n", dma_chan[ch].dev_id); + pr_info("DMA synchronization event drop occurred with device %d\n", + dma_chan[ch].dev_id); if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { printk(KERN_INFO "DMA transaction error with device %d\n", dma_chan[ch].dev_id); @@ -2014,8 +2006,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) p = pdev->dev.platform_data; if (!p) { - dev_err(&pdev->dev, "%s: System DMA initialized without" - "platform data\n", __func__); + dev_err(&pdev->dev, + "%s: System DMA initialized without platform data\n", + __func__); return -EINVAL; } @@ -2090,8 +2083,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) } ret = setup_irq(dma_irq, &omap24xx_dma_irq); if (ret) { - dev_err(&pdev->dev, "set_up failed for IRQ %d" - "for DMA (error %d)\n", dma_irq, ret); + dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", + dma_irq, ret); goto exit_dma_lch_fail; } } @@ -2099,8 +2092,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) /* reserve dma channels 0 and 1 in high security devices */ if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) { - printk(KERN_INFO "Reserving DMA channels 0 and 1 for " - "HS ROM code\n"); + pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); dma_chan[0].dev_id = 0; dma_chan[1].dev_id = 1; } @@ -2108,8 +2100,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev) return 0; exit_dma_irq_fail: - dev_err(&pdev->dev, "unable to request IRQ %d" - "for DMA (error %d)\n", dma_irq, ret); + dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", + dma_irq, ret); for (irq_rel = 0; irq_rel < ch; irq_rel++) { dma_irq = platform_get_irq(pdev, irq_rel); free_irq(dma_irq, (void *)(irq_rel + 1)); diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index dd6f92c99e56..bcbb9d5dc293 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -33,8 +33,6 @@ #include <mach/hardware.h> #include <asm/mach/map.h> -#include <plat/board.h> - #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static bool omapfb_lcd_configured; diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index db071bc71c4d..6013831a043e 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -32,13 +32,13 @@ #include <linux/clk.h> #include <mach/irqs.h> -#include <plat/mux.h> #include <plat/i2c.h> #include <plat/omap-pm.h> #include <plat/omap_device.h> #define OMAP_I2C_SIZE 0x3f #define OMAP1_I2C_BASE 0xfffb3800 +#define OMAP1_INT_I2C (32 + 4) static const char name[] = "omap_i2c"; @@ -105,7 +105,7 @@ static inline int omap1_i2c_add_bus(int bus_id) res = pdev->resource; res[0].start = OMAP1_I2C_BASE; res[0].end = res[0].start + OMAP_I2C_SIZE; - res[1].start = INT_I2C; + res[1].start = OMAP1_INT_I2C; pdata = &i2c_pdata[bus_id - 1]; /* all OMAP1 have IP version 1 register set */ diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h deleted file mode 100644 index e62f20a5c0af..000000000000 --- a/arch/arm/plat-omap/include/plat/board.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/board.h - * - * Information structures for board-specific data - * - * Copyright (C) 2004 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ - -#ifndef _OMAP_BOARD_H -#define _OMAP_BOARD_H - -#include <linux/types.h> - -#include <plat/gpio-switch.h> - -/* - * OMAP35x EVM revision - * Run time detection of EVM revision is done by reading Ethernet - * PHY ID - - * GEN_1 = 0x01150000 - * GEN_2 = 0x92200000 - */ -enum { - OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ - OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ -}; - -/* Different peripheral ids */ -#define OMAP_TAG_CLOCK 0x4f01 -#define OMAP_TAG_GPIO_SWITCH 0x4f06 -#define OMAP_TAG_STI_CONSOLE 0x4f09 -#define OMAP_TAG_CAMERA_SENSOR 0x4f0a - -#define OMAP_TAG_BOOT_REASON 0x4f80 -#define OMAP_TAG_FLASH_PART 0x4f81 -#define OMAP_TAG_VERSION_STR 0x4f82 - -struct omap_clock_config { - /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ - u8 system_clock_type; -}; - -struct omap_serial_console_config { - u8 console_uart; - u32 console_speed; -}; - -struct omap_sti_console_config { - unsigned enable:1; - u8 channel; -}; - -struct omap_camera_sensor_config { - u16 reset_gpio; - int (*power_on)(void * data); - int (*power_off)(void * data); -}; - -struct omap_lcd_config { - char panel_name[16]; - char ctrl_name[16]; - s16 nreset_gpio; - u8 data_lines; -}; - -struct device; -struct fb_info; -struct omap_backlight_config { - int default_intensity; - int (*set_power)(struct device *dev, int state); -}; - -struct omap_fbmem_config { - u32 start; - u32 size; -}; - -struct omap_pwm_led_platform_data { - const char *name; - int intensity_timer; - int blink_timer; - void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); -}; - -struct omap_uart_config { - /* Bit field of UARTs present; bit 0 --> UART1 */ - unsigned int enabled_uarts; -}; - - -struct omap_flash_part_config { - char part_table[0]; -}; - -struct omap_boot_reason_config { - char reason_str[12]; -}; - -struct omap_version_config { - char component[12]; - char version[12]; -}; - -struct omap_board_config_entry { - u16 tag; - u16 len; - u8 data[0]; -}; - -struct omap_board_config_kernel { - u16 tag; - const void *data; -}; - -extern const void *__init __omap_get_config(u16 tag, size_t len, int nr); - -#define omap_get_config(tag, type) \ - ((const type *) __omap_get_config((tag), sizeof(type), 0)) -#define omap_get_nr_config(tag, type, nr) \ - ((const type *) __omap_get_config((tag), sizeof(type), (nr))) - -extern const void *__init omap_get_var_config(u16 tag, size_t *len); - -extern struct omap_board_config_kernel *omap_board_config; -extern int omap_board_config_size; - - -/* for TI reference platforms sharing the same debug card */ -extern int debug_card_init(u32 addr, unsigned gpio); - -/* OMAP3EVM revision */ -#if defined(CONFIG_MACH_OMAP3EVM) -u8 get_omap3_evm_rev(void); -#else -#define get_omap3_evm_rev() (-EINVAL) -#endif -#endif diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index bb5d08a70dbc..67da857783ce 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -30,6 +30,8 @@ #ifndef __ASM_ARCH_OMAP_CPU_H #define __ASM_ARCH_OMAP_CPU_H +#ifndef __ASSEMBLY__ + #include <linux/bitops.h> #include <plat/multi.h> @@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ) OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index c5811d4409b0..0a87b052f8f7 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -31,6 +31,8 @@ /* Move omap4 specific defines to dma-44xx.h */ #include "dma-44xx.h" +#define INT_DMA_LCD 25 + /* DMA channels for omap1 */ #define OMAP_DMA_NO_DEVICE 0 #define OMAP_DMA_MCSI1_TX 1 diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h deleted file mode 100644 index 5927709b1908..000000000000 --- a/arch/arm/plat-omap/include/plat/dsp.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef __OMAP_DSP_H__ -#define __OMAP_DSP_H__ - -#include <linux/types.h> - -struct omap_dsp_platform_data { - void (*dsp_set_min_opp) (u8 opp_id); - u8 (*dsp_get_opp) (void); - void (*cpu_set_freq) (unsigned long f); - unsigned long (*cpu_get_freq) (void); - unsigned long mpu_speed[6]; - - /* functions to write and read PRCM registers */ - void (*dsp_prm_write)(u32, s16 , u16); - u32 (*dsp_prm_read)(s16 , u16); - u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16); - void (*dsp_cm_write)(u32, s16 , u16); - u32 (*dsp_cm_read)(s16 , u16); - u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); - - void (*set_bootaddr)(u32); - void (*set_bootmode)(u8); - - phys_addr_t phys_mempool_base; - phys_addr_t phys_mempool_size; -}; - -#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE) -extern void omap_dsp_reserve_sdram_memblock(void); -#else -static inline void omap_dsp_reserve_sdram_memblock(void) { } -#endif - -#endif diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h deleted file mode 100644 index 10da0e07c0cf..000000000000 --- a/arch/arm/plat-omap/include/plat/gpio-switch.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * GPIO switch definitions - * - * Copyright (C) 2006 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H -#define __ASM_ARCH_OMAP_GPIO_SWITCH_H - -#include <linux/types.h> - -/* Cover: - * high -> closed - * low -> open - * Connection: - * high -> connected - * low -> disconnected - * Activity: - * high -> active - * low -> inactive - * - */ -#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000 -#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001 -#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002 -#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001 -#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002 - -struct omap_gpio_switch { - const char *name; - s16 gpio; - unsigned flags:4; - unsigned type:4; - - /* Time in ms to debounce when transitioning from - * inactive state to active state. */ - u16 debounce_rising; - /* Same for transition from active to inactive state. */ - u16 debounce_falling; - - /* notify board-specific code about state changes */ - void (* notify)(void *data, int state); - void *notify_data; -}; - -/* Call at init time only */ -extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl, - int count); - -#endif diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h deleted file mode 100644 index 50fb7cc000ea..000000000000 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/gpio.h - * - * OMAP GPIO handling defines and functions - * - * Copyright (C) 2003-2005 Nokia Corporation - * - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_OMAP_GPIO_H -#define __ASM_ARCH_OMAP_GPIO_H - -#include <linux/io.h> -#include <linux/platform_device.h> -#include <mach/irqs.h> - -#define OMAP1_MPUIO_BASE 0xfffb5000 - -/* - * These are the omap15xx/16xx offsets. The omap7xx offset are - * OMAP_MPUIO_ / 2 offsets below. - */ -#define OMAP_MPUIO_INPUT_LATCH 0x00 -#define OMAP_MPUIO_OUTPUT 0x04 -#define OMAP_MPUIO_IO_CNTL 0x08 -#define OMAP_MPUIO_KBR_LATCH 0x10 -#define OMAP_MPUIO_KBC 0x14 -#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18 -#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c -#define OMAP_MPUIO_KBD_INT 0x20 -#define OMAP_MPUIO_GPIO_INT 0x24 -#define OMAP_MPUIO_KBD_MASKIT 0x28 -#define OMAP_MPUIO_GPIO_MASKIT 0x2c -#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 -#define OMAP_MPUIO_LATCH 0x34 - -#define OMAP34XX_NR_GPIOS 6 - -/* - * OMAP1510 GPIO registers - */ -#define OMAP1510_GPIO_DATA_INPUT 0x00 -#define OMAP1510_GPIO_DATA_OUTPUT 0x04 -#define OMAP1510_GPIO_DIR_CONTROL 0x08 -#define OMAP1510_GPIO_INT_CONTROL 0x0c -#define OMAP1510_GPIO_INT_MASK 0x10 -#define OMAP1510_GPIO_INT_STATUS 0x14 -#define OMAP1510_GPIO_PIN_CONTROL 0x18 - -#define OMAP1510_IH_GPIO_BASE 64 - -/* - * OMAP1610 specific GPIO registers - */ -#define OMAP1610_GPIO_REVISION 0x0000 -#define OMAP1610_GPIO_SYSCONFIG 0x0010 -#define OMAP1610_GPIO_SYSSTATUS 0x0014 -#define OMAP1610_GPIO_IRQSTATUS1 0x0018 -#define OMAP1610_GPIO_IRQENABLE1 0x001c -#define OMAP1610_GPIO_WAKEUPENABLE 0x0028 -#define OMAP1610_GPIO_DATAIN 0x002c -#define OMAP1610_GPIO_DATAOUT 0x0030 -#define OMAP1610_GPIO_DIRECTION 0x0034 -#define OMAP1610_GPIO_EDGE_CTRL1 0x0038 -#define OMAP1610_GPIO_EDGE_CTRL2 0x003c -#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c -#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 -#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 -#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc -#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 -#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 - -/* - * OMAP7XX specific GPIO registers - */ -#define OMAP7XX_GPIO_DATA_INPUT 0x00 -#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 -#define OMAP7XX_GPIO_DIR_CONTROL 0x08 -#define OMAP7XX_GPIO_INT_CONTROL 0x0c -#define OMAP7XX_GPIO_INT_MASK 0x10 -#define OMAP7XX_GPIO_INT_STATUS 0x14 - -/* - * omap2+ specific GPIO registers - */ -#define OMAP24XX_GPIO_REVISION 0x0000 -#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 -#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 -#define OMAP24XX_GPIO_IRQENABLE2 0x002c -#define OMAP24XX_GPIO_IRQENABLE1 0x001c -#define OMAP24XX_GPIO_WAKE_EN 0x0020 -#define OMAP24XX_GPIO_CTRL 0x0030 -#define OMAP24XX_GPIO_OE 0x0034 -#define OMAP24XX_GPIO_DATAIN 0x0038 -#define OMAP24XX_GPIO_DATAOUT 0x003c -#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 -#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 -#define OMAP24XX_GPIO_RISINGDETECT 0x0048 -#define OMAP24XX_GPIO_FALLINGDETECT 0x004c -#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 -#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 -#define OMAP24XX_GPIO_SETWKUENA 0x0084 -#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 -#define OMAP24XX_GPIO_SETDATAOUT 0x0094 - -#define OMAP4_GPIO_REVISION 0x0000 -#define OMAP4_GPIO_EOI 0x0020 -#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 -#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 -#define OMAP4_GPIO_IRQSTATUS0 0x002c -#define OMAP4_GPIO_IRQSTATUS1 0x0030 -#define OMAP4_GPIO_IRQSTATUSSET0 0x0034 -#define OMAP4_GPIO_IRQSTATUSSET1 0x0038 -#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c -#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 -#define OMAP4_GPIO_IRQWAKEN0 0x0044 -#define OMAP4_GPIO_IRQWAKEN1 0x0048 -#define OMAP4_GPIO_IRQENABLE1 0x011c -#define OMAP4_GPIO_WAKE_EN 0x0120 -#define OMAP4_GPIO_IRQSTATUS2 0x0128 -#define OMAP4_GPIO_IRQENABLE2 0x012c -#define OMAP4_GPIO_CTRL 0x0130 -#define OMAP4_GPIO_OE 0x0134 -#define OMAP4_GPIO_DATAIN 0x0138 -#define OMAP4_GPIO_DATAOUT 0x013c -#define OMAP4_GPIO_LEVELDETECT0 0x0140 -#define OMAP4_GPIO_LEVELDETECT1 0x0144 -#define OMAP4_GPIO_RISINGDETECT 0x0148 -#define OMAP4_GPIO_FALLINGDETECT 0x014c -#define OMAP4_GPIO_DEBOUNCENABLE 0x0150 -#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 -#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP4_GPIO_SETIRQENABLE1 0x0164 -#define OMAP4_GPIO_CLEARWKUENA 0x0180 -#define OMAP4_GPIO_SETWKUENA 0x0184 -#define OMAP4_GPIO_CLEARDATAOUT 0x0190 -#define OMAP4_GPIO_SETDATAOUT 0x0194 - -#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) -#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) - -struct omap_gpio_dev_attr { - int bank_width; /* GPIO bank width */ - bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ -}; - -struct omap_gpio_reg_offs { - u16 revision; - u16 direction; - u16 datain; - u16 dataout; - u16 set_dataout; - u16 clr_dataout; - u16 irqstatus; - u16 irqstatus2; - u16 irqstatus_raw0; - u16 irqstatus_raw1; - u16 irqenable; - u16 irqenable2; - u16 set_irqenable; - u16 clr_irqenable; - u16 debounce; - u16 debounce_en; - u16 ctrl; - u16 wkup_en; - u16 leveldetect0; - u16 leveldetect1; - u16 risingdetect; - u16 fallingdetect; - u16 irqctrl; - u16 edgectrl1; - u16 edgectrl2; - u16 pinctrl; - - bool irqenable_inv; -}; - -struct omap_gpio_platform_data { - int bank_type; - int bank_width; /* GPIO bank width */ - int bank_stride; /* Only needed for omap1 MPUIO */ - bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ - bool loses_context; /* whether the bank would ever lose context */ - bool is_mpuio; /* whether the bank is of type MPUIO */ - u32 non_wakeup_gpios; - - struct omap_gpio_reg_offs *regs; - - /* Return context loss count due to PM states changing */ - int (*get_context_loss_count)(struct device *dev); -}; - -extern void omap2_gpio_prepare_for_idle(int off_mode); -extern void omap2_gpio_resume_after_idle(void); -extern void omap_set_gpio_debounce(int gpio, int enable); -extern void omap_set_gpio_debounce_time(int gpio, int enable); -/*-------------------------------------------------------------------------*/ - -/* - * Wrappers for "new style" GPIO calls, using the new infrastructure - * which lets us plug in FPGA, I2C, and other implementations. - * - * The original OMAP-specific calls should eventually be removed. - */ - -#include <linux/errno.h> -#include <asm-generic/gpio.h> - -#endif diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index f37764a36072..2e6e2597178c 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -133,6 +133,25 @@ struct gpmc_timings { u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ }; +struct gpmc_nand_regs { + void __iomem *gpmc_status; + void __iomem *gpmc_nand_command; + void __iomem *gpmc_nand_address; + void __iomem *gpmc_nand_data; + void __iomem *gpmc_prefetch_config1; + void __iomem *gpmc_prefetch_config2; + void __iomem *gpmc_prefetch_control; + void __iomem *gpmc_prefetch_status; + void __iomem *gpmc_ecc_config; + void __iomem *gpmc_ecc_control; + void __iomem *gpmc_ecc_size_config; + void __iomem *gpmc_ecc1_result; + void __iomem *gpmc_bch_result0; +}; + +extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); +extern int gpmc_get_client_irq(unsigned irq_config); + extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h deleted file mode 100644 index ddbde38e1e33..000000000000 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/hardware.h - * - * Hardware definitions for TI OMAP processors and boards - * - * NOTE: Please put device driver specific defines into a separate header - * file for each driver. - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> - * - * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> - * and Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_HARDWARE_H -#define __ASM_ARCH_OMAP_HARDWARE_H - -#include <asm/sizes.h> -#ifndef __ASSEMBLER__ -#include <asm/types.h> -#include <plat/cpu.h> -#endif -#include <plat/serial.h> - -/* - * --------------------------------------------------------------------------- - * Common definitions for all OMAP processors - * NOTE: Put all processor or board specific parts to the special header - * files. - * --------------------------------------------------------------------------- - */ - -/* - * ---------------------------------------------------------------------------- - * Timers - * ---------------------------------------------------------------------------- - */ -#define OMAP_MPU_TIMER1_BASE (0xfffec500) -#define OMAP_MPU_TIMER2_BASE (0xfffec600) -#define OMAP_MPU_TIMER3_BASE (0xfffec700) -#define MPU_TIMER_FREE (1 << 6) -#define MPU_TIMER_CLOCK_ENABLE (1 << 5) -#define MPU_TIMER_AR (1 << 1) -#define MPU_TIMER_ST (1 << 0) - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_BASE (0xfffece00) -#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) -#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) -#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) -#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) -#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) -#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) -#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) -#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#define SETARM_IDLE_SHIFT - -/* DPLL control registers */ -#define DPLL_CTL (0xfffecf00) - -/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ -#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) -#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) -#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) -#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) -#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) - -/* - * --------------------------------------------------------------------------- - * UPLD - * --------------------------------------------------------------------------- - */ -#define ULPD_REG_BASE (0xfffe0800) -#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) -#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) -#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) -# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ -# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ -#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) -# define SOFT_UDC_REQ (1 << 4) -# define SOFT_USB_CLK_REQ (1 << 3) -# define SOFT_DPLL_REQ (1 << 0) -#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) -#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) -#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) -#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) -#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) -# define DIS_MMC2_DPLL_REQ (1 << 11) -# define DIS_MMC1_DPLL_REQ (1 << 10) -# define DIS_UART3_DPLL_REQ (1 << 9) -# define DIS_UART2_DPLL_REQ (1 << 8) -# define DIS_UART1_DPLL_REQ (1 << 7) -# define DIS_USB_HOST_DPLL_REQ (1 << 6) -#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) -#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) - -/* - * --------------------------------------------------------------------------- - * Watchdog timer - * --------------------------------------------------------------------------- - */ - -/* Watchdog timer within the OMAP3.2 gigacell */ -#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) -#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) -#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * Interrupts - * --------------------------------------------------------------------------- - */ -#ifdef CONFIG_ARCH_OMAP1 - -/* - * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c - * or something similar.. -- PFM. - */ - -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 - -#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) -#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) -#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) -#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) -#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) -#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) -#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) - -#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) -#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) -#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) -#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) -#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) -#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) -#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) - -#define IRQ_ITR_REG_OFFSET 0x00 -#define IRQ_MIR_REG_OFFSET 0x04 -#define IRQ_SIR_IRQ_REG_OFFSET 0x10 -#define IRQ_SIR_FIQ_REG_OFFSET 0x14 -#define IRQ_CONTROL_REG_OFFSET 0x18 -#define IRQ_ISR_REG_OFFSET 0x9c -#define IRQ_ILR0_REG_OFFSET 0x1c -#define IRQ_GMR_REG_OFFSET 0xa0 - -#endif - -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define MOD_CONF_CTRL_0 0xfffe1080 -#define MOD_CONF_CTRL_1 0xfffe1110 - -/* - * ---------------------------------------------------------------------------- - * Pin multiplexing registers - * ---------------------------------------------------------------------------- - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define PULL_DWN_CTRL_4 0xfffe10ac - -/* OMAP-1610 specific multiplexing registers */ -#define FUNC_MUX_CTRL_E 0xfffe1090 -#define FUNC_MUX_CTRL_F 0xfffe1094 -#define FUNC_MUX_CTRL_10 0xfffe1098 -#define FUNC_MUX_CTRL_11 0xfffe109c -#define FUNC_MUX_CTRL_12 0xfffe10a0 -#define PU_PD_SEL_0 0xfffe10b4 -#define PU_PD_SEL_1 0xfffe10b8 -#define PU_PD_SEL_2 0xfffe10bc -#define PU_PD_SEL_3 0xfffe10c0 -#define PU_PD_SEL_4 0xfffe10c4 - -/* Timer32K for 1610 and 1710*/ -#define OMAP_TIMER32K_BASE 0xFFFBC400 - -/* - * --------------------------------------------------------------------------- - * TIPB bus interface - * --------------------------------------------------------------------------- - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * ---------------------------------------------------------------------------- - * MPUI interface - * ---------------------------------------------------------------------------- - */ -#define MPUI_BASE (0xfffec900) -#define MPUI_CTRL (MPUI_BASE + 0x0) -#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) -#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) -#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) -#define MPUI_STATUS_REG (MPUI_BASE + 0x10) -#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) -#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) -#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) - -/* - * ---------------------------------------------------------------------------- - * LED Pulse Generator - * ---------------------------------------------------------------------------- - */ -#define OMAP_LPG1_BASE 0xfffbd000 -#define OMAP_LPG2_BASE 0xfffbd800 -#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) -#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) -#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) -#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) - -/* - * ---------------------------------------------------------------------------- - * Pulse-Width Light - * ---------------------------------------------------------------------------- - */ -#define OMAP_PWL_BASE 0xfffb5800 -#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) -#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) - -/* - * --------------------------------------------------------------------------- - * Processor specific defines - * --------------------------------------------------------------------------- - */ - -#include <plat/omap7xx.h> -#include <plat/omap1510.h> -#include <plat/omap16xx.h> -#include <plat/omap24xx.h> -#include <plat/omap34xx.h> -#include <plat/omap44xx.h> -#include <plat/ti81xx.h> -#include <plat/am33xx.h> -#include <plat/omap54xx.h> - -#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h deleted file mode 100644 index 518322c80116..000000000000 --- a/arch/arm/plat-omap/include/plat/irqs-44xx.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * OMAP4 Interrupt lines definitions - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H -#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H - -/* OMAP44XX IRQs numbers definitions */ -#define OMAP44XX_IRQ_LOCALTIMER 29 -#define OMAP44XX_IRQ_LOCALWDT 30 - -#define OMAP44XX_IRQ_GIC_START 32 - -#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START) -#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START) - -#endif diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h deleted file mode 100644 index 37bbbbb981b2..000000000000 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/irqs.h - * - * Copyright (C) Greg Lonnon 2001 - * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 - * are different. - */ - -#ifndef __ASM_ARCH_OMAP15XX_IRQS_H -#define __ASM_ARCH_OMAP15XX_IRQS_H - -/* All OMAP4 specific defines are moved to irqs-44xx.h */ -#include "irqs-44xx.h" - -/* - * IRQ numbers for interrupt handler 1 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - * - */ -#define INT_CAMERA 1 -#define INT_FIQ 3 -#define INT_RTDX 6 -#define INT_DSP_MMU_ABORT 7 -#define INT_HOST 8 -#define INT_ABORT 9 -#define INT_BRIDGE_PRIV 13 -#define INT_GPIO_BANK1 14 -#define INT_UART3 15 -#define INT_TIMER3 16 -#define INT_DMA_CH0_6 19 -#define INT_DMA_CH1_7 20 -#define INT_DMA_CH2_8 21 -#define INT_DMA_CH3 22 -#define INT_DMA_CH4 23 -#define INT_DMA_CH5 24 -#define INT_DMA_LCD 25 -#define INT_TIMER1 26 -#define INT_WD_TIMER 27 -#define INT_BRIDGE_PUB 28 -#define INT_TIMER2 30 -#define INT_LCD_CTRL 31 - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1510_IH2_IRQ 0 -#define INT_1510_RES2 2 -#define INT_1510_SPI_TX 4 -#define INT_1510_SPI_RX 5 -#define INT_1510_DSP_MAILBOX1 10 -#define INT_1510_DSP_MAILBOX2 11 -#define INT_1510_RES12 12 -#define INT_1510_LB_MMU 17 -#define INT_1510_RES18 18 -#define INT_1510_LOCAL_BUS 29 - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ -#define INT_1610_IH2_FIQ 2 -#define INT_1610_McBSP2_TX 4 -#define INT_1610_McBSP2_RX 5 -#define INT_1610_DSP_MAILBOX1 10 -#define INT_1610_DSP_MAILBOX2 11 -#define INT_1610_LCD_LINE 12 -#define INT_1610_GPTIMER1 17 -#define INT_1610_GPTIMER2 18 -#define INT_1610_SSR_FIFO_0 29 - -/* - * OMAP-7xx specific IRQ numbers for interrupt handler 1 - */ -#define INT_7XX_IH2_FIQ 0 -#define INT_7XX_IH2_IRQ 1 -#define INT_7XX_USB_NON_ISO 2 -#define INT_7XX_USB_ISO 3 -#define INT_7XX_ICR 4 -#define INT_7XX_EAC 5 -#define INT_7XX_GPIO_BANK1 6 -#define INT_7XX_GPIO_BANK2 7 -#define INT_7XX_GPIO_BANK3 8 -#define INT_7XX_McBSP2TX 10 -#define INT_7XX_McBSP2RX 11 -#define INT_7XX_McBSP2RX_OVF 12 -#define INT_7XX_LCD_LINE 14 -#define INT_7XX_GSM_PROTECT 15 -#define INT_7XX_TIMER3 16 -#define INT_7XX_GPIO_BANK5 17 -#define INT_7XX_GPIO_BANK6 18 -#define INT_7XX_SPGIO_WR 29 - -/* - * IRQ numbers for interrupt handler 2 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - */ -#define IH2_BASE 32 - -#define INT_KEYBOARD (1 + IH2_BASE) -#define INT_uWireTX (2 + IH2_BASE) -#define INT_uWireRX (3 + IH2_BASE) -#define INT_I2C (4 + IH2_BASE) -#define INT_MPUIO (5 + IH2_BASE) -#define INT_USB_HHC_1 (6 + IH2_BASE) -#define INT_McBSP3TX (10 + IH2_BASE) -#define INT_McBSP3RX (11 + IH2_BASE) -#define INT_McBSP1TX (12 + IH2_BASE) -#define INT_McBSP1RX (13 + IH2_BASE) -#define INT_UART1 (14 + IH2_BASE) -#define INT_UART2 (15 + IH2_BASE) -#define INT_BT_MCSI1TX (16 + IH2_BASE) -#define INT_BT_MCSI1RX (17 + IH2_BASE) -#define INT_SOSSI_MATCH (19 + IH2_BASE) -#define INT_USB_W2FC (20 + IH2_BASE) -#define INT_1WIRE (21 + IH2_BASE) -#define INT_OS_TIMER (22 + IH2_BASE) -#define INT_MMC (23 + IH2_BASE) -#define INT_GAUGE_32K (24 + IH2_BASE) -#define INT_RTC_TIMER (25 + IH2_BASE) -#define INT_RTC_ALARM (26 + IH2_BASE) -#define INT_MEM_STICK (27 + IH2_BASE) - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1510_DSP_MMU (28 + IH2_BASE) -#define INT_1510_COM_SPI_RO (31 + IH2_BASE) - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1610_FAC (0 + IH2_BASE) -#define INT_1610_USB_HHC_2 (7 + IH2_BASE) -#define INT_1610_USB_OTG (8 + IH2_BASE) -#define INT_1610_SoSSI (9 + IH2_BASE) -#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) -#define INT_1610_DSP_MMU (28 + IH2_BASE) -#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) -#define INT_1610_STI (32 + IH2_BASE) -#define INT_1610_STI_WAKEUP (33 + IH2_BASE) -#define INT_1610_GPTIMER3 (34 + IH2_BASE) -#define INT_1610_GPTIMER4 (35 + IH2_BASE) -#define INT_1610_GPTIMER5 (36 + IH2_BASE) -#define INT_1610_GPTIMER6 (37 + IH2_BASE) -#define INT_1610_GPTIMER7 (38 + IH2_BASE) -#define INT_1610_GPTIMER8 (39 + IH2_BASE) -#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) -#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) -#define INT_1610_MMC2 (42 + IH2_BASE) -#define INT_1610_CF (43 + IH2_BASE) -#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) -#define INT_1610_SPI (49 + IH2_BASE) -#define INT_1610_DMA_CH6 (53 + IH2_BASE) -#define INT_1610_DMA_CH7 (54 + IH2_BASE) -#define INT_1610_DMA_CH8 (55 + IH2_BASE) -#define INT_1610_DMA_CH9 (56 + IH2_BASE) -#define INT_1610_DMA_CH10 (57 + IH2_BASE) -#define INT_1610_DMA_CH11 (58 + IH2_BASE) -#define INT_1610_DMA_CH12 (59 + IH2_BASE) -#define INT_1610_DMA_CH13 (60 + IH2_BASE) -#define INT_1610_DMA_CH14 (61 + IH2_BASE) -#define INT_1610_DMA_CH15 (62 + IH2_BASE) -#define INT_1610_NAND (63 + IH2_BASE) -#define INT_1610_SHA1MD5 (91 + IH2_BASE) - -/* - * OMAP-7xx specific IRQ numbers for interrupt handler 2 - */ -#define INT_7XX_HW_ERRORS (0 + IH2_BASE) -#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) -#define INT_7XX_CFCD (2 + IH2_BASE) -#define INT_7XX_CFIREQ (3 + IH2_BASE) -#define INT_7XX_I2C (4 + IH2_BASE) -#define INT_7XX_PCC (5 + IH2_BASE) -#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) -#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) -#define INT_7XX_SYREN_SPI (8 + IH2_BASE) -#define INT_7XX_VLYNQ (9 + IH2_BASE) -#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) -#define INT_7XX_McBSP1TX (11 + IH2_BASE) -#define INT_7XX_McBSP1RX (12 + IH2_BASE) -#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) -#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) -#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) -#define INT_7XX_MCSI (16 + IH2_BASE) -#define INT_7XX_uWireTX (17 + IH2_BASE) -#define INT_7XX_uWireRX (18 + IH2_BASE) -#define INT_7XX_SMC_CD (19 + IH2_BASE) -#define INT_7XX_SMC_IREQ (20 + IH2_BASE) -#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) -#define INT_7XX_TIMER32K (22 + IH2_BASE) -#define INT_7XX_MMC_SDIO (23 + IH2_BASE) -#define INT_7XX_UPLD (24 + IH2_BASE) -#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) -#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) -#define INT_7XX_USB_GENI (29 + IH2_BASE) -#define INT_7XX_USB_OTG (30 + IH2_BASE) -#define INT_7XX_CAMERA_IF (31 + IH2_BASE) -#define INT_7XX_RNG (32 + IH2_BASE) -#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) -#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) -#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) -#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) -#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) -#define INT_7XX_RNG_IDLE (38 + IH2_BASE) -#define INT_7XX_MPUIO (39 + IH2_BASE) -#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) -#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) -#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) -#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) -#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_7XX_DMA_CH6 (53 + IH2_BASE) -#define INT_7XX_DMA_CH7 (54 + IH2_BASE) -#define INT_7XX_DMA_CH8 (55 + IH2_BASE) -#define INT_7XX_DMA_CH9 (56 + IH2_BASE) -#define INT_7XX_DMA_CH10 (57 + IH2_BASE) -#define INT_7XX_DMA_CH11 (58 + IH2_BASE) -#define INT_7XX_DMA_CH12 (59 + IH2_BASE) -#define INT_7XX_DMA_CH13 (60 + IH2_BASE) -#define INT_7XX_DMA_CH14 (61 + IH2_BASE) -#define INT_7XX_DMA_CH15 (62 + IH2_BASE) -#define INT_7XX_NAND (63 + IH2_BASE) - -#define INT_24XX_SYS_NIRQ 7 -#define INT_24XX_SDMA_IRQ0 12 -#define INT_24XX_SDMA_IRQ1 13 -#define INT_24XX_SDMA_IRQ2 14 -#define INT_24XX_SDMA_IRQ3 15 -#define INT_24XX_CAM_IRQ 24 -#define INT_24XX_DSS_IRQ 25 -#define INT_24XX_MAIL_U0_MPU 26 -#define INT_24XX_DSP_UMA 27 -#define INT_24XX_DSP_MMU 28 -#define INT_24XX_GPIO_BANK1 29 -#define INT_24XX_GPIO_BANK2 30 -#define INT_24XX_GPIO_BANK3 31 -#define INT_24XX_GPIO_BANK4 32 -#define INT_24XX_GPIO_BANK5 33 -#define INT_24XX_MAIL_U3_MPU 34 -#define INT_24XX_GPTIMER1 37 -#define INT_24XX_GPTIMER2 38 -#define INT_24XX_GPTIMER3 39 -#define INT_24XX_GPTIMER4 40 -#define INT_24XX_GPTIMER5 41 -#define INT_24XX_GPTIMER6 42 -#define INT_24XX_GPTIMER7 43 -#define INT_24XX_GPTIMER8 44 -#define INT_24XX_GPTIMER9 45 -#define INT_24XX_GPTIMER10 46 -#define INT_24XX_GPTIMER11 47 -#define INT_24XX_GPTIMER12 48 -#define INT_24XX_SHA1MD5 51 -#define INT_24XX_MCBSP4_IRQ_TX 54 -#define INT_24XX_MCBSP4_IRQ_RX 55 -#define INT_24XX_I2C1_IRQ 56 -#define INT_24XX_I2C2_IRQ 57 -#define INT_24XX_HDQ_IRQ 58 -#define INT_24XX_MCBSP1_IRQ_TX 59 -#define INT_24XX_MCBSP1_IRQ_RX 60 -#define INT_24XX_MCBSP2_IRQ_TX 62 -#define INT_24XX_MCBSP2_IRQ_RX 63 -#define INT_24XX_SPI1_IRQ 65 -#define INT_24XX_SPI2_IRQ 66 -#define INT_24XX_UART1_IRQ 72 -#define INT_24XX_UART2_IRQ 73 -#define INT_24XX_UART3_IRQ 74 -#define INT_24XX_USB_IRQ_GEN 75 -#define INT_24XX_USB_IRQ_NISO 76 -#define INT_24XX_USB_IRQ_ISO 77 -#define INT_24XX_USB_IRQ_HGEN 78 -#define INT_24XX_USB_IRQ_HSOF 79 -#define INT_24XX_USB_IRQ_OTG 80 -#define INT_24XX_MCBSP5_IRQ_TX 81 -#define INT_24XX_MCBSP5_IRQ_RX 82 -#define INT_24XX_MMC_IRQ 83 -#define INT_24XX_MMC2_IRQ 86 -#define INT_24XX_MCBSP3_IRQ_TX 89 -#define INT_24XX_MCBSP3_IRQ_RX 90 -#define INT_24XX_SPI3_IRQ 91 - -#define INT_243X_MCBSP2_IRQ 16 -#define INT_243X_MCBSP3_IRQ 17 -#define INT_243X_MCBSP4_IRQ 18 -#define INT_243X_MCBSP5_IRQ 19 -#define INT_243X_MCBSP1_IRQ 64 -#define INT_243X_HS_USB_MC 92 -#define INT_243X_HS_USB_DMA 93 -#define INT_243X_CARKIT_IRQ 94 - -#define INT_34XX_BENCH_MPU_EMUL 3 -#define INT_34XX_ST_MCBSP2_IRQ 4 -#define INT_34XX_ST_MCBSP3_IRQ 5 -#define INT_34XX_SSM_ABORT_IRQ 6 -#define INT_34XX_SYS_NIRQ 7 -#define INT_34XX_D2D_FW_IRQ 8 -#define INT_34XX_L3_DBG_IRQ 9 -#define INT_34XX_L3_APP_IRQ 10 -#define INT_34XX_PRCM_MPU_IRQ 11 -#define INT_34XX_MCBSP1_IRQ 16 -#define INT_34XX_MCBSP2_IRQ 17 -#define INT_34XX_GPMC_IRQ 20 -#define INT_34XX_MCBSP3_IRQ 22 -#define INT_34XX_MCBSP4_IRQ 23 -#define INT_34XX_CAM_IRQ 24 -#define INT_34XX_MCBSP5_IRQ 27 -#define INT_34XX_GPIO_BANK1 29 -#define INT_34XX_GPIO_BANK2 30 -#define INT_34XX_GPIO_BANK3 31 -#define INT_34XX_GPIO_BANK4 32 -#define INT_34XX_GPIO_BANK5 33 -#define INT_34XX_GPIO_BANK6 34 -#define INT_34XX_USIM_IRQ 35 -#define INT_34XX_WDT3_IRQ 36 -#define INT_34XX_SPI4_IRQ 48 -#define INT_34XX_SHA1MD52_IRQ 49 -#define INT_34XX_FPKA_READY_IRQ 50 -#define INT_34XX_SHA1MD51_IRQ 51 -#define INT_34XX_RNG_IRQ 52 -#define INT_34XX_I2C3_IRQ 61 -#define INT_34XX_FPKA_ERROR_IRQ 64 -#define INT_34XX_PBIAS_IRQ 75 -#define INT_34XX_OHCI_IRQ 76 -#define INT_34XX_EHCI_IRQ 77 -#define INT_34XX_TLL_IRQ 78 -#define INT_34XX_PARTHASH_IRQ 79 -#define INT_34XX_MMC3_IRQ 94 -#define INT_34XX_GPT12_IRQ 95 - -#define INT_36XX_UART4_IRQ 80 - -#define INT_35XX_HECC0_IRQ 24 -#define INT_35XX_HECC1_IRQ 28 -#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 -#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68 -#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69 -#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70 -#define INT_35XX_USBOTG_IRQ 71 -#define INT_35XX_UART4_IRQ 84 -#define INT_35XX_CCDC_VD0_IRQ 88 -#define INT_35XX_CCDC_VD1_IRQ 92 -#define INT_35XX_CCDC_VD2_IRQ 93 - -/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and - * 16 MPUIO lines */ -#define OMAP_MAX_GPIO_LINES 192 -#define IH_GPIO_BASE (128 + IH2_BASE) -#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) -#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) - -/* External FPGA handles interrupts on Innovator boards */ -#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) -#ifdef CONFIG_MACH_OMAP_INNOVATOR -#define OMAP_FPGA_NR_IRQS 24 -#else -#define OMAP_FPGA_NR_IRQS 0 -#endif -#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) - -/* External TWL4030 can handle interrupts on 2430 and 34xx boards */ -#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) -#ifdef CONFIG_TWL4030_CORE -#define TWL4030_BASE_NR_IRQS 8 -#define TWL4030_PWR_NR_IRQS 8 -#else -#define TWL4030_BASE_NR_IRQS 0 -#define TWL4030_PWR_NR_IRQS 0 -#endif -#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) -#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END -#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) - -/* External TWL4030 gpio interrupts are optional */ -#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END -#ifdef CONFIG_GPIO_TWL4030 -#define TWL4030_GPIO_NR_IRQS 18 -#else -#define TWL4030_GPIO_NR_IRQS 0 -#endif -#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) - -#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END) -#ifdef CONFIG_TWL4030_CORE -#define TWL6030_BASE_NR_IRQS 20 -#else -#define TWL6030_BASE_NR_IRQS 0 -#endif -#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS) - -#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END -#ifdef CONFIG_TWL6040_CODEC -#define TWL6040_CODEC_NR_IRQS 6 -#else -#define TWL6040_CODEC_NR_IRQS 0 -#endif -#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS) - -/* Total number of interrupts depends on the enabled blocks above */ -#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END) -#define TWL_IRQ_END TWL4030_GPIO_IRQ_END -#else -#define TWL_IRQ_END TWL6040_CODEC_IRQ_END -#endif - -/* GPMC related */ -#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) -#define OMAP_GPMC_NR_IRQS 8 -#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) - -/* PRCM IRQ handler */ -#ifdef CONFIG_ARCH_OMAP2PLUS -#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END) -#define OMAP_PRCM_NR_IRQS 64 -#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS) -#else -#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END -#endif - -#define NR_IRQS OMAP_PRCM_IRQ_END - -#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) - -#define INTCPS_NR_MIR_REGS 3 -#define INTCPS_NR_IRQS 96 - -#include <mach/hardware.h> - -#ifdef CONFIG_FIQ -#define FIQ_START 1024 -#endif - -#endif diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h deleted file mode 100644 index a6b21eddb212..000000000000 --- a/arch/arm/plat-omap/include/plat/keypad.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/keypad.h - * - * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_KEYPAD_H -#define ASMARM_ARCH_KEYPAD_H - -#ifndef CONFIG_ARCH_OMAP1 -#warning Please update the board to use matrix-keypad driver -#define omap_readw(reg) 0 -#define omap_writew(val, reg) do {} while (0) -#endif -#include <linux/input/matrix_keypad.h> - -struct omap_kp_platform_data { - int rows; - int cols; - const struct matrix_keymap_data *keymap_data; - bool rep; - unsigned long delay; - bool dbounce; - /* specific to OMAP242x*/ - unsigned int *row_gpios; - unsigned int *col_gpios; -}; - -/* Group (0..3) -- when multiple keys are pressed, only the - * keys pressed in the same group are considered as pressed. This is - * in order to workaround certain crappy HW designs that produce ghost - * keypresses. Two free bits, not used by neither row/col nor keynum, - * must be available for use as group bits. The below GROUP_SHIFT - * macro definition is based on some prior knowledge of the - * matrix_keypad defined KEY() macro internals. - */ -#define GROUP_SHIFT 14 -#define GROUP_0 (0 << GROUP_SHIFT) -#define GROUP_1 (1 << GROUP_SHIFT) -#define GROUP_2 (2 << GROUP_SHIFT) -#define GROUP_3 (3 << GROUP_SHIFT) -#define GROUP_MASK GROUP_3 -#if KEY_MAX & GROUP_MASK -#error Group bits in conflict with keynum bits -#endif - - -#endif - diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h deleted file mode 100644 index 8e52c6572281..000000000000 --- a/arch/arm/plat-omap/include/plat/lcd_mipid.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __LCD_MIPID_H -#define __LCD_MIPID_H - -enum mipid_test_num { - MIPID_TEST_RGB_LINES, -}; - -enum mipid_test_result { - MIPID_TEST_SUCCESS, - MIPID_TEST_INVALID, - MIPID_TEST_FAILED, -}; - -#ifdef __KERNEL__ - -struct mipid_platform_data { - int nreset_gpio; - int data_lines; - - void (*shutdown)(struct mipid_platform_data *pdata); - void (*set_bklight_level)(struct mipid_platform_data *pdata, - int level); - int (*get_bklight_level)(struct mipid_platform_data *pdata); - int (*get_bklight_max)(struct mipid_platform_data *pdata); -}; - -#endif - -#endif diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h deleted file mode 100644 index 18814127809a..000000000000 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/mcbsp.h - * - * Defines for Multi-Channel Buffered Serial Port - * - * Copyright (C) 2002 RidgeRun, Inc. - * Author: Steve Johnson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ -#ifndef __ASM_ARCH_OMAP_MCBSP_H -#define __ASM_ARCH_OMAP_MCBSP_H - -#include <linux/spinlock.h> -#include <linux/clk.h> - -#define MCBSP_CONFIG_TYPE2 0x2 -#define MCBSP_CONFIG_TYPE3 0x3 -#define MCBSP_CONFIG_TYPE4 0x4 - -/* Platform specific configuration */ -struct omap_mcbsp_ops { - void (*request)(unsigned int); - void (*free)(unsigned int); -}; - -struct omap_mcbsp_platform_data { - struct omap_mcbsp_ops *ops; - u16 buffer_size; - u8 reg_size; - u8 reg_step; - - /* McBSP platform and instance specific features */ - bool has_wakeup; /* Wakeup capability */ - bool has_ccr; /* Transceiver has configuration control registers */ - int (*enable_st_clock)(unsigned int, bool); - int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src); - int (*mux_signal)(struct device *dev, const char *signal, const char *src); -}; - -/** - * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod - * @sidetone: name of the sidetone device - */ -struct omap_mcbsp_dev_attr { - const char *sidetone; -}; - -#endif diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h deleted file mode 100644 index a357eb26bd25..000000000000 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _OMAP2_MCSPI_H -#define _OMAP2_MCSPI_H - -#define OMAP2_MCSPI_REV 0 -#define OMAP3_MCSPI_REV 1 -#define OMAP4_MCSPI_REV 2 - -#define OMAP4_MCSPI_REG_OFFSET 0x100 - -struct omap2_mcspi_platform_config { - unsigned short num_cs; - unsigned int regs_offset; -}; - -struct omap2_mcspi_dev_attr { - unsigned short num_chipselect; -}; - -struct omap2_mcspi_device_config { - unsigned turbo_mode:1; -}; - -#endif diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index eb3e4d555343..8b4e4f2da2f5 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -15,7 +15,6 @@ #include <linux/device.h> #include <linux/mmc/host.h> -#include <plat/board.h> #include <plat/omap_hwmod.h> #define OMAP15XX_NR_MMC 1 diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h deleted file mode 100644 index 67fc5060183e..000000000000 --- a/arch/arm/plat-omap/include/plat/nand.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/nand.h - * - * Copyright (C) 2006 Micron Technology Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <plat/gpmc.h> -#include <linux/mtd/partitions.h> - -enum nand_io { - NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ - NAND_OMAP_POLLED, /* polled mode, without prefetch */ - NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ - NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ -}; - -struct omap_nand_platform_data { - int cs; - struct mtd_partition *parts; - struct gpmc_timings *gpmc_t; - int nr_parts; - bool dev_ready; - int gpmc_irq; - enum nand_io xfer_type; - unsigned long phys_base; - int devsize; - enum omap_ecc ecc_opt; -}; - -/* minimum size for IO mapping */ -#define NAND_IO_SIZE 4 - -#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) -extern int gpmc_nand_init(struct omap_nand_platform_data *d); -#else -static inline int gpmc_nand_init(struct omap_nand_platform_data *d) -{ - return 0; -} -#endif diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 1a52725ffcf2..f4a4cd014795 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -18,11 +18,9 @@ #define __OMAP_SERIAL_H__ #include <linux/serial_core.h> -#include <linux/platform_device.h> +#include <linux/device.h> #include <linux/pm_qos.h> -#include <plat/mux.h> - #define DRIVER_NAME "omap_uart" /* @@ -42,10 +40,10 @@ #define OMAP_UART_WER_MOD_WKUP 0X7F /* Enable XON/XOFF flow control on output */ -#define OMAP_UART_SW_TX 0x04 +#define OMAP_UART_SW_TX 0x8 /* Enable XON/XOFF flow control on input */ -#define OMAP_UART_SW_RX 0x04 +#define OMAP_UART_SW_RX 0x2 #define OMAP_UART_SYSC_RESET 0X07 #define OMAP_UART_TCR_TRIG 0X0F @@ -54,7 +52,7 @@ #define OMAP_UART_DMA_CH_FREE -1 -#define OMAP_MAX_HSUART_PORTS 4 +#define OMAP_MAX_HSUART_PORTS 6 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA @@ -69,11 +67,14 @@ struct omap_uart_port_info { unsigned int dma_rx_timeout; unsigned int autosuspend_timeout; unsigned int dma_rx_poll_rate; + int DTR_gpio; + int DTR_inverted; + int DTR_present; int (*get_context_loss_count)(struct device *); - void (*set_forceidle)(struct platform_device *); - void (*set_noidle)(struct platform_device *); - void (*enable_wakeup)(struct platform_device *, bool); + void (*set_forceidle)(struct device *); + void (*set_noidle)(struct device *); + void (*enable_wakeup)(struct device *, bool); }; struct uart_omap_dma { @@ -102,39 +103,4 @@ struct uart_omap_dma { unsigned int rx_timeout; }; -struct uart_omap_port { - struct uart_port port; - struct uart_omap_dma uart_dma; - struct platform_device *pdev; - - unsigned char ier; - unsigned char lcr; - unsigned char mcr; - unsigned char fcr; - unsigned char efr; - unsigned char dll; - unsigned char dlh; - unsigned char mdr1; - unsigned char scr; - - int use_dma; - /* - * Some bits in registers are cleared on a read, so they must - * be saved whenever the register is read but the bits will not - * be immediately processed. - */ - unsigned int lsr_break_flag; - unsigned char msr_saved_flags; - char name[20]; - unsigned long port_activity; - u32 context_loss_cnt; - u32 errata; - u8 wakeups_enabled; - - struct pm_qos_request pm_qos_request; - u32 latency; - u32 calc_latency; - struct work_struct qos_work; -}; - #endif /* __OMAP_SERIAL_H__ */ diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 4327b2c90c3d..e7259c0d33ec 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain; * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM * @_state: one of OMAP_DEVICE_STATE_* (see above) * @flags: device flags + * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h> * * Integrates omap_hwmod data into Linux platform_device. * @@ -73,6 +74,7 @@ struct omap_device { struct omap_device_pm_latency *pm_lats; u32 dev_wakeup_lat; u32 _dev_wakeup_lat_limit; + unsigned long _driver_status; u8 pm_lats_cnt; s8 pm_lat_level; u8 hwmods_cnt; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 6132972aff37..05330735f23f 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); +int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res); int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, const char *name, struct resource *res); @@ -658,6 +659,7 @@ extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); +extern int am33xx_hwmod_init(void); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h deleted file mode 100644 index 2858667d2e4f..000000000000 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/onenand.h - * - * Copyright (C) 2006 Nokia Corporation - * Author: Juha Yrjola - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#define ONENAND_SYNC_READ (1 << 0) -#define ONENAND_SYNC_READWRITE (1 << 1) - -struct onenand_freq_info { - u16 maf_id; - u16 dev_id; - u16 ver_id; -}; - -struct omap_onenand_platform_data { - int cs; - int gpio_irq; - struct mtd_partition *parts; - int nr_parts; - int (*onenand_setup)(void __iomem *, int *freq_ptr); - int (*get_freq)(const struct onenand_freq_info *freq_info, - bool *clk_dep); - int dma_channel; - u8 flags; - u8 regulator_can_sleep; - u8 skip_initial_unlocking; -}; - -#define ONENAND_MAX_PARTITIONS 8 - -#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ - defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) - -extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); - -#else - -#define board_onenand_data NULL - -static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) -{ -} - -#endif diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h deleted file mode 100644 index 1eb4dc326979..000000000000 --- a/arch/arm/plat-omap/include/plat/param.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/param.h - * - */ - -#ifdef CONFIG_OMAP_32K_TIMER_HZ -#define HZ CONFIG_OMAP_32K_TIMER_HZ -#endif diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h deleted file mode 100644 index b10eac89e2e9..000000000000 --- a/arch/arm/plat-omap/include/plat/remoteproc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Remote Processor - omap-specific bits - * - * Copyright (C) 2011 Texas Instruments, Inc. - * Copyright (C) 2011 Google, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PLAT_REMOTEPROC_H -#define _PLAT_REMOTEPROC_H - -struct rproc_ops; -struct platform_device; - -/* - * struct omap_rproc_pdata - omap remoteproc's platform data - * @name: the remoteproc's name - * @oh_name: omap hwmod device - * @oh_name_opt: optional, secondary omap hwmod device - * @firmware: name of firmware file to load - * @mbox_name: name of omap mailbox device to use with this rproc - * @ops: start/stop rproc handlers - * @device_enable: omap-specific handler for enabling a device - * @device_shutdown: omap-specific handler for shutting down a device - */ -struct omap_rproc_pdata { - const char *name; - const char *oh_name; - const char *oh_name_opt; - const char *firmware; - const char *mbox_name; - const struct rproc_ops *ops; - int (*device_enable) (struct platform_device *pdev); - int (*device_shutdown) (struct platform_device *pdev); -}; - -#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE) - -void __init omap_rproc_reserve_cma(void); - -#else - -void __init omap_rproc_reserve_cma(void) -{ -} - -#endif - -#endif /* _PLAT_REMOTEPROC_H */ diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 548a4c8d63df..bd20588c356b 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -5,7 +5,6 @@ #include <linux/io.h> #include <linux/usb/musb.h> -#include <plat/board.h> #define OMAP3_HS_USB_PORTS 3 diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h deleted file mode 100644 index 5be4d5def427..000000000000 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * OMAP Voltage Management Routines - * - * Copyright (C) 2011, Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_OMAP_VOLTAGE_H -#define __ARCH_ARM_OMAP_VOLTAGE_H - -/** - * struct omap_volt_data - Omap voltage specific data. - * @voltage_nominal: The possible voltage value in uV - * @sr_efuse_offs: The offset of the efuse register(from system - * control module base address) from where to read - * the n-target value for the smartreflex module. - * @sr_errminlimit: Error min limit value for smartreflex. This value - * differs at differnet opp and thus is linked - * with voltage. - * @vp_errorgain: Error gain value for the voltage processor. This - * field also differs according to the voltage/opp. - */ -struct omap_volt_data { - u32 volt_nominal; - u32 sr_efuse_offs; - u8 sr_errminlimit; - u8 vp_errgain; -}; -struct voltagedomain; - -struct voltagedomain *voltdm_lookup(const char *name); -int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); -unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); -struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, - unsigned long volt); -#endif diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c deleted file mode 100644 index cff8712122bb..000000000000 --- a/arch/arm/plat-omap/mux.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * linux/arch/arm/plat-omap/mux.c - * - * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h - * - * Copyright (C) 2003 - 2008 Nokia Corporation - * - * Written by Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ -#include <linux/module.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/spinlock.h> - -#include <asm/system.h> - -#include <plat/cpu.h> -#include <plat/mux.h> - -#ifdef CONFIG_OMAP_MUX - -static struct omap_mux_cfg *mux_cfg; - -int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) -{ - if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 - || !arch_mux_cfg->cfg_reg) { - printk(KERN_ERR "Invalid pin table\n"); - return -EINVAL; - } - - mux_cfg = arch_mux_cfg; - - return 0; -} - -/* - * Sets the Omap MUX and PULL_DWN registers based on the table - */ -int __init_or_module omap_cfg_reg(const unsigned long index) -{ - struct pin_config *reg; - - if (!cpu_class_is_omap1()) { - printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", - index); - WARN_ON(1); - return -EINVAL; - } - - if (mux_cfg == NULL) { - printk(KERN_ERR "Pin mux table not initialized\n"); - return -ENODEV; - } - - if (index >= mux_cfg->size) { - printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", - index, mux_cfg->size); - dump_stack(); - return -ENODEV; - } - - reg = (struct pin_config *)&mux_cfg->pins[index]; - - if (!mux_cfg->cfg_reg) - return -ENODEV; - - return mux_cfg->cfg_reg(reg); -} -EXPORT_SYMBOL(omap_cfg_reg); -#else -#define omap_mux_init() do {} while(0) -#define omap_cfg_reg(x) do {} while(0) -#endif /* CONFIG_OMAP_MUX */ diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index 5a97b4d98d41..9f6413324df9 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -41,11 +41,11 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) }; if (t == -1) - pr_debug("OMAP PM: remove max MPU wakeup latency constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n", + dev_name(dev)); else - pr_debug("OMAP PM: add max MPU wakeup latency constraint: " - "dev %s, t = %ld usec\n", dev_name(dev), t); + pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n", + dev_name(dev), t); /* * For current Linux, this needs to map the MPU to a @@ -70,11 +70,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) }; if (r == 0) - pr_debug("OMAP PM: remove min bus tput constraint: " - "dev %s for agent_id %d\n", dev_name(dev), agent_id); + pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n", + dev_name(dev), agent_id); else - pr_debug("OMAP PM: add min bus tput constraint: " - "dev %s for agent_id %d: rate %ld KiB\n", + pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n", dev_name(dev), agent_id, r); /* @@ -97,11 +96,11 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, }; if (t == -1) - pr_debug("OMAP PM: remove max device latency constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove max device latency constraint: dev %s\n", + dev_name(dev)); else - pr_debug("OMAP PM: add max device latency constraint: " - "dev %s, t = %ld usec\n", dev_name(dev), t); + pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n", + dev_name(dev), t); /* * For current Linux, this needs to map the device to a @@ -127,11 +126,11 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t) }; if (t == -1) - pr_debug("OMAP PM: remove max DMA latency constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n", + dev_name(dev)); else - pr_debug("OMAP PM: add max DMA latency constraint: " - "dev %s, t = %ld usec\n", dev_name(dev), t); + pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n", + dev_name(dev), t); /* * For current Linux PM QOS params, this code should scan the @@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r) } if (r == 0) - pr_debug("OMAP PM: remove min clk rate constraint: " - "dev %s\n", dev_name(dev)); + pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n", + dev_name(dev)); else - pr_debug("OMAP PM: add min clk rate constraint: " - "dev %s, rate = %ld Hz\n", dev_name(dev), r); + pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n", + dev_name(dev), r); /* * Code in a real implementation should keep track of these diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index c490240bb82c..d5f617c542d3 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -1,4 +1,3 @@ - /* * omap_device implementation * @@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) act_lat = timespec_to_ns(&c); dev_dbg(&od->pdev->dev, - "omap_device: pm_lat %d: activate: elapsed time " - "%llu nsec\n", od->pm_lat_level, act_lat); + "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n", + od->pm_lat_level, act_lat); if (act_lat > odpl->activate_lat) { odpl->activate_lat_worst = act_lat; if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { odpl->activate_lat = act_lat; dev_dbg(&od->pdev->dev, - "new worst case activate latency " - "%d: %llu\n", + "new worst case activate latency %d: %llu\n", od->pm_lat_level, act_lat); } else dev_warn(&od->pdev->dev, - "activate latency %d " - "higher than exptected. (%llu > %d)\n", + "activate latency %d higher than expected. (%llu > %d)\n", od->pm_lat_level, act_lat, odpl->activate_lat); } @@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) deact_lat = timespec_to_ns(&c); dev_dbg(&od->pdev->dev, - "omap_device: pm_lat %d: deactivate: elapsed time " - "%llu nsec\n", od->pm_lat_level, deact_lat); + "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n", + od->pm_lat_level, deact_lat); if (deact_lat > odpl->deactivate_lat) { odpl->deactivate_lat_worst = deact_lat; if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { odpl->deactivate_lat = deact_lat; dev_dbg(&od->pdev->dev, - "new worst case deactivate latency " - "%d: %llu\n", + "new worst case deactivate latency %d: %llu\n", od->pm_lat_level, deact_lat); } else dev_warn(&od->pdev->dev, - "deactivate latency %d " - "higher than exptected. (%llu > %d)\n", + "deactivate latency %d higher than expected. (%llu > %d)\n", od->pm_lat_level, deact_lat, odpl->deactivate_lat); } @@ -370,6 +365,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev) goto odbfd_exit1; } + /* Fix up missing resource names */ + for (i = 0; i < pdev->num_resources; i++) { + struct resource *r = &pdev->resource[i]; + + if (r->name == NULL) + r->name = dev_name(&pdev->dev); + } + if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) omap_device_disable_idle_on_suspend(pdev); @@ -385,17 +388,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb, unsigned long event, void *dev) { struct platform_device *pdev = to_platform_device(dev); + struct omap_device *od; switch (event) { - case BUS_NOTIFY_ADD_DEVICE: - if (pdev->dev.of_node) - omap_device_build_from_dt(pdev); - break; - case BUS_NOTIFY_DEL_DEVICE: if (pdev->archdata.od) omap_device_delete(pdev->archdata.od); break; + case BUS_NOTIFY_ADD_DEVICE: + if (pdev->dev.of_node) + omap_device_build_from_dt(pdev); + /* fall through */ + default: + od = to_omap_device(pdev); + if (od) + od->_driver_status = event; } return NOTIFY_DONE; @@ -449,8 +456,8 @@ static int omap_device_count_resources(struct omap_device *od) for (i = 0; i < od->hwmods_cnt; i++) c += omap_hwmod_count_resources(od->hwmods[i]); - pr_debug("omap_device: %s: counted %d total resources across %d " - "hwmods\n", od->pdev->name, c, od->hwmods_cnt); + pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n", + od->pdev->name, c, od->hwmods_cnt); return c; } @@ -486,6 +493,33 @@ static int omap_device_fill_resources(struct omap_device *od, } /** + * _od_fill_dma_resources - fill in array of struct resource with dma resources + * @od: struct omap_device * + * @res: pointer to an array of struct resource to be filled in + * + * Populate one or more empty struct resource pointed to by @res with + * the dma resource data for this omap_device @od. Used by + * omap_device_alloc() after calling omap_device_count_resources(). + * + * Ideally this function would not be needed at all. If we have + * mechanism to get dma resources from DT. + * + * Returns 0. + */ +static int _od_fill_dma_resources(struct omap_device *od, + struct resource *res) +{ + int i, r; + + for (i = 0; i < od->hwmods_cnt; i++) { + r = omap_hwmod_fill_dma_resources(od->hwmods[i], res); + res += r; + } + + return 0; +} + +/** * omap_device_alloc - allocate an omap_device * @pdev: platform_device that will be included in this omap_device * @oh: ptr to the single omap_hwmod that backs this omap_device @@ -524,24 +558,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, od->hwmods = hwmods; od->pdev = pdev; + res_count = omap_device_count_resources(od); /* - * HACK: Ideally the resources from DT should match, and hwmod - * should just add the missing ones. Since the name is not - * properly populated by DT, stick to hwmod resources only. + * DT Boot: + * OF framework will construct the resource structure (currently + * does for MEM & IRQ resource) and we should respect/use these + * resources, killing hwmod dependency. + * If pdev->num_resources > 0, we assume that MEM & IRQ resources + * have been allocated by OF layer already (through DTB). + * + * Non-DT Boot: + * Here, pdev->num_resources = 0, and we should get all the + * resources from hwmod. + * + * TODO: Once DMA resource is available from OF layer, we should + * kill filling any resources from hwmod. */ - if (pdev->num_resources && pdev->resource) - dev_warn(&pdev->dev, "%s(): resources already allocated %d\n", - __func__, pdev->num_resources); - - res_count = omap_device_count_resources(od); - if (res_count > 0) { - dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n", - __func__, res_count); + if (res_count > pdev->num_resources) { + /* Allocate resources memory to account for new resources */ res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); if (!res) goto oda_exit3; - omap_device_fill_resources(od, res); + /* + * If pdev->num_resources > 0, then assume that, + * MEM and IRQ resources will only come from DT and only + * fill DMA resource from hwmod layer. + */ + if (pdev->num_resources && pdev->resource) { + dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n", + __func__, res_count); + memcpy(res, pdev->resource, + sizeof(struct resource) * pdev->num_resources); + _od_fill_dma_resources(od, &res[pdev->num_resources]); + } else { + dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n", + __func__, res_count); + omap_device_fill_resources(od, res); + } ret = platform_device_add_resources(pdev, res, res_count); kfree(res); @@ -752,6 +806,10 @@ static int _od_suspend_noirq(struct device *dev) struct omap_device *od = to_omap_device(pdev); int ret; + /* Don't attempt late suspend on a driver that is not bound */ + if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) + return 0; + ret = pm_generic_suspend_noirq(dev); if (!ret && !pm_runtime_status_suspended(dev)) { @@ -1125,3 +1183,41 @@ static int __init omap_device_init(void) return 0; } core_initcall(omap_device_init); + +/** + * omap_device_late_idle - idle devices without drivers + * @dev: struct device * associated with omap_device + * @data: unused + * + * Check the driver bound status of this device, and idle it + * if there is no driver attached. + */ +static int __init omap_device_late_idle(struct device *dev, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct omap_device *od = to_omap_device(pdev); + + if (!od) + return 0; + + /* + * If omap_device state is enabled, but has no driver bound, + * idle it. + */ + if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) { + if (od->_state == OMAP_DEVICE_STATE_ENABLED) { + dev_warn(dev, "%s: enabled but no driver. Idling\n", + __func__); + omap_device_idle(pdev); + } + } + + return 0; +} + +static int __init omap_device_late_init(void) +{ + bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle); + return 0; +} +late_initcall(omap_device_late_init); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 766181cb5c95..28acb383e7df 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -26,7 +26,6 @@ #include <asm/mach/map.h> #include <plat/sram.h> -#include <plat/board.h> #include <plat/cpu.h> #include "sram.h" @@ -68,6 +67,7 @@ static unsigned long omap_sram_start; static void __iomem *omap_sram_base; +static unsigned long omap_sram_skip; static unsigned long omap_sram_size; static void __iomem *omap_sram_ceil; @@ -106,6 +106,7 @@ static int is_sram_locked(void) */ static void __init omap_detect_sram(void) { + omap_sram_skip = SRAM_BOOTLOADER_SZ; if (cpu_class_is_omap2()) { if (is_sram_locked()) { if (cpu_is_omap34xx()) { @@ -113,6 +114,7 @@ static void __init omap_detect_sram(void) if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ + omap_sram_skip += SZ_16K; } else { omap_sram_size = 0x8000; /* 32K */ } @@ -175,8 +177,10 @@ static void __init omap_map_sram(void) return; #ifdef CONFIG_OMAP4_ERRATA_I688 + if (cpu_is_omap44xx()) { omap_sram_start += PAGE_SIZE; omap_sram_size -= SZ_16K; + } #endif if (cpu_is_omap34xx()) { /* @@ -203,8 +207,8 @@ static void __init omap_map_sram(void) * Looks like we need to preserve some bootloader code at the * beginning of SRAM for jumping to flash for reboot to work... */ - memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0, - omap_sram_size - SRAM_BOOTLOADER_SZ); + memset_io(omap_sram_base + omap_sram_skip, 0, + omap_sram_size - omap_sram_skip); } /* @@ -218,7 +222,7 @@ void *omap_sram_push_address(unsigned long size) { unsigned long available, new_ceil = (unsigned long)omap_sram_ceil; - available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ); + available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); if (size > available) { pr_err("Not enough space in SRAM\n"); diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 65c5eca475e7..012bbd0b8d81 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -119,7 +119,7 @@ void clk_disable(struct clk *clk) unsigned long clk_get_rate(struct clk *clk) { - if (IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; if (clk->rate != 0) @@ -136,7 +136,7 @@ unsigned long clk_get_rate(struct clk *clk) long clk_round_rate(struct clk *clk, unsigned long rate) { - if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) + if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate) return (clk->ops->round_rate)(clk, rate); return rate; @@ -144,9 +144,10 @@ long clk_round_rate(struct clk *clk, unsigned long rate) int clk_set_rate(struct clk *clk, unsigned long rate) { + unsigned long flags; int ret; - if (IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; /* We do not default just do a clk->rate = rate as @@ -159,9 +160,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (clk->ops == NULL || clk->ops->set_rate == NULL) return -EINVAL; - spin_lock(&clocks_lock); + spin_lock_irqsave(&clocks_lock, flags); ret = (clk->ops->set_rate)(clk, rate); - spin_unlock(&clocks_lock); + spin_unlock_irqrestore(&clocks_lock, flags); return ret; } @@ -173,17 +174,18 @@ struct clk *clk_get_parent(struct clk *clk) int clk_set_parent(struct clk *clk, struct clk *parent) { + unsigned long flags; int ret = 0; - if (IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent)) return -EINVAL; - spin_lock(&clocks_lock); + spin_lock_irqsave(&clocks_lock, flags); if (clk->ops && clk->ops->set_parent) ret = (clk->ops->set_parent)(clk, parent); - spin_unlock(&clocks_lock); + spin_unlock_irqrestore(&clocks_lock, flags); return ret; } diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index fc49f3dabd76..8d26ce6813bb 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -35,7 +35,6 @@ #include <media/s5p_hdmi.h> #include <asm/irq.h> -#include <asm/pmu.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -52,6 +51,7 @@ #include <plat/ehci.h> #include <plat/fb.h> #include <plat/fb-s3c2410.h> +#include <plat/hdmi.h> #include <plat/hwmon.h> #include <plat/iic.h> #include <plat/keypad.h> @@ -763,7 +763,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) &s5p_device_i2c_hdmiphy); } -struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; +static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata; void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info, struct i2c_board_info *mhl_info, int mhl_bus) @@ -1132,7 +1132,7 @@ static struct resource s5p_pmu_resource[] = { static struct platform_device s5p_device_pmu = { .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, + .id = -1, .num_resources = ARRAY_SIZE(s5p_pmu_resource), .resource = s5p_pmu_resource, }; @@ -1591,6 +1591,8 @@ struct platform_device s3c64xx_device_spi1 = { void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, int num_cs) { + struct s3c64xx_spi_info pd; + /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { pr_err("%s: Invalid SPI configuration\n", __func__); diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h index bab139201761..d1ecef0e38e0 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-fns.h +++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h @@ -1,98 +1 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h - * - * Copyright (c) 2003-2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - hardware - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __MACH_GPIO_FNS_H -#define __MACH_GPIO_FNS_H __FILE__ - -/* These functions are in the to-be-removed category and it is strongly - * encouraged not to use these in new code. They will be marked deprecated - * very soon. - * - * Most of the functionality can be either replaced by the gpiocfg calls - * for the s3c platform or by the generic GPIOlib API. - * - * As of 2.6.35-rc, these will be removed, with the few drivers using them - * either replaced or given a wrapper until the calls can be removed. -*/ - #include <plat/gpio-cfg.h> - -static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) -{ - /* 1:1 mapping between cfgpin and setcfg calls at the moment */ - s3c_gpio_cfgpin(pin, cfg); -} - -/* external functions for GPIO support - * - * These allow various different clients to access the same GPIO - * registers without conflicting. If your driver only owns the entire - * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. -*/ - -extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); - -/* s3c2410_gpio_getirq - * - * turn the given pin number into the corresponding IRQ number - * - * returns: - * < 0 = no interrupt for this pin - * >=0 = interrupt number for the pin -*/ - -extern int s3c2410_gpio_getirq(unsigned int pin); - -/* s3c2410_gpio_irqfilter - * - * set the irq filtering on the given pin - * - * on = 0 => disable filtering - * 1 => enable filtering - * - * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with - * width of filter (0 through 63) - * - * -*/ - -extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config); - -/* s3c2410_gpio_pullup - * - * This call should be replaced with s3c_gpio_setpull(). - * - * As a note, there is currently no distinction between pull-up and pull-down - * in the s3c24xx series devices with only an on/off configuration. - */ - -/* s3c2410_gpio_pullup - * - * configure the pull-up control on the given pin - * - * to = 1 => disable the pull-up - * 0 => enable the pull-up - * - * eg; - * - * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); - * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); -*/ - -extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - -extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - -extern unsigned int s3c2410_gpio_getpin(unsigned int pin); - -#endif /* __MACH_GPIO_FNS_H */ diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c index f9431fe5b06e..23557d30e44c 100644 --- a/arch/arm/plat-samsung/s5p-irq-gpioint.c +++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c @@ -24,7 +24,7 @@ #include <asm/mach/irq.h> -#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u) +#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) #define CON_OFFSET 0x700 #define MASK_OFFSET 0x900 @@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip) bank->chips[group - bank->start] = chip; gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base, - (void __iomem *)GPIO_BASE(chip), + GPIO_BASE(chip), handle_level_irq); if (!gc) return -ENOMEM; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 2997e56ce0dd..831e1fdfdb2f 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -66,7 +66,6 @@ iq80321 ARCH_IQ80321 IQ80321 169 ks8695 ARCH_KS8695 KS8695 180 karo ARCH_KARO KARO 190 smdk2410 ARCH_SMDK2410 SMDK2410 193 -ceiva ARCH_CEIVA CEIVA 200 voiceblue MACH_VOICEBLUE VOICEBLUE 218 h5400 ARCH_H5400 H5400 220 omap_innovator MACH_OMAP_INNOVATOR OMAP_INNOVATOR 234 @@ -158,7 +157,6 @@ edb9315a MACH_EDB9315A EDB9315A 772 stargate2 MACH_STARGATE2 STARGATE2 774 intelmote2 MACH_INTELMOTE2 INTELMOTE2 775 trizeps4 MACH_TRIZEPS4 TRIZEPS4 776 -pnx4008 MACH_PNX4008 PNX4008 782 cpuat91 MACH_CPUAT91 CPUAT91 787 iq81340sc MACH_IQ81340SC IQ81340SC 799 iq81340mc MACH_IQ81340MC IQ81340MC 801 |