diff options
Diffstat (limited to 'arch/arm')
153 files changed, 3900 insertions, 1260 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7bc4a583f4e1..11fff042aa81 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -64,6 +64,9 @@ config GENERIC_CALIBRATE_DELAY config GENERIC_BUST_SPINLOCK bool +config ARCH_MAY_HAVE_PC_FDC + bool + config GENERIC_ISA_DMA bool @@ -150,6 +153,7 @@ config ARCH_RPC select ARCH_ACORN select FIQ select TIMER_ACORN + select ARCH_MAY_HAVE_PC_FDC help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. @@ -310,7 +314,7 @@ menu "Kernel Features" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL #&& n + depends on EXPERIMENTAL && BROKEN #&& n help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -322,8 +326,8 @@ config SMP processor machines. On a single processor machine, the kernel will run faster if you say N here. - See also the <file:Documentation/smp.tex>, - <file:Documentation/smp.txt>, <file:Documentation/i386/IO-APIC.txt>, + See also the <file:Documentation/smp.txt>, + <file:Documentation/i386/IO-APIC.txt>, <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at <http://www.linuxdoc.org/docs.html#howto>. @@ -365,8 +369,8 @@ config NO_IDLE_HZ Please note that dynamic tick may affect the accuracy of timekeeping on some platforms depending on the implementation. - Currently at least OMAP platform is known to have accurate - timekeeping with dynamic tick. + Currently at least OMAP, PXA2xx and SA11x0 platforms are known + to have accurate timekeeping with dynamic tick. config ARCH_DISCONTIGMEM_ENABLE bool @@ -635,10 +639,6 @@ config PM and the Battery Powered Linux mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>. - Note that, even if you say N here, Linux on the x86 architecture - will issue the hlt instruction if nothing is to be done, thereby - sending the processor to sleep and saving power. - config APM tristate "Advanced Power Management Emulation" depends on PM @@ -650,12 +650,6 @@ config APM battery status information, and user-space programs will receive notification of APM "events" (e.g. battery status change). - If you select "Y" here, you can disable actual use of the APM - BIOS by passing the "apm=off" option to the kernel at boot time. - - Note that the APM support is almost completely disabled for - machines with more than one CPU. - In order to use APM, you will need supporting software. For location and more information, read <file:Documentation/pm.txt> and the Battery Powered Linux mini-HOWTO, available from @@ -665,39 +659,12 @@ config APM manpage ("man 8 hdparm") for that), and it doesn't turn off VESA-compliant "green" monitors. - This driver does not support the TI 4000M TravelMate and the ACER - 486/DX4/75 because they don't have compliant BIOSes. Many "green" - desktop machines also don't have compliant BIOSes, and this driver - may cause those machines to panic during the boot phase. - Generally, if you don't have a battery in your machine, there isn't much point in using this driver and you should say N. If you get random kernel OOPSes or reboots that don't seem to be related to anything, try disabling/enabling this option (or disabling/enabling APM in your BIOS). - Some other things you should try when experiencing seemingly random, - "weird" problems: - - 1) make sure that you have enough swap space and that it is - enabled. - 2) pass the "no-hlt" option to the kernel - 3) switch on floating point emulation in the kernel and pass - the "no387" option to the kernel - 4) pass the "floppy=nodma" option to the kernel - 5) pass the "mem=4M" option to the kernel (thereby disabling - all but the first 4 MB of RAM) - 6) make sure that the CPU is not over clocked. - 7) read the sig11 FAQ at <http://www.bitwizard.nl/sig11/> - 8) disable the cache from your BIOS settings - 9) install a fan for the video card or exchange video RAM - 10) install a better fan for the CPU - 11) exchange RAM chips - 12) exchange the motherboard. - - To compile this driver as a module, choose M here: the - module will be called apm. - endmenu source "net/Kconfig" @@ -752,6 +719,8 @@ source "drivers/hwmon/Kconfig" source "drivers/misc/Kconfig" +source "drivers/mfd/Kconfig" + source "drivers/media/Kconfig" source "drivers/video/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 45a5709eaaa4..5d3acff8c596 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -53,7 +53,7 @@ config DEBUG_LL bool "Kernel low-level debugging functions" depends on DEBUG_KERNEL help - Say Y here to include definitions of printascii, printchar, printhex + Say Y here to include definitions of printascii, printch, printhex in the kernel. This is helpful if you are debugging code that executes before the console is initialized. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 67f1453ade05..130e6228b587 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -175,10 +175,10 @@ else endif @touch $@ -prepare: maketools include/asm-arm/.arch +archprepare: maketools include/asm-arm/.arch .PHONY: maketools FORCE -maketools: include/asm-arm/constants.h include/linux/version.h FORCE +maketools: include/linux/version.h FORCE $(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h # Convert bzImage to zImage @@ -190,7 +190,7 @@ zImage Image xipImage bootpImage uImage: vmlinux zinstall install: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ -CLEAN_FILES += include/asm-arm/constants.h* include/asm-arm/mach-types.h \ +CLEAN_FILES += include/asm-arm/mach-types.h \ include/asm-arm/arch include/asm-arm/.arch # We use MRPROPER_FILES and CLEAN_FILES now @@ -201,11 +201,6 @@ archclean: bp:; $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/bootpImage i zi:; $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ -arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \ - include/asm-arm/.arch - -include/asm-$(ARCH)/constants.h: arch/$(ARCH)/kernel/asm-offsets.s - $(call filechk,gen-asm-offsets) define archhelp echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' diff --git a/arch/arm/boot/compressed/head-sharpsl.S b/arch/arm/boot/compressed/head-sharpsl.S index d6bf8a2b090d..59ad69640d6b 100644 --- a/arch/arm/boot/compressed/head-sharpsl.S +++ b/arch/arm/boot/compressed/head-sharpsl.S @@ -7,7 +7,8 @@ * so we have to figure out the machine for ourselves... * * Support for Poodle, Corgi (SL-C700), Shepherd (SL-C750) - * and Husky (SL-C760). + * Husky (SL-C760), Tosa (SL-C6000), Spitz (SL-C3000), + * Akita (SL-C1000) and Borzoi (SL-C3100). * */ @@ -23,6 +24,22 @@ __SharpSL_start: +/* Check for TC6393 - if found we have a Tosa */ + ldr r7, .TOSAID + mov r1, #0x10000000 @ Base address of TC6393 chip + mov r6, #0x03 + ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003 + cmp r6, r3 + beq .SHARPEND @ Success -> tosa + +/* Check for pxa270 - if found, branch */ + mrc p15, 0, r4, c0, c0 @ Get Processor ID + and r4, r4, #0xffffff00 + ldr r3, .PXA270ID + cmp r4, r3 + beq .PXA270 + +/* Check for w100 - if not found we have a Poodle */ ldr r1, .W100ADDR @ Base address of w100 chip + regs offset mov r6, #0x31 @ Load Magic Init value @@ -30,7 +47,7 @@ __SharpSL_start: mov r5, #0x3000 .W100LOOP: subs r5, r5, #1 - bne .W100LOOP + bne .W100LOOP mov r6, #0x30 @ Load 2nd Magic Init value str r6, [r1, #0x280] @ to SCRATCH_UMSK @@ -40,45 +57,52 @@ __SharpSL_start: cmp r6, r3 bne .SHARPEND @ We have no w100 - Poodle - mrc p15, 0, r6, c0, c0 @ Get Processor ID - and r6, r6, #0xffffff00 +/* Check for pxa250 - if found we have a Corgi */ ldr r7, .CORGIID ldr r3, .PXA255ID - cmp r6, r3 + cmp r4, r3 blo .SHARPEND @ We have a PXA250 - Corgi - mov r1, #0x0c000000 @ Base address of NAND chip - ldrb r3, [r1, #24] @ Load FLASHCTL - bic r3, r3, #0x11 @ SET NCE - orr r3, r3, #0x0a @ SET CLR + FLWP - strb r3, [r1, #24] @ Save to FLASHCTL - mov r2, #0x90 @ Command "readid" - strb r2, [r1, #20] @ Save to FLASHIO - bic r3, r3, #2 @ CLR CLE - orr r3, r3, #4 @ SET ALE - strb r3, [r1, #24] @ Save to FLASHCTL - mov r2, #0 @ Address 0x00 - strb r2, [r1, #20] @ Save to FLASHIO - bic r3, r3, #4 @ CLR ALE - strb r3, [r1, #24] @ Save to FLASHCTL -.SHARP1: - ldrb r3, [r1, #24] @ Load FLASHCTL - tst r3, #32 @ Is chip ready? - beq .SHARP1 - ldrb r2, [r1, #20] @ NAND Manufacturer ID - ldrb r3, [r1, #20] @ NAND Chip ID +/* Check for 64MiB flash - if found we have a Shepherd */ + bl get_flash_ids ldr r7, .SHEPHERDID cmp r3, #0x76 @ 64MiB flash beq .SHARPEND @ We have Shepherd + +/* Must be a Husky */ ldr r7, .HUSKYID @ Must be Husky b .SHARPEND +.PXA270: +/* Check for 16MiB flash - if found we have Spitz */ + bl get_flash_ids + ldr r7, .SPITZID + cmp r3, #0x73 @ 16MiB flash + beq .SHARPEND @ We have Spitz + +/* Check for a second SCOOP chip - if found we have Borzoi */ + ldr r1, .SCOOP2ADDR + ldr r7, .BORZOIID + mov r6, #0x0140 + strh r6, [r1] + ldrh r6, [r1] + cmp r6, #0x0140 + beq .SHARPEND @ We have Borzoi + +/* Must be Akita */ + ldr r7, .AKITAID + b .SHARPEND @ We have Borzoi + .PXA255ID: .word 0x69052d00 @ PXA255 Processor ID +.PXA270ID: + .word 0x69054100 @ PXA270 Processor ID .W100ID: .word 0x57411002 @ w100 Chip ID .W100ADDR: .word 0x08010000 @ w100 Chip ID Reg Address +.SCOOP2ADDR: + .word 0x08800040 .POODLEID: .word MACH_TYPE_POODLE .CORGIID: @@ -87,6 +111,41 @@ __SharpSL_start: .word MACH_TYPE_SHEPHERD .HUSKYID: .word MACH_TYPE_HUSKY -.SHARPEND: +.TOSAID: + .word MACH_TYPE_TOSA +.SPITZID: + .word MACH_TYPE_SPITZ +.AKITAID: + .word MACH_TYPE_AKITA +.BORZOIID: + .word MACH_TYPE_BORZOI +/* + * Return: r2 - NAND Manufacturer ID + * r3 - NAND Chip ID + * Corrupts: r1 + */ +get_flash_ids: + mov r1, #0x0c000000 @ Base address of NAND chip + ldrb r3, [r1, #24] @ Load FLASHCTL + bic r3, r3, #0x11 @ SET NCE + orr r3, r3, #0x0a @ SET CLR + FLWP + strb r3, [r1, #24] @ Save to FLASHCTL + mov r2, #0x90 @ Command "readid" + strb r2, [r1, #20] @ Save to FLASHIO + bic r3, r3, #2 @ CLR CLE + orr r3, r3, #4 @ SET ALE + strb r3, [r1, #24] @ Save to FLASHCTL + mov r2, #0 @ Address 0x00 + strb r2, [r1, #20] @ Save to FLASHIO + bic r3, r3, #4 @ CLR ALE + strb r3, [r1, #24] @ Save to FLASHCTL +.fids1: + ldrb r3, [r1, #24] @ Load FLASHCTL + tst r3, #32 @ Is chip ready? + beq .fids1 + ldrb r2, [r1, #20] @ NAND Manufacturer ID + ldrb r3, [r1, #20] @ NAND Chip ID + mov pc, lr +.SHARPEND: diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 692af6b5e8ff..666ba393575b 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,6 +1,9 @@ config ICST525 bool +config ARM_GIC + bool + config ICST307 bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 11f20a43ee3a..a87886564b19 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -4,6 +4,7 @@ obj-y += rtctime.o obj-$(CONFIG_ARM_AMBA) += amba.o +obj-$(CONFIG_ARM_GIC) += gic.o obj-$(CONFIG_ICST525) += icst525.o obj-$(CONFIG_ICST307) += icst307.o obj-$(CONFIG_SA1111) += sa1111.o diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c new file mode 100644 index 000000000000..d74990717559 --- /dev/null +++ b/arch/arm/common/gic.c @@ -0,0 +1,167 @@ +/* + * linux/arch/arm/common/gic.c + * + * Copyright (C) 2002 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Interrupt architecture for the GIC: + * + * o There is one Interrupt Distributor, which receives interrupts + * from system devices and sends them to the Interrupt Controllers. + * + * o There is one CPU Interface per CPU, which sends interrupts sent + * by the Distributor, and interrupts generated locally, to the + * associated CPU. + * + * Note that IRQs 0-31 are special - they are local to each CPU. + * As such, the enable set/clear, pending set/clear and active bit + * registers are banked per-cpu for these sources. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/smp.h> +#include <linux/cpumask.h> + +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/mach/irq.h> +#include <asm/hardware/gic.h> + +static void __iomem *gic_dist_base; +static void __iomem *gic_cpu_base; + +/* + * Routines to acknowledge, disable and enable interrupts + * + * Linux assumes that when we're done with an interrupt we need to + * unmask it, in the same way we need to unmask an interrupt when + * we first enable it. + * + * The GIC has a seperate notion of "end of interrupt" to re-enable + * an interrupt after handling, in order to support hardware + * prioritisation. + * + * We can make the GIC behave in the way that Linux expects by making + * our "acknowledge" routine disable the interrupt, then mark it as + * complete. + */ +static void gic_ack_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); + writel(irq, gic_cpu_base + GIC_CPU_EOI); +} + +static void gic_mask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); +} + +static void gic_unmask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4); +} + +static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu) +{ + void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3); + unsigned int shift = (irq % 4) * 8; + u32 val; + + val = readl(reg) & ~(0xff << shift); + val |= 1 << (cpu + shift); + writel(val, reg); +} + +static struct irqchip gic_chip = { + .ack = gic_ack_irq, + .mask = gic_mask_irq, + .unmask = gic_unmask_irq, +#ifdef CONFIG_SMP + .set_cpu = gic_set_cpu, +#endif +}; + +void __init gic_dist_init(void __iomem *base) +{ + unsigned int max_irq, i; + u32 cpumask = 1 << smp_processor_id(); + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + + gic_dist_base = base; + + writel(0, base + GIC_DIST_CTRL); + + /* + * Find out how many interrupts are supported. + */ + max_irq = readl(base + GIC_DIST_CTR) & 0x1f; + max_irq = (max_irq + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (max_irq > max(1020, NR_IRQS)) + max_irq = max(1020, NR_IRQS); + + /* + * Set all global interrupts to be level triggered, active low. + */ + for (i = 32; i < max_irq; i += 16) + writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); + + /* + * Set all global interrupts to this CPU only. + */ + for (i = 32; i < max_irq; i += 4) + writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); + + /* + * Set priority on all interrupts. + */ + for (i = 0; i < max_irq; i += 4) + writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); + + /* + * Disable all interrupts. + */ + for (i = 0; i < max_irq; i += 32) + writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); + + /* + * Setup the Linux IRQ subsystem. + */ + for (i = 29; i < max_irq; i++) { + set_irq_chip(i, &gic_chip); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + + writel(1, base + GIC_DIST_CTRL); +} + +void __cpuinit gic_cpu_init(void __iomem *base) +{ + gic_cpu_base = base; + writel(0xf0, base + GIC_CPU_PRIMASK); + writel(1, base + GIC_CPU_CTRL); +} + +#ifdef CONFIG_SMP +void gic_raise_softirq(cpumask_t cpumask, unsigned int irq) +{ + unsigned long map = *cpus_addr(cpumask); + + writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT); +} +#endif diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 41f12658c8b4..2786f7c34b3f 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -177,7 +177,7 @@ static void locomo_handler(unsigned int irq, struct irqdesc *desc, d = irq_desc + irq; for (i = 0; i <= 3; i++, d++, irq++) { if (req & (0x0100 << i)) { - d->handle(irq, d, regs); + desc_handle_irq(irq, d, regs); } } @@ -220,7 +220,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc, if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { d = irq_desc + LOCOMO_IRQ_KEY_START; - d->handle(LOCOMO_IRQ_KEY_START, d, regs); + desc_handle_irq(LOCOMO_IRQ_KEY_START, d, regs); } } @@ -273,7 +273,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc, d = irq_desc + LOCOMO_IRQ_GPIO_START; for (i = 0; i <= 15; i++, irq++, d++) { if (req & (0x0001 << i)) { - d->handle(irq, d, regs); + desc_handle_irq(irq, d, regs); } } } @@ -328,7 +328,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc, if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { d = irq_desc + LOCOMO_IRQ_LT_START; - d->handle(LOCOMO_IRQ_LT_START, d, regs); + desc_handle_irq(LOCOMO_IRQ_LT_START, d, regs); } } @@ -379,7 +379,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc, for (i = 0; i <= 3; i++, irq++, d++) { if (req & (0x0001 << i)) { - d->handle(irq, d, regs); + desc_handle_irq(irq, d, regs); } } } @@ -541,6 +541,103 @@ locomo_init_one_child(struct locomo *lchip, struct locomo_dev_info *info) return ret; } +#ifdef CONFIG_PM + +struct locomo_save_data { + u16 LCM_GPO; + u16 LCM_SPICT; + u16 LCM_GPE; + u16 LCM_ASD; + u16 LCM_SPIMD; +}; + +static int locomo_suspend(struct device *dev, u32 pm_message_t, u32 level) +{ + struct locomo *lchip = dev_get_drvdata(dev); + struct locomo_save_data *save; + unsigned long flags; + + if (level != SUSPEND_DISABLE) + return 0; + + save = kmalloc(sizeof(struct locomo_save_data), GFP_KERNEL); + if (!save) + return -ENOMEM; + + dev->power.saved_state = (void *) save; + + spin_lock_irqsave(&lchip->lock, flags); + + save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ + locomo_writel(0x00, lchip->base + LOCOMO_GPO); + save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPICT); /* SPI */ + locomo_writel(0x40, lchip->base + LOCOMO_SPICT); + save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */ + locomo_writel(0x00, lchip->base + LOCOMO_GPE); + save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */ + locomo_writel(0x00, lchip->base + LOCOMO_ASD); + save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPIMD); /* SPI */ + locomo_writel(0x3C14, lchip->base + LOCOMO_SPIMD); + + locomo_writel(0x00, lchip->base + LOCOMO_PAIF); + locomo_writel(0x00, lchip->base + LOCOMO_DAC); + locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC); + + if ( (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88) ) + locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */ + else + /* 18MHz already enabled, so no wait */ + locomo_writel(0xc1, lchip->base + LOCOMO_C32K); /* CLK32 on */ + + locomo_writel(0x00, lchip->base + LOCOMO_TADC); /* 18MHz clock off*/ + locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC); /* 22MHz/24MHz clock off */ + locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); /* FL */ + + spin_unlock_irqrestore(&lchip->lock, flags); + + return 0; +} + +static int locomo_resume(struct device *dev, u32 level) +{ + struct locomo *lchip = dev_get_drvdata(dev); + struct locomo_save_data *save; + unsigned long r; + unsigned long flags; + + if (level != RESUME_ENABLE) + return 0; + + save = (struct locomo_save_data *) dev->power.saved_state; + if (!save) + return 0; + + spin_lock_irqsave(&lchip->lock, flags); + + locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO); + locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPICT); + locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE); + locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD); + locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPIMD); + + locomo_writel(0x00, lchip->base + LOCOMO_C32K); + locomo_writel(0x90, lchip->base + LOCOMO_TADC); + + locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC); + r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); + r &= 0xFEFF; + locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); + locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD); + + spin_unlock_irqrestore(&lchip->lock, flags); + + dev->power.saved_state = NULL; + kfree(save); + + return 0; +} +#endif + /** * locomo_probe - probe for a single LoCoMo chip. * @phys_addr: physical address of device. @@ -651,15 +748,15 @@ __locomo_probe(struct device *me, struct resource *mem, int irq) return ret; } -static void __locomo_remove(struct locomo *lchip) +static int locomo_remove_child(struct device *dev, void *data) { - struct list_head *l, *n; - - list_for_each_safe(l, n, &lchip->dev->children) { - struct device *d = list_to_dev(l); + device_unregister(dev); + return 0; +} - device_unregister(d); - } +static void __locomo_remove(struct locomo *lchip) +{ + device_for_each_child(lchip->dev, NULL, locomo_remove_child); if (lchip->irq != NO_IRQ) { set_irq_chained_handler(lchip->irq, NULL); @@ -707,6 +804,10 @@ static struct device_driver locomo_device_driver = { .bus = &platform_bus_type, .probe = locomo_probe, .remove = locomo_remove, +#ifdef CONFIG_PM + .suspend = locomo_suspend, + .resume = locomo_resume, +#endif }; /* diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 38c2eb667eb9..1a47fbf9cbbc 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -268,8 +268,8 @@ static struct irqchip sa1111_low_chip = { .mask = sa1111_mask_lowirq, .unmask = sa1111_unmask_lowirq, .retrigger = sa1111_retrigger_lowirq, - .type = sa1111_type_lowirq, - .wake = sa1111_wake_lowirq, + .set_type = sa1111_type_lowirq, + .set_wake = sa1111_wake_lowirq, }; static void sa1111_mask_highirq(unsigned int irq) @@ -364,8 +364,8 @@ static struct irqchip sa1111_high_chip = { .mask = sa1111_mask_highirq, .unmask = sa1111_unmask_highirq, .retrigger = sa1111_retrigger_highirq, - .type = sa1111_type_highirq, - .wake = sa1111_wake_highirq, + .set_type = sa1111_type_highirq, + .set_wake = sa1111_wake_highirq, }; static void sa1111_setup_irq(struct sa1111 *sachip) diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index cfd0d3e550d9..d3a04c2a2c85 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -17,6 +17,12 @@ #define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr))) +/* PCMCIA to Scoop linkage structures for pxa2xx_sharpsl.c + There is no easy way to link multiple scoop devices into one + single entity for the pxa2xx_pcmcia device */ +int scoop_num; +struct scoop_pcmcia_dev *scoop_devs; + struct scoop_dev { void *base; spinlock_t scoop_lock; @@ -85,7 +91,7 @@ EXPORT_SYMBOL(read_scoop_reg); EXPORT_SYMBOL(write_scoop_reg); #ifdef CONFIG_PM -static int scoop_suspend(struct device *dev, uint32_t state, uint32_t level) +static int scoop_suspend(struct device *dev, pm_message_t state, uint32_t level) { if (level == SUSPEND_POWER_DOWN) { struct scoop_dev *sdev = dev_get_drvdata(dev); diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig index 24955263b096..4198677cd394 100644 --- a/arch/arm/configs/omap_h2_1610_defconfig +++ b/arch/arm/configs/omap_h2_1610_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc2 -# Fri Jul 8 04:49:34 2005 +# Linux kernel version: 2.6.13 +# Mon Sep 5 18:07:12 2005 # CONFIG_ARM=y CONFIG_MMU=y @@ -102,9 +102,11 @@ CONFIG_OMAP_MUX_WARNINGS=y # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 +# CONFIG_OMAP_DM_TIMER is not set CONFIG_OMAP_LL_DEBUG_UART1=y # CONFIG_OMAP_LL_DEBUG_UART2 is not set # CONFIG_OMAP_LL_DEBUG_UART3 is not set +CONFIG_OMAP_SERIAL_WAKE=y # # OMAP Core Type @@ -166,7 +168,6 @@ CONFIG_ISA_DMA_API=y # # Kernel Features # -# CONFIG_SMP is not set CONFIG_PREEMPT=y CONFIG_NO_IDLE_HZ=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set @@ -230,91 +231,82 @@ CONFIG_PM=y # CONFIG_APM is not set # -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) +# Networking # -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=3 -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set +CONFIG_NET=y # -# User Modules And Translation Layers +# Networking options # -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set # -# RAM/ROM/Flash chip drivers +# SCTP Configuration (EXPERIMENTAL) # -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set # -# Mapping drivers for chip access +# Network testing # -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_EDB7312 is not set +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set # -# Self-contained MTD device drivers +# Device Drivers # -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set # -# Disk-On-Chip Device Drivers +# Generic Driver Options # -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set # -# NAND Flash Device Drivers +# Memory Technology Devices (MTD) # -# CONFIG_MTD_NAND is not set +# CONFIG_MTD is not set # # Parallel port support @@ -403,72 +395,8 @@ CONFIG_SCSI_PROC_FS=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) +# Network device support # -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -518,6 +446,8 @@ CONFIG_SLIP_COMPRESSED=y # CONFIG_SLIP_MODE_SLIP6 is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -615,77 +545,15 @@ CONFIG_WATCHDOG_NOWAYOUT=y # # I2C support # -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y - -# -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# -# I2C Hardware Bus support -# -# CONFIG_I2C_ISA is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C is not set +# CONFIG_I2C_SENSOR is not set +CONFIG_ISP1301_OMAP=y # -# Hardware Sensors Chip support +# Hardware Monitoring support # -# CONFIG_I2C_SENSOR is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set - -# -# Other I2C Chip support -# -# CONFIG_SENSORS_DS1337 is not set -# CONFIG_SENSORS_DS1374 is not set -# CONFIG_SENSORS_EEPROM is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set -CONFIG_ISP1301_OMAP=y -CONFIG_TPS65010=y -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set # # Misc devices @@ -756,15 +624,9 @@ CONFIG_SOUND=y # Open Sound System # CONFIG_SOUND_PRIME=y -# CONFIG_SOUND_BT878 is not set -# CONFIG_SOUND_FUSION is not set -# CONFIG_SOUND_CS4281 is not set -# CONFIG_SOUND_SONICVIBES is not set -# CONFIG_SOUND_TRIDENT is not set # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set # CONFIG_SOUND_OSS is not set -# CONFIG_SOUND_TVMIXER is not set # CONFIG_SOUND_AD1980 is not set # @@ -810,6 +672,7 @@ CONFIG_EXT2_FS=y # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # # XFS support @@ -817,6 +680,7 @@ CONFIG_EXT2_FS=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -857,15 +721,6 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=2 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -1007,4 +862,3 @@ CONFIG_CRYPTO_DES=y CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 96a794d8de84..756348bf5170 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-git4 -# Wed Jun 22 15:56:42 2005 +# Linux kernel version: 2.6.13-git8 +# Thu Sep 8 19:24:02 2005 # CONFIG_ARM=y CONFIG_MMU=y @@ -22,6 +22,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set @@ -31,6 +32,7 @@ CONFIG_SYSCTL=y # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" # CONFIG_EMBEDDED is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set @@ -88,7 +90,9 @@ CONFIG_ARCH_S3C2410=y # # S3C24XX Implementations # +CONFIG_MACH_ANUBIS=y CONFIG_ARCH_BAST=y +CONFIG_BAST_PC104_IRQ=y CONFIG_ARCH_H1940=y CONFIG_MACH_N30=y CONFIG_ARCH_SMDK2410=y @@ -112,6 +116,7 @@ CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set # CONFIG_S3C2410_PM_DEBUG is not set # CONFIG_S3C2410_PM_CHECK is not set +CONFIG_PM_SIMTEC=y CONFIG_S3C2410_LOWLEVEL_UART_PORT=0 # @@ -149,7 +154,15 @@ CONFIG_ISA_DMA_API=y # # CONFIG_SMP is not set # CONFIG_PREEMPT is not set -# CONFIG_DISCONTIGMEM is not set +# CONFIG_NO_IDLE_HZ is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_ALIGNMENT_TRAP=y # @@ -186,6 +199,74 @@ CONFIG_PM=y CONFIG_APM=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# # Device Drivers # @@ -258,6 +339,7 @@ CONFIG_MTD_ROM=y # CONFIG_MTD_IMPA7 is not set CONFIG_MTD_BAST=y CONFIG_MTD_BAST_MAXSIZE=4 +# CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers @@ -312,7 +394,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" # CONFIG_CDROM_PKTCDVD is not set # @@ -354,6 +435,7 @@ CONFIG_BLK_DEV_IDE_BAST=y # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -376,70 +458,8 @@ CONFIG_BLK_DEV_IDE_BAST=y # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -# CONFIG_PACKET is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set @@ -447,6 +467,11 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # +# PHY device support +# +# CONFIG_PHYLIB is not set + +# # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y @@ -480,6 +505,8 @@ CONFIG_DM9000=m # CONFIG_SLIP is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -562,7 +589,6 @@ CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_MULTIPORT is not set # CONFIG_SERIAL_8250_RSA is not set # @@ -605,7 +631,6 @@ CONFIG_S3C2410_RTC=y # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # @@ -628,7 +653,7 @@ CONFIG_I2C_ALGOBIT=m # # I2C Hardware Bus support # -# CONFIG_I2C_ISA is not set +CONFIG_I2C_ISA=m # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set CONFIG_I2C_S3C2410=y @@ -636,14 +661,33 @@ CONFIG_I2C_S3C2410=y # CONFIG_I2C_PCA_ISA is not set # -# Hardware Sensors Chip support +# Miscellaneous I2C Chip support # -CONFIG_I2C_SENSOR=m +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +CONFIG_SENSORS_EEPROM=m +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_RTC8564 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +CONFIG_HWMON_VID=m # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_FSCHER is not set # CONFIG_SENSORS_FSCPOS is not set @@ -662,27 +706,21 @@ CONFIG_SENSORS_LM85=m # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set # -# Other I2C Chip support +# Misc devices # -# CONFIG_SENSORS_DS1337 is not set -CONFIG_SENSORS_EEPROM=m -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set # -# Misc devices +# Multimedia Capabilities Port drivers # # @@ -731,7 +769,7 @@ CONFIG_DUMMY_CONSOLE=y # USB support # CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB is not set # @@ -749,6 +787,7 @@ CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set @@ -758,6 +797,7 @@ CONFIG_JBD=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # # XFS support @@ -765,6 +805,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -791,11 +832,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_SYSFS=y -# CONFIG_DEVPTS_FS_XATTR is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set # # Miscellaneous filesystems @@ -812,8 +853,7 @@ CONFIG_JFFS_FS_VERBOSE=0 # CONFIG_JFFS_PROC_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y @@ -835,6 +875,7 @@ CONFIG_NFS_FS=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -920,6 +961,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_DEBUG_KERNEL=y # CONFIG_MAGIC_SYSRQ is not set CONFIG_LOG_BUF_SHIFT=16 +CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index e5d370c235d7..949ec4427f21 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -10,7 +10,7 @@ * This file is included twice in entry-common.S */ #ifndef NR_syscalls -#define NR_syscalls 320 +#define NR_syscalls 328 #else __syscall_start: @@ -284,7 +284,7 @@ __syscall_start: .long sys_fstatfs64 .long sys_tgkill .long sys_utimes -/* 270 */ .long sys_fadvise64_64 +/* 270 */ .long sys_arm_fadvise64_64_wrapper .long sys_pciconfig_iobase .long sys_pciconfig_read .long sys_pciconfig_write @@ -327,6 +327,15 @@ __syscall_start: /* 310 */ .long sys_request_key .long sys_keyctl .long sys_semtimedop +/* vserver */ .long sys_ni_syscall + .long sys_ioprio_set +/* 315 */ .long sys_ioprio_get + .long sys_inotify_init + .long sys_inotify_add_watch + .long sys_inotify_rm_watch + .long sys_mbind_wrapper +/* 320 */ .long sys_get_mempolicy + .long sys_set_mempolicy __syscall_end: .rept NR_syscalls - (__syscall_end - __syscall_start) / 4 diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 6540db691338..dceb826bd216 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) if (pending) { struct irqdesc *d = irq_desc + ec->irq; - d->handle(ec->irq, d, regs); + desc_handle_irq(ec->irq, d, regs); called ++; } } @@ -632,7 +632,7 @@ ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg * Serial cards should go in 0/1, ethernet/scsi in 2/3 * otherwise you will lose serial data at high speeds! */ - d->handle(ec->irq, d, regs); + desc_handle_irq(ec->irq, d, regs); } else { printk(KERN_WARNING "card%d: interrupt from unclaimed " "card???\n", slot); diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 3f8d0e3aefab..db302c6e5343 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -265,6 +265,14 @@ sys_futex_wrapper: str r5, [sp, #4] @ push sixth arg b sys_futex +sys_arm_fadvise64_64_wrapper: + str r5, [sp, #4] @ push r5 to stack + b sys_arm_fadvise64_64 + +sys_mbind_wrapper: + str r5, [sp, #4] + b sys_mbind + /* * Note: off_4k (r5) is always units of 4K. If we can't do the requested * offset, we return EINVAL. diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index afef21273963..648cfff93138 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -3,7 +3,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/errno.h> #include <asm/thread_info.h> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 1155cf07c871..539626351348 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -20,7 +20,7 @@ #include <asm/mach-types.h> #include <asm/procinfo.h> #include <asm/ptrace.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/thread_info.h> #include <asm/system.h> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 395137a8fad2..3284118f356b 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -207,8 +207,8 @@ void enable_irq_wake(unsigned int irq) unsigned long flags; spin_lock_irqsave(&irq_controller_lock, flags); - if (desc->chip->wake) - desc->chip->wake(irq, 1); + if (desc->chip->set_wake) + desc->chip->set_wake(irq, 1); spin_unlock_irqrestore(&irq_controller_lock, flags); } EXPORT_SYMBOL(enable_irq_wake); @@ -219,8 +219,8 @@ void disable_irq_wake(unsigned int irq) unsigned long flags; spin_lock_irqsave(&irq_controller_lock, flags); - if (desc->chip->wake) - desc->chip->wake(irq, 0); + if (desc->chip->set_wake) + desc->chip->set_wake(irq, 0); spin_unlock_irqrestore(&irq_controller_lock, flags); } EXPORT_SYMBOL(disable_irq_wake); @@ -517,7 +517,7 @@ static void do_pending_irqs(struct pt_regs *regs) list_for_each_safe(l, n, &head) { desc = list_entry(l, struct irqdesc, pend); list_del_init(&desc->pend); - desc->handle(desc - irq_desc, desc, regs); + desc_handle_irq(desc - irq_desc, desc, regs); } /* @@ -545,7 +545,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) irq_enter(); spin_lock(&irq_controller_lock); - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); /* * Now re-run any pending interrupts. @@ -624,9 +624,9 @@ int set_irq_type(unsigned int irq, unsigned int type) } desc = irq_desc + irq; - if (desc->chip->type) { + if (desc->chip->set_type) { spin_lock_irqsave(&irq_controller_lock, flags); - ret = desc->chip->type(irq, type); + ret = desc->chip->set_type(irq, type); spin_unlock_irqrestore(&irq_controller_lock, flags); } @@ -846,8 +846,8 @@ unsigned long probe_irq_on(void) irq_desc[i].probing = 1; irq_desc[i].triggered = 0; - if (irq_desc[i].chip->type) - irq_desc[i].chip->type(i, IRQT_PROBE); + if (irq_desc[i].chip->set_type) + irq_desc[i].chip->set_type(i, IRQT_PROBE); irq_desc[i].chip->unmask(i); irqs += 1; } diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index 8f74e24536ba..24c7b0477a09 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -17,7 +17,7 @@ #include <linux/linkage.h> #include <asm/ptrace.h> #include <asm/thread_info.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #define MMX_WR0 (0x00) #define MMX_WR1 (0x08) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 5e435e42dacd..a94d75fef598 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -658,11 +658,12 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, /* * Block the signal if we were unsuccessful. */ - if (ret != 0 || !(ka->sa.sa_flags & SA_NODEFER)) { + if (ret != 0) { spin_lock_irq(&tsk->sighand->siglock); sigorsets(&tsk->blocked, &tsk->blocked, &ka->sa.sa_mask); - sigaddset(&tsk->blocked, sig); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(&tsk->blocked, sig); recalc_sigpending(); spin_unlock_irq(&tsk->sighand->siglock); } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index b2085735a2ba..826164945747 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -110,7 +110,7 @@ int __cpuinit __cpu_up(unsigned int cpu) * We need to tell the secondary core where to find * its stack and the page tables. */ - secondary_data.stack = (void *)idle->thread_info + THREAD_SIZE - 8; + secondary_data.stack = (void *)idle->thread_info + THREAD_START_SP; secondary_data.pgdir = virt_to_phys(pgd); wmb(); diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index f897ce2ccf0d..42629ff84f5a 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -311,3 +311,13 @@ long execve(const char *filename, char **argv, char **envp) return ret; } EXPORT_SYMBOL(execve); + +/* + * Since loff_t is a 64 bit type we avoid a lot of ABI hastle + * with a different argument ordering. + */ +asmlinkage long sys_arm_fadvise64_64(int fd, int advice, + loff_t offset, loff_t len) +{ + return sys_fadvise64_64(fd, offset, len, advice); +} diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 1b7fcd50c3e2..69449a818dcc 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -102,7 +102,7 @@ static unsigned long next_rtc_update; */ static inline void do_set_rtc(void) { - if (time_status & STA_UNSYNC || set_rtc == NULL) + if (!ntp_synced() || set_rtc == NULL) return; if (next_rtc_update && @@ -292,10 +292,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); return 0; @@ -433,10 +430,12 @@ void timer_dyn_reprogram(void) { struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; - write_seqlock(&xtime_lock); - if (dyn_tick->state & DYN_TICK_ENABLED) - dyn_tick->reprogram(next_timer_interrupt() - jiffies); - write_sequnlock(&xtime_lock); + if (dyn_tick) { + write_seqlock(&xtime_lock); + if (dyn_tick->state & DYN_TICK_ENABLED) + dyn_tick->reprogram(next_timer_interrupt() - jiffies); + write_sequnlock(&xtime_lock); + } } static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf) diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index d571c37ac30c..4554c961251c 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -617,7 +617,7 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs) notify_die("unknown data abort code", regs, &info, instr, 0); } -volatile void __bug(const char *file, int line, void *data) +void __attribute__((noreturn)) __bug(const char *file, int line, void *data) { printk(KERN_CRIT"kernel BUG at %s:%d!", file, line); if (data) diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S index 4c38abdbe497..68117968482b 100644 --- a/arch/arm/lib/copy_page.S +++ b/arch/arm/lib/copy_page.S @@ -11,7 +11,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #define COPY_COUNT (PAGE_SZ/64 PLD( -1 )) diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index 46a2dc962e9d..333bca292de9 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -13,7 +13,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <asm/errno.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> .text diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 64aa6f4fe5e4..d204018070a4 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S @@ -26,7 +26,7 @@ * Note that ADDR_LIMIT is either 0 or 0xc0000000. * Note also that it is intended that __get_user_bad is not global. */ -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/thread_info.h> #include <asm/errno.h> diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index b09398d95aac..4593e9c07f05 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S @@ -26,7 +26,7 @@ * Note that ADDR_LIMIT is either 0 or 0xc0000000 * Note also that it is intended that __put_user_bad is not global. */ -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/thread_info.h> #include <asm/errno.h> diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c index 112f1d68fb2b..e216ab8b9e8f 100644 --- a/arch/arm/mach-clps7500/core.c +++ b/arch/arm/mach-clps7500/core.c @@ -354,7 +354,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 23c4da10101b..5aeadfd72143 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -219,7 +219,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-epxa10db/arch.c b/arch/arm/mach-epxa10db/arch.c index 7daa021676d0..44c56571d183 100644 --- a/arch/arm/mach-epxa10db/arch.c +++ b/arch/arm/mach-epxa10db/arch.c @@ -52,7 +52,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index 324d9edeec38..bdd257921cfb 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -87,6 +87,7 @@ config FOOTBRIDGE_ADDIN # EBSA285 board in either host or addin mode config ARCH_EBSA285 + select ARCH_MAY_HAVE_PC_FDC bool endif diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index b21016070ea3..e1c43b331d64 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -95,7 +95,7 @@ isa_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) } desc = irq_desc + isa_irq; - desc->handle(isa_irq, desc, regs); + desc_handle_irq(isa_irq, desc, regs); } static struct irqaction irq_cascade = { .handler = no_action, .name = "cascade", }; diff --git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c index aa3a1fef563e..28846c7edaaf 100644 --- a/arch/arm/mach-footbridge/isa.c +++ b/arch/arm/mach-footbridge/isa.c @@ -34,7 +34,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 96aa3af70d86..5110e2e65ddd 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -108,7 +108,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq, while (mask) { if (mask & 1) { IRQDBG("handling irq %d\n", irq); - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } irq++; desc++; diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index 593b6a2a30e1..a4a7c0125d03 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -90,7 +90,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, @@ -126,7 +126,7 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc, desc = irq_desc + irq; while (mask) { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); irq++; desc++; mask >>= 1; diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c index 0c2713426dfd..eeb8a6d4a399 100644 --- a/arch/arm/mach-imx/irq.c +++ b/arch/arm/mach-imx/irq.c @@ -152,7 +152,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq, while (mask) { if (mask & 1) { DEBUG_IRQ("handling irq %d\n", irq); - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } irq++; desc++; @@ -214,7 +214,7 @@ static struct irqchip imx_gpio_chip = { .ack = imx_gpio_ack_irq, .mask = imx_gpio_mask_irq, .unmask = imx_gpio_unmask_irq, - .type = imx_gpio_irq_type, + .set_type = imx_gpio_irq_type, }; void __init diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 569f328c479d..2be5c03ab87f 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -170,7 +170,7 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) irq += IRQ_SIC_START; desc = irq_desc + irq; - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } while (status); } diff --git a/arch/arm/mach-iop3xx/iop321-time.c b/arch/arm/mach-iop3xx/iop321-time.c index d53af1669502..0039793b694a 100644 --- a/arch/arm/mach-iop3xx/iop321-time.c +++ b/arch/arm/mach-iop3xx/iop321-time.c @@ -60,7 +60,7 @@ static unsigned long iop321_gettimeoffset(void) /* * Now convert them to usec. */ - usec = (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; + usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); return usec; } diff --git a/arch/arm/mach-iop3xx/iop331-time.c b/arch/arm/mach-iop3xx/iop331-time.c index 1a6d9d661e4b..8eddfac7e2b0 100644 --- a/arch/arm/mach-iop3xx/iop331-time.c +++ b/arch/arm/mach-iop3xx/iop331-time.c @@ -58,7 +58,7 @@ static unsigned long iop331_gettimeoffset(void) /* * Now convert them to usec. */ - usec = (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; + usec = (unsigned long)(elapsed / (CLOCK_TICK_RATE/1000000)); return usec; } diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 45b18658499f..74bd2fd602d4 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c @@ -174,7 +174,7 @@ static struct resource ixp2000_uart_resource = { static struct platform_device ixp2000_serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = ixp2000_serial_port, }, @@ -317,7 +317,7 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, str for (i = 0; i <= 7; i++) { if (status & (1<<i)) { desc = irq_desc + i + IRQ_IXP2000_GPIO0; - desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs); + desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc, regs); } } } @@ -380,10 +380,10 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq) } static struct irqchip ixp2000_GPIO_irq_chip = { - .type = ixp2000_GPIO_irq_type, - .ack = ixp2000_GPIO_irq_mask_ack, - .mask = ixp2000_GPIO_irq_mask, - .unmask = ixp2000_GPIO_irq_unmask + .ack = ixp2000_GPIO_irq_mask_ack, + .mask = ixp2000_GPIO_irq_mask, + .unmask = ixp2000_GPIO_irq_unmask, + .set_type = ixp2000_GPIO_irq_type, }; static void ixp2000_pci_irq_mask(unsigned int irq) diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index a43369ad876c..63ba0191aa65 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -133,7 +133,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc, struct struct irqdesc *cpld_desc; int cpld_irq = IXP2000_BOARD_IRQ(0) + i; cpld_desc = irq_desc + cpld_irq; - cpld_desc->handle(cpld_irq, cpld_desc, regs); + desc_handle_irq(cpld_irq, cpld_desc, regs); } } diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 43447dad1657..7a5109921287 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -82,7 +82,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct struct irqdesc *cpld_desc; int cpld_irq = IXP2000_BOARD_IRQ(0) + i; cpld_desc = irq_desc + cpld_irq; - cpld_desc->handle(cpld_irq, cpld_desc, regs); + desc_handle_irq(cpld_irq, cpld_desc, regs); } } diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 04490a9f8f6e..52ad11328e96 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -38,90 +38,6 @@ #include <asm/mach/irq.h> #include <asm/mach/time.h> -enum ixp4xx_irq_type { - IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE -}; -static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); - -/************************************************************************* - * GPIO acces functions - *************************************************************************/ - -/* - * Configure GPIO line for input, interrupt, or output operation - * - * TODO: Enable/disable the irq_desc based on interrupt or output mode. - * TODO: Should these be named ixp4xx_gpio_? - */ -void gpio_line_config(u8 line, u32 style) -{ - static const int gpio2irq[] = { - 6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 - }; - u32 enable; - volatile u32 *int_reg; - u32 int_style; - enum ixp4xx_irq_type irq_type; - - enable = *IXP4XX_GPIO_GPOER; - - if (style & IXP4XX_GPIO_OUT) { - enable &= ~((1) << line); - } else if (style & IXP4XX_GPIO_IN) { - enable |= ((1) << line); - - switch (style & IXP4XX_GPIO_INTSTYLE_MASK) - { - case (IXP4XX_GPIO_ACTIVE_HIGH): - int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; - irq_type = IXP4XX_IRQ_LEVEL; - break; - case (IXP4XX_GPIO_ACTIVE_LOW): - int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; - irq_type = IXP4XX_IRQ_LEVEL; - break; - case (IXP4XX_GPIO_RISING_EDGE): - int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; - irq_type = IXP4XX_IRQ_EDGE; - break; - case (IXP4XX_GPIO_FALLING_EDGE): - int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; - irq_type = IXP4XX_IRQ_EDGE; - break; - case (IXP4XX_GPIO_TRANSITIONAL): - int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; - irq_type = IXP4XX_IRQ_EDGE; - break; - default: - int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; - irq_type = IXP4XX_IRQ_LEVEL; - break; - } - - if (style & IXP4XX_GPIO_INTSTYLE_MASK) - ixp4xx_config_irq(gpio2irq[line], irq_type); - - if (line >= 8) { /* pins 8-15 */ - line -= 8; - int_reg = IXP4XX_GPIO_GPIT2R; - } - else { /* pins 0-7 */ - int_reg = IXP4XX_GPIO_GPIT1R; - } - - /* Clear the style for the appropriate pin */ - *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << - (line * IXP4XX_GPIO_STYLE_SIZE)); - - /* Set the new style */ - *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); - } - - *IXP4XX_GPIO_GPOER = enable; -} - -EXPORT_SYMBOL(gpio_line_config); - /************************************************************************* * IXP4xx chipset I/O mapping *************************************************************************/ @@ -165,6 +81,69 @@ void __init ixp4xx_map_io(void) * (be it PCI or something else) configures that GPIO line * as an IRQ. **************************************************************************/ +enum ixp4xx_irq_type { + IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE +}; + +static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type); + +/* + * IRQ -> GPIO mapping table + */ +static int irq2gpio[32] = { + -1, -1, -1, -1, -1, -1, 0, 1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, -1, -1, +}; + +static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) +{ + int line = irq2gpio[irq]; + u32 int_style; + enum ixp4xx_irq_type irq_type; + volatile u32 *int_reg; + + /* + * Only for GPIO IRQs + */ + if (line < 0) + return -EINVAL; + + if (type & IRQT_BOTHEDGE) { + int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; + irq_type = IXP4XX_IRQ_EDGE; + } else if (type & IRQT_RISING) { + int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; + irq_type = IXP4XX_IRQ_EDGE; + } else if (type & IRQT_FALLING) { + int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; + irq_type = IXP4XX_IRQ_EDGE; + } else if (type & IRQT_HIGH) { + int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; + irq_type = IXP4XX_IRQ_LEVEL; + } else if (type & IRQT_LOW) { + int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; + irq_type = IXP4XX_IRQ_LEVEL; + } + + ixp4xx_config_irq(irq, irq_type); + + if (line >= 8) { /* pins 8-15 */ + line -= 8; + int_reg = IXP4XX_GPIO_GPIT2R; + } else { /* pins 0-7 */ + int_reg = IXP4XX_GPIO_GPIT1R; + } + + /* Clear the style for the appropriate pin */ + *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << + (line * IXP4XX_GPIO_STYLE_SIZE)); + + /* Set the new style */ + *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); +} + static void ixp4xx_irq_mask(unsigned int irq) { if (cpu_is_ixp46x() && irq >= 32) @@ -183,12 +162,6 @@ static void ixp4xx_irq_unmask(unsigned int irq) static void ixp4xx_irq_ack(unsigned int irq) { - static int irq2gpio[32] = { - -1, -1, -1, -1, -1, -1, 0, 1, - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 2, 3, 4, 5, 6, - 7, 8, 9, 10, 11, 12, -1, -1, - }; int line = (irq < 32) ? irq2gpio[irq] : -1; if (line >= 0) @@ -206,15 +179,17 @@ static void ixp4xx_irq_level_unmask(unsigned int irq) } static struct irqchip ixp4xx_irq_level_chip = { - .ack = ixp4xx_irq_mask, - .mask = ixp4xx_irq_mask, - .unmask = ixp4xx_irq_level_unmask, + .ack = ixp4xx_irq_mask, + .mask = ixp4xx_irq_mask, + .unmask = ixp4xx_irq_level_unmask, + .set_type = ixp4xx_set_irq_type, }; static struct irqchip ixp4xx_irq_edge_chip = { - .ack = ixp4xx_irq_ack, - .mask = ixp4xx_irq_mask, - .unmask = ixp4xx_irq_unmask, + .ack = ixp4xx_irq_ack, + .mask = ixp4xx_irq_mask, + .unmask = ixp4xx_irq_unmask, + .set_type = ixp4xx_set_irq_type, }; static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type) diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index afafb42ae129..60de8a94cff5 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -30,11 +30,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); void __init coyote_pci_preinit(void) { - gpio_line_config(COYOTE_PCI_SLOT0_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); - - gpio_line_config(COYOTE_PCI_SLOT1_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); + set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); + set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW); gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN); gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN); diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index 7f58afb27e71..050c92768913 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c @@ -24,11 +24,6 @@ #include <asm/mach/arch.h> #include <asm/mach/flash.h> -void __init coyote_map_io(void) -{ - ixp4xx_map_io(); -} - static struct flash_platform_data coyote_flash_data = { .map_name = "cfi_probe", .width = 2, @@ -36,7 +31,7 @@ static struct flash_platform_data coyote_flash_data = { static struct resource coyote_flash_resource = { .start = COYOTE_FLASH_BASE, - .end = COYOTE_FLASH_BASE + COYOTE_FLASH_SIZE, + .end = COYOTE_FLASH_BASE + COYOTE_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }; @@ -71,7 +66,7 @@ static struct plat_serial8250_port coyote_uart_data[] = { static struct platform_device coyote_uart = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = coyote_uart_data, }, @@ -107,7 +102,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = coyote_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, @@ -125,7 +120,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = coyote_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index b18035824e3e..a66484b63d36 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -35,26 +35,20 @@ extern void ixp4xx_pci_preinit(void); extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); - /* - * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h - * Slot 0 isn't actually populated with a card connector but - * we initialize it anyway in case a future version has the - * slot populated or someone with good soldering skills has - * some free time. - */ - - -static void gtwx5715_init_gpio(u8 pin, u32 style) -{ - gpio_line_config(pin, style | IXP4XX_GPIO_ACTIVE_LOW); - - if (style & IXP4XX_GPIO_IN) gpio_line_isr_clear(pin); -} +/* + * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h + * Slot 0 isn't actually populated with a card connector but + * we initialize it anyway in case a future version has the + * slot populated or someone with good soldering skills has + * some free time. + */ void __init gtwx5715_pci_preinit(void) { - gtwx5715_init_gpio(GTWX5715_PCI_SLOT0_INTA_GPIO, IXP4XX_GPIO_IN); - gtwx5715_init_gpio(GTWX5715_PCI_SLOT1_INTA_GPIO, IXP4XX_GPIO_IN); + set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW); + set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW); + set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW); + set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 65e356bd10d6..29a6d02fa851 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -93,7 +93,7 @@ static struct plat_serial8250_port gtwx5715_uart_platform_data[] = { static struct platform_device gtwx5715_uart_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = gtwx5715_uart_platform_data, }, @@ -101,12 +101,6 @@ static struct platform_device gtwx5715_uart_device = { .resource = gtwx5715_uart_resources, }; - -void __init gtwx5715_map_io(void) -{ - ixp4xx_map_io(); -} - static struct flash_platform_data gtwx5715_flash_data = { .map_name = "cfi_probe", .width = 2, @@ -114,7 +108,7 @@ static struct flash_platform_data gtwx5715_flash_data = { static struct resource gtwx5715_flash_resource = { .start = GTWX5715_FLASH_BASE, - .end = GTWX5715_FLASH_BASE + GTWX5715_FLASH_SIZE, + .end = GTWX5715_FLASH_BASE + GTWX5715_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }; @@ -144,7 +138,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_UART2_BASE_PHYS, .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc, - .map_io = gtwx5715_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index c2ab9ebb5980..f9a1d3e7d692 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -27,14 +27,10 @@ void __init ixdp425_pci_preinit(void) { - gpio_line_config(IXDP425_PCI_INTA_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); - gpio_line_config(IXDP425_PCI_INTB_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); - gpio_line_config(IXDP425_PCI_INTC_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); - gpio_line_config(IXDP425_PCI_INTD_PIN, - IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW); + set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW); gpio_line_isr_clear(IXDP425_PCI_INTA_PIN); gpio_line_isr_clear(IXDP425_PCI_INTB_PIN); diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 4633470a6a37..ae1fa099d5fa 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -24,11 +24,6 @@ #include <asm/mach/arch.h> #include <asm/mach/flash.h> -void __init ixdp425_map_io(void) -{ - ixp4xx_map_io(); -} - static struct flash_platform_data ixdp425_flash_data = { .map_name = "cfi_probe", .width = 2, @@ -36,7 +31,7 @@ static struct flash_platform_data ixdp425_flash_data = { static struct resource ixdp425_flash_resource = { .start = IXDP425_FLASH_BASE, - .end = IXDP425_FLASH_BASE + IXDP425_FLASH_SIZE, + .end = IXDP425_FLASH_BASE + IXDP425_FLASH_SIZE - 1, .flags = IORESOURCE_MEM, }; @@ -101,7 +96,7 @@ static struct plat_serial8250_port ixdp425_uart_data[] = { static struct platform_device ixdp425_uart = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev.platform_data = ixdp425_uart_data, .num_resources = 2, .resource = ixdp425_uart_resources @@ -133,7 +128,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = ixdp425_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, @@ -145,7 +140,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = ixdp425_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, @@ -157,7 +152,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = ixdp425_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, @@ -176,7 +171,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform") .phys_ram = PHYS_OFFSET, .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, - .map_io = ixdp425_map_io, + .map_io = ixp4xx_map_io, .init_irq = ixp4xx_init_irq, .timer = &ixp4xx_timer, .boot_params = 0x0100, diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index ce4563f00676..fe5e7660de1d 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -29,8 +29,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); void __init ixdpg425_pci_preinit(void) { - gpio_line_config(6, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); - gpio_line_config(7, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW); + set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); + set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW); gpio_line_isr_clear(6); gpio_line_isr_clear(7); diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h index beda7c2602fb..578a52461fdb 100644 --- a/arch/arm/mach-lh7a40x/common.h +++ b/arch/arm/mach-lh7a40x/common.h @@ -13,4 +13,4 @@ extern struct sys_timer lh7a40x_timer; extern void lh7a400_init_irq (void); extern void lh7a404_init_irq (void); -#define IRQ_DISPATCH(irq) irq_desc[irq].handle ((irq), &irq_desc[irq], regs) +#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs) diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 7408ac94f771..27fc2e8e5fca 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -47,6 +47,14 @@ config MACH_OMAP_OSK TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here if you have such a board. +config OMAP_OSK_MISTRAL + bool "Mistral QVGA board Support" + depends on MACH_OMAP_OSK + help + The OSK supports an optional add-on board with a Quarter-VGA + touchscreen, PDA-ish buttons, a resume button, bicolor LED, + and camera connector. Say Y here if you have this board. + config MACH_OMAP_PERSEUS2 bool "TI Perseus2" depends on ARCH_OMAP1 && ARCH_OMAP730 diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index d386fd913f0c..181a93deaaee 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := io.o id.o irq.o time.o serial.o +obj-y := io.o id.o irq.o time.o serial.o devices.o led-y := leds.o # Specific board support @@ -23,6 +23,7 @@ endif # LEDs support led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o +led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 122796ebe8f5..c209c7172a9a 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -48,19 +48,43 @@ static struct omap_usb_config generic1510_usb_config __initdata = { #if defined(CONFIG_ARCH_OMAP16XX) static struct omap_usb_config generic1610_usb_config __initdata = { +#ifdef CONFIG_USB_OTG + .otg = 1, +#endif .register_host = 1, .register_dev = 1, .hmc_mode = 16, .pins[0] = 6, }; + +static struct omap_mmc_config generic_mmc_config __initdata = { + .mmc [0] = { + .enabled = 0, + .wire4 = 0, + .wp_pin = -1, + .power_pin = -1, + .switch_pin = -1, + }, + .mmc [1] = { + .enabled = 0, + .wire4 = 0, + .wp_pin = -1, + .power_pin = -1, + .switch_pin = -1, + }, +}; + #endif static struct omap_board_config_kernel generic_config[] = { { OMAP_TAG_USB, NULL }, + { OMAP_TAG_MMC, &generic_mmc_config }, }; static void __init omap_generic_init(void) { + const struct omap_uart_config *uart_conf; + /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on @@ -76,6 +100,18 @@ static void __init omap_generic_init(void) generic_config[0].data = &generic1610_usb_config; } #endif + + uart_conf = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); + if (uart_conf != NULL) { + unsigned int enabled_ports, i; + + enabled_ports = uart_conf->enabled_uarts; + for (i = 0; i < 3; i++) { + if (!(enabled_ports & (1 << i))) + generic_serial_ports[i] = 0; + } + } + omap_board_config = generic_config; omap_board_config_size = ARRAY_SIZE(generic_config); omap_serial_init(generic_serial_ports); @@ -83,7 +119,7 @@ static void __init omap_generic_init(void) static void __init omap_generic_map_io(void) { - omap_map_common_io() + omap_map_common_io(); } MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index f4983ee95ab4..d46a70063b0c 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -33,6 +33,7 @@ #include <asm/mach/map.h> #include <asm/arch/gpio.h> +#include <asm/arch/mux.h> #include <asm/arch/tc.h> #include <asm/arch/usb.h> #include <asm/arch/common.h> @@ -80,8 +81,7 @@ static struct flash_platform_data h2_flash_data = { }; static struct resource h2_flash_resource = { - .start = OMAP_CS2B_PHYS, - .end = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1, + /* This is on CS3, wherever it's mapped */ .flags = IORESOURCE_MEM, }; @@ -126,10 +126,9 @@ static void __init h2_init_smc91x(void) printk("Error requesting gpio 0 for smc91x irq\n"); return; } - omap_set_gpio_edge_ctrl(0, OMAP_GPIO_FALLING_EDGE); } -void h2_init_irq(void) +static void __init h2_init_irq(void) { omap_init_irq(); omap_gpio_init(); @@ -152,9 +151,13 @@ static struct omap_usb_config h2_usb_config __initdata = { }; static struct omap_mmc_config h2_mmc_config __initdata = { - .mmc_blocks = 1, - .mmc1_power_pin = -1, /* tps65010 gpio3 */ - .mmc1_switch_pin = OMAP_MPUIO(1), + .mmc [0] = { + .enabled = 1, + .wire4 = 1, + .wp_pin = OMAP_MPUIO(3), + .power_pin = -1, /* tps65010 gpio3 */ + .switch_pin = OMAP_MPUIO(1), + }, }; static struct omap_board_config_kernel h2_config[] = { @@ -164,6 +167,16 @@ static struct omap_board_config_kernel h2_config[] = { static void __init h2_init(void) { + /* NOTE: revC boards support NAND-boot, which can put NOR on CS2B + * and NAND (either 16bit or 8bit) on CS3. + */ + h2_flash_resource.end = h2_flash_resource.start = omap_cs3_phys(); + h2_flash_resource.end += SZ_32M - 1; + + /* MMC: card detect and WP */ + // omap_cfg_reg(U19_ARMIO1); /* CD */ + omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ + platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); omap_board_config = h2_config; omap_board_config_size = ARRAY_SIZE(h2_config); diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 7cd419d61b40..2798613696fa 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -82,8 +82,7 @@ static struct flash_platform_data h3_flash_data = { }; static struct resource h3_flash_resource = { - .start = OMAP_CS2B_PHYS, - .end = OMAP_CS2B_PHYS + OMAP_CS2B_SIZE - 1, + /* This is on CS3, wherever it's mapped */ .flags = IORESOURCE_MEM, }; @@ -161,13 +160,26 @@ static struct omap_usb_config h3_usb_config __initdata = { .pins[1] = 3, }; +static struct omap_mmc_config h3_mmc_config __initdata = { + .mmc[0] = { + .enabled = 1, + .power_pin = -1, /* tps65010 GPIO4 */ + .switch_pin = OMAP_MPUIO(1), + }, +}; + static struct omap_board_config_kernel h3_config[] = { { OMAP_TAG_USB, &h3_usb_config }, + { OMAP_TAG_MMC, &h3_mmc_config }, }; static void __init h3_init(void) { + h3_flash_resource.end = h3_flash_resource.start = omap_cs3_phys(); + h3_flash_resource.end += OMAP_CS3_SIZE - 1; (void) platform_add_devices(devices, ARRAY_SIZE(devices)); + omap_board_config = h3_config; + omap_board_config_size = ARRAY_SIZE(h3_config); } static void __init h3_init_smc91x(void) @@ -177,7 +189,6 @@ static void __init h3_init_smc91x(void) printk("Error requesting gpio 40 for smc91x irq\n"); return; } - omap_set_gpio_edge_ctrl(40, OMAP_GPIO_FALLING_EDGE); } void h3_init_irq(void) diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 91de60a91ef8..df0312b596e4 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -29,6 +29,7 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> +#include <asm/arch/mux.h> #include <asm/arch/fpga.h> #include <asm/arch/gpio.h> #include <asm/arch/tc.h> @@ -173,7 +174,6 @@ static void __init innovator_init_smc91x(void) printk("Error requesting gpio 0 for smc91x irq\n"); return; } - omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE); } } @@ -220,8 +220,19 @@ static struct omap_usb_config h2_usb_config __initdata = { }; #endif +static struct omap_mmc_config innovator_mmc_config __initdata = { + .mmc [0] = { + .enabled = 1, + .wire4 = 1, + .wp_pin = OMAP_MPUIO(3), + .power_pin = -1, /* FPGA F3 UIO42 */ + .switch_pin = -1, /* FPGA F4 UIO43 */ + }, +}; + static struct omap_board_config_kernel innovator_config[] = { { OMAP_TAG_USB, NULL }, + { OMAP_TAG_MMC, &innovator_mmc_config }, }; static void __init innovator_init(void) diff --git a/arch/arm/mach-omap1/board-netstar.c b/arch/arm/mach-omap1/board-netstar.c index 6750b2014092..d904e643f5ec 100644 --- a/arch/arm/mach-omap1/board-netstar.c +++ b/arch/arm/mach-omap1/board-netstar.c @@ -75,16 +75,15 @@ static void __init netstar_init(void) mdelay(50); /* 50ms until PHY ready */ /* smc91x interrupt pin */ omap_request_gpio(8); - omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE); omap_request_gpio(12); omap_request_gpio(13); omap_request_gpio(14); omap_request_gpio(15); - omap_set_gpio_edge_ctrl(12, OMAP_GPIO_FALLING_EDGE); - omap_set_gpio_edge_ctrl(13, OMAP_GPIO_FALLING_EDGE); - omap_set_gpio_edge_ctrl(14, OMAP_GPIO_FALLING_EDGE); - omap_set_gpio_edge_ctrl(15, OMAP_GPIO_FALLING_EDGE); + set_irq_type(OMAP_GPIO_IRQ(12), IRQT_FALLING); + set_irq_type(OMAP_GPIO_IRQ(13), IRQT_FALLING); + set_irq_type(OMAP_GPIO_IRQ(14), IRQT_FALLING); + set_irq_type(OMAP_GPIO_IRQ(15), IRQT_FALLING); platform_add_devices(netstar_devices, ARRAY_SIZE(netstar_devices)); diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 6844e536c698..21103df50415 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -29,11 +29,16 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/device.h> +#include <linux/interrupt.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> #include <asm/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/flash.h> #include <asm/arch/gpio.h> #include <asm/arch/usb.h> @@ -41,12 +46,56 @@ #include <asm/arch/tc.h> #include <asm/arch/common.h> -static struct map_desc osk5912_io_desc[] __initdata = { -{ OMAP_OSK_NOR_FLASH_BASE, OMAP_OSK_NOR_FLASH_START, OMAP_OSK_NOR_FLASH_SIZE, - MT_DEVICE }, +static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0}; + +static struct mtd_partition osk_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "bootloader", + .offset = 0, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } }; -static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0}; +static struct flash_platform_data osk_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = osk_partitions, + .nr_parts = ARRAY_SIZE(osk_partitions), +}; + +static struct resource osk_flash_resource = { + /* this is on CS3, wherever it's mapped */ + .flags = IORESOURCE_MEM, +}; + +static struct platform_device osk5912_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &osk_flash_data, + }, + .num_resources = 1, + .resource = &osk_flash_resource, +}; static struct resource osk5912_smc91x_resources[] = { [0] = { @@ -86,9 +135,16 @@ static struct platform_device osk5912_cf_device = { .resource = osk5912_cf_resources, }; +static struct platform_device osk5912_mcbsp1_device = { + .name = "omap_mcbsp", + .id = 1, +}; + static struct platform_device *osk5912_devices[] __initdata = { + &osk5912_flash_device, &osk5912_smc91x_device, &osk5912_cf_device, + &osk5912_mcbsp1_device, }; static void __init osk_init_smc91x(void) @@ -97,7 +153,6 @@ static void __init osk_init_smc91x(void) printk("Error requesting gpio 0 for smc91x irq\n"); return; } - omap_set_gpio_edge_ctrl(0, OMAP_GPIO_RISING_EDGE); /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */ EMIFS_CCS(1) |= 0x2; @@ -110,11 +165,11 @@ static void __init osk_init_cf(void) printk("Error requesting gpio 62 for CF irq\n"); return; } - /* it's really active-low */ - omap_set_gpio_edge_ctrl(62, OMAP_GPIO_FALLING_EDGE); + /* the CF I/O IRQ is really active-low */ + set_irq_type(OMAP_GPIO_IRQ(62), IRQT_FALLING); } -void osk_init_irq(void) +static void __init osk_init_irq(void) { omap_init_irq(); omap_gpio_init(); @@ -142,18 +197,69 @@ static struct omap_board_config_kernel osk_config[] = { { OMAP_TAG_USB, &osk_usb_config }, }; +#ifdef CONFIG_OMAP_OSK_MISTRAL + +#ifdef CONFIG_PM +static irqreturn_t +osk_mistral_wake_interrupt(int irq, void *ignored, struct pt_regs *regs) +{ + return IRQ_HANDLED; +} +#endif + +static void __init osk_mistral_init(void) +{ + /* FIXME here's where to feed in framebuffer, touchpad, and + * keyboard setup ... not in the drivers for those devices! + * + * NOTE: we could actually tell if there's a Mistral board + * attached, e.g. by trying to read something from the ads7846. + * But this is too early for that... + */ + + /* the sideways button (SW1) is for use as a "wakeup" button */ + omap_cfg_reg(N15_1610_MPUIO2); + if (omap_request_gpio(OMAP_MPUIO(2)) == 0) { + int ret = 0; + omap_set_gpio_direction(OMAP_MPUIO(2), 1); + set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING); +#ifdef CONFIG_PM + /* share the IRQ in case someone wants to use the + * button for more than wakeup from system sleep. + */ + ret = request_irq(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), + &osk_mistral_wake_interrupt, + SA_SHIRQ, "mistral_wakeup", + &osk_mistral_wake_interrupt); + if (ret != 0) { + omap_free_gpio(OMAP_MPUIO(2)); + printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", + ret); + } else + enable_irq_wake(OMAP_GPIO_IRQ(OMAP_MPUIO(2))); +#endif + } else + printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); +} +#else +static void __init osk_mistral_init(void) { } +#endif + static void __init osk_init(void) { + osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys(); + osk_flash_resource.end += SZ_32M - 1; platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices)); omap_board_config = osk_config; omap_board_config_size = ARRAY_SIZE(osk_config); USB_TRANSCEIVER_CTRL_REG |= (3 << 1); + + osk_mistral_init(); } static void __init osk_map_io(void) { omap_map_common_io(); - iotable_init(osk5912_io_desc, ARRAY_SIZE(osk5912_io_desc)); omap_serial_init(osk_serial_ports); } diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 213317392d9b..107c68c8ab54 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -24,6 +24,7 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> +#include <asm/arch/tc.h> #include <asm/arch/gpio.h> #include <asm/arch/mux.h> #include <asm/arch/fpga.h> @@ -83,8 +84,8 @@ static struct flash_platform_data p2_flash_data = { }; static struct resource p2_flash_resource = { - .start = OMAP_FLASH_0_START, - .end = OMAP_FLASH_0_START + OMAP_FLASH_0_SIZE - 1, + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index e42281988990..bf30b1acda0b 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -25,13 +25,14 @@ #include <asm/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/mach/flash.h> #include <asm/mach/map.h> +#include <asm/arch/common.h> #include <asm/arch/gpio.h> -#include <asm/arch/tc.h> #include <asm/arch/mux.h> +#include <asm/arch/tc.h> #include <asm/arch/usb.h> -#include <asm/arch/common.h> extern void omap_init_time(void); extern int omap_gpio_init(void); @@ -74,7 +75,7 @@ static struct plat_serial8250_port voiceblue_ports[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev = { .platform_data = voiceblue_ports, }, @@ -86,6 +87,27 @@ static int __init ext_uart_init(void) } arch_initcall(ext_uart_init); +static struct flash_platform_data voiceblue_flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource voiceblue_flash_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device voiceblue_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &voiceblue_flash_data, + }, + .num_resources = 1, + .resource = &voiceblue_flash_resource, +}; + static struct resource voiceblue_smc91x_resources[] = { [0] = { .start = OMAP_CS2_PHYS + 0x300, @@ -107,6 +129,7 @@ static struct platform_device voiceblue_smc91x_device = { }; static struct platform_device *voiceblue_devices[] __initdata = { + &voiceblue_flash_device, &voiceblue_smc91x_device, }; @@ -119,8 +142,17 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { .pins[2] = 6, }; +static struct omap_mmc_config voiceblue_mmc_config __initdata = { + .mmc[0] = { + .enabled = 1, + .power_pin = 2, + .switch_pin = -1, + }, +}; + static struct omap_board_config_kernel voiceblue_config[] = { { OMAP_TAG_USB, &voiceblue_usb_config }, + { OMAP_TAG_MMC, &voiceblue_mmc_config }, }; static void __init voiceblue_init_irq(void) @@ -131,9 +163,6 @@ static void __init voiceblue_init_irq(void) static void __init voiceblue_init(void) { - /* There is a good chance board is going up, so enable Power LED - * (it is connected through invertor) */ - omap_writeb(0x00, OMAP_LPG1_LCR); /* Watchdog */ omap_request_gpio(0); /* smc91x reset */ @@ -145,7 +174,6 @@ static void __init voiceblue_init(void) mdelay(50); /* 50ms until PHY ready */ /* smc91x interrupt pin */ omap_request_gpio(8); - omap_set_gpio_edge_ctrl(8, OMAP_GPIO_RISING_EDGE); /* 16C554 reset*/ omap_request_gpio(6); omap_set_gpio_direction(6, 0); @@ -155,14 +183,19 @@ static void __init voiceblue_init(void) omap_request_gpio(13); omap_request_gpio(14); omap_request_gpio(15); - omap_set_gpio_edge_ctrl(12, OMAP_GPIO_RISING_EDGE); - omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE); - omap_set_gpio_edge_ctrl(14, OMAP_GPIO_RISING_EDGE); - omap_set_gpio_edge_ctrl(15, OMAP_GPIO_RISING_EDGE); + set_irq_type(OMAP_GPIO_IRQ(12), IRQT_RISING); + set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING); + set_irq_type(OMAP_GPIO_IRQ(14), IRQT_RISING); + set_irq_type(OMAP_GPIO_IRQ(15), IRQT_RISING); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); omap_board_config = voiceblue_config; omap_board_config_size = ARRAY_SIZE(voiceblue_config); + + /* There is a good chance board is going up, so enable power LED + * (it is connected through invertor) */ + omap_writeb(0x00, OMAP_LPG1_LCR); + omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ } static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1}; @@ -184,9 +217,9 @@ static int panic_event(struct notifier_block *this, unsigned long event, if (test_and_set_bit(MACHINE_PANICED, &machine_state)) return NOTIFY_DONE; - /* Flash Power LED - * (TODO: Enable clock right way (enabled in bootloader already)) */ + /* Flash power LED */ omap_writeb(0x78, OMAP_LPG1_LCR); + omap_writeb(0x01, OMAP_LPG1_PMR); /* Enable clock */ return NOTIFY_DONE; } @@ -195,15 +228,14 @@ static struct notifier_block panic_block = { .notifier_call = panic_event, }; -static int __init setup_notifier(void) +static int __init voiceblue_setup(void) { /* Setup panic notifier */ notifier_chain_register(&panic_notifier_list, &panic_block); return 0; } - -postcore_initcall(setup_notifier); +postcore_initcall(voiceblue_setup); static int wdt_gpio_state; diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c new file mode 100644 index 000000000000..e8b3981444cd --- /dev/null +++ b/arch/arm/mach-omap1/devices.c @@ -0,0 +1,351 @@ +/* + * linux/arch/arm/mach-omap1/devices.c + * + * OMAP1 platform device setup/initialization + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/config.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/mach/map.h> + +#include <asm/arch/tc.h> +#include <asm/arch/board.h> +#include <asm/arch/mux.h> +#include <asm/arch/gpio.h> + + +static void omap_nop_release(struct device *dev) +{ + /* Nothing */ +} + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) + +#define OMAP_I2C_BASE 0xfffb3800 + +static struct resource i2c_resources[] = { + { + .start = OMAP_I2C_BASE, + .end = OMAP_I2C_BASE + 0x3f, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +/* DMA not used; works around erratum writing to non-empty i2c fifo */ + +static struct platform_device omap_i2c_device = { + .name = "i2c_omap", + .id = -1, + .dev = { + .release = omap_nop_release, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static void omap_init_i2c(void) +{ + /* FIXME define and use a boot tag, in case of boards that + * either don't wire up I2C, or chips that mux it differently... + * it can include clocking and address info, maybe more. + */ + omap_cfg_reg(I2C_SCL); + omap_cfg_reg(I2C_SDA); + + (void) platform_device_register(&omap_i2c_device); +} +#else +static inline void omap_init_i2c(void) {} +#endif + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_OMAP1610_IR) || defined(CONFIG_OMAP161O_IR_MODULE) + +static u64 irda_dmamask = 0xffffffff; + +static struct platform_device omap1610ir_device = { + .name = "omap1610-ir", + .id = -1, + .dev = { + .release = omap_nop_release, + .dma_mask = &irda_dmamask, + }, +}; + +static void omap_init_irda(void) +{ + /* FIXME define and use a boot tag, members something like: + * u8 uart; // uart1, or uart3 + * ... but driver only handles uart3 for now + * s16 fir_sel; // gpio for SIR vs FIR + * ... may prefer a callback for SIR/MIR/FIR mode select; + * while h2 uses a GPIO, H3 uses a gpio expander + */ + if (machine_is_omap_h2() + || machine_is_omap_h3()) + (void) platform_device_register(&omap1610ir_device); +} +#else +static inline void omap_init_irda(void) {} +#endif + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + +#define OMAP_MMC1_BASE 0xfffb7800 +#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */ + +static struct omap_mmc_conf mmc1_conf; + +static u64 mmc1_dmamask = 0xffffffff; + +static struct resource mmc1_resources[] = { + { + .start = IO_ADDRESS(OMAP_MMC1_BASE), + .end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MMC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mmc_omap_device1 = { + .name = "mmci-omap", + .id = 1, + .dev = { + .release = omap_nop_release, + .dma_mask = &mmc1_dmamask, + .platform_data = &mmc1_conf, + }, + .num_resources = ARRAY_SIZE(mmc1_resources), + .resource = mmc1_resources, +}; + +#ifdef CONFIG_ARCH_OMAP16XX + +static struct omap_mmc_conf mmc2_conf; + +static u64 mmc2_dmamask = 0xffffffff; + +static struct resource mmc2_resources[] = { + { + .start = IO_ADDRESS(OMAP_MMC2_BASE), + .end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_1610_MMC2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mmc_omap_device2 = { + .name = "mmci-omap", + .id = 2, + .dev = { + .release = omap_nop_release, + .dma_mask = &mmc2_dmamask, + .platform_data = &mmc2_conf, + }, + .num_resources = ARRAY_SIZE(mmc2_resources), + .resource = mmc2_resources, +}; +#endif + +static void __init omap_init_mmc(void) +{ + const struct omap_mmc_config *mmc_conf; + const struct omap_mmc_conf *mmc; + + /* NOTE: assumes MMC was never (wrongly) enabled */ + mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config); + if (!mmc_conf) + return; + + /* block 1 is always available and has just one pinout option */ + mmc = &mmc_conf->mmc[0]; + if (mmc->enabled) { + omap_cfg_reg(MMC_CMD); + omap_cfg_reg(MMC_CLK); + omap_cfg_reg(MMC_DAT0); + if (cpu_is_omap1710()) { + omap_cfg_reg(M15_1710_MMC_CLKI); + omap_cfg_reg(P19_1710_MMC_CMDDIR); + omap_cfg_reg(P20_1710_MMC_DATDIR0); + } + if (mmc->wire4) { + omap_cfg_reg(MMC_DAT1); + /* NOTE: DAT2 can be on W10 (here) or M15 */ + if (!mmc->nomux) + omap_cfg_reg(MMC_DAT2); + omap_cfg_reg(MMC_DAT3); + } + mmc1_conf = *mmc; + (void) platform_device_register(&mmc_omap_device1); + } + +#ifdef CONFIG_ARCH_OMAP16XX + /* block 2 is on newer chips, and has many pinout options */ + mmc = &mmc_conf->mmc[1]; + if (mmc->enabled) { + if (!mmc->nomux) { + omap_cfg_reg(Y8_1610_MMC2_CMD); + omap_cfg_reg(Y10_1610_MMC2_CLK); + omap_cfg_reg(R18_1610_MMC2_CLKIN); + omap_cfg_reg(W8_1610_MMC2_DAT0); + if (mmc->wire4) { + omap_cfg_reg(V8_1610_MMC2_DAT1); + omap_cfg_reg(W15_1610_MMC2_DAT2); + omap_cfg_reg(R10_1610_MMC2_DAT3); + } + + /* These are needed for the level shifter */ + omap_cfg_reg(V9_1610_MMC2_CMDDIR); + omap_cfg_reg(V5_1610_MMC2_DATDIR0); + omap_cfg_reg(W19_1610_MMC2_DATDIR1); + } + + /* Feedback clock must be set on OMAP-1710 MMC2 */ + if (cpu_is_omap1710()) + omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), + MOD_CONF_CTRL_1); + mmc2_conf = *mmc; + (void) platform_device_register(&mmc_omap_device2); + } +#endif + return; +} +#else +static inline void omap_init_mmc(void) {} +#endif + +#if defined(CONFIG_OMAP_RTC) || defined(CONFIG_OMAP_RTC) + +#define OMAP_RTC_BASE 0xfffb4800 + +static struct resource rtc_resources[] = { + { + .start = OMAP_RTC_BASE, + .end = OMAP_RTC_BASE + 0x5f, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_RTC_TIMER, + .flags = IORESOURCE_IRQ, + }, + { + .start = INT_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device omap_rtc_device = { + .name = "omap_rtc", + .id = -1, + .dev = { + .release = omap_nop_release, + }, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static void omap_init_rtc(void) +{ + (void) platform_device_register(&omap_rtc_device); +} +#else +static inline void omap_init_rtc(void) {} +#endif + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_OMAP16XX_WATCHDOG) || defined(CONFIG_OMAP16XX_WATCHDOG_MODULE) + +#define OMAP_WDT_BASE 0xfffeb000 + +static struct resource wdt_resources[] = { + { + .start = OMAP_WDT_BASE, + .end = OMAP_WDT_BASE + 0x4f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap_wdt_device = { + .name = "omap1610_wdt", + .id = -1, + .dev = { + .release = omap_nop_release, + }, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void omap_init_wdt(void) +{ + (void) platform_device_register(&omap_wdt_device); +} +#else +static inline void omap_init_wdt(void) {} +#endif + + +/*-------------------------------------------------------------------------*/ + +/* + * This gets called after board-specific INIT_MACHINE, and initializes most + * on-chip peripherals accessible on this board (except for few like USB): + * + * (a) Does any "standard config" pin muxing needed. Board-specific + * code will have muxed GPIO pins and done "nonstandard" setup; + * that code could live in the boot loader. + * (b) Populating board-specific platform_data with the data drivers + * rely on to handle wiring variations. + * (c) Creating platform devices as meaningful on this board and + * with this kernel configuration. + * + * Claiming GPIOs, and setting their direction and initial values, is the + * responsibility of the device drivers. So is responding to probe(). + * + * Board-specific knowlege like creating devices or pin setup is to be + * kept out of drivers as much as possible. In particular, pin setup + * may be handled by the boot loader, and drivers should expect it will + * normally have been done by the time they're probed. + */ +static int __init omap_init_devices(void) +{ + /* please keep these calls, and their implementations above, + * in alphabetical order so they're easier to sort through. + */ + omap_init_i2c(); + omap_init_irda(); + omap_init_mmc(); + omap_init_rtc(); + omap_init_wdt(); + + return 0; +} +arch_initcall(omap_init_devices); + diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 7c08f6c2e1d0..aca2a120813a 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/fpga.c + * linux/arch/arm/mach-omap1/fpga.c * * Interrupt handler for OMAP-1510 Innovator FPGA * @@ -102,7 +102,7 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc, fpga_irq++, stat >>= 1) { if (stat & 1) { d = irq_desc + fpga_irq; - d->handle(fpga_irq, d, regs); + desc_handle_irq(fpga_irq, d, regs); } } } @@ -181,7 +181,7 @@ void omap1510_fpga_init_irq(void) */ omap_request_gpio(13); omap_set_gpio_direction(13, 1); - omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE); + set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING); set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); } diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 207df0fe934d..eb8261d7dead 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -19,6 +19,7 @@ extern int clk_init(void); extern void omap_check_revision(void); +extern void omap_sram_init(void); /* * The machine specific code may provide the extra mapping besides the @@ -32,7 +33,6 @@ static struct map_desc omap_io_desc[] __initdata = { static struct map_desc omap730_io_desc[] __initdata = { { OMAP730_DSP_BASE, OMAP730_DSP_START, OMAP730_DSP_SIZE, MT_DEVICE }, { OMAP730_DSPREG_BASE, OMAP730_DSPREG_START, OMAP730_DSPREG_SIZE, MT_DEVICE }, - { OMAP730_SRAM_BASE, OMAP730_SRAM_START, OMAP730_SRAM_SIZE, MT_DEVICE } }; #endif @@ -40,27 +40,13 @@ static struct map_desc omap730_io_desc[] __initdata = { static struct map_desc omap1510_io_desc[] __initdata = { { OMAP1510_DSP_BASE, OMAP1510_DSP_START, OMAP1510_DSP_SIZE, MT_DEVICE }, { OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START, OMAP1510_DSPREG_SIZE, MT_DEVICE }, - { OMAP1510_SRAM_BASE, OMAP1510_SRAM_START, OMAP1510_SRAM_SIZE, MT_DEVICE } }; #endif #if defined(CONFIG_ARCH_OMAP16XX) -static struct map_desc omap1610_io_desc[] __initdata = { +static struct map_desc omap16xx_io_desc[] __initdata = { { OMAP16XX_DSP_BASE, OMAP16XX_DSP_START, OMAP16XX_DSP_SIZE, MT_DEVICE }, { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, MT_DEVICE }, - { OMAP16XX_SRAM_BASE, OMAP16XX_SRAM_START, OMAP1610_SRAM_SIZE, MT_DEVICE } -}; - -static struct map_desc omap5912_io_desc[] __initdata = { - { OMAP16XX_DSP_BASE, OMAP16XX_DSP_START, OMAP16XX_DSP_SIZE, MT_DEVICE }, - { OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START, OMAP16XX_DSPREG_SIZE, MT_DEVICE }, -/* - * The OMAP5912 has 250kByte internal SRAM. Because the mapping is baseed on page - * size (4kByte), it seems that the last 2kByte (=0x800) of the 250kByte are not mapped. - * Add additional 2kByte (0x800) so that the last page is mapped and the last 2kByte - * can be used. - */ - { OMAP16XX_SRAM_BASE, OMAP16XX_SRAM_START, OMAP5912_SRAM_SIZE + 0x800, MT_DEVICE } }; #endif @@ -86,14 +72,13 @@ static void __init _omap_map_io(void) } #endif #if defined(CONFIG_ARCH_OMAP16XX) - if (cpu_is_omap1610() || cpu_is_omap1710()) { - iotable_init(omap1610_io_desc, ARRAY_SIZE(omap1610_io_desc)); - } - if (cpu_is_omap5912()) { - iotable_init(omap5912_io_desc, ARRAY_SIZE(omap5912_io_desc)); + if (cpu_is_omap16xx()) { + iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc)); } #endif + omap_sram_init(); + /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort * on a Posted Write in the TIPB Bridge". */ @@ -108,8 +93,9 @@ static void __init _omap_map_io(void) /* * This should only get called from board specific init */ -void omap_map_common_io(void) +void __init omap_map_common_io(void) { if (!initialized) _omap_map_io(); } + diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index a11b6d807352..192ce6055faa 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/irq.c + * linux/arch/arm/mach-omap1/irq.c * * Interrupt handler for all OMAP boards * @@ -165,10 +165,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = { #endif static struct irqchip omap_irq_chip = { - .ack = omap_mask_ack_irq, - .mask = omap_mask_irq, - .unmask = omap_unmask_irq, - .wake = omap_wake_irq, + .ack = omap_mask_ack_irq, + .mask = omap_mask_irq, + .unmask = omap_unmask_irq, + .set_wake = omap_wake_irq, }; void __init omap_init_irq(void) diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c index ec0d8285f243..be283cda63dd 100644 --- a/arch/arm/mach-omap1/leds-h2p2-debug.c +++ b/arch/arm/mach-omap1/leds-h2p2-debug.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/leds-h2p2-debug.c + * linux/arch/arm/mach-omap1/leds-h2p2-debug.c * * Copyright 2003 by Texas Instruments Incorporated * @@ -13,6 +13,7 @@ #include <linux/init.h> #include <linux/kernel_stat.h> #include <linux/sched.h> +#include <linux/version.h> #include <asm/io.h> #include <asm/hardware.h> diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c index 8043b7d0f66e..c8ffd1ddcded 100644 --- a/arch/arm/mach-omap1/leds-innovator.c +++ b/arch/arm/mach-omap1/leds-innovator.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/leds-innovator.c + * linux/arch/arm/mach-omap1/leds-innovator.c */ #include <linux/config.h> #include <linux/init.h> diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c index 4a0e8b9d4fc3..2c8bda847c18 100644 --- a/arch/arm/mach-omap1/leds-osk.c +++ b/arch/arm/mach-omap1/leds-osk.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/leds-osk.c + * linux/arch/arm/mach-omap1/leds-osk.c * * LED driver for OSK, and optionally Mistral QVGA, boards */ @@ -64,7 +64,7 @@ static void tps_work(void *unused) static DECLARE_WORK(work, tps_work, NULL); -#ifdef CONFIG_FB_OMAP +#ifdef CONFIG_OMAP_OSK_MISTRAL /* For now, all system indicators require the Mistral board, since that * LED can be manipulated without a task context. This LED is either red, @@ -127,7 +127,7 @@ void osk_leds_event(led_event_t evt) hw_led_state = 0; break; -#ifdef CONFIG_FB_OMAP +#ifdef CONFIG_OMAP_OSK_MISTRAL case led_timer: hw_led_state ^= TIMER_LED; @@ -144,7 +144,7 @@ void osk_leds_event(led_event_t evt) mistral_setled(); break; -#endif /* CONFIG_FB_OMAP */ +#endif /* CONFIG_OMAP_OSK_MISTRAL */ /* "green" == tps LED1 (leftmost, normally power-good) * works only with DC adapter, not on battery power! diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c index 8ab21fe98e1b..5c6b1bb6e722 100644 --- a/arch/arm/mach-omap1/leds.c +++ b/arch/arm/mach-omap1/leds.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-omap/leds.c + * linux/arch/arm/mach-omap1/leds.c * * OMAP LEDs dispatcher */ @@ -20,7 +20,9 @@ omap_leds_init(void) if (machine_is_omap_innovator()) leds_event = innovator_leds_event; - else if (machine_is_omap_h2() || machine_is_omap_perseus2()) + else if (machine_is_omap_h2() + || machine_is_omap_h3() + || machine_is_omap_perseus2()) leds_event = h2p2_dbg_leds_event; else if (machine_is_omap_osk()) @@ -30,8 +32,12 @@ omap_leds_init(void) return -1; if (machine_is_omap_h2() + || machine_is_omap_h3() || machine_is_omap_perseus2() - || machine_is_omap_osk()) { +#ifdef CONFIG_OMAP_OSK_MISTRAL + || machine_is_omap_osk() +#endif + ) { /* LED1/LED2 pins can be used as GPIO (as done here), or by * the LPG (works even in deep sleep!), to drive a bicolor diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 214e5d17c8b5..40c4f7c40e73 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -24,7 +24,11 @@ #include <asm/arch/board.h> #include <asm/arch/mux.h> +#include <asm/arch/gpio.h> #include <asm/arch/fpga.h> +#ifdef CONFIG_PM +#include <asm/arch/pm.h> +#endif static struct clk * uart1_ck = NULL; static struct clk * uart2_ck = NULL; @@ -94,7 +98,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, @@ -193,6 +197,86 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS]) } } +#ifdef CONFIG_OMAP_SERIAL_WAKE + +static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + /* Need to do something with serial port right after wake-up? */ + return IRQ_HANDLED; +} + +/* + * Reroutes serial RX lines to GPIO lines for the duration of + * sleep to allow waking up the device from serial port even + * in deep sleep. + */ +void omap_serial_wake_trigger(int enable) +{ + if (!cpu_is_omap16xx()) + return; + + if (uart1_ck != NULL) { + if (enable) + omap_cfg_reg(V14_16XX_GPIO37); + else + omap_cfg_reg(V14_16XX_UART1_RX); + } + if (uart2_ck != NULL) { + if (enable) + omap_cfg_reg(R9_16XX_GPIO18); + else + omap_cfg_reg(R9_16XX_UART2_RX); + } + if (uart3_ck != NULL) { + if (enable) + omap_cfg_reg(L14_16XX_GPIO49); + else + omap_cfg_reg(L14_16XX_UART3_RX); + } +} + +static void __init omap_serial_set_port_wakeup(int gpio_nr) +{ + int ret; + + ret = omap_request_gpio(gpio_nr); + if (ret < 0) { + printk(KERN_ERR "Could not request UART wake GPIO: %i\n", + gpio_nr); + return; + } + omap_set_gpio_direction(gpio_nr, 1); + set_irq_type(OMAP_GPIO_IRQ(gpio_nr), IRQT_RISING); + ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt, + 0, "serial wakeup", NULL); + if (ret) { + omap_free_gpio(gpio_nr); + printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", + gpio_nr); + return; + } + enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr)); +} + +static int __init omap_serial_wakeup_init(void) +{ + if (!cpu_is_omap16xx()) + return 0; + + if (uart1_ck != NULL) + omap_serial_set_port_wakeup(37); + if (uart2_ck != NULL) + omap_serial_set_port_wakeup(18); + if (uart3_ck != NULL) + omap_serial_set_port_wakeup(49); + + return 0; +} +late_initcall(omap_serial_wakeup_init); + +#endif /* CONFIG_OMAP_SERIAL_WAKE */ + static int __init omap_init(void) { return platform_device_register(&serial_device); diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index d540539c9bbb..191a9b1ee9b7 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -247,13 +247,6 @@ unsigned long long sched_clock(void) #define OMAP_32K_TIMER_TCR 0x04 #define OMAP_32K_TICKS_PER_HZ (32768 / HZ) -#if (32768 % HZ) != 0 -/* We cannot ignore modulo. - * Potential error can be as high as several percent. - */ -#define OMAP_32K_TICK_MODULO (32768 % HZ) -static unsigned modulo_count = 0; /* Counts 1/HZ units */ -#endif /* * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 @@ -296,13 +289,22 @@ static inline void omap_32k_timer_stop(void) } /* - * Rounds down to nearest usec + * Rounds down to nearest usec. Note that this will overflow for larger values. */ static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k) { return (ticks_32k * 5*5*5*5*5*5) >> 9; } +/* + * Rounds down to nearest nsec. + */ +static inline unsigned long long +omap_32k_ticks_to_nsecs(unsigned long ticks_32k) +{ + return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9; +} + static unsigned long omap_32k_last_tick = 0; /* @@ -315,6 +317,15 @@ static unsigned long omap_32k_timer_gettimeoffset(void) } /* + * Returns current time from boot in nsecs. It's OK for this to wrap + * around for now, as it's just a relative time stamp. + */ +unsigned long long sched_clock(void) +{ + return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read()); +} + +/* * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this * function is also called from other interrupts to remove latency * issues with dynamic tick. In the dynamic tick case, we need to lock @@ -330,19 +341,6 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id, now = omap_32k_sync_timer_read(); while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) { -#ifdef OMAP_32K_TICK_MODULO - /* Modulo addition may put omap_32k_last_tick ahead of now - * and cause unwanted repetition of the while loop. - */ - if (unlikely(now - omap_32k_last_tick == ~0)) - break; - - modulo_count += OMAP_32K_TICK_MODULO; - if (modulo_count > HZ) { - ++omap_32k_last_tick; - modulo_count -= HZ; - } -#endif omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ; timer_tick(regs); } diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index efc2f657184e..33dae99ec2d8 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_PXA27x) += pxa27x.o obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o -obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o ssp.o +obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o ssp.o obj-$(CONFIG_MACH_POODLE) += poodle.o # Support for blinky lights diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 86b862f56e7e..07b5dd453565 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -39,7 +39,6 @@ #include <asm/mach/sharpsl_param.h> #include <asm/hardware/scoop.h> -#include <video/w100fb.h> #include "generic.h" @@ -60,6 +59,15 @@ static struct scoop_config corgi_scoop_setup = { .io_out = CORGI_SCOOP_IO_OUT, }; +static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = { +{ + .dev = &corgiscoop_device.dev, + .irq = CORGI_IRQ_GPIO_CF_IRQ, + .cd_irq = CORGI_IRQ_GPIO_CF_CD, + .cd_irq_str = "PCMCIA0 CD", +}, +}; + struct platform_device corgiscoop_device = { .name = "sharp-scoop", .id = -1, @@ -78,7 +86,7 @@ struct platform_device corgiscoop_device = { * also use scoop functions and this makes the power up/down order * work correctly. */ -static struct platform_device corgissp_device = { +struct platform_device corgissp_device = { .name = "corgi-ssp", .dev = { .parent = &corgiscoop_device.dev, @@ -88,41 +96,33 @@ static struct platform_device corgissp_device = { /* - * Corgi w100 Frame Buffer Device + * Corgi Backlight Device */ -static struct w100fb_mach_info corgi_fb_info = { - .w100fb_ssp_send = corgi_ssp_lcdtg_send, - .comadj = -1, - .phadadj = -1, -}; - -static struct resource corgi_fb_resources[] = { - [0] = { - .start = 0x08000000, - .end = 0x08ffffff, - .flags = IORESOURCE_MEM, +static struct platform_device corgibl_device = { + .name = "corgi-bl", + .dev = { + .parent = &corgifb_device.dev, }, + .id = -1, }; -static struct platform_device corgifb_device = { - .name = "w100fb", + +/* + * Corgi Keyboard Device + */ +static struct platform_device corgikbd_device = { + .name = "corgi-keyboard", .id = -1, - .dev = { - .platform_data = &corgi_fb_info, - .parent = &corgissp_device.dev, - }, - .num_resources = ARRAY_SIZE(corgi_fb_resources), - .resource = corgi_fb_resources, }; /* - * Corgi Backlight Device + * Corgi Touch Screen Device */ -static struct platform_device corgibl_device = { - .name = "corgi-bl", +static struct platform_device corgits_device = { + .name = "corgi-ts", .dev = { - .parent = &corgifb_device.dev, + .parent = &corgissp_device.dev, }, .id = -1, }; @@ -131,27 +131,12 @@ static struct platform_device corgibl_device = { /* * MMC/SD Device * - * The card detect interrupt isn't debounced so we delay it by HZ/4 + * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert/eject. */ -static struct mmc_detect { - struct timer_list detect_timer; - void *devid; -} mmc_detect; - -static void mmc_detect_callback(unsigned long data) -{ - mmc_detect_change(mmc_detect.devid); -} +static struct pxamci_platform_data corgi_mci_platform_data; -static irqreturn_t corgi_mmc_detect_int(int irq, void *devid, struct pt_regs *regs) -{ - mmc_detect.devid=devid; - mod_timer(&mmc_detect.detect_timer, jiffies + HZ/4); - return IRQ_HANDLED; -} - -static int corgi_mci_init(struct device *dev, irqreturn_t (*unused_detect_int)(int, void *, struct pt_regs *), void *data) +static int corgi_mci_init(struct device *dev, irqreturn_t (*corgi_detect_int)(int, void *, struct pt_regs *), void *data) { int err; @@ -161,11 +146,9 @@ static int corgi_mci_init(struct device *dev, irqreturn_t (*unused_detect_int)(i pxa_gpio_mode(CORGI_GPIO_nSD_DETECT | GPIO_IN); pxa_gpio_mode(CORGI_GPIO_SD_PWR | GPIO_OUT); - init_timer(&mmc_detect.detect_timer); - mmc_detect.detect_timer.function = mmc_detect_callback; - mmc_detect.detect_timer.data = (unsigned long) &mmc_detect; + corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250); - err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_mmc_detect_int, SA_INTERRUPT, + err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int, SA_INTERRUPT, "MMC card detect", data); if (err) { printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); @@ -190,20 +173,26 @@ static void corgi_mci_setpower(struct device *dev, unsigned int vdd) } } +static int corgi_mci_get_ro(struct device *dev) +{ + return GPLR(CORGI_GPIO_nSD_WP) & GPIO_bit(CORGI_GPIO_nSD_WP); +} + static void corgi_mci_exit(struct device *dev, void *data) { free_irq(CORGI_IRQ_GPIO_nSD_DETECT, data); - del_timer(&mmc_detect.detect_timer); } static struct pxamci_platform_data corgi_mci_platform_data = { .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, .init = corgi_mci_init, + .get_ro = corgi_mci_get_ro, .setpower = corgi_mci_setpower, .exit = corgi_mci_exit, }; + /* * USB Device Controller */ @@ -229,18 +218,20 @@ static struct platform_device *devices[] __initdata = { &corgiscoop_device, &corgissp_device, &corgifb_device, + &corgikbd_device, &corgibl_device, + &corgits_device, }; static void __init corgi_init(void) { - corgi_fb_info.comadj=sharpsl_param.comadj; - corgi_fb_info.phadadj=sharpsl_param.phadadj; - pxa_gpio_mode(CORGI_GPIO_USB_PULLUP | GPIO_OUT); pxa_set_udc_info(&udc_info); pxa_set_mci_info(&corgi_mci_platform_data); + scoop_num = 1; + scoop_devs = &corgi_pcmcia_scoop[0]; + platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c new file mode 100644 index 000000000000..deac29c00290 --- /dev/null +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -0,0 +1,396 @@ +/* + * linux/drivers/video/w100fb.c + * + * Corgi LCD Specific Code for ATI Imageon w100 (Wallaby) + * + * Copyright (C) 2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <asm/arch/corgi.h> +#include <asm/mach/sharpsl_param.h> +#include <video/w100fb.h> + +/* Register Addresses */ +#define RESCTL_ADRS 0x00 +#define PHACTRL_ADRS 0x01 +#define DUTYCTRL_ADRS 0x02 +#define POWERREG0_ADRS 0x03 +#define POWERREG1_ADRS 0x04 +#define GPOR3_ADRS 0x05 +#define PICTRL_ADRS 0x06 +#define POLCTRL_ADRS 0x07 + +/* Resgister Bit Definitions */ +#define RESCTL_QVGA 0x01 +#define RESCTL_VGA 0x00 + +#define POWER1_VW_ON 0x01 /* VW Supply FET ON */ +#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */ +#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */ + +#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */ +#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */ +#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */ + +#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ +#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ +#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ +#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ +#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ + +#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ +#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ +#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ + +#define PICTRL_INIT_STATE 0x01 +#define PICTRL_INIOFF 0x02 +#define PICTRL_POWER_DOWN 0x04 +#define PICTRL_COM_SIGNAL_OFF 0x08 +#define PICTRL_DAC_SIGNAL_OFF 0x10 + +#define POLCTRL_SYNC_POL_FALL 0x01 +#define POLCTRL_EN_POL_FALL 0x02 +#define POLCTRL_DATA_POL_FALL 0x04 +#define POLCTRL_SYNC_ACT_H 0x08 +#define POLCTRL_EN_ACT_L 0x10 + +#define POLCTRL_SYNC_POL_RISE 0x00 +#define POLCTRL_EN_POL_RISE 0x00 +#define POLCTRL_DATA_POL_RISE 0x00 +#define POLCTRL_SYNC_ACT_L 0x00 +#define POLCTRL_EN_ACT_H 0x00 + +#define PHACTRL_PHASE_MANUAL 0x01 +#define DEFAULT_PHAD_QVGA (9) +#define DEFAULT_COMADJ (125) + +/* + * This is only a psuedo I2C interface. We can't use the standard kernel + * routines as the interface is write only. We just assume the data is acked... + */ +static void lcdtg_ssp_i2c_send(u8 data) +{ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, data); + udelay(10); +} + +static void lcdtg_i2c_send_bit(u8 data) +{ + lcdtg_ssp_i2c_send(data); + lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK); + lcdtg_ssp_i2c_send(data); +} + +static void lcdtg_i2c_send_start(u8 base) +{ + lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT); + lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK); + lcdtg_ssp_i2c_send(base); +} + +static void lcdtg_i2c_send_stop(u8 base) +{ + lcdtg_ssp_i2c_send(base); + lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK); + lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT); +} + +static void lcdtg_i2c_send_byte(u8 base, u8 data) +{ + int i; + for (i = 0; i < 8; i++) { + if (data & 0x80) + lcdtg_i2c_send_bit(base | POWER0_COM_DOUT); + else + lcdtg_i2c_send_bit(base); + data <<= 1; + } +} + +static void lcdtg_i2c_wait_ack(u8 base) +{ + lcdtg_i2c_send_bit(base); +} + +static void lcdtg_set_common_voltage(u8 base_data, u8 data) +{ + /* Set Common Voltage to M62332FP via I2C */ + lcdtg_i2c_send_start(base_data); + lcdtg_i2c_send_byte(base_data, 0x9c); + lcdtg_i2c_wait_ack(base_data); + lcdtg_i2c_send_byte(base_data, 0x00); + lcdtg_i2c_wait_ack(base_data); + lcdtg_i2c_send_byte(base_data, data); + lcdtg_i2c_wait_ack(base_data); + lcdtg_i2c_send_stop(base_data); +} + +/* Set Phase Adjuct */ +static void lcdtg_set_phadadj(struct w100fb_par *par) +{ + int adj; + switch(par->xres) { + case 480: + case 640: + /* Setting for VGA */ + adj = sharpsl_param.phadadj; + if (adj < 0) { + adj = PHACTRL_PHASE_MANUAL; + } else { + adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL; + } + break; + case 240: + case 320: + default: + /* Setting for QVGA */ + adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL; + break; + } + + corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj); +} + +static int lcd_inited; + +static void lcdtg_hw_init(struct w100fb_par *par) +{ + if (!lcd_inited) { + int comadj; + + /* Initialize Internal Logic & Port */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE + | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF); + + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF + | POWER0_COM_OFF | POWER0_VCC5_OFF); + + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF); + + /* VDD(+8V), SVSS(-4V) ON */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON); + mdelay(3); + + /* DAC ON */ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON + | POWER0_COM_OFF | POWER0_VCC5_OFF); + + /* INIB = H, INI = L */ + /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF); + + /* Set Common Voltage */ + comadj = sharpsl_param.comadj; + if (comadj < 0) + comadj = DEFAULT_COMADJ; + lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj); + + /* VCC5 ON, DAC ON */ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON | + POWER0_COM_OFF | POWER0_VCC5_ON); + + /* GVSS(-8V) ON, VDD ON */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON); + mdelay(2); + + /* COM SIGNAL ON (PICTL[3] = L) */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE); + + /* COM ON, DAC ON, VCC5_ON */ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON + | POWER0_COM_ON | POWER0_VCC5_ON); + + /* VW ON, GVSS ON, VDD ON */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON); + + /* Signals output enable */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); + + /* Set Phase Adjuct */ + lcdtg_set_phadadj(par); + + /* Initialize for Input Signals from ATI */ + corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE + | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H); + udelay(1000); + + lcd_inited=1; + } else { + lcdtg_set_phadadj(par); + } + + switch(par->xres) { + case 480: + case 640: + /* Set Lcd Resolution (VGA) */ + corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA); + break; + case 240: + case 320: + default: + /* Set Lcd Resolution (QVGA) */ + corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA); + break; + } +} + +static void lcdtg_suspend(struct w100fb_par *par) +{ + /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */ + mdelay(34); + + /* (1)VW OFF */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON); + + /* (2)COM OFF */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF); + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON); + + /* (3)Set Common Voltage Bias 0V */ + lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0); + + /* (4)GVSS OFF */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON); + + /* (5)VCC5 OFF */ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF); + + /* (6)Set PDWN, INIOFF, DACOFF */ + corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF | + PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF); + + /* (7)DAC OFF */ + corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF); + + /* (8)VDD OFF */ + corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF); + + lcd_inited = 0; +} + +static struct w100_tg_info corgi_lcdtg_info = { + .change=lcdtg_hw_init, + .suspend=lcdtg_suspend, + .resume=lcdtg_hw_init, +}; + +/* + * Corgi w100 Frame Buffer Device + */ + +static struct w100_mem_info corgi_fb_mem = { + .ext_cntl = 0x00040003, + .sdram_mode_reg = 0x00650021, + .ext_timing_cntl = 0x10002a4a, + .io_cntl = 0x7ff87012, + .size = 0x1fffff, +}; + +static struct w100_gen_regs corgi_fb_regs = { + .lcd_format = 0x00000003, + .lcdd_cntl1 = 0x01CC0000, + .lcdd_cntl2 = 0x0003FFFF, + .genlcd_cntl1 = 0x00FFFF0D, + .genlcd_cntl2 = 0x003F3003, + .genlcd_cntl3 = 0x000102aa, +}; + +static struct w100_gpio_regs corgi_fb_gpio = { + .init_data1 = 0x000000bf, + .init_data2 = 0x00000000, + .gpio_dir1 = 0x00000000, + .gpio_oe1 = 0x03c0feff, + .gpio_dir2 = 0x00000000, + .gpio_oe2 = 0x00000000, +}; + +static struct w100_mode corgi_fb_modes[] = { +{ + .xres = 480, + .yres = 640, + .left_margin = 0x56, + .right_margin = 0x55, + .upper_margin = 0x03, + .lower_margin = 0x00, + .crtc_ss = 0x82360056, + .crtc_ls = 0xA0280000, + .crtc_gs = 0x80280028, + .crtc_vpos_gs = 0x02830002, + .crtc_rev = 0x00400008, + .crtc_dclk = 0xA0000000, + .crtc_gclk = 0x8015010F, + .crtc_goe = 0x80100110, + .crtc_ps1_active = 0x41060010, + .pll_freq = 75, + .fast_pll_freq = 100, + .sysclk_src = CLK_SRC_PLL, + .sysclk_divider = 0, + .pixclk_src = CLK_SRC_PLL, + .pixclk_divider = 2, + .pixclk_divider_rotated = 6, +},{ + .xres = 240, + .yres = 320, + .left_margin = 0x27, + .right_margin = 0x2e, + .upper_margin = 0x01, + .lower_margin = 0x00, + .crtc_ss = 0x81170027, + .crtc_ls = 0xA0140000, + .crtc_gs = 0xC0140014, + .crtc_vpos_gs = 0x00010141, + .crtc_rev = 0x00400008, + .crtc_dclk = 0xA0000000, + .crtc_gclk = 0x8015010F, + .crtc_goe = 0x80100110, + .crtc_ps1_active = 0x41060010, + .pll_freq = 0, + .fast_pll_freq = 0, + .sysclk_src = CLK_SRC_XTAL, + .sysclk_divider = 0, + .pixclk_src = CLK_SRC_XTAL, + .pixclk_divider = 1, + .pixclk_divider_rotated = 1, +}, + +}; + +static struct w100fb_mach_info corgi_fb_info = { + .tg = &corgi_lcdtg_info, + .init_mode = INIT_MODE_ROTATED, + .mem = &corgi_fb_mem, + .regs = &corgi_fb_regs, + .modelist = &corgi_fb_modes[0], + .num_modes = 2, + .gpio = &corgi_fb_gpio, + .xtal_freq = 12500000, + .xtal_dbl = 0, +}; + +static struct resource corgi_fb_resources[] = { + [0] = { + .start = 0x08000000, + .end = 0x08ffffff, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device corgifb_device = { + .name = "w100fb", + .id = -1, + .num_resources = ARRAY_SIZE(corgi_fb_resources), + .resource = corgi_fb_resources, + .dev = { + .platform_data = &corgi_fb_info, + .parent = &corgissp_device.dev, + }, + +}; diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 8ccffba0018f..366a9bde3d8b 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -22,7 +22,7 @@ #include <asm/arch/corgi.h> #include <asm/arch/pxa-regs.h> -static spinlock_t corgi_ssp_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(corgi_ssp_lock); static struct ssp_dev corgi_ssp_dev; static struct ssp_state corgi_ssp_state; diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index f3cac43124a5..539b596005fc 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -133,7 +133,7 @@ static struct irqchip pxa_low_gpio_chip = { .ack = pxa_ack_low_gpio, .mask = pxa_mask_low_irq, .unmask = pxa_unmask_low_irq, - .type = pxa_gpio_irq_type, + .set_type = pxa_gpio_irq_type, }; /* @@ -157,7 +157,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, mask >>= 2; do { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); irq++; desc++; mask >>= 1; @@ -172,7 +172,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, desc = irq_desc + irq; do { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); irq++; desc++; mask >>= 1; @@ -187,7 +187,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, desc = irq_desc + irq; do { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); irq++; desc++; mask >>= 1; @@ -203,7 +203,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc, desc = irq_desc + irq; do { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); irq++; desc++; mask >>= 1; @@ -241,7 +241,7 @@ static struct irqchip pxa_muxed_gpio_chip = { .ack = pxa_ack_muxed_gpio, .mask = pxa_mask_muxed_gpio, .unmask = pxa_unmask_muxed_gpio, - .type = pxa_gpio_irq_type, + .set_type = pxa_gpio_irq_type, }; diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 6309853b59be..923f6eb774c0 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -84,7 +84,7 @@ static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc, if (likely(pending)) { irq = LUBBOCK_IRQ(0) + __ffs(pending); desc = irq_desc + irq; - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; } while (pending); diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 827b7b5a5be8..85fdb5b1470a 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -72,7 +72,7 @@ static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc, if (likely(pending)) { irq = MAINSTONE_IRQ(0) + __ffs(pending); desc = irq_desc + irq; - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } pending = MST_INTSETCLR & mainstone_irq_enabled; } while (pending); diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 0e4f6fab100a..47cfb8bb8318 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -62,6 +62,15 @@ struct platform_device poodle_scoop_device = { .resource = poodle_scoop_resources, }; +static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = { +{ + .dev = &poodle_scoop_device.dev, + .irq = POODLE_IRQ_GPIO_CF_IRQ, + .cd_irq = POODLE_IRQ_GPIO_CF_CD, + .cd_irq_str = "PCMCIA0 CD", +}, +}; + /* LoCoMo device */ static struct resource locomo_resources[] = { @@ -147,6 +156,9 @@ static void __init poodle_init(void) set_pxa_fb_info(&poodle_fb_info); + scoop_num = 1; + scoop_devs = &poodle_pcmcia_scoop[0]; + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if (ret) { printk(KERN_WARNING "poodle: Unable to register LoCoMo device\n"); diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 6e5202154f91..7dad3f1465e0 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -70,6 +70,11 @@ static unsigned long pxa_gettimeoffset (void) return usec; } +#ifdef CONFIG_NO_IDLE_HZ +static unsigned long initial_match; +static int match_posponed; +#endif + static irqreturn_t pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { @@ -77,11 +82,19 @@ pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) write_seqlock(&xtime_lock); +#ifdef CONFIG_NO_IDLE_HZ + if (match_posponed) { + match_posponed = 0; + OSMR0 = initial_match; + } +#endif + /* Loop until we get ahead of the free running timer. * This ensures an exact clock tick count and time accuracy. - * IRQs are disabled inside the loop to ensure coherence between - * lost_ticks (updated in do_timer()) and the match reg value, so we - * can use do_gettimeofday() from interrupt handlers. + * Since IRQs are disabled at this point, coherence between + * lost_ticks(updated in do_timer()) and the match reg value is + * ensured, hence we can use do_gettimeofday() from interrupt + * handlers. * * HACK ALERT: it seems that the PXA timer regs aren't updated right * away in all cases when a write occurs. We therefore compare with @@ -126,6 +139,42 @@ static void __init pxa_timer_init(void) OSCR = 0; /* initialize free-running timer, force first match */ } +#ifdef CONFIG_NO_IDLE_HZ +static int pxa_dyn_tick_enable_disable(void) +{ + /* nothing to do */ + return 0; +} + +static void pxa_dyn_tick_reprogram(unsigned long ticks) +{ + if (ticks > 1) { + initial_match = OSMR0; + OSMR0 = initial_match + ticks * LATCH; + match_posponed = 1; + } +} + +static irqreturn_t +pxa_dyn_tick_handler(int irq, void *dev_id, struct pt_regs *regs) +{ + if (match_posponed) { + match_posponed = 0; + OSMR0 = initial_match; + if ( (signed long)(initial_match - OSCR) <= 8 ) + return pxa_timer_interrupt(irq, dev_id, regs); + } + return IRQ_NONE; +} + +static struct dyn_tick_timer pxa_dyn_tick = { + .enable = pxa_dyn_tick_enable_disable, + .disable = pxa_dyn_tick_enable_disable, + .reprogram = pxa_dyn_tick_reprogram, + .handler = pxa_dyn_tick_handler, +}; +#endif + #ifdef CONFIG_PM static unsigned long osmr[4], oier; @@ -161,4 +210,7 @@ struct sys_timer pxa_timer = { .suspend = pxa_timer_suspend, .resume = pxa_timer_resume, .offset = pxa_gettimeoffset, +#ifdef CONFIG_NO_IDLE_HZ + .dyn_tick = &pxa_dyn_tick, +#endif }; diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index a10268618f74..e3587efec4bf 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c @@ -140,7 +140,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index d4d03d0daaec..06807c6ee68a 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -2,6 +2,13 @@ if ARCH_S3C2410 menu "S3C24XX Implementations" +config MACH_ANUBIS + bool "Simtec Electronics ANUBIS" + select CPU_S3C2440 + help + Say Y gere if you are using the Simtec Electronics ANUBIS + development system + config ARCH_BAST bool "Simtec Electronics BAST (EB2410ITX)" select CPU_S3C2410 @@ -11,6 +18,14 @@ config ARCH_BAST Product page: <http://www.simtec.co.uk/products/EB2410ITX/>. +config BAST_PC104_IRQ + bool "BAST PC104 IRQ support" + depends on ARCH_BAST + default y + help + Say Y here to enable the PC104 IRQ routing on the + Simtec BAST (EB2410ITX) + config ARCH_H1940 bool "IPAQ H1940" select CPU_S3C2410 diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 55ed7c7e57da..b4f1e051c768 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -26,8 +26,13 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o +# bast extras + +obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o + # machine specific support +obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o obj-$(CONFIG_ARCH_H1940) += mach-h1940.o obj-$(CONFIG_MACH_N30) += mach-n30.o diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 5e5bbe893cbb..fbbeb0553006 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -1,6 +1,6 @@ /* linux/arch/arm/mach-s3c2410/bast-irq.c * - * Copyright (c) 2004 Simtec Electronics + * Copyright (c) 2003,2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * * http://www.simtec.co.uk/products/EB2410ITX/ @@ -21,7 +21,8 @@ * * Modifications: * 08-Jan-2003 BJD Moved from central IRQ code - */ + * 21-Aug-2005 BJD Fixed missing code and compile errors +*/ #include <linux/init.h> @@ -30,12 +31,19 @@ #include <linux/ptrace.h> #include <linux/sysdev.h> +#include <asm/mach-types.h> + #include <asm/hardware.h> #include <asm/irq.h> #include <asm/io.h> #include <asm/mach/irq.h> -#include <asm/hardware/s3c2410/irq.h> + +#include <asm/arch/regs-irq.h> +#include <asm/arch/bast-map.h> +#include <asm/arch/bast-irq.h> + +#include "irq.h" #if 0 #include <asm/debug-ll.h> @@ -79,15 +87,15 @@ bast_pc104_mask(unsigned int irqno) temp = __raw_readb(BAST_VA_PC104_IRQMASK); temp &= ~bast_pc104_irqmasks[irqno]; __raw_writeb(temp, BAST_VA_PC104_IRQMASK); - - if (temp == 0) - bast_extint_mask(IRQ_ISA); } static void -bast_pc104_ack(unsigned int irqno) +bast_pc104_maskack(unsigned int irqno) { - bast_extint_ack(IRQ_ISA); + struct irqdesc *desc = irq_desc + IRQ_ISA; + + bast_pc104_mask(irqno); + desc->chip->ack(IRQ_ISA); } static void @@ -98,14 +106,12 @@ bast_pc104_unmask(unsigned int irqno) temp = __raw_readb(BAST_VA_PC104_IRQMASK); temp |= bast_pc104_irqmasks[irqno]; __raw_writeb(temp, BAST_VA_PC104_IRQMASK); - - bast_extint_unmask(IRQ_ISA); } -static struct bast_pc104_chip = { +static struct irqchip bast_pc104_chip = { .mask = bast_pc104_mask, .unmask = bast_pc104_unmask, - .ack = bast_pc104_ack + .ack = bast_pc104_maskack }; static void @@ -119,14 +125,49 @@ bast_irq_pc104_demux(unsigned int irq, stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf; - for (i = 0; i < 4 && stat != 0; i++) { - if (stat & 1) { - irqno = bast_pc104_irqs[i]; - desc = irq_desc + irqno; + if (unlikely(stat == 0)) { + /* ack if we get an irq with nothing (ie, startup) */ + + desc = irq_desc + IRQ_ISA; + desc->chip->ack(IRQ_ISA); + } else { + /* handle the IRQ */ + + for (i = 0; stat != 0; i++, stat >>= 1) { + if (stat & 1) { + irqno = bast_pc104_irqs[i]; - desc->handle(irqno, desc, regs); + desc_handle_irq(irqno, irq_desc + irqno, regs); + } } + } +} - stat >>= 1; +static __init int bast_irq_init(void) +{ + unsigned int i; + + if (machine_is_bast()) { + printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n"); + + /* zap all the IRQs */ + + __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); + + set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); + + /* reigster our IRQs */ + + for (i = 0; i < 4; i++) { + unsigned int irqno = bast_pc104_irqs[i]; + + set_irq_chip(irqno, &bast_pc104_chip); + set_irq_handler(irqno, do_level_IRQ); + set_irq_flags(irqno, IRQF_VALID); + } } + + return 0; } + +arch_initcall(bast_irq_init); diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 9a66050e887d..f59608268751 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -388,6 +388,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, unsigned long hclk, unsigned long pclk) { + unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); struct clk *clkp = init_clocks; int ptr; int ret; @@ -446,5 +447,13 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, } } + /* show the clock-slow value */ + + printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", + print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), + (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", + (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", + (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); + return 0; } diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c index 4664bd11adc1..0077937a7ab8 100644 --- a/arch/arm/mach-s3c2410/devs.c +++ b/arch/arm/mach-s3c2410/devs.c @@ -29,7 +29,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> - +#include <asm/arch/fb.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/irq.h> @@ -103,6 +103,15 @@ struct platform_device s3c_device_lcd = { EXPORT_SYMBOL(s3c_device_lcd); +static struct s3c2410fb_mach_info s3c2410fb_info; + +void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info) +{ + memcpy(&s3c2410fb_info,hard_s3c2410fb_info,sizeof(struct s3c2410fb_mach_info)); + s3c_device_lcd.dev.platform_data = &s3c2410fb_info; +} +EXPORT_SYMBOL(set_s3c2410fb_info); + /* NAND Controller */ static struct resource s3c_nand_resource[] = { diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 973a5fe6769c..66d8c068e940 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -184,14 +184,14 @@ struct irqchip s3c_irq_level_chip = { .ack = s3c_irq_maskack, .mask = s3c_irq_mask, .unmask = s3c_irq_unmask, - .wake = s3c_irq_wake + .set_wake = s3c_irq_wake }; static struct irqchip s3c_irq_chip = { .ack = s3c_irq_ack, .mask = s3c_irq_mask, .unmask = s3c_irq_unmask, - .wake = s3c_irq_wake + .set_wake = s3c_irq_wake }; /* S3C2410_EINTMASK @@ -350,16 +350,16 @@ static struct irqchip s3c_irqext_chip = { .mask = s3c_irqext_mask, .unmask = s3c_irqext_unmask, .ack = s3c_irqext_ack, - .type = s3c_irqext_type, - .wake = s3c_irqext_wake + .set_type = s3c_irqext_type, + .set_wake = s3c_irqext_wake }; static struct irqchip s3c_irq_eint0t4 = { .ack = s3c_irq_ack, .mask = s3c_irq_mask, .unmask = s3c_irq_unmask, - .wake = s3c_irq_wake, - .type = s3c_irqext_type, + .set_wake = s3c_irq_wake, + .set_type = s3c_irqext_type, }; /* mask values for the parent registers for each of the interrupt types */ @@ -496,11 +496,11 @@ static void s3c_irq_demux_adc(unsigned int irq, if (subsrc != 0) { if (subsrc & 1) { mydesc = irq_desc + IRQ_TC; - mydesc->handle( IRQ_TC, mydesc, regs); + desc_handle_irq(IRQ_TC, mydesc, regs); } if (subsrc & 2) { mydesc = irq_desc + IRQ_ADC; - mydesc->handle(IRQ_ADC, mydesc, regs); + desc_handle_irq(IRQ_ADC, mydesc, regs); } } } @@ -529,17 +529,17 @@ static void s3c_irq_demux_uart(unsigned int start, desc = irq_desc + start; if (subsrc & 1) - desc->handle(start, desc, regs); + desc_handle_irq(start, desc, regs); desc++; if (subsrc & 2) - desc->handle(start+1, desc, regs); + desc_handle_irq(start+1, desc, regs); desc++; if (subsrc & 4) - desc->handle(start+2, desc, regs); + desc_handle_irq(start+2, desc, regs); } } diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c new file mode 100644 index 000000000000..f87aa0b669ad --- /dev/null +++ b/arch/arm/mach-s3c2410/mach-anubis.c @@ -0,0 +1,270 @@ +/* linux/arch/arm/mach-s3c2410/mach-anubis.c + * + * Copyright (c) 2003-2005 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 02-May-2005 BJD Copied from mach-bast.c +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/arch/anubis-map.h> +#include <asm/arch/anubis-irq.h> +#include <asm/arch/anubis-cpld.h> + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <asm/arch/regs-serial.h> +#include <asm/arch/regs-gpio.h> +#include <asm/arch/regs-mem.h> +#include <asm/arch/regs-lcd.h> +#include <asm/arch/nand.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/partitions.h> + +#include "clock.h" +#include "devs.h" +#include "cpu.h" + +#define COPYRIGHT ", (c) 2005 Simtec Electronics" + +static struct map_desc anubis_iodesc[] __initdata = { + /* ISA IO areas */ + + { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE }, + { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE }, + + /* we could possibly compress the next set down into a set of smaller tables + * pagetables, but that would mean using an L2 section, and it still means + * we cannot actually feed the same register to an LDR due to 16K spacing + */ + + /* CPLD control registers */ + + { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE }, + { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE }, + + /* IDE drives */ + + { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE }, + { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE }, + + { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE }, + { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE }, +}; + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { + [0] = { + .name = "uclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0. + } +}; + + +static struct s3c2410_uartcfg anubis_uartcfgs[] = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = anubis_serial_clocks, + .clocks_size = ARRAY_SIZE(anubis_serial_clocks) + }, + [1] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + .clocks = anubis_serial_clocks, + .clocks_size = ARRAY_SIZE(anubis_serial_clocks) + }, +}; + +/* NAND Flash on Anubis board */ + +static int external_map[] = { 2 }; +static int chip0_map[] = { 0 }; +static int chip1_map[] = { 1 }; + +struct mtd_partition anubis_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0 + }, + [1] = { + .name = "/boot", + .size = SZ_4M - SZ_16K, + .offset = SZ_16K, + }, + [2] = { + .name = "user1", + .offset = SZ_4M, + .size = SZ_32M - SZ_4M, + }, + [3] = { + .name = "user2", + .offset = SZ_32M, + .size = MTDPART_SIZ_FULL, + } +}; + +/* the Anubis has 3 selectable slots for nand-flash, the two + * on-board chip areas, as well as the external slot. + * + * Note, there is no current hot-plug support for the External + * socket. +*/ + +static struct s3c2410_nand_set anubis_nand_sets[] = { + [1] = { + .name = "External", + .nr_chips = 1, + .nr_map = external_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part + }, + [0] = { + .name = "chip0", + .nr_chips = 1, + .nr_map = chip0_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part + }, + [2] = { + .name = "chip1", + .nr_chips = 1, + .nr_map = chip1_map, + .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), + .partitions = anubis_default_nand_part + }, +}; + +static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) +{ + unsigned int tmp; + + slot = set->nr_map[slot] & 3; + + pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", + slot, set, set->nr_map); + + tmp = __raw_readb(ANUBIS_VA_CTRL1); + tmp &= ~ANUBIS_CTRL1_NANDSEL; + tmp |= slot; + + pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); + + __raw_writeb(tmp, ANUBIS_VA_CTRL1); +} + +static struct s3c2410_platform_nand anubis_nand_info = { + .tacls = 25, + .twrph0 = 80, + .twrph1 = 80, + .nr_sets = ARRAY_SIZE(anubis_nand_sets), + .sets = anubis_nand_sets, + .select_chip = anubis_nand_select, +}; + + +/* Standard Anubis devices */ + +static struct platform_device *anubis_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_adc, + &s3c_device_i2c, + &s3c_device_rtc, + &s3c_device_nand, +}; + +static struct clk *anubis_clocks[] = { + &s3c24xx_dclk0, + &s3c24xx_dclk1, + &s3c24xx_clkout0, + &s3c24xx_clkout1, + &s3c24xx_uclk, +}; + +static struct s3c24xx_board anubis_board __initdata = { + .devices = anubis_devices, + .devices_count = ARRAY_SIZE(anubis_devices), + .clocks = anubis_clocks, + .clocks_count = ARRAY_SIZE(anubis_clocks) +}; + +void __init anubis_map_io(void) +{ + /* initialise the clocks */ + + s3c24xx_dclk0.parent = NULL; + s3c24xx_dclk0.rate = 12*1000*1000; + + s3c24xx_dclk1.parent = NULL; + s3c24xx_dclk1.rate = 24*1000*1000; + + s3c24xx_clkout0.parent = &s3c24xx_dclk0; + s3c24xx_clkout1.parent = &s3c24xx_dclk1; + + s3c24xx_uclk.parent = &s3c24xx_clkout1; + + s3c_device_nand.dev.platform_data = &anubis_nand_info; + + s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); + s3c24xx_init_clocks(0); + s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); + s3c24xx_set_board(&anubis_board); + + /* ensure that the GPIO is setup */ + s3c2410_gpio_setpin(S3C2410_GPA0, 1); +} + +MACHINE_START(ANUBIS, "Simtec-Anubis") + /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ + .phys_ram = S3C2410_SDRAM_PA, + .phys_io = S3C2410_PA_UART, + .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C2410_SDRAM_PA + 0x100, + .map_io = anubis_map_io, + .init_irq = s3c24xx_init_irq, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index e9182242da95..1a3367da6408 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -381,7 +381,7 @@ static struct plat_serial8250_port bast_sio_data[] = { static struct platform_device bast_sio = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = &bast_sio_data, }, diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index ea4fb1a97a50..6ff1889fbd21 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -45,6 +45,9 @@ //#include <asm/debug-ll.h> #include <asm/arch/regs-serial.h> +#include <asm/arch/regs-lcd.h> + +#include <asm/arch/fb.h> #include <linux/serial_core.h> @@ -88,6 +91,48 @@ static struct s3c2410_uartcfg h1940_uartcfgs[] = { +/** + * Set lcd on or off + **/ +static struct s3c2410fb_mach_info h1940_lcdcfg __initdata = { + .fixed_syncs= 1, + .regs={ + .lcdcon1= S3C2410_LCDCON1_TFT16BPP | \ + S3C2410_LCDCON1_TFT | \ + S3C2410_LCDCON1_CLKVAL(0x0C), + + .lcdcon2= S3C2410_LCDCON2_VBPD(7) | \ + S3C2410_LCDCON2_LINEVAL(319) | \ + S3C2410_LCDCON2_VFPD(6) | \ + S3C2410_LCDCON2_VSPW(0), + + .lcdcon3= S3C2410_LCDCON3_HBPD(19) | \ + S3C2410_LCDCON3_HOZVAL(239) | \ + S3C2410_LCDCON3_HFPD(7), + + .lcdcon4= S3C2410_LCDCON4_MVAL(0) | \ + S3C2410_LCDCON4_HSPW(3), + + .lcdcon5= S3C2410_LCDCON5_FRM565 | \ + S3C2410_LCDCON5_INVVLINE | \ + S3C2410_LCDCON5_HWSWP, + }, + .lpcsel= 0x02, + .gpccon= 0xaa940659, + .gpccon_mask= 0xffffffff, + .gpcup= 0x0000ffff, + .gpcup_mask= 0xffffffff, + .gpdcon= 0xaa84aaa0, + .gpdcon_mask= 0xffffffff, + .gpdup= 0x0000faff, + .gpdup_mask= 0xffffffff, + + .width= 240, + .height= 320, + .xres= {240,240,240}, + .yres= {320,320,320}, + .bpp= {16,16,16}, +}; static struct platform_device *h1940_devices[] __initdata = { &s3c_device_usb, @@ -116,6 +161,11 @@ void __init h1940_init_irq(void) } +void __init h1940_init(void) +{ + set_s3c2410fb_info(&h1940_lcdcfg); +} + MACHINE_START(H1940, "IPAQ-H1940") /* Maintainer: Ben Dooks <ben@fluff.org> */ .phys_ram = S3C2410_SDRAM_PA, @@ -124,5 +174,6 @@ MACHINE_START(H1940, "IPAQ-H1940") .boot_params = S3C2410_SDRAM_PA + 0x100, .map_io = h1940_map_io, .init_irq = h1940_init_irq, + .init_machine = h1940_init, .timer = &s3c24xx_timer, MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 79044d9bce38..66bf5bb2b3db 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -110,34 +110,24 @@ void __init n30_init_irq(void) s3c24xx_init_irq(); } - -static int n30_usbstart_thread(void *unused) -{ - /* Turn off suspend on both USB ports, and switch the - * selectable USB port to USB device mode. */ - writel(readl(S3C2410_MISCCR) & ~0x00003008, S3C2410_MISCCR); - - /* Turn off the D+ pull up for 3 seconds so that the USB host - * at the other end will do a rescan of the USB bus. */ - s3c2410_gpio_setpin(S3C2410_GPB3, 0); - - msleep_interruptible(3*HZ); - - s3c2410_gpio_setpin(S3C2410_GPB3, 1); - - return 0; -} - +/* GPB3 is the line that controls the pull-up for the USB D+ line */ void __init n30_init(void) { s3c_device_i2c.dev.platform_data = &n30_i2ccfg; - kthread_run(n30_usbstart_thread, NULL, "n30_usbstart"); + /* Turn off suspend on both USB ports, and switch the + * selectable USB port to USB device mode. */ + + s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | + S3C2410_MISCCR_USBSUSPND0 | + S3C2410_MISCCR_USBSUSPND1, 0x0); } MACHINE_START(N30, "Acer-N30") - /* Maintainer: Christer Weinigel <christer@weinigel.se>, Ben Dooks <ben-linux@fluff.org> */ + /* Maintainer: Christer Weinigel <christer@weinigel.se>, + Ben Dooks <ben-linux@fluff.org> + */ .phys_ram = S3C2410_SDRAM_PA, .phys_io = S3C2410_PA_UART, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 924e8464c212..8f9ab2893df4 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -221,7 +221,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c index 2cb798832223..4c7ccef6c207 100644 --- a/arch/arm/mach-s3c2410/pm-simtec.c +++ b/arch/arm/mach-s3c2410/pm-simtec.c @@ -48,7 +48,7 @@ static __init int pm_simtec_init(void) /* check which machine we are running on */ - if (!machine_is_bast() && !machine_is_vr1000()) + if (!machine_is_bast() && !machine_is_vr1000() && !machine_is_anubis()) return 0; printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 13a48ee77484..fe57d966a34d 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -585,14 +585,16 @@ static int s3c2410_pm_enter(suspend_state_t state) s3c2410_pm_check_store(); - // need to make some form of time-delta - /* send the cpu to sleep... */ __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ s3c2410_cpu_suspend(regs_save); + /* restore the cpu state */ + + cpu_init(); + /* unset the return-from-sleep flag, to ensure reset */ tmp = __raw_readl(S3C2410_GSTATUS2); diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index ff2f25409e44..0b88993dfd27 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -18,6 +18,7 @@ * 28-Sep-2004 BJD Updates for new serial port bits * 04-Nov-2004 BJD Updated UART configuration process * 10-Jan-2005 BJD Removed s3c2410_clock_tick_rate + * 13-Aug-2005 DA Removed UART from initial I/O mappings */ #include <linux/kernel.h> @@ -49,10 +50,9 @@ static struct map_desc s3c2410_iodesc[] __initdata = { IODESC_ENT(USBHOST), IODESC_ENT(CLKPWR), IODESC_ENT(LCD), - IODESC_ENT(UART), IODESC_ENT(TIMER), IODESC_ENT(ADC), - IODESC_ENT(WATCHDOG) + IODESC_ENT(WATCHDOG), }; static struct resource s3c_uart0_resource[] = { diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c index b018a1f680ce..c67e0979aec3 100644 --- a/arch/arm/mach-s3c2410/s3c2440-clock.c +++ b/arch/arm/mach-s3c2410/s3c2440-clock.c @@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = { static int s3c2440_clk_add(struct sys_device *sysdev) { unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); + unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); struct clk *clk_h; struct clk *clk_p; struct clk *clk_xtal; @@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_device *sysdev) s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate); - printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", - print_mhz(s3c2440_clk_upll.rate)); + printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n", + print_mhz(s3c2440_clk_upll.rate), + (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); clk_p = clk_get(NULL, "pclk"); clk_h = clk_get(NULL, "hclk"); diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c index 7cb9912242a3..278d0044c85d 100644 --- a/arch/arm/mach-s3c2410/s3c2440-irq.c +++ b/arch/arm/mach-s3c2410/s3c2440-irq.c @@ -64,11 +64,11 @@ static void s3c_irq_demux_wdtac97(unsigned int irq, if (subsrc != 0) { if (subsrc & 1) { mydesc = irq_desc + IRQ_S3C2440_WDT; - mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs); + desc_handle_irq(IRQ_S3C2440_WDT, mydesc, regs); } if (subsrc & 2) { mydesc = irq_desc + IRQ_S3C2440_AC97; - mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs); + desc_handle_irq(IRQ_S3C2440_AC97, mydesc, regs); } } } @@ -122,11 +122,11 @@ static void s3c_irq_demux_cam(unsigned int irq, if (subsrc != 0) { if (subsrc & 1) { mydesc = irq_desc + IRQ_S3C2440_CAM_C; - mydesc->handle( IRQ_S3C2440_WDT, mydesc, regs); + desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs); } if (subsrc & 2) { mydesc = irq_desc + IRQ_S3C2440_CAM_P; - mydesc->handle(IRQ_S3C2440_AC97, mydesc, regs); + desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs); } } } diff --git a/arch/arm/mach-s3c2410/time.c b/arch/arm/mach-s3c2410/time.c index 765a3a9ae032..c0acfb2ad790 100644 --- a/arch/arm/mach-s3c2410/time.c +++ b/arch/arm/mach-s3c2410/time.c @@ -164,7 +164,7 @@ static void s3c2410_timer_setup (void) /* configure the system for whichever machine is in use */ - if (machine_is_bast() || machine_is_vr1000()) { + if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) { /* timer is at 12MHz, scaler is 1 */ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); tcnt = 12000000 / HZ; diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 4d4d303ee3a8..24687f511bf5 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -35,6 +35,7 @@ #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> #include <asm/arch/assabet.h> +#include <asm/arch/mcp.h> #include "generic.h" @@ -198,6 +199,11 @@ static struct irda_platform_data assabet_irda_data = { .set_speed = assabet_irda_set_speed, }; +static struct mcp_plat_data assabet_mcp_data = { + .mccr0 = MCCR0_ADM, + .sclk_rate = 11981000, +}; + static void __init assabet_init(void) { /* @@ -246,6 +252,7 @@ static void __init assabet_init(void) sa11x0_set_flash_data(&assabet_flash_data, assabet_flash_resources, ARRAY_SIZE(assabet_flash_resources)); sa11x0_set_irda_data(&assabet_irda_data); + sa11x0_set_mcp_data(&assabet_mcp_data); } /* diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 0aa918e24c31..9484be7dc671 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -29,6 +29,7 @@ #include <asm/mach/serial_sa1100.h> #include <asm/arch/cerf.h> +#include <asm/arch/mcp.h> #include "generic.h" static struct resource cerfuart2_resources[] = { @@ -116,10 +117,16 @@ static void __init cerf_map_io(void) GPDR |= CERF_GPIO_CF_RESET; } +static struct mcp_plat_data cerf_mcp_data = { + .mccr0 = MCCR0_ADM, + .sclk_rate = 11981000, +}; + static void __init cerf_init(void) { platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); sa11x0_set_flash_data(&cerf_flash_data, &cerf_flash_resource, 1); + sa11x0_set_mcp_data(&cerf_mcp_data); } MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube") diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 95ae217be1bc..3f1e358455e5 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -221,6 +221,11 @@ static struct platform_device sa11x0mcp_device = { .resource = sa11x0mcp_resources, }; +void sa11x0_set_mcp_data(struct mcp_plat_data *data) +{ + sa11x0mcp_device.dev.platform_data = data; +} + static struct resource sa11x0ssp_resources[] = { [0] = { .start = 0x80070000, diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index bfe41da9923e..279e3afa3c39 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h @@ -34,5 +34,8 @@ struct resource; extern void sa11x0_set_flash_data(struct flash_platform_data *flash, struct resource *res, int nr); +struct sa11x0_ssp_plat_ops; +extern void sa11x0_set_ssp_data(struct sa11x0_ssp_plat_ops *ops); + struct irda_platform_data; void sa11x0_set_irda_data(struct irda_platform_data *irda); diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 66a929cb7bc5..c131a5201b5b 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -98,8 +98,8 @@ static struct irqchip sa1100_low_gpio_chip = { .ack = sa1100_low_gpio_ack, .mask = sa1100_low_gpio_mask, .unmask = sa1100_low_gpio_unmask, - .type = sa1100_gpio_type, - .wake = sa1100_low_gpio_wake, + .set_type = sa1100_gpio_type, + .set_wake = sa1100_low_gpio_wake, }; /* @@ -126,7 +126,7 @@ sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc, mask >>= 11; do { if (mask & 1) - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); mask >>= 1; irq++; desc++; @@ -181,8 +181,8 @@ static struct irqchip sa1100_high_gpio_chip = { .ack = sa1100_high_gpio_ack, .mask = sa1100_high_gpio_mask, .unmask = sa1100_high_gpio_unmask, - .type = sa1100_gpio_type, - .wake = sa1100_high_gpio_wake, + .set_type = sa1100_gpio_type, + .set_wake = sa1100_high_gpio_wake, }; /* diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index 870b488aeda4..ed6744d480af 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c @@ -13,12 +13,23 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> +#include <asm/arch/mcp.h> #include "generic.h" #warning "include/asm/arch-sa1100/ide.h needs fixing for lart" +static struct mcp_plat_data lart_mcp_data = { + .mccr0 = MCCR0_ADM, + .sclk_rate = 11981000, +}; + +static void __init lart_init(void) +{ + sa11x0_set_mcp_data(&lart_mcp_data); +} + static struct map_desc lart_io_desc[] __initdata = { /* virtual physical length type */ { 0xe8000000, 0x00000000, 0x00400000, MT_DEVICE }, /* main flash memory */ @@ -47,5 +58,6 @@ MACHINE_START(LART, "LART") .boot_params = 0xc0000100, .map_io = lart_map_io, .init_irq = sa1100_init_irq, + .init_machine = lart_init, .timer = &sa1100_timer, MACHINE_END diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 1405383463ea..fc061641b7be 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -61,12 +61,12 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg if (irr & IRR_ETHERNET) { d = irq_desc + IRQ_NEPONSET_SMC9196; - d->handle(IRQ_NEPONSET_SMC9196, d, regs); + desc_handle_irq(IRQ_NEPONSET_SMC9196, d, regs); } if (irr & IRR_USAR) { d = irq_desc + IRQ_NEPONSET_USAR; - d->handle(IRQ_NEPONSET_USAR, d, regs); + desc_handle_irq(IRQ_NEPONSET_USAR, d, regs); } desc->chip->unmask(irq); @@ -74,7 +74,7 @@ neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *reg if (irr & IRR_SA1111) { d = irq_desc + IRQ_NEPONSET_SA1111; - d->handle(IRQ_NEPONSET_SA1111, d, regs); + desc_handle_irq(IRQ_NEPONSET_SA1111, d, regs); } } } diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index 43a00359fcdd..7482288278d9 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c @@ -18,6 +18,7 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> +#include <asm/arch/mcp.h> #include <asm/arch/shannon.h> #include "generic.h" @@ -52,9 +53,15 @@ static struct resource shannon_flash_resource = { .flags = IORESOURCE_MEM, }; +static struct mcp_plat_data shannon_mcp_data = { + .mccr0 = MCCR0_ADM, + .sclk_rate = 11981000, +}; + static void __init shannon_init(void) { sa11x0_set_flash_data(&shannon_flash_data, &shannon_flash_resource, 1); + sa11x0_set_mcp_data(&shannon_mcp_data); } static void __init shannon_map_io(void) diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 77978586b126..07f6d5fd7bb0 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -23,6 +23,7 @@ #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> +#include <asm/arch/mcp.h> #include <asm/arch/simpad.h> #include <linux/serial_core.h> @@ -123,6 +124,11 @@ static struct resource simpad_flash_resources [] = { } }; +static struct mcp_plat_data simpad_mcp_data = { + .mccr0 = MCCR0_ADM, + .sclk_rate = 11981000, +}; + static void __init simpad_map_io(void) @@ -157,6 +163,7 @@ static void __init simpad_map_io(void) sa11x0_set_flash_data(&simpad_flash_data, simpad_flash_resources, ARRAY_SIZE(simpad_flash_resources)); + sa11x0_set_mcp_data(&simpad_mcp_data); } static void simpad_power_off(void) diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 0eeb3616ffea..47e0420623fc 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -70,15 +70,11 @@ static unsigned long sa1100_gettimeoffset (void) return usec; } -/* - * We will be entered with IRQs enabled. - * - * Loop until we get ahead of the free running timer. - * This ensures an exact clock tick count and time accuracy. - * IRQs are disabled inside the loop to ensure coherence between - * lost_ticks (updated in do_timer()) and the match reg value, so we - * can use do_gettimeofday() from interrupt handlers. - */ +#ifdef CONFIG_NO_IDLE_HZ +static unsigned long initial_match; +static int match_posponed; +#endif + static irqreturn_t sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { @@ -86,6 +82,21 @@ sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) write_seqlock(&xtime_lock); +#ifdef CONFIG_NO_IDLE_HZ + if (match_posponed) { + match_posponed = 0; + OSMR0 = initial_match; + } +#endif + + /* + * Loop until we get ahead of the free running timer. + * This ensures an exact clock tick count and time accuracy. + * Since IRQs are disabled at this point, coherence between + * lost_ticks(updated in do_timer()) and the match reg value is + * ensured, hence we can use do_gettimeofday() from interrupt + * handlers. + */ do { timer_tick(regs); OSSR = OSSR_M0; /* Clear match on timer 0 */ @@ -120,6 +131,42 @@ static void __init sa1100_timer_init(void) OSCR = 0; /* initialize free-running timer, force first match */ } +#ifdef CONFIG_NO_IDLE_HZ +static int sa1100_dyn_tick_enable_disable(void) +{ + /* nothing to do */ + return 0; +} + +static void sa1100_dyn_tick_reprogram(unsigned long ticks) +{ + if (ticks > 1) { + initial_match = OSMR0; + OSMR0 = initial_match + ticks * LATCH; + match_posponed = 1; + } +} + +static irqreturn_t +sa1100_dyn_tick_handler(int irq, void *dev_id, struct pt_regs *regs) +{ + if (match_posponed) { + match_posponed = 0; + OSMR0 = initial_match; + if ((signed long)(initial_match - OSCR) <= 0) + return sa1100_timer_interrupt(irq, dev_id, regs); + } + return IRQ_NONE; +} + +static struct dyn_tick_timer sa1100_dyn_tick = { + .enable = sa1100_dyn_tick_enable_disable, + .disable = sa1100_dyn_tick_enable_disable, + .reprogram = sa1100_dyn_tick_reprogram, + .handler = sa1100_dyn_tick_handler, +}; +#endif + #ifdef CONFIG_PM unsigned long osmr[4], oier; @@ -156,4 +203,7 @@ struct sys_timer sa1100_timer = { .suspend = sa1100_timer_suspend, .resume = sa1100_timer_resume, .offset = sa1100_gettimeoffset, +#ifdef CONFIG_NO_IDLE_HZ + .dyn_tick = &sa1100_dyn_tick, +#endif }; diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index e737eae4521f..946c0d11c73b 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -41,7 +41,7 @@ static struct plat_serial8250_port serial_platform_data[] = { static struct platform_device serial_device = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev = { .platform_data = serial_platform_data, }, diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index f01c0f8a2bb3..3c8862fde51a 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -108,7 +108,7 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) irq += IRQ_SIC_START; desc = irq_desc + irq; - desc->handle(irq, desc, regs); + desc_handle_irq(irq, desc, regs); } while (status); } diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index afbbeb6f4658..db5e47dfc303 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -384,7 +384,7 @@ config CPU_DCACHE_DISABLE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE + depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 81f4a8a2d34b..4b39d867ac14 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -45,7 +45,7 @@ #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) -#define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */ +#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */ #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ #define RN_BITS(i) ((i >> 16) & 15) /* Rn */ @@ -68,6 +68,7 @@ static unsigned long ai_sys; static unsigned long ai_skipped; static unsigned long ai_half; static unsigned long ai_word; +static unsigned long ai_dword; static unsigned long ai_multi; static int ai_usermode; @@ -93,6 +94,8 @@ proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, p += sprintf(p, "Skipped:\t%lu\n", ai_skipped); p += sprintf(p, "Half:\t\t%lu\n", ai_half); p += sprintf(p, "Word:\t\t%lu\n", ai_word); + if (cpu_architecture() >= CPU_ARCH_ARMv5TE) + p += sprintf(p, "DWord:\t\t%lu\n", ai_dword); p += sprintf(p, "Multi:\t\t%lu\n", ai_multi); p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode, usermode_action[ai_usermode]); @@ -283,12 +286,6 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r { unsigned int rd = RD_BITS(instr); - if ((instr & 0x01f00ff0) == 0x01000090) - goto swp; - - if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0) - goto bad; - ai_half += 1; if (user_mode(regs)) @@ -323,10 +320,47 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r return TYPE_LDST; - swp: - printk(KERN_ERR "Alignment trap: not handling swp instruction\n"); - bad: - return TYPE_ERROR; + fault: + return TYPE_FAULT; +} + +static int +do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, + struct pt_regs *regs) +{ + unsigned int rd = RD_BITS(instr); + + ai_dword += 1; + + if (user_mode(regs)) + goto user; + + if ((instr & 0xf0) == 0xd0) { + unsigned long val; + get32_unaligned_check(val, addr); + regs->uregs[rd] = val; + get32_unaligned_check(val, addr+4); + regs->uregs[rd+1] = val; + } else { + put32_unaligned_check(regs->uregs[rd], addr); + put32_unaligned_check(regs->uregs[rd+1], addr+4); + } + + return TYPE_LDST; + + user: + if ((instr & 0xf0) == 0xd0) { + unsigned long val; + get32t_unaligned_check(val, addr); + regs->uregs[rd] = val; + get32t_unaligned_check(val, addr+4); + regs->uregs[rd+1] = val; + } else { + put32t_unaligned_check(regs->uregs[rd], addr); + put32t_unaligned_check(regs->uregs[rd+1], addr+4); + } + + return TYPE_LDST; fault: return TYPE_FAULT; @@ -617,12 +651,20 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) regs->ARM_pc += thumb_mode(regs) ? 2 : 4; switch (CODING_BITS(instr)) { - case 0x00000000: /* ldrh or strh */ - if (LDSTH_I_BIT(instr)) + case 0x00000000: /* 3.13.4 load/store instruction extensions */ + if (LDSTHD_I_BIT(instr)) offset.un = (instr & 0xf00) >> 4 | (instr & 15); else offset.un = regs->uregs[RM_BITS(instr)]; - handler = do_alignment_ldrhstrh; + + if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */ + (instr & 0x001000f0) == 0x001000f0) /* LDRSH */ + handler = do_alignment_ldrhstrh; + else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */ + (instr & 0x001000f0) == 0x000000f0) /* STRD */ + handler = do_alignment_ldrdstrd; + else + goto bad; break; case 0x04000000: /* ldr or str immediate */ diff --git a/arch/arm/mm/copypage-v3.S b/arch/arm/mm/copypage-v3.S index 4940f1908316..3c58ebbf0359 100644 --- a/arch/arm/mm/copypage-v3.S +++ b/arch/arm/mm/copypage-v3.S @@ -12,7 +12,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> .text .align 5 diff --git a/arch/arm/mm/copypage-v4wb.S b/arch/arm/mm/copypage-v4wb.S index b94c345ceb94..83117354b1cd 100644 --- a/arch/arm/mm/copypage-v4wb.S +++ b/arch/arm/mm/copypage-v4wb.S @@ -11,7 +11,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> .text .align 5 diff --git a/arch/arm/mm/copypage-v4wt.S b/arch/arm/mm/copypage-v4wt.S index 976793937a93..e1f2af28d549 100644 --- a/arch/arm/mm/copypage-v4wt.S +++ b/arch/arm/mm/copypage-v4wt.S @@ -14,7 +14,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> .text .align 5 diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 191788fb18d1..b0208c992576 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -16,6 +16,58 @@ #include <asm/tlbflush.h> #ifdef CONFIG_CPU_CACHE_VIPT + +void flush_cache_mm(struct mm_struct *mm) +{ + if (cache_is_vivt()) { + if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) + __cpuc_flush_user_all(); + return; + } + + if (cache_is_vipt_aliasing()) { + asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c5, 0\n" + " mcr p15, 0, %0, c7, c10, 4" + : + : "r" (0) + : "cc"); + } +} + +void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) +{ + if (cache_is_vivt()) { + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) + __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), + vma->vm_flags); + return; + } + + if (cache_is_vipt_aliasing()) { + asm( "mcr p15, 0, %0, c7, c14, 0\n" + " mcr p15, 0, %0, c7, c5, 0\n" + " mcr p15, 0, %0, c7, c10, 4" + : + : "r" (0) + : "cc"); + } +} + +void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) +{ + if (cache_is_vivt()) { + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + unsigned long addr = user_addr & PAGE_MASK; + __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); + } + return; + } + + if (cache_is_vipt_aliasing()) + flush_pfn_alias(pfn, user_addr); +} + #define ALIAS_FLUSH_START 0xffff4000 #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c index 3c655c54e231..d125a3dc061c 100644 --- a/arch/arm/mm/mm-armv.c +++ b/arch/arm/mm/mm-armv.c @@ -275,11 +275,9 @@ alloc_init_supersection(unsigned long virt, unsigned long phys, int prot) int i; for (i = 0; i < 16; i += 1) { - alloc_init_section(virt, phys & SUPERSECTION_MASK, - prot | PMD_SECT_SUPER); + alloc_init_section(virt, phys, prot | PMD_SECT_SUPER); virt += (PGDIR_SIZE / 2); - phys += (PGDIR_SIZE / 2); } } @@ -297,14 +295,10 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg pte_t *ptep; if (pmd_none(*pmdp)) { - unsigned long pmdval; ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); - pmdval = __pa(ptep) | prot_l1; - pmdp[0] = __pmd(pmdval); - pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); - flush_pmd_entry(pmdp); + __pmd_populate(pmdp, __pa(ptep) | prot_l1); } ptep = pte_offset_kernel(pmdp, virt); @@ -459,7 +453,7 @@ static void __init build_mem_type_table(void) for (i = 0; i < 16; i++) { unsigned long v = pgprot_val(protection_map[i]); - v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot; + v = (v & ~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot; protection_map[i] = __pgprot(v); } @@ -583,23 +577,23 @@ static void __init create_mapping(struct map_desc *md) */ void setup_mm_for_reboot(char mode) { - unsigned long pmdval; + unsigned long base_pmdval; pgd_t *pgd; - pmd_t *pmd; int i; - int cpu_arch = cpu_architecture(); if (current->mm && current->mm->pgd) pgd = current->mm->pgd; else pgd = init_mm.pgd; - for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) { - pmdval = (i << PGDIR_SHIFT) | - PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | - PMD_TYPE_SECT; - if (cpu_arch <= CPU_ARCH_ARMv5TEJ) - pmdval |= PMD_BIT4; + base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; + if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ) + base_pmdval |= PMD_BIT4; + + for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { + unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; + pmd_t *pmd; + pmd = pmd_off(pgd, i << PGDIR_SHIFT); pmd[0] = __pmd(pmdval); pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 5c0ae5260d1c..1d739d282a45 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -28,7 +28,7 @@ #include <linux/config.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index d69389c4d4ba..9b725665b5c7 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -28,7 +28,7 @@ #include <linux/config.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 747ed963e1df..37b70fa21c76 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -17,7 +17,7 @@ #include <linux/config.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 248110c9cf13..931b690d1be2 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -17,7 +17,7 @@ #include <linux/config.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 0ee214b824ff..d0f1bbb48f6c 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -13,7 +13,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> @@ -38,8 +38,8 @@ ENTRY(cpu_arm7_data_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR ldr r8, [r0] @ read arm instruction - tst r8, #1 << 20 @ L = 1 -> write? - orreq r1, r1, #1 << 8 @ yes. + tst r8, #1 << 20 @ L = 0 -> write? + orreq r1, r1, #1 << 11 @ yes. and r7, r8, #15 << 24 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine nop @@ -71,8 +71,8 @@ ENTRY(cpu_arm6_data_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR ldr r8, [r2] @ read arm instruction - tst r8, #1 << 20 @ L = 1 -> write? - orreq r1, r1, #1 << 8 @ yes. + tst r8, #1 << 20 @ L = 0 -> write? + orreq r1, r1, #1 << 11 @ yes. and r7, r8, #14 << 24 teq r7, #8 << 24 @ was it ldm/stm movne pc, lr diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 57cfa6a2f54f..c69c9de32391 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -33,7 +33,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/pgtable.h> #include <asm/procinfo.h> #include <asm/ptrace.h> diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 9137fe563599..7cfc2604a1ee 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -4,7 +4,7 @@ * VMA_VM_FLAGS * VM_EXEC */ -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/thread_info.h> /* diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 360cae905692..34f7e7d3f419 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -15,7 +15,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/procinfo.h> #include <asm/hardware.h> #include <asm/pgtable.h> diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index d447cd5f3dd9..ca14f80d5ab4 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -20,7 +20,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/procinfo.h> #include <asm/hardware.h> #include <asm/pgtable.h> diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 3429ddcf65d1..eb34823c9dbf 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -11,7 +11,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/procinfo.h> #include <asm/pgtable.h> @@ -105,7 +105,7 @@ ENTRY(cpu_v6_dcache_clean_area) ENTRY(cpu_v6_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 mcr p15, 0, r1, c13, c0, 1 @ set context ID diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S index 44b0daeaff9b..c10786ec8e0a 100644 --- a/arch/arm/mm/tlb-v3.S +++ b/arch/arm/mm/tlb-v3.S @@ -13,7 +13,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/tlbflush.h> #include "proc-macros.S" diff --git a/arch/arm/mm/tlb-v4.S b/arch/arm/mm/tlb-v4.S index db82ee468248..d6c94457c2b9 100644 --- a/arch/arm/mm/tlb-v4.S +++ b/arch/arm/mm/tlb-v4.S @@ -14,7 +14,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/tlbflush.h> #include "proc-macros.S" diff --git a/arch/arm/mm/tlb-v4wb.S b/arch/arm/mm/tlb-v4wb.S index 7908d5f1f130..cb829ca7845d 100644 --- a/arch/arm/mm/tlb-v4wb.S +++ b/arch/arm/mm/tlb-v4wb.S @@ -14,7 +14,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/tlbflush.h> #include "proc-macros.S" diff --git a/arch/arm/mm/tlb-v4wbi.S b/arch/arm/mm/tlb-v4wbi.S index efbe94bbe1a7..60cfc4a25dd5 100644 --- a/arch/arm/mm/tlb-v4wbi.S +++ b/arch/arm/mm/tlb-v4wbi.S @@ -14,7 +14,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/tlbflush.h> #include "proc-macros.S" diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 99ed26e78adf..6f76b89ef46e 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -11,7 +11,7 @@ * These assume a split I/D TLB. */ #include <linux/linkage.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/page.h> #include <asm/tlbflush.h> #include "proc-macros.S" diff --git a/arch/arm/nwfpe/entry26.S b/arch/arm/nwfpe/entry26.S index 0ed38b0913db..51940a96d6a6 100644 --- a/arch/arm/nwfpe/entry26.S +++ b/arch/arm/nwfpe/entry26.S @@ -20,7 +20,7 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <asm/constants.h> +#include <asm/asm-offsets.h> /* This is the kernel's entry point into the floating point emulator. It is called from the kernel with code similar to this: diff --git a/arch/arm/nwfpe/fpopcode.h b/arch/arm/nwfpe/fpopcode.h index 8035f4faafbf..1777e92a88e6 100644 --- a/arch/arm/nwfpe/fpopcode.h +++ b/arch/arm/nwfpe/fpopcode.h @@ -370,20 +370,20 @@ TABLE 5 #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5) #ifdef CONFIG_FPE_NWFPE_XP -static inline const floatx80 getExtendedConstant(const unsigned int nIndex) +static inline __attribute_pure__ floatx80 getExtendedConstant(const unsigned int nIndex) { extern const floatx80 floatx80Constant[]; return floatx80Constant[nIndex]; } #endif -static inline const float64 getDoubleConstant(const unsigned int nIndex) +static inline __attribute_pure__ float64 getDoubleConstant(const unsigned int nIndex) { extern const float64 float64Constant[]; return float64Constant[nIndex]; } -static inline const float32 getSingleConstant(const unsigned int nIndex) +static inline __attribute_pure__ float32 getSingleConstant(const unsigned int nIndex) { extern const float32 float32Constant[]; return float32Constant[nIndex]; diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c index 8b75a6e7cb3a..f9f049132a17 100644 --- a/arch/arm/nwfpe/softfloat.c +++ b/arch/arm/nwfpe/softfloat.c @@ -1602,9 +1602,7 @@ flag float32_le_quiet( float32 a, float32 b ) if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) ) { - if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) { - float_raise( float_flag_invalid ); - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloat32Sign( a ); @@ -1629,9 +1627,7 @@ flag float32_lt_quiet( float32 a, float32 b ) if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) ) { - if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) { - float_raise( float_flag_invalid ); - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloat32Sign( a ); @@ -2493,9 +2489,7 @@ flag float64_le_quiet( float64 a, float64 b ) if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) ) { - if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) { - float_raise( float_flag_invalid ); - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloat64Sign( a ); @@ -2520,9 +2514,7 @@ flag float64_lt_quiet( float64 a, float64 b ) if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) ) { - if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) { - float_raise( float_flag_invalid ); - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloat64Sign( a ); @@ -3256,7 +3248,7 @@ flag floatx80_eq( floatx80 a, floatx80 b ) ) { if ( floatx80_is_signaling_nan( a ) || floatx80_is_signaling_nan( b ) ) { - roundData->exception |= float_flag_invalid; + float_raise( float_flag_invalid ); } return 0; } @@ -3286,7 +3278,7 @@ flag floatx80_le( floatx80 a, floatx80 b ) || ( ( extractFloatx80Exp( b ) == 0x7FFF ) && (bits64) ( extractFloatx80Frac( b )<<1 ) ) ) { - roundData->exception |= float_flag_invalid; + float_raise( float_flag_invalid ); return 0; } aSign = extractFloatx80Sign( a ); @@ -3320,7 +3312,7 @@ flag floatx80_lt( floatx80 a, floatx80 b ) || ( ( extractFloatx80Exp( b ) == 0x7FFF ) && (bits64) ( extractFloatx80Frac( b )<<1 ) ) ) { - roundData->exception |= float_flag_invalid; + float_raise( float_flag_invalid ); return 0; } aSign = extractFloatx80Sign( a ); @@ -3353,7 +3345,7 @@ flag floatx80_eq_signaling( floatx80 a, floatx80 b ) || ( ( extractFloatx80Exp( b ) == 0x7FFF ) && (bits64) ( extractFloatx80Frac( b )<<1 ) ) ) { - roundData->exception |= float_flag_invalid; + float_raise( float_flag_invalid ); return 0; } return @@ -3382,10 +3374,7 @@ flag floatx80_le_quiet( floatx80 a, floatx80 b ) || ( ( extractFloatx80Exp( b ) == 0x7FFF ) && (bits64) ( extractFloatx80Frac( b )<<1 ) ) ) { - if ( floatx80_is_signaling_nan( a ) - || floatx80_is_signaling_nan( b ) ) { - roundData->exception |= float_flag_invalid; - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloatx80Sign( a ); @@ -3419,10 +3408,7 @@ flag floatx80_lt_quiet( floatx80 a, floatx80 b ) || ( ( extractFloatx80Exp( b ) == 0x7FFF ) && (bits64) ( extractFloatx80Frac( b )<<1 ) ) ) { - if ( floatx80_is_signaling_nan( a ) - || floatx80_is_signaling_nan( b ) ) { - roundData->exception |= float_flag_invalid; - } + /* Do nothing, even if NaN as we're quiet */ return 0; } aSign = extractFloatx80Sign( a ); diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 345365852f8c..9693e9b4ffd1 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -91,6 +91,13 @@ config OMAP_32K_TIMER_HZ Kernel internal timer frequency should be a divisor of 32768, such as 64 or 128. +config OMAP_DM_TIMER + bool "Use dual-mode timer" + default n + depends on ARCH_OMAP16XX + help + Select this option if you want to use OMAP Dual-Mode timers. + choice prompt "Low-level debug console UART" depends on ARCH_OMAP @@ -107,6 +114,15 @@ config OMAP_LL_DEBUG_UART3 endchoice +config OMAP_SERIAL_WAKE + bool "Enable wake-up events for serial ports" + depends OMAP_MUX + default y + help + Select this option if you want to have your system wake up + to data on the serial RX line. This allows you to wake the + system from serial console. + endmenu endif diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 531e11af54d4..7e144f9cad1c 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := common.o dma.o clock.o mux.o gpio.o mcbsp.o usb.o +obj-y := common.o sram.o sram-fn.o clock.o dma.o mux.o gpio.o mcbsp.o usb.o obj-m := obj-n := obj- := @@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o +obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o + diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 59d91b3262ba..52a58b2da288 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -21,6 +21,7 @@ #include <asm/arch/usb.h> #include "clock.h" +#include "sram.h" static LIST_HEAD(clocks); static DECLARE_MUTEX(clocks_sem); @@ -141,7 +142,7 @@ static struct clk arm_ck = { static struct clk armper_ck = { .name = "armper_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP730 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL, .enable_reg = ARM_IDLECT2, .enable_bit = EN_PERCK, @@ -385,7 +386,8 @@ static struct clk uart2_ck = { .name = "uart2_ck", /* Direct from ULPD, no parent */ .rate = 12000000, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT | + ALWAYS_ENABLED, .enable_reg = MOD_CONF_CTRL_0, .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ .set_rate = &set_uart_rate, @@ -443,6 +445,15 @@ static struct clk usb_hhc_ck16xx = { .enable_bit = 8 /* UHOST_EN */, }; +static struct clk usb_dc_ck = { + .name = "usb_dc_ck", + /* Direct from ULPD, no parent */ + .rate = 48000000, + .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, + .enable_reg = SOFT_REQ_REG, + .enable_bit = 4, +}; + static struct clk mclk_1510 = { .name = "mclk", /* Direct from ULPD, no parent. May be enabled by ext hardware. */ @@ -552,6 +563,7 @@ static struct clk * onchip_clks[] = { &uart3_16xx, &usb_clko, &usb_hhc_ck1510, &usb_hhc_ck16xx, + &usb_dc_ck, &mclk_1510, &mclk_16xx, &bclk_1510, &bclk_16xx, &mmc1_ck, @@ -946,14 +958,13 @@ static int select_table_rate(struct clk * clk, unsigned long rate) if (!ptr->rate) return -EINVAL; - if (!ptr->rate) - return -EINVAL; + /* + * In most cases we should not need to reprogram DPLL. + * Reprogramming the DPLL is tricky, it must be done from SRAM. + */ + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); - if (unlikely(ck_dpll1.rate == 0)) { - omap_writew(ptr->dpllctl_val, DPLL_CTL); - ck_dpll1.rate = ptr->pll_rate; - } - omap_writew(ptr->ckctl_val, ARM_CKCTL); + ck_dpll1.rate = ptr->pll_rate; propagate_rate(&ck_dpll1); return 0; } @@ -1224,9 +1235,11 @@ int __init clk_init(void) #endif /* Cache rates for clocks connected to ck_ref (not dpll1) */ propagate_rate(&ck_ref); - printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n", + printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " + "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate, arm_ck.rate); + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); #ifdef CONFIG_MACH_OMAP_PERSEUS2 /* Select slicer output as OMAP input clock */ @@ -1271,7 +1284,9 @@ static int __init omap_late_clk_reset(void) struct clk *p; __u32 regval32; - omap_writew(0, SOFT_REQ_REG); + /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ + regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4); + omap_writew(regval32, SOFT_REQ_REG); omap_writew(0, SOFT_REQ_REG2); list_for_each_entry(p, &clocks, node) { diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index ea967a8f6ce5..6cb20aea7f51 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -26,6 +26,7 @@ #include <asm/hardware/clock.h> #include <asm/io.h> #include <asm/mach-types.h> +#include <asm/setup.h> #include <asm/arch/board.h> #include <asm/arch/mux.h> @@ -35,11 +36,11 @@ #define NO_LENGTH_CHECK 0xffffffff -extern int omap_bootloader_tag_len; -extern u8 omap_bootloader_tag[]; +unsigned char omap_bootloader_tag[512]; +int omap_bootloader_tag_len; struct omap_board_config_kernel *omap_board_config; -int omap_board_config_size = 0; +int omap_board_config_size; static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) { diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c0a5c2fa42bd..da7b65145658 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -425,7 +425,7 @@ static int dma_handle_ch(int ch) dma_chan[ch + 6].saved_csr = csr >> 7; csr &= 0x7f; } - if (!csr) + if ((csr & 0x3f) == 0) return 0; if (unlikely(dma_chan[ch].dev_id == -1)) { printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n", @@ -890,11 +890,11 @@ void omap_enable_lcd_dma(void) w |= 1 << 8; omap_writew(w, OMAP1610_DMA_LCD_CTRL); + lcd_dma.active = 1; + w = omap_readw(OMAP1610_DMA_LCD_CCR); w |= 1 << 7; omap_writew(w, OMAP1610_DMA_LCD_CCR); - - lcd_dma.active = 1; } void omap_setup_lcd_dma(void) @@ -965,8 +965,8 @@ void omap_clear_dma(int lch) */ dma_addr_t omap_get_dma_src_pos(int lch) { - return (dma_addr_t) (OMAP_DMA_CSSA_L(lch) | - (OMAP_DMA_CSSA_U(lch) << 16)); + return (dma_addr_t) (omap_readw(OMAP_DMA_CSSA_L(lch)) | + (omap_readw(OMAP_DMA_CSSA_U(lch)) << 16)); } /* @@ -979,8 +979,18 @@ dma_addr_t omap_get_dma_src_pos(int lch) */ dma_addr_t omap_get_dma_dst_pos(int lch) { - return (dma_addr_t) (OMAP_DMA_CDSA_L(lch) | - (OMAP_DMA_CDSA_U(lch) << 16)); + return (dma_addr_t) (omap_readw(OMAP_DMA_CDSA_L(lch)) | + (omap_readw(OMAP_DMA_CDSA_U(lch)) << 16)); +} + +/* + * Returns current source transfer counting for the given DMA channel. + * Can be used to monitor the progress of a transfer inside a block. + * It must be called with disabled interrupts. + */ +int omap_get_dma_src_addr_counter(int lch) +{ + return (dma_addr_t) omap_readw(OMAP_DMA_CSAC(lch)); } int omap_dma_running(void) @@ -1076,6 +1086,7 @@ arch_initcall(omap_init_dma); EXPORT_SYMBOL(omap_get_dma_src_pos); EXPORT_SYMBOL(omap_get_dma_dst_pos); +EXPORT_SYMBOL(omap_get_dma_src_addr_counter); EXPORT_SYMBOL(omap_clear_dma); EXPORT_SYMBOL(omap_set_dma_priority); EXPORT_SYMBOL(omap_request_dma); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c new file mode 100644 index 000000000000..a1468d7326eb --- /dev/null +++ b/arch/arm/plat-omap/dmtimer.c @@ -0,0 +1,260 @@ +/* + * linux/arch/arm/plat-omap/dmtimer.c + * + * OMAP Dual-Mode Timers + * + * Copyright (C) 2005 Nokia Corporation + * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/init.h> +#include <asm/arch/hardware.h> +#include <asm/arch/dmtimer.h> +#include <asm/io.h> +#include <asm/arch/irqs.h> +#include <linux/spinlock.h> +#include <linux/list.h> + +#define OMAP_TIMER_COUNT 8 + +#define OMAP_TIMER_ID_REG 0x00 +#define OMAP_TIMER_OCP_CFG_REG 0x10 +#define OMAP_TIMER_SYS_STAT_REG 0x14 +#define OMAP_TIMER_STAT_REG 0x18 +#define OMAP_TIMER_INT_EN_REG 0x1c +#define OMAP_TIMER_WAKEUP_EN_REG 0x20 +#define OMAP_TIMER_CTRL_REG 0x24 +#define OMAP_TIMER_COUNTER_REG 0x28 +#define OMAP_TIMER_LOAD_REG 0x2c +#define OMAP_TIMER_TRIGGER_REG 0x30 +#define OMAP_TIMER_WRITE_PEND_REG 0x34 +#define OMAP_TIMER_MATCH_REG 0x38 +#define OMAP_TIMER_CAPTURE_REG 0x3c +#define OMAP_TIMER_IF_CTRL_REG 0x40 + + +static struct dmtimer_info_struct { + struct list_head unused_timers; + struct list_head reserved_timers; +} dm_timer_info; + +static struct omap_dm_timer dm_timers[] = { + { .base=0xfffb1400, .irq=INT_1610_GPTIMER1 }, + { .base=0xfffb1c00, .irq=INT_1610_GPTIMER2 }, + { .base=0xfffb2400, .irq=INT_1610_GPTIMER3 }, + { .base=0xfffb2c00, .irq=INT_1610_GPTIMER4 }, + { .base=0xfffb3400, .irq=INT_1610_GPTIMER5 }, + { .base=0xfffb3c00, .irq=INT_1610_GPTIMER6 }, + { .base=0xfffb4400, .irq=INT_1610_GPTIMER7 }, + { .base=0xfffb4c00, .irq=INT_1610_GPTIMER8 }, + { .base=0x0 }, +}; + + +static spinlock_t dm_timer_lock; + + +inline void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value) +{ + omap_writel(value, timer->base + reg); + while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG)) + ; +} + +u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) +{ + return omap_readl(timer->base + reg); +} + +int omap_dm_timers_active(void) +{ + struct omap_dm_timer *timer; + + for (timer = &dm_timers[0]; timer->base; ++timer) + if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & + OMAP_TIMER_CTRL_ST) + return 1; + + return 0; +} + + +void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) +{ + int n = (timer - dm_timers) << 1; + u32 l; + + l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l |= source << n; + omap_writel(l, MOD_CONF_CTRL_1); +} + + +static void omap_dm_timer_reset(struct omap_dm_timer *timer) +{ + /* Reset and set posted mode */ + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); + omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, 0x02); + + omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_ARMXOR); +} + + + +struct omap_dm_timer * omap_dm_timer_request(void) +{ + struct omap_dm_timer *timer = NULL; + unsigned long flags; + + spin_lock_irqsave(&dm_timer_lock, flags); + if (!list_empty(&dm_timer_info.unused_timers)) { + timer = (struct omap_dm_timer *) + dm_timer_info.unused_timers.next; + list_move_tail((struct list_head *)timer, + &dm_timer_info.reserved_timers); + } + spin_unlock_irqrestore(&dm_timer_lock, flags); + + return timer; +} + + +void omap_dm_timer_free(struct omap_dm_timer *timer) +{ + unsigned long flags; + + omap_dm_timer_reset(timer); + + spin_lock_irqsave(&dm_timer_lock, flags); + list_move_tail((struct list_head *)timer, &dm_timer_info.unused_timers); + spin_unlock_irqrestore(&dm_timer_lock, flags); +} + +void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, + unsigned int value) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); +} + +unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) +{ + return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); +} + +void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); +} + +void omap_dm_timer_enable_autoreload(struct omap_dm_timer *timer) +{ + u32 l; + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l |= OMAP_TIMER_CTRL_AR; + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); +} + +void omap_dm_timer_trigger(struct omap_dm_timer *timer) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 1); +} + +void omap_dm_timer_set_trigger(struct omap_dm_timer *timer, unsigned int value) +{ + u32 l; + + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l |= value & 0x3; + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); +} + +void omap_dm_timer_start(struct omap_dm_timer *timer) +{ + u32 l; + + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l |= OMAP_TIMER_CTRL_ST; + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); +} + +void omap_dm_timer_stop(struct omap_dm_timer *timer) +{ + u32 l; + + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l &= ~0x1; + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); +} + +unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) +{ + return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); +} + +void omap_dm_timer_reset_counter(struct omap_dm_timer *timer) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 0); +} + +void omap_dm_timer_set_load(struct omap_dm_timer *timer, unsigned int load) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); +} + +void omap_dm_timer_set_match(struct omap_dm_timer *timer, unsigned int match) +{ + omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); +} + +void omap_dm_timer_enable_compare(struct omap_dm_timer *timer) +{ + u32 l; + + l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); + l |= OMAP_TIMER_CTRL_CE; + omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); +} + + +static inline void __dm_timer_init(void) +{ + struct omap_dm_timer *timer; + + spin_lock_init(&dm_timer_lock); + INIT_LIST_HEAD(&dm_timer_info.unused_timers); + INIT_LIST_HEAD(&dm_timer_info.reserved_timers); + + timer = &dm_timers[0]; + while (timer->base) { + list_add_tail((struct list_head *)timer, &dm_timer_info.unused_timers); + omap_dm_timer_reset(timer); + timer++; + } +} + +static int __init omap_dm_timer_init(void) +{ + if (cpu_is_omap16xx()) + __dm_timer_init(); + return 0; +} + +arch_initcall(omap_dm_timer_init); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 1c85b4e536c2..55059a24ad41 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -3,7 +3,7 @@ * * Support functions for OMAP GPIO * - * Copyright (C) 2003 Nokia Corporation + * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä <juha.yrjola@nokia.com> * * This program is free software; you can redistribute it and/or modify @@ -17,8 +17,11 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/ptrace.h> +#include <linux/sysdev.h> +#include <linux/err.h> #include <asm/hardware.h> +#include <asm/hardware/clock.h> #include <asm/irq.h> #include <asm/arch/irqs.h> #include <asm/arch/gpio.h> @@ -29,7 +32,7 @@ /* * OMAP1510 GPIO registers */ -#define OMAP1510_GPIO_BASE 0xfffce000 +#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 #define OMAP1510_GPIO_DATA_INPUT 0x00 #define OMAP1510_GPIO_DATA_OUTPUT 0x04 #define OMAP1510_GPIO_DIR_CONTROL 0x08 @@ -43,34 +46,37 @@ /* * OMAP1610 specific GPIO registers */ -#define OMAP1610_GPIO1_BASE 0xfffbe400 -#define OMAP1610_GPIO2_BASE 0xfffbec00 -#define OMAP1610_GPIO3_BASE 0xfffbb400 -#define OMAP1610_GPIO4_BASE 0xfffbbc00 +#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 +#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 +#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 +#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 #define OMAP1610_GPIO_REVISION 0x0000 #define OMAP1610_GPIO_SYSCONFIG 0x0010 #define OMAP1610_GPIO_SYSSTATUS 0x0014 #define OMAP1610_GPIO_IRQSTATUS1 0x0018 #define OMAP1610_GPIO_IRQENABLE1 0x001c +#define OMAP1610_GPIO_WAKEUPENABLE 0x0028 #define OMAP1610_GPIO_DATAIN 0x002c #define OMAP1610_GPIO_DATAOUT 0x0030 #define OMAP1610_GPIO_DIRECTION 0x0034 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c +#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc +#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 /* * OMAP730 specific GPIO registers */ -#define OMAP730_GPIO1_BASE 0xfffbc000 -#define OMAP730_GPIO2_BASE 0xfffbc800 -#define OMAP730_GPIO3_BASE 0xfffbd000 -#define OMAP730_GPIO4_BASE 0xfffbd800 -#define OMAP730_GPIO5_BASE 0xfffbe000 -#define OMAP730_GPIO6_BASE 0xfffbe800 +#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 +#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 +#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 +#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 +#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 +#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 #define OMAP730_GPIO_DATA_INPUT 0x00 #define OMAP730_GPIO_DATA_OUTPUT 0x04 #define OMAP730_GPIO_DIR_CONTROL 0x08 @@ -78,14 +84,43 @@ #define OMAP730_GPIO_INT_MASK 0x10 #define OMAP730_GPIO_INT_STATUS 0x14 +/* + * omap24xx specific GPIO registers + */ +#define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000 +#define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000 +#define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000 +#define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000 +#define OMAP24XX_GPIO_REVISION 0x0000 +#define OMAP24XX_GPIO_SYSCONFIG 0x0010 +#define OMAP24XX_GPIO_SYSSTATUS 0x0014 +#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 +#define OMAP24XX_GPIO_IRQENABLE1 0x001c +#define OMAP24XX_GPIO_CTRL 0x0030 +#define OMAP24XX_GPIO_OE 0x0034 +#define OMAP24XX_GPIO_DATAIN 0x0038 +#define OMAP24XX_GPIO_DATAOUT 0x003c +#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 +#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 +#define OMAP24XX_GPIO_RISINGDETECT 0x0048 +#define OMAP24XX_GPIO_FALLINGDETECT 0x004c +#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 +#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 +#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 +#define OMAP24XX_GPIO_SETWKUENA 0x0084 +#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 +#define OMAP24XX_GPIO_SETDATAOUT 0x0094 + #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff) struct gpio_bank { - u32 base; + void __iomem *base; u16 irq; u16 virtual_irq_start; - u8 method; + int method; u32 reserved_map; + u32 suspend_wakeup; + u32 saved_wakeup; spinlock_t lock; }; @@ -93,8 +128,9 @@ struct gpio_bank { #define METHOD_GPIO_1510 1 #define METHOD_GPIO_1610 2 #define METHOD_GPIO_730 3 +#define METHOD_GPIO_24XX 4 -#if defined(CONFIG_ARCH_OMAP16XX) +#ifdef CONFIG_ARCH_OMAP16XX static struct gpio_bank gpio_bank_1610[5] = { { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, @@ -123,6 +159,15 @@ static struct gpio_bank gpio_bank_730[7] = { }; #endif +#ifdef CONFIG_ARCH_OMAP24XX +static struct gpio_bank gpio_bank_24xx[4] = { + { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, + { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, + { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, + { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, +}; +#endif + static struct gpio_bank *gpio_bank; static int gpio_bank_count; @@ -149,14 +194,23 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) return &gpio_bank[1 + (gpio >> 5)]; } #endif +#ifdef CONFIG_ARCH_OMAP24XX + if (cpu_is_omap24xx()) + return &gpio_bank[gpio >> 5]; +#endif } static inline int get_gpio_index(int gpio) { +#ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730()) return gpio & 0x1f; - else - return gpio & 0x0f; +#endif +#ifdef CONFIG_ARCH_OMAP24XX + if (cpu_is_omap24xx()) + return gpio & 0x1f; +#endif + return gpio & 0x0f; } static inline int gpio_valid(int gpio) @@ -180,6 +234,10 @@ static inline int gpio_valid(int gpio) if (cpu_is_omap730() && gpio < 192) return 0; #endif +#ifdef CONFIG_ARCH_OMAP24XX + if (cpu_is_omap24xx() && gpio < 128) + return 0; +#endif return -1; } @@ -195,7 +253,7 @@ static int check_gpio(int gpio) static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) { - u32 reg = bank->base; + void __iomem *reg = bank->base; u32 l; switch (bank->method) { @@ -211,6 +269,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) case METHOD_GPIO_730: reg += OMAP730_GPIO_DIR_CONTROL; break; + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_OE; + break; } l = __raw_readl(reg); if (is_input) @@ -234,7 +295,7 @@ void omap_set_gpio_direction(int gpio, int is_input) static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) { - u32 reg = bank->base; + void __iomem *reg = bank->base; u32 l = 0; switch (bank->method) { @@ -269,6 +330,13 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) else l &= ~(1 << gpio); break; + case METHOD_GPIO_24XX: + if (enable) + reg += OMAP24XX_GPIO_SETDATAOUT; + else + reg += OMAP24XX_GPIO_CLEARDATAOUT; + l = 1 << gpio; + break; default: BUG(); return; @@ -291,7 +359,7 @@ void omap_set_gpio_dataout(int gpio, int enable) int omap_get_gpio_datain(int gpio) { struct gpio_bank *bank; - u32 reg; + void __iomem *reg; if (check_gpio(gpio) < 0) return -1; @@ -310,109 +378,132 @@ int omap_get_gpio_datain(int gpio) case METHOD_GPIO_730: reg += OMAP730_GPIO_DATA_INPUT; break; + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_DATAIN; + break; default: BUG(); return -1; } - return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; + return (__raw_readl(reg) + & (1 << get_gpio_index(gpio))) != 0; } -static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge) +#define MOD_REG_BIT(reg, bit_mask, set) \ +do { \ + int l = __raw_readl(base + reg); \ + if (set) l |= bit_mask; \ + else l &= ~bit_mask; \ + __raw_writel(l, base + reg); \ +} while(0) + +static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger) { - u32 reg = bank->base; - u32 l; + u32 gpio_bit = 1 << gpio; + + MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, + trigger & IRQT_LOW); + MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, + trigger & IRQT_HIGH); + MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, + trigger & IRQT_RISING); + MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, + trigger & IRQT_FALLING); + /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level + * triggering requested. */ +} + +static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) +{ + void __iomem *reg = bank->base; + u32 l = 0; switch (bank->method) { case METHOD_MPUIO: reg += OMAP_MPUIO_GPIO_INT_EDGE; l = __raw_readl(reg); - if (edge == OMAP_GPIO_RISING_EDGE) + if (trigger == IRQT_RISING) l |= 1 << gpio; - else + else if (trigger == IRQT_FALLING) l &= ~(1 << gpio); - __raw_writel(l, reg); + else + goto bad; break; case METHOD_GPIO_1510: reg += OMAP1510_GPIO_INT_CONTROL; l = __raw_readl(reg); - if (edge == OMAP_GPIO_RISING_EDGE) + if (trigger == IRQT_RISING) l |= 1 << gpio; - else + else if (trigger == IRQT_FALLING) l &= ~(1 << gpio); - __raw_writel(l, reg); + else + goto bad; break; case METHOD_GPIO_1610: - edge &= 0x03; if (gpio & 0x08) reg += OMAP1610_GPIO_EDGE_CTRL2; else reg += OMAP1610_GPIO_EDGE_CTRL1; gpio &= 0x07; + /* We allow only edge triggering, i.e. two lowest bits */ + if (trigger & ~IRQT_BOTHEDGE) + BUG(); + /* NOTE: knows __IRQT_{FAL,RIS}EDGE match OMAP hardware */ + trigger &= 0x03; l = __raw_readl(reg); l &= ~(3 << (gpio << 1)); - l |= edge << (gpio << 1); - __raw_writel(l, reg); + l |= trigger << (gpio << 1); break; case METHOD_GPIO_730: reg += OMAP730_GPIO_INT_CONTROL; l = __raw_readl(reg); - if (edge == OMAP_GPIO_RISING_EDGE) + if (trigger == IRQT_RISING) l |= 1 << gpio; - else + else if (trigger == IRQT_FALLING) l &= ~(1 << gpio); - __raw_writel(l, reg); + else + goto bad; + break; + case METHOD_GPIO_24XX: + set_24xx_gpio_triggering(reg, gpio, trigger); break; default: BUG(); - return; + goto bad; } + __raw_writel(l, reg); + return 0; +bad: + return -EINVAL; } -void omap_set_gpio_edge_ctrl(int gpio, int edge) +static int gpio_irq_type(unsigned irq, unsigned type) { struct gpio_bank *bank; + unsigned gpio; + int retval; + + if (irq > IH_MPUIO_BASE) + gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); + else + gpio = irq - IH_GPIO_BASE; if (check_gpio(gpio) < 0) - return; + return -EINVAL; + + if (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL|IRQT_PROBE)) + return -EINVAL; + bank = get_gpio_bank(gpio); spin_lock(&bank->lock); - _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge); + retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); spin_unlock(&bank->lock); -} - - -static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio) -{ - u32 reg = bank->base, l; - - switch (bank->method) { - case METHOD_MPUIO: - l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE); - return (l & (1 << gpio)) ? - OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; - case METHOD_GPIO_1510: - l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL); - return (l & (1 << gpio)) ? - OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; - case METHOD_GPIO_1610: - if (gpio & 0x08) - reg += OMAP1610_GPIO_EDGE_CTRL2; - else - reg += OMAP1610_GPIO_EDGE_CTRL1; - return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03; - case METHOD_GPIO_730: - l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL); - return (l & (1 << gpio)) ? - OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; - default: - BUG(); - return -1; - } + return retval; } static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) { - u32 reg = bank->base; + void __iomem *reg = bank->base; switch (bank->method) { case METHOD_MPUIO: @@ -428,6 +519,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) case METHOD_GPIO_730: reg += OMAP730_GPIO_INT_STATUS; break; + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_IRQSTATUS1; + break; default: BUG(); return; @@ -442,7 +536,7 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) { - u32 reg = bank->base; + void __iomem *reg = bank->base; u32 l; switch (bank->method) { @@ -477,6 +571,13 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab else l |= gpio_mask; break; + case METHOD_GPIO_24XX: + if (enable) + reg += OMAP24XX_GPIO_SETIRQENABLE1; + else + reg += OMAP24XX_GPIO_CLEARIRQENABLE1; + l = gpio_mask; + break; default: BUG(); return; @@ -489,6 +590,50 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); } +/* + * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. + * 1510 does not seem to have a wake-up register. If JTAG is connected + * to the target, system will wake up always on GPIO events. While + * system is running all registered GPIO interrupts need to have wake-up + * enabled. When system is suspended, only selected GPIO interrupts need + * to have wake-up enabled. + */ +static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) +{ + switch (bank->method) { + case METHOD_GPIO_1610: + case METHOD_GPIO_24XX: + spin_lock(&bank->lock); + if (enable) + bank->suspend_wakeup |= (1 << gpio); + else + bank->suspend_wakeup &= ~(1 << gpio); + spin_unlock(&bank->lock); + return 0; + default: + printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", + bank->method); + return -EINVAL; + } +} + +/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ +static int gpio_wake_enable(unsigned int irq, unsigned int enable) +{ + unsigned int gpio = irq - IH_GPIO_BASE; + struct gpio_bank *bank; + int retval; + + if (check_gpio(gpio) < 0) + return -ENODEV; + bank = get_gpio_bank(gpio); + spin_lock(&bank->lock); + retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); + spin_unlock(&bank->lock); + + return retval; +} + int omap_request_gpio(int gpio) { struct gpio_bank *bank; @@ -505,15 +650,33 @@ int omap_request_gpio(int gpio) return -1; } bank->reserved_map |= (1 << get_gpio_index(gpio)); + + /* Set trigger to none. You need to enable the trigger after request_irq */ + _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); + #ifdef CONFIG_ARCH_OMAP1510 if (bank->method == METHOD_GPIO_1510) { - u32 reg; + void __iomem *reg; - /* Claim the pin for the ARM */ + /* Claim the pin for MPU */ reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); } #endif +#ifdef CONFIG_ARCH_OMAP16XX + if (bank->method == METHOD_GPIO_1610) { + /* Enable wake-up during idle for dynamic tick */ + void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + __raw_writel(1 << get_gpio_index(gpio), reg); + } +#endif +#ifdef CONFIG_ARCH_OMAP24XX + if (bank->method == METHOD_GPIO_24XX) { + /* Enable wake-up during idle for dynamic tick */ + void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA; + __raw_writel(1 << get_gpio_index(gpio), reg); + } +#endif spin_unlock(&bank->lock); return 0; @@ -533,6 +696,20 @@ void omap_free_gpio(int gpio) spin_unlock(&bank->lock); return; } +#ifdef CONFIG_ARCH_OMAP16XX + if (bank->method == METHOD_GPIO_1610) { + /* Disable wake-up during idle for dynamic tick */ + void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + __raw_writel(1 << get_gpio_index(gpio), reg); + } +#endif +#ifdef CONFIG_ARCH_OMAP24XX + if (bank->method == METHOD_GPIO_24XX) { + /* Disable wake-up during idle for dynamic tick */ + void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; + __raw_writel(1 << get_gpio_index(gpio), reg); + } +#endif bank->reserved_map &= ~(1 << get_gpio_index(gpio)); _set_gpio_direction(bank, get_gpio_index(gpio), 1); _set_gpio_irqenable(bank, gpio, 0); @@ -552,7 +729,7 @@ void omap_free_gpio(int gpio) static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) { - u32 isr_reg = 0; + void __iomem *isr_reg = NULL; u32 isr; unsigned int gpio_irq; struct gpio_bank *bank; @@ -574,24 +751,30 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc, if (bank->method == METHOD_GPIO_730) isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; #endif +#ifdef CONFIG_ARCH_OMAP24XX + if (bank->method == METHOD_GPIO_24XX) + isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; +#endif - isr = __raw_readl(isr_reg); - _enable_gpio_irqbank(bank, isr, 0); - _clear_gpio_irqbank(bank, isr); - _enable_gpio_irqbank(bank, isr, 1); - desc->chip->unmask(irq); - - if (unlikely(!isr)) - return; - - gpio_irq = bank->virtual_irq_start; - for (; isr != 0; isr >>= 1, gpio_irq++) { - struct irqdesc *d; - if (!(isr & 1)) - continue; - d = irq_desc + gpio_irq; - d->handle(gpio_irq, d, regs); - } + while(1) { + isr = __raw_readl(isr_reg); + _enable_gpio_irqbank(bank, isr, 0); + _clear_gpio_irqbank(bank, isr); + _enable_gpio_irqbank(bank, isr, 1); + desc->chip->unmask(irq); + + if (!isr) + break; + + gpio_irq = bank->virtual_irq_start; + for (; isr != 0; isr >>= 1, gpio_irq++) { + struct irqdesc *d; + if (!(isr & 1)) + continue; + d = irq_desc + gpio_irq; + desc_handle_irq(gpio_irq, d, regs); + } + } } static void gpio_ack_irq(unsigned int irq) @@ -613,14 +796,10 @@ static void gpio_mask_irq(unsigned int irq) static void gpio_unmask_irq(unsigned int irq) { unsigned int gpio = irq - IH_GPIO_BASE; + unsigned int gpio_idx = get_gpio_index(gpio); struct gpio_bank *bank = get_gpio_bank(gpio); - if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) { - printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n", - gpio); - _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE); - } - _set_gpio_irqenable(bank, gpio, 1); + _set_gpio_irqenable(bank, gpio_idx, 1); } static void mpuio_ack_irq(unsigned int irq) @@ -645,9 +824,11 @@ static void mpuio_unmask_irq(unsigned int irq) } static struct irqchip gpio_irq_chip = { - .ack = gpio_ack_irq, - .mask = gpio_mask_irq, - .unmask = gpio_unmask_irq, + .ack = gpio_ack_irq, + .mask = gpio_mask_irq, + .unmask = gpio_unmask_irq, + .set_type = gpio_irq_type, + .set_wake = gpio_wake_enable, }; static struct irqchip mpuio_irq_chip = { @@ -657,6 +838,7 @@ static struct irqchip mpuio_irq_chip = { }; static int initialized = 0; +static struct clk * gpio_ck = NULL; static int __init _omap_gpio_init(void) { @@ -665,6 +847,14 @@ static int __init _omap_gpio_init(void) initialized = 1; + if (cpu_is_omap1510()) { + gpio_ck = clk_get(NULL, "arm_gpio_ck"); + if (IS_ERR(gpio_ck)) + printk("Could not get arm_gpio_ck\n"); + else + clk_use(gpio_ck); + } + #ifdef CONFIG_ARCH_OMAP1510 if (cpu_is_omap1510()) { printk(KERN_INFO "OMAP1510 GPIO hardware\n"); @@ -674,7 +864,7 @@ static int __init _omap_gpio_init(void) #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap16xx()) { - int rev; + u32 rev; gpio_bank_count = 5; gpio_bank = gpio_bank_1610; @@ -690,6 +880,17 @@ static int __init _omap_gpio_init(void) gpio_bank = gpio_bank_730; } #endif +#ifdef CONFIG_ARCH_OMAP24XX + if (cpu_is_omap24xx()) { + int rev; + + gpio_bank_count = 4; + gpio_bank = gpio_bank_24xx; + rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); + printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n", + (rev >> 4) & 0x0f, rev & 0x0f); + } +#endif for (i = 0; i < gpio_bank_count; i++) { int j, gpio_count = 16; @@ -710,6 +911,7 @@ static int __init _omap_gpio_init(void) if (bank->method == METHOD_GPIO_1610) { __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); + __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); } #endif #ifdef CONFIG_ARCH_OMAP730 @@ -720,6 +922,14 @@ static int __init _omap_gpio_init(void) gpio_count = 32; /* 730 has 32-bit GPIOs */ } #endif +#ifdef CONFIG_ARCH_OMAP24XX + if (bank->method == METHOD_GPIO_24XX) { + __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); + __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); + + gpio_count = 32; + } +#endif for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + gpio_count; j++) { if (bank->method == METHOD_MPUIO) @@ -735,12 +945,97 @@ static int __init _omap_gpio_init(void) /* Enable system clock for GPIO module. * The CAM_CLK_CTRL *is* really the right place. */ - if (cpu_is_omap1610() || cpu_is_omap1710()) + if (cpu_is_omap16xx()) omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); return 0; } +#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) +static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) +{ + int i; + + if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) + return 0; + + for (i = 0; i < gpio_bank_count; i++) { + struct gpio_bank *bank = &gpio_bank[i]; + void __iomem *wake_status; + void __iomem *wake_clear; + void __iomem *wake_set; + + switch (bank->method) { + case METHOD_GPIO_1610: + wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; + wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + break; + case METHOD_GPIO_24XX: + wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; + wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; + wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; + break; + default: + continue; + } + + spin_lock(&bank->lock); + bank->saved_wakeup = __raw_readl(wake_status); + __raw_writel(0xffffffff, wake_clear); + __raw_writel(bank->suspend_wakeup, wake_set); + spin_unlock(&bank->lock); + } + + return 0; +} + +static int omap_gpio_resume(struct sys_device *dev) +{ + int i; + + if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) + return 0; + + for (i = 0; i < gpio_bank_count; i++) { + struct gpio_bank *bank = &gpio_bank[i]; + void __iomem *wake_clear; + void __iomem *wake_set; + + switch (bank->method) { + case METHOD_GPIO_1610: + wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + break; + case METHOD_GPIO_24XX: + wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; + wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; + break; + default: + continue; + } + + spin_lock(&bank->lock); + __raw_writel(0xffffffff, wake_clear); + __raw_writel(bank->saved_wakeup, wake_set); + spin_unlock(&bank->lock); + } + + return 0; +} + +static struct sysdev_class omap_gpio_sysclass = { + set_kset_name("gpio"), + .suspend = omap_gpio_suspend, + .resume = omap_gpio_resume, +}; + +static struct sys_device omap_gpio_device = { + .id = 0, + .cls = &omap_gpio_sysclass, +}; +#endif + /* * This may get called early from board specific init */ @@ -752,11 +1047,30 @@ int omap_gpio_init(void) return 0; } +static int __init omap_gpio_sysinit(void) +{ + int ret = 0; + + if (!initialized) + ret = _omap_gpio_init(); + +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) + if (cpu_is_omap16xx() || cpu_is_omap24xx()) { + if (ret == 0) { + ret = sysdev_class_register(&omap_gpio_sysclass); + if (ret == 0) + ret = sysdev_register(&omap_gpio_device); + } + } +#endif + + return ret; +} + EXPORT_SYMBOL(omap_request_gpio); EXPORT_SYMBOL(omap_free_gpio); EXPORT_SYMBOL(omap_set_gpio_direction); EXPORT_SYMBOL(omap_set_gpio_dataout); EXPORT_SYMBOL(omap_get_gpio_datain); -EXPORT_SYMBOL(omap_set_gpio_edge_ctrl); -arch_initcall(omap_gpio_init); +arch_initcall(omap_gpio_sysinit); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 43567d5edddb..9c9b7df3faf6 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -27,6 +27,7 @@ #include <asm/arch/dma.h> #include <asm/arch/mux.h> #include <asm/arch/irqs.h> +#include <asm/arch/dsp_common.h> #include <asm/arch/mcbsp.h> #include <asm/hardware/clock.h> @@ -187,9 +188,6 @@ static int omap_mcbsp_check(unsigned int id) return -1; } -#define EN_XORPCK 1 -#define DSP_RSTCT2 0xe1008014 - static void omap_mcbsp_dsp_request(void) { if (cpu_is_omap1510() || cpu_is_omap16xx()) { @@ -198,6 +196,11 @@ static void omap_mcbsp_dsp_request(void) /* enable 12MHz clock to mcbsp 1 & 3 */ clk_use(mcbsp_dspxor_ck); + + /* + * DSP external peripheral reset + * FIXME: This should be moved to dsp code + */ __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1, DSP_RSTCT2); } diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index ea7b955b9c81..64482040f89e 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -48,6 +48,9 @@ omap_cfg_reg(const reg_cfg_t reg_cfg) pull_orig = 0, pull = 0; unsigned int mask, warn = 0; + if (cpu_is_omap7xx()) + return 0; + if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) { printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg); return -EINVAL; diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/plat-omap/ocpi.c index 2ede2ee8cae4..1fb16f9edfd5 100644 --- a/arch/arm/plat-omap/ocpi.c +++ b/arch/arm/plat-omap/ocpi.c @@ -25,6 +25,7 @@ #include <linux/config.h> #include <linux/module.h> +#include <linux/version.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/kernel.h> diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c index e6536b16c385..e15c6c1ddec9 100644 --- a/arch/arm/plat-omap/pm.c +++ b/arch/arm/plat-omap/pm.c @@ -39,24 +39,32 @@ #include <linux/sched.h> #include <linux/proc_fs.h> #include <linux/pm.h> +#include <linux/interrupt.h> #include <asm/io.h> +#include <asm/irq.h> #include <asm/mach/time.h> -#include <asm/mach-types.h> +#include <asm/mach/irq.h> -#include <asm/arch/omap16xx.h> +#include <asm/mach-types.h> +#include <asm/arch/irqs.h> +#include <asm/arch/tc.h> #include <asm/arch/pm.h> #include <asm/arch/mux.h> -#include <asm/arch/tc.h> #include <asm/arch/tps65010.h> +#include <asm/arch/dsp_common.h> #include "clock.h" +#include "sram.h" static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; +static void (*omap_sram_idle)(void) = NULL; +static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; + /* * Let's power down on idle, but only if we are really * idle, because once we start down the path of @@ -65,7 +73,6 @@ static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; */ void omap_pm_idle(void) { - int (*func_ptr)(void) = 0; unsigned int mask32 = 0; /* @@ -84,6 +91,13 @@ void omap_pm_idle(void) mask32 = omap_readl(ARM_SYSST); /* + * Prevent the ULPD from entering low power state by setting + * POWER_CTRL_REG:4 = 0 + */ + omap_writew(omap_readw(ULPD_POWER_CTRL) & + ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL); + + /* * Since an interrupt may set up a timer, we don't want to * reprogram the hardware timer with interrupts enabled. * Re-enable interrupts only after returning from idle. @@ -92,18 +106,9 @@ void omap_pm_idle(void) if ((mask32 & DSP_IDLE) == 0) { __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); - } else { - - if (cpu_is_omap1510()) { - func_ptr = (void *)(OMAP1510_SRAM_IDLE_SUSPEND); - } else if (cpu_is_omap1610() || cpu_is_omap1710()) { - func_ptr = (void *)(OMAP1610_SRAM_IDLE_SUSPEND); - } else if (cpu_is_omap5912()) { - func_ptr = (void *)(OMAP5912_SRAM_IDLE_SUSPEND); - } + } else + omap_sram_idle(); - func_ptr(); - } local_fiq_enable(); local_irq_enable(); } @@ -115,58 +120,55 @@ void omap_pm_idle(void) */ static void omap_pm_wakeup_setup(void) { - /* - * Enable ARM XOR clock and release peripheral from reset by - * writing 1 to PER_EN bit in ARM_RSTCT2, this is required - * for UART configuration to use UART2 to wake up. - */ - - omap_writel(omap_readl(ARM_IDLECT2) | ENABLE_XORCLK, ARM_IDLECT2); - omap_writel(omap_readl(ARM_RSTCT2) | PER_EN, ARM_RSTCT2); - omap_writew(MODEM_32K_EN, ULPD_CLOCK_CTRL); + u32 level1_wake = OMAP_IRQ_BIT(INT_IH2_IRQ); + u32 level2_wake = OMAP_IRQ_BIT(INT_UART2) | OMAP_IRQ_BIT(INT_KEYBOARD); /* - * Turn off all interrupts except L1-2nd level cascade, - * and the L2 wakeup interrupts: keypad and UART2. + * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, + * and the L2 wakeup interrupts: keypad and UART2. Note that the + * drivers must still separately call omap_set_gpio_wakeup() to + * wake up to a GPIO interrupt. */ + if (cpu_is_omap1510() || cpu_is_omap16xx()) + level1_wake |= OMAP_IRQ_BIT(INT_GPIO_BANK1); + else if (cpu_is_omap730()) + level1_wake |= OMAP_IRQ_BIT(INT_730_GPIO_BANK1); - omap_writel(~IRQ_LEVEL2, OMAP_IH1_MIR); + omap_writel(~level1_wake, OMAP_IH1_MIR); - if (cpu_is_omap1510()) { - omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_MIR); - } + if (cpu_is_omap1510()) + omap_writel(~level2_wake, OMAP_IH2_MIR); + /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ if (cpu_is_omap16xx()) { - omap_writel(~(IRQ_UART2 | IRQ_KEYBOARD), OMAP_IH2_0_MIR); - - omap_writel(~0x0, OMAP_IH2_1_MIR); + omap_writel(~level2_wake, OMAP_IH2_0_MIR); + omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR); omap_writel(~0x0, OMAP_IH2_2_MIR); omap_writel(~0x0, OMAP_IH2_3_MIR); } - /* New IRQ agreement */ + /* New IRQ agreement, recalculate in cascade order */ + omap_writel(1, OMAP_IH2_CONTROL); omap_writel(1, OMAP_IH1_CONTROL); - - /* external PULL to down, bit 22 = 0 */ - omap_writel(omap_readl(PULL_DWN_CTRL_2) & ~(1<<22), PULL_DWN_CTRL_2); } void omap_pm_suspend(void) { - unsigned int mask32 = 0; unsigned long arg0 = 0, arg1 = 0; - int (*func_ptr)(unsigned short, unsigned short) = 0; - unsigned short save_dsp_idlect2; - printk("PM: OMAP%x is entering deep sleep now ...\n", system_rev); + printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev); + + omap_serial_wake_trigger(1); if (machine_is_omap_osk()) { /* Stop LED1 (D9) blink */ tps65010_set_led(LED1, OFF); } + omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); + /* - * Step 1: turn off interrupts + * Step 1: turn off interrupts (FIXME: NOTE: already disabled) */ local_irq_disable(); @@ -207,6 +209,8 @@ void omap_pm_suspend(void) ARM_SAVE(ARM_CKCTL); ARM_SAVE(ARM_IDLECT1); ARM_SAVE(ARM_IDLECT2); + if (!(cpu_is_omap1510())) + ARM_SAVE(ARM_IDLECT3); ARM_SAVE(ARM_EWUPCT); ARM_SAVE(ARM_RSTCT1); ARM_SAVE(ARM_RSTCT2); @@ -214,42 +218,12 @@ void omap_pm_suspend(void) ULPD_SAVE(ULPD_CLOCK_CTRL); ULPD_SAVE(ULPD_STATUS_REQ); - /* - * Step 3: LOW_PWR signal enabling - * - * Allow the LOW_PWR signal to be visible on MPUIO5 ball. - */ - if (cpu_is_omap1510()) { - /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */ - omap_writew(omap_readw(ULPD_POWER_CTRL) | - OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL); - } else if (cpu_is_omap16xx()) { - /* POWER_CTRL_REG = 0x1 (LOW_POWER is available) */ - omap_writew(omap_readw(ULPD_POWER_CTRL) | - OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL); - } - - /* configure LOW_PWR pin */ - omap_cfg_reg(T20_1610_LOW_PWR); + /* (Step 3 removed - we now allow deep sleep by default) */ /* * Step 4: OMAP DSP Shutdown */ - /* Set DSP_RST = 1 and DSP_EN = 0, put DSP block into reset */ - omap_writel((omap_readl(ARM_RSTCT1) | DSP_RST) & ~DSP_ENABLE, - ARM_RSTCT1); - - /* Set DSP boot mode to DSP-IDLE, DSP_BOOT_MODE = 0x2 */ - omap_writel(DSP_IDLE_MODE, MPUI_DSP_BOOT_CONFIG); - - /* Set EN_DSPCK = 0, stop DSP block clock */ - omap_writel(omap_readl(ARM_CKCTL) & ~DSP_CLOCK_ENABLE, ARM_CKCTL); - - /* Stop any DSP domain clocks */ - omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2); - save_dsp_idlect2 = __raw_readw(DSP_IDLECT2); - __raw_writew(0, DSP_IDLECT2); /* * Step 5: Wakeup Event Setup @@ -258,24 +232,9 @@ void omap_pm_suspend(void) omap_pm_wakeup_setup(); /* - * Step 6a: ARM and Traffic controller shutdown - * - * Step 6 starts here with clock and watchdog disable + * Step 6: ARM and Traffic controller shutdown */ - /* stop clocks */ - mask32 = omap_readl(ARM_IDLECT2); - mask32 &= ~(1<<EN_WDTCK); /* bit 0 -> 0 (WDT clock) */ - mask32 |= (1<<EN_XORPCK); /* bit 1 -> 1 (XORPCK clock) */ - mask32 &= ~(1<<EN_PERCK); /* bit 2 -> 0 (MPUPER_CK clock) */ - mask32 &= ~(1<<EN_LCDCK); /* bit 3 -> 0 (LCDC clock) */ - mask32 &= ~(1<<EN_LBCK); /* bit 4 -> 0 (local bus clock) */ - mask32 |= (1<<EN_APICK); /* bit 6 -> 1 (MPUI clock) */ - mask32 &= ~(1<<EN_TIMCK); /* bit 7 -> 0 (MPU timer clock) */ - mask32 &= ~(1<<DMACK_REQ); /* bit 8 -> 0 (DMAC clock) */ - mask32 &= ~(1<<EN_GPIOCK); /* bit 9 -> 0 (GPIO clock) */ - omap_writel(mask32, ARM_IDLECT2); - /* disable ARM watchdog */ omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); @@ -295,47 +254,24 @@ void omap_pm_suspend(void) arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; - if (cpu_is_omap1510()) { - func_ptr = (void *)(OMAP1510_SRAM_API_SUSPEND); - } else if (cpu_is_omap1610() || cpu_is_omap1710()) { - func_ptr = (void *)(OMAP1610_SRAM_API_SUSPEND); - } else if (cpu_is_omap5912()) { - func_ptr = (void *)(OMAP5912_SRAM_API_SUSPEND); - } - /* * Step 6c: ARM and Traffic controller shutdown * * Jump to assembly code. The processor will stay there * until wake up. */ - - func_ptr(arg0, arg1); + omap_sram_suspend(arg0, arg1); /* * If we are here, processor is woken up! */ - if (cpu_is_omap1510()) { - /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */ - omap_writew(omap_readw(ULPD_POWER_CTRL) & - ~OMAP1510_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL); - } else if (cpu_is_omap16xx()) { - /* POWER_CTRL_REG = 0x0 (LOW_POWER is disabled) */ - omap_writew(omap_readw(ULPD_POWER_CTRL) & - ~OMAP1610_ULPD_LOW_POWER_REQ, ULPD_POWER_CTRL); - } - - - /* Restore DSP clocks */ - omap_writel(omap_readl(ARM_IDLECT2) | (1<<EN_APICK), ARM_IDLECT2); - __raw_writew(save_dsp_idlect2, DSP_IDLECT2); - ARM_RESTORE(ARM_IDLECT2); - /* * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did */ + if (!(cpu_is_omap1510())) + ARM_RESTORE(ARM_IDLECT3); ARM_RESTORE(ARM_CKCTL); ARM_RESTORE(ARM_EWUPCT); ARM_RESTORE(ARM_RSTCT1); @@ -366,6 +302,8 @@ void omap_pm_suspend(void) MPUI1610_RESTORE(OMAP_IH2_3_MIR); } + omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); + /* * Reenable interrupts */ @@ -373,6 +311,8 @@ void omap_pm_suspend(void) local_irq_enable(); local_fiq_enable(); + omap_serial_wake_trigger(0); + printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev); if (machine_is_omap_osk()) { @@ -401,6 +341,8 @@ static int omap_pm_read_proc( ARM_SAVE(ARM_CKCTL); ARM_SAVE(ARM_IDLECT1); ARM_SAVE(ARM_IDLECT2); + if (!(cpu_is_omap1510())) + ARM_SAVE(ARM_IDLECT3); ARM_SAVE(ARM_EWUPCT); ARM_SAVE(ARM_RSTCT1); ARM_SAVE(ARM_RSTCT2); @@ -436,6 +378,7 @@ static int omap_pm_read_proc( "ARM_CKCTL_REG: 0x%-8x \n" "ARM_IDLECT1_REG: 0x%-8x \n" "ARM_IDLECT2_REG: 0x%-8x \n" + "ARM_IDLECT3_REG: 0x%-8x \n" "ARM_EWUPCT_REG: 0x%-8x \n" "ARM_RSTCT1_REG: 0x%-8x \n" "ARM_RSTCT2_REG: 0x%-8x \n" @@ -449,6 +392,7 @@ static int omap_pm_read_proc( ARM_SHOW(ARM_CKCTL), ARM_SHOW(ARM_IDLECT1), ARM_SHOW(ARM_IDLECT2), + ARM_SHOW(ARM_IDLECT3), ARM_SHOW(ARM_EWUPCT), ARM_SHOW(ARM_RSTCT1), ARM_SHOW(ARM_RSTCT2), @@ -507,7 +451,7 @@ static void omap_pm_init_proc(void) entry = create_proc_read_entry("driver/omap_pm", S_IWUSR | S_IRUGO, NULL, - omap_pm_read_proc, 0); + omap_pm_read_proc, NULL); } #endif /* DEBUG && CONFIG_PROC_FS */ @@ -580,7 +524,21 @@ static int omap_pm_finish(suspend_state_t state) } -struct pm_ops omap_pm_ops ={ +static irqreturn_t omap_wakeup_interrupt(int irq, void * dev, + struct pt_regs * regs) +{ + return IRQ_HANDLED; +} + +static struct irqaction omap_wakeup_irq = { + .name = "peripheral wakeup", + .flags = SA_INTERRUPT, + .handler = omap_wakeup_interrupt +}; + + + +static struct pm_ops omap_pm_ops ={ .pm_disk_mode = 0, .prepare = omap_pm_prepare, .enter = omap_pm_enter, @@ -590,42 +548,61 @@ struct pm_ops omap_pm_ops ={ static int __init omap_pm_init(void) { printk("Power Management for TI OMAP.\n"); - pm_idle = omap_pm_idle; /* * We copy the assembler sleep/wakeup routines to SRAM. * These routines need to be in SRAM as that's the only * memory the MPU can see when it wakes up. */ - -#ifdef CONFIG_ARCH_OMAP1510 if (cpu_is_omap1510()) { - memcpy((void *)OMAP1510_SRAM_IDLE_SUSPEND, - omap1510_idle_loop_suspend, - omap1510_idle_loop_suspend_sz); - memcpy((void *)OMAP1510_SRAM_API_SUSPEND, omap1510_cpu_suspend, - omap1510_cpu_suspend_sz); - } else -#endif - if (cpu_is_omap1610() || cpu_is_omap1710()) { - memcpy((void *)OMAP1610_SRAM_IDLE_SUSPEND, - omap1610_idle_loop_suspend, - omap1610_idle_loop_suspend_sz); - memcpy((void *)OMAP1610_SRAM_API_SUSPEND, omap1610_cpu_suspend, - omap1610_cpu_suspend_sz); - } else if (cpu_is_omap5912()) { - memcpy((void *)OMAP5912_SRAM_IDLE_SUSPEND, - omap1610_idle_loop_suspend, - omap1610_idle_loop_suspend_sz); - memcpy((void *)OMAP5912_SRAM_API_SUSPEND, omap1610_cpu_suspend, - omap1610_cpu_suspend_sz); + omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend, + omap1510_idle_loop_suspend_sz); + omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, + omap1510_cpu_suspend_sz); + } else if (cpu_is_omap16xx()) { + omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend, + omap1610_idle_loop_suspend_sz); + omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, + omap1610_cpu_suspend_sz); } + if (omap_sram_idle == NULL || omap_sram_suspend == NULL) { + printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); + return -ENODEV; + } + + pm_idle = omap_pm_idle; + + setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); +#if 0 + /* --- BEGIN BOARD-DEPENDENT CODE --- */ + /* Sleepx mask direction */ + omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008); + /* Unmask sleepx signal */ + omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004); + /* --- END BOARD-DEPENDENT CODE --- */ +#endif + + /* Program new power ramp-up time + * (0 for most boards since we don't lower voltage when in deep sleep) + */ + omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); + + /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ + omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); + + /* Configure IDLECT3 */ + if (cpu_is_omap16xx()) + omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); + pm_set_ops(&omap_pm_ops); #if defined(DEBUG) && defined(CONFIG_PROC_FS) omap_pm_init_proc(); #endif + /* configure LOW_PWR pin */ + omap_cfg_reg(T20_1610_LOW_PWR); + return 0; } __initcall(omap_pm_init); diff --git a/arch/arm/plat-omap/sleep.S b/arch/arm/plat-omap/sleep.S index 279490ce772b..9f745836f6aa 100644 --- a/arch/arm/plat-omap/sleep.S +++ b/arch/arm/plat-omap/sleep.S @@ -66,7 +66,7 @@ ENTRY(omap1510_idle_loop_suspend) @ get ARM_IDLECT2 into r2 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff - orr r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00 + orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] @ request ARM idle @@ -76,7 +76,7 @@ ENTRY(omap1510_idle_loop_suspend) strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] mov r5, #IDLE_WAIT_CYCLES & 0xff - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 + orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 l_1510: subs r5, r5, #1 bne l_1510 /* @@ -96,7 +96,7 @@ l_1510: subs r5, r5, #1 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - ldmfd sp!, {r0 - r12, pc} @ restore regs and return + ldmfd sp!, {r0 - r12, pc} @ restore regs and return ENTRY(omap1510_idle_loop_suspend_sz) .word . - omap1510_idle_loop_suspend @@ -115,8 +115,8 @@ ENTRY(omap1610_idle_loop_suspend) @ turn off clock domains @ get ARM_IDLECT2 into r2 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - mov r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff - orr r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00 + mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff + orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] @ request ARM idle @@ -126,7 +126,7 @@ ENTRY(omap1610_idle_loop_suspend) strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] mov r5, #IDLE_WAIT_CYCLES & 0xff - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 + orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 l_1610: subs r5, r5, #1 bne l_1610 /* @@ -146,7 +146,7 @@ l_1610: subs r5, r5, #1 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - ldmfd sp!, {r0 - r12, pc} @ restore regs and return + ldmfd sp!, {r0 - r12, pc} @ restore regs and return ENTRY(omap1610_idle_loop_suspend_sz) .word . - omap1610_idle_loop_suspend @@ -208,7 +208,7 @@ ENTRY(omap1510_cpu_suspend) @ turn off clock domains mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff - orr r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00 + orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] @ request ARM idle @@ -217,7 +217,7 @@ ENTRY(omap1510_cpu_suspend) strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] mov r5, #IDLE_WAIT_CYCLES & 0xff - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 + orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 l_1510_2: subs r5, r5, #1 bne l_1510_2 @@ -237,7 +237,7 @@ l_1510_2: strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] @ restore regs and return - ldmfd sp!, {r0 - r12, pc} + ldmfd sp!, {r0 - r12, pc} ENTRY(omap1510_cpu_suspend_sz) .word . - omap1510_cpu_suspend @@ -249,21 +249,26 @@ ENTRY(omap1610_cpu_suspend) @ save registers on stack stmfd sp!, {r0 - r12, lr} + @ Drain write cache + mov r4, #0 + mcr p15, 0, r0, c7, c10, 4 + nop + @ load base address of Traffic Controller - mov r4, #TCMIF_ASM_BASE & 0xff000000 - orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000 - orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00 + mov r6, #TCMIF_ASM_BASE & 0xff000000 + orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000 + orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00 @ prepare to put SDRAM into self-refresh manually - ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - orr r5, r5, #SELF_REFRESH_MODE & 0xff000000 - orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff - str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] + ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] + orr r9, r7, #SELF_REFRESH_MODE & 0xff000000 + orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff + str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] @ prepare to put EMIFS to Sleep - ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff - str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff] + ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] + orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff + str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] @ load base address of ARM_IDLECT1 and ARM_IDLECT2 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 @@ -271,26 +276,22 @@ ENTRY(omap1610_cpu_suspend) orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 @ turn off clock domains - mov r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff - orr r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - - @ work around errata of OMAP1610/5912. Enable (!) peripheral - @ clock to let the chip go into deep sleep - ldrh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - orr r5,r5, #EN_PERCK_BIT & 0xff + @ do not disable PERCK (0x04) + mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff + orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] @ request ARM idle - mov r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff - orr r3, r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff00 + mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff + orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - mov r5, #IDLE_WAIT_CYCLES & 0xff - orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 -l_1610_2: - subs r5, r5, #1 - bne l_1610_2 + @ disable instruction cache + mrc p15, 0, r9, c1, c0, 0 + bic r2, r9, #0x1000 + mcr p15, 0, r2, c1, c0, 0 + nop + /* * Let's wait for the next wake up event to wake us up. r0 can't be * used here because r0 holds ARM_IDLECT1 @@ -301,13 +302,21 @@ l_1610_2: * omap1610_cpu_suspend()'s resume point. * * It will just start executing here, so we'll restore stuff from the - * stack, reset the ARM_IDLECT1 and ARM_IDLECT2. + * stack. */ + @ re-enable Icache + mcr p15, 0, r9, c1, c0, 0 + + @ reset the ARM_IDLECT1 and ARM_IDLECT2. strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] + @ Restore EMIFF controls + str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] + str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] + @ restore regs and return - ldmfd sp!, {r0 - r12, pc} + ldmfd sp!, {r0 - r12, pc} ENTRY(omap1610_cpu_suspend_sz) .word . - omap1610_cpu_suspend diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/plat-omap/sram-fn.S new file mode 100644 index 000000000000..4bea36964a00 --- /dev/null +++ b/arch/arm/plat-omap/sram-fn.S @@ -0,0 +1,58 @@ +/* + * linux/arch/arm/plat-omap/sram.S + * + * Functions that need to be run in internal SRAM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/config.h> +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> + + .text + +/* + * Reprograms ULPD and CKCTL. + */ +ENTRY(sram_reprogram_clock) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + + mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000 + orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000 + orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00 + + mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000 + orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 + orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 + + tst r0, #1 << 4 @ want lock mode? + beq newck @ nope + bic r0, r0, #1 << 4 @ else clear lock bit + strh r0, [r2] @ set dpll into bypass mode + orr r0, r0, #1 << 4 @ set lock bit again + +newck: + strh r1, [r3] @ write new ckctl value + strh r0, [r2] @ write new dpll value + + mov r4, #0x0700 @ let the clocks settle + orr r4, r4, #0x00ff +delay: sub r4, r4, #1 + cmp r4, #0 + bne delay + +lock: ldrh r4, [r2], #0 @ read back dpll value + tst r0, #1 << 4 @ want lock mode? + beq out @ nope + tst r4, #1 << 0 @ dpll rate locked? + beq lock @ try again + +out: + ldmfd sp!, {r0 - r12, pc} @ restore regs and return +ENTRY(sram_reprogram_clock_sz) + .word . - sram_reprogram_clock diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c new file mode 100644 index 000000000000..7719a4062e3a --- /dev/null +++ b/arch/arm/plat-omap/sram.c @@ -0,0 +1,116 @@ +/* + * linux/arch/arm/plat-omap/sram.c + * + * OMAP SRAM detection and management + * + * Copyright (C) 2005 Nokia Corporation + * Written by Tony Lindgren <tony@atomide.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/config.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/mach/map.h> +#include <asm/io.h> +#include <asm/cacheflush.h> + +#include "sram.h" + +#define OMAP1_SRAM_BASE 0xd0000000 +#define OMAP1_SRAM_START 0x20000000 +#define SRAM_BOOTLOADER_SZ 0x80 + +static unsigned long omap_sram_base; +static unsigned long omap_sram_size; +static unsigned long omap_sram_ceil; + +/* + * The amount of SRAM depends on the core type: + * 730 = 200K, 1510 = 512K, 5912 = 256K, 1610 = 16K, 1710 = 16K + * Note that we cannot try to test for SRAM here because writes + * to secure SRAM will hang the system. Also the SRAM is not + * yet mapped at this point. + */ +void __init omap_detect_sram(void) +{ + omap_sram_base = OMAP1_SRAM_BASE; + + if (cpu_is_omap730()) + omap_sram_size = 0x32000; + else if (cpu_is_omap1510()) + omap_sram_size = 0x80000; + else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710()) + omap_sram_size = 0x4000; + else if (cpu_is_omap1611()) + omap_sram_size = 0x3e800; + else { + printk(KERN_ERR "Could not detect SRAM size\n"); + omap_sram_size = 0x4000; + } + + printk(KERN_INFO "SRAM size: 0x%lx\n", omap_sram_size); + omap_sram_ceil = omap_sram_base + omap_sram_size; +} + +static struct map_desc omap_sram_io_desc[] __initdata = { + { OMAP1_SRAM_BASE, OMAP1_SRAM_START, 0, MT_DEVICE } +}; + +/* + * In order to use last 2kB of SRAM on 1611b, we must round the size + * up to multiple of PAGE_SIZE. We cannot use ioremap for SRAM, as + * clock init needs SRAM early. + */ +void __init omap_map_sram(void) +{ + if (omap_sram_size == 0) + return; + + omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE; + omap_sram_io_desc[0].length *= PAGE_SIZE; + iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); + + /* + * Looks like we need to preserve some bootloader code at the + * beginning of SRAM for jumping to flash for reboot to work... + */ + memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, + omap_sram_size - SRAM_BOOTLOADER_SZ); +} + +static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl) = NULL; + +void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) +{ + if (_omap_sram_reprogram_clock == NULL) + panic("Cannot use SRAM"); + + return _omap_sram_reprogram_clock(dpllctl, ckctl); +} + +void * omap_sram_push(void * start, unsigned long size) +{ + if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { + printk(KERN_ERR "Not enough space in SRAM\n"); + return NULL; + } + omap_sram_ceil -= size; + omap_sram_ceil &= ~0x3; + memcpy((void *)omap_sram_ceil, start, size); + + return (void *)omap_sram_ceil; +} + +void __init omap_sram_init(void) +{ + omap_detect_sram(); + omap_map_sram(); + _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, + sram_reprogram_clock_sz); +} diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h new file mode 100644 index 000000000000..71984efa6ae8 --- /dev/null +++ b/arch/arm/plat-omap/sram.h @@ -0,0 +1,21 @@ +/* + * linux/arch/arm/plat-omap/sram.h + * + * Interface for functions that need to be run in internal SRAM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_OMAP_SRAM_H +#define __ARCH_ARM_OMAP_SRAM_H + +extern void * omap_sram_push(void * start, unsigned long size); +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); + +/* Do not use these */ +extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long sram_reprogram_clock_sz; + +#endif diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 25bc4a8dd763..98f1c76f8660 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -41,6 +41,7 @@ /* These routines should handle the standard chip-specific modes * for usb0/1/2 ports, covering basic mux and transceiver setup. + * Call omap_usb_init() once, from INIT_MACHINE(). * * Some board-*.c files will need to set up additional mux options, * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index e73c8deca592..6f17187ab32a 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -17,7 +17,7 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/constants.h> +#include <asm/asm-offsets.h> #include <asm/vfpmacros.h> .globl do_vfp |