diff options
Diffstat (limited to 'arch/arm')
698 files changed, 18403 insertions, 27076 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43594d5116ef..a00f4c1c7d71 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -52,6 +52,7 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 + select IRQ_FORCED_THREADING select KTIME_SCALAR select PERF_USE_VMALLOC select RTC_LIB @@ -441,7 +442,6 @@ config ARCH_NETX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU - select ARCH_SUPPORTS_MSI select CPU_XSC3 select NEED_MACH_MEMORY_H select NEED_RET_TO_USER @@ -630,6 +630,7 @@ config ARCH_MSM bool "Qualcomm MSM" select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_OF if OF select COMMON_CLK select GENERIC_CLOCKEVENTS help @@ -645,7 +646,7 @@ config ARCH_SHMOBILE select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP @@ -700,7 +701,7 @@ config ARCH_S3C24XX select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG select HAVE_CLK @@ -723,7 +724,7 @@ config ARCH_S3C64XX select ARCH_REQUIRE_GPIOLIB select ARM_VIC select CLKDEV_LOOKUP - select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG @@ -739,7 +740,6 @@ config ARCH_S3C64XX select SAMSUNG_ATAGS select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT - select SAMSUNG_IRQ_VIC_TIMER select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI help @@ -748,7 +748,7 @@ config ARCH_S3C64XX config ARCH_S5P64X0 bool "Samsung S5P6440 S5P6450" select CLKDEV_LOOKUP - select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG @@ -767,7 +767,7 @@ config ARCH_S5PC100 bool "Samsung S5PC100" select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG @@ -787,7 +787,7 @@ config ARCH_S5PV210 select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE select CLKDEV_LOOKUP - select CLKSRC_MMIO + select CLKSRC_SAMSUNG_PWM select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG @@ -1372,6 +1372,15 @@ config ARM_ERRATA_798181 which sends an IPI to the CPUs that are running the same ASID as the one being invalidated. +config ARM_ERRATA_773022 + bool "ARM errata: incorrect instructions may be executed from loop buffer" + depends on CPU_V7 + help + This option enables the workaround for the 773022 Cortex-A15 + (up to r0p4) erratum. In certain rare sequences of code, the + loop buffer may deliver incorrect instructions. This + workaround disables the loop buffer to avoid the erratum. + endmenu source "arch/arm/common/Kconfig" @@ -1584,23 +1593,13 @@ config ARM_PSCI 0022A ("Power State Coordination Interface System Software on ARM processors"). -config LOCAL_TIMERS - bool "Use local timer interrupts" - depends on SMP - default y - help - Enable support for local timers on SMP platforms, rather then the - legacy IPI broadcast method. Local timers allows the system - accounting to be spread across the timer interval, preventing a - "thundering herd" at every timer tick. - # The GPIO number here must be sorted by descending number. In case of # a multiplatform kernel, we just want the highest value required by the # selected platforms. config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA - default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 + default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX default 392 if ARCH_U8500 default 352 if ARCH_VT8500 default 288 if ARCH_SUNXI @@ -1613,13 +1612,49 @@ config ARCH_NR_GPIO source kernel/Kconfig.preempt -config HZ +config HZ_FIXED int default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ ARCH_S5PV210 || ARCH_EXYNOS4 default AT91_TIMER_HZ if ARCH_AT91 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE - default 100 + +choice + depends on !HZ_FIXED + prompt "Timer frequency" + +config HZ_100 + bool "100 Hz" + +config HZ_200 + bool "200 Hz" + +config HZ_250 + bool "250 Hz" + +config HZ_300 + bool "300 Hz" + +config HZ_500 + bool "500 Hz" + +config HZ_1000 + bool "1000 Hz" + +endchoice + +config HZ + int + default HZ_FIXED if HZ_FIXED + default 100 if HZ_100 + default 200 if HZ_200 + default 250 if HZ_250 + default 300 if HZ_300 + default 500 if HZ_500 + default 1000 + +config SCHED_HRTICK + def_bool HIGH_RES_TIMERS config SCHED_HRTICK def_bool HIGH_RES_TIMERS @@ -1756,6 +1791,9 @@ config HAVE_ARCH_TRANSPARENT_HUGEPAGE def_bool y depends on ARM_LPAE +config ARCH_WANT_GENERAL_HUGETLB + def_bool y + source "mm/Kconfig" config FORCE_MAX_ZONEORDER @@ -2064,8 +2102,7 @@ config KEXEC It is an ongoing process to be certain the hardware in a machine is properly shutdown, so do not be surprised if this code does not - initially work for you. It may help to enable device hotplugging - support. + initially work for you. config ATAGS_PROC bool "Export atags in procfs" @@ -2175,6 +2212,13 @@ config NEON Say Y to include support code for NEON, the ARMv7 Advanced SIMD Extension. +config KERNEL_MODE_NEON + bool "Support for NEON in kernel mode" + default n + depends on NEON + help + Say Y to include support for NEON in kernel mode. + endmenu menu "Userspace binary formats" @@ -2199,7 +2243,7 @@ source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE depends on !ARCH_S5PC100 - depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ + depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK def_bool y diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 583f4a00ec32..9762c84b4198 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -92,6 +92,7 @@ choice config DEBUG_BCM2835 bool "Kernel low-level debugging on BCM2835 PL011 UART" depends on ARCH_BCM2835 + select DEBUG_UART_PL01X config DEBUG_CLPS711X_UART1 bool "Kernel low-level debugging messages via UART1" @@ -110,6 +111,7 @@ choice config DEBUG_CNS3XXX bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" depends on ARCH_CNS3XXX + select DEBUG_UART_PL01X help Say Y here if you want the debug print routines to direct their output to the CNS3xxx UART0. @@ -117,6 +119,7 @@ choice config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART1 serial port on DaVinci DA8XX devices. @@ -124,6 +127,7 @@ choice config DEBUG_DAVINCI_DA8XX_UART2 bool "Kernel low-level debugging on DaVinci DA8XX using UART2" depends on ARCH_DAVINCI_DA8XX + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART2 serial port on DaVinci DA8XX devices. @@ -131,6 +135,7 @@ choice config DEBUG_DAVINCI_DMx_UART0 bool "Kernel low-level debugging on DaVinci DMx using UART0" depends on ARCH_DAVINCI_DMx + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART0 serial port on DaVinci DMx devices. @@ -138,6 +143,7 @@ choice config DEBUG_DAVINCI_TNETV107X_UART1 bool "Kernel low-level debugging on DaVinci TNETV107x using UART1" depends on ARCH_DAVINCI_TNETV107X + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART1 serial port on DaVinci TNETV107X @@ -174,9 +180,26 @@ choice Say Y here if you want the debug print routines to direct their output to the 8250 at PCI COM1. + config DEBUG_HI3620_UART + bool "Hisilicon HI3620 Debug UART" + depends on ARCH_HI3xxx + select DEBUG_UART_PL01X + help + Say Y here if you want kernel low-level debugging support + on HI3620 UART. + + config DEBUG_HI3716_UART + bool "Hisilicon Hi3716 Debug UART" + depends on ARCH_HI3xxx + select DEBUG_UART_PL01X + help + Say Y here if you want kernel low-level debugging support + on HI3716 UART. + config DEBUG_HIGHBANK_UART bool "Kernel low-level debugging messages via Highbank UART" depends on ARCH_HIGHBANK + select DEBUG_UART_PL01X help Say Y here if you want the debug print routines to direct their output to the UART on Highbank based devices. @@ -191,6 +214,7 @@ choice config DEBUG_IMX23_UART bool "i.MX23 Debug UART" depends on SOC_IMX23 + select DEBUG_UART_PL01X help Say Y here if you want kernel low-level debugging support on i.MX23. @@ -212,6 +236,7 @@ choice config DEBUG_IMX28_UART bool "i.MX28 Debug UART" depends on SOC_IMX28 + select DEBUG_UART_PL01X help Say Y here if you want kernel low-level debugging support on i.MX28. @@ -261,6 +286,7 @@ choice config DEBUG_KEYSTONE_UART0 bool "Kernel low-level debugging on KEYSTONE2 using UART0" depends on ARCH_KEYSTONE + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART0 serial port on KEYSTONE2 devices. @@ -268,6 +294,7 @@ choice config DEBUG_KEYSTONE_UART1 bool "Kernel low-level debugging on KEYSTONE2 using UART1" depends on ARCH_KEYSTONE + select DEBUG_UART_8250 help Say Y here if you want the debug print routines to direct their output to UART1 serial port on KEYSTONE2 devices. @@ -275,6 +302,7 @@ choice config DEBUG_MMP_UART2 bool "Kernel low-level debugging message via MMP UART2" depends on ARCH_MMP + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on MMP UART2. @@ -282,6 +310,7 @@ choice config DEBUG_MMP_UART3 bool "Kernel low-level debugging message via MMP UART3" depends on ARCH_MMP + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on MMP UART3. @@ -326,6 +355,7 @@ choice config DEBUG_MVEBU_UART bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)" depends on ARCH_MVEBU + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on MVEBU based platforms. @@ -344,6 +374,7 @@ choice config DEBUG_MVEBU_UART_ALTERNATE bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)" depends on ARCH_MVEBU + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on MVEBU based platforms. @@ -358,6 +389,7 @@ choice config DEBUG_NOMADIK_UART bool "Kernel low-level debugging messages via NOMADIK UART" depends on ARCH_NOMADIK + select DEBUG_UART_PL01X help Say Y here if you want kernel low-level debugging support on NOMADIK based platforms. @@ -365,6 +397,7 @@ choice config DEBUG_NSPIRE_CLASSIC_UART bool "Kernel low-level debugging via TI-NSPIRE 8250 UART" depends on ARCH_NSPIRE + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on TI-NSPIRE classic models. @@ -372,20 +405,82 @@ choice config DEBUG_NSPIRE_CX_UART bool "Kernel low-level debugging via TI-NSPIRE PL011 UART" depends on ARCH_NSPIRE + select DEBUG_UART_PL01X help Say Y here if you want kernel low-level debugging support on TI-NSPIRE CX models. - config DEBUG_OMAP2PLUS_UART - bool "Kernel low-level debugging messages via OMAP2PLUS UART" + config DEBUG_OMAP2UART1 + bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)" depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART help - Say Y here if you want kernel low-level debugging support - on OMAP2PLUS based platforms. + This covers at least h4, 2430sdp, 3430sdp, 3630sdp, + omap3 torpedo and 3530 lv som. + + config DEBUG_OMAP2UART2 + bool "Kernel low-level debugging messages via OMAP2/3/4 UART2" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_OMAP2UART3 + bool "Kernel low-level debugging messages via OMAP2 UART3 (n8x0)" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_OMAP3UART3 + bool "Kernel low-level debugging messages via OMAP3 UART3 (most omap3 boards)" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + This covers at least cm_t3x, beagle, crane, devkit8000, + igep00x0, ldp, n900, n9(50), pandora, overo, touchbook, + and 3517evm. + + config DEBUG_OMAP4UART3 + bool "Kernel low-level debugging messages via OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_OMAP3UART4 + bool "Kernel low-level debugging messages via OMAP36XX UART4" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_OMAP4UART4 + bool "Kernel low-level debugging messages via OMAP4/5 UART4" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_TI81XXUART1 + bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_TI81XXUART2 + bool "Kernel low-level debugging messages via TI81XX UART2" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_TI81XXUART3 + bool "Kernel low-level debugging messages via TI81XX UART3 (ti8168evm)" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_AM33XXUART1 + bool "Kernel low-level debugging messages via AM33XX UART1" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + + config DEBUG_ZOOM_UART + bool "Kernel low-level debugging messages via Zoom2/3 UART" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART config DEBUG_PICOXCELL_UART depends on ARCH_PICOXCELL bool "Use PicoXcell UART for low-level debug" + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on PicoXcell based platforms. @@ -393,6 +488,7 @@ choice config DEBUG_PXA_UART1 depends on ARCH_PXA bool "Use PXA UART1 for low-level debug" + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on PXA UART1. @@ -400,6 +496,7 @@ choice config DEBUG_REALVIEW_STD_PORT bool "RealView Default UART" depends on ARCH_REALVIEW + select DEBUG_UART_PL01X help Say Y here if you want the debug print routines to direct their output to the serial port on RealView EB, PB11MP, PBA8 @@ -408,14 +505,64 @@ choice config DEBUG_REALVIEW_PB1176_PORT bool "RealView PB1176 UART" depends on MACH_REALVIEW_PB1176 + select DEBUG_UART_PL01X help Say Y here if you want the debug print routines to direct their output to the standard serial port on the RealView PB1176 platform. - config DEBUG_ROCKCHIP_UART - bool "Kernel low-level debugging messages via Rockchip UART" + config DEBUG_RK29_UART0 + bool "Kernel low-level debugging messages via Rockchip RK29 UART0" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK29_UART1 + bool "Kernel low-level debugging messages via Rockchip RK29 UART1" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK29_UART2 + bool "Kernel low-level debugging messages via Rockchip RK29 UART2" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK3X_UART0 + bool "Kernel low-level debugging messages via Rockchip RK3X UART0" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK3X_UART1 + bool "Kernel low-level debugging messages via Rockchip RK3X UART1" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK3X_UART2 + bool "Kernel low-level debugging messages via Rockchip RK3X UART2" + depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + + config DEBUG_RK3X_UART3 + bool "Kernel low-level debugging messages via Rockchip RK3X UART3" depends on ARCH_ROCKCHIP + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on Rockchip based platforms. @@ -471,6 +618,7 @@ choice config DEBUG_SOCFPGA_UART depends on ARCH_SOCFPGA bool "Use SOCFPGA UART for low-level debug" + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on SOCFPGA based platforms. @@ -478,6 +626,7 @@ choice config DEBUG_SUNXI_UART0 bool "Kernel low-level debugging messages via sunXi UART0" depends on ARCH_SUNXI + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on Allwinner A1X based platforms on the UART0. @@ -485,13 +634,59 @@ choice config DEBUG_SUNXI_UART1 bool "Kernel low-level debugging messages via sunXi UART1" depends on ARCH_SUNXI + select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support on Allwinner A1X based platforms on the UART1. - config DEBUG_TEGRA_UART + config TEGRA_DEBUG_UART_AUTO_ODMDATA + bool "Kernel low-level debugging messages via Tegra UART via ODMDATA" + depends on ARCH_TEGRA + select DEBUG_TEGRA_UART + help + Automatically determines which UART to use for low-level + debug based on the ODMDATA value. This value is part of + the BCT, and is written to the boot memory device using + nvflash, or other flashing tool. When bits 19:18 are 3, + then bits 17:15 indicate which UART to use; 0/1/2/3/4 + are UART A/B/C/D/E. + + config TEGRA_DEBUG_UARTA + bool "Kernel low-level debugging messages via Tegra UART A" + depends on ARCH_TEGRA + select DEBUG_TEGRA_UART + help + Say Y here if you want kernel low-level debugging support + on Tegra based platforms. + + config TEGRA_DEBUG_UARTB + bool "Kernel low-level debugging messages via Tegra UART B" + depends on ARCH_TEGRA + select DEBUG_TEGRA_UART + help + Say Y here if you want kernel low-level debugging support + on Tegra based platforms. + + config TEGRA_DEBUG_UARTC + bool "Kernel low-level debugging messages via Tegra UART C" + depends on ARCH_TEGRA + select DEBUG_TEGRA_UART + help + Say Y here if you want kernel low-level debugging support + on Tegra based platforms. + + config TEGRA_DEBUG_UARTD + bool "Kernel low-level debugging messages via Tegra UART D" + depends on ARCH_TEGRA + select DEBUG_TEGRA_UART + help + Say Y here if you want kernel low-level debugging support + on Tegra based platforms. + + config TEGRA_DEBUG_UARTE + bool "Kernel low-level debugging messages via Tegra UART E" depends on ARCH_TEGRA - bool "Use Tegra UART for low-level debug" + select DEBUG_TEGRA_UART help Say Y here if you want kernel low-level debugging support on Tegra based platforms. @@ -510,19 +705,32 @@ choice Say Y here if you want the debug print routines to direct their output to the uart1 port on SiRFmarco devices. - config DEBUG_STI_UART + config STIH41X_DEBUG_ASC2 + bool "Use StiH415/416 ASC2 UART for low-level debug" + depends on ARCH_STI + select DEBUG_STI_UART + help + Say Y here if you want kernel low-level debugging support + on STiH415/416 based platforms like b2000, which has + default UART wired up to ASC2. + + If unsure, say N. + + config STIH41X_DEBUG_SBC_ASC1 + bool "Use StiH415/416 SBC ASC1 UART for low-level debug" depends on ARCH_STI - bool "Use StiH415/416 ASC for low-level debug" + select DEBUG_STI_UART help Say Y here if you want kernel low-level debugging support - on StiH415/416 based platforms like B2000, B2020. - It support UART2 and SBC_UART1. + on STiH415/416 based platforms like b2020. which has + default UART wired up to SBC ASC1. If unsure, say N. config DEBUG_U300_UART bool "Kernel low-level debugging messages via U300 UART0" depends on ARCH_U300 + select DEBUG_UART_PL01X help Say Y here if you want the debug print routines to direct their output to the uart port on U300 devices. @@ -548,6 +756,7 @@ choice config DEBUG_VEXPRESS_UART0_CA9 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)" depends on ARCH_VEXPRESS + select DEBUG_UART_PL01X help This option selects UART0 at 0x10009000. Except for custom models, this applies only to the V2P-CA9 tile. @@ -555,6 +764,7 @@ choice config DEBUG_VEXPRESS_UART0_RS1 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)" depends on ARCH_VEXPRESS + select DEBUG_UART_PL01X help This option selects UART0 at 0x1c090000. This applies to most of the tiles using the RS1 memory map, including all new A-class @@ -563,6 +773,7 @@ choice config DEBUG_VEXPRESS_UART0_CRX bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)" depends on ARCH_VEXPRESS && !MMU + select DEBUG_UART_PL01X help This option selects UART0 at 0xb0090000. This is appropriate for Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7 @@ -579,7 +790,7 @@ choice depends on !ARCH_MULTIPLATFORM help Say Y here if your platform doesn't provide a UART option - below. This relies on your platform choosing the right UART + above. This relies on your platform choosing the right UART definition internally in order for low-level debugging to work. @@ -610,11 +821,41 @@ choice For more details about semihosting, please see chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd. + config DEBUG_LL_UART_8250 + bool "Kernel low-level debugging via 8250 UART" + help + Say Y here if you wish the debug print routes to direct + their output to an 8250 UART. You can use this option + to provide the parameters for the 8250 UART rather than + selecting one of the platform specific options above if + you know the parameters for the port. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + + config DEBUG_LL_UART_PL01X + bool "Kernel low-level debugging via ARM Ltd PL01x Primecell UART" + help + Say Y here if you wish the debug print routes to direct + their output to a PL01x Primecell UART. You can use + this option to provide the parameters for the UART + rather than selecting one of the platform specific + options above if you know the parameters for the port. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + endchoice config DEBUG_EXYNOS_UART bool +config DEBUG_OMAP2PLUS_UART + bool + depends on ARCH_OMAP2PLUS + config DEBUG_IMX_UART_PORT int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ @@ -631,140 +872,19 @@ config DEBUG_IMX_UART_PORT Choose UART port on which kernel low-level debug messages should be output. -choice - prompt "Low-level debug console UART" - depends on DEBUG_OMAP2PLUS_UART - - config DEBUG_OMAP2UART1 - bool "OMAP2/3/4 UART1 (omap2/3 sdp boards and some omap3 boards)" - help - This covers at least h4, 2430sdp, 3430sdp, 3630sdp, - omap3 torpedo and 3530 lv som. - - config DEBUG_OMAP2UART2 - bool "OMAP2/3/4 UART2" - - config DEBUG_OMAP2UART3 - bool "OMAP2 UART3 (n8x0)" - - config DEBUG_OMAP3UART3 - bool "OMAP3 UART3 (most omap3 boards)" - help - This covers at least cm_t3x, beagle, crane, devkit8000, - igep00x0, ldp, n900, n9(50), pandora, overo, touchbook, - and 3517evm. - - config DEBUG_OMAP4UART3 - bool "OMAP4/5 UART3 (omap4 blaze, panda, omap5 sevm)" - - config DEBUG_OMAP3UART4 - bool "OMAP36XX UART4" - - config DEBUG_OMAP4UART4 - bool "OMAP4/5 UART4" - - config DEBUG_TI81XXUART1 - bool "TI81XX UART1 (ti8148evm)" - - config DEBUG_TI81XXUART2 - bool "TI81XX UART2" - - config DEBUG_TI81XXUART3 - bool "TI81XX UART3 (ti8168evm)" - - config DEBUG_AM33XXUART1 - bool "AM33XX UART1" - - config DEBUG_ZOOM_UART - bool "Zoom2/3 UART" -endchoice - -choice - prompt "Low-level debug console UART" - depends on DEBUG_ROCKCHIP_UART - - config DEBUG_RK29_UART0 - bool "RK29 UART0" - - config DEBUG_RK29_UART1 - bool "RK29 UART1" - - config DEBUG_RK29_UART2 - bool "RK29 UART2" - - config DEBUG_RK3X_UART0 - bool "RK3X UART0" - - config DEBUG_RK3X_UART1 - bool "RK3X UART1" - - config DEBUG_RK3X_UART2 - bool "RK3X UART2" - - config DEBUG_RK3X_UART3 - bool "RK3X UART3" -endchoice - -choice - prompt "Low-level debug console UART" - depends on DEBUG_LL && DEBUG_TEGRA_UART - - config TEGRA_DEBUG_UART_AUTO_ODMDATA - bool "Via ODMDATA" - help - Automatically determines which UART to use for low-level debug based - on the ODMDATA value. This value is part of the BCT, and is written - to the boot memory device using nvflash, or other flashing tool. - When bits 19:18 are 3, then bits 17:15 indicate which UART to use; - 0/1/2/3/4 are UART A/B/C/D/E. - - config TEGRA_DEBUG_UARTA - bool "UART A" - - config TEGRA_DEBUG_UARTB - bool "UART B" - - config TEGRA_DEBUG_UARTC - bool "UART C" - - config TEGRA_DEBUG_UARTD - bool "UART D" - - config TEGRA_DEBUG_UARTE - bool "UART E" - -endchoice - -choice - prompt "Low-level debug console UART" - depends on DEBUG_LL && DEBUG_STI_UART - - config STIH41X_DEBUG_ASC2 - bool "ASC2 UART" - help - Say Y here if you want kernel low-level debugging support - on STiH415/416 based platforms like b2000, which has - default UART wired up to ASC2. - - If unsure, say N. - - config STIH41X_DEBUG_SBC_ASC1 - bool "SBC ASC1 UART" - help - Say Y here if you want kernel low-level debugging support - on STiH415/416 based platforms like b2020. which has - default UART wired up to SBC ASC1. - - If unsure, say N. +config DEBUG_TEGRA_UART + bool + depends on ARCH_TEGRA -endchoice +config DEBUG_STI_UART + bool + depends on ARCH_STI config DEBUG_LL_INCLUDE string - default "debug/bcm2835.S" if DEBUG_BCM2835 - default "debug/cns3xxx.S" if DEBUG_CNS3XXX + default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X default "debug/exynos.S" if DEBUG_EXYNOS_UART - default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ @@ -775,38 +895,175 @@ config DEBUG_LL_INCLUDE DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART - default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \ - DEBUG_KEYSTONE_UART1 - default "debug/mvebu.S" if DEBUG_MVEBU_UART || \ - DEBUG_MVEBU_UART_ALTERNATE - default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART - default "debug/nomadik.S" if DEBUG_NOMADIK_UART - default "debug/nspire.S" if DEBUG_NSPIRE_CX_UART || \ - DEBUG_NSPIRE_CLASSIC_UART + default "debug/msm.S" if DEBUG_MSM_UART1 || \ + DEBUG_MSM_UART2 || \ + DEBUG_MSM_UART3 || \ + DEBUG_MSM8660_UART || \ + DEBUG_MSM8960_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART - default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART - default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ - DEBUG_MMP_UART3 - default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 - default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sti.S" if DEBUG_STI_UART - default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/tegra.S" if DEBUG_TEGRA_UART - default "debug/u300.S" if DEBUG_U300_UART default "debug/ux500.S" if DEBUG_UX500_UART - default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ - DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \ - DEBUG_VEXPRESS_UART0_CRX + default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" +# Compatibility options for PL01x +config DEBUG_UART_PL01X + def_bool ARCH_EP93XX || \ + ARCH_INTEGRATOR || \ + ARCH_SPEAR3XX || \ + ARCH_SPEAR6XX || \ + ARCH_SPEAR13XX || \ + ARCH_VERSATILE + +# Compatibility options for 8250 +config DEBUG_UART_8250 + def_bool ARCH_DOVE || ARCH_EBSA110 || \ + (FOOTBRIDGE && !DEBUG_DC21285_PORT) || \ + ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \ + ARCH_IOP33X || ARCH_IXP4XX || ARCH_KIRKWOOD || \ + ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC + +config DEBUG_UART_PHYS + hex "Physical base address of debug UART" + default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 + default 0x01c28000 if DEBUG_SUNXI_UART0 + default 0x01c28400 if DEBUG_SUNXI_UART1 + default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 + default 0x01d0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0x02530c00 if DEBUG_KEYSTONE_UART0 + default 0x02531000 if DEBUG_KEYSTONE_UART1 + default 0x03010fe0 if ARCH_RPC + default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1 + default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \ + DEBUG_VEXPRESS_UART0_CA9 + default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT + default 0x10124000 if DEBUG_RK3X_UART0 + default 0x10126000 if DEBUG_RK3X_UART1 + default 0x101f1000 if ARCH_VERSATILE + default 0x101fb000 if DEBUG_NOMADIK_UART + default 0x16000000 if ARCH_INTEGRATOR + default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0x20060000 if DEBUG_RK29_UART0 + default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 + default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 + default 0x20201000 if DEBUG_BCM2835 + default 0x40090000 if ARCH_LPC32XX + default 0x40100000 if DEBUG_PXA_UART1 + default 0x42000000 if ARCH_GEMINI + default 0x7c0003f8 if FOOTBRIDGE + default 0x80230000 if DEBUG_PICOXCELL_UART + default 0x80070000 if DEBUG_IMX23_UART + default 0x80074000 if DEBUG_IMX28_UART + default 0x808c0000 if ARCH_EP93XX + default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART + default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX + default 0xc0013000 if DEBUG_U300_UART + default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN + default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN + default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX + default 0xd0012000 if DEBUG_MVEBU_UART + default 0xd4017000 if DEBUG_MMP_UART2 + default 0xd4018000 if DEBUG_MMP_UART3 + default 0xe0000000 if ARCH_SPEAR13XX + default 0xf0000be0 if ARCH_EBSA110 + default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE + default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \ + ARCH_ORION5X + default 0xf8b00000 if DEBUG_HI3716_UART + default 0xfcb00000 if DEBUG_HI3620_UART + default 0xfe800000 if ARCH_IOP32X + default 0xffc02000 if DEBUG_SOCFPGA_UART + default 0xffd82340 if ARCH_IOP13XX + default 0xfff36000 if DEBUG_HIGHBANK_UART + default 0xfffff700 if ARCH_IOP33X + depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ + DEBUG_UART_8250 || DEBUG_UART_PL01X + +config DEBUG_UART_VIRT + hex "Virtual base address of debug UART" + default 0xe0010fe0 if ARCH_RPC + default 0xf0000be0 if ARCH_EBSA110 + default 0xf0009000 if DEBUG_CNS3XXX + default 0xf01fb000 if DEBUG_NOMADIK_UART + default 0xf0201000 if DEBUG_BCM2835 + default 0xf11f1000 if ARCH_VERSATILE + default 0xf1600000 if ARCH_INTEGRATOR + default 0xf1c28000 if DEBUG_SUNXI_UART0 + default 0xf1c28400 if DEBUG_SUNXI_UART1 + default 0xf2100000 if DEBUG_PXA_UART1 + default 0xf4090000 if ARCH_LPC32XX + default 0xf4200000 if ARCH_GEMINI + default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9 + default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0xfb009000 if DEBUG_REALVIEW_STD_PORT + default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT + default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX + default 0xfd000000 if ARCH_SPEAR13XX + default 0xfd012000 if ARCH_MV78XX0 + default 0xfde12000 if ARCH_DOVE + default 0xfe012000 if ARCH_ORION5X + default 0xfe017000 if DEBUG_MMP_UART2 + default 0xfe018000 if DEBUG_MMP_UART3 + default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART + default 0xfe230000 if DEBUG_PICOXCELL_UART + default 0xfe800000 if ARCH_IOP32X + default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART + default 0xfeb24000 if DEBUG_RK3X_UART0 + default 0xfeb26000 if DEBUG_RK3X_UART1 + default 0xfeb30c00 if DEBUG_KEYSTONE_UART0 + default 0xfeb31000 if DEBUG_KEYSTONE_UART1 + default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE + default 0xfed60000 if DEBUG_RK29_UART0 + default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 + default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 + default 0xfec02000 if DEBUG_SOCFPGA_UART + default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 + default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed12000 if ARCH_KIRKWOOD + default 0xfedc0000 if ARCH_EP93XX + default 0xfee003f8 if FOOTBRIDGE + default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1 + default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART + default 0xfef36000 if DEBUG_HIGHBANK_UART + default 0xfee82340 if ARCH_IOP13XX + default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN + default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN + default 0xfefff700 if ARCH_IOP33X + default 0xff003000 if DEBUG_U300_UART + default DEBUG_UART_PHYS if !MMU + depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ + DEBUG_UART_8250 || DEBUG_UART_PL01X + +config DEBUG_UART_8250_SHIFT + int "Register offset shift for the 8250 debug UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default 0 if FOOTBRIDGE || ARCH_IOP32X + default 2 + +config DEBUG_UART_8250_WORD + bool "Use 32-bit accesses for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + depends on DEBUG_UART_8250_SHIFT >= 2 + default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \ + ARCH_KEYSTONE || \ + DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ + DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 + +config DEBUG_UART_8250_FLOW_CONTROL + bool "Enable flow control for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_GEMINI || ARCH_RPC + config DEBUG_UNCOMPRESS bool - depends on ARCH_MULTIPLATFORM + depends on ARCH_MULTIPLATFORM || ARCH_MSM default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ - !DEBUG_TEGRA_UART + (!DEBUG_TEGRA_UART || !ZBOOT_ROM) help This option influences the normal decompressor output for multiplatform kernels. Normally, multiplatform kernels disable @@ -820,7 +1077,7 @@ config DEBUG_UNCOMPRESS config UNCOMPRESS_INCLUDE string - default "debug/uncompress.h" if ARCH_MULTIPLATFORM + default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM default "mach/uncompress.h" config EARLY_PRINTK diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6fd2ceae305a..a37a50f575a2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 machine-$(CONFIG_ARCH_SHARK) += shark machine-$(CONFIG_ARCH_SHMOBILE) += shmobile +machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STI) += sti diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index e2d636336b7c..e7f80928949c 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -55,12 +55,47 @@ __tmp_stack: __continue: #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ - /* Set board ID necessary for boot */ - ldr r7, 1f @ Set machine type register - mov r8, #0 @ pass null pointer as atag + adr r0, dtb_info + ldmia r0, {r1, r3, r4, r5, r7} + + sub r0, r0, r1 @ calculate the delta offset + add r5, r5, r0 @ _edata + + ldr lr, [r5, #0] @ check if valid DTB is present + cmp lr, r3 + bne 0f + + add r9, r7, #31 @ rounded up to a multiple + bic r9, r9, #31 @ ... of 32 bytes + + add r6, r9, r5 @ copy from _edata + add r9, r9, r4 @ to MEMORY_START + +1: ldmdb r6!, {r0 - r3, r10 - r12, lr} + cmp r6, r5 + stmdb r9!, {r0 - r3, r10 - r12, lr} + bhi 1b + + /* Success: Zero board ID, pointer to start of memory for atag/dtb */ + mov r7, #0 + mov r8, r4 b 2f -1 : .long MACH_TYPE + .align 2 +dtb_info: + .word dtb_info +#ifndef __ARMEB__ + .word 0xedfe0dd0 @ sig is 0xd00dfeed big endian +#else + .word 0xd00dfeed +#endif + .word MEMORY_START + .word _edata + .word 0x4000 @ maximum DTB size +0: + /* Failure: Zero board ID, NULL atag/dtb */ + mov r7, #0 + mov r8, #0 @ pass null pointer as atag 2 : #endif /* CONFIG_ZBOOT_ROM */ diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 07204ca96853..4e02f1b6c8a2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -42,24 +42,27 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb -dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb +dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \ + bcm28155-ap.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ + dove-d2plug.dtb \ dove-dove-db.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ exynos4412-odroidx.dtb \ - exynos4412-smdk4412.dtb \ exynos4412-origen.dtb \ + exynos4412-smdk4412.dtb \ + exynos4412-trats2.dtb \ exynos5250-arndale.dtb \ - exynos5440-sd5v1.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ exynos5420-smdk5420.dtb \ + exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb @@ -83,12 +86,14 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ + kirkwood-mv88f6281gtw-ge.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ kirkwood-ns2.dtb \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ + kirkwood-nsa310a.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ @@ -100,7 +105,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ armada-370-rd.dtb \ + armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ armada-xp-openblocks-ax3-4.dtb @@ -112,6 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx27-pdk.dtb \ imx27-phytec-phycore-som.dtb \ imx27-phytec-phycore-rdk.dtb \ + imx27-phytec-phycard-s-som.dtb \ + imx27-phytec-phycard-s-rdk.dtb \ imx31-bug.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ @@ -131,6 +140,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ + imx6q-wandboard.dtb \ imx6sl-evk.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ @@ -143,7 +153,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-cfa10037.dtb \ imx28-cfa10049.dtb \ imx28-cfa10055.dtb \ + imx28-cfa10056.dtb \ imx28-cfa10057.dtb \ + imx28-cfa10058.dtb \ imx28-evk.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ @@ -176,11 +188,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am43x-epos-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ - hrefprev60.dtb \ - hrefv60plus.dtb \ - ccu8540.dtb \ - ccu9540.dtb +dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ + ste-hrefprev60.dtb \ + ste-hrefv60plus.dtb \ + ste-ccu8540.dtb \ + ste-ccu9540.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ emev2-kzm9d-reference.dtb \ @@ -197,6 +209,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a73a4-ape6evm.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb +dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ @@ -211,11 +224,14 @@ dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \ stih415-b2020.dtb \ stih416-b2020.dtb dtb-$(CONFIG_ARCH_SUNXI) += \ + sun4i-a10-a1000.dtb \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ sun5i-a10s-olinuxino-micro.dtb \ - sun5i-a13-olinuxino.dtb + sun5i-a13-olinuxino.dtb \ + sun6i-a31-colombus.dtb \ + sun7i-a20-olinuxino-micro.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ tegra20-medcom-wide.dtb \ @@ -229,8 +245,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ - tegra114-dalmore.dtb \ - tegra114-pluto.dtb + tegra114-dalmore.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 444b4ede0d60..d318987d44a1 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -120,6 +120,35 @@ status = "okay"; }; + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + i2c0: i2c@44e0b000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 3aee1a43782d..e8ec8756e498 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -171,6 +171,35 @@ }; }; + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + i2c1: i2c@4802a000 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 0c8ad173d2b0..4f339fa91c57 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> / { model = "TI AM335x EVM-SK"; @@ -207,6 +208,22 @@ }; }; + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + }; + epwmss2: epwmss@48304000 { status = "okay"; @@ -298,7 +315,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&ecap2 0 50000 1>; + pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 58 61 66 75 90 125 170 255>; default-brightness-level = <8>; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 38b446ba1ce1..f9c5da9c7fe1 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -26,6 +26,10 @@ serial5 = &uart5; d_can0 = &dcan0; d_can1 = &dcan1; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; }; cpus { @@ -333,21 +337,132 @@ status = "disabled"; }; - usb@47400000 { - compatible = "ti,musb-am33xx"; - reg = <0x47400000 0x1000 /* usbss */ - 0x47401000 0x800 /* musb instance 0 */ - 0x47401800 0x800>; /* musb instance 1 */ - interrupts = <17 /* usbss */ - 18 /* musb instance 0 */ - 19>; /* musb instance 1 */ - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - port0-mode = <3>; - port1-mode = <3>; - power = <250>; + usb: usb@47400000 { + compatible = "ti,am33xx-usb"; + reg = <0x47400000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; ti,hwmods = "usb_otg_hs"; + status = "disabled"; + + ctrl_mod: control@44e10000 { + compatible = "ti,am335x-usb-ctrl-module"; + reg = <0x44e10620 0x10 + 0x44e10648 0x4>; + reg-names = "phy_ctrl", "wakeup"; + status = "disabled"; + }; + + usb0_phy: usb-phy@47401300 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401300 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb0: usb@47401000 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401400 0x400 + 0x47401000 0x200>; + reg-names = "mc", "control"; + + interrupts = <18>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb0_phy>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 4 0 &cppi41dma 5 0 + &cppi41dma 6 0 &cppi41dma 7 0 + &cppi41dma 8 0 &cppi41dma 9 0 + &cppi41dma 10 0 &cppi41dma 11 0 + &cppi41dma 12 0 &cppi41dma 13 0 + &cppi41dma 14 0 &cppi41dma 0 1 + &cppi41dma 1 1 &cppi41dma 2 1 + &cppi41dma 3 1 &cppi41dma 4 1 + &cppi41dma 5 1 &cppi41dma 6 1 + &cppi41dma 7 1 &cppi41dma 8 1 + &cppi41dma 9 1 &cppi41dma 10 1 + &cppi41dma 11 1 &cppi41dma 12 1 + &cppi41dma 13 1 &cppi41dma 14 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + usb1_phy: usb-phy@47401b00 { + compatible = "ti,am335x-usb-phy"; + reg = <0x47401b00 0x100>; + reg-names = "phy"; + status = "disabled"; + ti,ctrl_mod = <&ctrl_mod>; + }; + + usb1: usb@47401800 { + compatible = "ti,musb-am33xx"; + status = "disabled"; + reg = <0x47401c00 0x400 + 0x47401800 0x200>; + reg-names = "mc", "control"; + interrupts = <19>; + interrupt-names = "mc"; + dr_mode = "otg"; + mentor,multipoint = <1>; + mentor,num-eps = <16>; + mentor,ram-bits = <12>; + mentor,power = <500>; + phys = <&usb1_phy>; + + dmas = <&cppi41dma 15 0 &cppi41dma 16 0 + &cppi41dma 17 0 &cppi41dma 18 0 + &cppi41dma 19 0 &cppi41dma 20 0 + &cppi41dma 21 0 &cppi41dma 22 0 + &cppi41dma 23 0 &cppi41dma 24 0 + &cppi41dma 25 0 &cppi41dma 26 0 + &cppi41dma 27 0 &cppi41dma 28 0 + &cppi41dma 29 0 &cppi41dma 15 1 + &cppi41dma 16 1 &cppi41dma 17 1 + &cppi41dma 18 1 &cppi41dma 19 1 + &cppi41dma 20 1 &cppi41dma 21 1 + &cppi41dma 22 1 &cppi41dma 23 1 + &cppi41dma 24 1 &cppi41dma 25 1 + &cppi41dma 26 1 &cppi41dma 27 1 + &cppi41dma 28 1 &cppi41dma 29 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", + "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", + "rx14", "rx15", + "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", + "tx14", "tx15"; + }; + + cppi41dma: dma-controller@07402000 { + compatible = "ti,am3359-cppi41"; + reg = <0x47400000 0x1000 + 0x47402000 0x1000 + 0x47403000 0x1000 + 0x47404000 0x4000>; + reg-names = "glue", "controller", "scheduler", "queuemgr"; + interrupts = <17>; + interrupt-names = "glue"; + #dma-cells = <2>; + #dma-channels = <30>; + #dma-requests = <256>; + status = "disabled"; + }; }; epwmss0: epwmss@48300000 { diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index beee1699d49e..90ce29dbe119 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -14,7 +14,7 @@ */ /dts-v1/; -/include/ "armada-370.dtsi" +#include "armada-370.dtsi" / { model = "Marvell Armada 370 Evaluation Board"; @@ -30,6 +30,9 @@ }; soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; + internal-regs { serial@12000 { clock-frequency = <200000000>; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 45b107763e3b..2471d9da767b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "armada-370.dtsi" +#include "armada-370.dtsi" / { model = "Globalscale Mirabox"; @@ -25,6 +25,25 @@ }; soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + internal-regs { serial@12000 { clock-frequency = <200000000>; @@ -120,22 +139,6 @@ reg = <0x25>; }; }; - - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts new file mode 100644 index 000000000000..05e4485a8225 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -0,0 +1,179 @@ +/* + * Device Tree file for NETGEAR ReadyNAS 102 + * + * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "armada-370.dtsi" + +/ { + model = "NETGEAR ReadyNAS 102"; + compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + internal-regs { + serial@12000 { + clock-frequency = <200000000>; + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + pinctrl { + power_led_pin: power-led-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + ethernet@74000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <100000>; + status = "okay"; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + + pcie-controller { + status = "okay"; + + /* Connected to Marvell SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to FL1009 USB 3.0 controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + g762_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-0 = < &power_led_pin + &sata1_led_pin + &sata2_led_pin + &backup_led_pin >; + pinctrl-names = "default"; + + blue_power_led { + label = "rn102:blue:pwr"; + gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */ + linux,default-trigger = "heartbeat"; + }; + + green_sata1_led { + label = "rn102:green:sata1"; + gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */ + default-state = "on"; + }; + + green_sata2_led { + label = "rn102:green:sata2"; + gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */ + default-state = "on"; + }; + + green_backup_led { + label = "rn102:green:backup"; + gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "Power Button"; + linux,code = <116>; /* KEY_POWER */ + gpios = <&gpio1 30 1>; + }; + + button@2 { + label = "Reset Button"; + linux,code = <0x198>; /* KEY_RESTART */ + gpios = <&gpio0 6 1>; + }; + + button@3 { + label = "Backup Button"; + linux,code = <133>; /* KEY_COPY */ + gpios = <&gpio1 26 1>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index a3a2fedb8726..f81810a59629 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "armada-370.dtsi" +#include "armada-370.dtsi" / { model = "Marvell Armada 370 Reference Design"; @@ -28,6 +28,25 @@ }; soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Internal mini-PCIe connector */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + internal-regs { serial@12000 { clock-frequency = <200000000>; @@ -85,22 +104,6 @@ gpios = <&gpio0 6 1>; }; }; - - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Internal mini-PCIe connector */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 90b117624abb..1de2dae0fdae 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -18,6 +18,8 @@ /include/ "skeleton64.dtsi" +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + / { model = "Marvell Armada 370 and XP SoC"; compatible = "marvell,armada-370-xp"; @@ -38,18 +40,73 @@ }; soc { - #address-cells = <1>; + #address-cells = <2>; #size-cells = <1>; - compatible = "simple-bus"; + controller = <&mbusc>; interrupt-parent = <&mpic>; - ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ - 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; + pcie-mem-aperture = <0xe0000000 0x8000000>; + pcie-io-aperture = <0xe8000000 0x100000>; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; + ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; + ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3 { + compatible = "marvell,mvebu-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; + ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; internal-regs { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; mpic: interrupt-controller@20000 { compatible = "marvell,mpic"; @@ -81,10 +138,8 @@ }; timer@20300 { - compatible = "marvell,armada-370-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; - clocks = <&coreclk 2>; }; sata@a0000 { @@ -195,50 +250,6 @@ status = "disabled"; }; - devbus-bootcs@10400 { - compatible = "marvell,mvebu-devbus"; - reg = <0x10400 0x8>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs0@10408 { - compatible = "marvell,mvebu-devbus"; - reg = <0x10408 0x8>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs1@10410 { - compatible = "marvell,mvebu-devbus"; - reg = <0x10410 0x8>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs2@10418 { - compatible = "marvell,mvebu-devbus"; - reg = <0x10418 0x8>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - devbus-cs3@10420 { - compatible = "marvell,mvebu-devbus"; - reg = <0x10420 0x8>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&coreclk 0>; - status = "disabled"; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index fa3dfc6b4c6a..e134d7a90c9a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -15,7 +15,7 @@ * common to all Armada SoCs. */ -/include/ "armada-370-xp.dtsi" +#include "armada-370-xp.dtsi" /include/ "skeleton.dtsi" / { @@ -29,8 +29,66 @@ }; soc { - ranges = <0 0xd0000000 0x0100000 /* internal registers */ - 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; + compatible = "marvell,armada370-mbus", "simple-bus"; + + bootrom { + compatible = "marvell,bootrom"; + reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; + internal-regs { system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; @@ -78,7 +136,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; }; @@ -89,7 +147,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; }; @@ -100,10 +158,15 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <91>; }; + timer@20300 { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; + }; + coreclk: mvebu-sar@18230 { compatible = "marvell,armada-370-core-clock"; reg = <0x18230 0x08>; @@ -169,54 +232,6 @@ 0x18304 0x4>; status = "okay"; }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts new file mode 100644 index 000000000000..c5fe57269f5a --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -0,0 +1,164 @@ +/* + * Device Tree file for Marvell RD-AXPWiFiAP. + * + * Note: this board is shipped with a new generation boot loader that + * remaps internal registers at 0xf1000000. Therefore, if earlyprintk + * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be + * used. + * + * Copyright (C) 2013 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Marvell RD-AXPWiFiAP"; + compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* First mini-PCIe port */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Second mini-PCIe port */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Renesas uPD720202 USB 3.0 controller */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + }; + + internal-regs { + pinctrl { + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + + pmx_ge0: pmx-ge0 { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + pmx_keys: pmx-keys { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; + marvell,function = "spi"; + }; + + pmx_phy_int: pmx-phy-int { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; + }; + + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; + }; + + sata@a0000 { + nr-ports = <1>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + ethernet@70000 { + pinctrl-0 = <&pmx_ge0>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + spi0: spi@10600 { + status = "okay"; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_keys>; + pinctrl-names = "default"; + + button@1 { + label = "Factory Reset Button"; + linux,code = <141>; /* KEY_SETUP */ + gpios = <&gpio1 1 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index e28e68ff864d..bcf6d79a57ec 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -14,7 +14,7 @@ */ /dts-v1/; -/include/ "armada-xp-mv78460.dtsi" +#include "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Evaluation Board"; @@ -30,9 +30,70 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ - 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ - 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; internal-regs { serial@12000 { @@ -127,68 +188,6 @@ spi-max-frequency = <20000000>; }; }; - - pcie-controller { - status = "okay"; - - /* - * All 6 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 0, Lane 2 */ - status = "okay"; - }; - pcie@4,0 { - /* Port 0, Lane 3 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - - devbus-bootcs@10400 { - status = "okay"; - ranges = <0 0xf0000000 0x1000000>; - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index c87b2de29c30..2298e4a910e2 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -14,7 +14,7 @@ */ /dts-v1/; -/include/ "armada-xp-mv78460.dtsi" +#include "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Development Board DB-MV784MP-GP"; @@ -39,9 +39,58 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ - 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ - 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; internal-regs { serial@12000 { @@ -126,56 +175,6 @@ spi-max-frequency = <108000000>; }; }; - - devbus-bootcs@10400 { - status = "okay"; - ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 16 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x1000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f8eaa383e07f..0358a33cba48 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -13,7 +13,7 @@ * common to all Armada XP SoCs. */ -/include/ "armada-xp.dtsi" +#include "armada-xp.dtsi" / { model = "Marvell Armada XP MV78230 SoC"; @@ -44,6 +44,124 @@ }; soc { + /* + * MV78230 has 2 PCIe units Gen2.0: One unit can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + }; + internal-regs { pinctrl { compatible = "marvell,mv78230-pinctrl"; @@ -63,7 +181,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; }; @@ -74,113 +192,9 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <87>, <88>, <89>; }; - - /* - * MV78230 has 2 PCIe units Gen2.0: One unit can be - * configured as x4 or quad x1 lanes. One unit is - * x4/x1. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - -#address-cells = <3>; -#size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 2d9335da210c..0e82c5062243 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -13,7 +13,7 @@ * common to all Armada XP SoCs. */ -/include/ "armada-xp.dtsi" +#include "armada-xp.dtsi" / { model = "Marvell Armada XP MV78260 SoC"; @@ -45,6 +45,145 @@ }; soc { + /* + * MV78260 has 3 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; + internal-regs { pinctrl { compatible = "marvell,mv78260-pinctrl"; @@ -64,7 +203,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; }; @@ -75,7 +214,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; }; @@ -86,7 +225,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <91>; }; @@ -97,128 +236,6 @@ clocks = <&gateclk 1>; status = "disabled"; }; - - /* - * MV78260 has 3 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. One unit is - * x4/x1. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - pcie@10,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - status = "disabled"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index c7b1f4d5c1c7..e82c1b80af17 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -13,7 +13,7 @@ * common to all Armada XP SoCs. */ -/include/ "armada-xp.dtsi" +#include "armada-xp.dtsi" / { model = "Marvell Armada XP MV78460 SoC"; @@ -61,6 +61,227 @@ }; soc { + /* + * MV78460 has 4 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ + + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ + + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ + + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 + 0x81000000 0 0 0x81000000 0x3 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 + 0x81000000 0 0 0x81000000 0x4 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 + 0x81000000 0 0 0x81000000 0x5 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 + 0x81000000 0 0 0x81000000 0x6 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 + 0x81000000 0 0 0x81000000 0x7 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 + 0x81000000 0 0 0x81000000 0x8 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; + internal-regs { pinctrl { compatible = "marvell,mv78460-pinctrl"; @@ -80,7 +301,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; }; @@ -91,7 +312,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; }; @@ -102,7 +323,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupts-cells = <2>; + #interrupt-cells = <2>; interrupts = <91>; }; @@ -113,194 +334,6 @@ clocks = <&gateclk 1>; status = "disabled"; }; - - /* - * MV78460 has 4 PCIe units Gen2.0: Two units can be - * configured as x4 or quad x1 lanes. Two units are - * x4/x1. - */ - pcie-controller { - compatible = "marvell,armada-xp-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ - 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - pcie@5,0 { - device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; - status = "disabled"; - }; - pcie@9,0 { - device_type = "pci"; - assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; - status = "disabled"; - }; - - pcie@10,0 { - device_type = "pci"; - assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; - reg = <0x5000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 27>; - status = "disabled"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 8f510458ea86..5695afcc04bf 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -11,7 +11,7 @@ */ /dts-v1/; -/include/ "armada-xp-mv78260.dtsi" +#include "armada-xp-mv78260.dtsi" / { model = "PlatHome OpenBlocks AX3-4 board"; @@ -27,9 +27,46 @@ }; soc { - ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ - 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ - 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; internal-regs { serial@12000 { @@ -148,49 +185,6 @@ usb@51000 { status = "okay"; }; - - /* USB interface in the mini-PCIe connector */ - usb@52000 { - status = "okay"; - }; - - devbus-bootcs@10400 { - status = "okay"; - ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - - pcie-controller { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 416eb9481844..def125c0eeaa 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -16,7 +16,7 @@ * common to all Armada SoCs. */ -/include/ "armada-370-xp.dtsi" +#include "armada-370-xp.dtsi" / { model = "Marvell Armada XP family SoC"; @@ -27,6 +27,13 @@ }; soc { + compatible = "marvell,armadaxp-mbus", "simple-bus"; + + bootrom { + compatible = "marvell,bootrom"; + reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; + }; + internal-regs { L2: l2-cache { compatible = "marvell,aurora-system-cache"; @@ -62,7 +69,7 @@ }; timer@20300 { - marvell,timer-25Mhz; + compatible = "marvell,armada-xp-timer"; }; coreclk: mvebu-sar@18230 { diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 92b9e21389db..f77065506f1e 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -120,6 +120,7 @@ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/at91rm9200_pqfp.dtsi new file mode 100644 index 000000000000..93ca66f80360 --- /dev/null +++ b/arch/arm/boot/dts/at91rm9200_pqfp.dtsi @@ -0,0 +1,17 @@ +/* + * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC + * + * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 or later. + */ + +#include "at91rm9200.dtsi" + +/ { + compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200"; +}; + +&pioD { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index c7ccbcbffb3e..56ee8282a7a8 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -572,6 +572,7 @@ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index bb7f564b3a55..9fb7ffd32af2 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -291,6 +291,22 @@ }; }; + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE + AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + }; + tcb0 { pinctrl_tcb0_tclk0: tcb0_tclk0-0 { atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; @@ -471,6 +487,8 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; status = "disabled"; }; @@ -483,6 +501,8 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d59b70c6a6a0..27a9352b9d7a 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -14,11 +14,11 @@ compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9"; chosen { - bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; + bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2"; }; memory { - reg = <0x20000000 0x10000000>; + reg = <0x20000000 0x8000000>; }; clocks { @@ -40,6 +40,15 @@ i2c0: i2c@f8010000 { status = "okay"; + + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + }; }; i2c1: i2c@f8014000 { @@ -66,6 +75,13 @@ <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */ }; }; + + qt1070 { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; }; spi0: spi@f0000000 { @@ -121,7 +137,7 @@ enter { label = "Enter"; - gpios = <&pioB 4 GPIO_ACTIVE_LOW>; + gpios = <&pioB 3 GPIO_ACTIVE_LOW>; linux,code = <28>; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 57d45f5bea09..cf78ac0b04b1 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -542,6 +542,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index b753855b2058..3a9f6fa4a36a 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -59,6 +59,11 @@ i2c0: i2c@f8010000 { status = "okay"; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; }; pinctrl@fffff400 { @@ -90,12 +95,17 @@ watchdog@fffffe40 { status = "okay"; }; + + ssc0: ssc@f0010000 { + status = "okay"; + }; }; usb0: ohci@00600000 { status = "okay"; - num-ports = <2>; - atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ + &pioD 19 GPIO_ACTIVE_LOW &pioD 20 GPIO_ACTIVE_LOW >; }; @@ -104,4 +114,19 @@ status = "okay"; }; }; + + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; }; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index a0f2721ea583..8678e0c11119 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -329,6 +329,12 @@ sirf,function = "uart0"; }; }; + uart0_noflow_pins_a: uart0@1 { + uart { + sirf,pins = "uart0_nostreamctrlgrp"; + sirf,function = "uart0_nostreamctrl"; + }; + }; uart1_pins_a: uart1@0 { uart { sirf,pins = "uart1grp"; diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts index 67ec524098b5..9d36eb4e3c41 100644 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ b/arch/arm/boot/dts/bcm11351-brt.dts @@ -17,7 +17,7 @@ / { model = "BCM11351 BRT board"; - compatible = "bcm,bcm11351-brt", "bcm,bcm11351"; + compatible = "brcm,bcm11351-brt", "brcm,bcm11351"; memory { reg = <0x80000000 0x40000000>; /* 1 GB */ @@ -27,18 +27,18 @@ status = "okay"; }; - sdio0: sdio@0x3f180000 { + sdio1: sdio@3f180000 { max-frequency = <48000000>; status = "okay"; }; - sdio1: sdio@0x3f190000 { + sdio2: sdio@3f190000 { non-removable; max-frequency = <48000000>; status = "okay"; }; - sdio3: sdio@0x3f1b0000 { + sdio4: sdio@3f1b0000 { max-frequency = <48000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index c0cdf66f8964..05a5aabe3b2c 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Broadcom Corporation + * Copyright (C) 2012-2013 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,7 +18,7 @@ / { model = "BCM11351 SoC"; - compatible = "bcm,bcm11351"; + compatible = "brcm,bcm11351"; interrupt-parent = <&gic>; chosen { @@ -35,12 +35,12 @@ }; smc@0x3404c000 { - compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; + compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; uart@3e000000 { - compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; + compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x1000>; clock-frequency = <13000000>; @@ -50,42 +50,47 @@ }; L2: l2-cache { - compatible = "bcm,bcm11351-a2-pl310-cache"; + compatible = "brcm,bcm11351-a2-pl310-cache"; reg = <0x3ff20000 0x1000>; cache-unified; cache-level = <2>; }; + watchdog@35002f40 { + compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; + reg = <0x35002f40 0x6c>; + }; + timer@35006000 { - compatible = "bcm,kona-timer"; + compatible = "brcm,kona-timer"; reg = <0x35006000 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <32768>; }; - sdio0: sdio@0x3f180000 { - compatible = "bcm,kona-sdhci"; + sdio1: sdio@3f180000 { + compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; interrupts = <0x0 77 0x4>; status = "disabled"; }; - sdio1: sdio@0x3f190000 { - compatible = "bcm,kona-sdhci"; + sdio2: sdio@3f190000 { + compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; interrupts = <0x0 76 0x4>; status = "disabled"; }; - sdio2: sdio@0x3f1a0000 { - compatible = "bcm,kona-sdhci"; + sdio3: sdio@3f1a0000 { + compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; interrupts = <0x0 74 0x4>; status = "disabled"; }; - sdio3: sdio@0x3f1b0000 { - compatible = "bcm,kona-sdhci"; + sdio4: sdio@3f1b0000 { + compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; interrupts = <0x0 73 0x4>; status = "disabled"; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts new file mode 100644 index 000000000000..96ae67a2f0d3 --- /dev/null +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "bcm11351.dtsi" + +/ { + model = "BCM28155 AP board"; + compatible = "brcm,bcm28155-ap", "brcm,bcm11351"; + + memory { + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + uart@3e000000 { + status = "okay"; + }; + + sdio1: sdio@3f180000 { + max-frequency = <48000000>; + status = "okay"; + }; + + sdio2: sdio@3f190000 { + non-removable; + max-frequency = <48000000>; + status = "okay"; + }; + + sdio4: sdio@3f1b0000 { + max-frequency = <48000000>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts deleted file mode 100644 index 48ff03441f5a..000000000000 --- a/arch/arm/boot/dts/ccu8540.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2013 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "dbx5x0.dtsi" - -/ { - model = "ST-Ericsson U8540 platform with Device Tree"; - compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; - - memory@0 { - reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; - }; - - soc { - prcmu@80157000 { - reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; - reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - }; - - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 5bce7cc55cf3..588ce58a2959 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -90,6 +90,17 @@ }; }; }; + mdio: mdio@1e24000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + }; + eth0: ethernet@1e20000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + }; }; nand_cs3@62000000 { status = "okay"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index d70ba5504481..8d17346f9702 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -125,11 +125,33 @@ 0x14 0x00000010 0x000000f0 >; }; + mdio_pins: pinmux_mdio_pins { + pinctrl-single,bits = < + /* MDIO_CLK, MDIO_D */ + 0x10 0x00000088 0x000000ff + >; + }; + mii_pins: pinmux_mii_pins { + pinctrl-single,bits = < + /* + * MII_TXEN, MII_TXCLK, MII_COL + * MII_TXD_3, MII_TXD_2, MII_TXD_1 + * MII_TXD_0 + */ + 0x8 0x88888880 0xfffffff0 + /* + * MII_RXER, MII_CRS, MII_RXCLK + * MII_RXDV, MII_RXD_3, MII_RXD_2 + * MII_RXD_1, MII_RXD_0 + */ + 0xc 0x88888888 0xffffffff + >; + }; + }; serial0: serial@1c42000 { compatible = "ns16550a"; reg = <0x42000 0x100>; - clock-frequency = <150000000>; reg-shift = <2>; interrupts = <25>; status = "disabled"; @@ -137,7 +159,6 @@ serial1: serial@1d0c000 { compatible = "ns16550a"; reg = <0x10c000 0x100>; - clock-frequency = <150000000>; reg-shift = <2>; interrupts = <53>; status = "disabled"; @@ -145,7 +166,6 @@ serial2: serial@1d0d000 { compatible = "ns16550a"; reg = <0x10d000 0x100>; - clock-frequency = <150000000>; reg-shift = <2>; interrupts = <61>; status = "disabled"; @@ -216,6 +236,26 @@ interrupts = <56>; status = "disabled"; }; + mdio: mdio@1e24000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x224000 0x1000>; + }; + eth0: ethernet@1e20000 { + compatible = "ti,davinci-dm6467-emac"; + reg = <0x220000 0x4000>; + ti,davinci-ctrl-reg-offset = <0x3000>; + ti,davinci-ctrl-mod-reg-offset = <0x2000>; + ti,davinci-ctrl-ram-offset = <0>; + ti,davinci-ctrl-ram-size = <0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <33 + 34 + 35 + 36 + >; + }; }; nand_cs3@62000000 { compatible = "ti,davinci-nand"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 5cae2ab69762..022646ef4b38 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -42,6 +42,8 @@ regulator-always-on; regulator-boot-on; gpio = <&gpio0 1 0>; + pinctrl-0 = <&pmx_gpio_1>; + pinctrl-names = "default"; }; }; @@ -53,10 +55,24 @@ clock-frequency = <25000000>; }; }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 19 1>; + pinctrl-0 = <&pmx_gpio_19>; + pinctrl-names = "default"; + }; }; &uart0 { status = "okay"; }; &sata0 { status = "okay"; }; +&mdio { status = "okay"; }; +ð { status = "okay"; }; + +ðphy { + compatible = "marvell,88e1310"; + reg = <1>; +}; &i2c0 { status = "okay"; @@ -103,6 +119,7 @@ status = "okay"; /* sdio0 card detect is connected to wrong pin on CuBox */ cd-gpios = <&gpio0 12 1>; + pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>; }; &spi0 { @@ -115,23 +132,3 @@ reg = <0>; }; }; - -&pinctrl { - pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>; - pinctrl-names = "default"; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts new file mode 100644 index 000000000000..e2222ce94f2f --- /dev/null +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -0,0 +1,69 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "Globalscale D2Plug"; + compatible = "globalscale,d2plug", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; + pinctrl-names = "default"; + + wlan-ap { + label = "wlan-ap"; + gpios = <&gpio0 0 1>; + }; + + wlan-act { + label = "wlan-act"; + gpios = <&gpio0 1 1>; + }; + + bluetooth-act { + label = "bt-act"; + gpios = <&gpio0 2 1>; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; +&mdio { status = "okay"; }; +ð { status = "okay"; }; + +/* Samsung M8G2F eMMC */ +&sdio0 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +/* Marvell SD8787 WLAN/BT */ +&sdio1 { + status = "okay"; + non-removable; + bus-width = <4>; +}; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Macronix MX25L3205D */ + spi-flash@0 { + compatible = "st,m25l3205d"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 6cab46849cdb..cc279166646f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -10,6 +10,23 @@ gpio2 = &gpio2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "marvell,pj4a", "marvell,sheeva-v7"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + }; + + l2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0>; + }; + soc@f1000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -25,16 +42,28 @@ 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ - l2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0>; + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; }; - intc: interrupt-controller { + intc: main-interrupt-ctrl@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; - reg = <0x20204 0x04>, <0x20214 0x04>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; }; core_clk: core-clocks@d0214 { @@ -43,14 +72,14 @@ #clock-cells = <1>; }; - gate_clk: clock-gating-control@d0038 { + gate_clk: clock-gating-ctrl@d0038 { compatible = "marvell,dove-gating-clock"; reg = <0xd0038 0x4>; clocks = <&core_clk 0>; #clock-cells = <1>; }; - thermal: thermal@d001c { + thermal: thermal-diode@d001c { compatible = "marvell,dove-thermal"; reg = <0xd001c 0x0c>, <0xd005c 0x08>; }; @@ -70,6 +99,8 @@ reg-shift = <2>; interrupts = <8>; clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; status = "disabled"; }; @@ -91,7 +122,7 @@ status = "disabled"; }; - gpio0: gpio@d0400 { + gpio0: gpio-ctrl@d0400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; @@ -102,7 +133,7 @@ interrupts = <12>, <13>, <14>, <60>; }; - gpio1: gpio@d0420 { + gpio1: gpio-ctrl@d0420 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; @@ -113,7 +144,7 @@ interrupts = <61>; }; - gpio2: gpio@e8400 { + gpio2: gpio-ctrl@e8400 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; gpio-controller; @@ -121,13 +152,188 @@ ngpios = <8>; }; - pinctrl: pinctrl@d0200 { + pinctrl: pin-ctrl@d0200 { compatible = "marvell,dove-pinctrl"; reg = <0xd0200 0x10>; clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; }; - spi0: spi@10600 { + spi0: spi-ctrl@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; @@ -135,10 +341,12 @@ interrupts = <6>; reg = <0x10600 0x28>; clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; status = "disabled"; }; - spi1: spi@14600 { + spi1: spi-ctrl@14600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; @@ -149,7 +357,7 @@ status = "disabled"; }; - i2c0: i2c@11000 { + i2c0: i2c-ctrl@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; @@ -177,23 +385,27 @@ status = "okay"; }; - sdio0: sdio@92000 { + sdio0: sdio-host@92000 { compatible = "marvell,dove-sdhci"; reg = <0x92000 0x100>; interrupts = <35>, <37>; clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; status = "disabled"; }; - sdio1: sdio@90000 { + sdio1: sdio-host@90000 { compatible = "marvell,dove-sdhci"; reg = <0x90000 0x100>; interrupts = <36>, <38>; clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; status = "disabled"; }; - sata0: sata@a0000 { + sata0: sata-host@a0000 { compatible = "marvell,orion-sata"; reg = <0xa0000 0x2400>; interrupts = <62>; @@ -202,12 +414,12 @@ status = "disabled"; }; - rtc@d8500 { + rtc: real-time-clock@d8500 { compatible = "marvell,orion-rtc"; reg = <0xd8500 0x20>; }; - crypto: crypto@30000 { + crypto: crypto-engine@30000 { compatible = "marvell,orion-crypto"; reg = <0x30000 0x10000>, <0xc8000000 0x800>; @@ -258,5 +470,40 @@ dmacap,xor; }; }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + + ethphy: ethernet-phy { + device-type = "ethernet-phy"; + /* set phy address in board file */ + }; + }; + + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðphy>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 3f94fe8e3706..caadc0257342 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -36,6 +36,12 @@ i2c5 = &i2c_5; i2c6 = &i2c_6; i2c7 = &i2c_7; + csis0 = &csis_0; + csis1 = &csis_1; + fimc0 = &fimc_0; + fimc1 = &fimc_1; + fimc2 = &fimc_2; + fimc3 = &fimc_3; }; chipid@10000000 { @@ -92,6 +98,88 @@ reg = <0x10010000 0x400>; }; + camera { + compatible = "samsung,fimc", "simple-bus"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock_cam: clock-controller { + #clock-cells = <1>; + }; + + fimc_0: fimc@11800000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11800000 0x1000>; + interrupts = <0 84 0>; + clocks = <&clock 256>, <&clock 128>; + clock-names = "fimc", "sclk_fimc"; + samsung,power-domain = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + fimc_1: fimc@11810000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11810000 0x1000>; + interrupts = <0 85 0>; + clocks = <&clock 257>, <&clock 129>; + clock-names = "fimc", "sclk_fimc"; + samsung,power-domain = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + fimc_2: fimc@11820000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11820000 0x1000>; + interrupts = <0 86 0>; + clocks = <&clock 258>, <&clock 130>; + clock-names = "fimc", "sclk_fimc"; + samsung,power-domain = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + fimc_3: fimc@11830000 { + compatible = "samsung,exynos4210-fimc"; + reg = <0x11830000 0x1000>; + interrupts = <0 87 0>; + clocks = <&clock 259>, <&clock 131>; + clock-names = "fimc", "sclk_fimc"; + samsung,power-domain = <&pd_cam>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + csis_0: csis@11880000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11880000 0x4000>; + interrupts = <0 78 0>; + clocks = <&clock 260>, <&clock 134>; + clock-names = "csis", "sclk_csis"; + bus-width = <4>; + samsung,power-domain = <&pd_cam>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csis_1: csis@11890000 { + compatible = "samsung,exynos4210-csis"; + reg = <0x11890000 0x4000>; + interrupts = <0 80 0>; + clocks = <&clock 261>, <&clock 135>; + clock-names = "csis", "sclk_csis"; + bus-width = <2>; + samsung,power-domain = <&pd_cam>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; @@ -155,13 +243,31 @@ status = "disabled"; }; + ehci@12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = <0 70 0>; + clocks = <&clock 304>; + clock-names = "usbhost"; + status = "disabled"; + }; + + ohci@12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = <0 70 0>; + clocks = <&clock 304>; + clock-names = "usbhost"; + status = "disabled"; + }; + mfc: codec@13400000 { compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; interrupts = <0 94 0>; samsung,power-domain = <&pd_mfc>; - clocks = <&clock 170>, <&clock 273>; - clock-names = "sclk_mfc", "mfc"; + clocks = <&clock 273>; + clock-names = "mfc"; status = "disabled"; }; @@ -297,8 +403,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13920000 0x100>; interrupts = <0 66 0>; - tx-dma-channel = <&pdma0 7>; /* preliminary */ - rx-dma-channel = <&pdma0 6>; /* preliminary */ + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clock 327>, <&clock 159>; @@ -312,8 +418,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13930000 0x100>; interrupts = <0 67 0>; - tx-dma-channel = <&pdma1 7>; /* preliminary */ - rx-dma-channel = <&pdma1 6>; /* preliminary */ + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clock 328>, <&clock 160>; @@ -327,8 +433,8 @@ compatible = "samsung,exynos4210-spi"; reg = <0x13940000 0x100>; interrupts = <0 68 0>; - tx-dma-channel = <&pdma0 9>; /* preliminary */ - rx-dma-channel = <&pdma0 8>; /* preliminary */ + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clock 329>, <&clock 161>; @@ -342,6 +448,8 @@ compatible = "samsung,exynos4210-pwm"; reg = <0x139D0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; + clocks = <&clock 336>; + clock-names = "timers"; #pwm-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 553bceae8967..a7c212891674 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -797,6 +797,29 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + cam_port_a_io: cam-port-a-io { + samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", + "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_port_a_clk_active: cam-port-a-clk-active { + samsung,pins = "gpj1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle { + samsung,pins = "gpj1-3"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; }; pinctrl@03860000 { diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 94eebffe3044..1c164f234bcc 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,13 +30,62 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; - vemmc_reg: voltage-regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 0>; - enable-active-high; + regulators { + compatible = "simple-bus"; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 0>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpl0 3 0>; + enable-active-high; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 0>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 0>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 0>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 0>; + enable-active-high; + }; }; sdhci_emmc: sdhci@12510000 { @@ -97,15 +146,6 @@ }; }; - tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpl0 3 0>; - enable-active-high; - }; - i2c@13890000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -218,6 +258,12 @@ regulator-always-on; }; + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vcclcd_reg: LDO13 { regulator-name = "VCC_3.3V_LCD"; regulator-min-microvolt = <3300000>; @@ -301,4 +347,26 @@ clock-frequency = <24000000>; }; }; + + camera { + pinctrl-names = "default"; + pinctrl-0 = <>; + status = "okay"; + + fimc_0: fimc@11800000 { + status = "okay"; + }; + + fimc_1: fimc@11810000 { + status = "okay"; + }; + + fimc_2: fimc@11820000 { + status = "okay"; + }; + + fimc_3: fimc@11830000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b7f358a93bcb..057d6829d319 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -72,7 +72,7 @@ }; }; - clock: clock-controller@0x10030000 { + clock: clock-controller@10030000 { compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; @@ -125,4 +125,34 @@ clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; + + camera { + clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + fimc_0: fimc@11800000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_1: fimc@11810000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,cam-if; + }; + + fimc_2: fimc@11820000 { + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + + fimc_3: fimc@11830000 { + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,lcd-wb; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 7993641cb32a..8768b03702e5 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -27,6 +27,11 @@ bootargs ="console=ttySAC2,115200"; }; + firmware@0203F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0203F000 0x1000>; + }; + mmc_reg: voltage-regulator { compatible = "regulator-fixed"; regulator-name = "VMEM_VDD_2.8V"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts new file mode 100644 index 000000000000..fb7b9ae5f399 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -0,0 +1,579 @@ +/* + * Samsung's Exynos4412 based Trats 2 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Trats 2 board which is based on + * Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos4412.dtsi" + +/ { + model = "Samsung Trats 2 based on Exynos4412"; + compatible = "samsung,trats2", "samsung,exynos4412"; + + aliases { + i2c8 = &i2c_ak8975; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + }; + + firmware@0204F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti", "fixed-clock"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 0>; + enable-active-high; + }; + + cam_io_reg: voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_A"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpm0 2 0>; + enable-active-high; + }; + + /* More to come */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-down { + interrupt-parent = <&gpj1>; + interrupts = <2 0>; + gpios = <&gpj1 2 1>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <10>; + }; + + key-up { + interrupt-parent = <&gpj1>; + interrupts = <1 0>; + gpios = <&gpj1 1 1>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + interrupt-parent = <&gpx2>; + interrupts = <7 0>; + gpios = <&gpx2 7 1>; + linux,code = <116>; + label = "power"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + i2c@13890000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + mms114-touchscreen@48 { + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpm2>; + interrupts = <3 2>; + x-size = <720>; + y-size = <1280>; + avdd-supply = <&ldo23_reg>; + vdd-supply = <&ldo24_reg>; + }; + }; + + i2c@138D0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 0>; + reg = <0x09>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-off; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-mem-idle; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-idle; + }; + + buck1_reg: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck2_reg: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-mem-off; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-mem-off; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-mem-off; + }; + }; + }; + }; + + sdhci@12510000 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + + i2c_ak8975: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&gpy2 4 0>, <&gpy2 5 0>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ak8975@0c { + compatible = "ak,ak8975"; + reg = <0x0c>; + gpios = <&gpj0 7 0>; + }; + }; + + spi_1: spi@13930000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "okay"; + + s5c73m3_spi: s5c73m3 { + compatible = "samsung,s5c73m3"; + spi-max-frequency = <50000000>; + reg = <0>; + controller-data { + cs-gpio = <&gpb 5 0>; + samsung,spi-feedback-delay = <2>; + }; + }; + }; + + camera { + pinctrl-0 = <&cam_port_b_clk_active>; + pinctrl-names = "default"; + status = "okay"; + + fimc_0: fimc@11800000 { + status = "okay"; + }; + + fimc_1: fimc@11810000 { + status = "okay"; + }; + + fimc_2: fimc@11820000 { + status = "okay"; + }; + + fimc_3: fimc@11830000 { + status = "okay"; + }; + + csis_1: csis@11890000 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + clock-frequency = <160000000>; + status = "okay"; + + /* Camera D (4) MIPI CSI-2 (CSIS1) */ + port@4 { + reg = <4>; + csis1_ep: endpoint { + remote-endpoint = <&is_s5k6a3_ep>; + data-lanes = <1>; + samsung,csis-hs-settle = <18>; + samsung,csis-wclk; + }; + }; + }; + + fimc_lite_0: fimc-lite@12390000 { + status = "okay"; + }; + + fimc_lite_1: fimc-lite@123A0000 { + status = "okay"; + }; + + fimc-is@12000000 { + pinctrl-0 = <&fimc_is_uart>; + pinctrl-names = "default"; + status = "okay"; + + i2c1_isp: i2c-isp@12140000 { + pinctrl-0 = <&fimc_is_i2c1>; + pinctrl-names = "default"; + + s5k6a3@10 { + compatible = "samsung,s5k6a3"; + reg = <0x10>; + svdda-supply = <&cam_io_reg>; + svddio-supply = <&ldo19_reg>; + clock-frequency = <24000000>; + /* CAM_B_CLKOUT */ + clocks = <&clock_cam 1>; + clock-names = "mclk"; + samsung,camclk-out = <1>; + gpios = <&gpm1 6 0>; + + port { + is_s5k6a3_ep: endpoint { + remote-endpoint = <&csis1_ep>; + data-lanes = <1>; + }; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 704290f7c5c0..99b26df8dbc7 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -401,13 +401,26 @@ samsung,pin-drv = <0>; }; - cam_port_a: cam-port-a { + cam_port_a_io: cam-port-a-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", - "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3", - "gpj1-4"; + "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; samsung,pin-function = <2>; - samsung,pin-pud = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_port_a_clk_active: cam-port-a-clk-active { + samsung,pins = "gpj1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_a_clk_idle: cam-port-a-clk-idle { + samsung,pins = "gpj1-3"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; }; @@ -778,16 +791,29 @@ samsung,pin-drv = <3>; }; - cam_port_b: cam-port-b { + cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", - "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1", - "gpm2-2"; + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; samsung,pin-function = <3>; samsung,pin-pud = <3>; samsung,pin-drv = <0>; }; + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + eint0: ext-int0 { samsung,pins = "gpx0-0"; samsung,pin-function = <0xf>; @@ -822,6 +848,27 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; pinctrl@03860000 { diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 01da194ba329..ad531fe6ab95 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -26,9 +26,16 @@ pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; + fimc-lite0 = &fimc_lite_0; + fimc-lite1 = &fimc_lite_1; }; - clock: clock-controller@0x10030000 { + pd_isp: isp-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; @@ -73,4 +80,100 @@ clock-names = "sclk_fimg2d", "fimg2d"; status = "disabled"; }; + + camera { + clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + fimc_0: fimc@11800000 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; + }; + + fimc_1: fimc@11810000 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; + }; + + fimc_2: fimc@11820000 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + samsung,cam-if; + }; + + fimc_3: fimc@11830000 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + }; + + fimc_lite_0: fimc-lite@12390000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x12390000 0x1000>; + interrupts = <0 105 0>; + samsung,power-domain = <&pd_isp>; + clocks = <&clock 353>; + clock-names = "flite"; + status = "disabled"; + }; + + fimc_lite_1: fimc-lite@123A0000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x123A0000 0x1000>; + interrupts = <0 106 0>; + samsung,power-domain = <&pd_isp>; + clocks = <&clock 354>; + clock-names = "flite"; + status = "disabled"; + }; + + fimc_is: fimc-is@12000000 { + compatible = "samsung,exynos4212-fimc-is", "simple-bus"; + reg = <0x12000000 0x260000>; + interrupts = <0 90 0>, <0 95 0>; + samsung,power-domain = <&pd_isp>; + clocks = <&clock 353>, <&clock 354>, <&clock 355>, + <&clock 356>, <&clock 17>, <&clock 357>, + <&clock 358>, <&clock 359>, <&clock 360>, + <&clock 450>,<&clock 451>, <&clock 452>, + <&clock 453>, <&clock 176>, <&clock 13>, + <&clock 454>, <&clock 395>, <&clock 455>; + clock-names = "lite0", "lite1", "ppmuispx", + "ppmuispmx", "mpll", "isp", + "drc", "fd", "mcuisp", + "ispdiv0", "ispdiv1", "mcuispdiv0", + "mcuispdiv1", "uart", "aclk200", + "div_aclk200", "aclk400mcuisp", + "div_aclk400mcuisp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pmu { + reg = <0x10020000 0x3000>; + }; + + i2c1_isp: i2c-isp@12140000 { + compatible = "samsung,exynos4212-i2c-isp"; + reg = <0x12140000 0x100>; + clocks = <&clock 370>; + clock-names = "i2c_isp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index f65e124c04a6..6afa57d2fecc 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -108,4 +108,23 @@ interrupts = <0 42 0>; status = "disabled"; }; + + fimd@14400000 { + compatible = "samsung,exynos5250-fimd"; + interrupt-parent = <&combiner>; + reg = <0x14400000 0x40000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <18 4>, <18 5>, <18 6>; + status = "disabled"; + }; + + dp-controller@145B0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145B0000 0x1000>; + interrupts = <10 3>; + interrupt-parent = <&combiner>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index abc7272c7afd..452d0b04d273 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos5250.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; @@ -37,6 +38,28 @@ s5m8767_pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + vinb1-supply = <&main_dc_reg>; + vinb2-supply = <&main_dc_reg>; + vinb3-supply = <&main_dc_reg>; + vinb4-supply = <&main_dc_reg>; + vinb5-supply = <&main_dc_reg>; + vinb6-supply = <&main_dc_reg>; + vinb7-supply = <&main_dc_reg>; + vinb8-supply = <&main_dc_reg>; + vinb9-supply = <&main_dc_reg>; + + vinl1-supply = <&buck7_reg>; + vinl2-supply = <&buck7_reg>; + vinl3-supply = <&buck7_reg>; + vinl4-supply = <&main_dc_reg>; + vinl5-supply = <&main_dc_reg>; + vinl6-supply = <&main_dc_reg>; + vinl7-supply = <&main_dc_reg>; + vinl8-supply = <&buck8_reg>; + vinl9-supply = <&buck8_reg>; s5m8767,pmic-buck2-dvs-voltage = <1300000>; s5m8767,pmic-buck3-dvs-voltage = <1100000>; @@ -276,6 +299,16 @@ op_mode = <1>; }; + buck7_reg: BUCK7 { + regulator-name = "PVDD_BUCK7"; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "PVDD_BUCK8"; + regulator-always-on; + }; + buck9_reg: BUCK9 { regulator-name = "VDD_33_OFF_EXT1"; regulator-min-microvolt = <750000>; @@ -295,7 +328,22 @@ }; i2c@12C90000 { - status = "disabled"; + wm1811a@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + + AVDD2-supply = <&main_dc_reg>; + CPVDD-supply = <&main_dc_reg>; + DBVDD1-supply = <&main_dc_reg>; + DBVDD2-supply = <&main_dc_reg>; + DBVDD3-supply = <&main_dc_reg>; + LDO1VDD-supply = <&main_dc_reg>; + SPKVDD1-supply = <&main_dc_reg>; + SPKVDD2-supply = <&main_dc_reg>; + + wlf,ldo1ena = <&gpb0 0 0>; + wlf,ldo2ena = <&gpb0 1 0>; + }; }; i2c@12CA0000 { @@ -429,18 +477,29 @@ vdd-supply = <&ldo8_reg>; }; - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 1>; - enable-active-high; - }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_hdmi_en: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-en"; + main_dc_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "MAIN_DC"; + }; + + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 1>; + enable-active-high; + }; + + reg_hdmi_en: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-en"; + }; }; fixed-rate-clocks { @@ -450,16 +509,18 @@ }; }; - dp-controller { + dp-controller@145B0000 { samsung,color-space = <0>; samsung,dynamic-range = <0>; samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <4>; + status = "okay"; }; fimd: fimd@14400000 { + status = "okay"; display-timings { native-mode = <&timing0>; timing0: timing@0 { @@ -480,4 +541,22 @@ rtc { status = "okay"; }; + + usb_hub_bus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + // SMSC USB3503 connected in hardware only mode as a PHY + usb_hub: usb_hub { + compatible = "smsc,usb3503a"; + + reset-gpios = <&gpx3 5 1>; + connect-gpios = <&gpd1 7 1>; + }; + }; + + usb@12110000 { + usb-phy = <&usb2_phy>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c24a576..2538b329f2ce 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -250,7 +250,7 @@ samsung,vbus-gpio = <&gpx2 6 0>; }; - dp-controller { + dp-controller@145B0000 { samsung,color-space = <0>; samsung,dynamic-range = <0>; samsung,ycbcr-coeff = <0>; @@ -260,21 +260,25 @@ pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; + status = "okay"; }; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; + fimd@14400000 { + status = "okay"; + display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + /* 1280x800 */ + clock-frequency = <50000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <4>; + hback-porch = <4>; + hsync-len = <4>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index ef57277fc38f..f7e2d3493f82 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -68,17 +68,17 @@ }; }; - pd_gsc: gsc-power-domain@0x10044000 { + pd_gsc: gsc-power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; }; - pd_mfc: mfc-power-domain@0x10044040 { + pd_mfc: mfc-power-domain@10044040 { compatible = "samsung,exynos4210-pd"; reg = <0x10044040 0x20>; }; - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; @@ -163,11 +163,21 @@ clock-names = "watchdog"; }; + g2d@10850000 { + compatible = "samsung,exynos5250-g2d"; + reg = <0x10850000 0x1000>; + interrupts = <0 91 0>; + clocks = <&clock 345>; + clock-names = "fimg2d"; + }; + codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; samsung,power-domain = <&pd_mfc>; + clocks = <&clock 266>; + clock-names = "mfc"; }; rtc { @@ -405,7 +415,7 @@ }; i2s0: i2s@03830000 { - compatible = "samsung,i2s-v5"; + compatible = "samsung,s5pv210-i2s"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 &pdma0 9 @@ -415,16 +425,13 @@ <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_SCLK_I2S>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - samsung,supports-6ch; - samsung,supports-rstclr; - samsung,supports-secdai; samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; }; i2s1: i2s@12D60000 { - compatible = "samsung,i2s-v5"; + compatible = "samsung,s3c6410-i2s"; reg = <0x12D60000 0x100>; dmas = <&pdma1 12 &pdma1 11>; @@ -436,7 +443,7 @@ }; i2s2: i2s@12D70000 { - compatible = "samsung,i2s-v5"; + compatible = "samsung,s3c6410-i2s"; reg = <0x12D70000 0x100>; dmas = <&pdma0 12 &pdma0 11>; @@ -562,7 +569,7 @@ }; }; - gsc_0: gsc@0x13e00000 { + gsc_0: gsc@13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; @@ -571,7 +578,7 @@ clock-names = "gscl"; }; - gsc_1: gsc@0x13e10000 { + gsc_1: gsc@13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; @@ -580,7 +587,7 @@ clock-names = "gscl"; }; - gsc_2: gsc@0x13e20000 { + gsc_2: gsc@13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; @@ -589,7 +596,7 @@ clock-names = "gscl"; }; - gsc_3: gsc@0x13e30000 { + gsc_3: gsc@13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; @@ -614,28 +621,20 @@ interrupts = <0 94 0>; }; - dp-controller { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; + dp_phy: video-phy@10040720 { + compatible = "samsung,exynos5250-dp-video-phy"; + reg = <0x10040720 4>; + #phy-cells = <0>; + }; + + dp-controller@145B0000 { clocks = <&clock 342>; clock-names = "dp"; - #address-cells = <1>; - #size-cells = <0>; - - dptx-phy { - reg = <0x10040720>; - samsung,enable-mask = <1>; - }; + phys = <&dp_phy>; + phy-names = "dp"; }; - fimd { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; + fimd@14400000 { clocks = <&clock 133>, <&clock 339>; clock-names = "sclk_fimd", "fimd"; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 5848c425ae4d..e695aba5f73c 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -59,6 +59,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + dp_hpd: dp_hpd { + samsung,pins = "gpx0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; }; pinctrl@13410000 { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08607df6a180..bafba25ba7c2 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -30,4 +30,35 @@ clock-frequency = <24000000>; }; }; + + dp-controller@145B0000 { + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + status = "okay"; + }; + + fimd@14400000 { + status = "okay"; + display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; + }; + }; + }; + }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 8c54c4b74f0e..5353e32897a4 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -14,7 +14,10 @@ */ #include "exynos5.dtsi" -/include/ "exynos5420-pinctrl.dtsi" +#include "exynos5420-pinctrl.dtsi" + +#include <dt-bindings/clk/exynos-audss-clk.h> + / { compatible = "samsung,exynos5420"; @@ -59,12 +62,28 @@ }; }; - clock: clock-controller@0x10010000 { + clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; + clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5420-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + clocks = <&clock 148>; + clock-names = "sclk_audio"; + }; + + codec@11000000 { + compatible = "samsung,mfc-v7"; + reg = <0x11000000 0x10000>; + interrupts = <0 96 0>; + clocks = <&clock 401>; + clock-names = "mfc"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; @@ -90,6 +109,41 @@ }; }; + gsc_pd: power-domain@10044000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044000 0x20>; + }; + + isp_pd: power-domain@10044020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044020 0x20>; + }; + + mfc_pd: power-domain@10044060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044060 0x20>; + }; + + disp_pd: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + }; + + mau_pd: power-domain@100440E0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440E0 0x20>; + }; + + g2d_pd: power-domain@10044100 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044100 0x20>; + }; + + msc_pd: power-domain@10044120 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044120 0x20>; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -145,4 +199,23 @@ clocks = <&clock 260>, <&clock 131>; clock-names = "uart", "clk_uart_baud0"; }; + + dp_phy: video-phy@10040728 { + compatible = "samsung,exynos5250-dp-video-phy"; + reg = <0x10040728 4>; + #phy-cells = <0>; + }; + + dp-controller@145B0000 { + clocks = <&clock 412>; + clock-names = "dp"; + phys = <&dp_phy>; + phy-names = "dp"; + }; + + fimd@14400000 { + samsung,power-domain = <&disp_pd>; + clocks = <&clock 147>, <&clock 421>; + clock-names = "sclk_fimd", "fimd"; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index ff7f5d855845..5d6cf4965d6e 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -18,9 +18,12 @@ aliases { spi0 = &spi_0; + tmuctrl0 = &tmuctrl_0; + tmuctrl1 = &tmuctrl_1; + tmuctrl2 = &tmuctrl_2; }; - clock: clock-controller@0x160000 { + clock: clock-controller@160000 { compatible = "samsung,exynos5440-clock"; reg = <0x160000 0x1000>; #clock-cells = <1>; @@ -207,6 +210,30 @@ clock-names = "rtc"; }; + tmuctrl_0: tmuctrl@160118 { + compatible = "samsung,exynos5440-tmu"; + reg = <0x160118 0x230>, <0x160368 0x10>; + interrupts = <0 58 0>; + clocks = <&clock 21>; + clock-names = "tmu_apbif"; + }; + + tmuctrl_1: tmuctrl@16011C { + compatible = "samsung,exynos5440-tmu"; + reg = <0x16011C 0x230>, <0x160368 0x10>; + interrupts = <0 58 0>; + clocks = <&clock 21>; + clock-names = "tmu_apbif"; + }; + + tmuctrl_2: tmuctrl@160120 { + compatible = "samsung,exynos5440-tmu"; + reg = <0x160120 0x230>, <0x160368 0x10>; + interrupts = <0 58 0>; + clocks = <&clock 21>; + clock-names = "tmu_apbif"; + }; + sata@210000 { compatible = "snps,exynos5440-ahci"; reg = <0x210000 0x10000>; @@ -248,6 +275,7 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; + num-lanes = <4>; }; pcie@2a0000 { @@ -267,5 +295,6 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; + num-lanes = <4>; }; }; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index da0588a04131..185c7c01102a 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -90,6 +90,11 @@ }; apbx@80040000 { + lradc@80050000 { + status = "okay"; + fsl,lradc-touchscreen-wires = <4>; + }; + pwm: pwm@80064000 { pinctrl-names = "default"; pinctrl-0 = <&pwm2_pins_a>; @@ -107,6 +112,16 @@ pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index d107c4af321f..fc766ae12e24 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -69,6 +69,10 @@ }; apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + duart: serial@80070000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 587ceef81e45..28b5ce289662 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -20,6 +20,8 @@ gpio2 = &gpio2; serial0 = &auart0; serial1 = &auart1; + spi0 = &ssp0; + spi1 = &ssp1; }; cpus { @@ -76,23 +78,21 @@ #size-cells = <1>; reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <13>, <56>; - interrupt-names = "gpmi-dma", "bch"; + interrupts = <56>; + interrupt-names = "bch"; clocks = <&clks 34>; clock-names = "gpmi_io"; dmas = <&dma_apbh 4>; dma-names = "rx-tx"; - fsl,gpmi-dma-channel = <4>; status = "disabled"; }; ssp0: ssp@80010000 { reg = <0x80010000 0x2000>; - interrupts = <15 14>; + interrupts = <15>; clocks = <&clks 33>; dmas = <&dma_apbh 1>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -366,11 +366,10 @@ ssp1: ssp@80034000 { reg = <0x80034000 0x2000>; - interrupts = <2 20>; + interrupts = <2>; clocks = <&clks 33>; dmas = <&dma_apbh 2>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -472,7 +471,7 @@ auart0: serial@8006c000 { compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; + interrupts = <24>; clocks = <&clks 32>; dmas = <&dma_apbx 6>, <&dma_apbx 7>; dma-names = "rx", "tx"; @@ -482,7 +481,7 @@ auart1: serial@8006e000 { compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; - interrupts = <59 60 58>; + interrupts = <59>; clocks = <&clks 32>; dmas = <&dma_apbx 8>, <&dma_apbx 9>; dma-names = "rx", "tx"; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 701153992c69..737ed5da8f71 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -13,19 +13,35 @@ / { aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; usb0 = &usbotg; usb1 = &usbhost1; }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + asic: asic-interrupt-controller@68000000 { compatible = "fsl,imx25-asic", "fsl,avic"; interrupt-controller; @@ -377,7 +393,8 @@ status = "disabled"; }; - lcdc@53fbc000 { + lcdc: lcdc@53fbc000 { + compatible = "fsl,imx25-fb", "fsl,imx21-fb"; reg = <0x53fbc000 0x4000>; interrupts = <39>; clocks = <&clks 103>, <&clks 66>, <&clks 49>; @@ -424,6 +441,7 @@ reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; interrupts = <34>; }; @@ -444,6 +462,13 @@ interrupts = <26>; }; + iim: iim@53ff0000 { + compatible = "fsl,imx25-iim", "fsl,imx27-iim"; + reg = <0x53ff0000 0x4000>; + interrupts = <19>; + clocks = <&clks 99>; + }; + usbphy1: usbphy@1 { compatible = "nop-usbphy"; status = "disabled"; diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 66b8e1c1b0be..2a377ca1881a 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -53,6 +53,11 @@ &i2c1 { clock-frequency = <400000>; status = "okay"; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; }; &i2c2 { diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts new file mode 100644 index 000000000000..5a31c776513f --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2012 Markus Pargmann, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx27-phytec-phycard-s-som.dts" + +/ { + model = "Phytec pca100 rapid development kit"; + compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; + + display: display { + model = "Primeview-PD050VL1"; + native-mode = <&timing0>; + bits-per-pixel = <16>; /* non-standard but required */ + fsl,pcr = <0xf0c88080>; /* non-standard but required */ + display-timings { + timing0: 640x480 { + hactive = <640>; + vactive = <480>; + hback-porch = <112>; + hfront-porch = <36>; + hsync-len = <32>; + vback-porch = <33>; + vfront-porch = <33>; + vsync-len = <2>; + clock-frequency = <25000000>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3v3: 3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&fb { + display = <&display>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + adc@64 { + compatible = "maxim,max1037"; + vcc-supply = <®_3v3>; + reg = <0x64>; + }; +}; + +&owire { + status = "okay"; +}; + +&sdhci2 { + cd-gpios = <&gpio3 29 0>; + status = "okay"; +}; + +&uart1 { + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + fsl,uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts new file mode 100644 index 000000000000..c8d57d1d0743 --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar + * and Markus Pargmann, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pca100"; + compatible = "phytec,imx27-pca100", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x08000000>; /* 128MB */ + }; +}; + +&cspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 28 0>, + <&gpio4 27 0>; + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index e7ed9786920a..0fc6551786c6 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -35,3 +35,16 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&weim { + can@d4000000 { + compatible = "nxp,sja1000"; + reg = <4 0x00000000 0x00000100>; + interrupt-parent = <&gpio5>; + interrupts = <19 0x2>; + nxp,external-clock-frequency = <16000000>; + nxp,tx-output-config = <0x16>; + nxp,no-comparator-bypass; + fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>; + }; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts index f0105651869d..4ec402c38945 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts @@ -17,49 +17,22 @@ compatible = "phytec,imx27-pcm038", "fsl,imx27"; memory { - reg = <0x0 0x0>; + reg = <0xa0000000 0x08000000>; }; +}; - soc { - aipi@10000000 { /* aipi1 */ - serial@1000a000 { - status = "okay"; - }; - - i2c@1001d000 { - clock-frequency = <400000>; - status = "okay"; - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; - pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - lm75@4a { - compatible = "national,lm75"; - reg = <0x4a>; - }; - }; - }; +&audmux { + status = "okay"; - aipi@10020000 { /* aipi2 */ - ethernet@1002b000 { - phy-reset-gpios = <&gpio3 30 0>; - status = "okay"; - }; - }; + /* SSI0 <=> PINS_4 (MC13783 Audio) */ + ssi0 { + fsl,audmux-port = <0>; + fsl,port-config = <0xcb205000>; }; - nor_flash@c0000000 { - compatible = "cfi-flash"; - bank-width = <2>; - reg = <0xc0000000 0x02000000>; - linux,mtd-name = "physmap-flash.0"; - #address-cells = <1>; - #size-cells = <1>; + pins4 { + fsl,audmux-port = <2>; + fsl,port-config = <0x00001000>; }; }; @@ -80,28 +53,16 @@ fsl,mc13xxx-uses-rtc; regulators { - sw1a_reg: sw1a { + /* SW1A and SW1B joined operation */ + sw1_reg: sw1a { regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1520000>; regulator-always-on; regulator-boot-on; }; - sw1b_reg: sw1b { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2a_reg: sw2a { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sw2b_reg: sw2b { + /* SW2A and SW2B joined operation */ + sw2_reg: sw2a { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -172,8 +133,62 @@ }; }; +&fec { + phy-reset-gpios = <&gpio3 30 0>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + lm75@4a { + compatible = "national,lm75"; + reg = <0x4a>; + }; +}; + &nfc { nand-bus-width = <8>; nand-ecc-mode = "hw"; status = "okay"; }; + +&uart1 { + status = "okay"; +}; + +&weim { + status = "okay"; + + nor: nor@c0000000 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; + #address-cells = <1>; + #size-cells = <1>; + }; + + sram: sram@c8000000 { + compatible = "mtd-ram"; + reg = <1 0x00000000 0x00800000>; + bank-width = <2>; + linux,mtd-name = "mtd-ram.0"; + fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 0695264ddf1b..c037c223619a 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -13,25 +13,27 @@ / { aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; spi0 = &cspi1; spi1 = &cspi2; spi2 = &cspi3; }; - avic: avic-interrupt-controller@e0000000 { - compatible = "fsl,imx27-avic", "fsl,avic"; + aitc: aitc-interrupt-controller@e0000000 { + compatible = "fsl,imx27-aitc", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10040000 0x1000>; @@ -47,11 +49,29 @@ }; }; + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + operating-points = < + /* kHz uV */ + 266000 1300000 + 399000 1450000 + >; + clock-latency = <62500>; + clocks = <&clks 18>; + voltage-tolerance = <5>; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&avic>; + interrupt-parent = <&aitc>; ranges; aipi@10000000 { /* AIPI1 */ @@ -75,7 +95,7 @@ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; interrupts = <27>; - clocks = <&clks 0>; + clocks = <&clks 74>; }; gpt1: timer@10003000 { @@ -102,7 +122,7 @@ clock-names = "ipg", "per"; }; - pwm0: pwm@10006000 { + pwm: pwm@10006000 { compatible = "fsl,imx27-pwm"; reg = <0x10006000 0x1000>; interrupts = <23>; @@ -110,6 +130,21 @@ clock-names = "ipg", "per"; }; + kpp: kpp@10008000 { + compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; + reg = <0x10008000 0x1000>; + interrupts = <21>; + clocks = <&clks 37>; + status = "disabled"; + }; + + owire: owire@10009000 { + compatible = "fsl,imx27-owire", "fsl,imx21-owire"; + reg = <0x10009000 0x1000>; + clocks = <&clks 35>; + status = "disabled"; + }; + uart1: serial@1000a000 { compatible = "fsl,imx27-uart", "fsl,imx21-uart"; reg = <0x1000a000 0x1000>; @@ -260,6 +295,14 @@ #interrupt-cells = <2>; }; + audmux: audmux@10016000 { + compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; + reg = <0x10016000 0x1000>; + clocks = <&clks 0>; + clock-names = "audmux"; + status = "disabled"; + }; + cspi3: cspi@10017000 { #address-cells = <1>; #size-cells = <0>; @@ -342,6 +385,15 @@ reg = <0x10020000 0x20000>; ranges; + fb: fb@10021000 { + compatible = "fsl,imx27-fb", "fsl,imx21-fb"; + interrupts = <61>; + reg = <0x10021000 0x1000>; + clocks = <&clks 36>, <&clks 65>, <&clks 59>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + coda: coda@10023000 { compatible = "fsl,imx27-vpu"; reg = <0x10023000 0x0200>; @@ -351,27 +403,37 @@ iram = <&iram>; }; + sahara2: sahara@10025000 { + compatible = "fsl,imx27-sahara"; + reg = <0x10025000 0x1000>; + interrupts = <59>; + clocks = <&clks 32>, <&clks 64>; + clock-names = "ipg", "ahb"; + }; + clks: ccm@10027000{ compatible = "fsl,imx27-ccm"; reg = <0x10027000 0x1000>; #clock-cells = <1>; }; + iim: iim@10028000 { + compatible = "fsl,imx27-iim"; + reg = <0x10028000 0x1000>; + interrupts = <62>; + clocks = <&clks 38>; + }; + fec: ethernet@1002b000 { compatible = "fsl,imx27-fec"; reg = <0x1002b000 0x4000>; interrupts = <50>; - clocks = <&clks 48>, <&clks 67>, <&clks 0>; - clock-names = "ipg", "ahb", "ptp"; + clocks = <&clks 48>, <&clks 67>; + clock-names = "ipg", "ahb"; status = "disabled"; }; }; - iram: iram@ffff4c00 { - compatible = "mmio-sram"; - reg = <0xffff4c00 0xb400>; - }; - nfc: nand@d8000000 { #address-cells = <1>; #size-cells = <1>; @@ -381,5 +443,27 @@ clocks = <&clks 54>; status = "disabled"; }; + + weim: weim@d8002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx27-weim"; + reg = <0xd8002000 0x1000>; + clocks = <&clks 0>; + ranges = < + 0 0 0xc0000000 0x08000000 + 1 0 0xc8000000 0x08000000 + 2 0 0xd0000000 0x02000000 + 3 0 0xd2000000 0x02000000 + 4 0 0xd4000000 0x02000000 + 5 0 0xd6000000 0x02000000 + >; + status = "disabled"; + }; + + iram: iram@ffff4c00 { + compatible = "mmio-sram"; + reg = <0xffff4c00 0xb400>; + }; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 94c4476972c3..1ec8c94bbac9 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -23,10 +23,7 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_cfa10036>; - - hog_pins_cfa10036: hog-10036@0 { + ssd1306_cfa10036: ssd1306-10036@0 { reg = <0>; fsl,pinmux-ids = < 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ @@ -83,6 +80,8 @@ ssd1306: oled@3c { compatible = "solomon,ssd1306fb-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1306_cfa10036>; reg = <0x3c>; reset-gpios = <&gpio2 7 0>; solomon,height = <32>; diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index c2ef3a3d655e..182b99fe35f3 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts @@ -22,13 +22,19 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { - pinctrl-names = "default", "default"; - pinctrl-1 = <&hog_pins_cfa10037>; - - hog_pins_cfa10037: hog-10037@0 { + usb_pins_cfa10037: usb-10037@0 { reg = <0>; fsl,pinmux-ids = < 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mac0_pins_cfa10037: mac0-10037@0 { + reg = <0>; + fsl,pinmux-ids = < 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ >; fsl,drive-strength = <0>; @@ -56,7 +62,8 @@ mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; + pinctrl-0 = <&mac0_pins_a + &mac0_pins_cfa10037>; phy-reset-gpios = <&gpio2 21 0>; phy-reset-duration = <100>; status = "okay"; @@ -68,6 +75,8 @@ reg_usb1_vbus: usb1_vbus { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10037>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 04b2f769ffbd..06e4cfaf7dd2 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -22,32 +22,62 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { - pinctrl-names = "default", "default"; - pinctrl-1 = <&hog_pins_cfa10049 - &hog_pins_cfa10049_pullup>; - - hog_pins_cfa10049: hog-10049@0 { + usb_pins_cfa10049: usb-10049@0 { reg = <0>; fsl,pinmux-ids = < 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + i2cmux_pins_cfa10049: i2cmux-10049@0 { + reg = <0>; + fsl,pinmux-ids = < 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mac0_pins_cfa10049: mac0-10049@0 { + reg = <0>; + fsl,pinmux-ids = < 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; }; - hog_pins_cfa10049_pullup: hog-10049-pullup@0 { + pca_pins_cfa10049: pca-10049@0 { reg = <0>; fsl,pinmux-ids = < 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + rotary_pins_cfa10049: rotary-10049@0 { + reg = <0>; + fsl,pinmux-ids = < 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + rotary_btn_pins_cfa10049: rotary-btn-10049@0 { + reg = <0>; + fsl,pinmux-ids = < 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -60,6 +90,7 @@ 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -120,6 +151,16 @@ fsl,pull-up = <0>; }; + lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + w1_gpio_pins: w1-gpio@0 { reg = <0>; fsl,pinmux-ids = < @@ -134,7 +175,8 @@ lcdif@80030000 { pinctrl-names = "default"; pinctrl-0 = <&lcdif_18bit_pins_cfa10049 - &lcdif_pins_cfa10049>; + &lcdif_pins_cfa10049 + &lcdif_pins_cfa10049_pullup>; display = <&display>; status = "okay"; @@ -181,6 +223,8 @@ compatible = "i2c-mux-gpio"; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2cmux_pins_cfa10049>; mux-gpios = <&gpio1 22 0 &gpio1 23 0>; i2c-parent = <&i2c1>; @@ -203,6 +247,8 @@ pca9555: pca9555@20 { compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca_pins_cfa10049>; interrupt-parent = <&gpio2>; interrupts = <19 0x2>; gpio-controller; @@ -239,6 +285,8 @@ reg_usb1_vbus: usb1_vbus { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10049>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -250,7 +298,8 @@ mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; + pinctrl-0 = <&mac0_pins_a + &mac0_pins_cfa10049>; phy-reset-gpios = <&gpio2 21 0>; phy-reset-duration = <100>; status = "okay"; @@ -320,6 +369,8 @@ gpio_keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_btn_pins_cfa10049>; #address-cells = <1>; #size-cells = <0>; @@ -333,6 +384,8 @@ rotary { compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_pins_cfa10049>; gpios = <&gpio3 24 1>, <&gpio3 25 1>; linux,axis = <1>; /* REL_Y */ rotary-encoder,relative-axis; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index 158111244122..171bcbe1ec4b 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -23,36 +23,13 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { - pinctrl-names = "default", "default"; - pinctrl-1 = <&hog_pins_cfa10055 - &hog_pins_cfa10055_pullup>; - - hog_pins_cfa10055: hog-10055@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - hog_pins_cfa10055_pullup: hog-10055-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - spi2_pins_cfa10055: spi2-cfa10055@0 { reg = <0>; fsl,pinmux-ids = < 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -98,12 +75,23 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; }; lcdif@80030000 { pinctrl-names = "default"; pinctrl-0 = <&lcdif_18bit_pins_cfa10055 - &lcdif_pins_cfa10055>; + &lcdif_pins_cfa10055 + &lcdif_pins_cfa10055_pullup>; display = <&display>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts new file mode 100644 index 000000000000..b45dd0e4ee57 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2013 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10055 is an expansion board for the CFA-10036 module and + * CFA-10037, thus we need to include the CFA-10037 DTS. + */ +/include/ "imx28-cfa10037.dts" + +/ { + model = "Crystalfontz CFA-10056 Board"; + compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + spi2_pins_cfa10056: spi2-cfa10056@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ + 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ + 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + lcdif_pins_cfa10056: lcdif-10056@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10056 + &lcdif_pins_cfa10056_pullup >; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <32000000>; + hactive = <480>; + vactive = <800>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <5>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; + }; + }; + + spi2 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_cfa10056>; + status = "okay"; + gpio-sck = <&gpio2 16 0>; + gpio-mosi = <&gpio2 17 0>; + gpio-miso = <&gpio2 18 0>; + cs-gpios = <&gpio3 5 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hx8369: hx8369@0 { + compatible = "himax,hx8369a", "himax,hx8369"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + gpios-reset = <&gpio3 30 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 2da713cdb42a..0333c0532f28 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -23,35 +23,16 @@ apb@80000000 { apbh@80000000 { pinctrl@80018000 { - pinctrl-names = "default", "default"; - pinctrl-1 = <&hog_pins_cfa10057 - &hog_pins_cfa10057_pullup>; - - hog_pins_cfa10057: hog-10057@0 { + usb_pins_cfa10057: usb-10057@0 { reg = <0>; fsl,pinmux-ids = < 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ - 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; }; - hog_pins_cfa10057_pullup: hog-10057-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ - 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ - 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ - 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ - 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -164,6 +145,8 @@ reg_usb1_vbus: usb1_vbus { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10057>; regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts new file mode 100644 index 000000000000..64c64c55a82a --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Crystalfontz America, Inc. + * Copyright 2013 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10058 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +/include/ "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10058 Board"; + compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + usb_pins_cfa10058: usb-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_cfa10058: lcdif-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10058>; + display = <&display>; + status = "okay"; + + display: display { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <13>; + vfront-porch = <29>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; + }; + + apbx@80040000 { + lradc@80050000 { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb1_vbus: usb1_vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10058>; + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 0>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index e035f4664b97..15715d921d14 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -220,6 +220,7 @@ auart0: serial@8006a000 { pinctrl-names = "default"; pinctrl-0 = <&auart0_pins_a>; + fsl,uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 44d9da57736e..0d322a2bebaf 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -235,6 +235,12 @@ pinctrl-0 = <&auart2_2pins_b>; status = "okay"; }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; + }; }; }; @@ -270,6 +276,13 @@ }; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 4 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 9524a0571281..7363fded95ee 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -15,6 +15,8 @@ interrupt-parent = <&icoll>; aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -27,8 +29,8 @@ serial2 = &auart2; serial3 = &auart3; serial4 = &auart4; - ethernet0 = &mac0; - ethernet1 = &mac1; + spi0 = &ssp1; + spi1 = &ssp2; }; cpus { @@ -62,9 +64,9 @@ reg = <0x80000000 0x2000>; }; - hsadc@80002000 { + hsadc: hsadc@80002000 { reg = <0x80002000 0x2000>; - interrupts = <13 87>; + interrupts = <13>; dmas = <&dma_apbh 12>; dma-names = "rx"; status = "disabled"; @@ -86,25 +88,24 @@ clocks = <&clks 25>; }; - perfmon@80006000 { + perfmon: perfmon@80006000 { reg = <0x80006000 0x800>; interrupts = <27>; status = "disabled"; }; - gpmi-nand@8000c000 { + gpmi: gpmi-nand@8000c000 { compatible = "fsl,imx28-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <88>, <41>; - interrupt-names = "gpmi-dma", "bch"; + interrupts = <41>; + interrupt-names = "bch"; clocks = <&clks 50>; clock-names = "gpmi_io"; dmas = <&dma_apbh 4>; dma-names = "rx-tx"; - fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -112,11 +113,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80010000 0x2000>; - interrupts = <96 82>; + interrupts = <96>; clocks = <&clks 46>; dmas = <&dma_apbh 0>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <0>; status = "disabled"; }; @@ -124,11 +124,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80012000 0x2000>; - interrupts = <97 83>; + interrupts = <97>; clocks = <&clks 47>; dmas = <&dma_apbh 1>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -136,11 +135,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80014000 0x2000>; - interrupts = <98 84>; + interrupts = <98>; clocks = <&clks 48>; dmas = <&dma_apbh 2>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -148,15 +146,14 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80016000 0x2000>; - interrupts = <99 85>; + interrupts = <99>; clocks = <&clks 49>; dmas = <&dma_apbh 3>; dma-names = "rx-tx"; - fsl,ssp-dma-channel = <3>; status = "disabled"; }; - pinctrl@80018000 { + pinctrl: pinctrl@80018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx28-pinctrl", "simple-bus"; @@ -521,6 +518,18 @@ fsl,pull-up = <1>; }; + saif0_pins_b: saif0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + saif1_pins_a: saif1@0 { reg = <0>; fsl,pinmux-ids = < @@ -639,6 +648,19 @@ fsl,pull-up = <0>; }; + lcdif_sync_pins_a: lcdif-sync@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + can0_pins_a: can0@0 { reg = <0>; fsl,pinmux-ids = < @@ -674,6 +696,21 @@ fsl,pull-up = <1>; }; + spi3_pins_a: spi3@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */ + 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */ + 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */ + 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */ + 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */ + 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + usbphy0_pins_a: usbphy0@0 { reg = <0>; fsl,pinmux-ids = < @@ -705,14 +742,14 @@ }; }; - digctl@8001c000 { + digctl: digctl@8001c000 { compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; reg = <0x8001c000 0x2000>; interrupts = <89>; status = "disabled"; }; - etm@80022000 { + etm: etm@80022000 { reg = <0x80022000 0x2000>; status = "disabled"; }; @@ -733,19 +770,19 @@ clocks = <&clks 26>; }; - dcp@80028000 { + dcp: dcp@80028000 { reg = <0x80028000 0x2000>; interrupts = <52 53 54>; compatible = "fsl-dcp"; }; - pxp@8002a000 { + pxp: pxp@8002a000 { reg = <0x8002a000 0x2000>; interrupts = <39>; status = "disabled"; }; - ocotp@8002c000 { + ocotp: ocotp@8002c000 { compatible = "fsl,ocotp"; reg = <0x8002c000 0x2000>; status = "disabled"; @@ -756,10 +793,10 @@ status = "disabled"; }; - lcdif@80030000 { + lcdif: lcdif@80030000 { compatible = "fsl,imx28-lcdif"; reg = <0x80030000 0x2000>; - interrupts = <38 86>; + interrupts = <38>; clocks = <&clks 55>; dmas = <&dma_apbh 13>; dma-names = "rx"; @@ -784,41 +821,41 @@ status = "disabled"; }; - simdbg@8003c000 { + simdbg: simdbg@8003c000 { reg = <0x8003c000 0x200>; status = "disabled"; }; - simgpmisel@8003c200 { + simgpmisel: simgpmisel@8003c200 { reg = <0x8003c200 0x100>; status = "disabled"; }; - simsspsel@8003c300 { + simsspsel: simsspsel@8003c300 { reg = <0x8003c300 0x100>; status = "disabled"; }; - simmemsel@8003c400 { + simmemsel: simmemsel@8003c400 { reg = <0x8003c400 0x100>; status = "disabled"; }; - gpiomon@8003c500 { + gpiomon: gpiomon@8003c500 { reg = <0x8003c500 0x100>; status = "disabled"; }; - simenet@8003c700 { + simenet: simenet@8003c700 { reg = <0x8003c700 0x100>; status = "disabled"; }; - armjtag@8003c800 { + armjtag: armjtag@8003c800 { reg = <0x8003c800 0x100>; status = "disabled"; }; - }; + }; apbx@80040000 { compatible = "simple-bus"; @@ -836,16 +873,15 @@ saif0: saif@80042000 { compatible = "fsl,imx28-saif"; reg = <0x80042000 0x2000>; - interrupts = <59 80>; + interrupts = <59>; #clock-cells = <0>; clocks = <&clks 53>; dmas = <&dma_apbx 4>; dma-names = "rx-tx"; - fsl,saif-dma-channel = <4>; status = "disabled"; }; - power@80044000 { + power: power@80044000 { reg = <0x80044000 0x2000>; status = "disabled"; }; @@ -853,15 +889,14 @@ saif1: saif@80046000 { compatible = "fsl,imx28-saif"; reg = <0x80046000 0x2000>; - interrupts = <58 81>; + interrupts = <58>; clocks = <&clks 54>; dmas = <&dma_apbx 5>; dma-names = "rx-tx"; - fsl,saif-dma-channel = <5>; status = "disabled"; }; - lradc@80050000 { + lradc: lradc@80050000 { compatible = "fsl,imx28-lradc"; reg = <0x80050000 0x2000>; interrupts = <10 14 15 16 17 18 19 @@ -869,15 +904,15 @@ status = "disabled"; }; - spdif@80054000 { + spdif: spdif@80054000 { reg = <0x80054000 0x2000>; - interrupts = <45 66>; + interrupts = <45>; dmas = <&dma_apbx 2>; dma-names = "tx"; status = "disabled"; }; - rtc@80056000 { + mxs_rtc: rtc@80056000 { compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; reg = <0x80056000 0x2000>; interrupts = <29>; @@ -888,11 +923,10 @@ #size-cells = <0>; compatible = "fsl,imx28-i2c"; reg = <0x80058000 0x2000>; - interrupts = <111 68>; + interrupts = <111>; clock-frequency = <100000>; dmas = <&dma_apbx 6>; dma-names = "rx-tx"; - fsl,i2c-dma-channel = <6>; status = "disabled"; }; @@ -901,11 +935,10 @@ #size-cells = <0>; compatible = "fsl,imx28-i2c"; reg = <0x8005a000 0x2000>; - interrupts = <110 69>; + interrupts = <110>; clock-frequency = <100000>; dmas = <&dma_apbx 7>; dma-names = "rx-tx"; - fsl,i2c-dma-channel = <7>; status = "disabled"; }; @@ -918,7 +951,7 @@ status = "disabled"; }; - timrot@80068000 { + timer: timrot@80068000 { compatible = "fsl,imx28-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; interrupts = <48 49 50 51>; @@ -928,10 +961,9 @@ auart0: serial@8006a000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; + interrupts = <112>; dmas = <&dma_apbx 8>, <&dma_apbx 9>; dma-names = "rx", "tx"; - fsl,auart-dma-channel = <8 9>; clocks = <&clks 45>; status = "disabled"; }; @@ -939,7 +971,7 @@ auart1: serial@8006c000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; - interrupts = <113 72 73>; + interrupts = <113>; dmas = <&dma_apbx 10>, <&dma_apbx 11>; dma-names = "rx", "tx"; clocks = <&clks 45>; @@ -949,7 +981,7 @@ auart2: serial@8006e000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; - interrupts = <114 74 75>; + interrupts = <114>; dmas = <&dma_apbx 12>, <&dma_apbx 13>; dma-names = "rx", "tx"; clocks = <&clks 45>; @@ -959,7 +991,7 @@ auart3: serial@80070000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; - interrupts = <115 76 77>; + interrupts = <115>; dmas = <&dma_apbx 14>, <&dma_apbx 15>; dma-names = "rx", "tx"; clocks = <&clks 45>; @@ -969,7 +1001,7 @@ auart4: serial@80072000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; - interrupts = <116 78 79>; + interrupts = <116>; dmas = <&dma_apbx 0>, <&dma_apbx 1>; dma-names = "rx", "tx"; clocks = <&clks 45>; @@ -1026,7 +1058,7 @@ status = "disabled"; }; - dflpt@800c0000 { + dflpt: dflpt@800c0000 { reg = <0x800c0000 0x10000>; status = "disabled"; }; @@ -1049,10 +1081,9 @@ status = "disabled"; }; - switch@800f8000 { + etn_switch: switch@800f8000 { reg = <0x800f8000 0x8000>; status = "disabled"; }; - }; }; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index c5449257ad9a..c34f82581248 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -20,6 +20,16 @@ serial4 = &uart5; }; + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm1136"; + device_type = "cpu"; + }; + }; + avic: avic-interrupt-controller@60000000 { compatible = "fsl,imx31-avic", "fsl,avic"; interrupt-controller; @@ -94,6 +104,13 @@ status = "disabled"; }; + iim: iim@5001c000 { + compatible = "fsl,imx31-iim", "fsl,imx27-iim"; + reg = <0x5001c000 0x1000>; + interrupts = <19>; + clocks = <&clks 25>; + }; + clks: ccm@53f80000{ compatible = "fsl,imx31-ccm"; reg = <0x53f80000 0x4000>; diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 8f7f9ac0b989..b3606993f2e8 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts @@ -26,10 +26,6 @@ }; clocks { - ckih1 { - clock-frequency = <0>; - }; - osc { clock-frequency = <33554432>; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ad3471ca17c7..1d337d99ecd5 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -63,6 +63,10 @@ }; clocks { + ckih1 { + clock-frequency = <22579200>; + }; + clk_26M: codec_clock { compatible = "fixed-clock"; reg=<0>; @@ -108,6 +112,7 @@ #size-cells = <0>; compatible = "fsl,mc13892"; spi-max-frequency = <6000000>; + spi-cs-high; reg = <0>; interrupt-parent = <&gpio1>; interrupts = <8 0x4>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 25764b505a61..a85abb424c34 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -15,13 +15,18 @@ / { aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; + i2c0 = &i2c1; + i2c1 = &i2c2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; }; tzic: tz-interrupt-controller@e0000000 { @@ -42,7 +47,7 @@ ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; - clock-frequency = <22579200>; + clock-frequency = <0>; }; ckih2 { @@ -149,6 +154,9 @@ reg = <0x70014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -300,275 +308,6 @@ iomuxc: iomuxc@73fa8000 { compatible = "fsl,imx51-iomuxc"; reg = <0x73fa8000 0x4000>; - - audmux { - pinctrl_audmux_1: audmuxgrp-1 { - fsl,pins = < - MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 - MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 - MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 - MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 - >; - }; - }; - - fec { - pinctrl_fec_1: fecgrp-1 { - fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 - MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 - MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 - MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 - >; - }; - - pinctrl_fec_2: fecgrp-2 { - fsl,pins = < - MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 - MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 - MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 - MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 - MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 - MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 - MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 - MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 - MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 - MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 - MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 - MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 - MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 - MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 - MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 - MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 - MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 - >; - }; - }; - - ecspi2 { - pinctrl_ecspi2_1: ecspi2grp-1 { - fsl,pins = < - MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 - MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 - MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 - >; - }; - }; - - esdhc1 { - pinctrl_esdhc1_1: esdhc1grp-1 { - fsl,pins = < - MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 - MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 - MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 - MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 - MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 - MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 - >; - }; - }; - - esdhc2 { - pinctrl_esdhc2_1: esdhc2grp-1 { - fsl,pins = < - MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 - MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 - MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 - MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 - MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 - MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 - >; - }; - }; - - i2c2 { - pinctrl_i2c2_1: i2c2grp-1 { - fsl,pins = < - MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed - MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed - >; - }; - - pinctrl_i2c2_2: i2c2grp-2 { - fsl,pins = < - MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed - MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed - >; - }; - }; - - ipu_disp1 { - pinctrl_ipu_disp1_1: ipudisp1grp-1 { - fsl,pins = < - MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 - MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 - MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 - MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 - MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 - MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 - MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 - MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 - MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 - MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 - MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 - MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 - MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 - MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 - MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 - MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 - MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 - MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 - MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 - MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 - MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 - MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 - MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 - MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 - MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ - MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ - >; - }; - }; - - ipu_disp2 { - pinctrl_ipu_disp2_1: ipudisp2grp-1 { - fsl,pins = < - MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 - MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 - MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 - MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 - MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 - MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 - MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 - MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 - MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 - MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 - MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 - MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 - MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 - MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 - MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 - MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 - MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ - MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 - MX51_PAD_DI_GP4__DI2_PIN15 0x5 - >; - }; - }; - - pata { - pinctrl_pata_1: patagrp-1 { - fsl,pins = < - MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 - MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 - MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 - MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 - MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 - MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 - MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 - MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 - MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 - MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 - MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 - MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 - MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 - MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 - MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 - MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 - MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 - MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 - MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 - MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 - MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 - MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 - MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 - MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 - MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 - MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 - MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 - MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 - MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 - MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 - >; - }; - }; - - uart2 { - pinctrl_uart2_1: uart2grp-1 { - fsl,pins = < - MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 - MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 - >; - }; - }; - - uart3 { - pinctrl_uart3_1: uart3grp-1 { - fsl,pins = < - MX51_PAD_EIM_D25__UART3_RXD 0x1c5 - MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - MX51_PAD_EIM_D27__UART3_RTS 0x1c5 - MX51_PAD_EIM_D24__UART3_CTS 0x1c5 - >; - }; - - pinctrl_uart3_2: uart3grp-2 { - fsl,pins = < - MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 - MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 - >; - }; - }; - - kpp { - pinctrl_kpp_1: kppgrp-1 { - fsl,pins = < - MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 - MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 - MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 - MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 - MX51_PAD_KEY_COL0__KEY_COL0 0xe8 - MX51_PAD_KEY_COL1__KEY_COL1 0xe8 - MX51_PAD_KEY_COL2__KEY_COL2 0xe8 - MX51_PAD_KEY_COL3__KEY_COL3 0xe8 - >; - }; - }; }; pwm1: pwm@73fb4000 { @@ -628,6 +367,13 @@ reg = <0x80000000 0x10000000>; ranges; + iim: iim@83f98000 { + compatible = "fsl,imx51-iim", "fsl,imx27-iim"; + reg = <0x83f98000 0x4000>; + interrupts = <69>; + clocks = <&clks 107>; + }; + ecspi2: ecspi@83fac000 { #address-cells = <1>; #size-cells = <0>; @@ -645,6 +391,7 @@ interrupts = <6>; clocks = <&clks 56>, <&clks 56>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; @@ -684,6 +431,9 @@ reg = <0x83fcc000 0x4000>; interrupts = <29>; clocks = <&clks 48>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -695,6 +445,23 @@ status = "disabled"; }; + weim: weim@83fda000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx51-weim"; + reg = <0x83fda000 0x1000>; + clocks = <&clks 57>; + ranges = < + 0 0 0xb0000000 0x08000000 + 1 0 0xb8000000 0x08000000 + 2 0 0xc0000000 0x08000000 + 3 0 0xc8000000 0x04000000 + 4 0 0xcc000000 0x02000000 + 5 0 0xce000000 0x02000000 + >; + status = "disabled"; + }; + nfc: nand@83fdb000 { compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; @@ -716,6 +483,9 @@ reg = <0x83fe8000 0x4000>; interrupts = <96>; clocks = <&clks 50>; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -732,3 +502,319 @@ }; }; }; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 + MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 + MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 + MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 + MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 + MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 + MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 + >; + }; + + pinctrl_fec_2: fecgrp-2 { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + >; + }; + }; + + ecspi2 { + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 + MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 + MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_i2c2_2: i2c2grp-2 { + fsl,pins = < + MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed + MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_i2c2_3: i2c2grp-3 { + fsl,pins = < + MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed + MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed + >; + }; + }; + + ipu_disp1 { + pinctrl_ipu_disp1_1: ipudisp1grp-1 { + fsl,pins = < + MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 + MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 + MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 + MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 + MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 + MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 + MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 + MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 + MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 + MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 + MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 + MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 + MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 + MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 + MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 + MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 + MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 + MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 + MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 + MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 + MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 + MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 + MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 + MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 + MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ + MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ + >; + }; + }; + + ipu_disp2 { + pinctrl_ipu_disp2_1: ipudisp2grp-1 { + fsl,pins = < + MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 + MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 + MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 + MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 + MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 + MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 + MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 + MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 + MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 + MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 + MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 + MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 + MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 + MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 + MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 + MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 + MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ + MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ + MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ + MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ + >; + }; + }; + + kpp { + pinctrl_kpp_1: kppgrp-1 { + fsl,pins = < + MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 + MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 + MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 + MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 + MX51_PAD_KEY_COL0__KEY_COL0 0xe8 + MX51_PAD_KEY_COL1__KEY_COL1 0xe8 + MX51_PAD_KEY_COL2__KEY_COL2 0xe8 + MX51_PAD_KEY_COL3__KEY_COL3 0xe8 + >; + }; + }; + + pata { + pinctrl_pata_1: patagrp-1 { + fsl,pins = < + MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 + MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 + MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 + MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 + MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 + MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 + MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 + MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 + MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 + MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 + MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 + MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 + MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 + MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 + MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 + MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 + MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 + MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 + MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 + MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 + MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 + MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 + MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 + MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 + MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 + MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 + MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 + MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX51_PAD_EIM_D25__UART3_RXD 0x1c5 + MX51_PAD_EIM_D26__UART3_TXD 0x1c5 + MX51_PAD_EIM_D27__UART3_RTS 0x1c5 + MX51_PAD_EIM_D24__UART3_CTS 0x1c5 + >; + }; + + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + }; + + usbh1 { + pinctrl_usbh1_1: usbh1grp-1 { + fsl,pins = < + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + }; + + usbh2 { + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 + MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 + MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 + MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 + MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 + MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 + MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 + MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 + MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 + MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 + MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 + MX51_PAD_EIM_A26__USBH2_STP 0x1e5 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 512a1f608253..e97ddae09d74 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -93,6 +93,15 @@ regulator-max-microvolt = <3200000>; regulator-always-on; }; + + reg_usb_vbus: usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 0>; + enable-active-high; + }; }; sound { @@ -145,6 +154,7 @@ MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 >; }; @@ -297,8 +307,14 @@ status = "okay"; }; +&vpu { + status = "okay"; +}; + &usbh1 { - status = "okay"; + vbus-supply = <®_usb_vbus>; + phy_type = "utmi"; + status = "okay"; }; &usbotg { diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 569aa9f2c4ed..4307e80b2d2e 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -15,11 +15,6 @@ / { aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -30,6 +25,24 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; }; tzic: tz-interrupt-controller@0fffc000 { @@ -140,6 +153,9 @@ reg = <0x50014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -957,6 +973,13 @@ reg = <0x60000000 0x10000000>; ranges; + iim: iim@63f98000 { + compatible = "fsl,imx53-iim", "fsl,imx27-iim"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks 107>; + }; + uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; @@ -990,6 +1013,7 @@ interrupts = <6>; clocks = <&clks 56>, <&clks 56>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; @@ -1029,6 +1053,9 @@ reg = <0x63fcc000 0x4000>; interrupts = <29>; clocks = <&clks 48>; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -1053,6 +1080,9 @@ reg = <0x63fe8000 0x4000>; interrupts = <96>; clocks = <&clks 50>; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; @@ -1076,6 +1106,22 @@ crtcs = <&ipu 1>; status = "disabled"; }; + + vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks 63>, <&clks 63>; + clock-names = "per", "ahb"; + iram = <&ocram>; + status = "disabled"; + }; + }; + + ocram: sram@f8000000 { + compatible = "mmio-sram"; + reg = <0xf8000000 0x20000>; + clocks = <&clks 186>; }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index 9aab950ec269..b81a7a4ebab6 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h @@ -14,1072 +14,1076 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 -#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 -#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 -#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 -#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 -#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 -#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 -#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 -#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 -#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 -#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 -#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 -#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 -#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 -#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 -#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 -#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 -#define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 -#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 -#define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 -#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 -#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 -#define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 -#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 -#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 -#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 -#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 -#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 -#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 -#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 -#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 -#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 -#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 -#define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 -#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 -#define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 -#define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 -#define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 -#define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 -#define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 -#define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 -#define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 -#define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 -#define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 -#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 -#define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 -#define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 -#define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 -#define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 -#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 -#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 -#define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 -#define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 -#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 -#define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 -#define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 -#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 -#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 -#define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 -#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 -#define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 -#define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 -#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 -#define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 -#define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 -#define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 -#define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 -#define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 -#define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 -#define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 -#define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 -#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 -#define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 -#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 -#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 -#define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 -#define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 -#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 -#define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 -#define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 -#define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 -#define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 -#define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 -#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 -#define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 -#define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 -#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 -#define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 -#define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 -#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 -#define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 -#define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 -#define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 -#define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 -#define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 -#define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 -#define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 -#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 -#define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 -#define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 -#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 -#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 -#define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 -#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 -#define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 -#define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 -#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 -#define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 -#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 -#define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 -#define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 -#define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 -#define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 -#define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 -#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 -#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 -#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 -#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 -#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 -#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 -#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 -#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 -#define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 -#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 -#define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 -#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 -#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 -#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 -#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 -#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 -#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 -#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 -#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 -#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 -#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 -#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 -#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 -#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 -#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 -#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 -#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 -#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 -#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 -#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 -#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 -#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 -#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 -#define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 -#define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 -#define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 -#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 -#define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 -#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 -#define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 -#define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 -#define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 -#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 -#define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 -#define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 -#define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 -#define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 -#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 -#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 -#define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 -#define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 -#define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 -#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 -#define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 -#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 -#define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 -#define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 -#define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 -#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 -#define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 -#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 -#define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 -#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 -#define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 -#define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 -#define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 -#define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 -#define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 -#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 -#define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 -#define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 -#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 -#define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 -#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 -#define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 -#define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 -#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 -#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 -#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 -#define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 -#define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 -#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 -#define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 -#define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 -#define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 -#define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 -#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 -#define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 -#define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 -#define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 -#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 -#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 -#define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 -#define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 -#define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 -#define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 -#define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 -#define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 -#define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 -#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 -#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 -#define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 -#define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 -#define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 -#define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 -#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 -#define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 -#define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 -#define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 -#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 -#define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 -#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 -#define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 -#define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 -#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 -#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 -#define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 -#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 -#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 -#define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 -#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 -#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 -#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 -#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 -#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 -#define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 -#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 -#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 -#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 -#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 -#define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 -#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 -#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 -#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 -#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 -#define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 -#define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 -#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 -#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 -#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 -#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 -#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 -#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 -#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 -#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 -#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 -#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 -#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 -#define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 -#define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 -#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 -#define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 -#define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 -#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 -#define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 -#define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 -#define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 -#define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 -#define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 -#define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 -#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 -#define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 -#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 -#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 -#define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 -#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 -#define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 -#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 -#define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 -#define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 -#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 -#define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 -#define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 -#define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 -#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 -#define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 -#define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 -#define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 -#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 -#define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 -#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 -#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 -#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 -#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 -#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 -#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 -#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 -#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 -#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 -#define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 -#define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 -#define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 -#define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 -#define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 -#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 -#define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 -#define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 -#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 -#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 -#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 -#define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 -#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 -#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 -#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 +#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 +#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 +#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 +#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 +#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 +#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 +#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 +#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 +#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 +#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 +#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 +#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 +#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 +#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 +#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 +#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 +#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 +#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 +#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 +#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 +#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 +#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 +#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 +#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 +#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 +#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 +#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 +#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 +#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 +#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 +#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 +#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 +#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 +#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 +#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 +#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 +#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 +#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 +#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 +#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 +#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 +#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 +#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 +#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 +#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 +#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 +#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 +#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 +#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 +#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 +#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 +#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 +#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 +#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 +#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 +#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 +#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 +#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 +#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 +#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 +#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 +#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 +#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 +#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 +#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 +#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 +#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 +#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 +#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 +#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 +#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 +#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 +#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 +#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 +#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 +#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 +#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 +#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 +#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 +#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 +#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 +#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 +#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 +#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 +#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 +#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 +#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 +#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 +#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 +#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 +#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 +#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 +#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 +#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 +#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 +#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 +#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 +#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 +#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 +#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 +#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 +#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 +#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 +#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 +#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 +#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 +#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 +#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 +#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 +#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 +#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 +#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 +#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 +#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 +#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 +#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 +#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 +#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 +#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 +#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 +#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 +#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 +#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 +#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 +#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 +#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 +#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 +#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 +#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 +#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 +#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 +#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 +#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 +#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 +#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 +#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 +#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 +#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 +#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 +#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 +#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 +#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 +#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 +#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 +#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 +#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 +#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 +#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 +#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 +#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 +#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 +#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 +#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 +#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 +#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 +#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 +#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 +#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 +#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 +#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 +#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 #endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 95da71185a4a..a6ce7b487ad7 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -15,25 +15,3 @@ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 - MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { - fsl,pins = < - MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 8989df2b89e5..1e45f2f9d0b6 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts @@ -15,22 +15,3 @@ model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000 - MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 - MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 - MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 - MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts index bfc59c3566a4..e672891c1626 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard.dts @@ -10,6 +10,7 @@ */ /dts-v1/; #include "imx6dl.dtsi" +#include "imx6qdl-wandboard.dtsi" / { model = "Wandboard i.MX6 Dual Lite Board"; @@ -19,26 +20,3 @@ reg = <0x10000000 0x40000000>; }; }; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 2b3ecd679350..9e8ae118fdd4 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -8,8 +8,8 @@ * */ -#include "imx6qdl.dtsi" #include "imx6dl-pinfunc.h" +#include "imx6qdl.dtsi" / { cpus { @@ -32,238 +32,15 @@ }; soc { + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks 142>; + }; + aips1: aips-bus@02000000 { iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6dl-iomuxc"; - reg = <0x020e0000 0x4000>; - - audmux { - pinctrl_audmux_2: audmux-2 { - fsl,pins = < - MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 - MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 - MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 - MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - }; - - enet { - pinctrl_enet_1: enetgrp-1 { - fsl,pins = < - MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_enet_2: enetgrp-2 { - fsl,pins = < - MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - }; - - gpmi-nand { - pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = < - MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - }; - - i2c1 { - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - }; - - uart4 { - pinctrl_uart4_1: uart4grp-1 { - fsl,pins = < - MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - }; - - usbotg { - pinctrl_usbotg_2: usbotggrp-2 { - fsl,pins = < - MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - }; - - usdhc2 { - pinctrl_usdhc2_1: usdhc2grp-1 { - fsl,pins = < - MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - }; - - usdhc3 { - pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = < - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_2: usdhc3grp_2 { - fsl,pins = < - MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; - - weim { - pinctrl_weim_cs0_1: weim_cs0grp-1 { - fsl,pins = < - MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor_1: weim_norgrp-1 { - fsl,pins = < - MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - /* data */ - MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* address */ - MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - }; - }; pxp: pxp@020f0000 { @@ -294,3 +71,20 @@ }; }; }; + +&ldb { + clocks = <&clks 33>, <&clks 34>, + <&clks 39>, <&clks 40>, + <&clks 135>, <&clks 136>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + + lvds-channel@0 { + crtcs = <&ipu1 0>, <&ipu1 1>; + }; + + lvds-channel@1 { + crtcs = <&ipu1 0>, <&ipu1 1>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 4e54fde591bd..edf1bd967164 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -57,7 +57,7 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 >; }; }; @@ -65,8 +65,8 @@ arm2 { pinctrl_usdhc3_arm2: usdhc3grp-arm2 { fsl,pins = < - MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 - MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 >; }; }; @@ -97,6 +97,14 @@ status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index f5e1981025ed..1a3b50d4d8fa 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -20,6 +20,110 @@ }; }; +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_1>; + status = "okay"; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 0>; + + flash@0 { + compatible = "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + pmic@58 { + compatible = "dialog,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio4>; + interrupts = <17 0x8>; /* active-low GPIO4_17 */ + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_buckmem_reg: bmem { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_eth_reg: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_eth_io_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_3v3_pmic_io_reg: ldo6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd0_reg: ldo9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd1_reg: ldo10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_mx6_high_reg: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -27,7 +131,9 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ >; }; }; @@ -35,8 +141,8 @@ pfla02 { pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { fsl,pins = < - MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 >; }; }; diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index faea6e1ada00..c0e38a45e4bb 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -14,1028 +14,1032 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 -#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 -#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 -#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 -#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 -#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 -#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 -#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 -#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 -#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 -#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 -#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 -#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 -#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 -#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 -#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 -#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 -#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 -#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 -#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 -#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 -#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 -#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 -#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 -#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 -#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 -#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 -#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 -#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 -#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 -#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 -#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 -#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 -#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 -#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 -#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 -#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 -#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 -#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 -#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 -#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 -#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 -#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 -#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 -#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 -#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 -#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 -#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 -#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 -#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 -#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 -#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 -#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 -#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 -#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 -#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 -#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 -#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 -#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 -#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 -#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 -#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 -#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 -#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 -#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 -#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 -#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 -#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 -#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 -#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 -#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 -#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 -#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 -#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 -#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 -#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 -#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 -#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 -#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 -#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 -#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 -#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 -#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 -#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 -#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 -#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 -#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 -#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 -#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 -#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 -#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 -#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 -#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 -#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 -#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 -#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 -#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 -#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 -#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 -#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 -#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 -#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 -#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 -#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 -#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 -#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 -#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 -#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 -#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 -#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 -#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 -#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 -#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 -#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 -#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 -#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 -#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 -#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 -#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 -#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 -#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 -#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 -#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 -#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 -#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 -#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 -#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 -#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 -#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 -#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 -#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 -#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 -#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 -#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 -#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 -#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 -#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 -#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 -#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 -#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 -#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 -#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 -#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 -#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 -#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 -#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 -#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 -#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 -#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 -#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 -#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 -#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 -#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 -#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 -#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 -#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 -#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 -#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 -#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 -#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 -#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 -#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 -#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 -#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 -#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 -#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 -#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 -#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 -#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 -#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 -#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 -#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 -#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 -#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 -#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 -#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 -#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 -#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 -#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 -#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 -#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 -#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 -#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 -#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 -#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 -#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 -#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 -#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 -#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 -#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 -#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 -#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 -#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 -#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 -#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 -#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 -#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 -#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 -#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 -#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 -#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 -#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 -#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 -#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 -#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 -#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 -#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 -#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 -#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 -#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 -#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 -#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 -#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 -#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 -#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 -#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 -#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 -#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 -#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 -#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 -#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 -#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 -#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 -#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 -#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 -#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 -#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 -#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 -#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 -#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 -#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 -#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 -#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 -#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 -#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 -#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 -#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 -#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 -#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 -#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 -#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 -#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 -#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 -#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 -#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 -#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 -#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 -#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 -#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 -#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 -#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 -#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 -#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 -#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 -#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 -#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 -#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 -#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 -#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 -#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 -#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 -#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 -#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 -#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 -#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 -#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 -#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 -#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 -#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 -#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 -#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 -#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 -#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 -#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 -#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 -#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 -#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 -#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 -#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 -#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 -#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 -#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 -#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 -#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 -#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 -#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 -#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 -#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 -#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 -#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 -#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 -#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 -#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 -#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 -#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 -#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 -#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 -#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 -#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 -#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 -#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 -#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 -#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 -#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 -#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 -#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 -#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 -#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 -#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 -#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 -#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 -#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 -#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 -#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 -#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 -#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 -#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 -#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 -#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 -#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 -#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 -#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 -#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 -#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 -#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 -#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 -#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 -#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 -#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 -#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 -#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 -#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 -#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 -#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 -#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 +#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 +#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 +#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 +#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 +#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 +#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 +#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 +#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 +#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 +#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 +#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 +#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 +#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 +#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 +#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 +#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 +#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 +#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 +#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 +#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 +#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 +#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 +#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 +#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 +#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 +#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 +#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 +#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 +#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 +#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 +#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 +#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 +#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 +#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 +#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 +#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 +#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 +#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 +#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 +#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 +#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 +#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 +#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 +#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 +#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 +#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 +#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 +#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1 +#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 +#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 +#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 +#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 +#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 +#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 +#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 +#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 +#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 +#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 +#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 +#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 +#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 +#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 +#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 +#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 +#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 +#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 +#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 +#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 +#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 +#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 +#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 +#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 +#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 +#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 +#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 +#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 +#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 +#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 +#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 +#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 +#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 +#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 +#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 +#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 +#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 +#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 +#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 +#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 +#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 +#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 +#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 +#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 +#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 +#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 +#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 +#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 +#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 +#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 +#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 +#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 +#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 +#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 +#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 +#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 +#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 +#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 +#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 +#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 +#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 +#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 +#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 +#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 +#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 +#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 +#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 +#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 +#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 +#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 +#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 +#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 +#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 +#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 +#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 +#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 +#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 +#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 +#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 +#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 +#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 +#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 +#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 +#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 +#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 +#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 +#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 +#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 +#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 +#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 +#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 +#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 +#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 +#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 +#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 +#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 +#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 +#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 +#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 +#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 +#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 +#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 +#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 +#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 +#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 +#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 +#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 +#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 +#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 +#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 +#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 +#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 +#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 +#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 +#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 +#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 +#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 +#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 +#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 +#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 +#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 +#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 +#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 +#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 +#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 +#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 +#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 +#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 +#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 +#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 +#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 +#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 +#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 +#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 +#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 +#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 +#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 +#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 +#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 +#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 +#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 +#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 +#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 +#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 +#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 +#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 +#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 +#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 +#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 +#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 +#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 +#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 +#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 +#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 +#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 +#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 +#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 +#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 +#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 +#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 +#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 +#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 +#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 +#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 +#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 +#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 +#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 +#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 +#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 +#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 +#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 +#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 +#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 +#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 +#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 +#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 +#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 +#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 +#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 +#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 +#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 +#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 +#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 +#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 +#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 +#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 +#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 +#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 +#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 +#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 +#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 +#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 +#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 #endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 09a75807bc6d..334b9247e78c 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts @@ -20,24 +20,6 @@ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 - MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { - fsl,pins = < - MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 - >; - }; - }; +&sata { + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 6a000666c147..3530280f5150 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -65,6 +65,10 @@ }; }; +&sata { + status = "okay"; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; @@ -91,14 +95,14 @@ hog { pinctrl_hog: hoggrp { fsl,pins = < - MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 - MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 - MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 - MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 - MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 - MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 >; }; }; @@ -163,7 +167,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 169>; + clocks = <&clks 201>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 0038228c508c..9cbdfe7a0931 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -20,21 +20,6 @@ compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - hog { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000 - MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000 - MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 - MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 - MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0 - >; - }; - }; +&sata { + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts new file mode 100644 index 000000000000..36be17f207b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-wandboard.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-wandboard.dtsi" + +/ { + model = "Wandboard i.MX6 Quad Board"; + compatible = "wand,imx6q-wandboard", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index ba09dc32324e..f024ef28b34b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -8,8 +8,8 @@ * */ -#include "imx6qdl.dtsi" #include "imx6q-pinfunc.h" +#include "imx6qdl.dtsi" / { cpus { @@ -61,6 +61,12 @@ }; soc { + ocram: sram@00900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x40000>; + clocks = <&clks 142>; + }; + aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { ecspi5: ecspi@02018000 { @@ -77,357 +83,54 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - - /* shared pinctrl settings */ - audmux { - pinctrl_audmux_1: audmux-1 { - fsl,pins = < - MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000 - MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000 - MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000 - MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 - >; - }; - - pinctrl_audmux_2: audmux-2 { - fsl,pins = < - MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 - MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 - MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 - MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 - >; - }; - }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - >; - }; - }; - - ecspi3 { - pinctrl_ecspi3_1: ecspi3grp-1 { - fsl,pins = < - MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - }; - - enet { - pinctrl_enet_1: enetgrp-1 { - fsl,pins = < - MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - >; - }; - - pinctrl_enet_2: enetgrp-2 { - fsl,pins = < - MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_enet_3: enetgrp-3 { - fsl,pins = < - MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - }; - - gpmi-nand { - pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = < - MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - }; - - i2c1 { - pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - }; - - i2c2 { - pinctrl_i2c2_1: i2c2grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + ipu2 { + pinctrl_ipu2_1: ipu2grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 >; }; }; - - i2c3 { - pinctrl_i2c3_1: i2c3grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - }; - - uart1 { - pinctrl_uart1_1: uart1grp-1 { - fsl,pins = < - MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - }; - - uart2 { - pinctrl_uart2_1: uart2grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - }; - - uart4 { - pinctrl_uart4_1: uart4grp-1 { - fsl,pins = < - MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - }; - - usbotg { - pinctrl_usbotg_1: usbotggrp-1 { - fsl,pins = < - MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usbotg_2: usbotggrp-2 { - fsl,pins = < - MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - >; - }; - }; - - usdhc2 { - pinctrl_usdhc2_1: usdhc2grp-1 { - fsl,pins = < - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 - MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059 - MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059 - MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059 - MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_2: usdhc2grp-2 { - fsl,pins = < - MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - }; - - usdhc3 { - pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = < - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; - - pinctrl_usdhc3_2: usdhc3grp-2 { - fsl,pins = < - MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - }; - - usdhc4 { - pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = < - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 - MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059 - MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059 - MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059 - MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059 - >; - }; - - pinctrl_usdhc4_2: usdhc4grp-2 { - fsl,pins = < - MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059 - MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059 - MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059 - MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059 - MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059 - MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059 - >; - }; - }; - - weim { - pinctrl_weim_cs0_1: weim_cs0grp-1 { - fsl,pins = < - MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 - >; - }; - - pinctrl_weim_nor_1: weimnorgrp-1 { - fsl,pins = < - MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 - MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 - /* data */ - MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 - MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 - MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 - MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 - MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 - MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 - MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 - MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 - MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 - MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 - MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 - MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 - MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 - MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 - MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 - MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 - /* address */ - MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 - MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 - MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 - MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 - MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 - MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 - MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 - MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 - MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - }; }; }; + sata: sata@02200000 { + compatible = "fsl,imx6q-ahci"; + reg = <0x02200000 0x4000>; + interrupts = <0 39 0x04>; + clocks = <&clks 154>, <&clks 187>, <&clks 105>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + ipu2: ipu@02800000 { #crtc-cells = <1>; compatible = "fsl,imx6q-ipu"; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index e994011220e7..1cbbc5160d27 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -45,6 +45,28 @@ status = "okay"; }; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_1>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 6e5dfdb32416..39eafc222a2e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -27,6 +27,15 @@ enable-active-high; }; + reg_usb_h1_vbus: usb_h1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 0>; + enable-active-high; + }; + reg_audio: wm8962_supply { compatible = "regulator-fixed"; regulator-name = "wm8962-supply"; @@ -41,12 +50,14 @@ volume-up { label = "Volume Up"; gpios = <&gpio1 4 0>; + gpio-key,wakeup; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; gpios = <&gpio1 5 0>; + gpio-key,wakeup; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; @@ -77,6 +88,22 @@ status = "okay"; }; +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_2>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_1>; @@ -93,7 +120,7 @@ codec: wm8962@1a { compatible = "wlf,wm8962"; reg = <0x1a>; - clocks = <&clks 169>; + clocks = <&clks 201>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; @@ -113,6 +140,68 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_2>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + interrupt-parent = <&gpio6>; + interrupts = <7 2>; + wakeup-gpios = <&gpio6 7 0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; @@ -125,6 +214,7 @@ }; &usbh1 { + vbus-supply = <®_usb_h1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi new file mode 100644 index 000000000000..a55113e65bcb --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -0,0 +1,137 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/ { + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "fsl,imx6-wandboard-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-wandboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_2>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_2>; + cd-gpios = <&gpio1 2 0>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; + cd-gpios = <&gpio3 9 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f21d259080fd..ccd55c2fdb67 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -14,11 +14,6 @@ / { aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -26,6 +21,18 @@ gpio4 = &gpio5; gpio5 = &gpio6; gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; }; intc: interrupt-controller@00a01000 { @@ -81,15 +88,14 @@ #size-cells = <1>; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <0 13 0x04>, <0 15 0x04>; - interrupt-names = "gpmi-dma", "bch"; + interrupts = <0 15 0x04>; + interrupt-names = "bch"; clocks = <&clks 152>, <&clks 153>, <&clks 151>, <&clks 150>, <&clks 149>; clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"; dmas = <&dma_apbh 0>; dma-names = "rx-tx"; - fsl,gpmi-dma-channel = <0>; status = "disabled"; }; @@ -184,6 +190,8 @@ interrupts = <0 26 0x04>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -197,6 +205,9 @@ reg = <0x02028000 0x4000>; interrupts = <0 46 0x04>; clocks = <&clks 178>; + dmas = <&sdma 37 1 0>, + <&sdma 38 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <38 37>; status = "disabled"; @@ -207,6 +218,9 @@ reg = <0x0202c000 0x4000>; interrupts = <0 47 0x04>; clocks = <&clks 179>; + dmas = <&sdma 41 1 0>, + <&sdma 42 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <42 41>; status = "disabled"; @@ -217,6 +231,9 @@ reg = <0x02030000 0x4000>; interrupts = <0 48 0x04>; clocks = <&clks 180>; + dmas = <&sdma 45 1 0>, + <&sdma 46 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <46 45>; status = "disabled"; @@ -278,17 +295,23 @@ }; can1: flexcan@02090000 { + compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 0x04>; + clocks = <&clks 108>, <&clks 109>; + clock-names = "ipg", "per"; }; can2: flexcan@02094000 { + compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 0x04>; + clocks = <&clks 110>, <&clks 111>; + clock-names = "ipg", "per"; }; gpt: gpt@02098000 { - compatible = "fsl,imx6q-gpt"; + compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 0x04>; clocks = <&clks 119>, <&clks 120>; @@ -491,6 +514,13 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 0x04>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + }; + usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; @@ -546,6 +576,713 @@ reg = <0x020e0000 0x38>; }; + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; + reg = <0x020e0000 0x4000>; + + audmux { + pinctrl_audmux_1: audmux-1 { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 + >; + }; + + pinctrl_audmux_2: audmux-2 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 + >; + }; + + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi1_2: ecspi1grp-2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + >; + }; + }; + + ecspi3 { + pinctrl_ecspi3_1: ecspi3grp-1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + }; + + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_enet_3: enetgrp-3 { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 + MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 + MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 + MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 + MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 + MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 + MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 + MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 + MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_flexcan1_2: flexcan1grp-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + }; + + hdmi_hdcp { + pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + }; + + hdmi_cec { + pinctrl_hdmi_cec_1: hdmicecgrp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hdmi_cec_2: hdmicecgrp-2 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_2: i2c2grp-2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_3: i2c2grp-3 { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_3: i2c3grp-3 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_4: i2c3grp-4 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + }; + + ipu1 { + pinctrl_ipu1_1: ipu1grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + + pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 + >; + }; + }; + + pwm0 { + pinctrl_pwm0_1: pwm0grp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + }; + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + }; + + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_2: usbotggrp-2 { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + }; + + usbh2 { + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + }; + + usbh3 { + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_2: usdhc1grp-2 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 + /* data */ + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 + /* address */ + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + >; + }; + }; + }; + ldb: ldb@020e0008 { #address-cells = <1>; #size-cells = <0>; @@ -555,13 +1292,11 @@ lvds-channel@0 { reg = <0>; - crtcs = <&ipu1 0>; status = "disabled"; }; lvds-channel@1 { reg = <1>; - crtcs = <&ipu1 1>; status = "disabled"; }; }; @@ -582,6 +1317,7 @@ interrupts = <0 2 0x04>; clocks = <&clks 155>, <&clks 155>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; }; @@ -751,8 +1487,8 @@ clocks = <&clks 196>; }; - ocotp@021bc000 { - compatible = "fsl,imx6q-ocotp"; + ocotp: ocotp@021bc000 { + compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; }; @@ -791,6 +1527,8 @@ interrupts = <0 27 0x04>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -800,6 +1538,8 @@ interrupts = <0 28 0x04>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -809,6 +1549,8 @@ interrupts = <0 29 0x04>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -818,6 +1560,8 @@ interrupts = <0 30 0x04>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c5e5da02d7e3..c46651e4d966 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -152,32 +152,41 @@ }; uart5: serial@02018000 { - compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; interrupts = <0 30 0x04>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart2: serial@02024000 { - compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; interrupts = <0 27 0x04>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,6 +195,9 @@ reg = <0x02028000 0x4000>; interrupts = <0 46 0x04>; clocks = <&clks IMX6SL_CLK_SSI1>; + dmas = <&sdma 37 1 0>, + <&sdma 38 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; @@ -195,6 +207,9 @@ reg = <0x0202c000 0x4000>; interrupts = <0 47 0x04>; clocks = <&clks IMX6SL_CLK_SSI2>; + dmas = <&sdma 41 1 0>, + <&sdma 42 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; @@ -204,27 +219,36 @@ reg = <0x02030000 0x4000>; interrupts = <0 48 0x04>; clocks = <&clks IMX6SL_CLK_SSI3>; + dmas = <&sdma 45 1 0>, + <&sdma 46 1 0>; + dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; uart3: serial@02034000 { - compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; interrupts = <0 28 0x04>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; uart4: serial@02038000 { - compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; + compatible = "fsl,imx6sl-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; interrupts = <0 29 0x04>; clocks = <&clks IMX6SL_CLK_UART>, <&clks IMX6SL_CLK_UART_SERIAL>; clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; @@ -594,6 +618,7 @@ clocks = <&clks IMX6SL_CLK_SDMA>, <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; + #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; }; diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts index 1334b42c6b77..a68e34bbecb2 100644 --- a/arch/arm/boot/dts/keystone.dts +++ b/arch/arm/boot/dts/keystone.dts @@ -7,7 +7,9 @@ */ /dts-v1/; -/include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" / { model = "Texas Instruments Keystone 2 SoC"; @@ -67,18 +69,23 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0x308>; + interrupts = + <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; pmu { compatible = "arm,cortex-a15-pmu"; - interrupts = <0 20 0xf01>, - <0 21 0xf01>, - <0 22 0xf01>, - <0 23 0xf01>; + interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; }; soc { @@ -100,7 +107,7 @@ reg-io-width = <4>; reg = <0x02530c00 0x100>; clock-frequency = <133120000>; - interrupts = <0 277 0xf01>; + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; uart1: serial@02531000 { @@ -110,7 +117,7 @@ reg-io-width = <4>; reg = <0x02531000 0x100>; clock-frequency = <133120000>; - interrupts = <0 280 0xf01>; + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 1e5bef0bead7..650ef30e1856 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -1,4 +1,39 @@ / { + mbus { + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { compatible = "marvell,88f6281-pinctrl"; @@ -41,37 +76,6 @@ }; }; - pcie-controller { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index a63a11137262..3933a331ddc2 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -1,4 +1,59 @@ / { + mbus { + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + }; + }; + }; ocp@f1000000 { pinctrl: pinctrl@10000 { @@ -94,52 +149,5 @@ status = "disabled"; }; - pcie-controller { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ - 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ - - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 10>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - }; - }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 00c48d26de68..142b9cd3b454 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "LaCie CloudBox"; @@ -89,3 +89,19 @@ gpios = <&gpio0 17 0>; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index 9d777edd1f36..72c4b0a0366f 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -11,14 +11,15 @@ /dts-v1/; -/include/ "kirkwood-db.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood-db.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Marvell DB-88F6281-BP Development Board"; compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - ocp@f1000000 { + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index f4c852886d23..36c411d34926 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -11,14 +11,15 @@ /dts-v1/; -/include/ "kirkwood-db.dtsi" -/include/ "kirkwood-6282.dtsi" +#include "kirkwood-db.dtsi" +#include "kirkwood-6282.dtsi" / { model = "Marvell DB-88F6282-BP Development Board"; compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - ocp@f1000000 { + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index c87cfb816120..c0e2a5879174 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -12,7 +12,7 @@ * and 6282 variants of the Marvell Kirkwood Development Board. */ -/include/ "kirkwood.dtsi" +#include "kirkwood.dtsi" / { memory { @@ -77,13 +77,21 @@ cd-gpios = <&gpio1 6 0>; status = "okay"; }; + }; +}; - pcie-controller { - status = "okay"; +&mdio { + status = "okay"; - pcie@1,0 { - status = "okay"; - }; - }; + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index 14d4ceea3057..e112ca62d978 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-dnskw.dtsi" +#include "kirkwood-dnskw.dtsi" / { model = "D-Link DNS-320 NAS (Rev A1)"; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index 63872570e6ce..5119fb8a8eb6 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-dnskw.dtsi" +#include "kirkwood-dnskw.dtsi" / { model = "D-Link DNS-325 NAS (Rev A1)"; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 0afe1d07c803..d544f77a4ca4 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -1,5 +1,5 @@ -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "D-Link DNS NASes (kirkwood-based)"; @@ -219,3 +219,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 7714742bb8d8..59a2117c35a7 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Seagate FreeAgent Dockstar"; @@ -90,3 +90,20 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + compatible = "marvell,88e1116"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 36c7ba38d500..6f62af99c9cb 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Globalscale Technologies Dreamplug"; @@ -99,3 +99,31 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 31caa6405065..6f7c7d7ecf2a 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Seagate GoFlex Net"; @@ -170,3 +170,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 1e642f39b154..6548b9dc6855 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Globalscale Technologies Guruplug Server Plus"; @@ -96,3 +96,33 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + compatible = "marvell,88e1121"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "marvell,88e1121"; + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 20c4b081f420..cb711a3bd983 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; @@ -122,3 +122,19 @@ }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 441204e8abc6..0323f017eeed 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Iomega Iconnect"; @@ -18,6 +18,17 @@ linux,initrd-end = <0x4800000>; }; + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { pmx_button_reset: pmx-button-reset { @@ -101,14 +112,6 @@ reg = <0x980000 0x1f400000>; }; }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; }; gpio-leds { @@ -176,3 +179,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@11 { + device_type = "ethernet-phy"; + reg = <11>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 00a7bfe5e83b..df8447442b37 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "Iomega StorCenter ix2-200"; @@ -194,3 +194,27 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@11 { + device_type = "ethernet-phy"; + reg = <11>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index c3f036b86cca..da674bbd49a8 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-ns2-common.dtsi" +#include "kirkwood-ns2-common.dtsi" / { model = "LaCie Internet Space v2"; @@ -30,3 +30,5 @@ }; }; }; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5d9f5ea78700..6899408482d2 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-98dx4122.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-98dx4122.dtsi" / { model = "Keymile Kirkwood Reference Design"; @@ -50,3 +50,19 @@ i2c-gpio,delay-us = <2>; /* ~100 kHz */ }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts index 9f55d95f35f5..e2fa368aef25 100644 --- a/arch/arm/boot/dts/kirkwood-lschlv2.dts +++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-lsxl.dtsi" +#include "kirkwood-lsxl.dtsi" / { model = "Buffalo Linkstation LS-CHLv2"; diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts index 5c84c118ed8d..8d89cdf8d6bf 100644 --- a/arch/arm/boot/dts/kirkwood-lsxhl.dts +++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-lsxl.dtsi" +#include "kirkwood-lsxl.dtsi" / { model = "Buffalo Linkstation LS-XHL"; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 31b17f5b9d28..4e8f9e42c592 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -1,5 +1,5 @@ -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { chosen { @@ -207,3 +207,31 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; + + ethphy1: ethernet-phy@8 { + device_type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 6179333fd71f..ce2b94b513db 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { model = "MPL CEC4"; @@ -16,6 +16,17 @@ bootargs = "console=ttyS0,115200n8 earlyprintk"; }; + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { pmx_led_health: pmx-led-health { @@ -134,14 +145,6 @@ cd-gpios = <&gpio1 15 1>; /* No WP GPIO */ }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; }; gpio-leds { @@ -191,3 +194,30 @@ }; }; +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + device_type = "ethernet-phy"; + reg = <2>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts new file mode 100644 index 000000000000..6317e1d088b3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -0,0 +1,125 @@ +/* + * Marvell 88F6281 GTW GE Board + * + * Lennert Buytenhek <buytenh@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Marvell 88F6281 GTW GE Board"; + compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl@10000 { + pmx_usb_led: pmx-usb-led { + marvell,pins = "mpp12"; + marvell,function = "gpo"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "gpio"; + }; + + pmx_keys: pmx-keys { + marvell,pins = "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l12805d"; + reg = <0>; + spi-max-frequency = <50000000>; + mode = <0>; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + clock-frequency = <200000000>; + status = "ok"; + }; + + ehci@50000 { + status = "okay"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds &pmx_usb_led>; + pinctrl-names = "default"; + + green-status { + label = "gtw:green:Status"; + gpios = <&gpio0 20 0>; + }; + + red-status { + label = "gtw:red:Status"; + gpios = <&gpio0 21 0>; + }; + + green-usb { + label = "gtw:green:USB"; + gpios = <&gpio0 12 0>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_keys>; + pinctrl-names = "default"; + + button@1 { + label = "SWR Button"; + linux,code = <0x198>; /* KEY_RESTART */ + gpios = <&gpio1 15 1>; + }; + button@2 { + label = "WPS Button"; + linux,code = <0x211>; /* KEY_WPS_BUTTON */ + gpios = <&gpio1 14 1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index ad6ade7d9191..874857ea9cb8 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6282.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" / { model = "NETGEAR ReadyNAS Duo v2"; @@ -16,6 +16,17 @@ bootargs = "console=ttyS0,115200n8 earlyprintk"; }; + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { pmx_button_power: pmx-button-power { @@ -52,6 +63,17 @@ }; }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + g762_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + i2c@11000 { status = "okay"; @@ -59,6 +81,15 @@ compatible = "ricoh,rs5c372a"; reg = <0x32>; }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; }; serial@12000 { @@ -101,14 +132,6 @@ status = "okay"; nr-ports = <2>; }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; }; gpio-leds { @@ -184,3 +207,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 2afac0405816..2fcb82e20828 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -1,5 +1,5 @@ -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { chosen { @@ -84,3 +84,19 @@ }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy { + device_type = "ethernet-phy"; + /* overwrite reg property in board file */ + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index b50e93d7796c..53368d1022cc 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-ns2-common.dtsi" +#include "kirkwood-ns2-common.dtsi" / { model = "LaCie Network Space v2"; @@ -30,3 +30,5 @@ }; }; }; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index af8259fe8955..279607093cdb 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-ns2-common.dtsi" +#include "kirkwood-ns2-common.dtsi" / { model = "LaCie Network Space Lite v2"; @@ -30,3 +30,5 @@ }; }; }; + +ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index 85f24d227e17..defdc77fb550 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-ns2-common.dtsi" +#include "kirkwood-ns2-common.dtsi" / { model = "LaCie Network Space Max v2"; @@ -49,3 +49,5 @@ }; }; }; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index 329e530bffe7..adbafdd90991 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "kirkwood-ns2-common.dtsi" +#include "kirkwood-ns2-common.dtsi" / { /* This machine is embedded in the first LaCie CloudBox product. */ @@ -50,3 +50,5 @@ }; }; }; + +ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi new file mode 100644 index 000000000000..06267a91de38 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -0,0 +1,107 @@ +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "ZyXEL NSA310"; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pmx_usb_power_off: pmx-usb-power-off { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + }; + + serial@12000 { + status = "ok"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + nand@3000000 { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio1 16 0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_off>; + pinctrl-names = "default"; + + usb0_power_off: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power Off"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 69003598f5fa..7aeae0c2c1f4 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -1,10 +1,8 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood-nsa310-common.dtsi" / { - model = "ZyXEL NSA310"; compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; memory { @@ -16,6 +14,17 @@ bootargs = "console=ttyS0,115200"; }; + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { pinctrl-0 = <&pmx_unknown>; @@ -41,11 +50,6 @@ marvell,function = "gpio"; }; - pmx_usb_power_off: pmx-usb-power-off { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - pmx_led_sys_green: pmx-led-sys-green { marvell,pins = "mpp28"; marvell,function = "gpio"; @@ -95,20 +99,6 @@ marvell,pins = "mpp46"; marvell,function = "gpio"; }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; }; i2c@11000 { @@ -119,57 +109,6 @@ reg = <0x2e>; }; }; - - nand@3000000 { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; }; gpio_keys { @@ -246,30 +185,4 @@ gpios = <&gpio1 8 0>; }; }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 0>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_off>; - pinctrl-names = "default"; - - usb0_power_off: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power Off"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 0>; - }; - }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts new file mode 100644 index 000000000000..ab0212b0e6f5 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -0,0 +1,165 @@ +/dts-v1/; + +#include "kirkwood-nsa310-common.dtsi" + +/* + * There are at least two different NSA310 designs. This variant does + * not have the red USB Led. + */ + +/ { + compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-names = "default"; + + pmx_led_esata_green: pmx-led-esata-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_esata_red: pmx-led-esata-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_usb_power_off: pmx-usb-power-off { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_red: pmx-led-sys-red { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_green: pmx-led-hdd-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd_red: pmx-led-hdd-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + }; + + i2c@11000 { + status = "okay"; + + lm85: lm85@2e { + compatible = "lm85"; + reg = <0x2e>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + label = "Power Button"; + linux,code = <116>; + gpios = <&gpio1 14 0>; + }; + button@2 { + label = "Copy Button"; + linux,code = <133>; + gpios = <&gpio1 5 1>; + }; + button@3 { + label = "Reset Button"; + linux,code = <0x198>; + gpios = <&gpio1 4 1>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green-sys { + label = "nsa310:green:sys"; + gpios = <&gpio0 28 0>; + }; + red-sys { + label = "nsa310:red:sys"; + gpios = <&gpio0 29 0>; + }; + green-hdd { + label = "nsa310:green:hdd"; + gpios = <&gpio1 9 0>; + }; + red-hdd { + label = "nsa310:red:hdd"; + gpios = <&gpio1 10 0>; + }; + green-esata { + label = "nsa310:green:esata"; + gpios = <&gpio0 12 0>; + }; + red-esata { + label = "nsa310:red:esata"; + gpios = <&gpio0 13 0>; + }; + green-usb { + label = "nsa310:green:usb"; + gpios = <&gpio0 15 0>; + }; + green-copy { + label = "nsa310:green:copy"; + gpios = <&gpio1 7 0>; + }; + red-copy { + label = "nsa310:red:copy"; + gpios = <&gpio1 8 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 38dc8517d777..85ccf8d8abb1 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6282.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" / { model = "Plat'Home OpenBlocksA6"; @@ -166,3 +166,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index f7143f128504..5696b630b70b 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -6,8 +6,8 @@ * Licensed under GPLv2 */ -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" / { memory { @@ -91,3 +91,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts index f620ce48de97..eac6a21f3b1f 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -8,7 +8,7 @@ /dts-v1/; -/include/ "kirkwood-sheevaplug-common.dtsi" +#include "kirkwood-sheevaplug-common.dtsi" / { model = "Globalscale Technologies eSATA SheevaPlug"; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index bf1dff251432..bb61918313db 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -8,7 +8,7 @@ /dts-v1/; -/include/ "kirkwood-sheevaplug-common.dtsi" +#include "kirkwood-sheevaplug-common.dtsi" / { model = "Globalscale Technologies SheevaPlug"; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index f2052d7bc10f..30842b4ff293 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -1,7 +1,7 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6282.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" / { model = "Univeral Scientific Industrial Co. Topkick-1281P2"; @@ -203,3 +203,19 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 6dd1038e4de4..f755bc1dc604 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,8 +1,8 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6281.dtsi" -/include/ "kirkwood-ts219.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include "kirkwood-ts219.dtsi" / { ocp@f1000000 { @@ -50,4 +50,6 @@ gpios = <&gpio0 16 1>; }; }; -};
\ No newline at end of file +}; + +ðphy0 { reg = <8>; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 6fdc5ffcaae5..9efcd2dc79d3 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,10 +1,21 @@ /dts-v1/; -/include/ "kirkwood.dtsi" -/include/ "kirkwood-6282.dtsi" -/include/ "kirkwood-ts219.dtsi" +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" +#include "kirkwood-ts219.dtsi" / { + mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; + pcie-controller { + status = "okay"; + + pcie@2,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { pinctrl: pinctrl@10000 { @@ -30,14 +41,6 @@ marvell,function = "gpio"; }; }; - pcie-controller { - status = "okay"; - - pcie@2,0 { - status = "okay"; - }; - }; - }; gpio_keys { @@ -58,4 +61,6 @@ gpios = <&gpio1 5 1>; }; }; -};
\ No newline at end of file +}; + +ðphy0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 0c9a94cd666c..39158cf16258 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -11,6 +11,16 @@ bootargs = "console=ttyS0,115200n8"; }; + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + ocp@f1000000 { i2c@11000 { status = "okay"; @@ -87,12 +97,21 @@ status = "okay"; nr-ports = <2>; }; - pcie-controller { - status = "okay"; + }; +}; - pcie@1,0 { - status = "okay"; - }; - }; +&mdio { + status = "okay"; + + ethphy0: ethernet-phy { + device_type = "ethernet-phy"; + /* overwrite reg property in board file */ + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 9809fc1f105c..cf7aeaf89e9c 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,5 +1,7 @@ /include/ "skeleton.dtsi" +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + / { compatible = "marvell,kirkwood"; interrupt-parent = <&intc>; @@ -20,23 +22,53 @@ gpio0 = &gpio0; gpio1 = &gpio1; }; - intc: interrupt-controller { - compatible = "marvell,orion-intc", "marvell,intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf1020204 0x04>, - <0xf1020214 0x04>; + + mbus { + compatible = "marvell,kirkwood-mbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + controller = <&mbusc>; + pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ + pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ }; ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x0100000 - 0xe0000000 0xe0000000 0x8100000 /* PCIE */ 0xf4000000 0xf4000000 0x0000400 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x1500 0x20>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <1>; + marvell,#interrupts = <6>; + }; + core_clk: core-clocks@10030 { compatible = "marvell,kirkwood-core-clock"; reg = <0x10030 0x4>; @@ -103,9 +135,11 @@ #clock-cells = <1>; }; - wdt@20300 { + wdt: watchdog-timer@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; clocks = <&gate_clk 7>; status = "okay"; }; @@ -192,5 +226,57 @@ clocks = <&gate_clk 17>; status = "okay"; }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <46>; + clocks = <&gate_clk 0>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + eth0: ethernet-controller@72000 { + compatible = "marvell,kirkwood-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 0>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet0-port@0 { + device_type = "network"; + compatible = "marvell,kirkwood-eth-port"; + reg = <0>; + interrupts = <11>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; + + eth1: ethernet-controller@76000 { + compatible = "marvell,kirkwood-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76000 0x4000>; + clocks = <&gate_clk 19>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet1-port@0 { + device_type = "network"; + compatible = "marvell,kirkwood-eth-port"; + reg = <0>; + interrupts = <15>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index cdc010e0f93e..386d42870215 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -38,7 +38,7 @@ }; serial@19c40000 { - compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; interrupts = <0 195 0x0>; diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 9c1167b0459b..93e9f7e0b7ad 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts @@ -38,7 +38,7 @@ }; serial@16440000 { - compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; interrupts = <0 154 0x0>; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index e643620417a9..07be2cd7b318 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -644,7 +644,7 @@ utmi-mode = <2>; ranges; dwc3@4a030000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x4a030000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb2_phy>, <&usb3_phy>; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 0077fc8510b7..aed83deaa991 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -53,3 +53,20 @@ }; }; }; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + device-type = "ethernet-phy"; + reg = <8>; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 892c64e3f1e1..e06c37e91ac6 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -16,11 +16,12 @@ aliases { gpio0 = &gpio0; }; + intc: interrupt-controller { - compatible = "marvell,orion-intc", "marvell,intc"; + compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; - reg = <0xf1020204 0x04>; + reg = <0xf1020200 0x08>; }; ocp@f1000000 { @@ -132,5 +133,34 @@ interrupts = <28>; status = "okay"; }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; }; }; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index f9d92da86783..83bb0eff697b 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -28,5 +28,16 @@ marvell,intc-priority; marvell,intc-nr-irqs = <56>; }; + + gpio: gpio@40e00000 { + compatible = "intel,pxa3xx-gpio"; + reg = <0x40e00000 0x10000>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; + interrupts = <8 9 10>; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6ce699be6095..6c26caa880f2 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -185,6 +185,13 @@ status = "disabled"; }; + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + }; + sdhi0: sdhi@ee100000 { compatible = "renesas,r8a73a4-sdhi"; reg = <0 0xee100000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 43abf3a5cc67..c638e4ab91b8 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -10,6 +10,7 @@ /dts-v1/; /include/ "r8a7740.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "armadillo 800 eva reference"; @@ -33,6 +34,21 @@ regulator-boot-on; }; + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; + }; + led2 { + gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; + }; + led3 { + gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; + }; + led4 { + gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; + }; + }; }; &i2c0 { @@ -41,5 +57,23 @@ reg = <0x55>; interrupt-parent = <&irqpin1>; interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + pinctrl-0 = <&st1232_pins>; + pinctrl-names = "default"; + gpios = <&pfc 166 GPIO_ACTIVE_LOW>; + }; +}; + +&pfc { + pinctrl-0 = <&scifa1_pins>; + pinctrl-names = "default"; + + scifa1_pins: scifa1 { + renesas,groups = "scifa1_data"; + renesas,function = "scifa1"; + }; + + st1232_pins: st1232 { + renesas,groups = "intc_irq10"; + renesas,function = "intc"; }; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 27f014f3f1aa..44d3d520e01f 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -145,6 +145,14 @@ 0 73 0x4>; }; + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; reg = <0xe6600000 0x100>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 474373559bdc..45ac404ab6d8 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -32,4 +32,70 @@ reg = <0xfe438000 0x1000>, <0xfe430000 0x100>; }; + + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + reg = <0xffc40000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 103 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + reg = <0xffc41000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 103 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + reg = <0xffc42000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 103 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + reg = <0xffc43000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 103 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; + reg = <0xffc44000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 103 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 27>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7778"; + reg = <0xfffc000 0x118>; + #gpio-range-cells = <3>; + }; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 5c22feeaddd6..6d5508392252 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; /include/ "r8a7779.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "marzen"; @@ -37,6 +38,9 @@ lan0@18000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x18000000 0x100>; + pinctrl-0 = <&lan0_pins>; + pinctrl-names = "default"; + phy-mode = "mii"; interrupt-parent = <&gic>; interrupts = <0 28 0x4>; @@ -44,4 +48,49 @@ vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; + + leds { + compatible = "gpio-leds"; + led2 { + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + led3 { + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + }; + led4 { + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pfc { + pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; + pinctrl-names = "default"; + + lan0_pins: lan0 { + intc { + renesas,groups = "intc_irq1_b"; + renesas,function = "intc"; + }; + lbsc { + renesas,groups = "lbsc_ex_cs0"; + renesas,function = "lbsc"; + }; + }; + + scif2_pins: scif2 { + renesas,groups = "scif2_data_c"; + renesas,function = "scif2"; + }; + + scif4_pins: scif4 { + renesas,groups = "scif4_data"; + renesas,function = "scif4"; + }; + + sdhi0_pins: sdhi0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", + "sdhi0_wp"; + renesas,function = "sdhi0"; + }; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 86bd487d517c..23a62447359c 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -48,6 +48,90 @@ <0xf0000100 0x100>; }; + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc40000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 141 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc41000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 142 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc42000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 143 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc43000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 144 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc44000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 145 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@ffc45000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc45000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 146 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio6: gpio@ffc46000 { + compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; + reg = <0xffc46000 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 147 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 9>; + #interrupt-cells = <2>; + interrupt-controller; + }; + irqpin0: irqpin@fe780010 { compatible = "renesas,intc-irqpin"; #interrupt-cells = <2>; @@ -101,6 +185,12 @@ interrupts = <0 81 0x4>; }; + pfc: pfc@fffc0000 { + compatible = "renesas,pfc-r8a7779"; + reg = <0xfffc0000 0x23c>; + #gpio-range-cells = <3>; + }; + thermal@ffc48000 { compatible = "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9cd882028095..3b879e7c697c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -38,6 +38,78 @@ interrupts = <1 9 0xf04>; }; + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc40000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 4 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc41000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 5 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc42000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 6 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc43000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 7 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc44000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 8 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@ffc45000 { + compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; + reg = <0 0xffc45000 0 0x2c>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, @@ -73,6 +145,12 @@ status = "disabled"; }; + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7790"; + reg = <0 0xe6060000 0 0x250>; + #gpio-range-cells = <3>; + }; + sdhi0: sdhi@ee100000 { compatible = "renesas,r8a7790-sdhi"; reg = <0 0xee100000 0 0x100>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index a1d5e25a6698..ff63fbbd18ab 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -48,6 +48,11 @@ }; }; + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; + }; + memory { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 8a9e05d8a4b8..dba739b6ef36 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -81,6 +81,14 @@ macb1: ethernet@f802c000 { phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + reg = <1>; + }; }; pinctrl@fffff200 { diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi index 7bf020ecadf5..249f65be2a50 100644 --- a/arch/arm/boot/dts/sh7372.dtsi +++ b/arch/arm/boot/dts/sh7372.dtsi @@ -23,4 +23,12 @@ reg = <0x0>; }; }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-sh7372"; + reg = <0xe6050000 0x8000>, + <0xe605801c 0x1c>; + gpio-controller; + #gpio-cells = <2>; + }; }; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 6d9ece2399a0..212230629f27 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sh73a0.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "KZM-A9-GT"; @@ -58,6 +59,24 @@ regulator-boot-on; }; + vmmc_sdhi0: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vmmc_sdhi2: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + lan9220@10000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x10000000 0x100>; @@ -70,6 +89,22 @@ vddvario-supply = <®_1p8v>; vdd33a-supply = <®_3p3v>; }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 20 GPIO_ACTIVE_LOW>; + }; + led2 { + gpios = <&pfc 21 GPIO_ACTIVE_LOW>; + }; + led3 { + gpios = <&pfc 22 GPIO_ACTIVE_LOW>; + }; + led4 { + gpios = <&pfc 23 GPIO_ACTIVE_LOW>; + }; + }; }; &i2c0 { @@ -145,20 +180,71 @@ }; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; +}; + &mmcif { + pinctrl-0 = <&mmcif_pins>; + pinctrl-names = "default"; + bus-width = <8>; vmmc-supply = <®_1p8v>; status = "okay"; }; +&pfc { + pinctrl-0 = <&scifa4_pins>; + pinctrl-names = "default"; + + i2c3_pins: i2c3 { + renesas,groups = "i2c3_1"; + renesas,function = "i2c3"; + }; + + mmcif_pins: mmcif { + mux { + renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; + renesas,function = "mmc0"; + }; + cfg { + renesas,groups = "mmc0_data8_0"; + renesas,pins = "PORT279"; + bias-pull-up; + }; + }; + + scifa4_pins: scifa4 { + renesas,groups = "scifa4_data", "scifa4_ctrl"; + renesas,function = "scifa4"; + }; + + sdhi0_pins: sdhi0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; + + sdhi2_pins: sdhi2 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; +}; + &sdhi0 { - vmmc-supply = <®_3p3v>; + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi0>; bus-width = <4>; status = "okay"; }; &sdhi2 { - vmmc-supply = <®_3p3v>; + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi2>; bus-width = <4>; broken-cd; status = "okay"; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 7137c0f284f2..ba59a5875a10 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -228,4 +228,12 @@ cap-sd-highspeed; status = "disabled"; }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-sh73a0"; + reg = <0xe6050000 0x8000>, + <0xe605801c 0x1c>; + gpio-controller; + #gpio-cells = <2>; + }; }; diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi index 15994158a998..b5d7f36f33de 100644 --- a/arch/arm/boot/dts/skeleton64.dtsi +++ b/arch/arm/boot/dts/skeleton64.dtsi @@ -9,5 +9,5 @@ #size-cells = <2>; chosen { }; aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index bee62a2cf6d6..e273fa993b8c 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -476,25 +476,25 @@ }; timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; }; timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer-sp"; + compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; }; timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; }; timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; }; diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi new file mode 100644 index 000000000000..e0799966bc25 --- /dev/null +++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi @@ -0,0 +1,196 @@ +/* + * Copyright 2012 ST-Ericsson + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include "ste-nomadik-pinctrl.dtsi" + +/ { + soc { + pinctrl { + uart0 { + uart0_default_mux: uart0_mux { + default_mux { + ste,function = "u0"; + ste,pins = "u0_a_1"; + }; + }; + + uart0_default_mode: uart0_default { + default_cfg1 { + ste,pins = "GPIO0", "GPIO2"; + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO1", "GPIO3"; + ste,config = <&out_hi>; + }; + }; + + uart0_sleep_mode: uart0_sleep { + sleep_cfg1 { + ste,pins = "GPIO0", "GPIO2"; + ste,config = <&slpm_in_pu>; + }; + + sleep_cfg2 { + ste,pins = "GPIO1", "GPIO3"; + ste,config = <&slpm_out_hi>; + }; + }; + }; + + uart2 { + uart2_default_mode: uart2_default { + default_mux { + ste,function = "u2"; + ste,pins = "u2txrx_a_1"; + }; + + default_cfg1 { + ste,pins = "GPIO120"; + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO121"; + ste,config = <&out_hi>; + }; + }; + + uart2_sleep_mode: uart2_sleep { + sleep_cfg1 { + ste,pins = "GPIO120"; + ste,config = <&slpm_in_pu>; + }; + + sleep_cfg2 { + ste,pins = "GPIO121"; + ste,config = <&slpm_out_hi>; + }; + }; + }; + + i2c0 { + i2c0_default_mux: i2c_mux { + default_mux { + ste,function = "i2c0"; + ste,pins = "i2c0_a_1"; + }; + }; + + i2c0_default_mode: i2c_default { + default_cfg1 { + ste,pins = "GPIO147", "GPIO148"; + ste,config = <&in_pu>; + }; + }; + + i2c0_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO147", "GPIO148"; + ste,config = <&slpm_in_pu>; + }; + }; + }; + + i2c1 { + i2c1_default_mux: i2c_mux { + default_mux { + ste,function = "i2c1"; + ste,pins = "i2c1_b_2"; + }; + }; + + i2c1_default_mode: i2c_default { + default_cfg1 { + ste,pins = "GPIO16", "GPIO17"; + ste,config = <&in_pu>; + }; + }; + + i2c1_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO16", "GPIO17"; + ste,config = <&slpm_in_pu>; + }; + }; + }; + + i2c2 { + i2c2_default_mux: i2c_mux { + default_mux { + ste,function = "i2c2"; + ste,pins = "i2c2_b_2"; + }; + }; + + i2c2_default_mode: i2c_default { + default_cfg1 { + ste,pins = "GPIO10", "GPIO11"; + ste,config = <&in_pu>; + }; + }; + + i2c2_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO11", "GPIO11"; + ste,config = <&slpm_in_pu>; + }; + }; + }; + + i2c4 { + i2c4_default_mux: i2c_mux { + default_mux { + ste,function = "i2c4"; + ste,pins = "i2c4_b_2"; + }; + }; + + i2c4_default_mode: i2c_default { + default_cfg1 { + ste,pins = "GPIO122", "GPIO123"; + ste,config = <&in_pu>; + }; + }; + + i2c4_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO122", "GPIO123"; + ste,config = <&slpm_in_pu>; + }; + }; + }; + + i2c5 { + i2c5_default_mux: i2c_mux { + default_mux { + ste,function = "i2c5"; + ste,pins = "i2c5_c_2"; + }; + }; + + i2c5_default_mode: i2c_default { + default_cfg1 { + ste,pins = "GPIO118", "GPIO119"; + ste,config = <&in_pu>; + }; + }; + + i2c5_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO118", "GPIO119"; + ste,config = <&slpm_in_pu>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-ccu8540.dts b/arch/arm/boot/dts/ste-ccu8540.dts new file mode 100644 index 000000000000..7f3baf51a3a9 --- /dev/null +++ b/arch/arm/boot/dts/ste-ccu8540.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2013 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "ste-dbx5x0.dtsi" +#include "ste-ccu8540-pinctrl.dtsi" + +/ { + model = "ST-Ericsson U8540 platform with Device Tree"; + compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; + + memory@0 { + reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; + }; + + soc { + pinctrl { + compatible = "stericsson,db8540-pinctrl"; + }; + + prcmu@80157000 { + reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; + }; + + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; + status = "okay"; + }; + + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; + status = "okay"; + }; + + i2c0: i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; + pinctrl-1 = <&i2c0_sleep_mode>; + }; + + i2c1: i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; + pinctrl-1 = <&i2c1_sleep_mode>; + }; + + i2c2: i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_default_mux>, <&i2c2_default_mode>; + pinctrl-1 = <&i2c2_sleep_mode>; + }; + + i2c3: i2c@80110000 { + status = "disabled"; + }; + + i2c4: i2c@8012a000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c4_default_mux>, <&i2c4_default_mode>; + pinctrl-1 = <&i2c4_sleep_mode>; + }; + + i2c5: i2c@80001000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c5_default_mux>, <&i2c5_default_mode>; + pinctrl-1 = <&i2c5_sleep_mode>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts index ed29ec7288e4..229508750890 100644 --- a/arch/arm/boot/dts/ccu9540.dts +++ b/arch/arm/boot/dts/ste-ccu9540.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "dbx5x0.dtsi" +#include "ste-dbx5x0.dtsi" / { model = "ST-Ericsson CCU9540 platform with Device Tree"; diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index a1529455f081..1c1091eedade 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -245,7 +245,7 @@ <22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; status = "disabled"; - }; + }; db8500-prcmu-regulators { compatible = "stericsson,db8500-prcmu-regulator"; @@ -457,8 +457,36 @@ stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; + ext_regulators: ab8500-ext-regulators { + compatible = "stericsson,ab8500-ext-regulator"; + + ab8500_ext1_reg: ab8500_ext1 { + regulator-compatible = "ab8500_ext1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext2_reg: ab8500_ext2 { + regulator-compatible = "ab8500_ext2"; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-boot-on; + regulator-always-on; + }; + + ab8500_ext3_reg: ab8500_ext3 { + regulator-compatible = "ab8500_ext3"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; + vin-supply = <&ab8500_ext3_reg>; // supplies to the display/camera ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 9db41b9d8358..370e03f5e7b2 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -10,7 +10,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "dbx5x0.dtsi" +#include "ste-dbx5x0.dtsi" / { memory { diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts index c6bb07df2d1d..d8d3b99ab007 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/ste-hrefprev60.dts @@ -10,9 +10,9 @@ */ /dts-v1/; -#include "dbx5x0.dtsi" -#include "href.dtsi" -#include "stuib.dtsi" +#include "ste-dbx5x0.dtsi" +#include "ste-href.dtsi" +#include "ste-stuib.dtsi" / { model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts index 3d580d6447f9..6e52ebbf113f 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -10,9 +10,9 @@ */ /dts-v1/; -#include "dbx5x0.dtsi" -#include "href.dtsi" -#include "stuib.dtsi" +#include "ste-dbx5x0.dtsi" +#include "ste-href.dtsi" +#include "ste-stuib.dtsi" / { model = "ST-Ericsson HREF (v60+) platform with Device Tree"; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi new file mode 100644 index 000000000000..efddee9403c4 --- /dev/null +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -0,0 +1,95 @@ +/* + * Copyright 2012 ST-Ericsson + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <dt-bindings/pinctrl/nomadik.h> + +/ { + in_nopull: in_nopull { + ste,input = <INPUT_NOPULL>; + }; + + in_pu: input_pull_up { + ste,input = <INPUT_PULLUP>; + }; + + in_pd: input_pull_down { + ste,input = <INPUT_PULLDOWN>; + }; + + out_hi: output_high { + ste,output = <OUTPUT_HIGH>; + }; + + out_lo: output_low { + ste,output = <OUTPUT_LOW>; + }; + + gpio_out_lo: gpio_output_low { + ste,gpio = <GPIOMODE_ENABLED>; + ste,output = <OUTPUT_LOW>; + }; + + slpm_in_pu: slpm_in_pu { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-input = <SLPM_INPUT_PULLUP>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + }; + + slpm_in_wkup_pdis: slpm_in_wkup_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-input = <SLPM_DIR_INPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + slpm_out_lo: slpm_out_lo { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_OUTPUT_LOW>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + }; + + slpm_out_hi: slpm_out_hi { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_OUTPUT_HIGH>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + }; + + slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_OUTPUT_HIGH>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + slpm_out_wkup_pdis: slpm_out_wkup_pdis { + ste,sleep = <SLPM_ENABLED>; + ste,sleep-output = <SLPM_DIR_OUTPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + in_wkup_pdis: in_wkup_pdis { + ste,sleep-input = <SLPM_DIR_INPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + out_hi_wkup_pdis: out_hi_wkup_pdis { + ste,sleep-output = <SLPM_OUTPUT_HIGH>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; + + out_wkup_pdis: out_wkup_pdis { + ste,sleep-output = <SLPM_DIR_OUTPUT>; + ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; + ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; + }; +}; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index a3acfa7b3dc9..9169d3025f39 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -140,18 +140,30 @@ }; }; i2c0 { + i2c0_default_mux: i2c0_mux { + i2c0_default_mux { + ste,function = "i2c0"; + ste,pins = "i2c0_a_1"; + }; + }; i2c0_default_mode: i2c0_default { i2c0_default_cfg { ste,pins = "GPIO62_D3", "GPIO63_D2"; - ste,input = <1>; + ste,input = <0>; }; }; }; i2c1 { + i2c1_default_mux: i2c1_mux { + i2c1_default_mux { + ste,function = "i2c1"; + ste,pins = "i2c1_a_1"; + }; + }; i2c1_default_mode: i2c1_default { i2c1_default_cfg { ste,pins = "GPIO53_L4", "GPIO54_L3"; - ste,input = <1>; + ste,input = <0>; }; }; }; @@ -159,7 +171,7 @@ i2c2_default_mode: i2c2_default { i2c2_default_cfg { ste,pins = "GPIO73_C21", "GPIO74_C20"; - ste,input = <1>; + ste,input = <0>; }; }; }; @@ -682,13 +694,17 @@ /* I2C0 connected to the STw4811 power management chip */ i2c0 { - compatible = "i2c-gpio"; - gpios = <&gpio1 31 0>, /* sda */ - <&gpio1 30 0>; /* scl */ + compatible = "st,nomadik-i2c", "arm,primecell"; + reg = <0x101f8000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <20>; + clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&i2c0clk>, <&pclki2c0>; + clock-names = "mclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default_mode>; + pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; stw4811@2d { compatible = "st,stw4811"; @@ -698,13 +714,17 @@ /* I2C1 connected to various sensors */ i2c1 { - compatible = "i2c-gpio"; - gpios = <&gpio1 22 0>, /* sda */ - <&gpio1 21 0>; /* scl */ + compatible = "st,nomadik-i2c", "arm,primecell"; + reg = <0x101f7000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <21>; + clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&i2c1clk>, <&pclki2c1>; + clock-names = "mclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default_mode>; + pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; camera@2d { compatible = "st,camera"; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 49824be66845..f1fc128e249d 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "dbx5x0.dtsi" +#include "ste-dbx5x0.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -165,34 +165,6 @@ status = "okay"; }; - i2c@80004000 { - tc3589x@42 { - //compatible = "tc3589x"; - reg = <0x42>; - gpios = <&gpio6 25 0x4>; - interrupt-parent = <&gpio6>; - }; - tps61052@33 { - //compatible = "tps61052"; - reg = <0x33>; - }; - }; - - i2c@80128000 { - lp5521@33 { - // compatible = "lp5521"; - reg = <0x33>; - }; - lp5521@34 { - // compatible = "lp5521"; - reg = <0x34>; - }; - bh1780@29 { - // compatible = "rohm,bh1780gli"; - reg = <0x33>; - }; - }; - cpufreq-cooling { status = "okay"; }; @@ -310,6 +282,20 @@ compatible = "stericsson,ab8500-gpio"; }; + ext_regulators: ab8500-ext-regulators { + ab8500_ext1_reg: ab8500_ext1 { + regulator-name = "ab8500-ext-supply1"; + }; + + ab8500_ext2_reg_reg: ab8500_ext2 { + regulator-name = "ab8500-ext-supply2"; + }; + + ab8500_ext3_reg_reg: ab8500_ext3 { + regulator-name = "ab8500-ext-supply3"; + }; + }; + ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/ste-stuib.dtsi index 524e33240ad4..524e33240ad4 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/ste-stuib.dtsi diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts new file mode 100644 index 000000000000..eb4d73b6a090 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2013 Emilio López + * + * Emilio López <emilio@elopez.com.ar> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" + +/ { + model = "Mele A1000"; + compatible = "mele,a1000", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + phy-supply = <®_emac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + pinctrl@01c20800 { + emac_power_pin_a1000: emac_power_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_a1000: led_pins@0 { + allwinner,pins = "PH10", "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a1000>; + + red { + label = "a1000:red:usr"; + gpios = <&pio 7 10 0>; + }; + + blue { + label = "a1000:blue:usr"; + gpios = <&pio 7 20 0>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_emac_3v3: emac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&emac_power_pin_a1000>; + regulator-name = "emac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 15 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 757c4cd900ee..425a7db898c5 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -26,7 +26,7 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc@01c20000 { + soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; pinctrl-0 = <&emac_pins_a>; @@ -76,12 +76,12 @@ pinctrl-0 = <&led_pins_cubieboard>; blue { - label = "cubieboard::blue"; + label = "cubieboard:blue:usr"; gpios = <&pio 7 21 0>; /* LED1 */ }; green { - label = "cubieboard::green"; + label = "cubieboard:green:usr"; gpios = <&pio 7 20 0>; /* LED2 */ linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 3514b37d66bc..b3ae51fa9372 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -22,7 +22,7 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc@01c20000 { + soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; pinctrl-0 = <&emac_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 078ed7f618d7..0c1447c68059 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -22,7 +22,7 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc@01c20000 { + soc@01c00000 { uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b2bd6e124250..c32770a28acf 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -160,11 +160,10 @@ }; }; - soc@01c20000 { + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - reg = <0x01c20000 0x300000>; ranges; emac: ethernet@01c0b000 { diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 64dc0c42c43a..3c9f8b3cd3e3 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -18,7 +18,7 @@ model = "Olimex A10s-Olinuxino Micro"; compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; - soc@01c20000 { + soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; pinctrl-0 = <&emac_pins_a>; @@ -60,6 +60,31 @@ pinctrl-0 = <&uart3_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + at24@50 { + compatible = "at,24c16"; + pagesize = <16>; + reg = <0x50>; + read-only; + }; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; leds { diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 2307ce827ae0..ee0ff9ba1bca 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -157,11 +157,10 @@ }; }; - soc@01c20000 { + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - reg = <0x01c20000 0x300000>; ranges; emac: ethernet@01c0b000 { @@ -229,6 +228,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PB15", "PB16"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PB17", "PB18"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -282,5 +302,38 @@ clocks = <&apb1_gates 19>; status = "disabled"; }; + + i2c0: i2c@01c2ac00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <7>; + clocks = <&apb1_gates 0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@01c2b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <8>; + clocks = <&apb1_gates 1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@01c2b400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sun4i-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <9>; + clocks = <&apb1_gates 2>; + clock-frequency = <100000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 80497e376706..9e508dcc4245 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -22,7 +22,7 @@ bootargs = "earlyprintk console=ttyS0,115200"; }; - soc@01c20000 { + soc@01c00000 { pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { allwinner,pins = "PG9"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 7363211daf84..f6091dc0936c 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -150,11 +150,10 @@ }; }; - soc@01c20000 { + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - reg = <0x01c20000 0x300000>; ranges; intc: interrupt-controller@01c20400 { diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts new file mode 100644 index 000000000000..99c4b1847cab --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" + +/ { + model = "WITS A31 Colombus Evaluation Board"; + compatible = "wits,colombus", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + uart0: serial@01c28000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi new file mode 100644 index 000000000000..4d076ec24885 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -0,0 +1,156 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <0 18 1>, + <0 19 1>, + <0 20 1>, + <0 21 1>, + <0 22 1>; + clocks = <&osc>; + }; + + wdt1: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 0 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 1 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 2 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 3 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 4 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart5: serial@01c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <0 5 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts new file mode 100644 index 000000000000..d3395846491c --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -0,0 +1,34 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" + +/ { + model = "Olimex A20-Olinuxino Micro"; + compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; + + soc@01c00000 { + uart0: serial@01c28000 { + status = "okay"; + }; + + uart6: serial@01c29800 { + status = "okay"; + }; + + uart7: serial@01c29c00 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi new file mode 100644 index 000000000000..33391517118c --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -0,0 +1,172 @@ +/* + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M@01c20050 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <0 22 1>, + <0 23 1>, + <0 24 1>, + <0 25 1>, + <0 67 1>, + <0 68 1>; + clocks = <&osc24M>; + }; + + wdt: watchdog@01c20c90 { + compatible = "allwinner,sun4i-wdt"; + reg = <0x01c20c90 0x10>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 1 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 2 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 3 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 4 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 17 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart5: serial@01c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <0 18 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart6: serial@01c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <0 19 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart7: serial@01c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <0 20 1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index cb640eb6c932..60230288884b 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -791,7 +791,7 @@ regulator-boot-on; }; - dcdc3 { + tps65090_dcdc3_reg: dcdc3 { regulator-name = "vdd-ao"; regulator-always-on; regulator-boot-on; @@ -836,6 +836,182 @@ }; }; }; + + palmas: tps65913 { + compatible = "ti,palmas"; + reg = <0x58>; + interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + smps1-in-supply = <&tps65090_dcdc3_reg>; + smps3-in-supply = <&tps65090_dcdc3_reg>; + smps4-in-supply = <&tps65090_dcdc2_reg>; + smps7-in-supply = <&tps65090_dcdc2_reg>; + smps8-in-supply = <&tps65090_dcdc2_reg>; + smps9-in-supply = <&tps65090_dcdc2_reg>; + ldo1-in-supply = <&tps65090_dcdc2_reg>; + ldo2-in-supply = <&tps65090_dcdc2_reg>; + ldo3-in-supply = <&palmas_smps3_reg>; + ldo4-in-supply = <&tps65090_dcdc2_reg>; + ldo5-in-supply = <&vdd_ac_bat_reg>; + ldo6-in-supply = <&tps65090_dcdc2_reg>; + ldo7-in-supply = <&tps65090_dcdc2_reg>; + ldo8-in-supply = <&tps65090_dcdc3_reg>; + ldo9-in-supply = <&palmas_smps9_reg>; + ldoln-in-supply = <&tps65090_dcdc1_reg>; + ldousb-in-supply = <&tps65090_dcdc1_reg>; + + regulators { + smps12 { + regulator-name = "vddio-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas_smps3_reg: smps3 { + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps457 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8 { + regulator-name = "avdd-pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas_smps9_reg: smps9 { + regulator-name = "sdhci-vdd-sd-slot"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo1 { + regulator-name = "avdd-cam1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo2 { + regulator-name = "avdd-cam2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo3 { + regulator-name = "avdd-dsi-csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6 { + regulator-name = "vdd-sensor-2v85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo7 { + regulator-name = "vdd-af-cam1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + ldo9 { + regulator-name = "vddio-sdmmc-2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "hvdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldousb { + regulator-name = "avdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1 { + regulator-name = "rail-3v3"; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen2 { + regulator-name = "rail-5v0"; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + }; }; spi@7000da00 { @@ -850,6 +1026,13 @@ pmc { nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; }; ahub { @@ -870,6 +1053,15 @@ non-removable; }; + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&usb3_vbus_reg>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -883,6 +1075,35 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + linux,code = <102>; /* KEY_HOME */ + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + volume_down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ + }; + + volume_up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <115>; /* KEY_VOLUMEUP */ + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -951,6 +1172,16 @@ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&tps65090_dcdc1_reg>; }; + + vdd_cam_1v8_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&palmas_gpio 6 0>; + }; }; sound { @@ -964,7 +1195,9 @@ "Speakers", "SPORP", "Speakers", "SPORN", "Speakers", "SPOLP", - "Speakers", "SPOLN"; + "Speakers", "SPOLN", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&rt5640>; diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts deleted file mode 100644 index d5f8d3e0bde2..000000000000 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ /dev/null @@ -1,33 +0,0 @@ -/dts-v1/; - -#include "tegra114.dtsi" - -/ { - model = "NVIDIA Tegra114 Pluto evaluation board"; - compatible = "nvidia,pluto", "nvidia,tegra114"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - serial@70006300 { - status = "okay"; - }; - - pmc { - nvidia,invert-interrupt; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index abf6c40d28c6..2905145d8e59 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -430,6 +430,68 @@ status = "disable"; }; + usb@7d000000 { + compatible = "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USBD>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USB3>; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA114_CLK_USB3>, + <&tegra_car TEGRA114_CLK_PLL_U>, + <&tegra_car TEGRA114_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 5592be6f2f7a..d5c9bca01232 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -363,7 +363,7 @@ }; pmc { - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index d9f89cd879a7..e156ab30e763 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -335,7 +335,7 @@ regulator-always-on; }; - ldo0 { + pci_clk_reg: ldo0 { regulator-name = "vdd_ldo0,vddio_pex_clk"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -417,7 +417,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; @@ -425,6 +425,20 @@ nvidia,sys-clock-req-active-high; }; + pcie-controller { + pex-clk-supply = <&pci_clk_reg>; + vdd-supply = <&pci_vdd_reg>; + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + usb@c5000000 { status = "okay"; }; @@ -643,7 +657,7 @@ enable-active-high; }; - regulator@3 { + pci_vdd_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vdd_1v05"; @@ -651,8 +665,6 @@ regulator-max-microvolt = <1050000>; gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; enable-active-high; - /* Hack until board-harmony-pcie.c is removed */ - status = "disabled"; }; regulator@4 { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index cfd12763b1b2..8d71fc9d8a2f 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -417,7 +417,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; nvidia,cpu-pwr-off-time = <0>; nvidia,core-pwr-good-time = <3845 3845>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 365760b33a26..315aae26c3cd 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -518,7 +518,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; @@ -566,7 +566,6 @@ usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; dr_mode = "otg"; }; @@ -829,7 +828,9 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 24 0>; /* PD0 */ + gpio = <&gpio TEGRA_GPIO(D, 0) 0>; + regulator-always-on; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index c54faae7cfb3..7726dab3d08d 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -366,7 +366,7 @@ regulator-always-on; }; - ldo0 { + pci_clk_reg: ldo0 { regulator-name = "vdd_ldo0,vddio_pex_clk"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -459,7 +459,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; @@ -467,6 +467,11 @@ nvidia,sys-clock-req-active-high; }; + pcie-controller { + pex-clk-supply = <&pci_clk_reg>; + vdd-supply = <&pci_vdd_reg>; + }; + usb@c5008000 { status = "okay"; }; @@ -509,5 +514,15 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + pci_vdd_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; + }; }; }; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index c572c43751b1..3ada3cb67f07 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -32,6 +32,14 @@ }; }; + pcie-controller { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + }; + sound { compatible = "ad,tegra-audio-wm8903-tec", "nvidia,tegra-audio-wm8903"; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index ed4b901b0227..78deea5c0d21 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -302,7 +302,7 @@ }; pmc { - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; nvidia,core-pwr-good-time = <3845 3845>; @@ -310,9 +310,18 @@ nvidia,sys-clock-req-active-high; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&pci_clk_reg>; + vdd-supply = <&pci_vdd_reg>; + + pci@1,0 { + status = "okay"; + }; + }; + usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; }; usb-phy@c5000000 { @@ -411,7 +420,27 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio 170 0>; /* PV2 */ + gpio = <&gpio TEGRA_GPIO(V, 2) 0>; + regulator-always-on; + regulator-boot-on; + }; + + pci_clk_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci_vdd_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 7f8c28d1121f..aab872cd0530 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -494,7 +494,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; nvidia,cpu-pwr-off-time = <100>; nvidia,core-pwr-good-time = <3845 3845>; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index ab67c94db280..d33a73cf167c 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -497,7 +497,7 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; nvidia,cpu-pwr-off-time = <1000>; nvidia,core-pwr-good-time = <0 3845>; @@ -509,7 +509,6 @@ usb@c5000000 { status = "okay"; - nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>; }; usb-phy@c5000000 { @@ -519,7 +518,6 @@ usb@c5008000 { status = "okay"; - nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>; }; usb-phy@c5008000 { @@ -588,6 +586,8 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + regulator-always-on; + regulator-boot-on; }; vbus3_reg: regulator@3 { @@ -598,6 +598,8 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + regulator-always-on; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9653fd8288d2..df40b54fd8bc 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -455,6 +455,61 @@ #size-cells = <0>; }; + pcie-controller { + compatible = "nvidia,tegra20-pcie"; + device_type = "pci"; + reg = <0x80003000 0x00000800 /* PADS registers */ + 0x80003800 0x00000200 /* AFI registers */ + 0x90000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ + 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ + 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA20_CLK_PEX>, + <&tegra_car TEGRA20_CLK_AFI>, + <&tegra_car TEGRA20_CLK_PCIE_XCLK>, + <&tegra_car TEGRA20_CLK_PLL_E>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; @@ -477,13 +532,13 @@ <&tegra_car TEGRA20_CLK_USBD>; clock-names = "reg", "pll_u", "timer", "utmi-pads"; nvidia,has-legacy-mode; - hssync_start_delay = <9>; - idle_wait_delay = <17>; - elastic_limit = <16>; - term_range_adj = <6>; - xcvr_setup = <9>; - xcvr_lsfslew = <1>; - xcvr_lsrslew = <1>; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; status = "disabled"; }; @@ -527,13 +582,13 @@ <&tegra_car TEGRA20_CLK_CLK_M>, <&tegra_car TEGRA20_CLK_USBD>; clock-names = "reg", "pll_u", "timer", "utmi-pads"; - hssync_start_delay = <9>; - idle_wait_delay = <17>; - elastic_limit = <16>; - term_range_adj = <6>; - xcvr_setup = <9>; - xcvr_lsfslew = <2>; - xcvr_lsrslew = <2>; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 87c5f7b7c271..08cad696e89f 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -10,6 +10,40 @@ reg = <0x80000000 0x7ff00000>; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&sys_3v3_pexs_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + }; + + host1x { + hdmi { + status = "okay"; + + vdd-supply = <&sys_3v3_reg>; + pll-supply = <&vio_reg>; + + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmiddc>; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -76,6 +110,11 @@ nvidia,pull = <0>; nvidia,tristate = <0>; }; + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,pull = <2>; + }; sdio3 { nvidia,pins = "drive_sdio3"; nvidia,high-speed-mode = <0>; @@ -85,6 +124,10 @@ nvidia,slew-rate-rising = <1>; nvidia,slew-rate-falling = <1>; }; + gpv { + nvidia,pins = "drive_gpv"; + nvidia,pull-up-strength = <16>; + }; }; }; @@ -107,7 +150,7 @@ clock-frequency = <100000>; }; - i2c@7000c700 { + hdmiddc: i2c@7000c700 { status = "okay"; clock-frequency = <100000>; }; @@ -262,7 +305,7 @@ pmc { status = "okay"; nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; nvidia,cpu-pwr-off-time = <200>; nvidia,core-pwr-good-time = <3845 3845>; @@ -285,6 +328,15 @@ non-removable; }; + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -357,7 +409,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v_in_reg>; }; @@ -369,7 +421,7 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; gpio-open-drain; vin-supply = <&vdd_5v_in_reg>; }; @@ -421,7 +473,9 @@ nvidia,audio-routing = "Headphones", "HPOR", - "Headphones", "HPOL"; + "Headphones", "HPOL", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&rt5640>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index f65b53d32416..e19dbf238e5c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -31,6 +31,26 @@ reg = <0x80000000 0x40000000>; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&pex_hvdd_3v3_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -173,19 +193,6 @@ gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; }; - tps62361 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -286,6 +293,26 @@ }; }; }; + + nct1008 { + compatible = "onnn,nct1008"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; + }; + + tps62361 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; }; spi@7000da00 { @@ -307,7 +334,7 @@ pmc { status = "okay"; nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; + nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; nvidia,cpu-pwr-off-time = <200>; nvidia,core-pwr-good-time = <3845 3845>; @@ -330,6 +357,15 @@ non-removable; }; + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d8783f0fae63..0022c127e1d9 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -16,6 +16,76 @@ serial4 = &uarte; }; + pcie-controller { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800 /* PADS registers */ + 0x00003800 0x00000200 /* AFI registers */ + 0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ + GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIEX>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + host1x { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; @@ -561,6 +631,92 @@ status = "disabled"; }; + usb@7d000000 { + compatible = "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USBD>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <1>; + nvidia,xcvr-lsrslew = <1>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d004000 0x4000>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA30_CLK_USB2>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB3>; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA30_CLK_USB3>, + <&tegra_car TEGRA30_CLK_PLL_U>, + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts deleted file mode 100644 index 95892ec6c342..000000000000 --- a/arch/arm/boot/dts/u9540.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "dbx5x0.dtsi" - -/ { - model = "ST-Ericsson U9540 platform with Device Tree"; - compatible = "st-ericsson,u9540"; - - memory { - reg = <0x00000000 0x20000000>; - }; - - soc-u9500 { - uart@80120000 { - status = "okay"; - }; - - uart@80121000 { - status = "okay"; - }; - - uart@80007000 { - status = "okay"; - }; - - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio7 6 0x4>; // 230 - cd-inverted; - - status = "okay"; - }; - - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; - bus-width = <4>; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index d2803be4e1a8..759b0cd20013 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -125,6 +125,12 @@ clock-names = "apb_pclk"; }; + scc@7fff0000 { + compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; + reg = <0 0x7fff0000 0 0x1000>; + interrupts = <0 95 4>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index b3905f5bcaf9..1a58678b93fa 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -50,6 +50,13 @@ status = "okay"; }; +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_1>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_1>; diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts index 90e913fb64be..7a563d2523b0 100644 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/wm8850-w70v2.dts @@ -11,13 +11,14 @@ /dts-v1/; /include/ "wm8850.dtsi" +#include <dt-bindings/pwm/pwm.h> / { model = "Wondermedia WM8850-W70v2 Tablet"; backlight { compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 1>; /* duty inverted */ + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 40 60 80 100 130 190 255>; default-brightness-level = <5>; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 6f54a64850eb..e32b92b949d2 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -41,8 +41,8 @@ L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; - arm,data-latency = <2 3 2>; - arm,tag-latency = <2 3 2>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S index 80f033614a1f..39c96df3477a 100644 --- a/arch/arm/common/mcpm_head.S +++ b/arch/arm/common/mcpm_head.S @@ -151,7 +151,7 @@ mcpm_setup_leave: mov r0, #INBOUND_NOT_COMING_UP strb r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND] - dsb + dsb st sev mov r0, r11 diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S index ff198583f683..8b7df283fedf 100644 --- a/arch/arm/common/vlock.S +++ b/arch/arm/common/vlock.S @@ -42,7 +42,7 @@ dmb mov \rscratch, #0 strb \rscratch, [\rbase, \rcpu] - dsb + dsb st sev .endm @@ -102,7 +102,7 @@ ENTRY(vlock_unlock) dmb mov r1, #VLOCK_OWNER_NONE strb r1, [r0, #VLOCK_OWNER_OFFSET] - dsb + dsb st sev bx lr ENDPROC(vlock_unlock) diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig index dab5a7dfadc6..1ce39940795d 100644 --- a/arch/arm/configs/ape6evm_defconfig +++ b/arch/arm/configs/ape6evm_defconfig @@ -54,7 +54,8 @@ CONFIG_NETDEVICES=y CONFIG_SMC91X=y CONFIG_SMSC911X=y # CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set CONFIG_SERIAL_NONSTANDARD=y @@ -71,6 +72,9 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y # CONFIG_IOMMU_SUPPORT is not set # CONFIG_DNOTIFY is not set CONFIG_TMPFS=y diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 65edf6d47215..6e4931097dd4 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -42,6 +42,18 @@ CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_PROC_DEVICETREE=y @@ -112,7 +124,6 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y CONFIG_DEBUG_INFO=y # CONFIG_FTRACE is not set -CONFIG_DEBUG_LL=y CONFIG_CRC_CCITT=y CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=y diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index 845f5cdf62b5..e7e94948d194 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig @@ -82,6 +82,13 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HWMON is not set CONFIG_I2C=y CONFIG_I2C_RCAR=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_RCAR_VIN=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_VIDEO_ML86V7667=y CONFIG_SPI=y CONFIG_SPI_SH_HSPI=y CONFIG_USB=y diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 4364eff5b01e..110105476848 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -13,6 +13,9 @@ CONFIG_ARCH_DOVE=y CONFIG_MACH_DOVE_DB=y CONFIG_MACH_CM_A510=y CONFIG_MACH_DOVE_DT=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -78,6 +81,7 @@ CONFIG_SPI_ORION=y CONFIG_THERMAL=y CONFIG_DOVE_THERMAL=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_STORAGE=y diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig deleted file mode 100644 index bffe68e190a3..000000000000 --- a/arch/arm/configs/exynos4_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_EXYNOS=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 -CONFIG_MACH_SMDKC210=y -CONFIG_MACH_ARMLEX4210=y -CONFIG_MACH_UNIVERSAL_C210=y -CONFIG_MACH_NURI=y -CONFIG_MACH_ORIGEN=y -CONFIG_MACH_SMDK4412=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CRAMFS=y -CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_INFO=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index f07a847b00c9..e958ebe79779 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -17,16 +16,18 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_MXC=y CONFIG_ARCH_MULTI_V4T=y CONFIG_ARCH_MULTI_V5=y # CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_MXC=y +CONFIG_MXC_IRQ_PRIOR=y CONFIG_ARCH_MX1ADS=y CONFIG_MACH_SCB9328=y CONFIG_MACH_APF9328=y CONFIG_MACH_MX21ADS=y CONFIG_MACH_MX25_3DS=y CONFIG_MACH_EUKREA_CPUIMX25SD=y +CONFIG_MACH_IMX25_DT=y CONFIG_MACH_MX27ADS=y CONFIG_MACH_PCM038=y CONFIG_MACH_CPUIMX27=y @@ -39,8 +40,6 @@ CONFIG_MACH_PCA100=y CONFIG_MACH_MXT_TD60=y CONFIG_MACH_IMX27IPCAM=y CONFIG_MACH_IMX27_DT=y -CONFIG_MXC_IRQ_PRIOR=y -CONFIG_MXC_PWM=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -67,7 +66,6 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -123,24 +121,20 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=y -CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_OV2640=y CONFIG_VIDEO_MX2=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=y +CONFIG_SOC_CAMERA_OV2640=y CONFIG_FB=y CONFIG_FB_IMX=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y @@ -157,7 +151,6 @@ CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y -CONFIG_USB_ULPI=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -198,3 +191,5 @@ CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 06686e7303a9..5d488c24b132 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_KERNEL_LZO=y CONFIG_SYSVIPC=y @@ -17,10 +16,8 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_MXC=y CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_MACH_IMX31_DT=y +CONFIG_ARCH_MXC=y CONFIG_MACH_MX31LILLY=y CONFIG_MACH_MX31LITE=y CONFIG_MACH_PCM037=y @@ -30,6 +27,7 @@ CONFIG_MACH_MX31MOBOARD=y CONFIG_MACH_QONG=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_KZM_ARM11_01=y +CONFIG_MACH_IMX31_DT=y CONFIG_MACH_PCM043=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_VPR200=y @@ -39,7 +37,6 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_VF610=y -CONFIG_MXC_PWM=y CONFIG_SMP=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT_VOLUNTARY=y @@ -64,20 +61,24 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_INET_LRO is not set CONFIG_IPV6=y CONFIG_NETFILTER=y -# CONFIG_WIRELESS is not set +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set +CONFIG_IMX_WEIM=y CONFIG_CONNECTOR=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y CONFIG_MTD_SST25L=y @@ -88,6 +89,7 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SRAM=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y # CONFIG_SCSI_PROC_FS is not set @@ -98,10 +100,11 @@ CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y CONFIG_PATA_IMX=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set CONFIG_CS89x0=y CONFIG_CS89x0_PLATFORM=y # CONFIG_NET_VENDOR_FARADAY is not set @@ -115,7 +118,7 @@ CONFIG_SMC91X=y CONFIG_SMC911X=y CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_WLAN is not set +CONFIG_BRCMFMAC=m # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m @@ -124,6 +127,7 @@ CONFIG_KEYBOARD_IMX=y CONFIG_MOUSE_PS2=m CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_MC13783=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y @@ -133,13 +137,13 @@ CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_DEVKMEM is not set CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MXC_RNGA=y -CONFIG_I2C=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y # CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_ALGOBIT=m CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_I2C_IMX=y @@ -155,30 +159,26 @@ CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=y -CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_MX3=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=y CONFIG_SOC_CAMERA_OV2640=y CONFIG_DRM=y -CONFIG_VIDEO_MX3=y -CONFIG_FB=y -CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y @@ -192,11 +192,12 @@ CONFIG_SND_SOC_IMX_MC13783=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y -CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y @@ -213,9 +214,10 @@ CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y CONFIG_STAGING=y CONFIG_DRM_IMX=y -CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_FB_HELPER=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3_CORE=y CONFIG_DRM_IMX_IPUV3=y CONFIG_COMMON_CLK_DEBUG=y @@ -269,3 +271,6 @@ CONFIG_CRC_CCITT=m CONFIG_CRC_T10DIF=y CONFIG_CRC7=m CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 62e968cac9dc..1f36b823905f 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -104,6 +104,7 @@ CONFIG_IP_SCTP=y CONFIG_VLAN_8021Q=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CMA=y +CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 0f2aa61911a3..0ae0eaebf6b2 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -10,49 +10,18 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_KIRKWOOD=y CONFIG_MACH_D2NET_V2=y -CONFIG_MACH_DB88F6281_BP=y -CONFIG_MACH_DOCKSTAR=y -CONFIG_MACH_ESATA_SHEEVAPLUG=y -CONFIG_MACH_GURUPLUG=y -CONFIG_MACH_INETSPACE_V2=y -CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_NET2BIG_V2=y CONFIG_MACH_NET5BIG_V2=y -CONFIG_MACH_NETSPACE_MAX_V2=y -CONFIG_MACH_NETSPACE_V2=y CONFIG_MACH_OPENRD_BASE=y CONFIG_MACH_OPENRD_CLIENT=y CONFIG_MACH_OPENRD_ULTIMATE=y CONFIG_MACH_RD88F6192_NAS=y CONFIG_MACH_RD88F6281=y -CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_T5325=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y -CONFIG_MACH_CLOUDBOX_DT=y -CONFIG_MACH_DB88F628X_BP_DT=y -CONFIG_MACH_DLINK_KIRKWOOD_DT=y -CONFIG_MACH_DOCKSTAR_DT=y -CONFIG_MACH_DREAMPLUG_DT=y -CONFIG_MACH_GOFLEXNET_DT=y -CONFIG_MACH_GURUPLUG_DT=y -CONFIG_MACH_IB62X0_DT=y -CONFIG_MACH_ICONNECT_DT=y -CONFIG_MACH_INETSPACE_V2_DT=y -CONFIG_MACH_IOMEGA_IX2_200_DT=y -CONFIG_MACH_KM_KIRKWOOD_DT=y -CONFIG_MACH_LSXL_DT=y -CONFIG_MACH_MPLCEC4_DT=y -CONFIG_MACH_NETSPACE_LITE_V2_DT=y -CONFIG_MACH_NETSPACE_MAX_V2_DT=y -CONFIG_MACH_NETSPACE_MINI_V2_DT=y -CONFIG_MACH_NETSPACE_V2_DT=y -CONFIG_MACH_NSA310_DT=y -CONFIG_MACH_OPENBLOCKS_A6_DT=y -CONFIG_MACH_READYNAS_DT=y -CONFIG_MACH_SHEEVAPLUG_DT=y -CONFIG_MACH_TOPKICK_DT=y -CONFIG_MACH_TS219_DT=y +CONFIG_ARCH_KIRKWOOD_DT=y +CONFIG_MACH_MV88F6281GTW_GE_DT=y # CONFIG_CPU_FEROCEON_OLD_ID is not set CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y @@ -92,6 +61,7 @@ CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ORION=y CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m @@ -100,9 +70,9 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_MV=y CONFIG_NETDEVICES=y -CONFIG_MII=y CONFIG_NET_DSA_MV88E6123_61_65=y CONFIG_MV643XX_ETH=y +CONFIG_R8169=y CONFIG_MARVELL_PHY=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_SDIO=y @@ -123,9 +93,11 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_ADT7475=y +CONFIG_SENSORS_LM63=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_LM85=y CONFIG_THERMAL=y -CONFIG_KIRKWOOD_THERMAL=y CONFIG_WATCHDOG=y CONFIG_ORION_WATCHDOG=y CONFIG_HID_DRAGONRISE=y @@ -164,6 +136,8 @@ CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RS5C372=y +CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_MV=y CONFIG_DMADEVICES=y @@ -171,6 +145,7 @@ CONFIG_MV_XOR=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -186,12 +161,12 @@ CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y -CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_INFO=y CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_INFO=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig new file mode 100644 index 000000000000..e777ef22b801 --- /dev/null +++ b/arch/arm/configs/lager_defconfig @@ -0,0 +1,120 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +CONFIG_SLAB=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SHMOBILE=y +CONFIG_ARCH_R8A7790=y +CONFIG_MACH_LAGER=y +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_458693=y +CONFIG_ARM_ERRATA_460075=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NETDEVICES=y +# CONFIG_NET_CORE is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_SH_ETH=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=10 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_SH_MOBILE=y +CONFIG_GPIO_SH_PFC=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_RCAR=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_RCAR_THERMAL=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SH_MMCIF=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_SH_DMAE=y +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 494e70aeb9e1..000e9205b2b9 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig @@ -29,6 +29,7 @@ CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on" CONFIG_CMDLINE_FORCE=y CONFIG_KEXEC=y @@ -84,6 +85,13 @@ CONFIG_GPIO_RCAR=y CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_SSB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_RCAR_VIN=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_VIDEO_ADV7180=y CONFIG_USB=y CONFIG_USB_RCAR_PHY=y CONFIG_MMC=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 731814e2c189..594d706b641f 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -39,6 +39,8 @@ CONFIG_MVNETA=y CONFIG_MARVELL_PHY=y CONFIG_MWIFIEX=y CONFIG_MWIFIEX_SDIO=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_I2C=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 1d6d8fb7f4a1..4555c025629a 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -27,7 +26,6 @@ CONFIG_ARCH_MXS=y # CONFIG_ARM_THUMB is not set CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y -CONFIG_AUTO_ZRELADDR=y CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y @@ -43,8 +41,6 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m CONFIG_CAN_FLEXCAN=m # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y @@ -52,7 +48,6 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y @@ -67,12 +62,12 @@ CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y CONFIG_ENC28J60=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC95XX=y CONFIG_SMSC_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_REALTEK_PHY=y CONFIG_MICREL_PHY=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC95XX=y # CONFIG_WLAN is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=y @@ -110,7 +105,6 @@ CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y @@ -119,9 +113,9 @@ CONFIG_SND_MXS_SOC=y CONFIG_SND_SOC_MXS_SGTL5000=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_STORAGE=y CONFIG_USB_PHY=y CONFIG_USB_MXS_PHY=y CONFIG_MMC=y @@ -143,9 +137,9 @@ CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y CONFIG_STAGING=y CONFIG_MXS_LRADC=y -CONFIG_IIO_SYSFS_TRIGGER=y CONFIG_COMMON_CLK_DEBUG=y CONFIG_IIO=y +CONFIG_IIO_SYSFS_TRIGGER=y CONFIG_PWM=y CONFIG_PWM_MXS=y CONFIG_EXT2_FS=y @@ -173,14 +167,14 @@ CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y CONFIG_FRAME_WARN=2048 -CONFIG_MAGIC_SYSRQ=y CONFIG_UNUSED_SYMBOLS=y +CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_LOCKUP_DETECTOR=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_INFO=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_USER=y @@ -188,3 +182,4 @@ CONFIG_DEBUG_USER=y # CONFIG_CRYPTO_HW is not set CONFIG_CRC_ITU_T=m CONFIG_CRC7=m +CONFIG_FONTS=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 5339e6a4d639..254cf0539439 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -78,6 +78,7 @@ CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_CMA=y +CONFIG_DMA_CMA=y CONFIG_CONNECTOR=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -185,13 +186,11 @@ CONFIG_OMAP2_DSS_RFBI=y CONFIG_OMAP2_DSS_SDI=y CONFIG_OMAP2_DSS_DSI=y CONFIG_FB_OMAP2=m -CONFIG_PANEL_GENERIC_DPI=m -CONFIG_PANEL_TFP410=m -CONFIG_PANEL_SHARP_LS037V7DW01=m -CONFIG_PANEL_NEC_NL8048HL11_01B=m -CONFIG_PANEL_TAAL=m -CONFIG_PANEL_TPO_TD043MTEA1=m -CONFIG_PANEL_ACX565AKM=m +CONFIG_DISPLAY_ENCODER_TFP410=m +CONFIG_DISPLAY_ENCODER_TPD12S015=m +CONFIG_DISPLAY_CONNECTOR_DVI=m +CONFIG_DISPLAY_CONNECTOR_HDMI=m +CONFIG_DISPLAY_PANEL_DPI=m CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y @@ -306,3 +305,4 @@ CONFIG_TI_DAVINCI_MDIO=y CONFIG_TI_DAVINCI_CPDMA=y CONFIG_TI_CPSW=y CONFIG_AT803X_PHY=y +CONFIG_SOC_DRA7XX=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 1effb43dab80..ea042e80e54d 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -1,3 +1,4 @@ +CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y @@ -26,8 +27,11 @@ CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y -CONFIG_TEGRA_PCI=y CONFIG_TEGRA_EMC_SCALING_ENABLE=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_TEGRA=y +CONFIG_PCIEPORTBUS=y CONFIG_SMP=y CONFIG_PREEMPT=y CONFIG_AEABI=y @@ -79,6 +83,7 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_CMA=y +CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y @@ -91,6 +96,7 @@ CONFIG_ISL29003=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y +CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y @@ -105,6 +111,7 @@ CONFIG_RT2800USB=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_TEGRA=y +CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MPU3050=y # CONFIG_LEGACY_PTYS is not set @@ -177,6 +184,7 @@ CONFIG_SND_SOC_TEGRA_WM8903=y CONFIG_SND_SOC_TEGRA_TRIMSLICE=y CONFIG_SND_SOC_TEGRA_ALC5632=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_ACM=y diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index e406d575c94f..5665134bfa3e 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -17,7 +17,8 @@ int arch_timer_arch_init(void); * nicely work out which register we want, and chuck away the rest of * the code. At least it does so with a recent GCC (4.6.3). */ -static inline void arch_timer_reg_write(const int access, const int reg, u32 val) +static __always_inline +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) { if (access == ARCH_TIMER_PHYS_ACCESS) { switch (reg) { @@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); break; } - } - - if (access == ARCH_TIMER_VIRT_ACCESS) { + } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { case ARCH_TIMER_REG_CTRL: asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); @@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val isb(); } -static inline u32 arch_timer_reg_read(const int access, const int reg) +static __always_inline +u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) { u32 val = 0; @@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); break; } - } - - if (access == ARCH_TIMER_VIRT_ACCESS) { + } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { case ARCH_TIMER_REG_CTRL: asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index a5fef710af32..fcc1b5bf6979 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -220,9 +220,9 @@ #ifdef CONFIG_SMP #if __LINUX_ARM_ARCH__ >= 7 .ifeqs "\mode","arm" - ALT_SMP(dmb) + ALT_SMP(dmb ish) .else - ALT_SMP(W(dmb)) + ALT_SMP(W(dmb) ish) .endif #elif __LINUX_ARM_ARCH__ == 6 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 8dcd9c702d90..60f15e274e6d 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -14,27 +14,27 @@ #endif #if __LINUX_ARM_ARCH__ >= 7 -#define isb() __asm__ __volatile__ ("isb" : : : "memory") -#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") -#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") +#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") +#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") +#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 -#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ +#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") -#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ +#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ : : "r" (0) : "memory") -#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ +#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ : : "r" (0) : "memory") #elif defined(CONFIG_CPU_FA526) -#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ +#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") -#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ +#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ : : "r" (0) : "memory") -#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define dmb(x) __asm__ __volatile__ ("" : : : "memory") #else -#define isb() __asm__ __volatile__ ("" : : : "memory") -#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ +#define isb(x) __asm__ __volatile__ ("" : : : "memory") +#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ : : "r" (0) : "memory") -#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif #ifdef CONFIG_ARCH_HAS_BARRIERS @@ -42,7 +42,7 @@ #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) #define rmb() dsb() -#define wmb() mb() +#define wmb() do { dsb(st); outer_sync(); } while (0) #else #define mb() barrier() #define rmb() barrier() @@ -54,9 +54,9 @@ #define smp_rmb() barrier() #define smp_wmb() barrier() #else -#define smp_mb() dmb() -#define smp_rmb() dmb() -#define smp_wmb() dmb() +#define smp_mb() dmb(ish) +#define smp_rmb() smp_mb() +#define smp_wmb() dmb(ishst) #endif #define read_barrier_depends() do { } while(0) diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 17d0ae8672fa..15f2d5bf8875 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -268,8 +268,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ -#define flush_cache_user_range(start,end) \ - __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) +#define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e) /* * Perform necessary cache operations to ensure that data previously @@ -352,7 +351,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end) * set_pte_at() called from vmap_pte_range() does not * have a DSB after cleaning the cache line. */ - dsb(); + dsb(ishst); } static inline void flush_cache_vunmap(unsigned long start, unsigned long end) diff --git a/arch/arm/include/asm/dma-contiguous.h b/arch/arm/include/asm/dma-contiguous.h index 3ed37b4d93da..4f8e9e5514b1 100644 --- a/arch/arm/include/asm/dma-contiguous.h +++ b/arch/arm/include/asm/dma-contiguous.h @@ -2,10 +2,9 @@ #define ASMARM_DMA_CONTIGUOUS_H #ifdef __KERNEL__ -#ifdef CONFIG_CMA +#ifdef CONFIG_DMA_CMA #include <linux/types.h> -#include <asm-generic/dma-contiguous.h> void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 56211f2084ef..f4b46d39b9cf 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -19,8 +19,6 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef struct user_fp elf_fpregset_t; -#define EM_ARM 40 - #define EF_ARM_EABI_MASK 0xff000000 #define EF_ARM_EABI_UNKNOWN 0x00000000 #define EF_ARM_EABI_VER1 0x01000000 diff --git a/arch/arm/include/asm/hardware/debug-8250.S b/arch/arm/include/asm/hardware/debug-8250.S deleted file mode 100644 index 22c689255e6e..000000000000 --- a/arch/arm/include/asm/hardware/debug-8250.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/include/asm/hardware/debug-8250.S - * - * Copyright (C) 1994-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/serial_reg.h> - - .macro senduart,rd,rx - strb \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - .macro waituart,rd,rx -#ifdef FLOW_CONTROL -1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] - tst \rd, #UART_MSR_CTS - beq 1001b -#endif - .endm diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 472ac7091003..9b28c41f4ba9 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -64,7 +64,7 @@ void kvm_clear_hyp_idmap(void); static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) { - pte_val(*pte) = new_pte; + *pte = new_pte; /* * flush_pmd_entry just takes a void pointer and cleans the necessary * cache entries, so we can reuse the function for ptes. diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h deleted file mode 100644 index f77ffc1eb0c2..000000000000 --- a/arch/arm/include/asm/localtimer.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/include/asm/localtimer.h - * - * Copyright (C) 2004-2005 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_LOCALTIMER_H -#define __ASM_ARM_LOCALTIMER_H - -#include <linux/errno.h> - -struct clock_event_device; - -struct local_timer_ops { - int (*setup)(struct clock_event_device *); - void (*stop)(struct clock_event_device *); -}; - -#ifdef CONFIG_LOCAL_TIMERS -/* - * Register a local timer driver - */ -int local_timer_register(struct local_timer_ops *); -#else -static inline int local_timer_register(struct local_timer_ops *ops) -{ - return -ENXIO; -} -#endif - -#endif diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 441efc491b50..69b879ac0289 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -65,12 +65,12 @@ struct machine_desc { /* * Current machine - only accessible during boot. */ -extern struct machine_desc *machine_desc; +extern const struct machine_desc *machine_desc; /* * Machine type table - also only accessible during boot */ -extern struct machine_desc __arch_info_begin[], __arch_info_end[]; +extern const struct machine_desc __arch_info_begin[], __arch_info_end[]; #define for_each_machine_desc(p) \ for (p = __arch_info_begin; p < __arch_info_end; p++) diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index a1c90d7feb0e..454d642a4070 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -36,6 +36,8 @@ struct hw_pci { resource_size_t start, resource_size_t size, resource_size_t align); + void (*add_bus)(struct pci_bus *bus); + void (*remove_bus)(struct pci_bus *bus); }; /* @@ -63,6 +65,8 @@ struct pci_sys_data { resource_size_t start, resource_size_t size, resource_size_t align); + void (*add_bus)(struct pci_bus *bus); + void (*remove_bus)(struct pci_bus *bus); void *private_data; /* platform controller private data */ }; diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h index 00ca5f92648e..c2f5102ae659 100644 --- a/arch/arm/include/asm/memblock.h +++ b/arch/arm/include/asm/memblock.h @@ -4,8 +4,7 @@ struct meminfo; struct machine_desc; -extern void arm_memblock_init(struct meminfo *, struct machine_desc *); - +void arm_memblock_init(struct meminfo *, const struct machine_desc *); phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align); #endif diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 0d3a28dbc8e5..ed690c49ef93 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -12,6 +12,8 @@ enum { ARM_SEC_CORE, ARM_SEC_EXIT, ARM_SEC_DEVEXIT, + ARM_SEC_HOT, + ARM_SEC_UNLIKELY, ARM_SEC_MAX, }; diff --git a/arch/arm/include/asm/neon.h b/arch/arm/include/asm/neon.h new file mode 100644 index 000000000000..8f730fe70093 --- /dev/null +++ b/arch/arm/include/asm/neon.h @@ -0,0 +1,36 @@ +/* + * linux/arch/arm/include/asm/neon.h + * + * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm/hwcap.h> + +#define cpu_has_neon() (!!(elf_hwcap & HWCAP_NEON)) + +#ifdef __ARM_NEON__ + +/* + * If you are affected by the BUILD_BUG below, it probably means that you are + * using NEON code /and/ calling the kernel_neon_begin() function from the same + * compilation unit. To prevent issues that may arise from GCC reordering or + * generating(1) NEON instructions outside of these begin/end functions, the + * only supported way of using NEON code in the kernel is by isolating it in a + * separate compilation unit, and calling it from another unit from inside a + * kernel_neon_begin/kernel_neon_end pair. + * + * (1) Current GCC (4.7) might generate NEON instructions at O3 level if + * -mpfu=neon is set. + */ + +#define kernel_neon_begin() \ + BUILD_BUG_ON_MSG(1, "kernel_neon_begin() called from NEON code") + +#else +void kernel_neon_begin(void); +#endif +void kernel_neon_end(void); diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 04aeb02d2e11..be956dbf6bae 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -100,7 +100,7 @@ extern pgprot_t pgprot_s2_device; #define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP) #define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP) #define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY) -#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY) +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR) #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE) #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN) diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h index a219227c3e43..4a2985e21969 100644 --- a/arch/arm/include/asm/prom.h +++ b/arch/arm/include/asm/prom.h @@ -15,13 +15,13 @@ #ifdef CONFIG_OF -extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); +extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys); extern void arm_dt_memblock_reserve(void); extern void __init arm_dt_init_cpu_maps(void); #else /* CONFIG_OF */ -static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys) +static inline const struct machine_desc *setup_machine_fdt(unsigned int dt_phys) { return NULL; } diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index b07c09e5a0ac..4f2c28060c9a 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -46,7 +46,7 @@ static inline void dsb_sev(void) { #if __LINUX_ARM_ARCH__ >= 7 __asm__ __volatile__ ( - "dsb\n" + "dsb ishst\n" SEV ); #else diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index fa09e6b49bf1..c99e259469f7 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -4,6 +4,16 @@ #include <linux/thread_info.h> /* + * For v7 SMP cores running a preemptible kernel we may be pre-empted + * during a TLB maintenance operation, so execute an inner-shareable dsb + * to ensure that the maintenance completes in case we migrate to another + * CPU. + */ +#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7) +#define finish_arch_switch(prev) dsb(ish) +#endif + +/* * switch_to(prev, next) should switch from task `prev' to `next' * `prev' will never be the same as `next'. schedule() itself * contains the memory barrier to tell GCC not to cache `current'. diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 2b8114fcba09..df5e13d64f2c 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -43,6 +43,16 @@ struct cpu_context_save { __u32 extra[2]; /* Xscale 'acc' register, etc */ }; +struct arm_restart_block { + union { + /* For user cache flushing */ + struct { + unsigned long start; + unsigned long end; + } cache; + }; +}; + /* * low level task data that entry.S needs immediate access to. * __switch_to() assumes cpu_context follows immediately after cpu_domain. @@ -68,6 +78,7 @@ struct thread_info { unsigned long thumbee_state; /* ThumbEE Handler Base register */ #endif struct restart_block restart_block; + struct arm_restart_block arm_restart_block; }; #define INIT_THREAD_INFO(tsk) \ diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index f467e9b3f8d5..38960264040c 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -319,67 +319,110 @@ extern struct cpu_tlb_fns cpu_tlb; #define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg) #define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg) -static inline void local_flush_tlb_all(void) +static inline void __local_flush_tlb_all(void) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; - if (tlb_flag(TLB_WB)) - dsb(); - tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero); tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); - tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero); +} + +static inline void local_flush_tlb_all(void) +{ + const int zero = 0; + const unsigned int __tlb_flag = __cpu_tlb_flags; + + if (tlb_flag(TLB_WB)) + dsb(nshst); + + __local_flush_tlb_all(); + tlb_op(TLB_V7_UIS_FULL, "c8, c7, 0", zero); if (tlb_flag(TLB_BARRIER)) { - dsb(); + dsb(nsh); isb(); } } -static inline void local_flush_tlb_mm(struct mm_struct *mm) +static inline void __flush_tlb_all(void) { const int zero = 0; - const int asid = ASID(mm); const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_WB)) - dsb(); + dsb(ishst); + + __local_flush_tlb_all(); + tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero); + + if (tlb_flag(TLB_BARRIER)) { + dsb(ish); + isb(); + } +} + +static inline void __local_flush_tlb_mm(struct mm_struct *mm) +{ + const int zero = 0; + const int asid = ASID(mm); + const unsigned int __tlb_flag = __cpu_tlb_flags; if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) { - if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { + if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) { tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero); tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); } - put_cpu(); } tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid); tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid); tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); +} + +static inline void local_flush_tlb_mm(struct mm_struct *mm) +{ + const int asid = ASID(mm); + const unsigned int __tlb_flag = __cpu_tlb_flags; + + if (tlb_flag(TLB_WB)) + dsb(nshst); + + __local_flush_tlb_mm(mm); + tlb_op(TLB_V7_UIS_ASID, "c8, c7, 2", asid); + + if (tlb_flag(TLB_BARRIER)) + dsb(nsh); +} + +static inline void __flush_tlb_mm(struct mm_struct *mm) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + + if (tlb_flag(TLB_WB)) + dsb(ishst); + + __local_flush_tlb_mm(mm); #ifdef CONFIG_ARM_ERRATA_720789 - tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero); + tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0); #else - tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid); + tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm)); #endif if (tlb_flag(TLB_BARRIER)) - dsb(); + dsb(ish); } static inline void -local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) +__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); - if (tlb_flag(TLB_WB)) - dsb(); - if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) && cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); @@ -392,6 +435,36 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr); tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr); tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); +} + +static inline void +local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + + uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); + + if (tlb_flag(TLB_WB)) + dsb(nshst); + + __local_flush_tlb_page(vma, uaddr); + tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", uaddr); + + if (tlb_flag(TLB_BARRIER)) + dsb(nsh); +} + +static inline void +__flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + + uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); + + if (tlb_flag(TLB_WB)) + dsb(ishst); + + __local_flush_tlb_page(vma, uaddr); #ifdef CONFIG_ARM_ERRATA_720789 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK); #else @@ -399,19 +472,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) #endif if (tlb_flag(TLB_BARRIER)) - dsb(); + dsb(ish); } -static inline void local_flush_tlb_kernel_page(unsigned long kaddr) +static inline void __local_flush_tlb_kernel_page(unsigned long kaddr) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; - kaddr &= PAGE_MASK; - - if (tlb_flag(TLB_WB)) - dsb(); - tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr); tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); @@ -421,26 +489,75 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr); tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr); tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); +} + +static inline void local_flush_tlb_kernel_page(unsigned long kaddr) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + + kaddr &= PAGE_MASK; + + if (tlb_flag(TLB_WB)) + dsb(nshst); + + __local_flush_tlb_kernel_page(kaddr); + tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", kaddr); + + if (tlb_flag(TLB_BARRIER)) { + dsb(nsh); + isb(); + } +} + +static inline void __flush_tlb_kernel_page(unsigned long kaddr) +{ + const unsigned int __tlb_flag = __cpu_tlb_flags; + + kaddr &= PAGE_MASK; + + if (tlb_flag(TLB_WB)) + dsb(ishst); + + __local_flush_tlb_kernel_page(kaddr); tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr); if (tlb_flag(TLB_BARRIER)) { - dsb(); + dsb(ish); isb(); } } +/* + * Branch predictor maintenance is paired with full TLB invalidation, so + * there is no need for any barriers here. + */ +static inline void __local_flush_bp_all(void) +{ + const int zero = 0; + const unsigned int __tlb_flag = __cpu_tlb_flags; + + if (tlb_flag(TLB_V6_BP)) + asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); +} + static inline void local_flush_bp_all(void) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; + __local_flush_bp_all(); if (tlb_flag(TLB_V7_UIS_BP)) - asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); - else if (tlb_flag(TLB_V6_BP)) asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); +} - if (tlb_flag(TLB_BARRIER)) - isb(); +static inline void __flush_bp_all(void) +{ + const int zero = 0; + const unsigned int __tlb_flag = __cpu_tlb_flags; + + __local_flush_bp_all(); + if (tlb_flag(TLB_V7_UIS_BP)) + asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); } #include <asm/cputype.h> @@ -461,7 +578,7 @@ static inline void dummy_flush_tlb_a15_erratum(void) * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. */ asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(); + dsb(ish); } #else static inline int erratum_a15_798181(void) @@ -495,7 +612,7 @@ static inline void flush_pmd_entry(void *pmd) tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd); if (tlb_flag(TLB_WB)) - dsb(); + dsb(ishst); } static inline void clean_pmd_entry(void *pmd) diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h new file mode 100644 index 000000000000..a53cdb8f068c --- /dev/null +++ b/arch/arm/include/asm/types.h @@ -0,0 +1,40 @@ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +#include <asm-generic/int-ll64.h> + +/* + * The C99 types uintXX_t that are usually defined in 'stdint.h' are not as + * unambiguous on ARM as you would expect. For the types below, there is a + * difference on ARM between GCC built for bare metal ARM, GCC built for glibc + * and the kernel itself, which results in build errors if you try to build with + * -ffreestanding and include 'stdint.h' (such as when you include 'arm_neon.h' + * in order to use NEON intrinsics) + * + * As the typedefs for these types in 'stdint.h' are based on builtin defines + * supplied by GCC, we can tweak these to align with the kernel's idea of those + * types, so 'linux/types.h' and 'stdint.h' can be safely included from the same + * source file (provided that -ffreestanding is used). + * + * int32_t uint32_t uintptr_t + * bare metal GCC long unsigned long unsigned int + * glibc GCC int unsigned int unsigned int + * kernel int unsigned int unsigned long + */ + +#ifdef __INT32_TYPE__ +#undef __INT32_TYPE__ +#define __INT32_TYPE__ int +#endif + +#ifdef __UINT32_TYPE__ +#undef __UINT32_TYPE__ +#define __UINT32_TYPE__ unsigned int +#endif + +#ifdef __UINTPTR_TYPE__ +#undef __UINTPTR_TYPE__ +#define __UINTPTR_TYPE__ unsigned long +#endif + +#endif /* _ASM_TYPES_H */ diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h index fa88d09fa3d9..615781c61627 100644 --- a/arch/arm/include/asm/v7m.h +++ b/arch/arm/include/asm/v7m.h @@ -15,6 +15,10 @@ #define V7M_SCB_VTOR 0x08 +#define V7M_SCB_AIRCR 0x0c +#define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16) +#define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2) + #define V7M_SCB_SCR 0x10 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2) @@ -42,3 +46,11 @@ */ #define EXC_RET_STACK_MASK 0x00000004 #define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd + +#ifndef __ASSEMBLY__ + +enum reboot_mode; + +void armv7m_restart(enum reboot_mode mode, const char *cmd); + +#endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h index 7604673dc427..4ffb26d4cad8 100644 --- a/arch/arm/include/asm/xor.h +++ b/arch/arm/include/asm/xor.h @@ -7,7 +7,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <linux/hardirq.h> #include <asm-generic/xor.h> +#include <asm/hwcap.h> +#include <asm/neon.h> #define __XOR(a1, a2) a1 ^= a2 @@ -138,4 +141,74 @@ static struct xor_block_template xor_block_arm4regs = { xor_speed(&xor_block_arm4regs); \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ + NEON_TEMPLATES; \ } while (0) + +#ifdef CONFIG_KERNEL_MODE_NEON + +extern struct xor_block_template const xor_block_neon_inner; + +static void +xor_neon_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) +{ + if (in_interrupt()) { + xor_arm4regs_2(bytes, p1, p2); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_2(bytes, p1, p2); + kernel_neon_end(); + } +} + +static void +xor_neon_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3) +{ + if (in_interrupt()) { + xor_arm4regs_3(bytes, p1, p2, p3); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_3(bytes, p1, p2, p3); + kernel_neon_end(); + } +} + +static void +xor_neon_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3, unsigned long *p4) +{ + if (in_interrupt()) { + xor_arm4regs_4(bytes, p1, p2, p3, p4); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_4(bytes, p1, p2, p3, p4); + kernel_neon_end(); + } +} + +static void +xor_neon_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, + unsigned long *p3, unsigned long *p4, unsigned long *p5) +{ + if (in_interrupt()) { + xor_arm4regs_5(bytes, p1, p2, p3, p4, p5); + } else { + kernel_neon_begin(); + xor_block_neon_inner.do_5(bytes, p1, p2, p3, p4, p5); + kernel_neon_end(); + } +} + +static struct xor_block_template xor_block_neon = { + .name = "neon", + .do_2 = xor_neon_2, + .do_3 = xor_neon_3, + .do_4 = xor_neon_4, + .do_5 = xor_neon_5 +}; + +#define NEON_TEMPLATES \ + do { if (cpu_has_neon()) xor_speed(&xor_block_neon); } while (0) +#else +#define NEON_TEMPLATES +#endif diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S new file mode 100644 index 000000000000..7a2baf913aa0 --- /dev/null +++ b/arch/arm/include/debug/8250.S @@ -0,0 +1,54 @@ +/* + * arch/arm/include/debug/8250.S + * + * Copyright (C) 1994-2013 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/serial_reg.h> + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + +#ifdef CONFIG_DEBUG_UART_8250_WORD + .macro store, rd, rx:vararg + str \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldr \rd, \rx + .endm +#else + .macro store, rd, rx:vararg + strb \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldrb \rd, \rx + .endm +#endif + +#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT + + .macro senduart,rd,rx + store \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL +1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm diff --git a/arch/arm/include/debug/8250_32.S b/arch/arm/include/debug/8250_32.S deleted file mode 100644 index 8db01eeabbb4..000000000000 --- a/arch/arm/include/debug/8250_32.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2011 Picochip Ltd., Jamie Iles - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit - * accesses to the 8250. - */ - -#include <linux/serial_reg.h> - - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - /* The UART's don't have any flow control IO's wired up. */ - .macro waituart,rd,rx - .endm diff --git a/arch/arm/include/debug/bcm2835.S b/arch/arm/include/debug/bcm2835.S deleted file mode 100644 index aed9199bd847..000000000000 --- a/arch/arm/include/debug/bcm2835.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 2010 Broadcom - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#define BCM2835_DEBUG_PHYS 0x20201000 -#define BCM2835_DEBUG_VIRT 0xf0201000 - - .macro addruart, rp, rv, tmp - ldr \rp, =BCM2835_DEBUG_PHYS - ldr \rv, =BCM2835_DEBUG_VIRT - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/cns3xxx.S b/arch/arm/include/debug/cns3xxx.S deleted file mode 100644 index d04c150baa1c..000000000000 --- a/arch/arm/include/debug/cns3xxx.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright 1994-1999 Russell King - * Copyright 2008 Cavium Networks - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - - .macro addruart,rp,rv,tmp - mov \rp, #0x00009000 - orr \rv, \rp, #0xf0000000 @ virtual base - orr \rp, \rp, #0x10000000 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/highbank.S b/arch/arm/include/debug/highbank.S deleted file mode 100644 index 8cad4322a5a2..000000000000 --- a/arch/arm/include/debug/highbank.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - .macro addruart,rp,rv,tmp - ldr \rv, =0xfee36000 - ldr \rp, =0xfff36000 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S deleted file mode 100644 index 9aef9ba3f4f0..000000000000 --- a/arch/arm/include/debug/keystone.S +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Early serial debug output macro for Keystone SOCs - * - * Copyright 2013 Texas Instruments, Inc. - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Based on RMKs low level debug code. - * Copyright (C) 1994-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/serial_reg.h> - -#define UART_SHIFT 2 -#if defined(CONFIG_DEBUG_KEYSTONE_UART0) -#define UART_PHYS 0x02530c00 -#define UART_VIRT 0xfeb30c00 -#elif defined(CONFIG_DEBUG_KEYSTONE_UART1) -#define UART_PHYS 0x02531000 -#define UART_VIRT 0xfeb31000 -#endif - - .macro addruart, rp, rv, tmp - ldr \rv, =UART_VIRT @ physical base address - ldr \rp, =UART_PHYS @ virtual base address - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - .macro waituart,rd,rx - .endm diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/include/debug/msm.S index 0e05f88abcd5..9166e1bc470e 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/include/debug/msm.S @@ -15,8 +15,36 @@ * */ -#include <mach/hardware.h> -#include <mach/msm_iomap.h> +#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50) +#define MSM_UART1_PHYS 0xA9A00000 +#define MSM_UART2_PHYS 0xA9B00000 +#define MSM_UART3_PHYS 0xA9C00000 +#elif defined(CONFIG_ARCH_MSM7X30) +#define MSM_UART1_PHYS 0xACA00000 +#define MSM_UART2_PHYS 0xACB00000 +#define MSM_UART3_PHYS 0xACC00000 +#endif + +#if defined(CONFIG_DEBUG_MSM_UART1) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART2) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS +#elif defined(CONFIG_DEBUG_MSM_UART3) +#define MSM_DEBUG_UART_BASE 0xE1000000 +#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS +#endif + +#ifdef CONFIG_DEBUG_MSM8660_UART +#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_PHYS 0x19C40000 +#endif + +#ifdef CONFIG_DEBUG_MSM8960_UART +#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_PHYS 0x16440000 +#endif .macro addruart, rp, rv, tmp #ifdef MSM_DEBUG_UART_PHYS diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S deleted file mode 100644 index 6517311a1c91..000000000000 --- a/arch/arm/include/debug/mvebu.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Early serial output macro for Marvell SoC - * - * Copyright (C) 2012 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory Clement <gregory.clement@free-electrons.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE -#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000 -#else -#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#endif - -#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 - - .macro addruart, rp, rv, tmp - ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE - ldr \rv, =ARMADA_370_XP_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/include/debug/mxs.S b/arch/arm/include/debug/mxs.S deleted file mode 100644 index d86951551ca1..000000000000 --- a/arch/arm/include/debug/mxs.S +++ /dev/null @@ -1,27 +0,0 @@ -/* arch/arm/mach-mxs/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifdef CONFIG_DEBUG_IMX23_UART -#define UART_PADDR 0x80070000 -#elif defined (CONFIG_DEBUG_IMX28_UART) -#define UART_PADDR 0x80074000 -#endif - -#define UART_VADDR 0xfe100000 - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_PADDR @ physical - ldr \rv, =UART_VADDR @ virtual - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/nomadik.S b/arch/arm/include/debug/nomadik.S deleted file mode 100644 index 735417922ce2..000000000000 --- a/arch/arm/include/debug/nomadik.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00100000 - add \rp, \rp, #0x000fb000 - add \rv, \rp, #0xf0000000 @ virtual base - add \rp, \rp, #0x10000000 @ physical base address - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S deleted file mode 100644 index 886fd276fcbc..000000000000 --- a/arch/arm/include/debug/nspire.S +++ /dev/null @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/include/debug/nspire.S - * - * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ - -#define NSPIRE_EARLY_UART_PHYS_BASE 0x90020000 -#define NSPIRE_EARLY_UART_VIRT_BASE 0xfee20000 - -.macro addruart, rp, rv, tmp - ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE) @ physical base address - ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE) @ virtual base address -.endm - - -#ifdef CONFIG_DEBUG_NSPIRE_CX_UART -#include <asm/hardware/debug-pl01x.S> -#endif - -#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> -#endif diff --git a/arch/arm/include/debug/picoxcell.S b/arch/arm/include/debug/picoxcell.S deleted file mode 100644 index bc1f07c49cd4..000000000000 --- a/arch/arm/include/debug/picoxcell.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2011 Picochip Ltd., Jamie Iles - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#define UART_SHIFT 2 -#define PICOXCELL_UART1_BASE 0x80230000 -#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) - - .macro addruart, rp, rv, tmp - ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE) - ldr \rp, =PICOXCELL_UART1_BASE - .endm - -#include "8250_32.S" diff --git a/arch/arm/include/asm/hardware/debug-pl01x.S b/arch/arm/include/debug/pl01x.S index f9fd083eff63..37c6895b87e6 100644 --- a/arch/arm/include/asm/hardware/debug-pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -1,4 +1,4 @@ -/* arch/arm/include/asm/hardware/debug-pl01x.S +/* arch/arm/include/debug/pl01x.S * * Debugging macro include header * @@ -12,6 +12,13 @@ */ #include <linux/amba/serial.h> +#ifdef CONFIG_DEBUG_UART_PHYS + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm +#endif + .macro senduart,rd,rx strb \rd, [\rx, #UART01x_DR] .endm diff --git a/arch/arm/include/debug/pxa.S b/arch/arm/include/debug/pxa.S deleted file mode 100644 index e1e795aa3d7f..000000000000 --- a/arch/arm/include/debug/pxa.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Early serial output macro for Marvell PXA/MMP SoC - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * Copyright (C) 2013 Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#if defined(CONFIG_DEBUG_PXA_UART1) -#define PXA_UART_REG_PHYS_BASE 0x40100000 -#define PXA_UART_REG_VIRT_BASE 0xf2100000 -#elif defined(CONFIG_DEBUG_MMP_UART2) -#define PXA_UART_REG_PHYS_BASE 0xd4017000 -#define PXA_UART_REG_VIRT_BASE 0xfe017000 -#elif defined(CONFIG_DEBUG_MMP_UART3) -#define PXA_UART_REG_PHYS_BASE 0xd4018000 -#define PXA_UART_REG_VIRT_BASE 0xfe018000 -#else -#error "Select uart for DEBUG_LL" -#endif - - .macro addruart, rp, rv, tmp - ldr \rp, =PXA_UART_REG_PHYS_BASE - ldr \rv, =PXA_UART_REG_VIRT_BASE - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S deleted file mode 100644 index cfd883e69588..000000000000 --- a/arch/arm/include/debug/rockchip.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Early serial output macro for Rockchip SoCs - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#if defined(CONFIG_DEBUG_RK29_UART0) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000 -#elif defined(CONFIG_DEBUG_RK29_UART1) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 -#elif defined(CONFIG_DEBUG_RK29_UART2) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 -#elif defined(CONFIG_DEBUG_RK3X_UART0) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000 -#elif defined(CONFIG_DEBUG_RK3X_UART1) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000 -#elif defined(CONFIG_DEBUG_RK3X_UART2) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 -#elif defined(CONFIG_DEBUG_RK3X_UART3) -#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 -#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 -#endif - - .macro addruart, rp, rv, tmp - ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE - ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/include/debug/socfpga.S b/arch/arm/include/debug/socfpga.S deleted file mode 100644 index 966b2f994946..000000000000 --- a/arch/arm/include/debug/socfpga.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define UART_SHIFT 2 -#define DEBUG_LL_UART_OFFSET 0x00002000 - - .macro addruart, rp, rv, tmp - mov \rp, #DEBUG_LL_UART_OFFSET - orr \rp, \rp, #0x00c00000 - orr \rv, \rp, #0xfe000000 @ virtual base - orr \rp, \rp, #0xff000000 @ physical base - .endm - -#include "8250_32.S" - diff --git a/arch/arm/include/debug/sunxi.S b/arch/arm/include/debug/sunxi.S deleted file mode 100644 index 04eb56d5db2c..000000000000 --- a/arch/arm/include/debug/sunxi.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Early serial output macro for Allwinner A1X SoCs - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#if defined(CONFIG_DEBUG_SUNXI_UART0) -#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28000 -#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28000 -#elif defined(CONFIG_DEBUG_SUNXI_UART1) -#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400 -#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400 -#endif - - .macro addruart, rp, rv, tmp - ldr \rp, =SUNXI_UART_DEBUG_PHYS_BASE - ldr \rv, =SUNXI_UART_DEBUG_VIRT_BASE - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index 883d7c22fd9d..be6a720dd183 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -221,3 +221,32 @@ 1002: #endif .endm + +/* + * Storage for the state maintained by the macros above. + * + * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c. + * That's because this header is included from multiple files, and we only + * want a single copy of the data. In particular, the UART probing code above + * assumes it's running using physical addresses. This is true when this file + * is included from head.o, but not when included from debug.o. So we need + * to share the probe results between the two copies, rather than having + * to re-run the probing again later. + * + * In the decompressor, we put the symbol/storage right here, since common.c + * isn't included in the decompressor build. This symbol gets put in .text + * even though it's really data, since .data is discarded from the + * decompressor. Luckily, .text is writeable in the decompressor, unless + * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug. + */ +#if defined(ZIMAGE) +tegra_uart_config: + /* Debug UART initialization required */ + .word 1 + /* Debug UART physical address */ + .word 0 + /* Debug UART virtual address */ + .word 0 + /* Scratch space for debug macro */ + .word 0 +#endif diff --git a/arch/arm/include/debug/u300.S b/arch/arm/include/debug/u300.S deleted file mode 100644 index 6f04f08a203c..000000000000 --- a/arch/arm/include/debug/u300.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2006-2013 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Debugging macro include header. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#define U300_SLOW_PER_PHYS_BASE 0xc0010000 -#define U300_SLOW_PER_VIRT_BASE 0xff000000 - - .macro addruart, rp, rv, tmp - /* If we move the address using MMU, use this. */ - ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address - ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address - orr \rp, \rp, #0x00003000 - orr \rv, \rv, #0x00003000 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S index fbd24beeb1fa..aa7f63a8b5e0 100644 --- a/arch/arm/include/debug/ux500.S +++ b/arch/arm/include/debug/ux500.S @@ -45,4 +45,4 @@ ldr \rv, =UART_VIRT_BASE @ yes, virtual address .endm -#include <asm/hardware/debug-pl01x.S> +#include <debug/pl01x.S> diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S index acafb229e2b6..524acd5a223e 100644 --- a/arch/arm/include/debug/vexpress.S +++ b/arch/arm/include/debug/vexpress.S @@ -47,51 +47,5 @@ .endm -#include <asm/hardware/debug-pl01x.S> - -#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) - - .macro addruart,rp,rv,tmp - mov \rp, #DEBUG_LL_UART_OFFSET - orr \rv, \rp, #DEBUG_LL_VIRT_BASE - orr \rp, \rp, #DEBUG_LL_PHYS_BASE - .endm - -#include <asm/hardware/debug-pl01x.S> - -#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) - - .macro addruart,rp,rv,tmp - mov \rp, #DEBUG_LL_UART_OFFSET_RS1 - orr \rv, \rp, #DEBUG_LL_VIRT_BASE - orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 - .endm - -#include <asm/hardware/debug-pl01x.S> - -#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX) - - .macro addruart,rp,tmp,tmp2 - ldr \rp, =DEBUG_LL_UART_PHYS_CRX - .endm - -#include <asm/hardware/debug-pl01x.S> - -#else /* CONFIG_DEBUG_LL_UART_NONE */ - - .macro addruart, rp, rv, tmp - /* Safe dummy values */ - mov \rp, #0 - mov \rv, #DEBUG_LL_VIRT_BASE - .endm - - .macro senduart,rd,rx - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx - .endm - +#include <debug/pl01x.S> #endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 86d10dd47dc4..5140df5f23aa 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_ATAGS_PROC) += atags_proc.o obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o ifeq ($(CONFIG_CPU_V7M),y) -obj-y += entry-v7m.o +obj-y += entry-v7m.o v7m.o else obj-y += entry-armv.o endif diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h index 9edc9692332d..ec4164da6e30 100644 --- a/arch/arm/kernel/atags.h +++ b/arch/arm/kernel/atags.h @@ -7,9 +7,10 @@ static inline void save_atags(struct tag *tags) { } void convert_to_tag_list(struct tag *tags); #ifdef CONFIG_ATAGS -struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr); +const struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, + unsigned int machine_nr); #else -static inline struct machine_desc * +static inline const struct machine_desc * setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) { early_print("no ATAGS support: can't continue\n"); diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c index 14512e6931d8..8c14de8180c0 100644 --- a/arch/arm/kernel/atags_parse.c +++ b/arch/arm/kernel/atags_parse.c @@ -178,11 +178,11 @@ static void __init squash_mem_tags(struct tag *tag) tag->hdr.tag = ATAG_NONE; } -struct machine_desc * __init setup_machine_tags(phys_addr_t __atags_pointer, - unsigned int machine_nr) +const struct machine_desc * __init +setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) { struct tag *tags = (struct tag *)&default_tags; - struct machine_desc *mdesc = NULL, *p; + const struct machine_desc *mdesc = NULL, *p; char *from = default_command_line; default_tags.mem.start = PHYS_OFFSET; diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 261fcc826169..317da88ae65b 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus) } EXPORT_SYMBOL(pcibios_fixup_bus); +void pcibios_add_bus(struct pci_bus *bus) +{ + struct pci_sys_data *sys = bus->sysdata; + if (sys->add_bus) + sys->add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + struct pci_sys_data *sys = bus->sysdata; + if (sys->remove_bus) + sys->remove_bus(bus); +} + /* * Swizzle the device pin each time we cross a bridge. If a platform does * not provide a swizzle function, we perform the standard PCI swizzling. @@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, sys->swizzle = hw->swizzle; sys->map_irq = hw->map_irq; sys->align_resource = hw->align_resource; + sys->add_bus = hw->add_bus; + sys->remove_bus = hw->remove_bus; INIT_LIST_HEAD(&sys->resources); if (hw->private_data) @@ -525,11 +541,6 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) * Assign resources. */ pci_bus_assign_resources(bus); - - /* - * Enable bridges - */ - pci_enable_bridges(bus); } /* diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 5859c8bc727c..f35906b3d8c9 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -169,6 +169,11 @@ void __init arm_dt_init_cpu_maps(void) } } +bool arch_match_cpu_phys_id(int cpu, u64 phys_id) +{ + return (phys_id & MPIDR_HWID_BITMASK) == cpu_logical_map(cpu); +} + /** * setup_machine_fdt - Machine setup when an dtb was passed to the kernel * @dt_phys: physical address of dt blob @@ -176,10 +181,10 @@ void __init arm_dt_init_cpu_maps(void) * If a dtb was passed to the kernel in r2, then use it to choose the * correct machine_desc and to setup the system. */ -struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) +const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) { struct boot_param_header *devtree; - struct machine_desc *mdesc, *mdesc_best = NULL; + const struct machine_desc *mdesc, *mdesc_best = NULL; unsigned int score, mdesc_score = ~1; unsigned long dt_root; const char *model; @@ -188,7 +193,7 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) DT_MACHINE_START(GENERIC_DT, "Generic DT based system") MACHINE_END - mdesc_best = (struct machine_desc *)&__mach_desc_GENERIC_DT; + mdesc_best = &__mach_desc_GENERIC_DT; #endif if (!dt_phys) diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 94104bf69719..74ad15d1a065 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -442,10 +442,10 @@ local_restart: ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine add r1, sp, #S_OFF -2: mov why, #0 @ no longer a real syscall cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE) eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back - bcs arm_syscall + bcs arm_syscall +2: mov why, #0 @ no longer a real syscall b sys_ni_syscall @ not private func #if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI) diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c index fc7920288a3d..918875d96d5d 100644 --- a/arch/arm/kernel/fiq.c +++ b/arch/arm/kernel/fiq.c @@ -89,7 +89,8 @@ void set_fiq_handler(void *start, unsigned int length) memcpy(base + offset, start, length); if (!cache_is_vipt_nonaliasing()) - flush_icache_range(base + offset, offset + length); + flush_icache_range((unsigned long)base + offset, offset + + length); flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length); } diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index d7c82df69243..57221e349a7c 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -82,6 +82,7 @@ void machine_crash_nonpanic_core(void *unused) crash_save_cpu(®s, smp_processor_id()); flush_cache_all(); + set_cpu_online(smp_processor_id(), false); atomic_dec(&waiting_for_crash_ipi); while (1) cpu_relax(); diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 85c3fb6c93c2..084dc8896986 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -292,12 +292,20 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, maps[ARM_SEC_CORE].unw_sec = s; else if (strcmp(".ARM.exidx.exit.text", secname) == 0) maps[ARM_SEC_EXIT].unw_sec = s; + else if (strcmp(".ARM.exidx.text.unlikely", secname) == 0) + maps[ARM_SEC_UNLIKELY].unw_sec = s; + else if (strcmp(".ARM.exidx.text.hot", secname) == 0) + maps[ARM_SEC_HOT].unw_sec = s; else if (strcmp(".init.text", secname) == 0) maps[ARM_SEC_INIT].txt_sec = s; else if (strcmp(".text", secname) == 0) maps[ARM_SEC_CORE].txt_sec = s; else if (strcmp(".exit.text", secname) == 0) maps[ARM_SEC_EXIT].txt_sec = s; + else if (strcmp(".text.unlikely", secname) == 0) + maps[ARM_SEC_UNLIKELY].txt_sec = s; + else if (strcmp(".text.hot", secname) == 0) + maps[ARM_SEC_HOT].txt_sec = s; } for (i = 0; i < ARM_SEC_MAX; i++) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index aebe0e99c153..8d6147b2001f 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -118,7 +118,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) continue; } - err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu", + err = request_irq(irq, handler, + IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", cpu_pmu); if (err) { pr_err("unable to request IRQ%d for ARM PMU counters\n", diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index afc2489ee13b..0e1e2b3afa45 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -72,10 +72,10 @@ static int __init fpe_setup(char *line) __setup("fpe=", fpe_setup); #endif -extern void paging_init(struct machine_desc *desc); +extern void paging_init(const struct machine_desc *desc); extern void sanity_check_meminfo(void); extern enum reboot_mode reboot_mode; -extern void setup_dma_zone(struct machine_desc *desc); +extern void setup_dma_zone(const struct machine_desc *desc); unsigned int processor_id; EXPORT_SYMBOL(processor_id); @@ -139,7 +139,7 @@ EXPORT_SYMBOL(elf_platform); static const char *cpu_name; static const char *machine_name; static char __initdata cmd_line[COMMAND_LINE_SIZE]; -struct machine_desc *machine_desc __initdata; +const struct machine_desc *machine_desc __initdata; static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; #define ENDIANNESS ((char)endian_test.l) @@ -607,7 +607,7 @@ static void __init setup_processor(void) void __init dump_machine_table(void) { - struct machine_desc *p; + const struct machine_desc *p; early_print("Available machine support:\n\nID (hex)\tNAME\n"); for_each_machine_desc(p) @@ -694,7 +694,7 @@ static int __init early_mem(char *p) } early_param("mem", early_mem); -static void __init request_standard_resources(struct machine_desc *mdesc) +static void __init request_standard_resources(const struct machine_desc *mdesc) { struct memblock_region *region; struct resource *res; @@ -852,7 +852,7 @@ void __init hyp_mode_check(void) void __init setup_arch(char **cmdline_p) { - struct machine_desc *mdesc; + const struct machine_desc *mdesc; setup_processor(); mdesc = setup_machine_fdt(__atags_pointer); @@ -994,15 +994,6 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "model name\t: %s rev %d (%s)\n", cpu_name, cpuid & 15, elf_platform); -#if defined(CONFIG_SMP) - seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", - per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ), - (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100); -#else - seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", - loops_per_jiffy / (500000/HZ), - (loops_per_jiffy / (5000/HZ)) % 100); -#endif /* dump out the processor features */ seq_puts(m, "Features\t: "); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 2dc19349eb19..72024ea8a3a6 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -41,7 +41,6 @@ #include <asm/sections.h> #include <asm/tlbflush.h> #include <asm/ptrace.h> -#include <asm/localtimer.h> #include <asm/smp_plat.h> #include <asm/virt.h> #include <asm/mach/arch.h> @@ -156,8 +155,6 @@ int platform_can_cpu_hotplug(void) } #ifdef CONFIG_HOTPLUG_CPU -static void percpu_timer_stop(void); - static int platform_cpu_kill(unsigned int cpu) { if (smp_ops.cpu_kill) @@ -201,11 +198,6 @@ int __cpu_disable(void) migrate_irqs(); /* - * Stop the local timer for this CPU. - */ - percpu_timer_stop(); - - /* * Flush user cache and TLB mappings, and then remove this CPU * from the vm mask set of all processes. * @@ -326,8 +318,6 @@ static void smp_store_cpu_info(unsigned int cpuid) store_cpu_topology(cpuid); } -static void percpu_timer_setup(void); - /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -382,11 +372,6 @@ asmlinkage void secondary_start_kernel(void) set_cpu_online(cpu, true); complete(&cpu_running); - /* - * Setup the percpu timer for this CPU. - */ - percpu_timer_setup(); - local_irq_enable(); local_fiq_enable(); @@ -398,17 +383,8 @@ asmlinkage void secondary_start_kernel(void) void __init smp_cpus_done(unsigned int max_cpus) { - int cpu; - unsigned long bogosum = 0; - - for_each_online_cpu(cpu) - bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; - - printk(KERN_INFO "SMP: Total of %d processors activated " - "(%lu.%02lu BogoMIPS).\n", - num_online_cpus(), - bogosum / (500000/HZ), - (bogosum / (5000/HZ)) % 100); + printk(KERN_INFO "SMP: Total of %d processors activated.\n", + num_online_cpus()); hyp_mode_check(); } @@ -433,12 +409,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) max_cpus = ncores; if (ncores > 1 && max_cpus) { /* - * Enable the local timer or broadcast device for the - * boot CPU, but only if we have more than one CPU. - */ - percpu_timer_setup(); - - /* * Initialise the present map, which describes the set of CPUs * actually populated at the present time. A platform should * re-initialize the map in the platforms smp_prepare_cpus() @@ -514,11 +484,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu) return sum; } -/* - * Timer (local or broadcast) support - */ -static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); - #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST void tick_broadcast(const struct cpumask *mask) { @@ -526,67 +491,6 @@ void tick_broadcast(const struct cpumask *mask) } #endif -static void broadcast_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ -} - -static void broadcast_timer_setup(struct clock_event_device *evt) -{ - evt->name = "dummy_timer"; - evt->features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DUMMY; - evt->rating = 100; - evt->mult = 1; - evt->set_mode = broadcast_timer_set_mode; - - clockevents_register_device(evt); -} - -static struct local_timer_ops *lt_ops; - -#ifdef CONFIG_LOCAL_TIMERS -int local_timer_register(struct local_timer_ops *ops) -{ - if (!is_smp() || !setup_max_cpus) - return -ENXIO; - - if (lt_ops) - return -EBUSY; - - lt_ops = ops; - return 0; -} -#endif - -static void percpu_timer_setup(void) -{ - unsigned int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); - - evt->cpumask = cpumask_of(cpu); - - if (!lt_ops || lt_ops->setup(evt)) - broadcast_timer_setup(evt); -} - -#ifdef CONFIG_HOTPLUG_CPU -/* - * The generic clock events code purposely does not stop the local timer - * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it - * manually here. - */ -static void percpu_timer_stop(void) -{ - unsigned int cpu = smp_processor_id(); - struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); - - if (lt_ops) - lt_ops->stop(evt); -} -#endif - static DEFINE_RAW_SPINLOCK(stop_lock); /* diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index c2edfff573c2..83ccca303df8 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -104,7 +104,7 @@ void flush_tlb_all(void) if (tlb_ops_need_broadcast()) on_each_cpu(ipi_flush_tlb_all, NULL, 1); else - local_flush_tlb_all(); + __flush_tlb_all(); broadcast_tlb_a15_erratum(); } @@ -113,7 +113,7 @@ void flush_tlb_mm(struct mm_struct *mm) if (tlb_ops_need_broadcast()) on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); else - local_flush_tlb_mm(mm); + __flush_tlb_mm(mm); broadcast_tlb_mm_a15_erratum(mm); } @@ -126,7 +126,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1); } else - local_flush_tlb_page(vma, uaddr); + __flush_tlb_page(vma, uaddr); broadcast_tlb_mm_a15_erratum(vma->vm_mm); } @@ -137,7 +137,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) ta.ta_start = kaddr; on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); } else - local_flush_tlb_kernel_page(kaddr); + __flush_tlb_kernel_page(kaddr); broadcast_tlb_a15_erratum(); } @@ -173,5 +173,5 @@ void flush_bp_all(void) if (tlb_ops_need_broadcast()) on_each_cpu(ipi_flush_bp_all, NULL, 1); else - local_flush_bp_all(); + __flush_bp_all(); } diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 25956204ef23..2985c9f0905d 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/clk.h> +#include <linux/cpu.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> @@ -24,7 +25,6 @@ #include <asm/smp_plat.h> #include <asm/smp_twd.h> -#include <asm/localtimer.h> /* set up by the platform code */ static void __iomem *twd_base; @@ -33,7 +33,7 @@ static struct clk *twd_clk; static unsigned long twd_timer_rate; static DEFINE_PER_CPU(bool, percpu_setup_called); -static struct clock_event_device __percpu **twd_evt; +static struct clock_event_device __percpu *twd_evt; static int twd_ppi; static void twd_set_mode(enum clock_event_mode mode, @@ -90,8 +90,10 @@ static int twd_timer_ack(void) return 0; } -static void twd_timer_stop(struct clock_event_device *clk) +static void twd_timer_stop(void) { + struct clock_event_device *clk = __this_cpu_ptr(twd_evt); + twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk); disable_percpu_irq(clk->irq); } @@ -106,7 +108,7 @@ static void twd_update_frequency(void *new_rate) { twd_timer_rate = *((unsigned long *) new_rate); - clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); + clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate); } static int twd_rate_change(struct notifier_block *nb, @@ -132,7 +134,7 @@ static struct notifier_block twd_clk_nb = { static int twd_clk_init(void) { - if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) + if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) return clk_notifier_register(twd_clk, &twd_clk_nb); return 0; @@ -151,7 +153,7 @@ static void twd_update_frequency(void *data) { twd_timer_rate = clk_get_rate(twd_clk); - clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); + clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate); } static int twd_cpufreq_transition(struct notifier_block *nb, @@ -177,7 +179,7 @@ static struct notifier_block twd_cpufreq_nb = { static int twd_cpufreq_init(void) { - if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) + if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) return cpufreq_register_notifier(&twd_cpufreq_nb, CPUFREQ_TRANSITION_NOTIFIER); @@ -228,7 +230,7 @@ static void twd_calibrate_rate(void) static irqreturn_t twd_handler(int irq, void *dev_id) { - struct clock_event_device *evt = *(struct clock_event_device **)dev_id; + struct clock_event_device *evt = dev_id; if (twd_timer_ack()) { evt->event_handler(evt); @@ -265,9 +267,9 @@ static void twd_get_clock(struct device_node *np) /* * Setup the local clock events for a CPU. */ -static int twd_timer_setup(struct clock_event_device *clk) +static void twd_timer_setup(void) { - struct clock_event_device **this_cpu_clk; + struct clock_event_device *clk = __this_cpu_ptr(twd_evt); int cpu = smp_processor_id(); /* @@ -276,9 +278,9 @@ static int twd_timer_setup(struct clock_event_device *clk) */ if (per_cpu(percpu_setup_called, cpu)) { __raw_writel(0, twd_base + TWD_TIMER_CONTROL); - clockevents_register_device(*__this_cpu_ptr(twd_evt)); + clockevents_register_device(clk); enable_percpu_irq(clk->irq, 0); - return 0; + return; } per_cpu(percpu_setup_called, cpu) = true; @@ -297,27 +299,37 @@ static int twd_timer_setup(struct clock_event_device *clk) clk->set_mode = twd_set_mode; clk->set_next_event = twd_set_next_event; clk->irq = twd_ppi; - - this_cpu_clk = __this_cpu_ptr(twd_evt); - *this_cpu_clk = clk; + clk->cpumask = cpumask_of(cpu); clockevents_config_and_register(clk, twd_timer_rate, 0xf, 0xffffffff); enable_percpu_irq(clk->irq, 0); +} - return 0; +static int twd_timer_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_STARTING: + twd_timer_setup(); + break; + case CPU_DYING: + twd_timer_stop(); + break; + } + + return NOTIFY_OK; } -static struct local_timer_ops twd_lt_ops = { - .setup = twd_timer_setup, - .stop = twd_timer_stop, +static struct notifier_block twd_timer_cpu_nb = { + .notifier_call = twd_timer_cpu_notify, }; static int __init twd_local_timer_common_register(struct device_node *np) { int err; - twd_evt = alloc_percpu(struct clock_event_device *); + twd_evt = alloc_percpu(struct clock_event_device); if (!twd_evt) { err = -ENOMEM; goto out_free; @@ -329,12 +341,22 @@ static int __init twd_local_timer_common_register(struct device_node *np) goto out_free; } - err = local_timer_register(&twd_lt_ops); + err = register_cpu_notifier(&twd_timer_cpu_nb); if (err) goto out_irq; twd_get_clock(np); + /* + * Immediately configure the timer on the boot CPU, unless we need + * jiffies to be incrementing to calibrate the rate in which case + * setup the timer in late_time_init. + */ + if (twd_timer_rate) + twd_timer_setup(); + else + late_time_init = twd_timer_setup; + return 0; out_irq: diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index c5a59546a256..85a87370f144 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -74,12 +74,8 @@ struct cpu_efficiency table_efficiency[] = { {NULL, }, }; -struct cpu_capacity { - unsigned long hwid; - unsigned long capacity; -}; - -struct cpu_capacity *cpu_capacity; +unsigned long *__cpu_capacity; +#define cpu_capacity(cpu) __cpu_capacity[cpu] unsigned long middle_capacity = 1; @@ -100,15 +96,19 @@ static void __init parse_dt_topology(void) unsigned long capacity = 0; int alloc_size, cpu = 0; - alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity); - cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT); + alloc_size = nr_cpu_ids * sizeof(*__cpu_capacity); + __cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT); - while ((cn = of_find_node_by_type(cn, "cpu"))) { - const u32 *rate, *reg; + for_each_possible_cpu(cpu) { + const u32 *rate; int len; - if (cpu >= num_possible_cpus()) - break; + /* too early to use cpu->of_node */ + cn = of_get_cpu_node(cpu, NULL); + if (!cn) { + pr_err("missing device node for CPU %d\n", cpu); + continue; + } for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++) if (of_device_is_compatible(cn, cpu_eff->compatible)) @@ -124,12 +124,6 @@ static void __init parse_dt_topology(void) continue; } - reg = of_get_property(cn, "reg", &len); - if (!reg || len != 4) { - pr_err("%s missing reg property\n", cn->full_name); - continue; - } - capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency; /* Save min capacity of the system */ @@ -140,13 +134,9 @@ static void __init parse_dt_topology(void) if (capacity > max_capacity) max_capacity = capacity; - cpu_capacity[cpu].capacity = capacity; - cpu_capacity[cpu++].hwid = be32_to_cpup(reg); + cpu_capacity(cpu) = capacity; } - if (cpu < num_possible_cpus()) - cpu_capacity[cpu].hwid = (unsigned long)(-1); - /* If min and max capacities are equals, we bypass the update of the * cpu_scale because all CPUs have the same capacity. Otherwise, we * compute a middle_capacity factor that will ensure that the capacity @@ -154,9 +144,7 @@ static void __init parse_dt_topology(void) * SCHED_POWER_SCALE, which is the default value, but with the * constraint explained near table_efficiency[]. */ - if (min_capacity == max_capacity) - cpu_capacity[0].hwid = (unsigned long)(-1); - else if (4*max_capacity < (3*(max_capacity + min_capacity))) + if (4*max_capacity < (3*(max_capacity + min_capacity))) middle_capacity = (min_capacity + max_capacity) >> (SCHED_POWER_SHIFT+1); else @@ -170,23 +158,12 @@ static void __init parse_dt_topology(void) * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the * function returns directly for SMP system. */ -void update_cpu_power(unsigned int cpu, unsigned long hwid) +void update_cpu_power(unsigned int cpu) { - unsigned int idx = 0; - - /* look for the cpu's hwid in the cpu capacity table */ - for (idx = 0; idx < num_possible_cpus(); idx++) { - if (cpu_capacity[idx].hwid == hwid) - break; - - if (cpu_capacity[idx].hwid == -1) - return; - } - - if (idx == num_possible_cpus()) + if (!cpu_capacity(cpu)) return; - set_power_scale(cpu, cpu_capacity[idx].capacity / middle_capacity); + set_power_scale(cpu, cpu_capacity(cpu) / middle_capacity); printk(KERN_INFO "CPU%u: update cpu_power %lu\n", cpu, arch_scale_freq_power(NULL, cpu)); @@ -194,7 +171,7 @@ void update_cpu_power(unsigned int cpu, unsigned long hwid) #else static inline void parse_dt_topology(void) {} -static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {} +static inline void update_cpu_power(unsigned int cpuid) {} #endif /* @@ -281,7 +258,7 @@ void store_cpu_topology(unsigned int cpuid) update_siblings_masks(cpuid); - update_cpu_power(cpuid, mpidr & MPIDR_HWID_BITMASK); + update_cpu_power(cpuid); printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", cpuid, cpu_topology[cpuid].thread_id, diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index ab517fcce21b..8fcda140358d 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -497,28 +497,64 @@ static int bad_syscall(int n, struct pt_regs *regs) return regs->ARM_r0; } +static long do_cache_op_restart(struct restart_block *); + static inline int -do_cache_op(unsigned long start, unsigned long end, int flags) +__do_cache_op(unsigned long start, unsigned long end) { - struct mm_struct *mm = current->active_mm; - struct vm_area_struct *vma; + int ret; + unsigned long chunk = PAGE_SIZE; + + do { + if (signal_pending(current)) { + struct thread_info *ti = current_thread_info(); + + ti->restart_block = (struct restart_block) { + .fn = do_cache_op_restart, + }; + + ti->arm_restart_block = (struct arm_restart_block) { + { + .cache = { + .start = start, + .end = end, + }, + }, + }; + + return -ERESTART_RESTARTBLOCK; + } + + ret = flush_cache_user_range(start, start + chunk); + if (ret) + return ret; + cond_resched(); + start += chunk; + } while (start < end); + + return 0; +} + +static long do_cache_op_restart(struct restart_block *unused) +{ + struct arm_restart_block *restart_block; + + restart_block = ¤t_thread_info()->arm_restart_block; + return __do_cache_op(restart_block->cache.start, + restart_block->cache.end); +} + +static inline int +do_cache_op(unsigned long start, unsigned long end, int flags) +{ if (end < start || flags) return -EINVAL; - down_read(&mm->mmap_sem); - vma = find_vma(mm, start); - if (vma && vma->vm_start < end) { - if (start < vma->vm_start) - start = vma->vm_start; - if (end > vma->vm_end) - end = vma->vm_end; + if (!access_ok(VERIFY_READ, start, end - start)) + return -EFAULT; - up_read(&mm->mmap_sem); - return flush_cache_user_range(start, end); - } - up_read(&mm->mmap_sem); - return -EINVAL; + return __do_cache_op(start, end); } /* diff --git a/arch/arm/kernel/v7m.c b/arch/arm/kernel/v7m.c new file mode 100644 index 000000000000..4d2cba94f5cc --- /dev/null +++ b/arch/arm/kernel/v7m.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013 Uwe Kleine-Koenig for Pengutronix + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/io.h> +#include <linux/reboot.h> +#include <asm/barrier.h> +#include <asm/v7m.h> + +void armv7m_restart(enum reboot_mode mode, const char *cmd) +{ + dsb(); + __raw_writel(V7M_SCB_AIRCR_VECTKEY | V7M_SCB_AIRCR_SYSRESETREQ, + BASEADDR_V7M_SCB + V7M_SCB_AIRCR); + dsb(); +} diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 741f66a2edbd..9c697db2787e 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -219,6 +219,10 @@ long kvm_arch_dev_ioctl(struct file *filp, return -EINVAL; } +void kvm_arch_memslots_updated(struct kvm *kvm) +{ +} + int kvm_arch_prepare_memory_region(struct kvm *kvm, struct kvm_memory_slot *memslot, struct kvm_userspace_memory_region *mem, diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 4a5199070430..db9cf692d4dd 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -146,7 +146,11 @@ static bool pm_fake(struct kvm_vcpu *vcpu, #define access_pmintenclr pm_fake /* Architected CP15 registers. - * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API for 64-bit register access in line with the terminology used + * in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceding 32-bit ones. */ static const struct coproc_reg cp15_regs[] = { /* CSSELR: swapped by interrupt.S. */ @@ -154,8 +158,8 @@ static const struct coproc_reg cp15_regs[] = { NULL, reset_unknown, c0_CSSELR }, /* TTBR0/TTBR1: swapped by interrupt.S. */ - { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, - { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, + { CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, + { CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, /* TTBCR: swapped by interrupt.S. */ { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, @@ -182,7 +186,7 @@ static const struct coproc_reg cp15_regs[] = { NULL, reset_unknown, c6_IFAR }, /* PAR swapped by interrupt.S */ - { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR }, + { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR }, /* * DC{C,I,CI}SW operations: @@ -399,12 +403,13 @@ static bool index_to_params(u64 id, struct coproc_params *params) | KVM_REG_ARM_OPC1_MASK)) return false; params->is_64bit = true; - params->CRm = ((id & KVM_REG_ARM_CRM_MASK) + /* CRm to CRn: see cp15_to_index for details */ + params->CRn = ((id & KVM_REG_ARM_CRM_MASK) >> KVM_REG_ARM_CRM_SHIFT); params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) >> KVM_REG_ARM_OPC1_SHIFT); params->Op2 = 0; - params->CRn = 0; + params->CRm = 0; return true; default: return false; @@ -898,7 +903,14 @@ static u64 cp15_to_index(const struct coproc_reg *reg) if (reg->is_64) { val |= KVM_REG_SIZE_U64; val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); - val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); + /* + * CRn always denotes the primary coproc. reg. nr. for the + * in-kernel representation, but the user space API uses the + * CRm for the encoding, because it is modelled after the + * MRRC/MCRR instructions: see the ARM ARM rev. c page + * B3-1445 + */ + val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); } else { val |= KVM_REG_SIZE_U32; val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h index b7301d3e4799..0461d5c8d3de 100644 --- a/arch/arm/kvm/coproc.h +++ b/arch/arm/kvm/coproc.h @@ -135,6 +135,8 @@ static inline int cmp_reg(const struct coproc_reg *i1, return -1; if (i1->CRn != i2->CRn) return i1->CRn - i2->CRn; + if (i1->is_64 != i2->is_64) + return i2->is_64 - i1->is_64; if (i1->CRm != i2->CRm) return i1->CRm - i2->CRm; if (i1->Op1 != i2->Op1) @@ -145,6 +147,7 @@ static inline int cmp_reg(const struct coproc_reg *i1, #define CRn(_x) .CRn = _x #define CRm(_x) .CRm = _x +#define CRm64(_x) .CRn = _x, .CRm = 0 #define Op1(_x) .Op1 = _x #define Op2(_x) .Op2 = _x #define is64 .is_64 = true diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c index 685063a6d0cf..cf93472b9dd6 100644 --- a/arch/arm/kvm/coproc_a15.c +++ b/arch/arm/kvm/coproc_a15.c @@ -114,7 +114,11 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu, /* * A15-specific CP15 registers. - * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API for 64-bit register access in line with the terminology used + * in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceding 32-bit ones. */ static const struct coproc_reg a15_regs[] = { /* MPIDR: we use VMPIDR for guest access. */ diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S index f048338135f7..1b9844d369cc 100644 --- a/arch/arm/kvm/init.S +++ b/arch/arm/kvm/init.S @@ -142,7 +142,7 @@ target: @ We're now in the trampoline code, switch page tables @ Invalidate the old TLBs mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH - dsb + dsb ish eret diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index 16cd4ba5d7fd..ddc15539bad2 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -55,7 +55,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) mcrr p15, 6, r2, r3, c2 @ Write VTTBR isb mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored) - dsb + dsb ish isb mov r2, #0 mov r3, #0 @@ -79,7 +79,7 @@ ENTRY(__kvm_flush_vm_context) mcr p15, 4, r0, c8, c3, 4 /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */ mcr p15, 0, r0, c7, c1, 0 - dsb + dsb ish isb @ Not necessary if followed by eret bx lr @@ -492,10 +492,10 @@ __kvm_hyp_code_end: .section ".rodata" und_die_str: - .ascii "unexpected undefined exception in Hyp mode at: %#08x" + .ascii "unexpected undefined exception in Hyp mode at: %#08x\n" pabt_die_str: - .ascii "unexpected prefetch abort in Hyp mode at: %#08x" + .ascii "unexpected prefetch abort in Hyp mode at: %#08x\n" dabt_die_str: - .ascii "unexpected data abort in Hyp mode at: %#08x" + .ascii "unexpected data abort in Hyp mode at: %#08x\n" svc_die_str: - .ascii "unexpected HVC/SVC trap in Hyp mode at: %#08x" + .ascii "unexpected HVC/SVC trap in Hyp mode at: %#08x\n" diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c index b8e06b7a2833..0c25d9487d53 100644 --- a/arch/arm/kvm/mmio.c +++ b/arch/arm/kvm/mmio.c @@ -63,7 +63,8 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, struct kvm_exit_mmio *mmio) { - unsigned long rt, len; + unsigned long rt; + int len; bool is_write, sign_extend; if (kvm_vcpu_dabt_isextabt(vcpu)) { diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index ca6bea4859b4..b0de86b56c13 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -85,6 +85,12 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) return p; } +static bool page_empty(void *ptr) +{ + struct page *ptr_page = virt_to_page(ptr); + return page_count(ptr_page) == 1; +} + static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) { pmd_t *pmd_table = pmd_offset(pud, 0); @@ -103,12 +109,6 @@ static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr) put_page(virt_to_page(pmd)); } -static bool pmd_empty(pmd_t *pmd) -{ - struct page *pmd_page = virt_to_page(pmd); - return page_count(pmd_page) == 1; -} - static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr) { if (pte_present(*pte)) { @@ -118,12 +118,6 @@ static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr) } } -static bool pte_empty(pte_t *pte) -{ - struct page *pte_page = virt_to_page(pte); - return page_count(pte_page) == 1; -} - static void unmap_range(struct kvm *kvm, pgd_t *pgdp, unsigned long long start, u64 size) { @@ -132,37 +126,37 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp, pmd_t *pmd; pte_t *pte; unsigned long long addr = start, end = start + size; - u64 range; + u64 next; while (addr < end) { pgd = pgdp + pgd_index(addr); pud = pud_offset(pgd, addr); if (pud_none(*pud)) { - addr += PUD_SIZE; + addr = pud_addr_end(addr, end); continue; } pmd = pmd_offset(pud, addr); if (pmd_none(*pmd)) { - addr += PMD_SIZE; + addr = pmd_addr_end(addr, end); continue; } pte = pte_offset_kernel(pmd, addr); clear_pte_entry(kvm, pte, addr); - range = PAGE_SIZE; + next = addr + PAGE_SIZE; /* If we emptied the pte, walk back up the ladder */ - if (pte_empty(pte)) { + if (page_empty(pte)) { clear_pmd_entry(kvm, pmd, addr); - range = PMD_SIZE; - if (pmd_empty(pmd)) { + next = pmd_addr_end(addr, end); + if (page_empty(pmd) && !page_empty(pud)) { clear_pud_entry(kvm, pud, addr); - range = PUD_SIZE; + next = pud_addr_end(addr, end); } } - addr += range; + addr = next; } } @@ -495,7 +489,6 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) { pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE); - kvm_set_s2pte_writable(&pte); ret = mmu_topup_memory_cache(&cache, 2, 2); if (ret) diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c index b7840e7aa452..71e08baee209 100644 --- a/arch/arm/kvm/reset.c +++ b/arch/arm/kvm/reset.c @@ -40,7 +40,7 @@ static struct kvm_regs a15_regs_reset = { }; static const struct kvm_irq_level a15_vtimer_irq = { - .irq = 27, + { .irq = 27 }, .level = 1, }; diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h index a8e73ed5ad5b..b1d640f78623 100644 --- a/arch/arm/kvm/trace.h +++ b/arch/arm/kvm/trace.h @@ -59,10 +59,9 @@ TRACE_EVENT(kvm_guest_fault, __entry->ipa = ipa; ), - TP_printk("guest fault at PC %#08lx (hxfar %#08lx, " - "ipa %#16llx, hsr %#08lx", - __entry->vcpu_pc, __entry->hxfar, - __entry->ipa, __entry->hsr) + TP_printk("ipa %#llx, hsr %#08lx, hxfar %#08lx, pc %#08lx", + __entry->ipa, __entry->hsr, + __entry->hxfar, __entry->vcpu_pc) ); TRACE_EVENT(kvm_irq_line, diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index af72969820b4..aaf3a8731136 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -45,3 +45,9 @@ lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S + +ifeq ($(CONFIG_KERNEL_MODE_NEON),y) + NEON_FLAGS := -mfloat-abi=softfp -mfpu=neon + CFLAGS_xor-neon.o += $(NEON_FLAGS) + lib-$(CONFIG_XOR_BLOCKS) += xor-neon.o +endif diff --git a/arch/arm/lib/xor-neon.c b/arch/arm/lib/xor-neon.c new file mode 100644 index 000000000000..f485e5a2af4b --- /dev/null +++ b/arch/arm/lib/xor-neon.c @@ -0,0 +1,42 @@ +/* + * linux/arch/arm/lib/xor-neon.c + * + * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/raid/xor.h> + +#ifndef __ARM_NEON__ +#error You should compile this file with '-mfloat-abi=softfp -mfpu=neon' +#endif + +/* + * Pull in the reference implementations while instructing GCC (through + * -ftree-vectorize) to attempt to exploit implicit parallelism and emit + * NEON instructions. + */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) +#pragma GCC optimize "tree-vectorize" +#else +/* + * While older versions of GCC do not generate incorrect code, they fail to + * recognize the parallel nature of these functions, and emit plain ARM code, + * which is known to be slower than the optimized ARM code in asm-arm/xor.h. + */ +#warning This code requires at least version 4.6 of GCC +#endif + +#pragma GCC diagnostic ignored "-Wunused-variable" +#include <asm-generic/xor.h> + +struct xor_block_template const xor_block_neon_inner = { + .name = "__inner_neon__", + .do_2 = xor_8regs_2, + .do_3 = xor_8regs_3, + .do_4 = xor_8regs_4, + .do_5 = xor_8regs_5, +}; diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 2abee6626aac..916e5a142917 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -227,6 +227,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk), + CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk), + CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk), CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk), diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index ad95f6a23a28..bf00d15d954d 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -42,20 +42,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy) { int value; -#define GMII_RCCPSR 260 -#define GMII_RRDPSR 261 -#define GMII_ERCR 11 -#define GMII_ERDWR 12 - /* Set delay values */ - value = GMII_RCCPSR | 0x8000; - phy_write(phy, GMII_ERCR, value); + value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000; + phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); value = 0xF2F4; - phy_write(phy, GMII_ERDWR, value); - value = GMII_RRDPSR | 0x8000; - phy_write(phy, GMII_ERCR, value); + phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); + value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000; + phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value); value = 0x2222; - phy_write(phy, GMII_ERDWR, value); + phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value); return 0; } diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 3aaa9784cf0e..f1d49e929ccb 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -26,7 +26,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h index 8e7ed5c90817..048a57f76bd3 100644 --- a/arch/arm/mach-at91/include/mach/at91_adc.h +++ b/arch/arm/mach-at91/include/mach/at91_adc.h @@ -28,9 +28,12 @@ #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ -#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ +#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ +#define AT91_ADC_PRESCAL_9G45 (0xff << 8) #define AT91_ADC_PRESCAL_(x) ((x) << 8) -#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ +#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ +#define AT91_ADC_STARTUP_9G45 (0x7f << 16) +#define AT91_ADC_STARTUP_9X5 (0xf << 16) #define AT91_ADC_STARTUP_(x) ((x) << 16) #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ #define AT91_ADC_SHTIM_(x) ((x) << 24) @@ -48,6 +51,9 @@ #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ +#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ +#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ + #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ #define AT91_ADC_LDATA (0x3ff) @@ -58,4 +64,10 @@ #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ #define AT91_ADC_DATA (0x3ff) +#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ + +#define AT91_ADC_TRGR_9260 AT91_ADC_MR +#define AT91_ADC_TRGR_9G45 0x08 +#define AT91_ADC_TRGR_9X5 0xC0 + #endif diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index f11289519c39..69d67f714a2f 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -12,6 +12,7 @@ config ARCH_BCM select GPIO_BCM select SPARSE_IRQ select TICK_ONESHOT + select CACHE_L2X0 help This enables support for system based on Broadcom SoCs. It currently supports the 'BCM281XX' family, which includes diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 6adb6aecf48f..e3d03033a7e2 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2012 Broadcom Corporation +# Copyright (C) 2012-2013 Broadcom Corporation # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -10,6 +10,6 @@ # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -obj-$(CONFIG_ARCH_BCM) := board_bcm.o bcm_kona_smc.o bcm_kona_smc_asm.o +obj-$(CONFIG_ARCH_BCM) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index 56d9d19b2470..5e31e918f325 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -36,18 +36,20 @@ struct bcm_kona_smc_data { }; static const struct of_device_id bcm_kona_smc_ids[] __initconst = { - {.compatible = "bcm,kona-smc"}, + {.compatible = "brcm,kona-smc"}, + {.compatible = "bcm,kona-smc"}, /* deprecated name */ {}, }; /* Map in the bounce area */ -void __init bcm_kona_smc_init(void) +int __init bcm_kona_smc_init(void) { struct device_node *node; /* Read buffer addr and size from the device tree node */ node = of_find_matching_node(NULL, bcm_kona_smc_ids); - BUG_ON(!node); + if (!node) + return -ENODEV; /* Don't care about size or flags of the DT node */ bridge_data.buffer_addr = @@ -59,7 +61,9 @@ void __init bcm_kona_smc_init(void) bridge_data.initialized = 1; - pr_info("Secure API initialized!\n"); + pr_info("Kona Secure API initialized\n"); + + return 0; } /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */ diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h index 3bedbed1c21b..d098a7e76744 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.h +++ b/arch/arm/mach-bcm/bcm_kona_smc.h @@ -64,7 +64,7 @@ #define SSAPI_BRCM_START_VC_CORE 0x0E000008 #ifndef __ASSEMBLY__ -extern void bcm_kona_smc_init(void); +extern int __init bcm_kona_smc_init(void); extern unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm281xx.c index 28599326d4ad..8d9f931164bb 100644 --- a/arch/arm/mach-bcm/board_bcm.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Broadcom Corporation + * Copyright (C) 2012-2013 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,23 +21,39 @@ #include <asm/mach/time.h> #include <asm/hardware/cache-l2x0.h> - #include "bcm_kona_smc.h" +#include "kona.h" static int __init kona_l2_cache_init(void) { if (!IS_ENABLED(CONFIG_CACHE_L2X0)) return 0; + if (bcm_kona_smc_init() < 0) { + pr_info("Kona secure API not available. Skipping L2 init\n"); + return 0; + } + bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); /* * The aux_val and aux_mask have no effect since L2 cache is already * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. */ - l2x0_of_init(0, ~0); + return l2x0_of_init(0, ~0); +} - return 0; +static void bcm_board_setup_restart(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "brcm,bcm11351"); + if (np) { + if (of_device_is_available(np)) + bcm_kona_setup_restart(); + of_node_put(np); + } + /* Restart setup for other boards goes here */ } static void __init board_init(void) @@ -45,15 +61,15 @@ static void __init board_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, &platform_bus); - bcm_kona_smc_init(); - + bcm_board_setup_restart(); kona_l2_cache_init(); } -static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, }; +static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") .init_time = clocksource_of_init, .init_machine = board_init, + .restart = bcm_kona_restart, .dt_compat = bcm11351_dt_compat, MACHINE_END diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c new file mode 100644 index 000000000000..6939d9017f63 --- /dev/null +++ b/arch/arm/mach-bcm/kona.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/of_address.h> +#include <asm/io.h> + +#include "kona.h" + +static void __iomem *watchdog_base; + +void bcm_kona_setup_restart(void) +{ + struct device_node *np_wdog; + + /* + * The assumption is that whoever calls bcm_kona_setup_restart() + * also needs a Kona Watchdog Timer entry in Device Tree, i.e. we + * report an error if the DT entry is missing. + */ + np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt"); + if (!np_wdog) { + pr_err("brcm,kona-wdt not found in DT, reboot disabled\n"); + return; + } + watchdog_base = of_iomap(np_wdog, 0); + WARN(!watchdog_base, "failed to map watchdog base"); + of_node_put(np_wdog); +} + +#define SECWDOG_OFFSET 0x00000000 +#define SECWDOG_RESERVED_MASK 0xE2000000 +#define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000 +#define SECWDOG_EN_MASK 0x08000000 +#define SECWDOG_SRSTEN_MASK 0x04000000 +#define SECWDOG_CLKS_SHIFT 20 +#define SECWDOG_LOCK_SHIFT 0 + +void bcm_kona_restart(enum reboot_mode mode, const char *cmd) +{ + uint32_t val; + + if (!watchdog_base) + panic("Watchdog not mapped. Reboot failed.\n"); + + /* Enable watchdog2 with very short timeout. */ + val = readl(watchdog_base + SECWDOG_OFFSET); + val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK; + val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK | + (0x8 << SECWDOG_CLKS_SHIFT) | + (0x8 << SECWDOG_LOCK_SHIFT); + writel(val, watchdog_base + SECWDOG_OFFSET); + + while (1) + ; +} diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h new file mode 100644 index 000000000000..291eca3e06ff --- /dev/null +++ b/arch/arm/mach-bcm/kona.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/reboot.h> + +void bcm_kona_setup_restart(void); +void bcm_kona_restart(enum reboot_mode mode, const char *cmd); diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 01ad4d41e728..bea6295c8c59 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -33,9 +33,6 @@ config ARCH_P720T Say Y here if you intend to run this kernel on the ARM Prospector 720T. -config ARCH_FORTUNET - bool "FORTUNET" - config EP72XX_ROM_BOOT bool "EP721x/EP731x ROM boot" help diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index f30ed2b496fb..f04151efd96a 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -10,5 +10,4 @@ obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o obj-$(CONFIG_ARCH_CLEP7312) += board-clep7312.o obj-$(CONFIG_ARCH_EDB7211) += board-edb7211.o -obj-$(CONFIG_ARCH_FORTUNET) += board-fortunet.o obj-$(CONFIG_ARCH_P720T) += board-p720t.o diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index 5867aebd8d0c..f8d71a89644a 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -259,11 +259,7 @@ static void __init autcpu12_init(void) static void __init autcpu12_init_late(void) { gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios)); - - if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) { - /* We are need both drivers to handle NAND */ - platform_device_register(&autcpu12_nand_pdev); - } + platform_device_register(&autcpu12_nand_pdev); } MACHINE_START(AUTCPU12, "autronix autcpu12") diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index 9dfb990f0801..fe6184ead896 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c @@ -126,21 +126,6 @@ static struct gpio edb7211_gpios[] __initconst = { { EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" }, }; -static struct map_desc edb7211_io_desc[] __initdata = { - { /* Memory-mapped extra keyboard row */ - .virtual = IO_ADDRESS(EDB7211_EXTKBD_BASE), - .pfn = __phys_to_pfn(EDB7211_EXTKBD_BASE), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -void __init edb7211_map_io(void) -{ - clps711x_map_io(); - iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc)); -} - /* Reserve screen memory region at the start of main system memory. */ static void __init edb7211_reserve(void) { @@ -195,7 +180,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_edb7211, .reserve = edb7211_reserve, - .map_io = edb7211_map_io, + .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c deleted file mode 100644 index b1561e3d7c5c..000000000000 --- a/arch/arm/mach-clps711x/board-fortunet.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * linux/arch/arm/mach-clps711x/fortunet.c - * - * Derived from linux/arch/arm/mach-integrator/arch.c - * - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/types.h> -#include <linux/init.h> -#include <linux/initrd.h> - -#include <mach/hardware.h> -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> - -#include <asm/memory.h> - -#include "common.h" - -struct meminfo memmap = { - .nr_banks = 1, - .bank = { - { - .start = 0xC0000000, - .size = 0x01000000, - }, - }, -}; - -typedef struct tag_IMAGE_PARAMS -{ - int ramdisk_ok; - int ramdisk_address; - int ramdisk_size; - int ram_size; - int extra_param_type; - int extra_param_ptr; - int command_line; -} IMAGE_PARAMS; - -#define IMAGE_PARAMS_PHYS 0xC01F0000 - -static void __init -fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) -{ - IMAGE_PARAMS *ip = phys_to_virt(IMAGE_PARAMS_PHYS); - *cmdline = phys_to_virt(ip->command_line); -#ifdef CONFIG_BLK_DEV_INITRD - if(ip->ramdisk_ok) - { - initrd_start = __phys_to_virt(ip->ramdisk_address); - initrd_end = initrd_start + ip->ramdisk_size; - } -#endif - memmap.bank[0].size = ip->ram_size; - *mi = memmap; -} - -MACHINE_START(FORTUNET, "ARM-FortuNet") - /* Maintainer: FortuNet Inc. */ - .nr_irqs = CLPS711X_NR_IRQS, - .fixup = fortunet_fixup, - .map_io = clps711x_map_io, - .init_early = clps711x_init_early, - .init_irq = clps711x_init_irq, - .init_time = clps711x_timer_init, - .handle_irq = clps711x_handle_irq, - .restart = clps711x_restart, -MACHINE_END diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c index 856b81cf2f8a..fb77d1448fec 100644 --- a/arch/arm/mach-clps711x/devices.c +++ b/arch/arm/mach-clps711x/devices.c @@ -57,7 +57,7 @@ static void __init clps711x_add_syscon(void) unsigned i; for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) - platform_device_register_simple("clps711x-syscon", i + 1, + platform_device_register_simple("syscon", i + 1, &clps711x_syscon_res[i], 1); } diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 1332de8c52c9..c4bdc0a1c36e 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -185,10 +185,6 @@ static __init void da830_evm_usb_init(void) __func__, ret); } -static struct davinci_uart_config da830_evm_uart_config __initdata = { - .enabled_uarts = 0x7, -}; - static const short da830_evm_mcasp1_pins[] = { DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, @@ -630,7 +626,7 @@ static __init void da830_evm_init(void) pr_warning("da830_evm_init: watchdog registration failed: %d\n", ret); - davinci_serial_init(&da830_evm_uart_config); + davinci_serial_init(da8xx_serial_device); i2c_register_board_info(1, da830_evm_i2c_devices, ARRAY_SIZE(da830_evm_i2c_devices)); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index bea6793a7ede..dd1fb24521aa 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -19,7 +19,7 @@ #include <linux/kernel.h> #include <linux/i2c.h> #include <linux/i2c/at24.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/input.h> #include <linux/input/tps6507x-ts.h> #include <linux/mfd/tps6507x.h> @@ -746,10 +746,6 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { .bus_delay = 0, /* usec */ }; -static struct davinci_uart_config da850_evm_uart_config __initdata = { - .enabled_uarts = 0x7, -}; - /* davinci da850 evm audio machine driver */ static u8 da850_iis_serializer_direction[] = { INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, @@ -1249,12 +1245,10 @@ static struct vpif_capture_config da850_vpif_capture_config = { static struct adv7343_platform_data adv7343_pdata = { .mode_config = { - .dac_3 = 1, - .dac_2 = 1, - .dac_1 = 1, + .dac = { 1, 1, 1 }, }, .sd_config = { - .sd_dac_out1 = 1, + .sd_dac_out = { 1 }, }, }; @@ -1494,7 +1488,7 @@ static __init void da850_evm_init(void) __func__, ret); } - davinci_serial_init(&da850_evm_uart_config); + davinci_serial_init(da8xx_serial_device); i2c_register_board_info(1, da850_evm_i2c_devices, ARRAY_SIZE(da850_evm_i2c_devices)); diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index c2a0a67d09e0..42b23a3194a0 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -314,10 +314,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = { &davinci_nand_device, }; -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init dm355_evm_map_io(void) { dm355_init(); @@ -393,7 +389,7 @@ static __init void dm355_evm_init(void) platform_add_devices(davinci_evm_devices, ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); - davinci_serial_init(&uart_config); + davinci_serial_init(dm355_serial_device); /* NOTE: NAND flash timings set by the UBL are slower than * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index dff4ddc5ef81..65a984c52df6 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -75,6 +75,7 @@ static struct davinci_nand_pdata davinci_nand_data = { .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), .ecc_mode = NAND_ECC_HW_SYNDROME, + .ecc_bits = 4, .bbt_options = NAND_BBT_USE_FLASH, }; @@ -172,10 +173,6 @@ static struct platform_device *davinci_leopard_devices[] __initdata = { &davinci_nand_device, }; -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init dm355_leopard_map_io(void) { dm355_init(); @@ -251,7 +248,7 @@ static __init void dm355_leopard_init(void) platform_add_devices(davinci_leopard_devices, ARRAY_SIZE(davinci_leopard_devices)); leopard_init_i2c(); - davinci_serial_init(&uart_config); + davinci_serial_init(dm355_serial_device); /* NOTE: NAND flash timings set by the UBL are slower than * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 4cdb61c54459..92b7f770615a 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -718,10 +718,6 @@ fail: /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ } -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init dm365_evm_map_io(void) { dm365_init(); @@ -748,7 +744,7 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = { static __init void dm365_evm_init(void) { evm_init_i2c(); - davinci_serial_init(&uart_config); + davinci_serial_init(dm365_serial_device); dm365evm_emac_configure(); dm365evm_mmc_configure(); diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index a33686a6fbb2..40bb9b5b87e8 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -153,6 +153,7 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = { .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, + .ecc_bits = 1, .bbt_options = NAND_BBT_USE_FLASH, .timing = &davinci_evm_nandflash_timing, }; @@ -726,10 +727,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = { &rtc_dev, }; -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init davinci_evm_map_io(void) { @@ -791,7 +788,7 @@ static __init void davinci_evm_init(void) davinci_setup_mmc(0, &dm6446evm_mmc_config); dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); - davinci_serial_init(&uart_config); + davinci_serial_init(dm644x_serial_device); dm644x_init_asp(&dm644x_evm_snd_data); /* irlml6401 switches over 1A, in under 8 msec */ diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index fbb8e5ab1dc1..2bc3651d56cc 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -90,6 +90,7 @@ static struct davinci_nand_pdata davinci_nand_data = { .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), .ecc_mode = NAND_ECC_HW, + .ecc_bits = 1, .options = 0, }; @@ -749,10 +750,6 @@ static void __init davinci_map_io(void) cdce_clk_init(); } -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - #define DM646X_EVM_PHY_ID "davinci_mdio-0:01" /* * The following EDMA channels/slots are not being used by drivers (for @@ -792,7 +789,7 @@ static __init void evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; evm_init_i2c(); - davinci_serial_init(&uart_config); + davinci_serial_init(dm646x_serial_device); dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 9549d53aa63f..cd0f58730c2b 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -434,10 +434,6 @@ static void __init mityomapl138_setup_nand(void) ARRAY_SIZE(mityomapl138_devices)); } -static struct davinci_uart_config mityomapl138_uart_config __initdata = { - .enabled_uarts = 0x7, -}; - static const short mityomap_mii_pins[] = { DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, @@ -517,7 +513,7 @@ static void __init mityomapl138_init(void) if (ret) pr_warning("watchdog registration failed: %d\n", ret); - davinci_serial_init(&mityomapl138_uart_config); + davinci_serial_init(da8xx_serial_device); ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); if (ret) diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 2bc112adf565..46f336fca803 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -88,6 +88,7 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = { .parts = davinci_ntosd2_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition), .ecc_mode = NAND_ECC_HW, + .ecc_bits = 1, .bbt_options = NAND_BBT_USE_FLASH, }; @@ -153,10 +154,6 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = { &ntosd2_leds_dev, }; -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init davinci_ntosd2_map_io(void) { dm644x_init(); @@ -197,7 +194,7 @@ static __init void davinci_ntosd2_init(void) platform_add_devices(davinci_ntosd2_devices, ARRAY_SIZE(davinci_ntosd2_devices)); - davinci_serial_init(&uart_config); + davinci_serial_init(dm644x_serial_device); dm644x_init_asp(&dm644x_ntosd2_snd_data); soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index b8c20de10ca2..ab98c75cabb4 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -286,15 +286,11 @@ usb11_setup_oc_fail: gpio_free(DA850_USB1_VBUS_PIN); } -static struct davinci_uart_config omapl138_hawk_uart_config __initdata = { - .enabled_uarts = 0x7, -}; - static __init void omapl138_hawk_init(void) { int ret; - davinci_serial_init(&omapl138_hawk_uart_config); + davinci_serial_init(da8xx_serial_device); omapl138_hawk_config_emac(); diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 513eee14f77d..d84360148100 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -125,10 +125,6 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = { &davinci_sffsdr_nandflash_device, }; -static struct davinci_uart_config uart_config __initdata = { - .enabled_uarts = (1 << 0), -}; - static void __init davinci_sffsdr_map_io(void) { dm644x_init(); @@ -141,7 +137,7 @@ static __init void davinci_sffsdr_init(void) platform_add_devices(davinci_sffsdr_devices, ARRAY_SIZE(davinci_sffsdr_devices)); sffsdr_init_i2c(); - davinci_serial_init(&uart_config); + davinci_serial_init(dm644x_serial_device); soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; davinci_setup_usb(0, 0); /* We support only peripheral mode. */ diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index 36aef3a7dedb..f1ac1c94ac0f 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -65,7 +65,7 @@ static struct cpuidle_driver davinci_idle_driver = { .states[1] = { .enter = davinci_enter_idle, .exit_latency = 10, - .target_residency = 100000, + .target_residency = 10000, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "DDR SR", .desc = "WFI and DDR Self Refresh", diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index abbaf0270be6..d6c746e35ad9 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -395,9 +395,9 @@ static struct clk_lookup da830_clks[] = { CLK(NULL, "tptc0", &tptc0_clk), CLK(NULL, "tptc1", &tptc1_clk), CLK("da830-mmc.0", NULL, &mmcsd_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), CLK(NULL, "ecap0", &ecap0_clk), @@ -417,6 +417,7 @@ static struct clk_lookup da830_clks[] = { CLK(NULL, "aintc", &aintc_clk), CLK(NULL, "secu_mgr", &secu_mgr_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK(NULL, "gpio", &gpio_clk), CLK("i2c_davinci.2", NULL, &i2c1_clk), CLK(NULL, "usb11", &usb11_clk), @@ -1199,7 +1200,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = { .gpio_base = DA8XX_GPIO_BASE, .gpio_num = 128, .gpio_irq = IRQ_DA8XX_GPIO0, - .serial_dev = &da8xx_serial_device, .emac_pdata = &da8xx_emac_pdata, }; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index a0d4f6038b60..f56e5fbfa2fd 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -451,9 +451,9 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "tpcc1", &tpcc1_clk), CLK(NULL, "tptc2", &tptc2_clk), CLK("pruss_uio", "pruss", &pruss_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK(NULL, "aintc", &aintc_clk), CLK(NULL, "gpio", &gpio_clk), CLK("i2c_davinci.2", NULL, &i2c1_clk), @@ -461,6 +461,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "arm", &arm_clk), CLK(NULL, "rmii", &rmii_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK("da8xx_lcdc.0", "fck", &lcdc_clk), CLK("da830-mmc.0", NULL, &mmcsd0_clk), @@ -1301,7 +1302,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = { .gpio_base = DA8XX_GPIO_BASE, .gpio_num = 144, .gpio_irq = IRQ_DA8XX_GPIO0, - .serial_dev = &da8xx_serial_device, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 961aea8bbad5..d2bc574ae172 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -20,13 +20,6 @@ #define DA8XX_NUM_UARTS 3 -static void __init da8xx_uart_clk_enable(void) -{ - int i; - for (i = 0; i < DA8XX_NUM_UARTS; i++) - davinci_serial_setup_clk(i, NULL); -} - static struct of_device_id da8xx_irq_match[] __initdata = { { .compatible = "ti,cp-intc", .data = cp_intc_of_init, }, { } @@ -47,6 +40,12 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), + OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL), + OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL), + OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL), + OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL), + OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1", + NULL), {} }; @@ -57,7 +56,6 @@ static void __init da850_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, da850_auxdata_lookup, NULL); - da8xx_uart_clk_enable(); } static const char *da850_boards_compat[] __initdata = { diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index a883043d0820..2ab5d577186f 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -106,4 +106,9 @@ int dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); + +extern struct platform_device dm365_serial_device[]; +extern struct platform_device dm355_serial_device[]; +extern struct platform_device dm644x_serial_device[]; +extern struct platform_device dm646x_serial_device[]; #endif /*__DAVINCI_H */ diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 71a46a348761..2e473fefd71e 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -68,7 +68,7 @@ void __iomem *da8xx_syscfg0_base; void __iomem *da8xx_syscfg1_base; -static struct plat_serial8250_port da8xx_serial_pdata[] = { +static struct plat_serial8250_port da8xx_serial0_pdata[] = { { .mapbase = DA8XX_UART0_BASE, .irq = IRQ_DA8XX_UARTINT0, @@ -78,6 +78,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port da8xx_serial1_pdata[] = { + { .mapbase = DA8XX_UART1_BASE, .irq = IRQ_DA8XX_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -86,6 +91,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port da8xx_serial2_pdata[] = { + { .mapbase = DA8XX_UART2_BASE, .irq = IRQ_DA8XX_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -95,15 +105,33 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = { }, { .flags = 0, - }, + } }; -struct platform_device da8xx_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = da8xx_serial_pdata, +struct platform_device da8xx_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = da8xx_serial0_pdata, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = da8xx_serial1_pdata, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = da8xx_serial2_pdata, + } }, + { + } }; static s8 da8xx_queue_tc_mapping[][2] = { @@ -453,12 +481,8 @@ int __init da8xx_register_emac(void) ret = platform_device_register(&da8xx_mdio_device); if (ret < 0) return ret; - ret = platform_device_register(&da8xx_emac_device); - if (ret < 0) - return ret; - ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), - NULL, &da8xx_emac_device.dev); - return ret; + + return platform_device_register(&da8xx_emac_device); } static struct resource da830_mcasp1_resources[] = { @@ -828,14 +852,7 @@ static struct platform_device da8xx_rtc_device = { int da8xx_register_rtc(void) { - int ret; - - ret = platform_device_register(&da8xx_rtc_device); - if (!ret) - /* Atleast on DA850, RTC is a wakeup source */ - device_init_wakeup(&da8xx_rtc_device.dev, true); - - return ret; + return platform_device_register(&da8xx_rtc_device); } static void __iomem *da8xx_ddr2_ctlr_base; diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 128cb9ae80f4..01d8686e553c 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -126,7 +126,7 @@ static struct platform_device edma_device = { .dev.platform_data = tnetv107x_edma_info, }; -static struct plat_serial8250_port serial_data[] = { +static struct plat_serial8250_port serial0_platform_data[] = { { .mapbase = TNETV107X_UART0_BASE, .irq = IRQ_TNETV107X_UART0, @@ -137,6 +137,11 @@ static struct plat_serial8250_port serial_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port serial1_platform_data[] = { + { .mapbase = TNETV107X_UART1_BASE, .irq = IRQ_TNETV107X_UART1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -146,6 +151,11 @@ static struct plat_serial8250_port serial_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port serial2_platform_data[] = { + { .mapbase = TNETV107X_UART2_BASE, .irq = IRQ_TNETV107X_UART2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -156,13 +166,28 @@ static struct plat_serial8250_port serial_data[] = { }, { .flags = 0, - }, + } }; -struct platform_device tnetv107x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial_data, + +struct platform_device tnetv107x_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = serial0_platform_data, + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev.platform_data = serial1_platform_data, + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev.platform_data = serial2_platform_data, + }, + { + } }; static struct resource mmc0_resources[] = { @@ -385,7 +410,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) platform_device_register(&tsc_device); if (info->serial_config) - davinci_serial_init(info->serial_config); + davinci_serial_init(tnetv107x_serial_device); for (i = 0; i < 2; i++) if (info->mmc_config[i]) { diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 86100d179694..3eaa5f6b2160 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -357,9 +357,9 @@ static struct clk_lookup dm355_clks[] = { CLK(NULL, "clkout3", &clkout3_clk), CLK(NULL, "arm", &arm_clk), CLK(NULL, "mjcp", &mjcp_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("davinci-mcbsp.0", NULL, &asp0_clk), CLK("davinci-mcbsp.1", NULL, &asp1_clk), @@ -922,7 +922,7 @@ static struct davinci_timer_info dm355_timer_info = { .clocksource_id = T0_TOP, }; -static struct plat_serial8250_port dm355_serial_platform_data[] = { +static struct plat_serial8250_port dm355_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -932,6 +932,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm355_serial1_platform_data[] = { + { .mapbase = DAVINCI_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -940,6 +945,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm355_serial2_platform_data[] = { + { .mapbase = DM355_UART2_BASE, .irq = IRQ_DM355_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -948,16 +958,34 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm355_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm355_serial_platform_data, +struct platform_device dm355_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm355_serial0_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm355_serial1_platform_data, + } }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = dm355_serial2_platform_data, + } + }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm355 = { @@ -981,7 +1009,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 104, .gpio_irq = IRQ_DM355_GPIOBNK0, - .serial_dev = &dm355_serial_device, .sram_dma = 0x00010000, .sram_len = SZ_32K, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index dad28029ba9b..c29e324eb0bb 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -455,8 +455,8 @@ static struct clk_lookup dm365_clks[] = { CLK("vpss", "master", &vpss_master_clk), CLK("vpss", "slave", &vpss_slave_clk), CLK(NULL, "arm", &arm_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("da830-mmc.0", NULL, &mmcsd0_clk), CLK("da830-mmc.1", NULL, &mmcsd1_clk), @@ -477,6 +477,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "timer3", &timer3_clk), CLK(NULL, "usb", &usb_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK("davinci_voicecodec", NULL, &voicecodec_clk), CLK("davinci-mcbsp", NULL, &asp0_clk), CLK(NULL, "rto", &rto_clk), @@ -1041,7 +1042,7 @@ static struct davinci_timer_info dm365_timer_info = { #define DM365_UART1_BASE (IO_PHYS + 0x106000) -static struct plat_serial8250_port dm365_serial_platform_data[] = { +static struct plat_serial8250_port dm365_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -1051,6 +1052,11 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm365_serial1_platform_data[] = { + { .mapbase = DM365_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -1059,16 +1065,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm365_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm365_serial_platform_data, +struct platform_device dm365_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm365_serial0_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm365_serial1_platform_data, + } }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm365 = { @@ -1093,7 +1110,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { .gpio_num = 104, .gpio_irq = IRQ_DM365_GPIO0, .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ - .serial_dev = &dm365_serial_device, .emac_pdata = &dm365_emac_pdata, .sram_dma = 0x00010000, .sram_len = SZ_32K, @@ -1407,8 +1423,6 @@ static int __init dm365_init_devices(void) platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); - clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), - NULL, &dm365_emac_device.dev); return 0; } diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index a49d18246fe9..4f74682293d6 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -303,10 +303,11 @@ static struct clk_lookup dm644x_clks[] = { CLK("vpss", "master", &vpss_master_clk), CLK("vpss", "slave", &vpss_slave_clk), CLK(NULL, "arm", &arm_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("palm_bk3710", NULL, &ide_clk), CLK("davinci-mcbsp", NULL, &asp_clk), @@ -813,7 +814,7 @@ static struct davinci_timer_info dm644x_timer_info = { .clocksource_id = T0_TOP, }; -static struct plat_serial8250_port dm644x_serial_platform_data[] = { +static struct plat_serial8250_port dm644x_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -823,6 +824,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm644x_serial1_platform_data[] = { + { .mapbase = DAVINCI_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -831,6 +837,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm644x_serial2_platform_data[] = { + { .mapbase = DAVINCI_UART2_BASE, .irq = IRQ_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -839,16 +850,34 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm644x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm644x_serial_platform_data, +struct platform_device dm644x_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm644x_serial0_platform_data, + } }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm644x_serial1_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = dm644x_serial2_platform_data, + } + }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm644x = { @@ -872,7 +901,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 71, .gpio_irq = IRQ_GPIOBNK0, - .serial_dev = &dm644x_serial_device, .emac_pdata = &dm644x_emac_pdata, .sram_dma = 0x00008000, .sram_len = SZ_16K, @@ -923,8 +951,6 @@ static int __init dm644x_init_devices(void) platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); - clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev), - NULL, &dm644x_emac_device.dev); return 0; } diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index d1259e80141b..68f8d1f1aca1 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -342,15 +342,16 @@ static struct clk_lookup dm646x_clks[] = { CLK(NULL, "edma_tc1", &edma_tc1_clk), CLK(NULL, "edma_tc2", &edma_tc2_clk), CLK(NULL, "edma_tc3", &edma_tc3_clk), - CLK(NULL, "uart0", &uart0_clk), - CLK(NULL, "uart1", &uart1_clk), - CLK(NULL, "uart2", &uart2_clk), + CLK("serial8250.0", NULL, &uart0_clk), + CLK("serial8250.1", NULL, &uart1_clk), + CLK("serial8250.2", NULL, &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK(NULL, "gpio", &gpio_clk), CLK("davinci-mcasp.0", NULL, &mcasp0_clk), CLK("davinci-mcasp.1", NULL, &mcasp1_clk), CLK(NULL, "aemif", &aemif_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci_mdio.0", "fck", &emac_clk), CLK(NULL, "pwm0", &pwm0_clk), CLK(NULL, "pwm1", &pwm1_clk), CLK(NULL, "timer0", &timer0_clk), @@ -790,7 +791,7 @@ static struct davinci_timer_info dm646x_timer_info = { .clocksource_id = T0_TOP, }; -static struct plat_serial8250_port dm646x_serial_platform_data[] = { +static struct plat_serial8250_port dm646x_serial0_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, .irq = IRQ_UARTINT0, @@ -800,6 +801,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm646x_serial1_platform_data[] = { + { .mapbase = DAVINCI_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -808,6 +814,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { .regshift = 2, }, { + .flags = 0, + } +}; +static struct plat_serial8250_port dm646x_serial2_platform_data[] = { + { .mapbase = DAVINCI_UART2_BASE, .irq = IRQ_DM646X_UARTINT2, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | @@ -816,16 +827,34 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = { .regshift = 2, }, { - .flags = 0 - }, + .flags = 0, + } }; -static struct platform_device dm646x_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = dm646x_serial_platform_data, +struct platform_device dm646x_serial_device[] = { + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm646x_serial0_platform_data, + } + }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = dm646x_serial1_platform_data, + } }, + { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = dm646x_serial2_platform_data, + } + }, + { + } }; static struct davinci_soc_info davinci_soc_info_dm646x = { @@ -849,7 +878,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .gpio_base = DAVINCI_GPIO_BASE, .gpio_num = 43, /* Only 33 usable */ .gpio_irq = IRQ_DM646X_GPIOBNK0, - .serial_dev = &dm646x_serial_device, .emac_pdata = &dm646x_emac_pdata, .sram_dma = 0x10010000, .sram_len = SZ_32K, @@ -913,8 +941,6 @@ static int __init dm646x_init_devices(void) platform_device_register(&dm646x_mdio_device); platform_device_register(&dm646x_emac_device); - clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev), - NULL, &dm646x_emac_device.dev); return 0; } diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index cce316b92c06..0b3c169758ed 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -72,7 +72,6 @@ struct davinci_soc_info { unsigned gpio_unbanked; struct davinci_gpio_controller *gpio_ctlrs; int gpio_ctlrs_num; - struct platform_device *serial_dev; struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; unsigned sram_len; diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 7b41a5e9bc31..aae53072c0eb 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -111,7 +111,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd); void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); -extern struct platform_device da8xx_serial_device; +extern struct platform_device da8xx_serial_device[]; extern struct emac_platform_data da8xx_emac_pdata; extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S deleted file mode 100644 index b18b8ebc6508..000000000000 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Debugging macro for DaVinci - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -/* Modifications - * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart - * macros, based on debug-8250.S file - * but using 32-bit accesses required for - * some davinci devices. - */ - -#include <linux/serial_reg.h> - -#include <mach/serial.h> - -#define UART_SHIFT 2 - -#if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0) -#define UART_BASE DAVINCI_UART0_BASE -#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1) -#define UART_BASE DA8XX_UART1_BASE -#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2) -#define UART_BASE DA8XX_UART2_BASE -#elif defined(CONFIG_DEBUG_DAVINCI_TNETV107X_UART1) -#define UART_BASE TNETV107X_UART2_BASE -#define UART_VIRTBASE TNETV107X_UART2_VIRT -#else -#error "Select a specifc port for DEBUG_LL" -#endif - -#ifndef UART_VIRTBASE -#define UART_VIRTBASE IO_ADDRESS(UART_BASE) -#endif - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_BASE - ldr \rv, =UART_VIRTBASE - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - .macro waituart,rd,rx -#ifdef FLOW_CONTROL -1001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT] - tst \rd, #UART_MSR_CTS - beq 1001b -#endif - .endm - diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 62ad300440f5..52b8571b2e70 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -15,6 +15,8 @@ #include <mach/hardware.h> +#include <linux/platform_device.h> + #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) @@ -37,13 +39,7 @@ #define UART_DM646X_SCR_TX_WATERMARK 0x08 #ifndef __ASSEMBLY__ -struct davinci_uart_config { - /* Bit field of UARTs present; bit 0 --> UART0 */ - unsigned int enabled_uarts; -}; - -extern int davinci_serial_init(struct davinci_uart_config *); -extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate); +extern int davinci_serial_init(struct platform_device *); #endif #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index 16314c64f755..494fcf5ccfe1 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -42,7 +42,6 @@ #include <mach/serial.h> struct tnetv107x_device_info { - struct davinci_uart_config *serial_config; struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ struct matrix_keypad_platform_data *keypad_config; @@ -50,7 +49,7 @@ struct tnetv107x_device_info { }; extern struct platform_device tnetv107x_wdt_device; -extern struct platform_device tnetv107x_serial_device; +extern struct platform_device tnetv107x_serial_device[]; extern void tnetv107x_init(void); extern void tnetv107x_devices_init(struct tnetv107x_device_info *); diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index f2625814c3c9..5e93a734c858 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -70,49 +70,36 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p) UART_DM646X_SCR_TX_WATERMARK); } -/* Enable UART clock and obtain its rate */ -int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate) +int __init davinci_serial_init(struct platform_device *serial_dev) { - char name[16]; + int i, ret = 0; + struct device *dev; + struct plat_serial8250_port *p; struct clk *clk; - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct device *dev = &soc_info->serial_dev->dev; - - sprintf(name, "uart%d", instance); - clk = clk_get(dev, name); - if (IS_ERR(clk)) { - pr_err("%s:%d: failed to get UART%d clock\n", - __func__, __LINE__, instance); - return PTR_ERR(clk); - } - - clk_prepare_enable(clk); - - if (rate) - *rate = clk_get_rate(clk); - - return 0; -} - -int __init davinci_serial_init(struct davinci_uart_config *info) -{ - int i, ret; - struct davinci_soc_info *soc_info = &davinci_soc_info; - struct device *dev = &soc_info->serial_dev->dev; - struct plat_serial8250_port *p = dev->platform_data; /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on if not needed. */ - for (i = 0; p->flags; i++, p++) { - if (!(info->enabled_uarts & (1 << i))) - continue; + for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) { + dev = &serial_dev[i].dev; + p = dev->platform_data; - ret = davinci_serial_setup_clk(i, &p->uartclk); + ret = platform_device_register(&serial_dev[i]); if (ret) continue; + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + pr_err("%s:%d: failed to get UART%d clock\n", + __func__, __LINE__, i); + continue; + } + + clk_prepare_enable(clk); + + p->uartclk = clk_get_rate(clk); + if (!p->membase && p->mapbase) { p->membase = ioremap(p->mapbase, SZ_4K); @@ -125,6 +112,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info) if (p->membase && p->type != PORT_AR7) davinci_serial_reset(p); } - - return platform_device_register(soc_info->serial_dev); + return ret; } diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 4545667ecd3c..f4d7fbb24b3b 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -264,7 +264,7 @@ static struct clk_lookup clks[] = { CLK(NULL, "clk_chipcfg", &clk_chipcfg), CLK("tnetv107x-ts.0", NULL, &clk_tsc), CLK(NULL, "clk_rom", &clk_rom), - CLK(NULL, "uart2", &clk_uart2), + CLK("serial8250.2", NULL, &clk_uart2), CLK(NULL, "clk_pktsec", &clk_pktsec), CLK("tnetv107x-rng.0", NULL, &clk_rng), CLK("tnetv107x-pka.0", NULL, &clk_pka), @@ -274,8 +274,8 @@ static struct clk_lookup clks[] = { CLK(NULL, "clk_gpio", &clk_gpio), CLK(NULL, "clk_mdio", &clk_mdio), CLK("dm6441-mmc.0", NULL, &clk_sdio0), - CLK(NULL, "uart0", &clk_uart0), - CLK(NULL, "uart1", &clk_uart1), + CLK("serial8250.0", NULL, &clk_uart0), + CLK("serial8250.1", NULL, &clk_uart1), CLK(NULL, "timer0", &clk_timer0), CLK(NULL, "timer1", &clk_timer1), CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), @@ -757,7 +757,7 @@ static struct davinci_soc_info tnetv107x_soc_info = { .gpio_type = GPIO_TYPE_TNETV107X, .gpio_num = TNETV107X_N_GPIO, .timer_info = &timer_info, - .serial_dev = &tnetv107x_serial_device, + .serial_dev = tnetv107x_serial_device, }; void __init tnetv107x_init(void) diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index dff7b2fd4e20..0bc7cdf8cf46 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -23,6 +23,8 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" select DOVE_CLK + select ORION_IRQCHIP + select ORION_TIMER select REGULATOR select REGULATOR_FIXED_VOLTAGE select USE_OF diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 4d9d2ffc4535..cbc5c0618788 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,5 +1,5 @@ -obj-y += common.o irq.o -obj-$(CONFIG_DOVE_LEGACY) += mpp.o +obj-y += common.o +obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index f3755ac81148..49f72a848423 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,11 +10,14 @@ #include <linux/init.h> #include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_data/usb-ehci-orion.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> +#include <mach/dove.h> #include <mach/pm.h> #include <plat/common.h> #include <plat/irq.h> @@ -33,10 +36,6 @@ static void __init dove_legacy_clk_init(void) clkspec.np = np; clkspec.args_count = 1; - clkspec.args[0] = CLOCK_GATING_BIT_GBE; - orion_clkdev_add(NULL, "mv643xx_eth_port.0", - of_clk_get_from_provider(&clkspec)); - clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; orion_clkdev_add("0", "pcie", of_clk_get_from_provider(&clkspec)); @@ -46,15 +45,18 @@ static void __init dove_legacy_clk_init(void) of_clk_get_from_provider(&clkspec)); } -static void __init dove_of_clk_init(void) +static void __init dove_dt_time_init(void) { of_clk_init(NULL); - dove_legacy_clk_init(); + clocksource_of_init(); } -static struct mv643xx_eth_platform_data dove_dt_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, -}; +static void __init dove_dt_init_early(void) +{ + mvebu_mbus_init("marvell,dove-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); +} static void __init dove_dt_init(void) { @@ -65,11 +67,10 @@ static void __init dove_dt_init(void) #endif dove_setup_cpu_wins(); - /* Setup root of clk tree */ - dove_of_clk_init(); + /* Setup clocks for legacy devices */ + dove_legacy_clk_init(); /* Internal devices not ported to DT yet */ - dove_ge00_init(&dove_dt_ge00_data); dove_pcie_init(1, 1); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -82,9 +83,8 @@ static const char * const dove_dt_board_compat[] = { DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") .map_io = dove_map_io, - .init_early = dove_init_early, - .init_irq = orion_dt_init_irq, - .init_time = dove_timer_init, + .init_early = dove_dt_init_early, + .init_time = dove_dt_time_init, .init_machine = dove_dt_init, .restart = dove_restart, .dt_compat = dove_dt_board_compat, diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 00247c771313..c122bcff9f7c 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -27,6 +27,22 @@ #include <plat/time.h> #include "common.h" +/* These can go away once Dove uses the mvebu-mbus DT binding */ +#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 +#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 +#define DOVE_MBUS_PCIE0_IO_TARGET 0x4 +#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 +#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 +#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 +#define DOVE_MBUS_PCIE1_IO_TARGET 0x8 +#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 +#define DOVE_MBUS_CESA_TARGET 0x3 +#define DOVE_MBUS_CESA_ATTR 0x1 +#define DOVE_MBUS_BOOTROM_TARGET 0x1 +#define DOVE_MBUS_BOOTROM_ATTR 0xfd +#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd +#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 + /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -108,8 +124,8 @@ static void __init dove_clk_init(void) orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); orion_clkdev_add(NULL, "orion_nand", nand); orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); - orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0); - orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1); + orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); + orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); orion_clkdev_add(NULL, "mv_crypto", crypto); orion_clkdev_add(NULL, "dove-ac97", ac97); orion_clkdev_add(NULL, "dove-pdma", pdma); @@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void) { /* * The PCIe windows will no longer be statically allocated - * here once Dove is migrated to the pci-mvebu driver. + * here once Dove is migrated to the pci-mvebu driver. The + * non-PCIe windows will no longer be created here once Dove + * fully moves to DT. */ - mvebu_mbus_add_window_remap_flags("pcie0.0", + mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, + DOVE_MBUS_PCIE0_IO_ATTR, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - DOVE_PCIE0_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", + DOVE_PCIE0_IO_BUS_BASE); + mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, + DOVE_MBUS_PCIE1_IO_ATTR, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - DOVE_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - DOVE_PCIE0_MEM_PHYS_BASE, - DOVE_PCIE0_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", - DOVE_PCIE1_MEM_PHYS_BASE, - DOVE_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, - DOVE_CESA_SIZE); - mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, - DOVE_BOOTROM_SIZE); - mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, - DOVE_SCRATCHPAD_SIZE); + DOVE_PCIE1_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, + DOVE_MBUS_PCIE0_MEM_ATTR, + DOVE_PCIE0_MEM_PHYS_BASE, + DOVE_PCIE0_MEM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, + DOVE_MBUS_PCIE1_MEM_ATTR, + DOVE_PCIE1_MEM_PHYS_BASE, + DOVE_PCIE1_MEM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, + DOVE_MBUS_CESA_ATTR, + DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, + DOVE_MBUS_BOOTROM_ATTR, + DOVE_BOOTROM_PHYS_BASE, + DOVE_BOOTROM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, + DOVE_MBUS_SCRATCHPAD_ATTR, + DOVE_SCRATCHPAD_PHYS_BASE, + DOVE_SCRATCHPAD_SIZE); } void __init dove_init(void) diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S deleted file mode 100644 index 5929cbc59161..000000000000 --- a/arch/arm/mach-dove/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/bridge-regs.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =DOVE_SB_REGS_PHYS_BASE - ldr \rv, =DOVE_SB_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 60bd729a1ba5..8a433a51289c 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -47,7 +47,7 @@ static const struct dove_mpp_grp dove_mpp_grp[] = { /* Enable gpio for a range of pins. mode should be a combination of GPIO_OUTPUT_OK | GPIO_INPUT_OK */ -static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) +static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode) { int i; diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S deleted file mode 100644 index bb02c05e6812..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S +++ /dev/null @@ -1,22 +0,0 @@ -/* arch/arm/mach-ebsa110/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -**/ - - .macro addruart, rp, rv, tmp - mov \rp, #0xf0000000 - orr \rp, \rp, #0x00000be0 - mov \rp, \rv - .endm - -#define UART_SHIFT 2 -#define FLOW_CONTROL -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index fe3c1fa5462b..93e54fd4e3d5 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -194,20 +194,6 @@ config MACH_VISION_EP9307 Say 'Y' here if you want your kernel to support the Vision Engraving Systems EP9307 SoM. -choice - prompt "Select a UART for early kernel messages" - -config EP93XX_EARLY_UART1 - bool "UART1" - -config EP93XX_EARLY_UART2 - bool "UART2" - -config EP93XX_EARLY_UART3 - bool "UART3" - -endchoice - endmenu endif diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S deleted file mode 100644 index af54e43132cf..000000000000 --- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-ep93xx/include/mach/debug-macro.S - * Debugging macro include header - * - * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ -#include <mach/ep93xx-regs.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =EP93XX_APB_PHYS_BASE @ Physical base - ldr \rv, =EP93XX_APB_VIRT_BASE @ virtual base - orr \rp, \rp, #0x000c0000 - orr \rv, \rv, #0x000c0000 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index b5cc77d2380b..03c42e5400d2 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -31,18 +31,8 @@ static void __raw_writel(unsigned int value, unsigned int ptr) *((volatile unsigned int *)ptr) = value; } -#if defined(CONFIG_EP93XX_EARLY_UART1) -#define UART_BASE EP93XX_UART1_PHYS_BASE -#elif defined(CONFIG_EP93XX_EARLY_UART2) -#define UART_BASE EP93XX_UART2_PHYS_BASE -#elif defined(CONFIG_EP93XX_EARLY_UART3) -#define UART_BASE EP93XX_UART3_PHYS_BASE -#else -#define UART_BASE EP93XX_UART1_PHYS_BASE -#endif - -#define PHYS_UART_DATA (UART_BASE + 0x00) -#define PHYS_UART_FLAG (UART_BASE + 0x18) +#define PHYS_UART_DATA (CONFIG_DEBUG_UART_PHYS + 0x00) +#define PHYS_UART_FLAG (CONFIG_DEBUG_UART_PHYS + 0x18) #define UART_FLAG_TXFF 0x20 static inline void putc(int c) diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index 605956fd07a2..64f2e50e19ca 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -23,7 +23,7 @@ #include <linux/mtd/partitions.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> #include <linux/spi/mmc_spi.h> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 972490fc09d6..8646a141ae46 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -17,7 +17,6 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); void exynos_init_time(void); -extern unsigned long xxti_f, xusbxti_f; struct map_desc; void exynos_init_io(void); @@ -25,56 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char *cmd); void exynos5_restart(enum reboot_mode mode, const char *cmd); void exynos_init_late(void); -/* ToDo: remove these after migrating legacy exynos4 platforms to dt */ -void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom); -void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); - void exynos_firmware_init(void); -void exynos_set_timer_source(u8 channels); - #ifdef CONFIG_PM_GENERIC_DOMAINS int exynos_pm_late_initcall(void); #else static inline int exynos_pm_late_initcall(void) { return 0; } #endif -#ifdef CONFIG_ARCH_EXYNOS4 -void exynos4_register_clocks(void); -void exynos4_setup_clocks(void); - -#else -#define exynos4_register_clocks() -#define exynos4_setup_clocks() -#endif - -#ifdef CONFIG_ARCH_EXYNOS5 -void exynos5_register_clocks(void); -void exynos5_setup_clocks(void); - -#else -#define exynos5_register_clocks() -#define exynos5_setup_clocks() -#endif - -#ifdef CONFIG_CPU_EXYNOS4210 -void exynos4210_register_clocks(void); - -#else -#define exynos4210_register_clocks() -#endif - -#ifdef CONFIG_SOC_EXYNOS4212 -void exynos4212_register_clocks(void); - -#else -#define exynos4212_register_clocks() -#endif - -struct device_node; -void combiner_init(void __iomem *combiner_base, struct device_node *np, - unsigned int max_nr, int irq_base); - extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S index c169f0c99b2a..02247f313e94 100644 --- a/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -13,20 +13,6 @@ #include <asm/hardware/dec21285.h> -#ifndef CONFIG_DEBUG_DC21285_PORT - /* For NetWinder debugging */ - .macro addruart, rp, rv, tmp - mov \rp, #0x000003f8 - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00e00000 @ virtual - orr \rp, \rp, #0x7c000000 @ physical - .endm - -#define UART_SHIFT 0 -#define FLOW_CONTROL -#include <asm/hardware/debug-8250.S> - -#else #include <mach/hardware.h> /* For EBSA285 debugging */ .equ dc21285_high, ARMCSR_BASE & 0xff000000 @@ -54,4 +40,3 @@ .macro waituart,rd,rx .endm -#endif diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S deleted file mode 100644 index 837670763b85..000000000000 --- a/arch/arm/mach-gemini/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2001-2006 Storlink, Corp. - * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <mach/hardware.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =GEMINI_UART_BASE @ physical - ldr \rv, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual - .endm - -#define UART_SHIFT 2 -#define FLOW_CONTROL -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index cd9fcb1cd7ab..6acbdabf6222 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -12,7 +12,7 @@ config ARCH_HIGHBANK select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP select MAILBOX select PL320_MBOX diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f54656091a9d..29a8af6922a8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,6 +1,7 @@ config ARCH_MXC bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 select ARCH_REQUIRE_GPIOLIB + select ARM_CPU_SUSPEND if PM select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR if !ZBOOT_ROM select CLKDEV_LOOKUP @@ -8,6 +9,7 @@ config ARCH_MXC select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP + select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 select MULTI_IRQ_HANDLER select SPARSE_IRQ select USE_OF @@ -785,7 +787,6 @@ config SOC_IMX6Q bool "i.MX6 Quad/DualLite support" select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP - select ARM_CPU_SUSPEND if PM select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 @@ -793,7 +794,7 @@ config SOC_IMX6Q select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_IMX_ANATOP select HAVE_IMX_GPC select HAVE_IMX_MMDC diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e20f22d58fd8..5383c589ad71 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -15,7 +15,8 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ - clk-pfd.o clk-busy.o clk.o + clk-pfd.o clk-busy.o clk.o \ + clk-fixup-div.o clk-fixup-mux.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 0cfa07dd9aa4..ad3b755abb78 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -66,7 +66,7 @@ void imx_anatop_post_resume(void) imx_anatop_enable_weak2p5(false); } -void imx_anatop_usb_chrg_detect_disable(void) +static void imx_anatop_usb_chrg_detect_disable(void) { regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, BM_ANADIG_USB_CHRG_DETECT_EN_B @@ -100,4 +100,6 @@ void __init imx_anatop_init(void) pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); return; } + + imx_anatop_usb_chrg_detect_disable(); } diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c new file mode 100644 index 000000000000..21db020b1f2d --- /dev/null +++ b/arch/arm/mach-imx/clk-fixup-div.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include "clk.h" + +#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw) +#define div_mask(d) ((1 << (d->width)) - 1) + +/** + * struct clk_fixup_div - imx integer fixup divider clock + * @divider: the parent class + * @ops: pointer to clk_ops of parent class + * @fixup: a hook to fixup the write value + * + * The imx fixup divider clock is a subclass of basic clk_divider + * with an addtional fixup hook. + */ +struct clk_fixup_div { + struct clk_divider divider; + const struct clk_ops *ops; + void (*fixup)(u32 *val); +}; + +static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw) +{ + struct clk_divider *divider = to_clk_div(hw); + + return container_of(divider, struct clk_fixup_div, divider); +} + +static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); + + return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); +} + +static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); + + return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); +} + +static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); + struct clk_divider *div = to_clk_div(hw); + unsigned int divider, value; + unsigned long flags = 0; + u32 val; + + divider = parent_rate / rate; + + /* Zero based divider */ + value = divider - 1; + + if (value > div_mask(div)) + value = div_mask(div); + + spin_lock_irqsave(div->lock, flags); + + val = readl(div->reg); + val &= ~(div_mask(div) << div->shift); + val |= value << div->shift; + fixup_div->fixup(&val); + writel(val, div->reg); + + spin_unlock_irqrestore(div->lock, flags); + + return 0; +} + +static const struct clk_ops clk_fixup_div_ops = { + .recalc_rate = clk_fixup_div_recalc_rate, + .round_rate = clk_fixup_div_round_rate, + .set_rate = clk_fixup_div_set_rate, +}; + +struct clk *imx_clk_fixup_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, + void (*fixup)(u32 *val)) +{ + struct clk_fixup_div *fixup_div; + struct clk *clk; + struct clk_init_data init; + + if (!fixup) + return ERR_PTR(-EINVAL); + + fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL); + if (!fixup_div) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_fixup_div_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent ? &parent : NULL; + init.num_parents = parent ? 1 : 0; + + fixup_div->divider.reg = reg; + fixup_div->divider.shift = shift; + fixup_div->divider.width = width; + fixup_div->divider.lock = &imx_ccm_lock; + fixup_div->divider.hw.init = &init; + fixup_div->ops = &clk_divider_ops; + fixup_div->fixup = fixup; + + clk = clk_register(NULL, &fixup_div->divider.hw); + if (IS_ERR(clk)) + kfree(fixup_div); + + return clk; +} diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c new file mode 100644 index 000000000000..deb4b8093b30 --- /dev/null +++ b/arch/arm/mach-imx/clk-fixup-mux.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include "clk.h" + +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + +/** + * struct clk_fixup_mux - imx integer fixup multiplexer clock + * @mux: the parent class + * @ops: pointer to clk_ops of parent class + * @fixup: a hook to fixup the write value + * + * The imx fixup multiplexer clock is a subclass of basic clk_mux + * with an addtional fixup hook. + */ +struct clk_fixup_mux { + struct clk_mux mux; + const struct clk_ops *ops; + void (*fixup)(u32 *val); +}; + +static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + + return container_of(mux, struct clk_fixup_mux, mux); +} + +static u8 clk_fixup_mux_get_parent(struct clk_hw *hw) +{ + struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); + + return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); +} + +static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw); + struct clk_mux *mux = to_clk_mux(hw); + unsigned long flags = 0; + u32 val; + + spin_lock_irqsave(mux->lock, flags); + + val = readl(mux->reg); + val &= ~(mux->mask << mux->shift); + val |= index << mux->shift; + fixup_mux->fixup(&val); + writel(val, mux->reg); + + spin_unlock_irqrestore(mux->lock, flags); + + return 0; +} + +static const struct clk_ops clk_fixup_mux_ops = { + .get_parent = clk_fixup_mux_get_parent, + .set_parent = clk_fixup_mux_set_parent, +}; + +struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, + int num_parents, void (*fixup)(u32 *val)) +{ + struct clk_fixup_mux *fixup_mux; + struct clk *clk; + struct clk_init_data init; + + if (!fixup) + return ERR_PTR(-EINVAL); + + fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL); + if (!fixup_mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_fixup_mux_ops; + init.parent_names = parents; + init.num_parents = num_parents; + + fixup_mux->mux.reg = reg; + fixup_mux->mux.shift = shift; + fixup_mux->mux.mask = BIT(width) - 1; + fixup_mux->mux.lock = &imx_ccm_lock; + fixup_mux->mux.hw.init = &init; + fixup_mux->ops = &clk_mux_ops; + fixup_mux->fixup = fixup; + + clk = clk_register(NULL, &fixup_mux->mux.hw); + if (IS_ERR(clk)) + kfree(fixup_mux); + + return clk; +} diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 9afac26fa1cc..1a56a3319997 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -119,7 +119,7 @@ enum imx5_clks { srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - clk_max + ocram, clk_max }; static struct clk *clk[clk_max]; @@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); + clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 86567d980b07..9181a241d3a8 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -206,6 +206,17 @@ static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; +static const char *cko2_sels[] = { + "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", + "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", + "usdhc3", "dummy", "arm", "ipu1", + "ipu2", "vdo_axi", "osc", "gpu2d_core", + "gpu3d_core", "usdhc2", "ssi1", "ssi2", + "ssi3", "gpu3d_shader", "vpu_axi", "can_root", + "ldb_di0", "ldb_di1", "esai", "eim_slow", + "uart_serial", "spdif", "asrc", "hsi_tx", +}; +static const char *cko_sels[] = { "cko1", "cko2", }; enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -239,7 +250,8 @@ enum mx6q_clks { pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, + spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max }; static struct clk *clk[clk_max]; @@ -276,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) struct device_node *np; void __iomem *base; int i, irq; + int ret; clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckil] = imx_obtain_fixed_clock("ckil", 0); @@ -384,19 +397,21 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); - clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); - clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); - clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels)); + clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); + clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); + clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); + clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); /* name reg shift width busy: reg, shift parent_names num_parents */ clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); @@ -406,7 +421,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); - clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); + clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); @@ -442,10 +457,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); - clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); - clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); + clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); + clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); + clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); /* name parent_name reg shift width busy: reg, shift */ clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); @@ -486,6 +502,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); + clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); @@ -521,6 +538,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); + clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); @@ -535,6 +553,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); + clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) @@ -554,7 +573,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); - if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { + if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); } @@ -574,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clk[usbphy2_gate]); } + /* + * Let's initially set up CLKO with OSC24M, since this configuration + * is widely used by imx6q board designs to clock audio codec. + */ + ret = clk_set_parent(clk[cko2_sel], clk[osc]); + if (!ret) + ret = clk_set_parent(clk[cko], clk[cko2]); + if (ret) + pr_warn("failed to set up CLKO: %d\n", ret); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index a307ac22dffe..a5c3c5d21aee 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -138,14 +138,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); - clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); + clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); + clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); @@ -179,14 +179,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); - clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); - clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); + clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index a9fad5f8d340..f6640b6a7b31 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -48,7 +48,7 @@ struct clk_pllv3 { static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long timeout = jiffies + msecs_to_jiffies(10); + unsigned long timeout; u32 val; val = readl_relaxed(pll->base); @@ -59,12 +59,19 @@ static int clk_pllv3_prepare(struct clk_hw *hw) val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); + timeout = jiffies + msecs_to_jiffies(10); /* Wait for PLL to lock */ - while (!(readl_relaxed(pll->base) & BM_PLL_LOCK)) + do { + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + break; if (time_after(jiffies, timeout)) - return -ETIMEDOUT; + break; + } while (1); - return 0; + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + return 0; + else + return -ETIMEDOUT; } static void clk_pllv3_unprepare(struct clk_hw *hw) diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index 55bc80a00666..edc35df7bed4 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -37,3 +37,29 @@ struct clk * __init imx_obtain_fixed_clock( clk = imx_clk_fixed(name, rate); return clk; } + +/* + * This fixups the register CCM_CSCMR1 write value. + * The write/read/divider values of the aclk_podf field + * of that register have the relationship described by + * the following table: + * + * write value read value divider + * 3b'000 3b'110 7 + * 3b'001 3b'111 8 + * 3b'010 3b'100 5 + * 3b'011 3b'101 6 + * 3b'100 3b'010 3 + * 3b'101 3b'011 4 + * 3b'110 3b'000 1 + * 3b'111 3b'001 2(default) + * + * That's why we do the xor operation below. + */ +#define CSCMR1_FIXUP 0x00600000 + +void imx_cscmr1_fixup(u32 *val) +{ + *val ^= CSCMR1_FIXUP; + return; +} diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 0e4e8bb261b9..048c5ad8a80b 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -6,6 +6,8 @@ extern spinlock_t imx_ccm_lock; +extern void imx_cscmr1_fixup(u32 *val); + struct clk *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); @@ -49,6 +51,14 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char **parent_names, int num_parents); +struct clk *imx_clk_fixup_divider(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width, + void (*fixup)(u32 *val)); + +struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, + u8 shift, u8 width, const char **parents, + int num_parents, void (*fixup)(u32 *val)); + static inline struct clk *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); @@ -79,7 +89,8 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent, static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { - return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift, + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, &imx_ccm_lock); } @@ -88,7 +99,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name, int num_parents, unsigned long flags) { return clk_register_mux(NULL, name, parents, num_parents, - flags, reg, shift, width, 0, + flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, &imx_ccm_lock); } diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index cb6c838b63ed..4517fd760bfc 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -137,7 +137,6 @@ extern void imx_gpc_restore_all(void); extern void imx_anatop_init(void); extern void imx_anatop_pre_suspend(void); extern void imx_anatop_post_resume(void); -extern void imx_anatop_usb_chrg_detect_disable(void); extern u32 imx_anatop_get_digprog(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); extern void imx6q_set_chicken_bit(void); @@ -147,12 +146,10 @@ extern int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM extern void imx6q_pm_init(void); -extern void imx51_pm_init(void); -extern void imx53_pm_init(void); +extern void imx5_pm_init(void); #else static inline void imx6q_pm_init(void) {} -static inline void imx51_pm_init(void) {} -static inline void imx53_pm_init(void) {} +static inline void imx5_pm_init(void) {} #endif #ifdef CONFIG_NEON @@ -161,6 +158,12 @@ extern int mx51_neon_fixup(void); static inline int mx51_neon_fixup(void) { return 0; } #endif +#ifdef CONFIG_CACHE_L2X0 +extern void imx_init_l2cache(void); +#else +static inline void imx_init_l2cache(void) {} +#endif + extern struct smp_operations imx_smp_ops; #endif diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 29ac8ee651d2..97f9c6297fcf 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -26,7 +26,7 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> #include <linux/i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/input.h> #include <linux/gpio.h> #include <linux/delay.h> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 7be13f8e69a0..85a1b51346c8 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -31,7 +31,7 @@ #include <linux/regmap.h> #include <linux/micrel_phy.h> #include <linux/mfd/syscon.h> -#include <asm/hardware/cache-l2x0.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> @@ -103,87 +103,77 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { if (IS_BUILTIN(CONFIG_PHYLIB)) { /* min rx data delay */ - phy_write(phydev, 0x0b, 0x8105); - phy_write(phydev, 0x0c, 0x0000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); /* max rx/tx clock delay, min rx/tx control delay */ - phy_write(phydev, 0x0b, 0x8104); - phy_write(phydev, 0x0c, 0xf0f0); - phy_write(phydev, 0x0b, 0x104); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); } return 0; } -static void __init imx6q_sabrelite_cko1_setup(void) +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) { - struct clk *cko1_sel, *ahb, *cko1; - unsigned long rate; - - cko1_sel = clk_get_sys(NULL, "cko1_sel"); - ahb = clk_get_sys(NULL, "ahb"); - cko1 = clk_get_sys(NULL, "cko1"); - if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) { - pr_err("cko1 setup failed!\n"); - goto put_clk; - } - clk_set_parent(cko1_sel, ahb); - rate = clk_round_rate(cko1, 16000000); - clk_set_rate(cko1, rate); -put_clk: - if (!IS_ERR(cko1_sel)) - clk_put(cko1_sel); - if (!IS_ERR(ahb)) - clk_put(ahb); - if (!IS_ERR(cko1)) - clk_put(cko1); + phy_write(dev, 0x0d, device); + phy_write(dev, 0x0e, reg); + phy_write(dev, 0x0d, (1 << 14) | device); + phy_write(dev, 0x0e, val); } -static void __init imx6q_sabrelite_init(void) +static int ksz9031rn_phy_fixup(struct phy_device *dev) { - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); - imx6q_sabrelite_cko1_setup(); + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + mmd_write_reg(dev, 2, 4, 0); + mmd_write_reg(dev, 2, 5, 0); + mmd_write_reg(dev, 2, 8, 0x003ff); + + return 0; } -static void __init imx6q_sabresd_cko1_setup(void) +static int ar8031_phy_fixup(struct phy_device *dev) { - struct clk *cko1_sel, *pll4, *pll4_post, *cko1; - unsigned long rate; - - cko1_sel = clk_get_sys(NULL, "cko1_sel"); - pll4 = clk_get_sys(NULL, "pll4_audio"); - pll4_post = clk_get_sys(NULL, "pll4_post_div"); - cko1 = clk_get_sys(NULL, "cko1"); - if (IS_ERR(cko1_sel) || IS_ERR(pll4) - || IS_ERR(pll4_post) || IS_ERR(cko1)) { - pr_err("cko1 setup failed!\n"); - goto put_clk; - } - /* - * Setting pll4 at 768MHz (24MHz * 32) - * So its child clock can get 24MHz easily - */ - clk_set_rate(pll4, 768000000); - - clk_set_parent(cko1_sel, pll4_post); - rate = clk_round_rate(cko1, 24000000); - clk_set_rate(cko1, rate); -put_clk: - if (!IS_ERR(cko1_sel)) - clk_put(cko1_sel); - if (!IS_ERR(pll4_post)) - clk_put(pll4_post); - if (!IS_ERR(pll4)) - clk_put(pll4); - if (!IS_ERR(cko1)) - clk_put(cko1); + u16 val; + + /* To enable AR8031 output a 125MHz clk from CLK_25M */ + phy_write(dev, 0xd, 0x7); + phy_write(dev, 0xe, 0x8016); + phy_write(dev, 0xd, 0x4007); + + val = phy_read(dev, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(dev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(dev, 0x1d, 0x5); + val = phy_read(dev, 0x1e); + val |= 0x0100; + phy_write(dev, 0x1e, val); + + return 0; } -static void __init imx6q_sabresd_init(void) +#define PHY_ID_AR8031 0x004dd074 + +static void __init imx6q_enet_phy_init(void) { - imx6q_sabresd_cko1_setup(); + if (IS_BUILTIN(CONFIG_PHYLIB)) { + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, + ksz9031rn_phy_fixup); + phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, + ar8031_phy_fixup); + } } static void __init imx6q_1588_init(void) @@ -192,29 +182,22 @@ static void __init imx6q_1588_init(void) gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) - regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6Q_GPR1_ENET_CLK_SEL_MASK, + IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); } -static void __init imx6q_usb_init(void) -{ - imx_anatop_usb_chrg_detect_disable(); -} static void __init imx6q_init_machine(void) { - if (of_machine_is_compatible("fsl,imx6q-sabrelite")) - imx6q_sabrelite_init(); - else if (of_machine_is_compatible("fsl,imx6q-sabresd") || - of_machine_is_compatible("fsl,imx6dl-sabresd")) - imx6q_sabresd_init(); + imx6q_enet_phy_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx_anatop_init(); imx6q_pm_init(); - imx6q_usb_init(); imx6q_1588_init(); } @@ -254,13 +237,12 @@ static void __init imx6q_opp_init(struct device *cpu_dev) { struct device_node *np; - np = of_find_node_by_path("/cpus/cpu@0"); + np = of_node_get(cpu_dev->of_node); if (!np) { pr_warn("failed to find cpu0 node\n"); return; } - cpu_dev->of_node = np; if (of_init_opp_table(cpu_dev)) { pr_warn("failed to init OPP table\n"); goto put_node; @@ -297,44 +279,10 @@ static void __init imx6q_map_io(void) imx_scu_map_io(); } -#ifdef CONFIG_CACHE_L2X0 -static void __init imx6q_init_l2cache(void) -{ - void __iomem *l2x0_base; - struct device_node *np; - unsigned int val; - - np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); - if (!np) - goto out; - - l2x0_base = of_iomap(np, 0); - if (!l2x0_base) { - of_node_put(np); - goto out; - } - - /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); - val |= 0x70800000; - writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); - val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; - writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); - - iounmap(l2x0_base); - of_node_put(np); - -out: - l2x0_of_init(0, ~0UL); -} -#else -static inline void imx6q_init_l2cache(void) {} -#endif - static void __init imx6q_init_irq(void) { imx6q_init_revision(); - imx6q_init_l2cache(); + imx_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 132db2609507..0d75dc54f715 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -11,7 +11,6 @@ #include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -26,7 +25,7 @@ static void __init imx6sl_init_machine(void) static void __init imx6sl_init_irq(void) { - l2x0_of_init(0, ~0UL); + imx_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index a27faaba98ec..c91894003da9 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -26,7 +26,7 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <linux/gpio.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include "common.h" #include "devices-imx27.h" diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index cf193d87274a..a8229b7f10bf 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -153,10 +153,10 @@ void __init imx51_soc_init(void) void __init imx51_init_late(void) { mx51_neon_fixup(); - imx51_pm_init(); + imx5_pm_init(); } void __init imx53_init_late(void) { - imx53_pm_init(); + imx5_pm_init(); } diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 82e79c658eb2..58aeaf5baaf6 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -169,14 +169,9 @@ static int __init imx5_pm_common_init(void) return imx5_cpuidle_init(); } -void __init imx51_pm_init(void) +void __init imx5_pm_init(void) { int ret = imx5_pm_common_init(); if (!ret) suspend_set_ops(&mx5_suspend_ops); } - -void __init imx53_pm_init(void) -{ - imx5_pm_common_init(); -} diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 6fe81bb4d3c9..64ff37ea72b1 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -27,6 +27,7 @@ #include <asm/system_misc.h> #include <asm/proc-fns.h> #include <asm/mach-types.h> +#include <asm/hardware/cache-l2x0.h> #include "common.h" #include "hardware.h" @@ -95,3 +96,35 @@ void __init mxc_arch_reset_init_dt(void) clk_prepare(wdog_clk); } + +#ifdef CONFIG_CACHE_L2X0 +void __init imx_init_l2cache(void) +{ + void __iomem *l2x0_base; + struct device_node *np; + unsigned int val; + + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (!np) + goto out; + + l2x0_base = of_iomap(np, 0); + if (!l2x0_base) { + of_node_put(np); + goto out; + } + + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); + val |= 0x70800000; + writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); + val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; + writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); + + iounmap(l2x0_base); + of_node_put(np); + +out: + l2x0_of_init(0, ~0UL); +} +#endif diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S deleted file mode 100644 index 411b116077e4..000000000000 --- a/arch/arm/mach-integrator/include/mach/debug-macro.S +++ /dev/null @@ -1,20 +0,0 @@ -/* arch/arm/mach-integrator/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x16000000 @ physical base address - mov \rv, #0xf0000000 @ virtual base - add \rv, \rv, #0x16000000 >> 4 - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S deleted file mode 100644 index d869a6f67e5c..000000000000 --- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-iop13xx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00002300 - orr \rp, \rp, #0x00000040 - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00e80000 - orr \rp, \rp, #0xff000000 @ physical - orr \rp, \rp, #0x00d80000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S deleted file mode 100644 index 363bdf90b34d..000000000000 --- a/arch/arm/mach-iop32x/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - .macro addruart, rp, rv, tmp - mov \rp, #0xfe000000 @ physical as well as virtual - orr \rp, \rp, #0x00800000 @ location of the UART - mov \rv, \rp - .endm - -#define UART_SHIFT 0 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S deleted file mode 100644 index 361be1f6026e..000000000000 --- a/arch/arm/mach-iop33x/include/mach/debug-macro.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00ff0000 - orr \rp, \rp, #0x0000f700 - orr \rv, #0xfe000000 @ virtual - orr \rp, #0xff000000 @ physical - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S deleted file mode 100644 index ff686cbc5df4..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-ixp4xx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - .macro addruart, rp, rv, tmp -#ifdef __ARMEB__ - mov \rp, #3 @ Uart regs are at off set of 3 if - @ byte writes used - Big Endian. -#else - mov \rp, #0 -#endif - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00f00000 - orr \rp, \rp, #0xc8000000 @ physical - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 51a50e996840..366d1a3b418d 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -7,7 +7,6 @@ config ARCH_KEYSTONE select HAVE_SMP select CLKSRC_MMIO select GENERIC_CLOCKEVENTS - select HAVE_SCHED_CLOCK select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_ERRATA_798181 if SMP help diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c index 14378e3fef16..c12296157d4a 100644 --- a/arch/arm/mach-keystone/platsmp.c +++ b/arch/arm/mach-keystone/platsmp.c @@ -38,6 +38,5 @@ static int keystone_smp_boot_secondary(unsigned int cpu, } struct smp_operations keystone_smp_ops __initdata = { - .smp_init_cpus = arm_dt_init_cpu_maps, .smp_boot_secondary = keystone_smp_boot_secondary, }; diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S index 9b9e4f7b241e..d15de8179fab 100644 --- a/arch/arm/mach-keystone/smc.S +++ b/arch/arm/mach-keystone/smc.S @@ -22,8 +22,7 @@ * Return: Non zero value on failure */ ENTRY(keystone_cpu_smc) - stmfd sp!, {r4-r12, lr} + stmfd sp!, {r4-r11, lr} smc #0 - dsb - ldmfd sp!, {r4-r12, pc} + ldmfd sp!, {r4-r11, pc} ENDPROC(keystone_cpu_smc) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index b634f9650a7b..fe8319ad3158 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -2,67 +2,32 @@ if ARCH_KIRKWOOD menu "Marvell Kirkwood Implementations" +config KIRKWOOD_LEGACY + bool + config MACH_D2NET_V2 bool "LaCie d2 Network v2 NAS Board" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the LaCie d2 Network v2 NAS. -config MACH_DOCKSTAR - bool "Seagate FreeAgent DockStar" - help - Say 'Y' here if you want your kernel to support the - Seagate FreeAgent DockStar. - -config MACH_ESATA_SHEEVAPLUG - bool "Marvell eSATA SheevaPlug Reference Board" - help - Say 'Y' here if you want your kernel to support the - Marvell eSATA SheevaPlug Reference Board. - -config MACH_GURUPLUG - bool "Marvell GuruPlug Reference Board" - help - Say 'Y' here if you want your kernel to support the - Marvell GuruPlug Reference Board. - -config MACH_INETSPACE_V2 - bool "LaCie Internet Space v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie Internet Space v2 NAS. - -config MACH_MV88F6281GTW_GE - bool "Marvell 88F6281 GTW GE Board" - help - Say 'Y' here if you want your kernel to support the - Marvell 88F6281 GTW GE Board. - config MACH_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the LaCie 2Big Network v2 NAS. config MACH_NET5BIG_V2 bool "LaCie 5Big Network v2 NAS Board" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the LaCie 5Big Network v2 NAS. -config MACH_NETSPACE_MAX_V2 - bool "LaCie Network Space Max v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie Network Space Max v2 NAS. - -config MACH_NETSPACE_V2 - bool "LaCie Network Space v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie Network Space v2 NAS. - config MACH_OPENRD + select KIRKWOOD_LEGACY bool config MACH_OPENRD_BASE @@ -88,30 +53,28 @@ config MACH_OPENRD_ULTIMATE config MACH_RD88F6192_NAS bool "Marvell RD-88F6192-NAS Reference Board" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the Marvell RD-88F6192-NAS Reference Board. config MACH_RD88F6281 bool "Marvell RD-88F6281 Reference Board" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the Marvell RD-88F6281 Reference Board. -config MACH_SHEEVAPLUG - bool "Marvell SheevaPlug Reference Board" - help - Say 'Y' here if you want your kernel to support the - Marvell SheevaPlug Reference Board. - config MACH_T5325 bool "HP t5325 Thin Client" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the HP t5325 Thin Client. config MACH_TS219 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and @@ -119,6 +82,7 @@ config MACH_TS219 config MACH_TS41X bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS" + select KIRKWOOD_LEGACY help Say 'Y' here if you want your kernel to support the QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo @@ -129,6 +93,9 @@ comment "Device tree entries" config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" select KIRKWOOD_CLK + select OF_IRQ + select ORION_IRQCHIP + select ORION_TIMER select POWER_SUPPLY select POWER_RESET select POWER_RESET_GPIO @@ -139,184 +106,12 @@ config ARCH_KIRKWOOD_DT Say 'Y' here if you want your kernel to support the Marvell Kirkwood using flattened device tree. -config MACH_CLOUDBOX_DT - bool "LaCie CloudBox NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - CloudBox NAS, using Flattened Device Tree. - -config MACH_DB88F628X_BP_DT - bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)" - help - Say 'Y' here if you want your kernel to support the Marvell - DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened - Device Tree). - -config MACH_DLINK_KIRKWOOD_DT - bool "D-Link Kirkwood-based NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Kirkwood-based D-Link NASes such as DNS-320 & DNS-325, - using Flattened Device Tree. - -config MACH_DOCKSTAR_DT - bool "Seagate FreeAgent Dockstar (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT +config MACH_MV88F6281GTW_GE_DT + bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)" + depends on ARCH_KIRKWOOD_DT help Say 'Y' here if you want your kernel to support the - Seagate FreeAgent Dockstar (Flattened Device Tree). - -config MACH_DREAMPLUG_DT - bool "Marvell DreamPlug (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Marvell DreamPlug (Flattened Device Tree). - -config MACH_GOFLEXNET_DT - bool "Seagate GoFlex Net (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Seagate GoFlex Net (Flattened Device Tree). - -config MACH_GURUPLUG_DT - bool "Marvell GuruPlug Reference Board (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Marvell GuruPlug Reference Board (Flattened Device Tree). - -config MACH_IB62X0_DT - bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - RaidSonic IB-NAS6210 & IB-NAS6220 devices, using - Flattened Device Tree. - -config MACH_ICONNECT_DT - bool "Iomega Iconnect (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here to enable Iomega Iconnect support. - -config MACH_INETSPACE_V2_DT - bool "LaCie Internet Space v2 NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - Internet Space v2 NAS, using Flattened Device Tree. - -config MACH_IOMEGA_IX2_200_DT - bool "Iomega StorCenter ix2-200 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Iomega StorCenter ix2-200 (Flattened Device Tree). - -config MACH_KM_KIRKWOOD_DT - bool "Keymile Kirkwood Reference Design (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Keymile Kirkwood Reference Desgin, using Flattened Device Tree. - -config MACH_LSXL_DT - bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - select POWER_RESET_RESTART - help - Say 'Y' here if you want your kernel to support the - Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using - Flattened Device Tree. - -config MACH_MPLCEC4_DT - bool "MPL CEC4 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - MPL CEC4 (Flattened Device Tree). - -config MACH_NETSPACE_LITE_V2_DT - bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - Network Space Lite v2 NAS, using Flattened Device Tree. - -config MACH_NETSPACE_MAX_V2_DT - bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - Network Space Max v2 NAS, using Flattened Device Tree. - -config MACH_NETSPACE_MINI_V2_DT - bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - Network Space Mini v2 NAS using Flattened Device Tree. - - This board is embedded in a product named CloudBox, which - provides automatic backup on a 100GB cloud storage. This - should not confused with a more recent LaCie NAS also named - CloudBox. For this last, the disk capacity is 1TB or above. - -config MACH_NETSPACE_V2_DT - bool "LaCie Network Space v2 NAS (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the LaCie - Network Space v2 NAS, using Flattened Device Tree. - -config MACH_OPENBLOCKS_A6_DT - bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Plat'Home OpenBlocks A6 (Flattened Device Tree). - -config MACH_READYNAS_DT - bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - select ARM_APPENDED_DTB - select ARM_ATAG_DTB_COMPAT - help - Say 'Y' here if you want your kernel to support the - NETGEAR ReadyNAS Duo v2 using Fattened Device Tree. - -config MACH_SHEEVAPLUG_DT - bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Marvell (eSATA) SheevaPlug (Flattened Device Tree). - -config MACH_TOPKICK_DT - bool "USI Topkick (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - USI Topkick, using Flattened Device Tree - -config MACH_TS219_DT - bool "Device Tree for QNAP TS-11X, TS-21X NAS" - select ARCH_KIRKWOOD_DT - select ARM_APPENDED_DTB - select ARM_ATAG_DTB_COMPAT - select POWER_RESET_QNAP - help - Say 'Y' here if you want your kernel to support the QNAP - TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and - TS-219P+ Turbo NAS devices using Fattened Device Tree. - There are two different Device Tree descriptions, depending - on if the device is based on an if the board uses the MV6281 - or MV6282. If you have the wrong one, the buttons will not - work. + Marvell 88F6281 GTW GE Board (Flattened Device Tree). endmenu diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index ac4cd75dd499..d1f8e3d0793b 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,44 +1,14 @@ -obj-y += common.o irq.o pcie.o mpp.o - +obj-y += common.o pcie.o +obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o -obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o -obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o -obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o -obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o -obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o -obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o -obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o -obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o -obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o -obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o -obj-$(CONFIG_MACH_GURUPLUG_DT) += board-guruplug.o -obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o -obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o -obj-$(CONFIG_MACH_INETSPACE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o -obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o -obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o -obj-$(CONFIG_MACH_MPLCEC4_DT) += board-mplcec4.o -obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o -obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o -obj-$(CONFIG_MACH_SHEEVAPLUG_DT) += board-sheevaplug.o -obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o -obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o +obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c deleted file mode 100644 index 2f574bc8ed40..000000000000 --- a/arch/arm/mach-kirkwood/board-db88f628x-bp.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Saeed Bishara <saeed@marvell.com> - * - * Marvell DB-88F628{1,2}-BP Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/of.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data db88f628x_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -void __init db88f628x_init(void) -{ - kirkwood_ge00_init(&db88f628x_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c deleted file mode 100644 index a1aa87f09180..000000000000 --- a/arch/arm/mach-kirkwood/board-dnskw.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2012 (C), Jamie Lentin <jm@lentin.co.uk> - * - * arch/arm/mach-kirkwood/board-dnskw.c - * - * D-link DNS-320 & DNS-325 NAS Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include "common.h" - -static struct mv643xx_eth_platform_data dnskw_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/* Register any GPIO for output and set the value */ -static void __init dnskw_gpio_register(unsigned gpio, char *name, int def) -{ - if (gpio_request(gpio, name) == 0 && - gpio_direction_output(gpio, 0) == 0) { - gpio_set_value(gpio, def); - if (gpio_export(gpio, 0) != 0) - pr_err("dnskw: Failed to export GPIO %s\n", name); - } else - pr_err("dnskw: Failed to register %s\n", name); -} - -void __init dnskw_init(void) -{ - kirkwood_ge00_init(&dnskw_ge00_data); - - /* Set NAS to turn back on after a power failure */ - dnskw_gpio_register(37, "dnskw:power:recover", 1); -} diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c deleted file mode 100644 index d7196db33984..000000000000 --- a/arch/arm/mach-kirkwood/board-dockstar.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-dockstar.c - * - * Seagate FreeAgent Dockstar Board Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Copied and modified for Seagate GoFlex Net support by - * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's - * GoFlex kernel patches. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data dockstar_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init dockstar_dt_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&dockstar_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c deleted file mode 100644 index 0903242c00dc..000000000000 --- a/arch/arm/mach-kirkwood/board-dreamplug.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> - * - * arch/arm/mach-kirkwood/board-dreamplug.c - * - * Marvell DreamPlug Reference Board Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include "common.h" - -static struct mv643xx_eth_platform_data dreamplug_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv643xx_eth_platform_data dreamplug_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(1), -}; - -void __init dreamplug_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&dreamplug_ge00_data); - kirkwood_ge01_init(&dreamplug_ge01_data); -} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 6e122ed3282f..82d3ad8e87cf 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -15,6 +15,9 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/dma-mapping.h> +#include <linux/irqchip.h> #include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -49,10 +52,6 @@ static void __init kirkwood_legacy_clk_init(void) orion_clkdev_add("1", "pcie", of_clk_get_from_provider(&clkspec)); - clkspec.args[0] = CGC_BIT_SDIO; - orion_clkdev_add(NULL, "mvsdio", - of_clk_get_from_provider(&clkspec)); - /* * The ethernet interfaces forget the MAC address assigned by * u-boot if the clocks are turned off. Until proper DT support @@ -60,19 +59,24 @@ static void __init kirkwood_legacy_clk_init(void) */ clkspec.args[0] = CGC_BIT_GE0; clk = of_clk_get_from_provider(&clkspec); - orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk); clk_prepare_enable(clk); clkspec.args[0] = CGC_BIT_GE1; clk = of_clk_get_from_provider(&clkspec); - orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk); clk_prepare_enable(clk); } -static void __init kirkwood_of_clk_init(void) +static void __init kirkwood_dt_time_init(void) { of_clk_init(NULL); - kirkwood_legacy_clk_init(); + clocksource_of_init(); +} + +static void __init kirkwood_dt_init_early(void) +{ + mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } static void __init kirkwood_dt_init(void) @@ -87,14 +91,15 @@ static void __init kirkwood_dt_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); + BUG_ON(mvebu_mbus_dt_init()); kirkwood_setup_wins(); kirkwood_l2_init(); kirkwood_cpufreq_init(); - /* Setup root of clk tree */ - kirkwood_of_clk_init(); + /* Setup clocks for legacy devices */ + kirkwood_legacy_clk_init(); kirkwood_cpuidle_init(); @@ -102,105 +107,22 @@ static void __init kirkwood_dt_init(void) kexec_reinit = kirkwood_enable_pcie; #endif - if (of_machine_is_compatible("globalscale,dreamplug")) - dreamplug_init(); - - if (of_machine_is_compatible("globalscale,guruplug")) - guruplug_dt_init(); - - if (of_machine_is_compatible("globalscale,sheevaplug")) - sheevaplug_dt_init(); - - if (of_machine_is_compatible("dlink,dns-kirkwood")) - dnskw_init(); - - if (of_machine_is_compatible("iom,iconnect")) - iconnect_init(); - - if (of_machine_is_compatible("raidsonic,ib-nas62x0")) - ib62x0_init(); - - if (of_machine_is_compatible("qnap,ts219")) - qnap_dt_ts219_init(); - - if (of_machine_is_compatible("seagate,dockstar")) - dockstar_dt_init(); - - if (of_machine_is_compatible("seagate,goflexnet")) - goflexnet_init(); - - if (of_machine_is_compatible("buffalo,lsxl")) - lsxl_init(); - - if (of_machine_is_compatible("iom,ix2-200")) - iomega_ix2_200_init(); - - if (of_machine_is_compatible("keymile,km_kirkwood")) - km_kirkwood_init(); - - if (of_machine_is_compatible("lacie,cloudbox") || - of_machine_is_compatible("lacie,inetspace_v2") || - of_machine_is_compatible("lacie,netspace_lite_v2") || - of_machine_is_compatible("lacie,netspace_max_v2") || - of_machine_is_compatible("lacie,netspace_mini_v2") || - of_machine_is_compatible("lacie,netspace_v2")) - ns2_init(); - - if (of_machine_is_compatible("marvell,db-88f6281-bp") || - of_machine_is_compatible("marvell,db-88f6282-bp")) - db88f628x_init(); - - if (of_machine_is_compatible("mpl,cec4")) - mplcec4_init(); - - if (of_machine_is_compatible("netgear,readynas-duo-v2")) - netgear_readynas_init(); - - if (of_machine_is_compatible("plathome,openblocks-a6")) - openblocks_a6_init(); - - if (of_machine_is_compatible("usi,topkick")) - usi_topkick_init(); + if (of_machine_is_compatible("marvell,mv88f6281gtw-ge")) + mv88f6281gtw_ge_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const kirkwood_dt_board_compat[] = { - "globalscale,dreamplug", - "globalscale,guruplug", - "globalscale,sheevaplug", - "dlink,dns-320", - "dlink,dns-325", - "iom,iconnect", - "raidsonic,ib-nas62x0", - "qnap,ts219", - "seagate,dockstar", - "seagate,goflexnet", - "buffalo,lsxl", - "iom,ix2-200", - "keymile,km_kirkwood", - "lacie,cloudbox", - "lacie,inetspace_v2", - "lacie,netspace_lite_v2", - "lacie,netspace_max_v2", - "lacie,netspace_mini_v2", - "lacie,netspace_v2", - "marvell,db-88f6281-bp", - "marvell,db-88f6282-bp", - "mpl,cec4", - "netgear,readynas-duo-v2", - "plathome,openblocks-a6", - "usi,topkick", - "zyxel,nsa310", + "marvell,kirkwood", NULL }; DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = orion_dt_init_irq, - .init_time = kirkwood_timer_init, + .init_early = kirkwood_dt_init_early, + .init_time = kirkwood_dt_time_init, .init_machine = kirkwood_dt_init, .restart = kirkwood_restart, .dt_compat = kirkwood_dt_board_compat, diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c deleted file mode 100644 index 9db979aec82e..000000000000 --- a/arch/arm/mach-kirkwood/board-goflexnet.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> - * - * arch/arm/mach-kirkwood/board-goflexnet.c - * - * Seagate GoFlext Net Board Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Copied and modified for Seagate GoFlex Net support by - * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's - * GoFlex kernel patches. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data goflexnet_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init goflexnet_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&goflexnet_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c deleted file mode 100644 index a857163954a5..000000000000 --- a/arch/arm/mach-kirkwood/board-guruplug.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-guruplug.c - * - * Marvell Guruplug Reference Board Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include "common.h" - -static struct mv643xx_eth_platform_data guruplug_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv643xx_eth_platform_data guruplug_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(1), -}; - -void __init guruplug_dt_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&guruplug_ge00_data); - kirkwood_ge01_init(&guruplug_ge01_data); -} diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c deleted file mode 100644 index 9a857ae83984..000000000000 --- a/arch/arm/mach-kirkwood/board-ib62x0.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2012 (C), Simon Baatz <gmbnomis@gmail.com> - * - * arch/arm/mach-kirkwood/board-ib62x0.c - * - * RaidSonic ICY BOX IB-NAS6210 & IB-NAS6220 init for drivers not - * converted to flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data ib62x0_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -void __init ib62x0_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&ib62x0_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c deleted file mode 100644 index 98b5ad1bba90..000000000000 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-iconnect.c - * - * Iomega i-connect Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/of.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data iconnect_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(11), -}; - -void __init iconnect_init(void) -{ - kirkwood_ge00_init(&iconnect_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c deleted file mode 100644 index e5f70415905a..000000000000 --- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-iomega_ix2_200.c - * - * Iomega StorCenter ix2-200 - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include "common.h" - -static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(11), -}; - -void __init iomega_ix2_200_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&iomega_ix2_200_ge00_data); - kirkwood_ge01_init(&iomega_ix2_200_ge01_data); -} diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c deleted file mode 100644 index 44e4605ba0bf..000000000000 --- a/arch/arm/mach-kirkwood/board-km_kirkwood.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * arch/arm/mach-kirkwood/board-km_kirkwood.c - * - * Keymile km_kirkwood Reference Desing Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include <linux/clk.h> -#include <linux/clk-private.h> -#include "common.h" - -static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init km_kirkwood_init(void) -{ - struct clk *sata_clk; - /* - * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing - * SATA bits (14-15) of the Clock Gating Control Register. Since these - * devices are also not present in this variant, their clocks get - * disabled because unused when clk_disable_unused() gets called. - * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED - */ - sata_clk = clk_get_sys("sata_mv.0", "0"); - if (!IS_ERR(sata_clk)) - sata_clk->flags |= CLK_IGNORE_UNUSED; - sata_clk = clk_get_sys("sata_mv.0", "1"); - if (!IS_ERR(sata_clk)) - sata_clk->flags |= CLK_IGNORE_UNUSED; - - kirkwood_ge00_init(&km_kirkwood_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c deleted file mode 100644 index 348395238df6..000000000000 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2012 (C), Michael Walle <michael@walle.cc> - * - * arch/arm/mach-kirkwood/board-lsxl.c - * - * Buffalo Linkstation LS-XHL and LS-CHLv2 init for drivers not - * converted to flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data lsxl_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv643xx_eth_platform_data lsxl_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -void __init lsxl_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - - kirkwood_ge00_init(&lsxl_ge00_data); - kirkwood_ge01_init(&lsxl_ge01_data); -} diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c deleted file mode 100644 index 938712e248f1..000000000000 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2012 MPL AG, Switzerland - * Stefan Peter <s.peter@mpl.ch> - * - * arch/arm/mach-kirkwood/board-mplcec4.c - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data mplcec4_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(1), -}; - -static struct mv643xx_eth_platform_data mplcec4_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(2), -}; - -void __init mplcec4_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&mplcec4_ge00_data); - kirkwood_ge01_init(&mplcec4_ge01_data); -} - - - diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c new file mode 100644 index 000000000000..ee5eea678c11 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c @@ -0,0 +1,50 @@ +/* + * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c + * + * Marvell 88F6281 GTW GE Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/timer.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <linux/gpio.h> +#include <net/dsa.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <mach/kirkwood.h> +#include "common.h" + +static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_NONE, + .speed = SPEED_1000, + .duplex = DUPLEX_FULL, +}; + +static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { + .port_names[0] = "lan1", + .port_names[1] = "lan2", + .port_names[2] = "lan3", + .port_names[3] = "lan4", + .port_names[4] = "wan", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { + .nr_chips = 1, + .chip = &mv88f6281gtw_ge_switch_chip_data, +}; + +void __init mv88f6281gtw_ge_init(void) +{ + kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); + kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); +} diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c deleted file mode 100644 index f8f660525ace..000000000000 --- a/arch/arm/mach-kirkwood/board-ns2.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2012 (C), Simon Guinot <simon.guinot@sequanux.org> - * - * arch/arm/mach-kirkwood/board-ns2.c - * - * LaCie Network Space v2 board (and parents) initialization for drivers - * not converted to flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mv643xx_eth.h> -#include <linux/of.h> -#include "common.h" - -static struct mv643xx_eth_platform_data ns2_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -void __init ns2_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - if (of_machine_is_compatible("lacie,cloudbox") || - of_machine_is_compatible("lacie,netspace_lite_v2") || - of_machine_is_compatible("lacie,netspace_mini_v2")) - ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); - kirkwood_ge00_init(&ns2_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c deleted file mode 100644 index b11d8fdeca93..000000000000 --- a/arch/arm/mach-kirkwood/board-openblocks_a6.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * arch/arm/mach-kirkwood/board-openblocks_a6.c - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data openblocks_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init openblocks_a6_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&openblocks_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c deleted file mode 100644 index 341b82d9cadb..000000000000 --- a/arch/arm/mach-kirkwood/board-readynas.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already - * converted to DT. - * - * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mv643xx_eth.h> -#include <mach/kirkwood.h> -#include "common.h" - -static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init netgear_readynas_init(void) -{ - kirkwood_ge00_init(&netgear_readynas_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c deleted file mode 100644 index fa389373ca74..000000000000 --- a/arch/arm/mach-kirkwood/board-sheevaplug.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-sheevaplug.c - * - * Marvell Sheevaplug Reference Board Init for drivers not converted to - * flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include "common.h" - -static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init sheevaplug_dt_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&sheevaplug_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c deleted file mode 100644 index 860f44ab457d..000000000000 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * - * QNAP TS-11x/TS-21x Turbo NAS Board Setup via DT - * - * Copyright (C) 2012 Andrew Lunn <andrew@lunn.ch> - * - * Based on the board file ts219-setup.c: - * - * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> - * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mv643xx_eth.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include "common.h" - -static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -void __init qnap_dt_ts219_init(void) -{ - u32 dev, rev; - - kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6282_DEV_ID) - qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); - - kirkwood_ge00_init(&qnap_ts219_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c deleted file mode 100644 index 1cc04ec33f0b..000000000000 --- a/arch/arm/mach-kirkwood/board-usi_topkick.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> - * - * arch/arm/mach-kirkwood/board-usi_topkick.c - * - * USI Topkick Init for drivers not converted to flattened device tree yet. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include "common.h" - -static struct mv643xx_eth_platform_data topkick_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -void __init usi_topkick_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_ge00_init(&topkick_ge00_data); -} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index e9238b5567ee..176761134a66 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -37,6 +37,12 @@ #include <linux/platform_data/dma-mv_xor.h> #include "common.h" +/* These can go away once Kirkwood uses the mvebu-mbus DT binding */ +#define KIRKWOOD_MBUS_NAND_TARGET 0x01 +#define KIRKWOOD_MBUS_NAND_ATTR 0x2f +#define KIRKWOOD_MBUS_SRAM_TARGET 0x03 +#define KIRKWOOD_MBUS_SRAM_ATTR 0x01 + /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -264,7 +270,7 @@ void __init kirkwood_clk_init(void) orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); orion_clkdev_add("0", "pcie", pex0); orion_clkdev_add("1", "pcie", pex1); - orion_clkdev_add(NULL, "kirkwood-i2s", audio); + orion_clkdev_add(NULL, "mvebu-audio", audio); orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit); orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".1", runit); @@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void) void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); - - mvebu_mbus_init("marvell,kirkwood-mbus", - BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, - DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } int kirkwood_tclk; @@ -560,7 +562,7 @@ void __init kirkwood_timer_init(void) /***************************************************************************** * Audio ****************************************************************************/ -static struct resource kirkwood_i2s_resources[] = { +static struct resource kirkwood_audio_resources[] = { [0] = { .start = AUDIO_PHYS_BASE, .end = AUDIO_PHYS_BASE + SZ_16K - 1, @@ -573,29 +575,23 @@ static struct resource kirkwood_i2s_resources[] = { }, }; -static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { +static struct kirkwood_asoc_platform_data kirkwood_audio_data = { .burst = 128, }; -static struct platform_device kirkwood_i2s_device = { - .name = "kirkwood-i2s", +static struct platform_device kirkwood_audio_device = { + .name = "mvebu-audio", .id = -1, - .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), - .resource = kirkwood_i2s_resources, + .num_resources = ARRAY_SIZE(kirkwood_audio_resources), + .resource = kirkwood_audio_resources, .dev = { - .platform_data = &kirkwood_i2s_data, + .platform_data = &kirkwood_audio_data, }, }; -static struct platform_device kirkwood_pcm_device = { - .name = "kirkwood-pcm-audio", - .id = -1, -}; - void __init kirkwood_audio_init(void) { - platform_device_register(&kirkwood_i2s_device); - platform_device_register(&kirkwood_pcm_device); + platform_device_register(&kirkwood_audio_device); } /***************************************************************************** @@ -672,10 +668,14 @@ char * __init kirkwood_id(void) void __init kirkwood_setup_wins(void) { - mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, - KIRKWOOD_NAND_MEM_SIZE); - mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, - KIRKWOOD_SRAM_SIZE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET, + KIRKWOOD_MBUS_NAND_ATTR, + KIRKWOOD_NAND_MEM_PHYS_BASE, + KIRKWOOD_NAND_MEM_SIZE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET, + KIRKWOOD_MBUS_SRAM_ATTR, + KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE); } void __init kirkwood_l2_init(void) @@ -703,6 +703,10 @@ void __init kirkwood_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); + BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ)); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index fcf3ba682e24..1296de94febf 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -59,119 +59,10 @@ void kirkwood_restart(enum reboot_mode, const char *); void kirkwood_clk_init(void); /* board init functions for boards not fully converted to fdt */ -#ifdef CONFIG_MACH_DREAMPLUG_DT -void dreamplug_init(void); +#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT +void mv88f6281gtw_ge_init(void); #else -static inline void dreamplug_init(void) {}; -#endif -#ifdef CONFIG_MACH_GURUPLUG_DT -void guruplug_dt_init(void); -#else -static inline void guruplug_dt_init(void) {}; -#endif -#ifdef CONFIG_MACH_SHEEVAPLUG_DT -void sheevaplug_dt_init(void); -#else -static inline void sheevaplug_dt_init(void) {}; -#endif -#ifdef CONFIG_MACH_TS219_DT -void qnap_dt_ts219_init(void); -#else -static inline void qnap_dt_ts219_init(void) {}; -#endif - -#ifdef CONFIG_MACH_DLINK_KIRKWOOD_DT -void dnskw_init(void); -#else -static inline void dnskw_init(void) {}; -#endif - -#ifdef CONFIG_MACH_ICONNECT_DT -void iconnect_init(void); -#else -static inline void iconnect_init(void) {}; -#endif - -#ifdef CONFIG_MACH_IB62X0_DT -void ib62x0_init(void); -#else -static inline void ib62x0_init(void) {}; -#endif - -#ifdef CONFIG_MACH_DOCKSTAR_DT -void dockstar_dt_init(void); -#else -static inline void dockstar_dt_init(void) {}; -#endif - -#ifdef CONFIG_MACH_GOFLEXNET_DT -void goflexnet_init(void); -#else -static inline void goflexnet_init(void) {}; -#endif - -#ifdef CONFIG_MACH_LSXL_DT -void lsxl_init(void); -#else -static inline void lsxl_init(void) {}; -#endif - -#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT -void iomega_ix2_200_init(void); -#else -static inline void iomega_ix2_200_init(void) {}; -#endif - -#ifdef CONFIG_MACH_KM_KIRKWOOD_DT -void km_kirkwood_init(void); -#else -static inline void km_kirkwood_init(void) {}; -#endif - -#ifdef CONFIG_MACH_DB88F628X_BP_DT -void db88f628x_init(void); -#else -static inline void db88f628x_init(void) {}; -#endif - -#ifdef CONFIG_MACH_MPLCEC4_DT -void mplcec4_init(void); -#else -static inline void mplcec4_init(void) {}; -#endif - -#if defined(CONFIG_MACH_INETSPACE_V2_DT) || \ - defined(CONFIG_MACH_NETSPACE_V2_DT) || \ - defined(CONFIG_MACH_NETSPACE_MAX_V2_DT) || \ - defined(CONFIG_MACH_NETSPACE_LITE_V2_DT) || \ - defined(CONFIG_MACH_NETSPACE_MINI_V2_DT) -void ns2_init(void); -#else -static inline void ns2_init(void) {}; -#endif - -#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT -void openblocks_a6_init(void); -#else -static inline void openblocks_a6_init(void) {}; -#endif - -#ifdef CONFIG_MACH_READYNAS_DT -void netgear_readynas_init(void); -#else -static inline void netgear_readynas_init(void) {}; -#endif - -#ifdef CONFIG_MACH_TOPKICK_DT -void usi_topkick_init(void); -#else -static inline void usi_topkick_init(void) {}; -#endif - -#ifdef CONFIG_MACH_CLOUDBOX_DT -void cloudbox_init(void); -#else -static inline void cloudbox_init(void) {}; +static inline void mv88f6281gtw_ge_init(void) {}; #endif /* early init functions not converted to fdt yet */ diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c deleted file mode 100644 index 060ccf9cb63f..000000000000 --- a/arch/arm/mach-kirkwood/dockstar-setup.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * arch/arm/mach-kirkwood/dockstar-setup.c - * - * Seagate FreeAgent DockStar Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mtd/partitions.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition dockstar_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data dockstar_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct gpio_led dockstar_led_pins[] = { - { - .name = "dockstar:green:health", - .default_trigger = "default-on", - .gpio = 46, - .active_low = 1, - }, - { - .name = "dockstar:orange:misc", - .default_trigger = "none", - .gpio = 47, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data dockstar_led_data = { - .leds = dockstar_led_pins, - .num_leds = ARRAY_SIZE(dockstar_led_pins), -}; - -static struct platform_device dockstar_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &dockstar_led_data, - } -}; - -static unsigned int dockstar_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP46_GPIO, /* LED green */ - MPP47_GPIO, /* LED orange */ - 0 -}; - -static void __init dockstar_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - - /* setup gpio pin select */ - kirkwood_mpp_conf(dockstar_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25); - - if (gpio_request(29, "USB Power Enable") != 0 || - gpio_direction_output(29, 1) != 0) - pr_err("can't set up GPIO 29 (USB Power Enable)\n"); - kirkwood_ehci_init(); - - kirkwood_ge00_init(&dockstar_ge00_data); - - platform_device_register(&dockstar_leds); -} - -MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar") - .atag_offset = 0x100, - .init_machine = dockstar_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c deleted file mode 100644 index 08dd739aa709..000000000000 --- a/arch/arm/mach-kirkwood/guruplug-setup.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * arch/arm/mach-kirkwood/guruplug-setup.c - * - * Marvell GuruPlug Reference Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition guruplug_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data guruplug_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv643xx_eth_platform_data guruplug_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(1), -}; - -static struct mv_sata_platform_data guruplug_sata_data = { - .n_ports = 1, -}; - -static struct mvsdio_platform_data guruplug_mvsdio_data = { - /* unfortunately the CD signal has not been connected */ - .gpio_card_detect = -1, - .gpio_write_protect = -1, -}; - -static struct gpio_led guruplug_led_pins[] = { - { - .name = "guruplug:red:health", - .gpio = 46, - .active_low = 1, - }, - { - .name = "guruplug:green:health", - .gpio = 47, - .active_low = 1, - }, - { - .name = "guruplug:red:wmode", - .gpio = 48, - .active_low = 1, - }, - { - .name = "guruplug:green:wmode", - .gpio = 49, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data guruplug_led_data = { - .leds = guruplug_led_pins, - .num_leds = ARRAY_SIZE(guruplug_led_pins), -}; - -static struct platform_device guruplug_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &guruplug_led_data, - } -}; - -static unsigned int guruplug_mpp_config[] __initdata = { - MPP46_GPIO, /* M_RLED */ - MPP47_GPIO, /* M_GLED */ - MPP48_GPIO, /* B_RLED */ - MPP49_GPIO, /* B_GLED */ - 0 -}; - -static void __init guruplug_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(guruplug_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(guruplug_nand_parts), 25); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&guruplug_ge00_data); - kirkwood_ge01_init(&guruplug_ge01_data); - kirkwood_sata_init(&guruplug_sata_data); - kirkwood_sdio_init(&guruplug_mvsdio_data); - - platform_device_register(&guruplug_leds); -} - -MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board") - /* Maintainer: Siddarth Gore <gores@marvell.com> */ - .atag_offset = 0x100, - .init_machine = guruplug_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S deleted file mode 100644 index f785d401a607..000000000000 --- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-kirkwood/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/bridge-regs.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =KIRKWOOD_REGS_PHYS_BASE - ldr \rv, =KIRKWOOD_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c deleted file mode 100644 index ba384b992bef..000000000000 --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c - * - * Marvell 88F6281 GTW GE Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/timer.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/input.h> -#include <linux/gpio_keys.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> -#include <net/dsa.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <mach/kirkwood.h> -#include "common.h" -#include "mpp.h" - -static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { - .nr_chips = 1, - .chip = &mv88f6281gtw_ge_switch_chip_data, -}; - -static const struct flash_platform_data mv88f6281gtw_ge_spi_slave_data = { - .type = "mx25l12805d", -}; - -static struct spi_board_info __initdata mv88f6281gtw_ge_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &mv88f6281gtw_ge_spi_slave_data, - .irq = -1, - .max_speed_hz = 50000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = { - { - .code = KEY_RESTART, - .gpio = 47, - .desc = "SWR Button", - .active_low = 1, - }, { - .code = KEY_WPS_BUTTON, - .gpio = 46, - .desc = "WPS Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data mv88f6281gtw_ge_button_data = { - .buttons = mv88f6281gtw_ge_button_pins, - .nbuttons = ARRAY_SIZE(mv88f6281gtw_ge_button_pins), -}; - -static struct platform_device mv88f6281gtw_ge_buttons = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &mv88f6281gtw_ge_button_data, - }, -}; - -static struct gpio_led mv88f6281gtw_ge_led_pins[] = { - { - .name = "gtw:green:Status", - .gpio = 20, - .active_low = 0, - }, { - .name = "gtw:red:Status", - .gpio = 21, - .active_low = 0, - }, { - .name = "gtw:green:USB", - .gpio = 12, - .active_low = 0, - }, -}; - -static struct gpio_led_platform_data mv88f6281gtw_ge_led_data = { - .leds = mv88f6281gtw_ge_led_pins, - .num_leds = ARRAY_SIZE(mv88f6281gtw_ge_led_pins), -}; - -static struct platform_device mv88f6281gtw_ge_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &mv88f6281gtw_ge_led_data, - }, -}; - -static unsigned int mv88f6281gtw_ge_mpp_config[] __initdata = { - MPP12_GPO, /* Status#_USB pin */ - MPP20_GPIO, /* Status#_GLED pin */ - MPP21_GPIO, /* Status#_RLED pin */ - MPP46_GPIO, /* WPS_Switch pin */ - MPP47_GPIO, /* SW_Init pin */ - 0 -}; - -static void __init mv88f6281gtw_ge_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(mv88f6281gtw_ge_mpp_config); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); - kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); - spi_register_board_info(mv88f6281gtw_ge_spi_slave_info, - ARRAY_SIZE(mv88f6281gtw_ge_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_uart0_init(); - platform_device_register(&mv88f6281gtw_ge_leds); - platform_device_register(&mv88f6281gtw_ge_buttons); -} - -static int __init mv88f6281gtw_ge_pci_init(void) -{ - if (machine_is_mv88f6281gtw_ge()) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} -subsys_initcall(mv88f6281gtw_ge_pci_init); - -MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") - /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ - .atag_offset = 0x100, - .init_machine = mv88f6281gtw_ge_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c deleted file mode 100644 index 3b706611da8e..000000000000 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * arch/arm/mach-kirkwood/netspace_v2-setup.c - * - * LaCie Network Space v2 board setup - * - * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> - * Copyright (C) 2009 Benoît Canet <benoit.canet@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <linux/input.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/leds.h> -#include <linux/gpio-fan.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/leds-kirkwood-ns2.h> -#include "common.h" -#include "mpp.h" -#include "lacie_v2-common.h" - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data netspace_v2_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data netspace_v2_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * GPIO keys - ****************************************************************************/ - -#define NETSPACE_V2_PUSH_BUTTON 32 - -static struct gpio_keys_button netspace_v2_buttons[] = { - [0] = { - .code = KEY_POWER, - .gpio = NETSPACE_V2_PUSH_BUTTON, - .desc = "Power push button", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data netspace_v2_button_data = { - .buttons = netspace_v2_buttons, - .nbuttons = ARRAY_SIZE(netspace_v2_buttons), -}; - -static struct platform_device netspace_v2_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &netspace_v2_button_data, - }, -}; - -/***************************************************************************** - * GPIO LEDs - ****************************************************************************/ - -#define NETSPACE_V2_GPIO_RED_LED 12 - -static struct gpio_led netspace_v2_gpio_led_pins[] = { - { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, - }, -}; - -static struct gpio_led_platform_data netspace_v2_gpio_leds_data = { - .num_leds = ARRAY_SIZE(netspace_v2_gpio_led_pins), - .leds = netspace_v2_gpio_led_pins, -}; - -static struct platform_device netspace_v2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &netspace_v2_gpio_leds_data, - }, -}; - -/***************************************************************************** - * Dual-GPIO CPLD LEDs - ****************************************************************************/ - -#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 -#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 - -static struct ns2_led netspace_v2_led_pins[] = { - { - .name = "ns_v2:blue:sata", - .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD, - .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW, - }, -}; - -static struct ns2_led_platform_data netspace_v2_leds_data = { - .num_leds = ARRAY_SIZE(netspace_v2_led_pins), - .leds = netspace_v2_led_pins, -}; - -static struct platform_device netspace_v2_leds = { - .name = "leds-ns2", - .id = -1, - .dev = { - .platform_data = &netspace_v2_leds_data, - }, -}; - -/***************************************************************************** - * GPIO fan - ****************************************************************************/ - -/* Designed for fan 40x40x16: ADDA AD0412LB-D50 6000rpm@12v */ -static struct gpio_fan_speed netspace_max_v2_fan_speed[] = { - { 0, 0 }, - { 1500, 15 }, - { 1700, 14 }, - { 1800, 13 }, - { 2100, 12 }, - { 3100, 11 }, - { 3300, 10 }, - { 4300, 9 }, - { 5500, 8 }, -}; - -static unsigned netspace_max_v2_fan_ctrl[] = { 22, 7, 33, 23 }; - -static struct gpio_fan_alarm netspace_max_v2_fan_alarm = { - .gpio = 25, - .active_low = 1, -}; - -static struct gpio_fan_platform_data netspace_max_v2_fan_data = { - .num_ctrl = ARRAY_SIZE(netspace_max_v2_fan_ctrl), - .ctrl = netspace_max_v2_fan_ctrl, - .alarm = &netspace_max_v2_fan_alarm, - .num_speed = ARRAY_SIZE(netspace_max_v2_fan_speed), - .speed = netspace_max_v2_fan_speed, -}; - -static struct platform_device netspace_max_v2_gpio_fan = { - .name = "gpio-fan", - .id = -1, - .dev = { - .platform_data = &netspace_max_v2_fan_data, - }, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static unsigned int netspace_v2_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, /* Fan speed (bit 0) */ - MPP23_GPIO, /* Fan power */ - MPP24_GPIO, /* USB mode select */ - MPP25_GPIO, /* Fan rotation fail */ - MPP26_GPIO, /* USB device vbus */ - MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* Blue led (slow register) */ - MPP30_GPIO, /* Blue led (command register) */ - MPP31_GPIO, /* Board power off */ - MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ - MPP33_GPO, /* Fan speed (bit 2) */ - 0 -}; - -#define NETSPACE_V2_GPIO_POWER_OFF 31 - -static void netspace_v2_power_off(void) -{ - gpio_set_value(NETSPACE_V2_GPIO_POWER_OFF, 1); -} - -static void __init netspace_v2_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(netspace_v2_mpp_config); - - if (machine_is_netspace_max_v2()) - lacie_v2_hdd_power_init(2); - else - lacie_v2_hdd_power_init(1); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&netspace_v2_ge00_data); - kirkwood_sata_init(&netspace_v2_sata_data); - kirkwood_uart0_init(); - lacie_v2_register_flash(); - lacie_v2_register_i2c_devices(); - - platform_device_register(&netspace_v2_leds); - platform_device_register(&netspace_v2_gpio_leds); - platform_device_register(&netspace_v2_gpio_buttons); - if (machine_is_netspace_max_v2()) - platform_device_register(&netspace_max_v2_gpio_fan); - - if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && - gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0) - pm_power_off = netspace_v2_power_off; - else - pr_err("netspace_v2: failed to configure power-off GPIO\n"); -} - -#ifdef CONFIG_MACH_NETSPACE_V2 -MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") - .atag_offset = 0x100, - .init_machine = netspace_v2_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_INETSPACE_V2 -MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") - .atag_offset = 0x100, - .init_machine = netspace_v2_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_NETSPACE_MAX_V2 -MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") - .atag_offset = 0x100, - .init_machine = netspace_v2_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index 6a6eb548307d..e5cf84103583 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -158,7 +158,8 @@ static void __init openrd_init(void) kirkwood_mpp_conf(openrd_mpp_config); kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(openrd_nand_parts), 25); + kirkwood_nand_init(openrd_nand_parts, ARRAY_SIZE(openrd_nand_parts), + 25); kirkwood_ehci_init(); diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index ddcb09f5bdd3..12d86f39f380 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -20,6 +20,16 @@ #include <mach/bridge-regs.h> #include "common.h" +/* These can go away once Kirkwood uses the mvebu-mbus DT binding */ +#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8 +#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0 +#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8 +#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0 + static void kirkwood_enable_pcie_clk(const char *port) { struct clk *clk; @@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base) void __init kirkwood_pcie_init(unsigned int portmask) { - mvebu_mbus_add_window_remap_flags("pcie0.0", + mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET, + KIRKWOOD_MBUS_PCIE0_IO_ATTR, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - KIRKWOOD_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_MEM_PHYS_BASE, - KIRKWOOD_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET, + KIRKWOOD_MBUS_PCIE0_MEM_ATTR, + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE); + mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET, + KIRKWOOD_MBUS_PCIE1_IO_ATTR, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - KIRKWOOD_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_MEM_PHYS_BASE, - KIRKWOOD_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); + KIRKWOOD_PCIE1_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET, + KIRKWOOD_MBUS_PCIE1_MEM_ATTR, + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE); vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index d24223166e06..5154bd2a3ad3 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -87,7 +87,9 @@ static void __init rd88f6281_init(void) kirkwood_init(); kirkwood_mpp_conf(rd88f6281_mpp_config); - kirkwood_nand_init(ARRAY_AND_SIZE(rd88f6281_nand_parts), 25); + kirkwood_nand_init(rd88f6281_nand_parts, + ARRAY_SIZE(rd88f6281_nand_parts), + 25); kirkwood_ehci_init(); kirkwood_ge00_init(&rd88f6281_ge00_data); diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c deleted file mode 100644 index 55b68fa39f45..000000000000 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * arch/arm/mach-kirkwood/sheevaplug-setup.c - * - * Marvell SheevaPlug Reference Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mtd/partitions.h> -#include <linux/mv643xx_eth.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition sheevaplug_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv_sata_platform_data sheeva_esata_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data sheevaplug_mvsdio_data = { - /* unfortunately the CD signal has not been connected */ -}; - -static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { - .gpio_write_protect = 44, /* MPP44 used as SD write protect */ - .gpio_card_detect = 47, /* MPP47 used as SD card detect */ -}; - -static struct gpio_led sheevaplug_led_pins[] = { - { - .name = "plug:red:misc", - .default_trigger = "none", - .gpio = 46, - .active_low = 1, - }, - { - .name = "plug:green:health", - .default_trigger = "default-on", - .gpio = 49, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data sheevaplug_led_data = { - .leds = sheevaplug_led_pins, - .num_leds = ARRAY_SIZE(sheevaplug_led_pins), -}; - -static struct platform_device sheevaplug_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &sheevaplug_led_data, - } -}; - -static unsigned int sheevaplug_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP46_GPIO, /* LED Red */ - MPP49_GPIO, /* LED */ - 0 -}; - -static unsigned int sheeva_esata_mpp_config[] __initdata = { - MPP29_GPIO, /* USB Power Enable */ - MPP44_GPIO, /* SD Write Protect */ - MPP47_GPIO, /* SD Card Detect */ - MPP49_GPIO, /* LED Green */ - 0 -}; - -static void __init sheevaplug_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - - /* setup gpio pin select */ - if (machine_is_esata_sheevaplug()) - kirkwood_mpp_conf(sheeva_esata_mpp_config); - else - kirkwood_mpp_conf(sheevaplug_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25); - - if (gpio_request(29, "USB Power Enable") != 0 || - gpio_direction_output(29, 1) != 0) - pr_err("can't set up GPIO 29 (USB Power Enable)\n"); - kirkwood_ehci_init(); - - kirkwood_ge00_init(&sheevaplug_ge00_data); - - /* honor lower power consumption for plugs with out eSATA */ - if (machine_is_esata_sheevaplug()) - kirkwood_sata_init(&sheeva_esata_sata_data); - - /* enable sd wp and sd cd on plugs with esata */ - if (machine_is_esata_sheevaplug()) - kirkwood_sdio_init(&sheeva_esata_mvsdio_data); - else - kirkwood_sdio_init(&sheevaplug_mvsdio_data); - - platform_device_register(&sheevaplug_leds); -} - -#ifdef CONFIG_MACH_SHEEVAPLUG -MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") - /* Maintainer: shadi Ammouri <shadi@marvell.com> */ - .atag_offset = 0x100, - .init_machine = sheevaplug_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG -MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") - .atag_offset = 0x100, - .init_machine = sheevaplug_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c index 456d6386edf8..9f9c0441a917 100644 --- a/arch/arm/mach-ks8695/board-acs5k.c +++ b/arch/arm/mach-ks8695/board-acs5k.c @@ -20,7 +20,7 @@ #include <linux/i2c.h> #include <linux/i2c-algo-bit.h> #include <linux/i2c-gpio.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S deleted file mode 100644 index 351bd6c84909..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/mach-lpc32xx/include/mach/debug-macro.S - * - * Author: Kevin Wells <kevin.wells@nxp.com> - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Debug output is hardcoded to standard UART 5 -*/ - - .macro addruart, rp, rv, tmp - ldreq \rp, =0x40090000 - ldrne \rv, =0xF4090000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 8483906d4308..702232996c8c 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -15,7 +15,7 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/onenand.h> #include <linux/interrupt.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/gpio.h> #include <linux/gpio-pxa.h> #include <linux/mfd/88pm860x.h> diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index d257ff40e16b..d872634c2f85 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,17 +1,16 @@ -obj-y += io.o timer.o +obj-y += timer.o obj-y += clock.o obj-$(CONFIG_MSM_VIC) += irq-vic.o -obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o obj-$(CONFIG_ARCH_MSM7X00A) += irq.o obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o -obj-$(CONFIG_ARCH_MSM7X00A) += dma.o -obj-$(CONFIG_ARCH_MSM7X30) += dma.o -obj-$(CONFIG_ARCH_QSD8X50) += dma.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o +obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o +obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c index 492f5cd87b0a..c2946892f5e3 100644 --- a/arch/arm/mach-msm/board-dt-8660.c +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -15,8 +15,8 @@ #include <linux/of_platform.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> -#include <mach/board.h> #include "common.h" static void __init msm8x60_init_late(void) @@ -42,9 +42,7 @@ static const char *msm8x60_fluid_match[] __initdata = { DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), - .map_io = msm_map_msm8x60_io, .init_machine = msm8x60_dt_init, .init_late = msm8x60_init_late, - .init_time = msm_dt_timer_init, .dt_compat = msm8x60_fluid_match, MACHINE_END diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c index bb5530957c4f..d4ca52c45111 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -14,6 +14,7 @@ #include <linux/of_platform.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> #include "common.h" @@ -29,8 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = { DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), - .map_io = msm_map_msm8960_io, - .init_time = msm_dt_timer_init, .init_machine = msm_dt_init, .dt_compat = msm8960_dt_match, MACHINE_END diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 803651ad4f62..a77529887cbc 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -29,7 +29,6 @@ #include <asm/setup.h> #include <mach/irqs.h> -#include <mach/board.h> #include <mach/msm_iomap.h> #include <linux/mtd/nand.h> diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index 30c3496db593..7d9981cb400e 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -28,12 +28,12 @@ #include <asm/mach/map.h> #include <asm/setup.h> -#include <mach/board.h> #include <mach/hardware.h> #include "board-mahimahi.h" #include "devices.h" #include "proc_comm.h" +#include "common.h" static uint debug_uart; diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index db3d8c0bc8a4..f9af5a46e8b6 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -30,7 +30,6 @@ #include <asm/memory.h> #include <asm/setup.h> -#include <mach/board.h> #include <mach/msm_iomap.h> #include <mach/dma.h> diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index f14a73d86bc0..5f933bc50783 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -28,7 +28,6 @@ #include <asm/io.h> #include <asm/setup.h> -#include <mach/board.h> #include <mach/irqs.h> #include <mach/sirc.h> #include <mach/vreg.h> diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 70730111b37c..327605174d63 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -28,7 +28,6 @@ #include <asm/mach/map.h> #include <asm/mach/flash.h> #include <mach/vreg.h> -#include <mach/board.h> #include <asm/io.h> #include <asm/delay.h> @@ -41,6 +40,7 @@ #include "board-sapphire.h" #include "proc_comm.h" #include "devices.h" +#include "common.h" void msm_init_irq(void); void msm_init_gpio(void); diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 64a46eb4fc49..ccf6621bc664 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -25,7 +25,6 @@ #include <asm/mach/map.h> #include <asm/setup.h> -#include <mach/board.h> #include <mach/hardware.h> #include <mach/msm_iomap.h> diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h index 651851c3e1dd..b2379ede43bc 100644 --- a/arch/arm/mach-msm/board-trout.h +++ b/arch/arm/mach-msm/board-trout.h @@ -4,7 +4,7 @@ #ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H #define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H -#include <mach/board.h> +#include "common.h" #define MSM_SMI_BASE 0x00000000 #define MSM_SMI_SIZE 0x00800000 diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 421cf7751a80..33c7725adae2 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h @@ -14,13 +14,10 @@ extern void msm7x01_timer_init(void); extern void msm7x30_timer_init(void); -extern void msm_dt_timer_init(void); extern void qsd8x50_timer_init(void); extern void msm_map_common_io(void); extern void msm_map_msm7x30_io(void); -extern void msm_map_msm8x60_io(void); -extern void msm_map_msm8960_io(void); extern void msm_map_qsd8x50_io(void); extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, @@ -29,4 +26,19 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, extern struct smp_operations msm_smp_ops; extern void msm_cpu_die(unsigned int cpu); +struct msm_mmc_platform_data; + +extern void msm_add_devices(void); +extern void msm_init_irq(void); +extern void msm_init_gpio(void); +extern int msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags); + +#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS) +extern int smd_debugfs_init(void); +#else +static inline int smd_debugfs_init(void) { return 0; } +#endif + #endif diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c deleted file mode 100644 index 0fb7a17df398..000000000000 --- a/arch/arm/mach-msm/devices-iommu.c +++ /dev/null @@ -1,912 +0,0 @@ -/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/bootmem.h> -#include <linux/module.h> -#include <mach/irqs.h> -#include <mach/iommu.h> - -static struct resource msm_iommu_jpegd_resources[] = { - { - .start = 0x07300000, - .end = 0x07300000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, - .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vpe_resources[] = { - { - .start = 0x07400000, - .end = 0x07400000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VPE_CB_SC_SECURE_IRQ, - .end = SMMU_VPE_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_mdp0_resources[] = { - { - .start = 0x07500000, - .end = 0x07500000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_MDP0_CB_SC_SECURE_IRQ, - .end = SMMU_MDP0_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_mdp1_resources[] = { - { - .start = 0x07600000, - .end = 0x07600000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_MDP1_CB_SC_SECURE_IRQ, - .end = SMMU_MDP1_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_rot_resources[] = { - { - .start = 0x07700000, - .end = 0x07700000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_ROT_CB_SC_SECURE_IRQ, - .end = SMMU_ROT_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_ijpeg_resources[] = { - { - .start = 0x07800000, - .end = 0x07800000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, - .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vfe_resources[] = { - { - .start = 0x07900000, - .end = 0x07900000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VFE_CB_SC_SECURE_IRQ, - .end = SMMU_VFE_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vcodec_a_resources[] = { - { - .start = 0x07A00000, - .end = 0x07A00000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_vcodec_b_resources[] = { - { - .start = 0x07B00000, - .end = 0x07B00000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, - .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx3d_resources[] = { - { - .start = 0x07C00000, - .end = 0x07C00000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, - .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx2d0_resources[] = { - { - .start = 0x07D00000, - .end = 0x07D00000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource msm_iommu_gfx2d1_resources[] = { - { - .start = 0x07E00000, - .end = 0x07E00000 + SZ_1M - 1, - .name = "physbase", - .flags = IORESOURCE_MEM, - }, - { - .name = "nonsecure_irq", - .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, - { - .name = "secure_irq", - .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, - .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device msm_root_iommu_dev = { - .name = "msm_iommu", - .id = -1, -}; - -static struct msm_iommu_dev jpegd_iommu = { - .name = "jpegd", - .ncb = 2, -}; - -static struct msm_iommu_dev vpe_iommu = { - .name = "vpe", - .ncb = 2, -}; - -static struct msm_iommu_dev mdp0_iommu = { - .name = "mdp0", - .ncb = 2, -}; - -static struct msm_iommu_dev mdp1_iommu = { - .name = "mdp1", - .ncb = 2, -}; - -static struct msm_iommu_dev rot_iommu = { - .name = "rot", - .ncb = 2, -}; - -static struct msm_iommu_dev ijpeg_iommu = { - .name = "ijpeg", - .ncb = 2, -}; - -static struct msm_iommu_dev vfe_iommu = { - .name = "vfe", - .ncb = 2, -}; - -static struct msm_iommu_dev vcodec_a_iommu = { - .name = "vcodec_a", - .ncb = 2, -}; - -static struct msm_iommu_dev vcodec_b_iommu = { - .name = "vcodec_b", - .ncb = 2, -}; - -static struct msm_iommu_dev gfx3d_iommu = { - .name = "gfx3d", - .ncb = 3, -}; - -static struct msm_iommu_dev gfx2d0_iommu = { - .name = "gfx2d0", - .ncb = 2, -}; - -static struct msm_iommu_dev gfx2d1_iommu = { - .name = "gfx2d1", - .ncb = 2, -}; - -static struct platform_device msm_device_iommu_jpegd = { - .name = "msm_iommu", - .id = 0, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), - .resource = msm_iommu_jpegd_resources, -}; - -static struct platform_device msm_device_iommu_vpe = { - .name = "msm_iommu", - .id = 1, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), - .resource = msm_iommu_vpe_resources, -}; - -static struct platform_device msm_device_iommu_mdp0 = { - .name = "msm_iommu", - .id = 2, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), - .resource = msm_iommu_mdp0_resources, -}; - -static struct platform_device msm_device_iommu_mdp1 = { - .name = "msm_iommu", - .id = 3, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), - .resource = msm_iommu_mdp1_resources, -}; - -static struct platform_device msm_device_iommu_rot = { - .name = "msm_iommu", - .id = 4, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), - .resource = msm_iommu_rot_resources, -}; - -static struct platform_device msm_device_iommu_ijpeg = { - .name = "msm_iommu", - .id = 5, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), - .resource = msm_iommu_ijpeg_resources, -}; - -static struct platform_device msm_device_iommu_vfe = { - .name = "msm_iommu", - .id = 6, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), - .resource = msm_iommu_vfe_resources, -}; - -static struct platform_device msm_device_iommu_vcodec_a = { - .name = "msm_iommu", - .id = 7, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), - .resource = msm_iommu_vcodec_a_resources, -}; - -static struct platform_device msm_device_iommu_vcodec_b = { - .name = "msm_iommu", - .id = 8, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), - .resource = msm_iommu_vcodec_b_resources, -}; - -static struct platform_device msm_device_iommu_gfx3d = { - .name = "msm_iommu", - .id = 9, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), - .resource = msm_iommu_gfx3d_resources, -}; - -static struct platform_device msm_device_iommu_gfx2d0 = { - .name = "msm_iommu", - .id = 10, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), - .resource = msm_iommu_gfx2d0_resources, -}; - -struct platform_device msm_device_iommu_gfx2d1 = { - .name = "msm_iommu", - .id = 11, - .dev = { - .parent = &msm_root_iommu_dev.dev, - }, - .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), - .resource = msm_iommu_gfx2d1_resources, -}; - -static struct msm_iommu_ctx_dev jpegd_src_ctx = { - .name = "jpegd_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev jpegd_dst_ctx = { - .name = "jpegd_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev vpe_src_ctx = { - .name = "vpe_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev vpe_dst_ctx = { - .name = "vpe_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev mdp_vg1_ctx = { - .name = "mdp_vg1", - .num = 0, - .mids = {0, 2, -1} -}; - -static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { - .name = "mdp_rgb1", - .num = 1, - .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} -}; - -static struct msm_iommu_ctx_dev mdp_vg2_ctx = { - .name = "mdp_vg2", - .num = 0, - .mids = {0, 2, -1} -}; - -static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { - .name = "mdp_rgb2", - .num = 1, - .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} -}; - -static struct msm_iommu_ctx_dev rot_src_ctx = { - .name = "rot_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev rot_dst_ctx = { - .name = "rot_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev ijpeg_src_ctx = { - .name = "ijpeg_src", - .num = 0, - .mids = {0, -1} -}; - -static struct msm_iommu_ctx_dev ijpeg_dst_ctx = { - .name = "ijpeg_dst", - .num = 1, - .mids = {1, -1} -}; - -static struct msm_iommu_ctx_dev vfe_imgwr_ctx = { - .name = "vfe_imgwr", - .num = 0, - .mids = {2, 3, 4, 5, 6, 7, 8, -1} -}; - -static struct msm_iommu_ctx_dev vfe_misc_ctx = { - .name = "vfe_misc", - .num = 1, - .mids = {0, 1, 9, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = { - .name = "vcodec_a_stream", - .num = 0, - .mids = {2, 5, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = { - .name = "vcodec_a_mm1", - .num = 1, - .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { - .name = "vcodec_b_mm2", - .num = 0, - .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_user_ctx = { - .name = "gfx3d_user", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { - .name = "gfx3d_priv", - .num = 1, - .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { - .name = "gfx2d0_2d0", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { - .name = "gfx2d1_2d1", - .num = 0, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct platform_device msm_device_jpegd_src_ctx = { - .name = "msm_iommu_ctx", - .id = 0, - .dev = { - .parent = &msm_device_iommu_jpegd.dev, - }, -}; - -static struct platform_device msm_device_jpegd_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 1, - .dev = { - .parent = &msm_device_iommu_jpegd.dev, - }, -}; - -static struct platform_device msm_device_vpe_src_ctx = { - .name = "msm_iommu_ctx", - .id = 2, - .dev = { - .parent = &msm_device_iommu_vpe.dev, - }, -}; - -static struct platform_device msm_device_vpe_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 3, - .dev = { - .parent = &msm_device_iommu_vpe.dev, - }, -}; - -static struct platform_device msm_device_mdp_vg1_ctx = { - .name = "msm_iommu_ctx", - .id = 4, - .dev = { - .parent = &msm_device_iommu_mdp0.dev, - }, -}; - -static struct platform_device msm_device_mdp_rgb1_ctx = { - .name = "msm_iommu_ctx", - .id = 5, - .dev = { - .parent = &msm_device_iommu_mdp0.dev, - }, -}; - -static struct platform_device msm_device_mdp_vg2_ctx = { - .name = "msm_iommu_ctx", - .id = 6, - .dev = { - .parent = &msm_device_iommu_mdp1.dev, - }, -}; - -static struct platform_device msm_device_mdp_rgb2_ctx = { - .name = "msm_iommu_ctx", - .id = 7, - .dev = { - .parent = &msm_device_iommu_mdp1.dev, - }, -}; - -static struct platform_device msm_device_rot_src_ctx = { - .name = "msm_iommu_ctx", - .id = 8, - .dev = { - .parent = &msm_device_iommu_rot.dev, - }, -}; - -static struct platform_device msm_device_rot_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 9, - .dev = { - .parent = &msm_device_iommu_rot.dev, - }, -}; - -static struct platform_device msm_device_ijpeg_src_ctx = { - .name = "msm_iommu_ctx", - .id = 10, - .dev = { - .parent = &msm_device_iommu_ijpeg.dev, - }, -}; - -static struct platform_device msm_device_ijpeg_dst_ctx = { - .name = "msm_iommu_ctx", - .id = 11, - .dev = { - .parent = &msm_device_iommu_ijpeg.dev, - }, -}; - -static struct platform_device msm_device_vfe_imgwr_ctx = { - .name = "msm_iommu_ctx", - .id = 12, - .dev = { - .parent = &msm_device_iommu_vfe.dev, - }, -}; - -static struct platform_device msm_device_vfe_misc_ctx = { - .name = "msm_iommu_ctx", - .id = 13, - .dev = { - .parent = &msm_device_iommu_vfe.dev, - }, -}; - -static struct platform_device msm_device_vcodec_a_stream_ctx = { - .name = "msm_iommu_ctx", - .id = 14, - .dev = { - .parent = &msm_device_iommu_vcodec_a.dev, - }, -}; - -static struct platform_device msm_device_vcodec_a_mm1_ctx = { - .name = "msm_iommu_ctx", - .id = 15, - .dev = { - .parent = &msm_device_iommu_vcodec_a.dev, - }, -}; - -static struct platform_device msm_device_vcodec_b_mm2_ctx = { - .name = "msm_iommu_ctx", - .id = 16, - .dev = { - .parent = &msm_device_iommu_vcodec_b.dev, - }, -}; - -static struct platform_device msm_device_gfx3d_user_ctx = { - .name = "msm_iommu_ctx", - .id = 17, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - -static struct platform_device msm_device_gfx3d_priv_ctx = { - .name = "msm_iommu_ctx", - .id = 18, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - -static struct platform_device msm_device_gfx2d0_2d0_ctx = { - .name = "msm_iommu_ctx", - .id = 19, - .dev = { - .parent = &msm_device_iommu_gfx2d0.dev, - }, -}; - -static struct platform_device msm_device_gfx2d1_2d1_ctx = { - .name = "msm_iommu_ctx", - .id = 20, - .dev = { - .parent = &msm_device_iommu_gfx2d1.dev, - }, -}; - -static struct platform_device *msm_iommu_devs[] = { - &msm_device_iommu_jpegd, - &msm_device_iommu_vpe, - &msm_device_iommu_mdp0, - &msm_device_iommu_mdp1, - &msm_device_iommu_rot, - &msm_device_iommu_ijpeg, - &msm_device_iommu_vfe, - &msm_device_iommu_vcodec_a, - &msm_device_iommu_vcodec_b, - &msm_device_iommu_gfx3d, - &msm_device_iommu_gfx2d0, - &msm_device_iommu_gfx2d1, -}; - -static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_iommu, - &vpe_iommu, - &mdp0_iommu, - &mdp1_iommu, - &rot_iommu, - &ijpeg_iommu, - &vfe_iommu, - &vcodec_a_iommu, - &vcodec_b_iommu, - &gfx3d_iommu, - &gfx2d0_iommu, - &gfx2d1_iommu, -}; - -static struct platform_device *msm_iommu_ctx_devs[] = { - &msm_device_jpegd_src_ctx, - &msm_device_jpegd_dst_ctx, - &msm_device_vpe_src_ctx, - &msm_device_vpe_dst_ctx, - &msm_device_mdp_vg1_ctx, - &msm_device_mdp_rgb1_ctx, - &msm_device_mdp_vg2_ctx, - &msm_device_mdp_rgb2_ctx, - &msm_device_rot_src_ctx, - &msm_device_rot_dst_ctx, - &msm_device_ijpeg_src_ctx, - &msm_device_ijpeg_dst_ctx, - &msm_device_vfe_imgwr_ctx, - &msm_device_vfe_misc_ctx, - &msm_device_vcodec_a_stream_ctx, - &msm_device_vcodec_a_mm1_ctx, - &msm_device_vcodec_b_mm2_ctx, - &msm_device_gfx3d_user_ctx, - &msm_device_gfx3d_priv_ctx, - &msm_device_gfx2d0_2d0_ctx, - &msm_device_gfx2d1_2d1_ctx, -}; - -static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { - &jpegd_src_ctx, - &jpegd_dst_ctx, - &vpe_src_ctx, - &vpe_dst_ctx, - &mdp_vg1_ctx, - &mdp_rgb1_ctx, - &mdp_vg2_ctx, - &mdp_rgb2_ctx, - &rot_src_ctx, - &rot_dst_ctx, - &ijpeg_src_ctx, - &ijpeg_dst_ctx, - &vfe_imgwr_ctx, - &vfe_misc_ctx, - &vcodec_a_stream_ctx, - &vcodec_a_mm1_ctx, - &vcodec_b_mm2_ctx, - &gfx3d_user_ctx, - &gfx3d_priv_ctx, - &gfx2d0_2d0_ctx, - &gfx2d1_2d1_ctx, -}; - -static int __init msm8x60_iommu_init(void) -{ - int ret, i; - - ret = platform_device_register(&msm_root_iommu_dev); - if (ret != 0) { - pr_err("Failed to register root IOMMU device!\n"); - goto failure; - } - - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { - ret = platform_device_add_data(msm_iommu_devs[i], - msm_iommu_data[i], - sizeof(struct msm_iommu_dev)); - if (ret != 0) { - pr_err("platform_device_add_data failed, " - "i = %d\n", i); - goto failure_unwind; - } - - ret = platform_device_register(msm_iommu_devs[i]); - - if (ret != 0) { - pr_err("platform_device_register iommu failed, " - "i = %d\n", i); - goto failure_unwind; - } - } - - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { - ret = platform_device_add_data(msm_iommu_ctx_devs[i], - msm_iommu_ctx_data[i], - sizeof(*msm_iommu_ctx_devs[i])); - if (ret != 0) { - pr_err("platform_device_add_data iommu failed, " - "i = %d\n", i); - goto failure_unwind2; - } - - ret = platform_device_register(msm_iommu_ctx_devs[i]); - if (ret != 0) { - pr_err("platform_device_register ctx failed, " - "i = %d\n", i); - goto failure_unwind2; - } - } - return 0; - -failure_unwind2: - while (--i >= 0) - platform_device_unregister(msm_iommu_ctx_devs[i]); -failure_unwind: - while (--i >= 0) - platform_device_unregister(msm_iommu_devs[i]); - - platform_device_unregister(&msm_root_iommu_dev); -failure: - return ret; -} - -static void __exit msm8x60_iommu_exit(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) - platform_device_unregister(msm_iommu_ctx_devs[i]); - - for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) - platform_device_unregister(msm_iommu_devs[i]); - - platform_device_unregister(&msm_root_iommu_dev); -} - -subsys_initcall(msm8x60_iommu_init); -module_exit(msm8x60_iommu_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>"); diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index 6d50fb964863..d83404d4b328 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -456,9 +456,9 @@ static struct clk_pcom_desc msm_clocks_7x01a[] = { CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF), - CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), - CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), + CLK_PCOM("core", UART1_CLK, "msm_serial.0", OFF), + CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0), + CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF), CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF), diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index d4db75acff56..c15ea8ab20a7 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c @@ -21,10 +21,10 @@ #include <mach/irqs.h> #include <mach/msm_iomap.h> #include <mach/dma.h> -#include <mach/board.h> #include "devices.h" #include "smd_private.h" +#include "common.h" #include <asm/mach/flash.h> @@ -211,7 +211,7 @@ static struct clk_pcom_desc msm_clocks_7x30[] = { CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), + CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0), CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index f5518112284b..9e1e9ce07b1a 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c @@ -21,9 +21,9 @@ #include <mach/irqs.h> #include <mach/msm_iomap.h> #include <mach/dma.h> -#include <mach/board.h> #include "devices.h" +#include "common.h" #include <asm/mach/flash.h> @@ -358,9 +358,9 @@ static struct clk_pcom_desc msm_clocks_8x50[] = { CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF), - CLK_PCOM("uart_clk", UART2_CLK, NULL, 0), - CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), + CLK_PCOM("core", UART1_CLK, NULL, OFF), + CLK_PCOM("core", UART2_CLK, NULL, 0), + CLK_PCOM("core", UART3_CLK, "msm_serial.2", OFF), CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF), CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0), CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h deleted file mode 100644 index c34e246a3e07..000000000000 --- a/arch/arm/mach-msm/include/mach/board.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-msm/include/mach/board.h - * - * Copyright (C) 2007 Google, Inc. - * Author: Brian Swetland <swetland@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MSM_BOARD_H -#define __ASM_ARCH_MSM_BOARD_H - -#include <linux/types.h> -#include <linux/platform_data/mmc-msm_sdcc.h> - -/* common init routines for use by arch/arm/mach-msm/board-*.c */ - -void __init msm_add_devices(void); -void __init msm_init_irq(void); -void __init msm_init_gpio(void); -int __init msm_add_sdcc(unsigned int controller, - struct msm_mmc_platform_data *plat, - unsigned int stat_irq, unsigned long stat_irq_flags); - -#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS) -int smd_debugfs_init(void); -#else -static inline int smd_debugfs_init(void) { return 0; } -#endif - -#endif diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h deleted file mode 100644 index 5c7c955e6d25..000000000000 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#ifndef MSM_IOMMU_H -#define MSM_IOMMU_H - -#include <linux/interrupt.h> -#include <linux/clk.h> - -/* Sharability attributes of MSM IOMMU mappings */ -#define MSM_IOMMU_ATTR_NON_SH 0x0 -#define MSM_IOMMU_ATTR_SH 0x4 - -/* Cacheability attributes of MSM IOMMU mappings */ -#define MSM_IOMMU_ATTR_NONCACHED 0x0 -#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 -#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 -#define MSM_IOMMU_ATTR_CACHED_WT 0x3 - -/* Mask for the cache policy attribute */ -#define MSM_IOMMU_CP_MASK 0x03 - -/* Maximum number of Machine IDs that we are allowing to be mapped to the same - * context bank. The number of MIDs mapped to the same CB does not affect - * performance, but there is a practical limit on how many distinct MIDs may - * be present. These mappings are typically determined at design time and are - * not expected to change at run time. - */ -#define MAX_NUM_MIDS 32 - -/** - * struct msm_iommu_dev - a single IOMMU hardware instance - * name Human-readable name given to this IOMMU HW instance - * ncb Number of context banks present on this IOMMU HW instance - */ -struct msm_iommu_dev { - const char *name; - int ncb; -}; - -/** - * struct msm_iommu_ctx_dev - an IOMMU context bank instance - * name Human-readable name given to this context bank - * num Index of this context bank within the hardware - * mids List of Machine IDs that are to be mapped into this context - * bank, terminated by -1. The MID is a set of signals on the - * AXI bus that identifies the function associated with a specific - * memory request. (See ARM spec). - */ -struct msm_iommu_ctx_dev { - const char *name; - int num; - int mids[MAX_NUM_MIDS]; -}; - - -/** - * struct msm_iommu_drvdata - A single IOMMU hardware instance - * @base: IOMMU config port base address (VA) - * @ncb The number of contexts on this IOMMU - * @irq: Interrupt number - * @clk: The bus clock for this IOMMU hardware instance - * @pclk: The clock for the IOMMU bus interconnect - * - * A msm_iommu_drvdata holds the global driver data about a single piece - * of an IOMMU hardware instance. - */ -struct msm_iommu_drvdata { - void __iomem *base; - int irq; - int ncb; - struct clk *clk; - struct clk *pclk; -}; - -/** - * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance - * @num: Hardware context number of this context - * @pdev: Platform device associated wit this HW instance - * @attached_elm: List element for domains to track which devices are - * attached to them - * - * A msm_iommu_ctx_drvdata holds the driver data for a single context bank - * within each IOMMU hardware instance - */ -struct msm_iommu_ctx_drvdata { - int num; - struct platform_device *pdev; - struct list_head attached_elm; -}; - -/* - * Look up an IOMMU context device by its context name. NULL if none found. - * Useful for testing and drivers that do not yet fully have IOMMU stuff in - * their platform devices. - */ -struct device *msm_iommu_get_ctx(const char *ctx_name); - -/* - * Interrupt handler for the IOMMU context fault interrupt. Hooking the - * interrupt is not supported in the API yet, but this will print an error - * message and dump useful IOMMU registers. - */ -irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id); - -#endif diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h deleted file mode 100644 index fc160101dead..000000000000 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ /dev/null @@ -1,1865 +0,0 @@ -/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H -#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H - -#define CTX_SHIFT 12 - -#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg))) -#define GET_CTX_REG(reg, base, ctx) \ - (readl((base) + (reg) + ((ctx) << CTX_SHIFT))) - -#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) - -#define SET_CTX_REG(reg, base, ctx, val) \ - writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) - -/* Wrappers for numbered registers */ -#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) -#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2))) - -/* Field wrappers */ -#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT) -#define GET_CONTEXT_FIELD(b, c, r, F) \ - GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT) - -#define SET_GLOBAL_FIELD(b, r, F, v) \ - SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v)) -#define SET_CONTEXT_FIELD(b, c, r, F, v) \ - SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v)) - -#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask)) - -#define SET_FIELD(addr, mask, shift, v) \ -do { \ - int t = readl(addr); \ - writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\ -} while (0) - - -#define NUM_FL_PTE 4096 -#define NUM_SL_PTE 256 -#define NUM_TEX_CLASS 8 - -/* First-level page table bits */ -#define FL_BASE_MASK 0xFFFFFC00 -#define FL_TYPE_TABLE (1 << 0) -#define FL_TYPE_SECT (2 << 0) -#define FL_SUPERSECTION (1 << 18) -#define FL_AP_WRITE (1 << 10) -#define FL_AP_READ (1 << 11) -#define FL_SHARED (1 << 16) -#define FL_BUFFERABLE (1 << 2) -#define FL_CACHEABLE (1 << 3) -#define FL_TEX0 (1 << 12) -#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) -#define FL_NG (1 << 17) - -/* Second-level page table bits */ -#define SL_BASE_MASK_LARGE 0xFFFF0000 -#define SL_BASE_MASK_SMALL 0xFFFFF000 -#define SL_TYPE_LARGE (1 << 0) -#define SL_TYPE_SMALL (2 << 0) -#define SL_AP0 (1 << 4) -#define SL_AP1 (2 << 4) -#define SL_SHARED (1 << 10) -#define SL_BUFFERABLE (1 << 2) -#define SL_CACHEABLE (1 << 3) -#define SL_TEX0 (1 << 6) -#define SL_OFFSET(va) (((va) & 0xFF000) >> 12) -#define SL_NG (1 << 11) - -/* Memory type and cache policy attributes */ -#define MT_SO 0 -#define MT_DEV 1 -#define MT_NORMAL 2 -#define CP_NONCACHED 0 -#define CP_WB_WA 1 -#define CP_WT 2 -#define CP_WB_NWA 3 - -/* Global register setters / getters */ -#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) -#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) -#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v)) -#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v)) -#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v)) -#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v)) -#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v)) -#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v)) -#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v)) -#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v)) -#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v)) -#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v)) -#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v)) -#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v)) -#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v)) -#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v)) - -#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b)) -#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b)) -#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b)) -#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b)) -#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b)) -#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b)) -#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b)) -#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b)) -#define GET_CR(b) GET_GLOBAL_REG(CR, (b)) -#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b)) -#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b)) -#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b)) -#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b)) -#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b)) -#define GET_REV(b) GET_GLOBAL_REG(REV, (b)) -#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b)) -#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b)) - - -/* Context register setters/getters */ -#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v)) -#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v)) -#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v)) -#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v)) -#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v)) -#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v)) -#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v)) -#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v)) -#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v)) -#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v)) -#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v)) -#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v)) -#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v)) -#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v)) -#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v)) -#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v)) -#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v)) -#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v)) -#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v)) -#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v)) -#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v)) -#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v)) -#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v)) -#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v)) -#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v)) -#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v)) -#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v)) -#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v)) - -#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c)) -#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c)) -#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c)) -#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c)) -#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c)) -#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c)) -#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c)) -#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c)) -#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c)) -#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c)) -#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c)) -#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c)) -#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c)) -#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c)) -#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c)) -#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c)) -#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c)) -#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c)) -#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c)) -#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c)) -#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c)) -#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c)) -#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c)) -#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c)) -#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c)) -#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c)) -#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c)) -#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c)) - - -/* Global field setters / getters */ -/* Global Field Setters: */ -/* CBACR_N */ -#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v) -#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v) -#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v) -#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v) -#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v) - - -/* M2VCBR_N */ -#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v) -#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v) -#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v) -#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v) -#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v) -#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v) -#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v) -#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v) -#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v) -#define SET_BPMEMTYPE(b, n, v) \ - SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v) - - -/* CR */ -#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v) -#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v) -#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v) -#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v) -#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v) -#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v) -#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v) -#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v) -#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v) -#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v) - - -/* ESR */ -#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v) -#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v) -#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v) - - -/* ESYNR0 */ -#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v) -#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v) -#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v) -#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v) -#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v) - - -/* ESYNR1 */ -#define SET_ESYNR1_AMEMTYPE(b, v) \ - SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v) -#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v) -#define SET_ESYNR1_AINNERSHARED(b, v) \ - SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v) -#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v) -#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v) -#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v) -#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v) -#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v) -#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v) -#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v) -#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v) -#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v) -#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v) -#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v) -#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v) - - -/* TESTBUSCR */ -#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v) -#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v) -#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v) -#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v) -#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v) -#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v) -#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v) -#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v) -#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v) - - -/* TLBIVMID */ -#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v) - - -/* TLBRSW */ -#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v) -#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v) - - -/* TLBTR0 */ -#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v) -#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v) -#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v) -#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v) -#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v) -#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v) -#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v) -#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v) -#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v) -#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v) -#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v) - - -/* TLBTR1 */ -#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v) -#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v) - - -/* TLBTR2 */ -#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v) -#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v) -#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v) -#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v) -#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v) - - -/* Global Field Getters */ -/* CBACR_N */ -#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID) -#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE) -#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE) -#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID) -#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX) - - -/* M2VCBR_N */ -#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID) -#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX) -#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD) -#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH) -#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH) -#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH) -#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG) -#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG) -#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG) -#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE) - - -/* CR */ -#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE) -#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE) -#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE) -#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE) -#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD) -#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD) -#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE) -#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG) -#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG) -#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME) - - -/* ESR */ -#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG) -#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS) -#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI) - - -/* ESYNR0 */ -#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID) -#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID) -#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID) -#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID) -#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID) - - -/* ESYNR1 */ -#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE) -#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED) -#define GET_ESYNR1_AINNERSHARED(b) \ - GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED) -#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV) -#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS) -#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST) -#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE) -#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST) -#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN) -#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE) -#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK) -#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO) -#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL) -#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC) -#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD) - - -/* IDR */ -#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT) -#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW) -#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM) -#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE) -#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB) -#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT) - - -/* REV */ -#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR) -#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR) - - -/* TESTBUSCR */ -#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE) -#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE) -#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL) -#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL) -#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL) -#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL) -#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL) -#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL) -#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL) - - -/* TLBIVMID */ -#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID) - - -/* TLBTR0 */ -#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR) -#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW) -#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR) -#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW) -#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN) -#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC) -#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH) -#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH) -#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT) -#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR) -#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC) - - -/* TLBTR1 */ -#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID) -#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA) - - -/* TLBTR2 */ -#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID) -#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V) -#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID) -#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV) -#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA) - - -/* Context Register setters / getters */ -/* Context Register setters */ -/* ACTLR */ -#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v) -#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v) -#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v) -#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v) -#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v) -#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v) -#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v) -#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v) -#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v) -#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v) -#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v) -#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v) -#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v) -#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v) -#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v) -#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v) - - -/* BFBCR */ -#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v) -#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v) -#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v) -#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v) -#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v) - - -/* CONTEXTIDR */ -#define SET_CONTEXTIDR_ASID(b, c, v) \ - SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v) -#define SET_CONTEXTIDR_PROCID(b, c, v) \ - SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v) - - -/* FSR */ -#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v) -#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v) -#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v) -#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v) -#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v) -#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v) -#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v) -#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v) -#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v) -#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v) - - -/* FSYNR0 */ -#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v) -#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v) -#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v) -#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v) - - -/* FSYNR1 */ -#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v) -#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v) -#define SET_AINNERSHARED(b, c, v) \ - SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v) -#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v) -#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v) -#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v) -#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v) -#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v) -#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v) -#define SET_FSYNR1_ASIZE(b, c, v) \ - SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v) -#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v) -#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v) - - -/* NMRR */ -#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v) -#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v) -#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v) -#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v) -#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v) -#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v) -#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v) -#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v) -#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v) -#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v) -#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v) -#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v) -#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v) -#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v) -#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v) -#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v) - - -/* PAR */ -#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v) - -#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v) -#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v) -#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v) -#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v) -#define SET_FAULT_HTWDEEF(b, c, v) \ - SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v) -#define SET_FAULT_HTWSEEF(b, c, v) \ - SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v) -#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v) -#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v) -#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v) - -#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v) -#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v) -#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v) -#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v) -#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v) -#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v) - - -/* PRRR */ -#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v) -#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v) -#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v) -#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v) -#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v) -#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v) -#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v) -#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v) -#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v) -#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v) -#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v) -#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v) -#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v) -#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v) -#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v) -#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v) -#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v) -#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v) -#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v) -#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v) - - -/* RESUME */ -#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v) - - -/* SCTLR */ -#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v) -#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v) -#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v) -#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v) -#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v) -#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v) - - -/* TLBLKCR */ -#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v) -#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \ - SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v) -#define SET_TLBIASIDCFG(b, c, v) \ - SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v) -#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v) -#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v) -#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v) - - -/* TTBCR */ -#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v) -#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v) -#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v) - - -/* TTBR0 */ -#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v) -#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v) -#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v) -#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v) -#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v) -#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v) - - -/* TTBR1 */ -#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v) -#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v) -#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v) -#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v) -#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v) -#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v) - - -/* V2PSR */ -#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v) -#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) - - -/* Context Register getters */ -/* ACTLR */ -#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) -#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE) -#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG) -#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH) -#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH) -#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH) -#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG) -#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA) -#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA) -#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG) -#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG) -#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF) -#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG) -#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME) -#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG) -#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE) - -/* BFBCR */ -#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE) -#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE) -#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS) -#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC) -#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC) - - -/* CONTEXTIDR */ -#define GET_CONTEXTIDR_ASID(b, c) \ - GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID) -#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID) - - -/* FSR */ -#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF) -#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF) -#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF) -#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF) -#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF) -#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF) -#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF) -#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL) -#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS) -#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI) - - -/* FSYNR0 */ -#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID) -#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID) -#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID) -#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID) - - -/* FSYNR1 */ -#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE) -#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED) -#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED) -#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV) -#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS) -#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST) -#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE) -#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST) -#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN) -#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE) -#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK) -#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL) - - -/* NMRR */ -#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0) -#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1) -#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2) -#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3) -#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4) -#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5) -#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6) -#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7) -#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0) -#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1) -#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2) -#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3) -#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4) -#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) -#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) -#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) -#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) -#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ - ((n) * 2 + 16)) - -/* PAR */ -#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) - -#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF) -#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF) -#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF) -#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF) -#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF) -#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF) -#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF) -#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL) -#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS) - -#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS) -#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT) -#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH) -#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS) -#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS) -#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA) - - -/* PRRR */ -#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0) -#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1) -#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2) -#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3) -#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4) -#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5) -#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6) -#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7) -#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0) -#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1) -#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0) -#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1) -#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0) -#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1) -#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2) -#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3) -#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4) -#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) -#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) -#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) -#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) -#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) - - -/* RESUME */ -#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR) - - -/* SCTLR */ -#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M) -#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE) -#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE) -#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF) -#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE) -#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD) - - -/* TLBLKCR */ -#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE) -#define GET_TLBLCKR_TLBIALLCFG(b, c) \ - GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG) -#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG) -#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG) -#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR) -#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM) - - -/* TTBCR */ -#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N) -#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0) -#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1) - - -/* TTBR0 */ -#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH) -#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH) -#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN) -#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS) -#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL) -#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA) - - -/* TTBR1 */ -#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH) -#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH) -#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN) -#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS) -#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL) -#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA) - - -/* V2PSR */ -#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT) -#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) - - -/* Global Registers */ -#define M2VCBR_N (0xFF000) -#define CBACR_N (0xFF800) -#define TLBRSW (0xFFE00) -#define TLBTR0 (0xFFE80) -#define TLBTR1 (0xFFE84) -#define TLBTR2 (0xFFE88) -#define TESTBUSCR (0xFFE8C) -#define GLOBAL_TLBIALL (0xFFF00) -#define TLBIVMID (0xFFF04) -#define CR (0xFFF80) -#define EAR (0xFFF84) -#define ESR (0xFFF88) -#define ESRRESTORE (0xFFF8C) -#define ESYNR0 (0xFFF90) -#define ESYNR1 (0xFFF94) -#define REV (0xFFFF4) -#define IDR (0xFFFF8) -#define RPU_ACR (0xFFFFC) - - -/* Context Bank Registers */ -#define SCTLR (0x000) -#define ACTLR (0x004) -#define CONTEXTIDR (0x008) -#define TTBR0 (0x010) -#define TTBR1 (0x014) -#define TTBCR (0x018) -#define PAR (0x01C) -#define FSR (0x020) -#define FSRRESTORE (0x024) -#define FAR (0x028) -#define FSYNR0 (0x02C) -#define FSYNR1 (0x030) -#define PRRR (0x034) -#define NMRR (0x038) -#define TLBLCKR (0x03C) -#define V2PSR (0x040) -#define TLBFLPTER (0x044) -#define TLBSLPTER (0x048) -#define BFBCR (0x04C) -#define CTX_TLBIALL (0x800) -#define TLBIASID (0x804) -#define TLBIVA (0x808) -#define TLBIVAA (0x80C) -#define V2PPR (0x810) -#define V2PPW (0x814) -#define V2PUR (0x818) -#define V2PUW (0x81C) -#define RESUME (0x820) - - -/* Global Register Fields */ -/* CBACRn */ -#define RWVMID (RWVMID_MASK << RWVMID_SHIFT) -#define RWE (RWE_MASK << RWE_SHIFT) -#define RWGE (RWGE_MASK << RWGE_SHIFT) -#define CBVMID (CBVMID_MASK << CBVMID_SHIFT) -#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT) - - -/* CR */ -#define RPUE (RPUE_MASK << RPUE_SHIFT) -#define RPUERE (RPUERE_MASK << RPUERE_SHIFT) -#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT) -#define DCDEE (DCDEE_MASK << DCDEE_SHIFT) -#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT) -#define STALLD (STALLD_MASK << STALLD_SHIFT) -#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT) -#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT) -#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT) -#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT) - - -/* ESR */ -#define CFG (CFG_MASK << CFG_SHIFT) -#define BYPASS (BYPASS_MASK << BYPASS_SHIFT) -#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT) - - -/* ESYNR0 */ -#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT) -#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT) -#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT) -#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT) -#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT) - - -/* ESYNR1 */ -#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT) -#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT) -#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \ - ESYNR1_AINNERSHARED_SHIFT) -#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT) -#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT) -#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT) -#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT) -#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT) -#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT) -#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT) -#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT) -#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT) -#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT) -#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT) -#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT) - - -/* IDR */ -#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT) -#define HTW (HTW_MASK << HTW_SHIFT) -#define HUM (HUM_MASK << HUM_SHIFT) -#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT) -#define NCB (NCB_MASK << NCB_SHIFT) -#define NIRPT (NIRPT_MASK << NIRPT_SHIFT) - - -/* M2VCBRn */ -#define VMID (VMID_MASK << VMID_SHIFT) -#define CBNDX (CBNDX_MASK << CBNDX_SHIFT) -#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT) -#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT) -#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT) -#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT) -#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT) -#define NSCFG (NSCFG_MASK << NSCFG_SHIFT) -#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT) -#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT) - - -/* REV */ -#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT) -#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT) - - -/* TESTBUSCR */ -#define TBE (TBE_MASK << TBE_SHIFT) -#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT) -#define WGSEL (WGSEL_MASK << WGSEL_SHIFT) -#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT) -#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT) -#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT) -#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT) -#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT) -#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT) - - -/* TLBIVMID */ -#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT) - - -/* TLBRSW */ -#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT) -#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT) - - -/* TLBTR0 */ -#define PR (PR_MASK << PR_SHIFT) -#define PW (PW_MASK << PW_SHIFT) -#define UR (UR_MASK << UR_SHIFT) -#define UW (UW_MASK << UW_SHIFT) -#define XN (XN_MASK << XN_SHIFT) -#define NSDESC (NSDESC_MASK << NSDESC_SHIFT) -#define ISH (ISH_MASK << ISH_SHIFT) -#define SH (SH_MASK << SH_SHIFT) -#define MT (MT_MASK << MT_SHIFT) -#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT) -#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT) - - -/* TLBTR1 */ -#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT) -#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT) - - -/* TLBTR2 */ -#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT) -#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT) -#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT) -#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT) -#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT) - - -/* Context Register Fields */ -/* ACTLR */ -#define CFERE (CFERE_MASK << CFERE_SHIFT) -#define CFEIE (CFEIE_MASK << CFEIE_SHIFT) -#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT) -#define RCOSH (RCOSH_MASK << RCOSH_SHIFT) -#define RCISH (RCISH_MASK << RCISH_SHIFT) -#define RCNSH (RCNSH_MASK << RCNSH_SHIFT) -#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT) -#define DNA (DNA_MASK << DNA_SHIFT) -#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT) -#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT) -#define CFCFG (CFCFG_MASK << CFCFG_SHIFT) -#define TIPCF (TIPCF_MASK << TIPCF_SHIFT) -#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT) -#define HUME (HUME_MASK << HUME_SHIFT) -#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT) -#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT) - - -/* BFBCR */ -#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT) -#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT) -#define SFVS (SFVS_MASK << SFVS_SHIFT) -#define FLVIC (FLVIC_MASK << FLVIC_SHIFT) -#define SLVIC (SLVIC_MASK << SLVIC_SHIFT) - - -/* CONTEXTIDR */ -#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT) -#define PROCID (PROCID_MASK << PROCID_SHIFT) - - -/* FSR */ -#define TF (TF_MASK << TF_SHIFT) -#define AFF (AFF_MASK << AFF_SHIFT) -#define APF (APF_MASK << APF_SHIFT) -#define TLBMF (TLBMF_MASK << TLBMF_SHIFT) -#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT) -#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT) -#define MHF (MHF_MASK << MHF_SHIFT) -#define SL (SL_MASK << SL_SHIFT) -#define SS (SS_MASK << SS_SHIFT) -#define MULTI (MULTI_MASK << MULTI_SHIFT) - - -/* FSYNR0 */ -#define AMID (AMID_MASK << AMID_SHIFT) -#define APID (APID_MASK << APID_SHIFT) -#define ABID (ABID_MASK << ABID_SHIFT) -#define ATID (ATID_MASK << ATID_SHIFT) - - -/* FSYNR1 */ -#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT) -#define ASHARED (ASHARED_MASK << ASHARED_SHIFT) -#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT) -#define APRIV (APRIV_MASK << APRIV_SHIFT) -#define APROTNS (APROTNS_MASK << APROTNS_SHIFT) -#define AINST (AINST_MASK << AINST_SHIFT) -#define AWRITE (AWRITE_MASK << AWRITE_SHIFT) -#define ABURST (ABURST_MASK << ABURST_SHIFT) -#define ALEN (ALEN_MASK << ALEN_SHIFT) -#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT) -#define ALOCK (ALOCK_MASK << ALOCK_SHIFT) -#define AFULL (AFULL_MASK << AFULL_SHIFT) - - -/* NMRR */ -#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT) -#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT) -#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT) -#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT) -#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT) -#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT) -#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT) -#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT) -#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT) -#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT) -#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT) -#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT) -#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT) -#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT) -#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT) -#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT) - - -/* PAR */ -#define FAULT (FAULT_MASK << FAULT_SHIFT) -/* If a fault is present, these are the -same as the fault fields in the FAR */ -#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT) -#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT) -#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT) -#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT) -#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT) -#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT) -#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT) -#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT) -#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT) - -/* If NO fault is present, the following fields are in effect */ -/* (FAULT remains as before) */ -#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT) -#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT) -#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT) -#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT) -#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT) -#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT) - - -/* PRRR */ -#define MTC0 (MTC0_MASK << MTC0_SHIFT) -#define MTC1 (MTC1_MASK << MTC1_SHIFT) -#define MTC2 (MTC2_MASK << MTC2_SHIFT) -#define MTC3 (MTC3_MASK << MTC3_SHIFT) -#define MTC4 (MTC4_MASK << MTC4_SHIFT) -#define MTC5 (MTC5_MASK << MTC5_SHIFT) -#define MTC6 (MTC6_MASK << MTC6_SHIFT) -#define MTC7 (MTC7_MASK << MTC7_SHIFT) -#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT) -#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT) -#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT) -#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT) -#define NOS0 (NOS0_MASK << NOS0_SHIFT) -#define NOS1 (NOS1_MASK << NOS1_SHIFT) -#define NOS2 (NOS2_MASK << NOS2_SHIFT) -#define NOS3 (NOS3_MASK << NOS3_SHIFT) -#define NOS4 (NOS4_MASK << NOS4_SHIFT) -#define NOS5 (NOS5_MASK << NOS5_SHIFT) -#define NOS6 (NOS6_MASK << NOS6_SHIFT) -#define NOS7 (NOS7_MASK << NOS7_SHIFT) - - -/* RESUME */ -#define TNR (TNR_MASK << TNR_SHIFT) - - -/* SCTLR */ -#define M (M_MASK << M_SHIFT) -#define TRE (TRE_MASK << TRE_SHIFT) -#define AFE (AFE_MASK << AFE_SHIFT) -#define HAF (HAF_MASK << HAF_SHIFT) -#define BE (BE_MASK << BE_SHIFT) -#define AFFD (AFFD_MASK << AFFD_SHIFT) - - -/* TLBIASID */ -#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT) - - -/* TLBIVA */ -#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT) -#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT) - - -/* TLBIVAA */ -#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT) - - -/* TLBLCKR */ -#define LKE (LKE_MASK << LKE_SHIFT) -#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT) -#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT) -#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT) -#define FLOOR (FLOOR_MASK << FLOOR_SHIFT) -#define VICTIM (VICTIM_MASK << VICTIM_SHIFT) - - -/* TTBCR */ -#define N (N_MASK << N_SHIFT) -#define PD0 (PD0_MASK << PD0_SHIFT) -#define PD1 (PD1_MASK << PD1_SHIFT) - - -/* TTBR0 */ -#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT) -#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT) -#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT) -#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT) -#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT) -#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT) - - -/* TTBR1 */ -#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT) -#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT) -#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT) -#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT) -#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT) -#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT) - - -/* V2PSR */ -#define HIT (HIT_MASK << HIT_SHIFT) -#define INDEX (INDEX_MASK << INDEX_SHIFT) - - -/* V2Pxx */ -#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT) -#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT) - - -/* Global Register Masks */ -/* CBACRn */ -#define RWVMID_MASK 0x1F -#define RWE_MASK 0x01 -#define RWGE_MASK 0x01 -#define CBVMID_MASK 0x1F -#define IRPTNDX_MASK 0xFF - - -/* CR */ -#define RPUE_MASK 0x01 -#define RPUERE_MASK 0x01 -#define RPUEIE_MASK 0x01 -#define DCDEE_MASK 0x01 -#define CLIENTPD_MASK 0x01 -#define STALLD_MASK 0x01 -#define TLBLKCRWE_MASK 0x01 -#define CR_TLBIALLCFG_MASK 0x01 -#define TLBIVMIDCFG_MASK 0x01 -#define CR_HUME_MASK 0x01 - - -/* ESR */ -#define CFG_MASK 0x01 -#define BYPASS_MASK 0x01 -#define ESR_MULTI_MASK 0x01 - - -/* ESYNR0 */ -#define ESYNR0_AMID_MASK 0xFF -#define ESYNR0_APID_MASK 0x1F -#define ESYNR0_ABID_MASK 0x07 -#define ESYNR0_AVMID_MASK 0x1F -#define ESYNR0_ATID_MASK 0xFF - - -/* ESYNR1 */ -#define ESYNR1_AMEMTYPE_MASK 0x07 -#define ESYNR1_ASHARED_MASK 0x01 -#define ESYNR1_AINNERSHARED_MASK 0x01 -#define ESYNR1_APRIV_MASK 0x01 -#define ESYNR1_APROTNS_MASK 0x01 -#define ESYNR1_AINST_MASK 0x01 -#define ESYNR1_AWRITE_MASK 0x01 -#define ESYNR1_ABURST_MASK 0x01 -#define ESYNR1_ALEN_MASK 0x0F -#define ESYNR1_ASIZE_MASK 0x01 -#define ESYNR1_ALOCK_MASK 0x03 -#define ESYNR1_AOOO_MASK 0x01 -#define ESYNR1_AFULL_MASK 0x01 -#define ESYNR1_AC_MASK 0x01 -#define ESYNR1_DCD_MASK 0x01 - - -/* IDR */ -#define NM2VCBMT_MASK 0x1FF -#define HTW_MASK 0x01 -#define HUM_MASK 0x01 -#define TLBSIZE_MASK 0x0F -#define NCB_MASK 0xFF -#define NIRPT_MASK 0xFF - - -/* M2VCBRn */ -#define VMID_MASK 0x1F -#define CBNDX_MASK 0xFF -#define BYPASSD_MASK 0x01 -#define BPRCOSH_MASK 0x01 -#define BPRCISH_MASK 0x01 -#define BPRCNSH_MASK 0x01 -#define BPSHCFG_MASK 0x03 -#define NSCFG_MASK 0x03 -#define BPMTCFG_MASK 0x01 -#define BPMEMTYPE_MASK 0x07 - - -/* REV */ -#define MINOR_MASK 0x0F -#define MAJOR_MASK 0x0F - - -/* TESTBUSCR */ -#define TBE_MASK 0x01 -#define SPDMBE_MASK 0x01 -#define WGSEL_MASK 0x03 -#define TBLSEL_MASK 0x03 -#define TBHSEL_MASK 0x03 -#define SPDM0SEL_MASK 0x0F -#define SPDM1SEL_MASK 0x0F -#define SPDM2SEL_MASK 0x0F -#define SPDM3SEL_MASK 0x0F - - -/* TLBIMID */ -#define TLBIVMID_VMID_MASK 0x1F - - -/* TLBRSW */ -#define TLBRSW_INDEX_MASK 0xFF -#define TLBBFBS_MASK 0x03 - - -/* TLBTR0 */ -#define PR_MASK 0x01 -#define PW_MASK 0x01 -#define UR_MASK 0x01 -#define UW_MASK 0x01 -#define XN_MASK 0x01 -#define NSDESC_MASK 0x01 -#define ISH_MASK 0x01 -#define SH_MASK 0x01 -#define MT_MASK 0x07 -#define DPSIZR_MASK 0x07 -#define DPSIZC_MASK 0x07 - - -/* TLBTR1 */ -#define TLBTR1_VMID_MASK 0x1F -#define TLBTR1_PA_MASK 0x000FFFFF - - -/* TLBTR2 */ -#define TLBTR2_ASID_MASK 0xFF -#define TLBTR2_V_MASK 0x01 -#define TLBTR2_NSTID_MASK 0x01 -#define TLBTR2_NV_MASK 0x01 -#define TLBTR2_VA_MASK 0x000FFFFF - - -/* Global Register Shifts */ -/* CBACRn */ -#define RWVMID_SHIFT 0 -#define RWE_SHIFT 8 -#define RWGE_SHIFT 9 -#define CBVMID_SHIFT 16 -#define IRPTNDX_SHIFT 24 - - -/* CR */ -#define RPUE_SHIFT 0 -#define RPUERE_SHIFT 1 -#define RPUEIE_SHIFT 2 -#define DCDEE_SHIFT 3 -#define CLIENTPD_SHIFT 4 -#define STALLD_SHIFT 5 -#define TLBLKCRWE_SHIFT 6 -#define CR_TLBIALLCFG_SHIFT 7 -#define TLBIVMIDCFG_SHIFT 8 -#define CR_HUME_SHIFT 9 - - -/* ESR */ -#define CFG_SHIFT 0 -#define BYPASS_SHIFT 1 -#define ESR_MULTI_SHIFT 31 - - -/* ESYNR0 */ -#define ESYNR0_AMID_SHIFT 0 -#define ESYNR0_APID_SHIFT 8 -#define ESYNR0_ABID_SHIFT 13 -#define ESYNR0_AVMID_SHIFT 16 -#define ESYNR0_ATID_SHIFT 24 - - -/* ESYNR1 */ -#define ESYNR1_AMEMTYPE_SHIFT 0 -#define ESYNR1_ASHARED_SHIFT 3 -#define ESYNR1_AINNERSHARED_SHIFT 4 -#define ESYNR1_APRIV_SHIFT 5 -#define ESYNR1_APROTNS_SHIFT 6 -#define ESYNR1_AINST_SHIFT 7 -#define ESYNR1_AWRITE_SHIFT 8 -#define ESYNR1_ABURST_SHIFT 10 -#define ESYNR1_ALEN_SHIFT 12 -#define ESYNR1_ASIZE_SHIFT 16 -#define ESYNR1_ALOCK_SHIFT 20 -#define ESYNR1_AOOO_SHIFT 22 -#define ESYNR1_AFULL_SHIFT 24 -#define ESYNR1_AC_SHIFT 30 -#define ESYNR1_DCD_SHIFT 31 - - -/* IDR */ -#define NM2VCBMT_SHIFT 0 -#define HTW_SHIFT 9 -#define HUM_SHIFT 10 -#define TLBSIZE_SHIFT 12 -#define NCB_SHIFT 16 -#define NIRPT_SHIFT 24 - - -/* M2VCBRn */ -#define VMID_SHIFT 0 -#define CBNDX_SHIFT 8 -#define BYPASSD_SHIFT 16 -#define BPRCOSH_SHIFT 17 -#define BPRCISH_SHIFT 18 -#define BPRCNSH_SHIFT 19 -#define BPSHCFG_SHIFT 20 -#define NSCFG_SHIFT 22 -#define BPMTCFG_SHIFT 24 -#define BPMEMTYPE_SHIFT 25 - - -/* REV */ -#define MINOR_SHIFT 0 -#define MAJOR_SHIFT 4 - - -/* TESTBUSCR */ -#define TBE_SHIFT 0 -#define SPDMBE_SHIFT 1 -#define WGSEL_SHIFT 8 -#define TBLSEL_SHIFT 12 -#define TBHSEL_SHIFT 14 -#define SPDM0SEL_SHIFT 16 -#define SPDM1SEL_SHIFT 20 -#define SPDM2SEL_SHIFT 24 -#define SPDM3SEL_SHIFT 28 - - -/* TLBIMID */ -#define TLBIVMID_VMID_SHIFT 0 - - -/* TLBRSW */ -#define TLBRSW_INDEX_SHIFT 0 -#define TLBBFBS_SHIFT 8 - - -/* TLBTR0 */ -#define PR_SHIFT 0 -#define PW_SHIFT 1 -#define UR_SHIFT 2 -#define UW_SHIFT 3 -#define XN_SHIFT 4 -#define NSDESC_SHIFT 6 -#define ISH_SHIFT 7 -#define SH_SHIFT 8 -#define MT_SHIFT 9 -#define DPSIZR_SHIFT 16 -#define DPSIZC_SHIFT 20 - - -/* TLBTR1 */ -#define TLBTR1_VMID_SHIFT 0 -#define TLBTR1_PA_SHIFT 12 - - -/* TLBTR2 */ -#define TLBTR2_ASID_SHIFT 0 -#define TLBTR2_V_SHIFT 8 -#define TLBTR2_NSTID_SHIFT 9 -#define TLBTR2_NV_SHIFT 10 -#define TLBTR2_VA_SHIFT 12 - - -/* Context Register Masks */ -/* ACTLR */ -#define CFERE_MASK 0x01 -#define CFEIE_MASK 0x01 -#define PTSHCFG_MASK 0x03 -#define RCOSH_MASK 0x01 -#define RCISH_MASK 0x01 -#define RCNSH_MASK 0x01 -#define PRIVCFG_MASK 0x03 -#define DNA_MASK 0x01 -#define DNLV2PA_MASK 0x01 -#define TLBMCFG_MASK 0x03 -#define CFCFG_MASK 0x01 -#define TIPCF_MASK 0x01 -#define V2PCFG_MASK 0x03 -#define HUME_MASK 0x01 -#define PTMTCFG_MASK 0x01 -#define PTMEMTYPE_MASK 0x07 - - -/* BFBCR */ -#define BFBDFE_MASK 0x01 -#define BFBSFE_MASK 0x01 -#define SFVS_MASK 0x01 -#define FLVIC_MASK 0x0F -#define SLVIC_MASK 0x0F - - -/* CONTEXTIDR */ -#define CONTEXTIDR_ASID_MASK 0xFF -#define PROCID_MASK 0x00FFFFFF - - -/* FSR */ -#define TF_MASK 0x01 -#define AFF_MASK 0x01 -#define APF_MASK 0x01 -#define TLBMF_MASK 0x01 -#define HTWDEEF_MASK 0x01 -#define HTWSEEF_MASK 0x01 -#define MHF_MASK 0x01 -#define SL_MASK 0x01 -#define SS_MASK 0x01 -#define MULTI_MASK 0x01 - - -/* FSYNR0 */ -#define AMID_MASK 0xFF -#define APID_MASK 0x1F -#define ABID_MASK 0x07 -#define ATID_MASK 0xFF - - -/* FSYNR1 */ -#define AMEMTYPE_MASK 0x07 -#define ASHARED_MASK 0x01 -#define AINNERSHARED_MASK 0x01 -#define APRIV_MASK 0x01 -#define APROTNS_MASK 0x01 -#define AINST_MASK 0x01 -#define AWRITE_MASK 0x01 -#define ABURST_MASK 0x01 -#define ALEN_MASK 0x0F -#define FSYNR1_ASIZE_MASK 0x07 -#define ALOCK_MASK 0x03 -#define AFULL_MASK 0x01 - - -/* NMRR */ -#define ICPC0_MASK 0x03 -#define ICPC1_MASK 0x03 -#define ICPC2_MASK 0x03 -#define ICPC3_MASK 0x03 -#define ICPC4_MASK 0x03 -#define ICPC5_MASK 0x03 -#define ICPC6_MASK 0x03 -#define ICPC7_MASK 0x03 -#define OCPC0_MASK 0x03 -#define OCPC1_MASK 0x03 -#define OCPC2_MASK 0x03 -#define OCPC3_MASK 0x03 -#define OCPC4_MASK 0x03 -#define OCPC5_MASK 0x03 -#define OCPC6_MASK 0x03 -#define OCPC7_MASK 0x03 - - -/* PAR */ -#define FAULT_MASK 0x01 -/* If a fault is present, these are the -same as the fault fields in the FAR */ -#define FAULT_TF_MASK 0x01 -#define FAULT_AFF_MASK 0x01 -#define FAULT_APF_MASK 0x01 -#define FAULT_TLBMF_MASK 0x01 -#define FAULT_HTWDEEF_MASK 0x01 -#define FAULT_HTWSEEF_MASK 0x01 -#define FAULT_MHF_MASK 0x01 -#define FAULT_SL_MASK 0x01 -#define FAULT_SS_MASK 0x01 - -/* If NO fault is present, the following - * fields are in effect - * (FAULT remains as before) */ -#define PAR_NOFAULT_SS_MASK 0x01 -#define PAR_NOFAULT_MT_MASK 0x07 -#define PAR_NOFAULT_SH_MASK 0x01 -#define PAR_NOFAULT_NS_MASK 0x01 -#define PAR_NOFAULT_NOS_MASK 0x01 -#define PAR_NPFAULT_PA_MASK 0x000FFFFF - - -/* PRRR */ -#define MTC0_MASK 0x03 -#define MTC1_MASK 0x03 -#define MTC2_MASK 0x03 -#define MTC3_MASK 0x03 -#define MTC4_MASK 0x03 -#define MTC5_MASK 0x03 -#define MTC6_MASK 0x03 -#define MTC7_MASK 0x03 -#define SHDSH0_MASK 0x01 -#define SHDSH1_MASK 0x01 -#define SHNMSH0_MASK 0x01 -#define SHNMSH1_MASK 0x01 -#define NOS0_MASK 0x01 -#define NOS1_MASK 0x01 -#define NOS2_MASK 0x01 -#define NOS3_MASK 0x01 -#define NOS4_MASK 0x01 -#define NOS5_MASK 0x01 -#define NOS6_MASK 0x01 -#define NOS7_MASK 0x01 - - -/* RESUME */ -#define TNR_MASK 0x01 - - -/* SCTLR */ -#define M_MASK 0x01 -#define TRE_MASK 0x01 -#define AFE_MASK 0x01 -#define HAF_MASK 0x01 -#define BE_MASK 0x01 -#define AFFD_MASK 0x01 - - -/* TLBIASID */ -#define TLBIASID_ASID_MASK 0xFF - - -/* TLBIVA */ -#define TLBIVA_ASID_MASK 0xFF -#define TLBIVA_VA_MASK 0x000FFFFF - - -/* TLBIVAA */ -#define TLBIVAA_VA_MASK 0x000FFFFF - - -/* TLBLCKR */ -#define LKE_MASK 0x01 -#define TLBLCKR_TLBIALLCFG_MASK 0x01 -#define TLBIASIDCFG_MASK 0x01 -#define TLBIVAACFG_MASK 0x01 -#define FLOOR_MASK 0xFF -#define VICTIM_MASK 0xFF - - -/* TTBCR */ -#define N_MASK 0x07 -#define PD0_MASK 0x01 -#define PD1_MASK 0x01 - - -/* TTBR0 */ -#define TTBR0_IRGNH_MASK 0x01 -#define TTBR0_SH_MASK 0x01 -#define TTBR0_ORGN_MASK 0x03 -#define TTBR0_NOS_MASK 0x01 -#define TTBR0_IRGNL_MASK 0x01 -#define TTBR0_PA_MASK 0x0003FFFF - - -/* TTBR1 */ -#define TTBR1_IRGNH_MASK 0x01 -#define TTBR1_SH_MASK 0x01 -#define TTBR1_ORGN_MASK 0x03 -#define TTBR1_NOS_MASK 0x01 -#define TTBR1_IRGNL_MASK 0x01 -#define TTBR1_PA_MASK 0x0003FFFF - - -/* V2PSR */ -#define HIT_MASK 0x01 -#define INDEX_MASK 0xFF - - -/* V2Pxx */ -#define V2Pxx_INDEX_MASK 0xFF -#define V2Pxx_VA_MASK 0x000FFFFF - - -/* Context Register Shifts */ -/* ACTLR */ -#define CFERE_SHIFT 0 -#define CFEIE_SHIFT 1 -#define PTSHCFG_SHIFT 2 -#define RCOSH_SHIFT 4 -#define RCISH_SHIFT 5 -#define RCNSH_SHIFT 6 -#define PRIVCFG_SHIFT 8 -#define DNA_SHIFT 10 -#define DNLV2PA_SHIFT 11 -#define TLBMCFG_SHIFT 12 -#define CFCFG_SHIFT 14 -#define TIPCF_SHIFT 15 -#define V2PCFG_SHIFT 16 -#define HUME_SHIFT 18 -#define PTMTCFG_SHIFT 20 -#define PTMEMTYPE_SHIFT 21 - - -/* BFBCR */ -#define BFBDFE_SHIFT 0 -#define BFBSFE_SHIFT 1 -#define SFVS_SHIFT 2 -#define FLVIC_SHIFT 4 -#define SLVIC_SHIFT 8 - - -/* CONTEXTIDR */ -#define CONTEXTIDR_ASID_SHIFT 0 -#define PROCID_SHIFT 8 - - -/* FSR */ -#define TF_SHIFT 1 -#define AFF_SHIFT 2 -#define APF_SHIFT 3 -#define TLBMF_SHIFT 4 -#define HTWDEEF_SHIFT 5 -#define HTWSEEF_SHIFT 6 -#define MHF_SHIFT 7 -#define SL_SHIFT 16 -#define SS_SHIFT 30 -#define MULTI_SHIFT 31 - - -/* FSYNR0 */ -#define AMID_SHIFT 0 -#define APID_SHIFT 8 -#define ABID_SHIFT 13 -#define ATID_SHIFT 24 - - -/* FSYNR1 */ -#define AMEMTYPE_SHIFT 0 -#define ASHARED_SHIFT 3 -#define AINNERSHARED_SHIFT 4 -#define APRIV_SHIFT 5 -#define APROTNS_SHIFT 6 -#define AINST_SHIFT 7 -#define AWRITE_SHIFT 8 -#define ABURST_SHIFT 10 -#define ALEN_SHIFT 12 -#define FSYNR1_ASIZE_SHIFT 16 -#define ALOCK_SHIFT 20 -#define AFULL_SHIFT 24 - - -/* NMRR */ -#define ICPC0_SHIFT 0 -#define ICPC1_SHIFT 2 -#define ICPC2_SHIFT 4 -#define ICPC3_SHIFT 6 -#define ICPC4_SHIFT 8 -#define ICPC5_SHIFT 10 -#define ICPC6_SHIFT 12 -#define ICPC7_SHIFT 14 -#define OCPC0_SHIFT 16 -#define OCPC1_SHIFT 18 -#define OCPC2_SHIFT 20 -#define OCPC3_SHIFT 22 -#define OCPC4_SHIFT 24 -#define OCPC5_SHIFT 26 -#define OCPC6_SHIFT 28 -#define OCPC7_SHIFT 30 - - -/* PAR */ -#define FAULT_SHIFT 0 -/* If a fault is present, these are the -same as the fault fields in the FAR */ -#define FAULT_TF_SHIFT 1 -#define FAULT_AFF_SHIFT 2 -#define FAULT_APF_SHIFT 3 -#define FAULT_TLBMF_SHIFT 4 -#define FAULT_HTWDEEF_SHIFT 5 -#define FAULT_HTWSEEF_SHIFT 6 -#define FAULT_MHF_SHIFT 7 -#define FAULT_SL_SHIFT 16 -#define FAULT_SS_SHIFT 30 - -/* If NO fault is present, the following - * fields are in effect - * (FAULT remains as before) */ -#define PAR_NOFAULT_SS_SHIFT 1 -#define PAR_NOFAULT_MT_SHIFT 4 -#define PAR_NOFAULT_SH_SHIFT 7 -#define PAR_NOFAULT_NS_SHIFT 9 -#define PAR_NOFAULT_NOS_SHIFT 10 -#define PAR_NPFAULT_PA_SHIFT 12 - - -/* PRRR */ -#define MTC0_SHIFT 0 -#define MTC1_SHIFT 2 -#define MTC2_SHIFT 4 -#define MTC3_SHIFT 6 -#define MTC4_SHIFT 8 -#define MTC5_SHIFT 10 -#define MTC6_SHIFT 12 -#define MTC7_SHIFT 14 -#define SHDSH0_SHIFT 16 -#define SHDSH1_SHIFT 17 -#define SHNMSH0_SHIFT 18 -#define SHNMSH1_SHIFT 19 -#define NOS0_SHIFT 24 -#define NOS1_SHIFT 25 -#define NOS2_SHIFT 26 -#define NOS3_SHIFT 27 -#define NOS4_SHIFT 28 -#define NOS5_SHIFT 29 -#define NOS6_SHIFT 30 -#define NOS7_SHIFT 31 - - -/* RESUME */ -#define TNR_SHIFT 0 - - -/* SCTLR */ -#define M_SHIFT 0 -#define TRE_SHIFT 1 -#define AFE_SHIFT 2 -#define HAF_SHIFT 3 -#define BE_SHIFT 4 -#define AFFD_SHIFT 5 - - -/* TLBIASID */ -#define TLBIASID_ASID_SHIFT 0 - - -/* TLBIVA */ -#define TLBIVA_ASID_SHIFT 0 -#define TLBIVA_VA_SHIFT 12 - - -/* TLBIVAA */ -#define TLBIVAA_VA_SHIFT 12 - - -/* TLBLCKR */ -#define LKE_SHIFT 0 -#define TLBLCKR_TLBIALLCFG_SHIFT 1 -#define TLBIASIDCFG_SHIFT 2 -#define TLBIVAACFG_SHIFT 3 -#define FLOOR_SHIFT 8 -#define VICTIM_SHIFT 8 - - -/* TTBCR */ -#define N_SHIFT 3 -#define PD0_SHIFT 4 -#define PD1_SHIFT 5 - - -/* TTBR0 */ -#define TTBR0_IRGNH_SHIFT 0 -#define TTBR0_SH_SHIFT 1 -#define TTBR0_ORGN_SHIFT 3 -#define TTBR0_NOS_SHIFT 5 -#define TTBR0_IRGNL_SHIFT 6 -#define TTBR0_PA_SHIFT 14 - - -/* TTBR1 */ -#define TTBR1_IRGNH_SHIFT 0 -#define TTBR1_SH_SHIFT 1 -#define TTBR1_ORGN_SHIFT 3 -#define TTBR1_NOS_SHIFT 5 -#define TTBR1_IRGNL_SHIFT 6 -#define TTBR1_PA_SHIFT 14 - - -/* V2PSR */ -#define HIT_SHIFT 0 -#define INDEX_SHIFT 8 - - -/* V2Pxx */ -#define V2Pxx_INDEX_SHIFT 0 -#define V2Pxx_VA_SHIFT 12 - -#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h deleted file mode 100644 index 7bca8d7108d6..000000000000 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. - * Author: Brian Swetland <swetland@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * The MSM peripherals are spread all over across 768MB of physical - * space, which makes just having a simple IO_ADDRESS macro to slide - * them into the right virtual location rough. Instead, we will - * provide a master phys->virt mapping for peripherals here. - * - */ - -#ifndef __ASM_ARCH_MSM_IOMAP_8960_H -#define __ASM_ARCH_MSM_IOMAP_8960_H - -/* Physical base address and size of peripherals. - * Ordered by the virtual base addresses they will be mapped at. - * - * If you add or remove entries here, you'll want to edit the - * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your - * changes. - * - */ - -#define MSM8960_TMR_PHYS 0x0200A000 -#define MSM8960_TMR_SIZE SZ_4K - -#define MSM8960_TMR0_PHYS 0x0208A000 -#define MSM8960_TMR0_SIZE SZ_4K - -#ifdef CONFIG_DEBUG_MSM8960_UART -#define MSM_DEBUG_UART_BASE 0xF0040000 -#define MSM_DEBUG_UART_PHYS 0x16440000 -#endif - -#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h deleted file mode 100644 index 75a7b62c1c74..000000000000 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. - * Author: Brian Swetland <swetland@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * The MSM peripherals are spread all over across 768MB of physical - * space, which makes just having a simple IO_ADDRESS macro to slide - * them into the right virtual location rough. Instead, we will - * provide a master phys->virt mapping for peripherals here. - * - */ - -#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H -#define __ASM_ARCH_MSM_IOMAP_8X60_H - -/* Physical base address and size of peripherals. - * Ordered by the virtual base addresses they will be mapped at. - * - * MSM_VIC_BASE must be an value that can be loaded via a "mov" - * instruction, otherwise entry-macro.S will not compile. - * - * If you add or remove entries here, you'll want to edit the - * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your - * changes. - * - */ - -#define MSM_TLMM_BASE IOMEM(0xF0004000) -#define MSM_TLMM_PHYS 0x00800000 -#define MSM_TLMM_SIZE SZ_16K - -#define MSM8X60_TMR_PHYS 0x02000000 -#define MSM8X60_TMR_SIZE SZ_4K - -#define MSM8X60_TMR0_PHYS 0x02040000 -#define MSM8X60_TMR0_SIZE SZ_4K - -#ifdef CONFIG_DEBUG_MSM8660_UART -#define MSM_DEBUG_UART_BASE 0xF0040000 -#define MSM_DEBUG_UART_PHYS 0x19C40000 -#endif - -#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index c56e81ffdcde..0e4f49157684 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -45,25 +45,8 @@ #include "msm_iomap-7x00.h" #endif -#include "msm_iomap-8x60.h" -#include "msm_iomap-8960.h" - -#define MSM_DEBUG_UART_SIZE SZ_4K -#if defined(CONFIG_DEBUG_MSM_UART1) -#define MSM_DEBUG_UART_BASE 0xE1000000 -#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS -#elif defined(CONFIG_DEBUG_MSM_UART2) -#define MSM_DEBUG_UART_BASE 0xE1000000 -#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS -#elif defined(CONFIG_DEBUG_MSM_UART3) -#define MSM_DEBUG_UART_BASE 0xE1000000 -#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS -#endif - /* Virtual addresses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_TMR_BASE IOMEM(0xF0200000) -#define MSM_TMR0_BASE IOMEM(0xF0201000) #define MSM_GPIO1_BASE IOMEM(0xE0003000) #define MSM_GPIO2_BASE IOMEM(0xE0004000) diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h deleted file mode 100644 index 94324870fb04..000000000000 --- a/arch/arm/mach-msm/include/mach/uncompress.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H -#define __ASM_ARCH_MSM_UNCOMPRESS_H - -#include <asm/barrier.h> -#include <asm/processor.h> -#include <mach/msm_iomap.h> - -#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)) -#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c)) - -#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))) -#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10))) -#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14))) -#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40))) -#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70))) - -static void putc(int c) -{ -#if defined(MSM_DEBUG_UART_PHYS) -#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS - /* - * Wait for TX_READY to be set; but skip it if we have a - * TX underrun. - */ - if (!(UART_DM_SR & 0x08)) - while (!(UART_DM_ISR & 0x80)) - cpu_relax(); - - UART_DM_CR = 0x300; - UART_DM_NCHAR = 0x1; - UART_DM_TF = c; -#else - while (!(UART_CSR & 0x04)) - cpu_relax(); - UART_TF = c; -#endif -#endif -} - -static inline void flush(void) -{ -} - -static inline void arch_decomp_setup(void) -{ -} - -#endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 3dc04ccaf59f..adc8971c7266 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -18,6 +18,7 @@ */ #include <linux/kernel.h> +#include <linux/bug.h> #include <linux/init.h> #include <linux/io.h> #include <linux/export.h> @@ -27,8 +28,6 @@ #include <mach/msm_iomap.h> #include <asm/mach/map.h> -#include <mach/board.h> - #include "common.h" #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ @@ -52,26 +51,38 @@ static struct map_desc msm_io_desc[] __initdata = { MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), -#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ - defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), -#endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), .length = MSM_SHARED_RAM_SIZE, .type = MT_DEVICE, }, +#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ + defined(CONFIG_DEBUG_MSM_UART3) + { + /* Must be last: virtual and pfn filled in by debug_ll_addr() */ + .length = SZ_4K, + .type = MT_DEVICE_NONSHARED, + } +#endif }; void __init msm_map_common_io(void) { + size_t size = ARRAY_SIZE(msm_io_desc); + /* Make sure the peripheral register window is closed, since * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which * pages are peripheral interface or not. */ asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); - iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); +#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ + defined(CONFIG_DEBUG_MSM_UART3) + debug_ll_addr(&msm_io_desc[size - 1].pfn, + &msm_io_desc[size - 1].virtual); + msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn); +#endif + iotable_init(msm_io_desc, size); } #endif @@ -87,10 +98,6 @@ static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(SCPLL), MSM_DEVICE(AD5), MSM_DEVICE(MDC), -#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ - defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE(DEBUG_UART), -#endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), @@ -101,40 +108,11 @@ static struct map_desc qsd8x50_io_desc[] __initdata = { void __init msm_map_qsd8x50_io(void) { + debug_ll_io_init(); iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); } #endif /* CONFIG_ARCH_QSD8X50 */ -#ifdef CONFIG_ARCH_MSM8X60 -static struct map_desc msm8x60_io_desc[] __initdata = { - MSM_CHIP_DEVICE(TMR, MSM8X60), - MSM_CHIP_DEVICE(TMR0, MSM8X60), -#ifdef CONFIG_DEBUG_MSM8660_UART - MSM_DEVICE(DEBUG_UART), -#endif -}; - -void __init msm_map_msm8x60_io(void) -{ - iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc)); -} -#endif /* CONFIG_ARCH_MSM8X60 */ - -#ifdef CONFIG_ARCH_MSM8960 -static struct map_desc msm8960_io_desc[] __initdata = { - MSM_CHIP_DEVICE(TMR, MSM8960), - MSM_CHIP_DEVICE(TMR0, MSM8960), -#ifdef CONFIG_DEBUG_MSM8960_UART - MSM_DEVICE(DEBUG_UART), -#endif -}; - -void __init msm_map_msm8960_io(void) -{ - iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); -} -#endif /* CONFIG_ARCH_MSM8960 */ - #ifdef CONFIG_ARCH_MSM7X30 static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), @@ -150,10 +128,6 @@ static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(SAW), MSM_DEVICE(GCC), MSM_DEVICE(TCSR), -#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ - defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE(DEBUG_UART), -#endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), @@ -164,10 +138,12 @@ static struct map_desc msm7x30_io_desc[] __initdata = { void __init msm_map_msm7x30_io(void) { + debug_ll_io_init(); iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); } #endif /* CONFIG_ARCH_MSM7X30 */ +#ifdef CONFIG_ARCH_MSM7X00A void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, unsigned int mtype, void *caller) { @@ -182,3 +158,4 @@ void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, return __arm_ioremap_caller(phys_addr, size, mtype, caller); } +#endif diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 8697cfc0d0b6..696fb73296d0 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -16,6 +16,7 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> +#include <linux/cpu.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -26,7 +27,6 @@ #include <linux/sched_clock.h> #include <asm/mach/time.h> -#include <asm/localtimer.h> #include "common.h" @@ -49,7 +49,7 @@ static void __iomem *sts_base; static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = *(struct clock_event_device **)dev_id; + struct clock_event_device *evt = dev_id; /* Stop the timer tick */ if (evt->mode == CLOCK_EVT_MODE_ONESHOT) { u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); @@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode, writel_relaxed(ctrl, event_base + TIMER_ENABLE); } -static struct clock_event_device msm_clockevent = { - .name = "gp_timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = msm_timer_set_next_event, - .set_mode = msm_timer_set_mode, -}; - -static union { - struct clock_event_device *evt; - struct clock_event_device * __percpu *percpu_evt; -} msm_evt; +static struct clock_event_device __percpu *msm_evt; static void __iomem *source_base; @@ -138,23 +127,34 @@ static struct clocksource msm_clocksource = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -#ifdef CONFIG_LOCAL_TIMERS +static int msm_timer_irq; +static int msm_timer_has_ppi; + static int msm_local_timer_setup(struct clock_event_device *evt) { - /* Use existing clock_event for cpu 0 */ - if (!smp_processor_id()) - return 0; - - evt->irq = msm_clockevent.irq; - evt->name = "local_timer"; - evt->features = msm_clockevent.features; - evt->rating = msm_clockevent.rating; + int cpu = smp_processor_id(); + int err; + + evt->irq = msm_timer_irq; + evt->name = "msm_timer"; + evt->features = CLOCK_EVT_FEAT_ONESHOT; + evt->rating = 200; evt->set_mode = msm_timer_set_mode; evt->set_next_event = msm_timer_set_next_event; + evt->cpumask = cpumask_of(cpu); + + clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff); + + if (msm_timer_has_ppi) { + enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); + } else { + err = request_irq(evt->irq, msm_timer_interrupt, + IRQF_TIMER | IRQF_NOBALANCING | + IRQF_TRIGGER_RISING, "gp_timer", evt); + if (err) + pr_err("request_irq failed\n"); + } - *__this_cpu_ptr(msm_evt.percpu_evt) = evt; - clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000); - enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } @@ -164,11 +164,28 @@ static void msm_local_timer_stop(struct clock_event_device *evt) disable_percpu_irq(evt->irq); } -static struct local_timer_ops msm_local_timer_ops = { - .setup = msm_local_timer_setup, - .stop = msm_local_timer_stop, +static int msm_timer_cpu_notify(struct notifier_block *self, + unsigned long action, void *hcpu) +{ + /* + * Grab cpu pointer in each case to avoid spurious + * preemptible warnings + */ + switch (action & ~CPU_TASKS_FROZEN) { + case CPU_STARTING: + msm_local_timer_setup(this_cpu_ptr(msm_evt)); + break; + case CPU_DYING: + msm_local_timer_stop(this_cpu_ptr(msm_evt)); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block msm_timer_cpu_nb = { + .notifier_call = msm_timer_cpu_notify, }; -#endif /* CONFIG_LOCAL_TIMERS */ static notrace u32 msm_sched_clock_read(void) { @@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void) static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, bool percpu) { - struct clock_event_device *ce = &msm_clockevent; struct clocksource *cs = &msm_clocksource; - int res; + int res = 0; + + msm_timer_irq = irq; + msm_timer_has_ppi = percpu; + + msm_evt = alloc_percpu(struct clock_event_device); + if (!msm_evt) { + pr_err("memory allocation failed for clockevents\n"); + goto err; + } - ce->cpumask = cpumask_of(0); - ce->irq = irq; + if (percpu) + res = request_percpu_irq(irq, msm_timer_interrupt, + "gp_timer", msm_evt); - clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); - if (percpu) { - msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); - if (!msm_evt.percpu_evt) { - pr_err("memory allocation failed for %s\n", ce->name); + if (res) { + pr_err("request_percpu_irq failed\n"); + } else { + res = register_cpu_notifier(&msm_timer_cpu_nb); + if (res) { + free_percpu_irq(irq, msm_evt); goto err; } - *__this_cpu_ptr(msm_evt.percpu_evt) = ce; - res = request_percpu_irq(ce->irq, msm_timer_interrupt, - ce->name, msm_evt.percpu_evt); - if (!res) { - enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING); -#ifdef CONFIG_LOCAL_TIMERS - local_timer_register(&msm_local_timer_ops); -#endif - } - } else { - msm_evt.evt = ce; - res = request_irq(ce->irq, msm_timer_interrupt, - IRQF_TIMER | IRQF_NOBALANCING | - IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt); + + /* Immediately configure the timer on the boot CPU */ + msm_local_timer_setup(__this_cpu_ptr(msm_evt)); } - if (res) - pr_err("request_irq failed for %s\n", ce->name); err: writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); res = clocksource_register_hz(cs, dgt_hz); @@ -219,15 +233,8 @@ err: } #ifdef CONFIG_OF -static const struct of_device_id msm_timer_match[] __initconst = { - { .compatible = "qcom,kpss-timer" }, - { .compatible = "qcom,scss-timer" }, - { }, -}; - -void __init msm_dt_timer_init(void) +static void __init msm_dt_timer_init(struct device_node *np) { - struct device_node *np; u32 freq; int irq; struct resource res; @@ -235,12 +242,6 @@ void __init msm_dt_timer_init(void) void __iomem *base; void __iomem *cpu0_base; - np = of_find_matching_node(NULL, msm_timer_match); - if (!np) { - pr_err("Can't find msm timer DT node\n"); - return; - } - base = of_iomap(np, 0); if (!base) { pr_err("Failed to map event base\n"); @@ -283,6 +284,8 @@ void __init msm_dt_timer_init(void) msm_timer_init(freq, 32, irq, !!percpu_offset); } +CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); +CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); #endif static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S deleted file mode 100644 index a7df02b049b7..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/mv78xx0.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =MV78XX0_REGS_PHYS_BASE - ldr \rv, =MV78XX0_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index dc26a654c496..445e553f4a28 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -18,6 +18,11 @@ #include <mach/mv78xx0.h> #include "common.h" +#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) +#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) +#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) +#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) + struct pcie_port { u8 maj; u8 min; @@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void) start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; - char winname[MVEBU_MBUS_MAX_WINNAME_SZ]; snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); @@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void) if (request_resource(&iomem_resource, &pp->res)) panic("can't allocate PCIe MEM sub-space"); - snprintf(winname, sizeof(winname), "pcie%d.%d", - pp->maj, pp->min); - - mvebu_mbus_add_window_remap_flags(winname, - pp->res.start, - resource_size(&pp->res), - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags(winname, - i * SZ_64K, SZ_64K, - 0, MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min), + MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min), + pp->res.start, resource_size(&pp->res)); + mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min), + MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min), + i * SZ_64K, SZ_64K, 0); } } diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 97cbb8021919..829b57306328 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void) debug_ll_io_init(); } -/* - * This initialization will be replaced by a DT-based - * initialization once the mvebu-mbus driver gains DT support. - */ - -#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000 -#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 -#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180 -#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 - -static void __init armada_370_xp_mbus_init(void) -{ - char *mbus_soc_name; - struct device_node *dn; - const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS); - const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS); - - if (of_machine_is_compatible("marvell,armada370")) - mbus_soc_name = "marvell,armada370-mbus"; - else - mbus_soc_name = "marvell,armadaxp-mbus"; - - dn = of_find_node_by_name(NULL, "internal-regs"); - BUG_ON(!dn); - - mvebu_mbus_init(mbus_soc_name, - of_translate_address(dn, &mbus_wins_offs), - ARMADA_370_XP_MBUS_WINS_SIZE, - of_translate_address(dn, &sdram_wins_offs), - ARMADA_370_XP_SDRAM_WINS_SIZE); -} - static void __init armada_370_xp_timer_and_clk_init(void) { of_clk_init(NULL); armada_370_xp_timer_init(); coherency_init(); - armada_370_xp_mbus_init(); + BUG_ON(mvebu_mbus_dt_init()); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index ce81d3031405..ff69c2df298b 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -21,6 +21,7 @@ #include <linux/smp.h> #include <linux/clk.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/mbus.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -29,45 +30,43 @@ #include "pmsu.h" #include "coherency.h" +#define AXP_BOOTROM_BASE 0xfff00000 +#define AXP_BOOTROM_SIZE 0x100000 + +static struct clk *__init get_cpu_clk(int cpu) +{ + struct clk *cpu_clk; + struct device_node *np = of_get_cpu_node(cpu, NULL); + + if (WARN(!np, "missing cpu node\n")) + return NULL; + cpu_clk = of_clk_get(np, 0); + if (WARN_ON(IS_ERR(cpu_clk))) + return NULL; + return cpu_clk; +} + void __init set_secondary_cpus_clock(void) { - int thiscpu; + int thiscpu, cpu; unsigned long rate; - struct clk *cpu_clk = NULL; - struct device_node *np = NULL; + struct clk *cpu_clk; thiscpu = smp_processor_id(); - for_each_node_by_type(np, "cpu") { - int err; - int cpu; - - err = of_property_read_u32(np, "reg", &cpu); - if (WARN_ON(err)) - return; - - if (cpu == thiscpu) { - cpu_clk = of_clk_get(np, 0); - break; - } - } - if (WARN_ON(IS_ERR(cpu_clk))) + cpu_clk = get_cpu_clk(thiscpu); + if (!cpu_clk) return; clk_prepare_enable(cpu_clk); rate = clk_get_rate(cpu_clk); /* set all the other CPU clk to the same rate than the boot CPU */ - for_each_node_by_type(np, "cpu") { - int err; - int cpu; - - err = of_property_read_u32(np, "reg", &cpu); - if (WARN_ON(err)) + for_each_possible_cpu(cpu) { + if (cpu == thiscpu) + continue; + cpu_clk = get_cpu_clk(cpu); + if (!cpu_clk) return; - - if (cpu != thiscpu) { - cpu_clk = of_clk_get(np, 0); - clk_set_rate(cpu_clk, rate); - } + clk_set_rate(cpu_clk, rate); } } @@ -87,37 +86,39 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init armada_xp_smp_init_cpus(void) { - struct device_node *np; - unsigned int i, ncores; + unsigned int ncores = num_possible_cpus(); - np = of_find_node_by_name(NULL, "cpus"); - if (!np) - panic("No 'cpus' node found\n"); - - ncores = of_get_child_count(np); if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS) panic("Invalid number of CPUs in DT\n"); - /* Limit possible CPUs to defconfig */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %d CPUs physically present. Only %d configured.", - ncores, nr_cpu_ids); - pr_warn("Clipping CPU count to %d\n", nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); - set_smp_cross_call(armada_mpic_send_doorbell); } void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) { + struct device_node *node; + struct resource res; + int err; + set_secondary_cpus_clock(); flush_cache_all(); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); - mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); + + /* + * In order to boot the secondary CPUs we need to ensure + * the bootROM is mapped at the correct address. + */ + node = of_find_compatible_node(NULL, NULL, "marvell,bootrom"); + if (!node) + panic("Cannot find 'marvell,bootrom' compatible node"); + + err = of_address_to_resource(node, 0, &res); + if (err < 0) + panic("Cannot get 'bootrom' node address"); + + if (res.start != AXP_BOOTROM_BASE || + resource_size(&res) != AXP_BOOTROM_SIZE) + panic("The address for the BootROM is incorrect"); } struct smp_operations armada_xp_smp_ops __initdata = { diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 4ce27b536dc9..98f6e2adb53e 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -14,6 +14,7 @@ #include <linux/clk/mxs.h> #include <linux/clkdev.h> #include <linux/clocksource.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio.h> @@ -61,6 +62,8 @@ static u32 chipid; static u32 socid; +static void __iomem *reset_addr; + static inline void __mxs_setl(u32 mask, void __iomem *reg) { __raw_writel(mask, reg + MXS_SET_ADDR); @@ -393,12 +396,33 @@ static const char __init *mxs_get_revision(void) u32 rev = mxs_get_cpu_rev(); if (rev != MXS_CHIP_REV_UNKNOWN) - return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf, + return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf, rev & 0xf); else return kasprintf(GFP_KERNEL, "%s", "Unknown"); } +#define MX23_CLKCTRL_RESET_OFFSET 0x120 +#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 + +static int __init mxs_restart_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); + reset_addr = of_iomap(np, 0); + if (!reset_addr) + return -ENODEV; + + if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) + reset_addr += MX23_CLKCTRL_RESET_OFFSET; + else + reset_addr += MX28_CLKCTRL_RESET_OFFSET; + of_node_put(np); + + return 0; +} + static void __init mxs_machine_init(void) { struct device_node *root; @@ -433,21 +457,18 @@ static void __init mxs_machine_init(void) imx28_evk_init(); else if (of_machine_is_compatible("bluegiga,apx4devkit")) apx4devkit_init(); - else if (of_machine_is_compatible("crystalfontz,cfa10037") || - of_machine_is_compatible("crystalfontz,cfa10049") || - of_machine_is_compatible("crystalfontz,cfa10055") || - of_machine_is_compatible("crystalfontz,cfa10057")) + else if (of_machine_is_compatible("crystalfontz,cfa10036")) crystalfontz_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); + mxs_restart_init(); + if (of_machine_is_compatible("karo,tx28")) tx28_post_init(); } -#define MX23_CLKCTRL_RESET_OFFSET 0x120 -#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 #define MXS_CLKCTRL_RESET_CHIP (1 << 1) /* @@ -455,28 +476,16 @@ static void __init mxs_machine_init(void) */ static void mxs_restart(enum reboot_mode mode, const char *cmd) { - struct device_node *np; - void __iomem *reset_addr; + if (reset_addr) { + /* reset the chip */ + __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); - np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); - reset_addr = of_iomap(np, 0); - if (!reset_addr) - goto soft; + pr_err("Failed to assert the chip reset\n"); - if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) - reset_addr += MX23_CLKCTRL_RESET_OFFSET; - else - reset_addr += MX28_CLKCTRL_RESET_OFFSET; - - /* reset the chip */ - __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); - - pr_err("Failed to assert the chip reset\n"); - - /* Delay to allow the serial port to show the message */ - mdelay(50); + /* Delay to allow the serial port to show the message */ + mdelay(50); + } -soft: /* We'll take a jump through zero as a poor second */ soft_restart(0); } @@ -487,6 +496,7 @@ static void __init mxs_timer_init(void) mx23_clocks_init(); else mx28_clocks_init(); + of_clk_init(NULL); clocksource_of_init(); } diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c index b2494d2db2c4..0170e99fd70f 100644 --- a/arch/arm/mach-mxs/pm.c +++ b/arch/arm/mach-mxs/pm.c @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/suspend.h> #include <linux/io.h> +#include "pm.h" static int mxs_suspend_enter(suspend_state_t state) { diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 5981c3db9b41..4d42da49753c 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -27,6 +27,7 @@ config MACH_NOMADIK_8815NHK select NOMADIK_8815 select I2C select I2C_ALGOBIT + select I2C_NOMADIK endmenu endif diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h index 6cf9c1cc2bef..612bd1cc257c 100644 --- a/arch/arm/mach-omap1/include/mach/soc.h +++ b/arch/arm/mach-omap1/include/mach/soc.h @@ -195,6 +195,7 @@ IS_OMAP_TYPE(1710, 0x1710) #define cpu_is_omap34xx() 0 #define cpu_is_omap44xx() 0 #define soc_is_omap54xx() 0 +#define soc_is_dra7xx() 0 #define soc_is_am33xx() 0 #define cpu_class_is_omap1() 1 #define cpu_class_is_omap2() 0 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3eed0006d189..b5fb5f7992df 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -37,9 +37,8 @@ config ARCH_OMAP4 select CACHE_L2X0 select CPU_V7 select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP - select LOCAL_TIMERS if SMP select OMAP_INTERCONNECT select PL310_ERRATA_588369 select PL310_ERRATA_727915 @@ -65,7 +64,7 @@ config SOC_OMAP5 select ARM_ERRATA_798181 if SMP config SOC_AM33XX - bool "AM33XX support" + bool "TI AM33XX" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS select ARM_CPU_SUSPEND if PM @@ -118,7 +117,7 @@ config ARCH_OMAP2PLUS_TYPICAL select I2C select I2C_OMAP select MENELAUS if ARCH_OMAP2 - select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 + select NEON if CPU_V7 select PM_RUNTIME select REGULATOR select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 @@ -132,9 +131,17 @@ config SOC_HAS_OMAP2_SDRC config SOC_HAS_REALTIME_COUNTER bool "Real time free running counter" - depends on SOC_OMAP5 + depends on SOC_OMAP5 || SOC_DRA7XX default y +config SOC_DRA7XX + bool "TI DRA7XX" + select ARM_ARCH_TIMER + select CPU_V7 + select ARM_GIC + select HAVE_SMP + select COMMON_CLK + comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d4f671547c37..cc36bfe104fe 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -87,6 +89,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o +obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -114,6 +117,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ vc44xx_data.o vp44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -143,6 +147,7 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -160,6 +165,7 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c index 1eae96212315..c88d8df753c2 100644 --- a/arch/arm/mach-omap2/am33xx-restart.c +++ b/arch/arm/mach-omap2/am33xx-restart.c @@ -24,8 +24,8 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd) { /* TODO: Handle mode and cmd if necessary */ - am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK, - AM33XX_GLOBAL_WARM_SW_RST_MASK, + am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, + AM33XX_RST_GLOBAL_WARM_SW_MASK, AM33XX_PRM_DEVICE_MOD, AM33XX_PRM_RSTCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 244d8a5aa54b..c711ad6ac067 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -100,39 +100,52 @@ static struct platform_device sdp2430_flash_device = { .resource = &sdp2430_flash_resource, }; -static struct platform_device *sdp2430_devices[] __initdata = { - &sdp2430_flash_device, -}; - /* LCD */ #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 #define SDP2430_LCD_PANEL_ENABLE_GPIO 154 -static struct panel_generic_dpi_data sdp2430_panel_data = { - .name = "nec_nl2432dr22-11b", - .num_gpios = 2, - .gpios = { - SDP2430_LCD_PANEL_ENABLE_GPIO, - SDP2430_LCD_PANEL_BACKLIGHT_GPIO, - }, +static const struct display_timing sdp2430_lcd_videomode = { + .pixelclock = { 0, 5400000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 39, 0 }, + .hsync_len = { 0, 3, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 2, 0 }, + .vback_porch = { 0, 7, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device sdp2430_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &sdp2430_panel_data, +static struct panel_dpi_platform_data sdp2430_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &sdp2430_lcd_videomode, + + .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO, + .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO, }; -static struct omap_dss_device *sdp2430_dss_devices[] = { - &sdp2430_lcd_device, +static struct platform_device sdp2430_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &sdp2430_lcd_pdata, }; static struct omap_dss_board_info sdp2430_dss_data = { - .num_devices = ARRAY_SIZE(sdp2430_dss_devices), - .devices = sdp2430_dss_devices, - .default_device = &sdp2430_lcd_device, + .default_display_name = "lcd", +}; + +static struct platform_device *sdp2430_devices[] __initdata = { + &sdp2430_flash_device, + &sdp2430_lcd_device, }; #if IS_ENABLED(CONFIG_SMC91X) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 23b004afa3f8..d95d0ef1354a 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -126,53 +126,65 @@ static void __init sdp3430_display_init(void) } -static struct panel_sharp_ls037v7dw01_data sdp3430_lcd_data = { - .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO, - .ini_gpio = -1, - .mo_gpio = -1, - .lr_gpio = -1, - .ud_gpio = -1, +static struct panel_sharp_ls037v7dw01_platform_data sdp3430_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO, + .ini_gpio = -1, + .mo_gpio = -1, + .lr_gpio = -1, + .ud_gpio = -1, +}; + +static struct platform_device sdp3430_lcd_device = { + .name = "panel-sharp-ls037v7dw01", + .id = 0, + .dev.platform_data = &sdp3430_lcd_pdata, }; -static struct omap_dss_device sdp3430_lcd_device = { - .name = "lcd", - .driver_name = "sharp_ls_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &sdp3430_lcd_data, +static struct connector_dvi_platform_data sdp3430_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = -1, +static struct platform_device sdp3430_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &sdp3430_dvi_connector_pdata, }; -static struct omap_dss_device sdp3430_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct encoder_tfp410_platform_data sdp3430_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, }; -static struct omap_dss_device sdp3430_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device sdp3430_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &sdp3430_tfp410_pdata, }; +static struct connector_atv_platform_data sdp3430_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; -static struct omap_dss_device *sdp3430_dss_devices[] = { - &sdp3430_lcd_device, - &sdp3430_dvi_device, - &sdp3430_tv_device, +static struct platform_device sdp3430_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &sdp3430_tv_pdata, }; static struct omap_dss_board_info sdp3430_dss_data = { - .num_devices = ARRAY_SIZE(sdp3430_dss_devices), - .devices = sdp3430_dss_devices, - .default_device = &sdp3430_lcd_device, + .default_display_name = "lcd", }; static struct omap2_hsmmc_info mmc[] = { @@ -583,6 +595,11 @@ static void __init omap_3430sdp_init(void) omap_hsmmc_init(mmc); omap3430_i2c_init(); omap_display_init(&sdp3430_dss_data); + platform_device_register(&sdp3430_lcd_device); + platform_device_register(&sdp3430_tfp410_device); + platform_device_register(&sdp3430_dvi_connector_device); + platform_device_register(&sdp3430_tv_connector_device); + if (omap_rev() > OMAP3430_REV_ES1_0) gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2; else diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index fc53911d0d13..0d499a1878f6 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -110,8 +110,6 @@ static void __init am3517_crane_i2c_init(void) static void __init am3517_crane_init(void) { - int ret; - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); omap_sdrc_init(NULL, NULL); diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index d63f14b534b5..543d9a882de3 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -21,7 +21,7 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> #include <linux/mmc/host.h> @@ -120,56 +120,95 @@ static int __init am3517_evm_i2c_init(void) return 0; } -static struct panel_generic_dpi_data lcd_panel = { - .name = "sharp_lq", - .num_gpios = 3, - .gpios = { - LCD_PANEL_PWR, - LCD_PANEL_BKLIGHT_PWR, - LCD_PANEL_PWM, - }, +static const struct display_timing am3517_evm_lcd_videomode = { + .pixelclock = { 0, 9000000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 2, 0 }, + .hsync_len = { 0, 42, 0 }, + + .vactive = { 0, 272, 0 }, + .vfront_porch = { 0, 3, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 11, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW | DISPLAY_FLAGS_PIXDATA_POSEDGE, +}; + +static struct panel_dpi_platform_data am3517_evm_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &am3517_evm_lcd_videomode, + + .enable_gpio = LCD_PANEL_PWR, + .backlight_gpio = LCD_PANEL_BKLIGHT_PWR, +}; + +static struct platform_device am3517_evm_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &am3517_evm_lcd_pdata, }; -static struct omap_dss_device am3517_evm_lcd_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "lcd", - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 16, +static struct connector_dvi_platform_data am3517_evm_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct omap_dss_device am3517_evm_tv_device = { - .type = OMAP_DISPLAY_TYPE_VENC, - .name = "tv", - .driver_name = "venc", - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device am3517_evm_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &am3517_evm_dvi_connector_pdata, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = -1, +static struct encoder_tfp410_platform_data am3517_evm_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, }; -static struct omap_dss_device am3517_evm_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device am3517_evm_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &am3517_evm_tfp410_pdata, }; -static struct omap_dss_device *am3517_evm_dss_devices[] = { - &am3517_evm_lcd_device, - &am3517_evm_tv_device, - &am3517_evm_dvi_device, +static struct connector_atv_platform_data am3517_evm_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device am3517_evm_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &am3517_evm_tv_pdata, }; static struct omap_dss_board_info am3517_evm_dss_data = { - .num_devices = ARRAY_SIZE(am3517_evm_dss_devices), - .devices = am3517_evm_dss_devices, - .default_device = &am3517_evm_lcd_device, + .default_display_name = "lcd", }; +static void __init am3517_evm_display_init(void) +{ + gpio_request_one(LCD_PANEL_PWM, GPIOF_OUT_INIT_HIGH, "lcd panel pwm"); + + omap_display_init(&am3517_evm_dss_data); + + platform_device_register(&am3517_evm_tfp410_device); + platform_device_register(&am3517_evm_dvi_connector_device); + platform_device_register(&am3517_evm_lcd_device); + platform_device_register(&am3517_evm_tv_connector_device); +} + /* * Board initialization */ @@ -295,7 +334,9 @@ static void __init am3517_evm_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); - omap_display_init(&am3517_evm_dss_data); + + am3517_evm_display_init(); + omap_serial_init(); omap_sdrc_init(NULL, NULL); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index d4622ed26252..33d159e2386e 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -190,52 +190,81 @@ static inline void cm_t35_init_nand(void) {} #define CM_T35_LCD_BL_GPIO 58 #define CM_T35_DVI_EN_GPIO 54 -static struct panel_generic_dpi_data lcd_panel = { - .name = "toppoly_tdo35s", - .num_gpios = 1, - .gpios = { - CM_T35_LCD_BL_GPIO, - }, +static const struct display_timing cm_t35_lcd_videomode = { + .pixelclock = { 0, 26000000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 104, 0 }, + .hback_porch = { 0, 8, 0 }, + .hsync_len = { 0, 8, 0 }, + + .vactive = { 0, 640, 0 }, + .vfront_porch = { 0, 4, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 2, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + +static struct panel_dpi_platform_data cm_t35_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .display_timing = &cm_t35_lcd_videomode, + + .enable_gpio = -1, + .backlight_gpio = CM_T35_LCD_BL_GPIO, +}; + +static struct platform_device cm_t35_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &cm_t35_lcd_pdata, }; -static struct omap_dss_device cm_t35_lcd_device = { - .name = "lcd", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 18, +static struct connector_dvi_platform_data cm_t35_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = CM_T35_DVI_EN_GPIO, - .i2c_bus_num = -1, +static struct platform_device cm_t35_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &cm_t35_dvi_connector_pdata, }; -static struct omap_dss_device cm_t35_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct encoder_tfp410_platform_data cm_t35_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = CM_T35_DVI_EN_GPIO, }; -static struct omap_dss_device cm_t35_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device cm_t35_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &cm_t35_tfp410_pdata, }; -static struct omap_dss_device *cm_t35_dss_devices[] = { - &cm_t35_lcd_device, - &cm_t35_dvi_device, - &cm_t35_tv_device, +static struct connector_atv_platform_data cm_t35_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device cm_t35_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &cm_t35_tv_pdata, }; static struct omap_dss_board_info cm_t35_dss_data = { - .num_devices = ARRAY_SIZE(cm_t35_dss_devices), - .devices = cm_t35_dss_devices, - .default_device = &cm_t35_dvi_device, + .default_display_name = "dvi", }; static struct omap2_mcspi_device_config tdo24m_mcspi_config = { @@ -280,6 +309,11 @@ static void __init cm_t35_init_display(void) pr_err("CM-T35: failed to register DSS device\n"); gpio_free(CM_T35_LCD_EN_GPIO); } + + platform_device_register(&cm_t35_tfp410_device); + platform_device_register(&cm_t35_dvi_connector_device); + platform_device_register(&cm_t35_lcd_device); + platform_device_register(&cm_t35_tv_connector_device); } static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index f1d91ba5d1ac..cdc4fb9960a9 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -112,50 +112,81 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = { REGULATOR_SUPPLY("vcc", "spi2.0"), }; -static struct panel_generic_dpi_data lcd_panel = { - .name = "innolux_at070tn83", - /* gpios filled in code */ +static const struct display_timing devkit8000_lcd_videomode = { + .pixelclock = { 0, 40000000, 0 }, + + .hactive = { 0, 800, 0 }, + .hfront_porch = { 0, 1, 0 }, + .hback_porch = { 0, 1, 0 }, + .hsync_len = { 0, 48, 0 }, + + .vactive = { 0, 480, 0 }, + .vfront_porch = { 0, 12, 0 }, + .vback_porch = { 0, 25, 0 }, + .vsync_len = { 0, 3, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device devkit8000_lcd_device = { +static struct panel_dpi_platform_data devkit8000_lcd_pdata = { .name = "lcd", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 24, + .source = "dpi.0", + + .data_lines = 24, + + .display_timing = &devkit8000_lcd_videomode, + + .enable_gpio = -1, /* filled in code */ + .backlight_gpio = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = 1, +static struct platform_device devkit8000_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &devkit8000_lcd_pdata, }; -static struct omap_dss_device devkit8000_dvi_device = { +static struct connector_dvi_platform_data devkit8000_dvi_connector_pdata = { .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, + .source = "tfp410.0", + .i2c_bus_num = 1, }; -static struct omap_dss_device devkit8000_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device devkit8000_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &devkit8000_dvi_connector_pdata, }; +static struct encoder_tfp410_platform_data devkit8000_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, /* filled in code */ +}; -static struct omap_dss_device *devkit8000_dss_devices[] = { - &devkit8000_lcd_device, - &devkit8000_dvi_device, - &devkit8000_tv_device, +static struct platform_device devkit8000_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &devkit8000_tfp410_pdata, +}; + +static struct connector_atv_platform_data devkit8000_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device devkit8000_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &devkit8000_tv_pdata, }; static struct omap_dss_board_info devkit8000_dss_data = { - .num_devices = ARRAY_SIZE(devkit8000_dss_devices), - .devices = devkit8000_dss_devices, - .default_device = &devkit8000_lcd_device, + .default_display_name = "lcd", }; static uint32_t board_keymap[] = { @@ -204,11 +235,10 @@ static int devkit8000_twl_gpio_setup(struct device *dev, gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */ - lcd_panel.num_gpios = 1; - lcd_panel.gpios[0] = gpio + TWL4030_GPIO_MAX + 0; + devkit8000_lcd_pdata.enable_gpio = gpio + TWL4030_GPIO_MAX + 0; /* gpio + 7 is "DVI_PD" (out, active low) */ - dvi_panel.power_down_gpio = gpio + 7; + devkit8000_tfp410_pdata.power_down_gpio = gpio + 7; return 0; } @@ -413,6 +443,10 @@ static struct platform_device *devkit8000_devices[] __initdata = { &leds_gpio, &keys_gpio, &omap_dm9000_dev, + &devkit8000_lcd_device, + &devkit8000_tfp410_device, + &devkit8000_dvi_connector_device, + &devkit8000_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index be5d005ebad2..b89e55ba2c13 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -222,3 +222,21 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .dt_compat = am43_boards_compat, MACHINE_END #endif + +#ifdef CONFIG_SOC_DRA7XX +static const char *dra7xx_boards_compat[] __initdata = { + "ti,dra7", + NULL, +}; + +DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") + .reserve = omap_reserve, + .smp = smp_ops(omap4_smp_ops), + .map_io = omap5_map_io, + .init_early = dra7xx_init_early, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap5_realtime_timer_init, + .dt_compat = dra7xx_boards_compat, +MACHINE_END +#endif diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 69c0acf5aa63..87e41a8b8d46 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -194,30 +194,48 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -static struct platform_device *h4_devices[] __initdata = { - &h4_flash_device, +static const struct display_timing cm_t35_lcd_videomode = { + .pixelclock = { 0, 6250000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 15, 0 }, + .hback_porch = { 0, 60, 0 }, + .hsync_len = { 0, 15, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 1, 0 }, + .vback_porch = { 0, 1, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct panel_generic_dpi_data h4_panel_data = { - .name = "h4", +static struct panel_dpi_platform_data cm_t35_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &cm_t35_lcd_videomode, + + .enable_gpio = -1, + .backlight_gpio = -1, }; -static struct omap_dss_device h4_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &h4_panel_data, +static struct platform_device cm_t35_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &cm_t35_lcd_pdata, }; -static struct omap_dss_device *h4_dss_devices[] = { - &h4_lcd_device, +static struct platform_device *h4_devices[] __initdata = { + &h4_flash_device, + &cm_t35_lcd_device, }; static struct omap_dss_board_info h4_dss_data = { - .num_devices = ARRAY_SIZE(h4_dss_devices), - .devices = h4_dss_devices, - .default_device = &h4_lcd_device, + .default_display_name = "lcd", }; /* 2420 Sysboot setup (2430 is different) */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 87e65dde8e13..06dbb2d3d38b 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -429,31 +429,39 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { .setup = igep_twl_gpio_setup, }; -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = IGEP2_GPIO_DVI_PUP, +static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device igep2_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device omap3stalker_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3stalker_dvi_connector_pdata, }; -static struct omap_dss_device *igep2_dss_devices[] = { - &igep2_dvi_device +static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = IGEP2_GPIO_DVI_PUP, +}; + +static struct platform_device omap3stalker_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3stalker_tfp410_pdata, }; static struct omap_dss_board_info igep2_dss_data = { - .num_devices = ARRAY_SIZE(igep2_dss_devices), - .devices = igep2_dss_devices, - .default_device = &igep2_dvi_device, + .default_display_name = "dvi", }; static struct platform_device *igep_devices[] __initdata = { &igep_vwlan_device, + &omap3stalker_tfp410_device, + &omap3stalker_dvi_connector_device, }; static int igep2_keymap[] = { diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 62e4f701b63b..dd8da2c5399f 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -184,45 +184,70 @@ static inline void __init ldp_init_smsc911x(void) #define LCD_PANEL_RESET_GPIO 55 #define LCD_PANEL_QVGA_GPIO 56 -static struct panel_generic_dpi_data ldp_panel_data = { - .name = "nec_nl2432dr22-11b", - .num_gpios = 4, - /* gpios filled in code */ +static const struct display_timing ldp_lcd_videomode = { + .pixelclock = { 0, 5400000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 39, 0 }, + .hsync_len = { 0, 3, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 2, 0 }, + .vback_porch = { 0, 7, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device ldp_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 18, - .data = &ldp_panel_data, +static struct panel_dpi_platform_data ldp_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .display_timing = &ldp_lcd_videomode, + + .enable_gpio = -1, /* filled in code */ + .backlight_gpio = -1, /* filled in code */ }; -static struct omap_dss_device *ldp_dss_devices[] = { - &ldp_lcd_device, +static struct platform_device ldp_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &ldp_lcd_pdata, }; static struct omap_dss_board_info ldp_dss_data = { - .num_devices = ARRAY_SIZE(ldp_dss_devices), - .devices = ldp_dss_devices, - .default_device = &ldp_lcd_device, + .default_display_name = "lcd", }; static void __init ldp_display_init(void) { - ldp_panel_data.gpios[2] = LCD_PANEL_RESET_GPIO; - ldp_panel_data.gpios[3] = LCD_PANEL_QVGA_GPIO; + int r; + + static struct gpio gpios[] __initdata = { + {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"}, + {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"}, + }; + + r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (r) { + pr_err("Cannot request LCD GPIOs, error %d\n", r); + return; + } omap_display_init(&ldp_dss_data); } static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - ldp_panel_data.gpios[0] = gpio + 7; - ldp_panel_data.gpio_invert[0] = true; + /* LCD enable GPIO */ + ldp_lcd_pdata.enable_gpio = gpio + 7; - ldp_panel_data.gpios[1] = gpio + 15; - ldp_panel_data.gpio_invert[1] = true; + /* Backlight enable GPIO */ + ldp_lcd_pdata.backlight_gpio = gpio + 15; return 0; } @@ -322,6 +347,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { static struct platform_device *ldp_devices[] __initdata = { &ldp_gpio_keys_device, + &ldp_lcd_device, }; #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index f6eeb87e4e95..827d15009a86 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -122,11 +122,7 @@ static struct musb_hdrc_config musb_config = { }; static struct musb_hdrc_platform_data tusb_data = { -#ifdef CONFIG_USB_GADGET_MUSB_HDRC .mode = MUSB_OTG, -#else - .mode = MUSB_HOST, -#endif .set_power = tusb_set_power, .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */ .power = 100, /* Max 100 mA VBUS for host mode */ diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 04c116555412..f26918467efc 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,7 @@ #include <linux/mtd/nand.h> #include <linux/mmc/host.h> #include <linux/usb/phy.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -225,35 +225,46 @@ static struct mtd_partition omap3beagle_nand_partitions[] = { /* DSS */ -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = -1, +static struct connector_dvi_platform_data beagle_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device beagle_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device beagle_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &beagle_dvi_connector_pdata, }; -static struct omap_dss_device beagle_tv_device = { +static struct encoder_tfp410_platform_data beagle_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, +}; + +static struct platform_device beagle_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &beagle_tfp410_pdata, +}; + +static struct connector_atv_platform_data beagle_tv_pdata = { .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *beagle_dss_devices[] = { - &beagle_dvi_device, - &beagle_tv_device, +static struct platform_device beagle_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &beagle_tv_pdata, }; static struct omap_dss_board_info beagle_dss_data = { - .num_devices = ARRAY_SIZE(beagle_dss_devices), - .devices = beagle_dss_devices, - .default_device = &beagle_dvi_device, + .default_display_name = "dvi", }; #include "sdram-micron-mt46h32m32lf-6.h" @@ -279,7 +290,7 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = { static struct gpio_led gpio_leds[]; /* PHY's VCC regulator might be added later, so flag that we need it */ -static struct nop_usb_xceiv_platform_data hsusb2_phy_data = { +static struct usb_phy_gen_xceiv_platform_data hsusb2_phy_data = { .needs_vcc = true, }; @@ -332,7 +343,11 @@ static int beagle_twl_gpio_setup(struct device *dev, if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) pr_err("%s: unable to configure EHCI_nOC\n", __func__); } - dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio; + beagle_tfp410_pdata.power_down_gpio = beagle_config.dvi_pd_gpio; + + platform_device_register(&beagle_tfp410_device); + platform_device_register(&beagle_dvi_connector_device); + platform_device_register(&beagle_tv_connector_device); /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */ phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX; @@ -547,6 +562,7 @@ static void __init omap3_beagle_init(void) if (gpio_is_valid(beagle_config.dvi_pd_gpio)) omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT); omap_display_init(&beagle_dss_data); + omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 8c026269baca..18143873346c 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -33,7 +33,7 @@ #include <linux/i2c/twl.h> #include <linux/usb/otg.h> #include <linux/usb/musb.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include <linux/smsc911x.h> #include <linux/wl12xx.h> @@ -166,14 +166,6 @@ static inline void __init omap3evm_init_smsc911x(void) { return; } */ #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 -static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = { - .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, - .ini_gpio = OMAP3EVM_LCD_PANEL_INI, - .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, - .lr_gpio = OMAP3EVM_LCD_PANEL_LR, - .ud_gpio = OMAP3EVM_LCD_PANEL_UD, -}; - #ifdef CONFIG_BROKEN static void __init omap3_evm_display_init(void) { @@ -196,44 +188,65 @@ static void __init omap3_evm_display_init(void) } #endif -static struct omap_dss_device omap3_evm_lcd_device = { - .name = "lcd", - .driver_name = "sharp_ls_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 18, - .data = &omap3_evm_lcd_data, +static struct panel_sharp_ls037v7dw01_platform_data omap3_evm_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, + .ini_gpio = OMAP3EVM_LCD_PANEL_INI, + .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, + .lr_gpio = OMAP3EVM_LCD_PANEL_LR, + .ud_gpio = OMAP3EVM_LCD_PANEL_UD, +}; + +static struct platform_device omap3_evm_lcd_device = { + .name = "panel-sharp-ls037v7dw01", + .id = 0, + .dev.platform_data = &omap3_evm_lcd_pdata, +}; + +static struct connector_dvi_platform_data omap3_evm_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, +}; + +static struct platform_device omap3_evm_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3_evm_dvi_connector_pdata, }; -static struct omap_dss_device omap3_evm_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct encoder_tfp410_platform_data omap3_evm_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, - .i2c_bus_num = -1, +static struct platform_device omap3_evm_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3_evm_tfp410_pdata, }; -static struct omap_dss_device omap3_evm_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct connector_atv_platform_data omap3_evm_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *omap3_evm_dss_devices[] = { - &omap3_evm_lcd_device, - &omap3_evm_tv_device, - &omap3_evm_dvi_device, +static struct platform_device omap3_evm_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &omap3_evm_tv_pdata, }; static struct omap_dss_board_info omap3_evm_dss_data = { - .num_devices = ARRAY_SIZE(omap3_evm_dss_devices), - .devices = omap3_evm_dss_devices, - .default_device = &omap3_evm_lcd_device, + .default_display_name = "lcd", }; static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = { @@ -468,7 +481,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = { static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = { REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */ REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */ - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ REGULATOR_SUPPLY("vaux2", NULL), }; @@ -678,6 +691,10 @@ static void __init omap3_evm_init(void) omap3_evm_i2c_init(); omap_display_init(&omap3_evm_dss_data); + platform_device_register(&omap3_evm_lcd_device); + platform_device_register(&omap3_evm_tfp410_device); + platform_device_register(&omap3_evm_dvi_connector_device); + platform_device_register(&omap3_evm_tv_connector_device); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b1547a0edfcd..de1bc6bbe585 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -231,34 +231,21 @@ static struct twl4030_keypad_data pandora_kp_data = { .rep = 1, }; -static struct panel_tpo_td043_data lcd_data = { - .nreset_gpio = 157, -}; - -static struct omap_dss_device pandora_lcd_device = { - .name = "lcd", - .driver_name = "tpo_td043mtea1_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .data = &lcd_data, -}; - -static struct omap_dss_device pandora_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct connector_atv_platform_data pandora_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *pandora_dss_devices[] = { - &pandora_lcd_device, - &pandora_tv_device, +static struct platform_device pandora_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &pandora_tv_pdata, }; static struct omap_dss_board_info pandora_dss_data = { - .num_devices = ARRAY_SIZE(pandora_dss_devices), - .devices = pandora_dss_devices, - .default_device = &pandora_lcd_device, + .default_display_name = "lcd", }; static void pandora_wl1251_init_card(struct mmc_card *card) @@ -348,11 +335,11 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = { }; static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { - REGULATOR_SUPPLY("vcc", "display0"), + REGULATOR_SUPPLY("vcc", "spi1.1"), }; static struct regulator_consumer_supply pandora_usb_phy_supply[] = { - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ }; /* ads7846 on SPI and 2 nub controllers on I2C */ @@ -529,13 +516,21 @@ static int __init omap3pandora_i2c_init(void) return 0; } +static struct panel_tpo_td043mtea1_platform_data pandora_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 24, + .nreset_gpio = 157, +}; + static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { { - .modalias = "tpo_td043mtea1_panel_spi", + .modalias = "panel-tpo-td043mtea1", .bus_num = 1, .chip_select = 1, .max_speed_hz = 375000, - .platform_data = &pandora_lcd_device, + .platform_data = &pandora_lcd_pdata, } }; @@ -580,6 +575,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_keys_gpio, &pandora_vwlan_device, &pandora_backlight, + &pandora_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index d37e6b187ae4..ba8342fef799 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -93,40 +93,50 @@ static void __init omap3_stalker_display_init(void) { return; } +static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, +}; -static struct omap_dss_device omap3_stalker_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, -#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) - .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -#endif +static struct platform_device omap3stalker_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3stalker_dvi_connector_pdata, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = DSS_ENABLE_GPIO, - .i2c_bus_num = -1, +static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = DSS_ENABLE_GPIO, }; -static struct omap_dss_device omap3_stalker_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device omap3stalker_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3stalker_tfp410_pdata, +}; + +static struct connector_atv_platform_data omap3stalker_tv_pdata = { + .name = "tv", + .source = "venc.0", +#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, +#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) + .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, +#endif + .invert_polarity = false, }; -static struct omap_dss_device *omap3_stalker_dss_devices[] = { - &omap3_stalker_tv_device, - &omap3_stalker_dvi_device, +static struct platform_device omap3stalker_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &omap3stalker_tv_pdata, }; static struct omap_dss_board_info omap3_stalker_dss_data = { - .num_devices = ARRAY_SIZE(omap3_stalker_dss_devices), - .devices = omap3_stalker_dss_devices, - .default_device = &omap3_stalker_dvi_device, + .default_display_name = "dvi", }; static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = { @@ -356,6 +366,9 @@ static struct usbhs_phy_data phy_data[] __initdata = { static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, + &omap3stalker_tfp410_device, + &omap3stalker_dvi_connector_device, + &omap3stalker_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 5748b5d06c23..f6d384111911 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -72,6 +72,9 @@ #define OVERO_SMSC911X2_CS 4 #define OVERO_SMSC911X2_GPIO 65 +/* whether to register LCD35 instead of LCD43 */ +static bool overo_use_lcd35; + #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) @@ -149,78 +152,94 @@ static inline void __init overo_init_smsc911x(void) { return; } #define OVERO_GPIO_LCD_EN 144 #define OVERO_GPIO_LCD_BL 145 -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = -1, +static struct connector_atv_platform_data overo_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device overo_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device overo_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &overo_tv_pdata, }; -static struct omap_dss_device overo_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static const struct display_timing overo_lcd43_videomode = { + .pixelclock = { 0, 9200000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 8, 0 }, + .hback_porch = { 0, 4, 0 }, + .hsync_len = { 0, 41, 0 }, + + .vactive = { 0, 272, 0 }, + .vfront_porch = { 0, 4, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 10, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct panel_generic_dpi_data lcd43_panel = { - .name = "samsung_lte430wq_f0c", - .num_gpios = 2, - .gpios = { - OVERO_GPIO_LCD_EN, - OVERO_GPIO_LCD_BL - }, +static struct panel_dpi_platform_data overo_lcd43_pdata = { + .name = "lcd43", + .source = "dpi.0", + + .data_lines = 24, + + .display_timing = &overo_lcd43_videomode, + + .enable_gpio = OVERO_GPIO_LCD_EN, + .backlight_gpio = OVERO_GPIO_LCD_BL, }; -static struct omap_dss_device overo_lcd43_device = { - .name = "lcd43", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd43_panel, - .phy.dpi.data_lines = 24, +static struct platform_device overo_lcd43_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &overo_lcd43_pdata, }; -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -static struct panel_generic_dpi_data lcd35_panel = { - .num_gpios = 2, - .gpios = { - OVERO_GPIO_LCD_EN, - OVERO_GPIO_LCD_BL - }, +static struct connector_dvi_platform_data overo_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device overo_lcd35_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "lcd35", - .driver_name = "lgphilips_lb035q02_panel", - .phy.dpi.data_lines = 24, - .data = &lcd35_panel, +static struct platform_device overo_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &overo_dvi_connector_pdata, }; -#endif -static struct omap_dss_device *overo_dss_devices[] = { - &overo_dvi_device, - &overo_tv_device, -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) - &overo_lcd35_device, -#endif - &overo_lcd43_device, +static struct encoder_tfp410_platform_data overo_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, +}; + +static struct platform_device overo_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &overo_tfp410_pdata, }; static struct omap_dss_board_info overo_dss_data = { - .num_devices = ARRAY_SIZE(overo_dss_devices), - .devices = overo_dss_devices, - .default_device = &overo_dvi_device, + .default_display_name = "lcd43", }; +static void __init overo_display_init(void) +{ + omap_display_init(&overo_dss_data); + + if (!overo_use_lcd35) + platform_device_register(&overo_lcd43_device); + platform_device_register(&overo_tfp410_device); + platform_device_register(&overo_dvi_connector_device); + platform_device_register(&overo_tv_connector_device); +} + static struct mtd_partition overo_nand_partitions[] = { { .name = "xloader", @@ -408,24 +427,41 @@ static int __init overo_i2c_init(void) return 0; } +static struct panel_lb035q02_platform_data overo_lcd35_pdata = { + .name = "lcd35", + .source = "dpi.0", + + .data_lines = 24, + + .enable_gpio = OVERO_GPIO_LCD_EN, + .backlight_gpio = OVERO_GPIO_LCD_BL, +}; + +/* + * NOTE: We need to add either the lgphilips panel, or the lcd43 panel. The + * selection is done based on the overo_use_lcd35 field. If new SPI + * devices are added here, extra work is needed to make only the lgphilips panel + * affected by the overo_use_lcd35 field. + */ static struct spi_board_info overo_spi_board_info[] __initdata = { -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) { - .modalias = "lgphilips_lb035q02_panel-spi", + .modalias = "panel_lgphilips_lb035q02", .bus_num = 1, .chip_select = 1, .max_speed_hz = 500000, .mode = SPI_MODE_3, + .platform_data = &overo_lcd35_pdata, }, -#endif }; static int __init overo_spi_init(void) { overo_ads7846_init(); - spi_register_board_info(overo_spi_board_info, - ARRAY_SIZE(overo_spi_board_info)); + + if (overo_use_lcd35) { + spi_register_board_info(overo_spi_board_info, + ARRAY_SIZE(overo_spi_board_info)); + } return 0; } @@ -463,11 +499,13 @@ static void __init overo_init(void) { int ret; + if (strstr(boot_command_line, "omapdss.def_disp=lcd35")) + overo_use_lcd35 = true; + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); overo_i2c_init(); omap_hsmmc_init(mmc); - omap_display_init(&overo_dss_data); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); @@ -484,6 +522,8 @@ static void __init overo_init(void) overo_init_keys(); omap_twl4030_audio_init("overo", NULL); + overo_display_init(); + /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 9c2dd102fbbb..c3270c0f1fce 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -45,6 +45,8 @@ #include <linux/platform_data/tsl2563.h> #include <linux/lis3lv02d.h> +#include <video/omap-panel-data.h> + #if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE) #include <media/ir-rx51.h> #endif @@ -226,6 +228,15 @@ static struct lp55xx_platform_data rx51_lp5523_platform_data = { }; #endif +#define RX51_LCD_RESET_GPIO 90 + +static struct panel_acx565akm_platform_data acx_pdata = { + .name = "lcd", + .source = "sdi.0", + .reset_gpio = RX51_LCD_RESET_GPIO, + .datapairs = 2, +}; + static struct omap2_mcspi_device_config wl1251_mcspi_config = { .turbo_mode = 0, }; @@ -254,6 +265,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .chip_select = 2, .max_speed_hz = 6000000, .controller_data = &mipid_mcspi_config, + .platform_data = &acx_pdata, }, [RX51_SPI_TSC2005] = { .modalias = "tsc2005", diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index bdd1e3a179e1..43a90c8d6837 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -29,34 +29,21 @@ #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) -static struct panel_acx565akm_data lcd_data = { - .reset_gpio = RX51_LCD_RESET_GPIO, +static struct connector_atv_platform_data rx51_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, + .invert_polarity = false, }; -static struct omap_dss_device rx51_lcd_device = { - .name = "lcd", - .driver_name = "panel-acx565akm", - .type = OMAP_DISPLAY_TYPE_SDI, - .phy.sdi.datapairs = 2, - .data = &lcd_data, -}; - -static struct omap_dss_device rx51_tv_device = { - .name = "tv", - .type = OMAP_DISPLAY_TYPE_VENC, - .driver_name = "venc", - .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -}; - -static struct omap_dss_device *rx51_dss_devices[] = { - &rx51_lcd_device, - &rx51_tv_device, +static struct platform_device rx51_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &rx51_tv_pdata, }; static struct omap_dss_board_info rx51_dss_board_info = { - .num_devices = ARRAY_SIZE(rx51_dss_devices), - .devices = rx51_dss_devices, - .default_device = &rx51_lcd_device, + .default_display_name = "lcd", }; static int __init rx51_video_init(void) @@ -71,6 +58,8 @@ static int __init rx51_video_init(void) omap_display_init(&rx51_dss_board_info); + platform_device_register(&rx51_tv_connector_device); + return 0; } diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index d2ea68ea678a..7735105561d8 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -85,7 +85,7 @@ static struct omap_board_mux board_mux[] __initdata = { static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, - .mode = MUSB_PERIPHERAL, + .mode = MUSB_OTG, .power = 0, }; diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index c2a079cb76fc..3d8ecc1e05bd 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -25,32 +25,23 @@ #define LCD_PANEL_RESET_GPIO_PILOT 55 #define LCD_PANEL_QVGA_GPIO 56 -static struct panel_nec_nl8048_data zoom_lcd_data = { - /* res_gpio filled in code */ - .qvga_gpio = LCD_PANEL_QVGA_GPIO, -}; +static struct panel_nec_nl8048hl11_platform_data zoom_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", -static struct omap_dss_device zoom_lcd_device = { - .name = "lcd", - .driver_name = "NEC_8048_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .data = &zoom_lcd_data, -}; + .data_lines = 24, -static struct omap_dss_device *zoom_dss_devices[] = { - &zoom_lcd_device, + .res_gpio = -1, /* filled in code */ + .qvga_gpio = LCD_PANEL_QVGA_GPIO, }; static struct omap_dss_board_info zoom_dss_data = { - .num_devices = ARRAY_SIZE(zoom_dss_devices), - .devices = zoom_dss_devices, - .default_device = &zoom_lcd_device, + .default_display_name = "lcd", }; static void __init zoom_lcd_panel_init(void) { - zoom_lcd_data.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? + zoom_lcd_pdata.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? LCD_PANEL_RESET_GPIO_PROD : LCD_PANEL_RESET_GPIO_PILOT; } @@ -61,19 +52,20 @@ static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { static struct spi_board_info nec_8048_spi_board_info[] __initdata = { [0] = { - .modalias = "nec_8048_spi", + .modalias = "panel-nec-nl8048hl11", .bus_num = 1, .chip_select = 2, .max_speed_hz = 375000, .controller_data = &dss_lcd_mcspi_config, + .platform_data = &zoom_lcd_pdata, }, }; void __init zoom_display_init(void) { omap_display_init(&zoom_dss_data); + zoom_lcd_panel_init(); spi_register_board_info(nec_8048_spi_board_info, ARRAY_SIZE(nec_8048_spi_board_info)); - zoom_lcd_panel_init(); } diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 669ef51b17a8..8538669cc2ad 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -14,439 +14,121 @@ * published by the Free Software Foundation. */ -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ #define OMAP24XX_EN_CAM_SHIFT 31 -#define OMAP24XX_EN_CAM_MASK (1 << 31) #define OMAP24XX_EN_WDT4_SHIFT 29 -#define OMAP24XX_EN_WDT4_MASK (1 << 29) #define OMAP2420_EN_WDT3_SHIFT 28 -#define OMAP2420_EN_WDT3_MASK (1 << 28) #define OMAP24XX_EN_MSPRO_SHIFT 27 -#define OMAP24XX_EN_MSPRO_MASK (1 << 27) #define OMAP24XX_EN_FAC_SHIFT 25 -#define OMAP24XX_EN_FAC_MASK (1 << 25) #define OMAP2420_EN_EAC_SHIFT 24 -#define OMAP2420_EN_EAC_MASK (1 << 24) #define OMAP24XX_EN_HDQ_SHIFT 23 -#define OMAP24XX_EN_HDQ_MASK (1 << 23) #define OMAP2420_EN_I2C2_SHIFT 20 -#define OMAP2420_EN_I2C2_MASK (1 << 20) #define OMAP2420_EN_I2C1_SHIFT 19 -#define OMAP2420_EN_I2C1_MASK (1 << 19) - -/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ #define OMAP2430_EN_MCBSP5_SHIFT 5 -#define OMAP2430_EN_MCBSP5_MASK (1 << 5) #define OMAP2430_EN_MCBSP4_SHIFT 4 -#define OMAP2430_EN_MCBSP4_MASK (1 << 4) #define OMAP2430_EN_MCBSP3_SHIFT 3 -#define OMAP2430_EN_MCBSP3_MASK (1 << 3) #define OMAP24XX_EN_SSI_SHIFT 1 -#define OMAP24XX_EN_SSI_MASK (1 << 1) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ #define OMAP24XX_EN_MPU_WDT_SHIFT 3 -#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) - -/* Bits specific to each register */ - -/* CM_IDLEST_MPU */ -/* 2430 only */ -#define OMAP2430_ST_MPU_MASK (1 << 0) - -/* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 -#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_MPU_WIDTH 5 - -/* CM_CLKSTCTRL_MPU */ -#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits*/ #define OMAP24XX_EN_TV_SHIFT 2 -#define OMAP24XX_EN_TV_MASK (1 << 2) #define OMAP24XX_EN_DSS2_SHIFT 1 -#define OMAP24XX_EN_DSS2_MASK (1 << 1) #define OMAP24XX_EN_DSS1_SHIFT 0 #define OMAP24XX_EN_DSS1_MASK (1 << 0) - -/* CM_FCLKEN2_CORE specific bits */ #define OMAP2430_EN_I2CHS2_SHIFT 20 -#define OMAP2430_EN_I2CHS2_MASK (1 << 20) #define OMAP2430_EN_I2CHS1_SHIFT 19 -#define OMAP2430_EN_I2CHS1_MASK (1 << 19) #define OMAP2430_EN_MMCHSDB2_SHIFT 17 -#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) #define OMAP2430_EN_MMCHSDB1_SHIFT 16 -#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) - -/* CM_ICLKEN1_CORE specific bits */ #define OMAP24XX_EN_MAILBOXES_SHIFT 30 -#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_EN_DSS_SHIFT 0 -#define OMAP24XX_EN_DSS_MASK (1 << 0) - -/* CM_ICLKEN2_CORE specific bits */ - -/* CM_ICLKEN3_CORE */ -/* 2430 only */ #define OMAP2430_EN_SDRC_SHIFT 2 -#define OMAP2430_EN_SDRC_MASK (1 << 2) - -/* CM_ICLKEN4_CORE */ #define OMAP24XX_EN_PKA_SHIFT 4 -#define OMAP24XX_EN_PKA_MASK (1 << 4) #define OMAP24XX_EN_AES_SHIFT 3 -#define OMAP24XX_EN_AES_MASK (1 << 3) #define OMAP24XX_EN_RNG_SHIFT 2 -#define OMAP24XX_EN_RNG_MASK (1 << 2) #define OMAP24XX_EN_SHA_SHIFT 1 -#define OMAP24XX_EN_SHA_MASK (1 << 1) #define OMAP24XX_EN_DES_SHIFT 0 -#define OMAP24XX_EN_DES_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ #define OMAP24XX_ST_MAILBOXES_SHIFT 30 -#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_ST_WDT4_SHIFT 29 -#define OMAP24XX_ST_WDT4_MASK (1 << 29) -#define OMAP2420_ST_WDT3_SHIFT 28 -#define OMAP2420_ST_WDT3_MASK (1 << 28) -#define OMAP24XX_ST_MSPRO_SHIFT 27 -#define OMAP24XX_ST_MSPRO_MASK (1 << 27) -#define OMAP24XX_ST_FAC_SHIFT 25 -#define OMAP24XX_ST_FAC_MASK (1 << 25) -#define OMAP2420_ST_EAC_SHIFT 24 -#define OMAP2420_ST_EAC_MASK (1 << 24) #define OMAP24XX_ST_HDQ_SHIFT 23 -#define OMAP24XX_ST_HDQ_MASK (1 << 23) #define OMAP2420_ST_I2C2_SHIFT 20 -#define OMAP2420_ST_I2C2_MASK (1 << 20) #define OMAP2430_ST_I2CHS1_SHIFT 19 -#define OMAP2430_ST_I2CHS1_MASK (1 << 19) #define OMAP2420_ST_I2C1_SHIFT 19 -#define OMAP2420_ST_I2C1_MASK (1 << 19) #define OMAP2430_ST_I2CHS2_SHIFT 20 -#define OMAP2430_ST_I2CHS2_MASK (1 << 20) #define OMAP24XX_ST_MCBSP2_SHIFT 16 -#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) #define OMAP24XX_ST_MCBSP1_SHIFT 15 -#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) #define OMAP24XX_ST_DSS_SHIFT 0 -#define OMAP24XX_ST_DSS_MASK (1 << 0) - -/* CM_IDLEST2_CORE */ #define OMAP2430_ST_MCBSP5_SHIFT 5 -#define OMAP2430_ST_MCBSP5_MASK (1 << 5) #define OMAP2430_ST_MCBSP4_SHIFT 4 -#define OMAP2430_ST_MCBSP4_MASK (1 << 4) #define OMAP2430_ST_MCBSP3_SHIFT 3 -#define OMAP2430_ST_MCBSP3_MASK (1 << 3) -#define OMAP24XX_ST_SSI_SHIFT 1 -#define OMAP24XX_ST_SSI_MASK (1 << 1) - -/* CM_IDLEST3_CORE */ -/* 2430 only */ -#define OMAP2430_ST_SDRC_MASK (1 << 2) - -/* CM_IDLEST4_CORE */ -#define OMAP24XX_ST_PKA_SHIFT 4 -#define OMAP24XX_ST_PKA_MASK (1 << 4) #define OMAP24XX_ST_AES_SHIFT 3 -#define OMAP24XX_ST_AES_MASK (1 << 3) #define OMAP24XX_ST_RNG_SHIFT 2 -#define OMAP24XX_ST_RNG_MASK (1 << 2) #define OMAP24XX_ST_SHA_SHIFT 1 -#define OMAP24XX_ST_SHA_MASK (1 << 1) -#define OMAP24XX_ST_DES_SHIFT 0 -#define OMAP24XX_ST_DES_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP24XX_AUTO_CAM_MASK (1 << 31) -#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_AUTO_WDT4_MASK (1 << 29) -#define OMAP2420_AUTO_WDT3_MASK (1 << 28) -#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) -#define OMAP2420_AUTO_MMC_MASK (1 << 26) -#define OMAP24XX_AUTO_FAC_MASK (1 << 25) -#define OMAP2420_AUTO_EAC_MASK (1 << 24) -#define OMAP24XX_AUTO_HDQ_MASK (1 << 23) -#define OMAP24XX_AUTO_UART2_MASK (1 << 22) -#define OMAP24XX_AUTO_UART1_MASK (1 << 21) -#define OMAP24XX_AUTO_I2C2_MASK (1 << 20) -#define OMAP24XX_AUTO_I2C1_MASK (1 << 19) -#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) -#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) -#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) -#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) -#define OMAP24XX_AUTO_GPT12_MASK (1 << 14) -#define OMAP24XX_AUTO_GPT11_MASK (1 << 13) -#define OMAP24XX_AUTO_GPT10_MASK (1 << 12) -#define OMAP24XX_AUTO_GPT9_MASK (1 << 11) -#define OMAP24XX_AUTO_GPT8_MASK (1 << 10) -#define OMAP24XX_AUTO_GPT7_MASK (1 << 9) -#define OMAP24XX_AUTO_GPT6_MASK (1 << 8) -#define OMAP24XX_AUTO_GPT5_MASK (1 << 7) -#define OMAP24XX_AUTO_GPT4_MASK (1 << 6) -#define OMAP24XX_AUTO_GPT3_MASK (1 << 5) -#define OMAP24XX_AUTO_GPT2_MASK (1 << 4) -#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) -#define OMAP24XX_AUTO_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE2_CORE */ -#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) -#define OMAP2430_AUTO_GPIO5_MASK (1 << 10) -#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) -#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) -#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) -#define OMAP2430_AUTO_USBHS_MASK (1 << 6) -#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) -#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) -#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) -#define OMAP24XX_AUTO_UART3_MASK (1 << 2) -#define OMAP24XX_AUTO_SSI_MASK (1 << 1) -#define OMAP24XX_AUTO_USB_MASK (1 << 0) - -/* CM_AUTOIDLE3_CORE */ #define OMAP24XX_AUTO_SDRC_SHIFT 2 -#define OMAP24XX_AUTO_SDRC_MASK (1 << 2) #define OMAP24XX_AUTO_GPMC_SHIFT 1 -#define OMAP24XX_AUTO_GPMC_MASK (1 << 1) #define OMAP24XX_AUTO_SDMA_SHIFT 0 -#define OMAP24XX_AUTO_SDMA_MASK (1 << 0) - -/* CM_AUTOIDLE4_CORE */ -#define OMAP24XX_AUTO_PKA_MASK (1 << 4) -#define OMAP24XX_AUTO_AES_MASK (1 << 3) -#define OMAP24XX_AUTO_RNG_MASK (1 << 2) -#define OMAP24XX_AUTO_SHA_MASK (1 << 1) -#define OMAP24XX_AUTO_DES_MASK (1 << 0) - -/* CM_CLKSEL1_CORE */ -#define OMAP24XX_CLKSEL_USB_SHIFT 25 #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) -#define OMAP24XX_CLKSEL_SSI_SHIFT 20 #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) -#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) -#define OMAP24XX_CLKSEL_DSS2_SHIFT 13 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) -#define OMAP24XX_CLKSEL_DSS1_SHIFT 8 #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_L4_SHIFT 5 -#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) #define OMAP24XX_CLKSEL_L4_WIDTH 2 #define OMAP24XX_CLKSEL_L3_SHIFT 0 -#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_L3_WIDTH 5 - -/* CM_CLKSEL2_CORE */ -#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) -#define OMAP24XX_CLKSEL_GPT11_SHIFT 20 #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) -#define OMAP24XX_CLKSEL_GPT10_SHIFT 18 #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) -#define OMAP24XX_CLKSEL_GPT9_SHIFT 16 #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) -#define OMAP24XX_CLKSEL_GPT8_SHIFT 14 #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) -#define OMAP24XX_CLKSEL_GPT7_SHIFT 12 #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) -#define OMAP24XX_CLKSEL_GPT6_SHIFT 10 #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) -#define OMAP24XX_CLKSEL_GPT5_SHIFT 8 #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) -#define OMAP24XX_CLKSEL_GPT4_SHIFT 6 #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) -#define OMAP24XX_CLKSEL_GPT3_SHIFT 4 #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) -#define OMAP24XX_CLKSEL_GPT2_SHIFT 2 #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) - -/* CM_CLKSTCTRL_CORE */ -#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2 #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) -#define OMAP24XX_AUTOSTATE_L4_SHIFT 1 #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) -#define OMAP24XX_AUTOSTATE_L3_SHIFT 0 #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ #define OMAP24XX_EN_3D_SHIFT 2 -#define OMAP24XX_EN_3D_MASK (1 << 2) #define OMAP24XX_EN_2D_SHIFT 1 -#define OMAP24XX_EN_2D_MASK (1 << 1) - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ - -/* CM_ICLKEN_WKUP specific bits */ #define OMAP2430_EN_ICR_SHIFT 6 -#define OMAP2430_EN_ICR_MASK (1 << 6) #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 -#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) #define OMAP24XX_EN_WDT1_SHIFT 4 -#define OMAP24XX_EN_WDT1_MASK (1 << 4) #define OMAP24XX_EN_32KSYNC_SHIFT 1 -#define OMAP24XX_EN_32KSYNC_MASK (1 << 1) - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP2430_ST_ICR_SHIFT 6 -#define OMAP2430_ST_ICR_MASK (1 << 6) -#define OMAP24XX_ST_OMAPCTRL_SHIFT 5 -#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_ST_WDT1_SHIFT 4 -#define OMAP24XX_ST_WDT1_MASK (1 << 4) #define OMAP24XX_ST_MPU_WDT_SHIFT 3 -#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) #define OMAP24XX_ST_32KSYNC_SHIFT 1 -#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_AUTO_WDT1_MASK (1 << 4) -#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) -#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) -#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) -#define OMAP24XX_AUTO_GPT1_MASK (1 << 0) - -/* CM_CLKSEL_WKUP */ -#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) - -/* CM_CLKEN_PLL */ #define OMAP24XX_EN_54M_PLL_SHIFT 6 -#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) #define OMAP24XX_EN_96M_PLL_SHIFT 2 -#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) -#define OMAP24XX_EN_DPLL_SHIFT 0 #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) - -/* CM_IDLEST_CKGEN */ #define OMAP24XX_ST_54M_APLL_SHIFT 9 -#define OMAP24XX_ST_54M_APLL_MASK (1 << 9) #define OMAP24XX_ST_96M_APLL_SHIFT 8 -#define OMAP24XX_ST_96M_APLL_MASK (1 << 8) -#define OMAP24XX_ST_54M_CLK_MASK (1 << 6) -#define OMAP24XX_ST_12M_CLK_MASK (1 << 5) -#define OMAP24XX_ST_48M_CLK_MASK (1 << 4) -#define OMAP24XX_ST_96M_CLK_MASK (1 << 2) -#define OMAP24XX_ST_CORE_CLK_SHIFT 0 -#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP24XX_AUTO_54M_SHIFT 6 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) -#define OMAP24XX_AUTO_96M_SHIFT 2 #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) - -/* CM_CLKSEL1_PLL */ -#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 -#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) #define OMAP24XX_APLLS_CLKIN_SHIFT 23 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) -#define OMAP24XX_DPLL_MULT_SHIFT 12 #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) -#define OMAP24XX_DPLL_DIV_SHIFT 8 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 -#define OMAP24XX_54M_SOURCE_MASK (1 << 5) #define OMAP24XX_54M_SOURCE_WIDTH 1 #define OMAP2430_96M_SOURCE_SHIFT 4 -#define OMAP2430_96M_SOURCE_MASK (1 << 4) #define OMAP2430_96M_SOURCE_WIDTH 1 -#define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_MASK (1 << 3) -#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 -#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) - -/* CM_CLKSEL2_PLL */ -#define OMAP24XX_CORE_CLK_SRC_SHIFT 0 #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) - -/* CM_FCLKEN_DSP */ #define OMAP2420_EN_IVA_COP_SHIFT 10 -#define OMAP2420_EN_IVA_COP_MASK (1 << 10) #define OMAP2420_EN_IVA_MPU_SHIFT 8 -#define OMAP2420_EN_IVA_MPU_MASK (1 << 8) #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 -#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) - -/* CM_ICLKEN_DSP */ #define OMAP2420_EN_DSP_IPI_SHIFT 1 -#define OMAP2420_EN_DSP_IPI_MASK (1 << 1) - -/* CM_IDLEST_DSP */ -#define OMAP2420_ST_IVA_MASK (1 << 8) -#define OMAP2420_ST_IPI_MASK (1 << 1) -#define OMAP24XX_ST_DSP_MASK (1 << 0) - -/* CM_AUTOIDLE_DSP */ -#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) - -/* CM_CLKSEL_DSP */ -#define OMAP2420_SYNC_IVA_MASK (1 << 13) -#define OMAP2420_CLKSEL_IVA_SHIFT 8 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) -#define OMAP24XX_SYNC_DSP_MASK (1 << 7) -#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) -#define OMAP24XX_CLKSEL_DSP_SHIFT 0 #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) - -/* CM_CLKSTCTRL_DSP */ -#define OMAP2420_AUTOSTATE_IVA_SHIFT 8 #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) -#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0 #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) - -/* CM_FCLKEN_MDM */ -/* 2430 only */ #define OMAP2430_EN_OSC_SHIFT 1 -#define OMAP2430_EN_OSC_MASK (1 << 1) - -/* CM_ICLKEN_MDM */ -/* 2430 only */ #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 -#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) - -/* CM_IDLEST_MDM specific bits */ -/* 2430 only */ - -/* CM_AUTOIDLE_MDM */ -/* 2430 only */ -#define OMAP2430_AUTO_OSC_MASK (1 << 1) -#define OMAP2430_AUTO_MDM_MASK (1 << 0) - -/* CM_CLKSEL_MDM */ -/* 2430 only */ -#define OMAP2430_SYNC_MDM_MASK (1 << 4) -#define OMAP2430_CLKSEL_MDM_SHIFT 0 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) - -/* CM_CLKSTCTRL_MDM */ -/* 2430 only */ -#define OMAP2430_AUTOSTATE_MDM_SHIFT 0 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) - -/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 - - #endif diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index adf7bb79b18f..c0823fd6d5e0 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -20,798 +20,49 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H -/* - * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, - * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER - */ -#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 -#define AM33XX_AUTO_DPLL_MODE_WIDTH 3 -#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) - -/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_CPSW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 -#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3S_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4FW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) - -/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) - -/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) - -/* Used by CM_MPU_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 -#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2DIV_SHIFT 3 #define AM33XX_CLKOUT2DIV_WIDTH 3 -#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2EN_SHIFT 7 -#define AM33XX_CLKOUT2EN_WIDTH 1 -#define AM33XX_CLKOUT2EN_MASK (1 << 7) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_WIDTH 3 #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) - -/* - * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, - * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, - * CLKSEL_TIMER7_CLK - */ -#define AM33XX_CLKSEL_SHIFT 0 -#define AM33XX_CLKSEL_WIDTH 1 -#define AM33XX_CLKSEL_MASK (0x01 << 0) - -/* - * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, - * CM_CPTS_RFT_CLKSEL - */ #define AM33XX_CLKSEL_0_0_SHIFT 0 #define AM33XX_CLKSEL_0_0_WIDTH 1 #define AM33XX_CLKSEL_0_0_MASK (1 << 0) - -#define AM33XX_CLKSEL_0_1_SHIFT 0 -#define AM33XX_CLKSEL_0_1_WIDTH 2 #define AM33XX_CLKSEL_0_1_MASK (3 << 0) - -/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ -#define AM33XX_CLKSEL_0_2_SHIFT 0 -#define AM33XX_CLKSEL_0_2_WIDTH 3 #define AM33XX_CLKSEL_0_2_MASK (7 << 0) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 -#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) - -/* - * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, - * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, - * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, - * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, - * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, - * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL - */ #define AM33XX_CLKTRCTRL_SHIFT 0 -#define AM33XX_CLKTRCTRL_WIDTH 2 #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, - * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER - */ -#define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_WIDTH 20 -#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) - -/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ -#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 -#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 -#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_DIV_SHIFT 0 -#define AM33XX_DPLL_DIV_WIDTH 7 #define AM33XX_DPLL_DIV_MASK (0x7f << 0) - #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_WIDTH 8 -#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 -#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_EN_SHIFT 0 -#define AM33XX_DPLL_EN_WIDTH 3 #define AM33XX_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 -#define AM33XX_DPLL_LPMODE_EN_WIDTH 1 -#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_MULT_SHIFT 8 -#define AM33XX_DPLL_MULT_WIDTH 11 #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 -#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_REGM4XEN_SHIFT 11 -#define AM33XX_DPLL_REGM4XEN_WIDTH 1 -#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_WIDTH 8 -#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_ACK_SHIFT 13 -#define AM33XX_DPLL_SSC_ACK_WIDTH 1 -#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 -#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_EN_SHIFT 12 -#define AM33XX_DPLL_SSC_EN_WIDTH 1 -#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL - */ #define AM33XX_IDLEST_SHIFT 16 -#define AM33XX_IDLEST_WIDTH 2 #define AM33XX_IDLEST_MASK (0x3 << 16) - -/* Used by CM_MAC_CLKSEL */ -#define AM33XX_MII_CLK_SEL_SHIFT 2 -#define AM33XX_MII_CLK_SEL_WIDTH 1 -#define AM33XX_MII_CLK_SEL_MASK (1 << 2) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, - * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, - * CM_CEFUSE_CEFUSE_CLKCTRL - */ #define AM33XX_MODULEMODE_SHIFT 0 -#define AM33XX_MODULEMODE_WIDTH 2 #define AM33XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 -#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 -#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) - -/* Used by CM_WKUP_GPIO0_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO1_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO2_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO3_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO4_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO5_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO6_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, - * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, - * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, - * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL - */ -#define AM33XX_STBYST_SHIFT 18 -#define AM33XX_STBYST_WIDTH 1 -#define AM33XX_STBYST_MASK (1 << 18) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLK_SHIFT 0 -#define AM33XX_ST_DPLL_CLK_WIDTH 1 #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 -#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 -#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 -#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 -#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_MN_BYPASS_SHIFT 8 -#define AM33XX_ST_MN_BYPASS_WIDTH 1 -#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) - -/* Used by CONTROL_SEC_CLK_CTRL */ -#define AM33XX_TIMER0_CLKSEL_WIDTH 2 -#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index adf78d325804..04dab2fcf862 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -14,833 +14,201 @@ * published by the Free Software Foundation. */ -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ -#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) #define OMAP3430ES2_EN_MMC3_SHIFT 30 -#define OMAP3430_EN_MSPRO_MASK (1 << 23) #define OMAP3430_EN_MSPRO_SHIFT 23 -#define OMAP3430_EN_HDQ_MASK (1 << 22) #define OMAP3430_EN_HDQ_SHIFT 22 -#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430ES1_EN_D2D_MASK (1 << 3) #define OMAP3430ES1_EN_D2D_SHIFT 3 -#define OMAP3430_EN_SSI_MASK (1 << 0) #define OMAP3430_EN_SSI_SHIFT 0 - -/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ #define OMAP3430ES2_EN_USBTLL_SHIFT 2 -#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ -#define OMAP3430_EN_WDT2_MASK (1 << 5) #define OMAP3430_EN_WDT2_SHIFT 5 - -/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ -#define OMAP3430_EN_CAM_MASK (1 << 0) #define OMAP3430_EN_CAM_SHIFT 0 - -/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ -#define OMAP3430_EN_WDT3_MASK (1 << 12) #define OMAP3430_EN_WDT3_SHIFT 12 - -/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ -#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) - - -/* Bits specific to each register */ - -/* CM_FCLKEN_IVA2 */ #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 - -/* CM_CLKEN_PLL_IVA2 */ -#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_IVA2_DPLL_SHIFT 0 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_IVA2 */ #define OMAP3430_ST_IVA2_SHIFT 0 -#define OMAP3430_ST_IVA2_MASK (1 << 0) - -/* CM_IDLEST_PLL_IVA2 */ -#define OMAP3430_ST_IVA2_CLK_SHIFT 0 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL_IVA2 */ -#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 -#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_IVA2 */ #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 - -/* CM_CLKSTCTRL_IVA2 */ -#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) - -/* CM_CLKSTST_IVA2 */ -#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) - -/* CM_REVISION specific bits */ - -/* CM_SYSCONFIG specific bits */ - -/* CM_CLKEN_PLL_MPU */ -#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_MPU_DPLL_SHIFT 0 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_MPU */ -#define OMAP3430_ST_MPU_MASK (1 << 0) - -/* CM_IDLEST_PLL_MPU */ #define OMAP3430_ST_MPU_CLK_SHIFT 0 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) #define OMAP3430_ST_MPU_CLK_WIDTH 1 - -/* CM_AUTOIDLE_PLL_MPU */ -#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_CLK_SRC_WIDTH 3 -#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_MPU */ #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 - -/* CM_CLKSTCTRL_MPU */ -#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) - -/* CM_CLKSTST_MPU */ -#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits */ -#define OMAP3430_EN_MODEM_MASK (1 << 31) #define OMAP3430_EN_MODEM_SHIFT 31 - -/* CM_ICLKEN1_CORE specific bits */ -#define OMAP3430_EN_ICR_MASK (1 << 29) #define OMAP3430_EN_ICR_SHIFT 29 -#define OMAP3430_EN_AES2_MASK (1 << 28) #define OMAP3430_EN_AES2_SHIFT 28 -#define OMAP3430_EN_SHA12_MASK (1 << 27) #define OMAP3430_EN_SHA12_SHIFT 27 -#define OMAP3430_EN_DES2_MASK (1 << 26) #define OMAP3430_EN_DES2_SHIFT 26 -#define OMAP3430ES1_EN_FAC_MASK (1 << 8) #define OMAP3430ES1_EN_FAC_SHIFT 8 -#define OMAP3430_EN_MAILBOXES_MASK (1 << 7) #define OMAP3430_EN_MAILBOXES_SHIFT 7 -#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) #define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D_MASK (1 << 3) #define OMAP3430_EN_SAD2D_SHIFT 3 -#define OMAP3430_EN_SDRC_MASK (1 << 1) #define OMAP3430_EN_SDRC_SHIFT 1 - -/* AM35XX specific CM_ICLKEN1_CORE bits */ -#define AM35XX_EN_IPSS_MASK (1 << 4) #define AM35XX_EN_IPSS_SHIFT 4 - -/* CM_ICLKEN2_CORE */ -#define OMAP3430_EN_PKA_MASK (1 << 4) #define OMAP3430_EN_PKA_SHIFT 4 -#define OMAP3430_EN_AES1_MASK (1 << 3) #define OMAP3430_EN_AES1_SHIFT 3 -#define OMAP3430_EN_RNG_MASK (1 << 2) #define OMAP3430_EN_RNG_SHIFT 2 -#define OMAP3430_EN_SHA11_MASK (1 << 1) #define OMAP3430_EN_SHA11_SHIFT 1 -#define OMAP3430_EN_DES1_MASK (1 << 0) #define OMAP3430_EN_DES1_SHIFT 0 - -/* CM_ICLKEN3_CORE */ #define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430_EN_MAD2D_MASK (1 << 3) - -/* CM_FCLKEN3_CORE specific bits */ #define OMAP3430ES2_EN_TS_SHIFT 1 -#define OMAP3430ES2_EN_TS_MASK (1 << 1) #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ -#define OMAP3430ES2_ST_MMC3_SHIFT 30 -#define OMAP3430ES2_ST_MMC3_MASK (1 << 30) -#define OMAP3430_ST_ICR_SHIFT 29 -#define OMAP3430_ST_ICR_MASK (1 << 29) #define OMAP3430_ST_AES2_SHIFT 28 -#define OMAP3430_ST_AES2_MASK (1 << 28) #define OMAP3430_ST_SHA12_SHIFT 27 -#define OMAP3430_ST_SHA12_MASK (1 << 27) -#define OMAP3430_ST_DES2_SHIFT 26 -#define OMAP3430_ST_DES2_MASK (1 << 26) -#define OMAP3430_ST_MSPRO_SHIFT 23 -#define OMAP3430_ST_MSPRO_MASK (1 << 23) #define AM35XX_ST_UART4_SHIFT 23 -#define AM35XX_ST_UART4_MASK (1 << 23) #define OMAP3430_ST_HDQ_SHIFT 22 -#define OMAP3430_ST_HDQ_MASK (1 << 22) -#define OMAP3430ES1_ST_FAC_SHIFT 8 -#define OMAP3430ES1_ST_FAC_MASK (1 << 8) #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 -#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) #define OMAP3430_ST_MAILBOXES_SHIFT 7 -#define OMAP3430_ST_MAILBOXES_MASK (1 << 7) -#define OMAP3430_ST_OMAPCTRL_SHIFT 6 -#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) #define OMAP3430_ST_SAD2D_SHIFT 3 -#define OMAP3430_ST_SAD2D_MASK (1 << 3) #define OMAP3430_ST_SDMA_SHIFT 2 -#define OMAP3430_ST_SDMA_MASK (1 << 2) -#define OMAP3430_ST_SDRC_SHIFT 1 -#define OMAP3430_ST_SDRC_MASK (1 << 1) -#define OMAP3430_ST_SSI_STDBY_SHIFT 0 -#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) - -/* AM35xx specific CM_IDLEST1_CORE bits */ #define AM35XX_ST_IPSS_SHIFT 5 -#define AM35XX_ST_IPSS_MASK (1 << 5) - -/* CM_IDLEST2_CORE */ -#define OMAP3430_ST_PKA_SHIFT 4 -#define OMAP3430_ST_PKA_MASK (1 << 4) -#define OMAP3430_ST_AES1_SHIFT 3 -#define OMAP3430_ST_AES1_MASK (1 << 3) -#define OMAP3430_ST_RNG_SHIFT 2 -#define OMAP3430_ST_RNG_MASK (1 << 2) -#define OMAP3430_ST_SHA11_SHIFT 1 -#define OMAP3430_ST_SHA11_MASK (1 << 1) -#define OMAP3430_ST_DES1_SHIFT 0 -#define OMAP3430_ST_DES1_MASK (1 << 0) - -/* CM_IDLEST3_CORE */ #define OMAP3430ES2_ST_USBTLL_SHIFT 2 -#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) -#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP3430_AUTO_MODEM_MASK (1 << 31) -#define OMAP3430_AUTO_MODEM_SHIFT 31 -#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) -#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 -#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) -#define OMAP3430ES2_AUTO_ICR_SHIFT 29 -#define OMAP3430_AUTO_AES2_MASK (1 << 28) -#define OMAP3430_AUTO_AES2_SHIFT 28 -#define OMAP3430_AUTO_SHA12_MASK (1 << 27) -#define OMAP3430_AUTO_SHA12_SHIFT 27 -#define OMAP3430_AUTO_DES2_MASK (1 << 26) -#define OMAP3430_AUTO_DES2_SHIFT 26 -#define OMAP3430_AUTO_MMC2_MASK (1 << 25) -#define OMAP3430_AUTO_MMC2_SHIFT 25 -#define OMAP3430_AUTO_MMC1_MASK (1 << 24) -#define OMAP3430_AUTO_MMC1_SHIFT 24 -#define OMAP3430_AUTO_MSPRO_MASK (1 << 23) -#define OMAP3430_AUTO_MSPRO_SHIFT 23 -#define OMAP3430_AUTO_HDQ_MASK (1 << 22) -#define OMAP3430_AUTO_HDQ_SHIFT 22 -#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) -#define OMAP3430_AUTO_MCSPI4_SHIFT 21 -#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) -#define OMAP3430_AUTO_MCSPI3_SHIFT 20 -#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) -#define OMAP3430_AUTO_MCSPI2_SHIFT 19 -#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) -#define OMAP3430_AUTO_MCSPI1_SHIFT 18 -#define OMAP3430_AUTO_I2C3_MASK (1 << 17) -#define OMAP3430_AUTO_I2C3_SHIFT 17 -#define OMAP3430_AUTO_I2C2_MASK (1 << 16) -#define OMAP3430_AUTO_I2C2_SHIFT 16 -#define OMAP3430_AUTO_I2C1_MASK (1 << 15) -#define OMAP3430_AUTO_I2C1_SHIFT 15 -#define OMAP3430_AUTO_UART2_MASK (1 << 14) -#define OMAP3430_AUTO_UART2_SHIFT 14 -#define OMAP3430_AUTO_UART1_MASK (1 << 13) -#define OMAP3430_AUTO_UART1_SHIFT 13 -#define OMAP3430_AUTO_GPT11_MASK (1 << 12) -#define OMAP3430_AUTO_GPT11_SHIFT 12 -#define OMAP3430_AUTO_GPT10_MASK (1 << 11) -#define OMAP3430_AUTO_GPT10_SHIFT 11 -#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) -#define OMAP3430_AUTO_MCBSP5_SHIFT 10 -#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) -#define OMAP3430_AUTO_MCBSP1_SHIFT 9 -#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) -#define OMAP3430ES1_AUTO_FAC_SHIFT 8 -#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) -#define OMAP3430_AUTO_MAILBOXES_SHIFT 7 -#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) -#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 -#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) -#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 -#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) -#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 -#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) -#define OMAP3430ES1_AUTO_D2D_SHIFT 3 -#define OMAP3430_AUTO_SAD2D_MASK (1 << 3) -#define OMAP3430_AUTO_SAD2D_SHIFT 3 -#define OMAP3430_AUTO_SSI_MASK (1 << 0) -#define OMAP3430_AUTO_SSI_SHIFT 0 - -/* CM_AUTOIDLE2_CORE */ -#define OMAP3430_AUTO_PKA_MASK (1 << 4) -#define OMAP3430_AUTO_PKA_SHIFT 4 -#define OMAP3430_AUTO_AES1_MASK (1 << 3) -#define OMAP3430_AUTO_AES1_SHIFT 3 -#define OMAP3430_AUTO_RNG_MASK (1 << 2) -#define OMAP3430_AUTO_RNG_SHIFT 2 -#define OMAP3430_AUTO_SHA11_MASK (1 << 1) -#define OMAP3430_AUTO_SHA11_SHIFT 1 -#define OMAP3430_AUTO_DES1_MASK (1 << 0) -#define OMAP3430_AUTO_DES1_SHIFT 0 - -/* CM_AUTOIDLE3_CORE */ -#define OMAP3430ES2_AUTO_USBHOST (1 << 0) -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBTLL (1 << 2) -#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 -#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) -#define OMAP3430_AUTO_MAD2D_SHIFT 3 -#define OMAP3430_AUTO_MAD2D_MASK (1 << 3) - -/* CM_CLKSEL_CORE */ -#define OMAP3430_CLKSEL_SSI_SHIFT 8 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT11_SHIFT 7 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT10_SHIFT 6 -#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) #define OMAP3430_CLKSEL_L4_SHIFT 2 -#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) #define OMAP3430_CLKSEL_L4_WIDTH 2 #define OMAP3430_CLKSEL_L3_SHIFT 0 -#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) #define OMAP3430_CLKSEL_L3_WIDTH 2 -#define OMAP3630_CLKSEL_96M_SHIFT 12 #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) -#define OMAP3630_CLKSEL_96M_WIDTH 2 - -/* CM_CLKSTCTRL_CORE */ -#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) -#define OMAP3430_CLKTRCTRL_L4_SHIFT 2 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) -#define OMAP3430_CLKTRCTRL_L3_SHIFT 0 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) - -/* CM_CLKSTST_CORE */ -#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 -#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) -#define OMAP3430_CLKACTIVITY_L4_SHIFT 1 -#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) -#define OMAP3430_CLKACTIVITY_L3_SHIFT 0 -#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ -#define OMAP3430ES1_EN_3D_MASK (1 << 2) #define OMAP3430ES1_EN_3D_SHIFT 2 -#define OMAP3430ES1_EN_2D_MASK (1 << 1) #define OMAP3430ES1_EN_2D_SHIFT 1 - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_SLEEPDEP_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) - -/* CM_CLKSTST_GFX */ -#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 -#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) - -/* CM_FCLKEN_SGX */ #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 -#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) - -/* CM_IDLEST_SGX */ -#define OMAP3430ES2_ST_SGX_SHIFT 1 -#define OMAP3430ES2_ST_SGX_MASK (1 << 1) - -/* CM_ICLKEN_SGX */ #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 -#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) - -/* CM_CLKSEL_SGX */ -#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) - -/* CM_CLKSTCTRL_SGX */ -#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) - -/* CM_CLKSTST_SGX */ -#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 -#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) - -/* CM_ICLKEN_WKUP specific bits */ -#define OMAP3430_EN_WDT1_MASK (1 << 4) #define OMAP3430_EN_WDT1_SHIFT 4 -#define OMAP3430_EN_32KSYNC_MASK (1 << 2) #define OMAP3430_EN_32KSYNC_SHIFT 2 - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP3430ES2_ST_USIMOCP_SHIFT 9 -#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) #define OMAP3430_ST_WDT2_SHIFT 5 -#define OMAP3430_ST_WDT2_MASK (1 << 5) -#define OMAP3430_ST_WDT1_SHIFT 4 -#define OMAP3430_ST_WDT1_MASK (1 << 4) #define OMAP3430_ST_32KSYNC_SHIFT 2 -#define OMAP3430_ST_32KSYNC_MASK (1 << 2) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) -#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 -#define OMAP3430_AUTO_WDT2_MASK (1 << 5) -#define OMAP3430_AUTO_WDT2_SHIFT 5 -#define OMAP3430_AUTO_WDT1_MASK (1 << 4) -#define OMAP3430_AUTO_WDT1_SHIFT 4 -#define OMAP3430_AUTO_GPIO1_MASK (1 << 3) -#define OMAP3430_AUTO_GPIO1_SHIFT 3 -#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) -#define OMAP3430_AUTO_32KSYNC_SHIFT 2 -#define OMAP3430_AUTO_GPT12_MASK (1 << 1) -#define OMAP3430_AUTO_GPT12_SHIFT 1 -#define OMAP3430_AUTO_GPT1_MASK (1 << 0) -#define OMAP3430_AUTO_GPT1_SHIFT 0 - -/* CM_CLKSEL_WKUP */ #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) #define OMAP3430_CLKSEL_RM_SHIFT 1 -#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) #define OMAP3430_CLKSEL_RM_WIDTH 2 -#define OMAP3430_CLKSEL_GPT1_SHIFT 0 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) - -/* CM_CLKEN_PLL */ #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 #define OMAP3430_PWRDN_CAM_SHIFT 30 #define OMAP3430_PWRDN_DSS1_SHIFT 29 #define OMAP3430_PWRDN_TV_SHIFT 28 #define OMAP3430_PWRDN_96M_SHIFT 27 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) -#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 -#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) -#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 -#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_CORE_DPLL_SHIFT 0 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) - -/* CM_CLKEN2_PLL */ -#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 -#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_CKGEN */ -#define OMAP3430_ST_54M_CLK_MASK (1 << 5) -#define OMAP3430_ST_12M_CLK_MASK (1 << 4) -#define OMAP3430_ST_48M_CLK_MASK (1 << 3) -#define OMAP3430_ST_96M_CLK_MASK (1 << 2) -#define OMAP3430_ST_PERIPH_CLK_SHIFT 1 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) -#define OMAP3430_ST_CORE_CLK_SHIFT 0 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) - -/* CM_IDLEST2_CKGEN */ -#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 -#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) -#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 -#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) -#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) - -/* CM_AUTOIDLE2_PLL */ -#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL */ -/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 -#define OMAP3430_CORE_DPLL_MULT_SHIFT 16 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) #define OMAP3430_SOURCE_96M_SHIFT 6 -#define OMAP3430_SOURCE_96M_MASK (1 << 6) #define OMAP3430_SOURCE_96M_WIDTH 1 #define OMAP3430_SOURCE_54M_SHIFT 5 -#define OMAP3430_SOURCE_54M_MASK (1 << 5) #define OMAP3430_SOURCE_54M_WIDTH 1 -#define OMAP3430_SOURCE_48M_SHIFT 3 #define OMAP3430_SOURCE_48M_MASK (1 << 3) - -/* CM_CLKSEL2_PLL */ -#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) -#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) - -/* CM_CLKSEL3_PLL */ #define OMAP3430_DIV_96M_SHIFT 0 -#define OMAP3430_DIV_96M_MASK (0x1f << 0) -#define OMAP3430_DIV_96M_WIDTH 5 -#define OMAP3630_DIV_96M_MASK (0x3f << 0) #define OMAP3630_DIV_96M_WIDTH 6 - -/* CM_CLKSEL4_PLL */ -#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL5_PLL */ #define OMAP3430ES2_DIV_120M_SHIFT 0 -#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) #define OMAP3430ES2_DIV_120M_WIDTH 5 - -/* CM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT2_EN_SHIFT 7 -#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) #define OMAP3430_CLKOUT2_DIV_SHIFT 3 -#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) #define OMAP3430_CLKOUT2_DIV_WIDTH 3 -#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) - -/* CM_FCLKEN_DSS */ -#define OMAP3430_EN_TV_MASK (1 << 2) #define OMAP3430_EN_TV_SHIFT 2 -#define OMAP3430_EN_DSS2_MASK (1 << 1) #define OMAP3430_EN_DSS2_SHIFT 1 -#define OMAP3430_EN_DSS1_MASK (1 << 0) #define OMAP3430_EN_DSS1_SHIFT 0 - -/* CM_ICLKEN_DSS */ -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 - -/* CM_IDLEST_DSS */ #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) #define OMAP3430ES1_ST_DSS_SHIFT 0 -#define OMAP3430ES1_ST_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE_DSS */ -#define OMAP3430_AUTO_DSS_MASK (1 << 0) -#define OMAP3430_AUTO_DSS_SHIFT 0 - -/* CM_CLKSEL_DSS */ #define OMAP3430_CLKSEL_TV_SHIFT 8 -#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) -#define OMAP3430_CLKSEL_TV_WIDTH 5 -#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) #define OMAP3630_CLKSEL_TV_WIDTH 6 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 -#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) -#define OMAP3430_CLKSEL_DSS1_WIDTH 5 -#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) #define OMAP3630_CLKSEL_DSS1_WIDTH 6 - -/* CM_SLEEPDEP_DSS specific bits */ - -/* CM_CLKSTCTRL_DSS */ -#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) - -/* CM_CLKSTST_DSS */ -#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 -#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) - -/* CM_FCLKEN_CAM specific bits */ -#define OMAP3430_EN_CSI2_MASK (1 << 1) #define OMAP3430_EN_CSI2_SHIFT 1 - -/* CM_ICLKEN_CAM specific bits */ - -/* CM_IDLEST_CAM */ -#define OMAP3430_ST_CAM_MASK (1 << 0) - -/* CM_AUTOIDLE_CAM */ -#define OMAP3430_AUTO_CAM_MASK (1 << 0) -#define OMAP3430_AUTO_CAM_SHIFT 0 - -/* CM_CLKSEL_CAM */ #define OMAP3430_CLKSEL_CAM_SHIFT 0 -#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) -#define OMAP3430_CLKSEL_CAM_WIDTH 5 -#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) #define OMAP3630_CLKSEL_CAM_WIDTH 6 - -/* CM_SLEEPDEP_CAM specific bits */ - -/* CM_CLKSTCTRL_CAM */ -#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) - -/* CM_CLKSTST_CAM */ -#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 -#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) - -/* CM_FCLKEN_PER specific bits */ - -/* CM_ICLKEN_PER specific bits */ - -/* CM_IDLEST_PER */ -#define OMAP3430_ST_WDT3_SHIFT 12 -#define OMAP3430_ST_WDT3_MASK (1 << 12) #define OMAP3430_ST_MCBSP4_SHIFT 2 -#define OMAP3430_ST_MCBSP4_MASK (1 << 2) #define OMAP3430_ST_MCBSP3_SHIFT 1 -#define OMAP3430_ST_MCBSP3_MASK (1 << 1) #define OMAP3430_ST_MCBSP2_SHIFT 0 -#define OMAP3430_ST_MCBSP2_MASK (1 << 0) - -/* CM_AUTOIDLE_PER */ -#define OMAP3630_AUTO_UART4_MASK (1 << 18) -#define OMAP3630_AUTO_UART4_SHIFT 18 -#define OMAP3430_AUTO_GPIO6_MASK (1 << 17) -#define OMAP3430_AUTO_GPIO6_SHIFT 17 -#define OMAP3430_AUTO_GPIO5_MASK (1 << 16) -#define OMAP3430_AUTO_GPIO5_SHIFT 16 -#define OMAP3430_AUTO_GPIO4_MASK (1 << 15) -#define OMAP3430_AUTO_GPIO4_SHIFT 15 -#define OMAP3430_AUTO_GPIO3_MASK (1 << 14) -#define OMAP3430_AUTO_GPIO3_SHIFT 14 -#define OMAP3430_AUTO_GPIO2_MASK (1 << 13) -#define OMAP3430_AUTO_GPIO2_SHIFT 13 -#define OMAP3430_AUTO_WDT3_MASK (1 << 12) -#define OMAP3430_AUTO_WDT3_SHIFT 12 -#define OMAP3430_AUTO_UART3_MASK (1 << 11) -#define OMAP3430_AUTO_UART3_SHIFT 11 -#define OMAP3430_AUTO_GPT9_MASK (1 << 10) -#define OMAP3430_AUTO_GPT9_SHIFT 10 -#define OMAP3430_AUTO_GPT8_MASK (1 << 9) -#define OMAP3430_AUTO_GPT8_SHIFT 9 -#define OMAP3430_AUTO_GPT7_MASK (1 << 8) -#define OMAP3430_AUTO_GPT7_SHIFT 8 -#define OMAP3430_AUTO_GPT6_MASK (1 << 7) -#define OMAP3430_AUTO_GPT6_SHIFT 7 -#define OMAP3430_AUTO_GPT5_MASK (1 << 6) -#define OMAP3430_AUTO_GPT5_SHIFT 6 -#define OMAP3430_AUTO_GPT4_MASK (1 << 5) -#define OMAP3430_AUTO_GPT4_SHIFT 5 -#define OMAP3430_AUTO_GPT3_MASK (1 << 4) -#define OMAP3430_AUTO_GPT3_SHIFT 4 -#define OMAP3430_AUTO_GPT2_MASK (1 << 3) -#define OMAP3430_AUTO_GPT2_SHIFT 3 -#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) -#define OMAP3430_AUTO_MCBSP4_SHIFT 2 -#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) -#define OMAP3430_AUTO_MCBSP3_SHIFT 1 -#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) -#define OMAP3430_AUTO_MCBSP2_SHIFT 0 - -/* CM_CLKSEL_PER */ #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT9_SHIFT 7 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT8_SHIFT 6 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) -#define OMAP3430_CLKSEL_GPT7_SHIFT 5 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) -#define OMAP3430_CLKSEL_GPT6_SHIFT 4 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) -#define OMAP3430_CLKSEL_GPT5_SHIFT 3 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) -#define OMAP3430_CLKSEL_GPT4_SHIFT 2 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) -#define OMAP3430_CLKSEL_GPT3_SHIFT 1 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) -#define OMAP3430_CLKSEL_GPT2_SHIFT 0 - -/* CM_SLEEPDEP_PER specific bits */ -#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_PER */ -#define OMAP3430_CLKTRCTRL_PER_SHIFT 0 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) - -/* CM_CLKSTST_PER */ -#define OMAP3430_CLKACTIVITY_PER_SHIFT 0 -#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) - -/* CM_CLKSEL1_EMU */ #define OMAP3430_DIV_DPLL4_SHIFT 24 -#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) -#define OMAP3430_DIV_DPLL4_WIDTH 5 -#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) #define OMAP3630_DIV_DPLL4_WIDTH 6 #define OMAP3430_DIV_DPLL3_SHIFT 16 -#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) #define OMAP3430_DIV_DPLL3_WIDTH 5 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 -#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 -#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) #define OMAP3430_CLKSEL_PCLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 -#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 -#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 -#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 -#define OMAP3430_MUX_CTRL_SHIFT 0 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) -#define OMAP3430_MUX_CTRL_WIDTH 2 - -/* CM_CLKSTCTRL_EMU */ -#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) - -/* CM_CLKSTST_EMU */ -#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) - -/* CM_CLKSEL2_EMU specific bits */ -#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL3_EMU specific bits */ -#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_POLCTRL */ -#define OMAP3430_CLKOUT2_POL_MASK (1 << 0) - -/* CM_IDLEST_NEON */ -#define OMAP3430_ST_NEON_MASK (1 << 0) - -/* CM_CLKSTCTRL_NEON */ -#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) - -/* CM_FCLKEN_USBHOST */ #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 -#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) - -/* CM_ICLKEN_USBHOST */ #define OMAP3430ES2_EN_USBHOST_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) - -/* CM_IDLEST_USBHOST */ #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) - -/* CM_AUTOIDLE_USBHOST */ -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) - -/* CM_SLEEPDEP_USBHOST */ -#define OMAP3430ES2_EN_MPU_SHIFT 1 -#define OMAP3430ES2_EN_MPU_MASK (1 << 1) -#define OMAP3430ES2_EN_IVA2_SHIFT 2 -#define OMAP3430ES2_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_USBHOST */ -#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) - -/* CM_CLKSTST_USBHOST */ -#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) - -/* - * - */ - -/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 - - #endif diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 4c6c2f7de65b..4dbbd99b6e1e 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -22,1683 +22,125 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H -/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_WIDTH 0x1 -#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_WIDTH 0x1 -#define OMAP4430_ABE_STATDEP_MASK (1 << 3) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 -#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 -#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) - -/* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, - * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB - */ -#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 -#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 -#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) - -/* Used by CM_DUCATI_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) - -/* Used by CM_IVAHD_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) - -/* Used by CM_L3_1_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) - -/* Used by CM_L3_2_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) - -/* Used by CM_SDMA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) - -/* Used by CM_MPU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) - -/* Used by CM_TESLA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) - -/* - * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, - * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL - */ #define OMAP4430_CLKSEL_SHIFT 24 #define OMAP4430_CLKSEL_WIDTH 0x1 #define OMAP4430_CLKSEL_MASK (1 << 24) - -/* - * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL - */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 -#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) - -/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 -#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) - -/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 -#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 #define OMAP4430_CLKSEL_60M_WIDTH 0x1 -#define OMAP4430_CLKSEL_60M_MASK (1 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 -#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) - -/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) - -/* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 -#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) - -/* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 -#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) - -/* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) - -/* - * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 #define OMAP4430_CLKSEL_L3_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_MASK (1 << 4) - -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 #define OMAP4430_CLKSEL_L4_WIDTH 0x1 -#define OMAP4430_CLKSEL_L4_MASK (1 << 8) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 -#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) - -/* - * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, - * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) - -/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) - -/* - * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, - * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, - * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL - */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_WIDTH 0x2 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_WIDTH 0x2 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_WIDTH 0x1 -#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_WIDTH 0x1 -#define OMAP4430_D2D_STATDEP_MASK (1 << 18) - -/* Used by CM_CLKSEL_DPLL_MPU */ -#define OMAP4460_DCC_COUNT_MAX_SHIFT 24 -#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 -#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) - -/* Used by CM_CLKSEL_DPLL_MPU */ -#define OMAP4460_DCC_EN_SHIFT 22 -#define OMAP4460_DCC_EN_MASK (1 << 22) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, - * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, - * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB - */ -#define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_WIDTH 0x14 -#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) - -/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ -#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 -#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 -#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) - -/* Used by CM_DLL_CTRL */ -#define OMAP4430_DLL_OVERRIDE_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 -#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) - -/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 -#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_WIDTH 0x1 -#define OMAP4430_DLL_RESET_MASK (1 << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB - */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKSEL_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO - */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB - */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_WIDTH 0x7 #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_WIDTH 0xb #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_WIDTH 0x1 -#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_WIDTH 0x1 -#define OMAP4430_DSS_STATDEP_MASK (1 << 8) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 -#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) - -/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 -#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_WIDTH 0x1 -#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_WIDTH 0xc -#define OMAP4430_FUNC_MASK (0xfff << 16) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_WIDTH 0x1 -#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_WIDTH 0x1 -#define OMAP4430_GFX_STATDEP_MASK (1 << 10) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, - * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, - * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, - * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, - * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, - * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL - */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_WIDTH 0x2 #define OMAP4430_IDLEST_MASK (0x3 << 16) - -/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_WIDTH 0x1 -#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) - -/* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_TESLA_STATICDEP - */ -#define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_WIDTH 0x1 -#define OMAP4430_ISS_STATDEP_MASK (1 << 9) - -/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 -#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 -#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 -#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) - -/* - * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_WIDTH 0x1 -#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) - -/* - * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, - * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP - */ -#define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_WIDTH 0x1 -#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) - -/* Used by CM_L3_1_DYNAMICDEP */ -#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 -#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_WIDTH 0x1 -#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) - -/* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP - */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 -#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) - -/* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 -#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) - -/* - * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MPU_DYNAMICDEP - */ -#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 -#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 -#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, - * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, - * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, - * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, - * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, - * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL - */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_WIDTH 0x2 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4460_MPU_DYNDEP_SHIFT 19 -#define OMAP4460_MPU_DYNDEP_WIDTH 0x1 -#define OMAP4460_MPU_DYNDEP_MASK (1 << 19) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) - -/* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) - -/* Used by CM_ALWON_USBPHY_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) - -/* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) - -/* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, - * CM_WKUP_GPIO1_CLKCTRL - */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) - -/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) - -/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) - -/* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 -#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 -#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 -#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 -#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) - -/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ -#define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_WIDTH 0x8 -#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) - -/* - * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, - * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, - * CM_IVA_DVFS_PERF_TESLA - */ -#define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_WIDTH 0x8 -#define OMAP4430_PERF_REQ_MASK (0xff << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) - -/* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_WIDTH 0x6 -#define OMAP4430_PRESCAL_MASK (0x3f << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_WIDTH 0x5 -#define OMAP4430_R_RTL_MASK (0x1f << 11) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ -#define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_WIDTH 0x1 -#define OMAP4430_SAR_MODE_MASK (1 << 4) - -/* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 #define OMAP4430_SCALE_FCLK_WIDTH 0x1 -#define OMAP4430_SCALE_FCLK_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_WIDTH 0x2 -#define OMAP4430_SCHEME_MASK (0x3 << 30) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 -#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_WIDTH 0x1 -#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL - */ -#define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_WIDTH 0x1 -#define OMAP4430_STBYST_MASK (1 << 18) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB - */ -#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ -#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_MN_BYPASS_SHIFT 8 -#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 -#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 -#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 -#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_WIDTH 0x1 -#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) - -/* - * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_WIDTH 0x4 -#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_WIDTH 0x3 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_WIDTH 0x6 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h index e83b8e352b6e..896ae9fc4cfb 100644 --- a/arch/arm/mach-omap2/cm-regbits-54xx.h +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h @@ -21,1717 +21,84 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H -/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ -#define OMAP54XX_ABE_DYNDEP_SHIFT 3 -#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 -#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_ABE_STATDEP_SHIFT 3 -#define OMAP54XX_ABE_STATDEP_WIDTH 0x1 -#define OMAP54XX_ABE_STATDEP_MASK (1 << 3) - -/* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, - * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, - * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB - */ -#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_C2C_DYNDEP_SHIFT 18 -#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 -#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP54XX_C2C_STATDEP_SHIFT 18 -#define OMAP54XX_C2C_STATDEP_WIDTH 0x1 -#define OMAP54XX_C2C_STATDEP_MASK (1 << 18) - -/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_CAM_DYNDEP_SHIFT 9 -#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 -#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) - -/* - * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, - * CM_MPU_STATICDEP - */ -#define OMAP54XX_CAM_STATDEP_SHIFT 9 -#define OMAP54XX_CAM_STATDEP_WIDTH 0x1 -#define OMAP54XX_CAM_STATDEP_MASK (1 << 9) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) - -/* Used by CM_CUSTEFUSE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CUSTEFUSE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) - -/* Used by CM_DMA_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) - -/* Used by CM_DSP_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) - -/* Used by CM_IPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) - -/* Used by CM_IVA_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) - -/* Used by CM_L3MAIN1_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3MAIN2_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) - -/* Used by CM_MPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) - -/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ -#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 -#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) - -/* - * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL - */ #define OMAP54XX_CLKSEL_SHIFT 24 #define OMAP54XX_CLKSEL_WIDTH 0x1 -#define OMAP54XX_CLKSEL_MASK (1 << 24) - -/* - * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, - * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON - */ #define OMAP54XX_CLKSEL_0_0_SHIFT 0 #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 -#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) - -/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ -#define OMAP54XX_CLKSEL_0_1_SHIFT 0 -#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 -#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) - -/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ -#define OMAP54XX_CLKSEL_24_25_SHIFT 24 -#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 -#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - -/* Used by CM_ABE_AESS_CLKCTRL */ #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ #define OMAP54XX_CLKSEL_DIV_SHIFT 25 #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 -#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) - -/* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) - -/* Used by CM_GPU_GPU_CLKCTRL */ #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) - -/* Used by CM_GPU_GPU_CLKCTRL */ #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) - -/* Used by CM_GPU_GPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) - -/* - * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, - * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL - */ #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) - -/* Used by CM_CLKSEL_CORE */ -#define OMAP54XX_CLKSEL_L3_SHIFT 4 -#define OMAP54XX_CLKSEL_L3_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L3_MASK (1 << 4) - -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 -#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) - -/* Used by CM_CLKSEL_CORE */ -#define OMAP54XX_CLKSEL_L4_SHIFT 8 -#define OMAP54XX_CLKSEL_L4_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L4_MASK (1 << 8) - -/* Used by CM_EMIF_EMIF1_CLKCTRL */ -#define OMAP54XX_CLKSEL_LL_SHIFT 24 -#define OMAP54XX_CLKSEL_LL_WIDTH 0x1 -#define OMAP54XX_CLKSEL_LL_MASK (1 << 24) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_CLKSEL_OPP_SHIFT 0 #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 -#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) - -/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ -#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 -#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 -#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) - -/* - * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, - * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL - */ #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) - -/* - * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL - */ #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 -#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) - -/* - * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, - * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, - * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, - * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, - * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, - * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, - * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, - * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER - */ -#define OMAP54XX_CLKST_SHIFT 9 -#define OMAP54XX_CLKST_WIDTH 0x1 -#define OMAP54XX_CLKST_MASK (1 << 9) - -/* - * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, - * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, - * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, - * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, - * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, - * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL - */ -#define OMAP54XX_CLKTRCTRL_SHIFT 0 -#define OMAP54XX_CLKTRCTRL_WIDTH 0x2 -#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ -#define OMAP54XX_CLKX2ST_SHIFT 11 -#define OMAP54XX_CLKX2ST_WIDTH 0x1 -#define OMAP54XX_CLKX2ST_MASK (1 << 11) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_COREAON_DYNDEP_SHIFT 16 -#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 -#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) - -/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_COREAON_STATDEP_SHIFT 16 -#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 -#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 -#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 -#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) - -/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 -#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 -#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_CUSTOM_SHIFT 6 -#define OMAP54XX_CUSTOM_WIDTH 0x2 -#define OMAP54XX_CUSTOM_MASK (0x3 << 6) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DCC_EN_SHIFT 22 -#define OMAP54XX_DCC_EN_WIDTH 0x1 -#define OMAP54XX_DCC_EN_MASK (1 << 22) - -/* - * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, - * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, - * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS - */ -#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 -#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd -#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, - * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 -#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, - * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 -#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, - * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 -#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, - * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 -#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, - * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb -#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, - * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 -#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 -#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa -#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b -#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe -#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 -#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER - */ -#define OMAP54XX_DELTAMSTEP_SHIFT 0 -#define OMAP54XX_DELTAMSTEP_WIDTH 0x14 -#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) - -/* - * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, - * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB - */ -#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 -#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 -#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) - -/* - * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, - * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, - * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, - * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, - * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE - */ -#define OMAP54XX_DIVHS_SHIFT 0 -#define OMAP54XX_DIVHS_WIDTH 0x6 #define OMAP54XX_DIVHS_MASK (0x3f << 0) - -/* - * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER - */ -#define OMAP54XX_DIVHS_0_4_SHIFT 0 -#define OMAP54XX_DIVHS_0_4_WIDTH 0x5 #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) - -/* - * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, - * CM_DIV_M2_DPLL_USB - */ -#define OMAP54XX_DIVHS_0_6_SHIFT 0 -#define OMAP54XX_DIVHS_0_6_WIDTH 0x7 #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) - -/* Used by CM_DLL_CTRL */ -#define OMAP54XX_DLL_OVERRIDE_SHIFT 0 -#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 -#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) - -/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 -#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 -#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DLL_RESET_SHIFT 3 -#define OMAP54XX_DLL_RESET_WIDTH 0x1 -#define OMAP54XX_DLL_RESET_MASK (1 << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKSEL_DPLL_CORE */ -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 -#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 -#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 -#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 -#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER - */ -#define OMAP54XX_DPLL_DIV_SHIFT 0 -#define OMAP54XX_DPLL_DIV_WIDTH 0x7 #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) - -/* - * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 -#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 -#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_EN_SHIFT 0 -#define OMAP54XX_DPLL_EN_WIDTH 0x3 #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER - */ -#define OMAP54XX_DPLL_MULT_SHIFT 8 -#define OMAP54XX_DPLL_MULT_WIDTH 0xb #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) - -/* - * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 -#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc -#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 -#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ -#define OMAP54XX_DPLL_SD_DIV_SHIFT 24 -#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) - -/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ -#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 -#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 -#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 -#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_EN_SHIFT 12 -#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_DSP_DYNDEP_SHIFT 1 -#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 -#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_DSP_STATDEP_SHIFT 1 -#define OMAP54XX_DSP_STATDEP_WIDTH 0x1 -#define OMAP54XX_DSP_STATDEP_MASK (1 << 1) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_DSS_DYNDEP_SHIFT 8 -#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 -#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) - -/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_DSS_STATDEP_SHIFT 8 -#define OMAP54XX_DSS_STATDEP_WIDTH 0x1 -#define OMAP54XX_DSS_STATDEP_MASK (1 << 8) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_EMIF_DYNDEP_SHIFT 4 -#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 -#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_EMIF_STATDEP_SHIFT 4 -#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 -#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_FREQ_UPDATE_SHIFT 0 -#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 -#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_FUNC_SHIFT 16 -#define OMAP54XX_FUNC_WIDTH 0xc -#define OMAP54XX_FUNC_MASK (0xfff << 16) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 -#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_GPU_DYNDEP_SHIFT 10 -#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_GPU_STATDEP_SHIFT 10 -#define OMAP54XX_GPU_STATDEP_WIDTH 0x1 -#define OMAP54XX_GPU_STATDEP_MASK (1 << 10) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, - * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, - * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, - * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, - * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, - * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, - * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, - * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, - * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, - * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, - * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, - * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, - * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, - * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, - * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, - * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, - * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, - * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, - * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, - * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, - * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, - * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, - * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, - * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, - * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL - */ -#define OMAP54XX_IDLEST_SHIFT 16 -#define OMAP54XX_IDLEST_WIDTH 0x2 -#define OMAP54XX_IDLEST_MASK (0x3 << 16) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_IPU_DYNDEP_SHIFT 0 -#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) - -/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_IPU_STATDEP_SHIFT 0 -#define OMAP54XX_IPU_STATDEP_WIDTH 0x1 -#define OMAP54XX_IPU_STATDEP_MASK (1 << 0) - -/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_IVA_DYNDEP_SHIFT 2 -#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 -#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_IVA_STATDEP_SHIFT 2 -#define OMAP54XX_IVA_STATDEP_WIDTH 0x1 -#define OMAP54XX_IVA_STATDEP_MASK (1 << 2) - -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 -#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 -#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) - -/* - * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 -#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 -#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, - * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, - * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP - */ -#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 -#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 -#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) - -/* Used by CM_L3MAIN1_DYNAMICDEP */ -#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 -#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 -#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_L4PER_DYNDEP_SHIFT 13 -#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L4PER_STATDEP_SHIFT 13 -#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 -#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) - -/* - * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP - */ #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 -#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 -#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 -#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 -#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 -#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 -#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 -#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, - * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, - * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, - * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, - * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, - * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, - * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, - * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, - * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, - * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, - * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, - * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, - * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, - * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, - * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, - * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, - * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, - * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, - * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, - * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, - * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, - * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, - * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, - * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, - * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL - */ -#define OMAP54XX_MODULEMODE_SHIFT 0 -#define OMAP54XX_MODULEMODE_WIDTH 0x2 -#define OMAP54XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_MPU_DYNDEP_SHIFT 19 -#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) - -/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) - -/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) - -/* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) - -/* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, - * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL - */ #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) - -/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) - -/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) - -/* Used by CM_L3INIT_SATA_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) - -/* Used by CM_WKUPAON_SCRM_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) - -/* Used by CM_WKUPAON_SCRM_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) - -/* Used by CM_MIPIEXT_LLI_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) - -/* Used by CM_MIPIEXT_LLI_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) - -/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ -#define OMAP54XX_OUTPUT_SHIFT 0 -#define OMAP54XX_OUTPUT_WIDTH 0x20 -#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 -#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 -#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 -#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) - -/* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP54XX_PRESCAL_SHIFT 0 -#define OMAP54XX_PRESCAL_WIDTH 0x6 -#define OMAP54XX_PRESCAL_MASK (0x3f << 0) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_R_RTL_SHIFT 11 -#define OMAP54XX_R_RTL_WIDTH 0x5 -#define OMAP54XX_R_RTL_MASK (0x1f << 11) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ -#define OMAP54XX_SAR_MODE_SHIFT 4 -#define OMAP54XX_SAR_MODE_WIDTH 0x1 -#define OMAP54XX_SAR_MODE_MASK (1 << 4) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_SCHEME_SHIFT 30 -#define OMAP54XX_SCHEME_WIDTH 0x2 -#define OMAP54XX_SCHEME_MASK (0x3 << 30) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_SDMA_DYNDEP_SHIFT 11 -#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 -#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_SDMA_STATDEP_SHIFT 11 -#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 -#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL0_SHIFT 0 -#define OMAP54XX_SEL0_WIDTH 0x7 -#define OMAP54XX_SEL0_MASK (0x7f << 0) - -/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL0_0_7_SHIFT 0 -#define OMAP54XX_SEL0_0_7_WIDTH 0x8 -#define OMAP54XX_SEL0_0_7_MASK (0xff << 0) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL1_SHIFT 8 -#define OMAP54XX_SEL1_WIDTH 0x7 -#define OMAP54XX_SEL1_MASK (0x7f << 8) - -/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL2_SHIFT 16 -#define OMAP54XX_SEL2_WIDTH 0x7 -#define OMAP54XX_SEL2_MASK (0x7f << 16) - -/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL3_SHIFT 24 -#define OMAP54XX_SEL3_WIDTH 0x7 -#define OMAP54XX_SEL3_MASK (0x7f << 24) - -/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 -#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 -#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, - * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, - * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, - * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, - * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, - * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL - */ -#define OMAP54XX_STBYST_SHIFT 18 -#define OMAP54XX_STBYST_WIDTH 0x1 -#define OMAP54XX_STBYST_MASK (1 << 18) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_CLK_SHIFT 0 -#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) - -/* - * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, - * CM_CLKDCOLDO_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 -#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_INIT_SHIFT 4 -#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 -#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_MODE_SHIFT 1 -#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 -#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) - -/* Used by CM_CLKSEL_SYS */ #define OMAP54XX_SYS_CLKSEL_SHIFT 0 #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 -#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, - * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, - * CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_WINDOWSIZE_SHIFT 24 -#define OMAP54XX_WINDOWSIZE_WIDTH 0x4 -#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) - -/* Used by CM_L3MAIN1_DYNAMICDEP */ -#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 -#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 -#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) - -/* - * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 -#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 -#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_X_MAJOR_SHIFT 8 -#define OMAP54XX_X_MAJOR_WIDTH 0x3 -#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_Y_MINOR_SHIFT 0 -#define OMAP54XX_Y_MINOR_WIDTH 0x6 -#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index dfcc182ecff9..4a5684b96492 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -110,6 +110,7 @@ void omap3630_init_late(void); void am35xx_init_late(void); void ti81xx_init_late(void); int omap2_common_pm_late_init(void); +void dra7xx_init_early(void); #ifdef CONFIG_SOC_BUS void omap_soc_device_init(void); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 3c1279f27d1f..5c5315ba129b 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -327,44 +327,6 @@ static void omap_init_audio(void) static inline void omap_init_audio(void) {} #endif -#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ - defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) - -static void __init omap_init_mcpdm(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("mcpdm"); - if (!oh) - return; - - pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); -} -#else -static inline void omap_init_mcpdm(void) {} -#endif - -#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \ - defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE) - -static void __init omap_init_dmic(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("dmic"); - if (!oh) - return; - - pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); -} -#else -static inline void omap_init_dmic(void) {} -#endif - #if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \ defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE) @@ -565,17 +527,15 @@ static int __init omap2_init_devices(void) omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { - omap_init_dmic(); - omap_init_mcpdm(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); + omap_init_rng(); } else { /* These can be removed when bindings are done */ omap_init_wl12xx_of(); } omap_init_sti(); - omap_init_rng(); omap_init_vout(); return 0; diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index ff37be1f6f93..03a0516c7f67 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -400,7 +400,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) /* Create devices for DPI and SDI */ - pdev = create_simple_dss_pdev("omapdss_dpi", -1, + pdev = create_simple_dss_pdev("omapdss_dpi", 0, board_data, sizeof(*board_data), dss_pdev); if (IS_ERR(pdev)) { pr_err("Could not build platform_device for omapdss_dpi\n"); @@ -408,7 +408,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) } if (cpu_is_omap34xx()) { - pdev = create_simple_dss_pdev("omapdss_sdi", -1, + pdev = create_simple_dss_pdev("omapdss_sdi", 0, board_data, sizeof(*board_data), dss_pdev); if (IS_ERR(pdev)) { pr_err("Could not build platform_device for omapdss_sdi\n"); diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index 043e5705f2a6..bf89effa4c99 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c @@ -25,6 +25,7 @@ #include <linux/kernel.h> #include <linux/gpio.h> +#include <linux/platform_device.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> @@ -37,70 +38,76 @@ #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ #define HDMI_GPIO_HPD 63 /* Hotplug detect */ -/* Display DVI */ #define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 -/* Using generic display panel */ -static struct tfp410_platform_data omap4_dvi_panel = { - .i2c_bus_num = 2, - .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, +/* DVI Connector */ +static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 2, }; -static struct omap_dss_device omap4_panda_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &omap4_dvi_panel, - .phy.dpi.data_lines = 24, - .channel = OMAP_DSS_CHANNEL_LCD2, +static struct platform_device omap4_panda_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap4_panda_dvi_connector_pdata, }; -static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { +/* TFP410 DPI-to-DVI chip */ +static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, +}; + +static struct platform_device omap4_panda_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap4_panda_tfp410_pdata, +}; + +/* HDMI Connector */ +static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = { + .name = "hdmi", + .source = "tpd12s015.0", +}; + +static struct platform_device omap4_panda_hdmi_connector_device = { + .name = "connector-hdmi", + .id = 0, + .dev.platform_data = &omap4_panda_hdmi_connector_pdata, +}; + +/* TPD12S015 HDMI ESD protection & level shifter chip */ +static struct encoder_tpd12s015_platform_data omap4_panda_tpd_pdata = { + .name = "tpd12s015.0", + .source = "hdmi.0", + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, .ls_oe_gpio = HDMI_GPIO_LS_OE, .hpd_gpio = HDMI_GPIO_HPD, }; -static struct omap_dss_device omap4_panda_hdmi_device = { - .name = "hdmi", - .driver_name = "hdmi_panel", - .type = OMAP_DISPLAY_TYPE_HDMI, - .channel = OMAP_DSS_CHANNEL_DIGIT, - .data = &omap4_panda_hdmi_data, -}; - -static struct omap_dss_device *omap4_panda_dss_devices[] = { - &omap4_panda_dvi_device, - &omap4_panda_hdmi_device, +static struct platform_device omap4_panda_tpd_device = { + .name = "tpd12s015", + .id = 0, + .dev.platform_data = &omap4_panda_tpd_pdata, }; static struct omap_dss_board_info omap4_panda_dss_data = { - .num_devices = ARRAY_SIZE(omap4_panda_dss_devices), - .devices = omap4_panda_dss_devices, - .default_device = &omap4_panda_dvi_device, + .default_display_name = "dvi", }; -void __init omap4_panda_display_init(void) +void __init omap4_panda_display_init_of(void) { omap_display_init(&omap4_panda_dss_data); - /* - * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and - * later have external pull up on the HDMI I2C lines - */ - if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2) - omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); - else - omap_hdmi_init(0); - - omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); -} + platform_device_register(&omap4_panda_tfp410_device); + platform_device_register(&omap4_panda_dvi_connector_device); -void __init omap4_panda_display_init_of(void) -{ - omap_display_init(&omap4_panda_dss_data); + platform_device_register(&omap4_panda_tpd_device); + platform_device_register(&omap4_panda_hdmi_connector_device); } @@ -109,93 +116,73 @@ void __init omap4_panda_display_init_of(void) #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ #define DLP_POWER_ON_GPIO 40 -static struct nokia_dsi_panel_data dsi1_panel = { - .name = "taal", - .reset_gpio = 102, - .use_ext_te = false, - .ext_te_gpio = 101, - .esd_interval = 0, - .pin_config = { - .num_pins = 6, - .pins = { 0, 1, 2, 3, 4, 5 }, - }, -}; - -static struct omap_dss_device sdp4430_lcd_device = { - .name = "lcd", - .driver_name = "taal", - .type = OMAP_DISPLAY_TYPE_DSI, - .data = &dsi1_panel, - .phy.dsi = { - .module = 0, +static struct panel_dsicm_platform_data dsi1_panel = { + .name = "lcd", + .source = "dsi.0", + .reset_gpio = 102, + .use_ext_te = false, + .ext_te_gpio = 101, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, }, - .channel = OMAP_DSS_CHANNEL_LCD, }; -static struct nokia_dsi_panel_data dsi2_panel = { - .name = "taal", - .reset_gpio = 104, - .use_ext_te = false, - .ext_te_gpio = 103, - .esd_interval = 0, - .pin_config = { - .num_pins = 6, - .pins = { 0, 1, 2, 3, 4, 5 }, - }, +static struct platform_device sdp4430_lcd_device = { + .name = "panel-dsi-cm", + .id = 0, + .dev.platform_data = &dsi1_panel, }; -static struct omap_dss_device sdp4430_lcd2_device = { - .name = "lcd2", - .driver_name = "taal", - .type = OMAP_DISPLAY_TYPE_DSI, - .data = &dsi2_panel, - .phy.dsi = { - - .module = 1, +static struct panel_dsicm_platform_data dsi2_panel = { + .name = "lcd2", + .source = "dsi.1", + .reset_gpio = 104, + .use_ext_te = false, + .ext_te_gpio = 103, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, }, - .channel = OMAP_DSS_CHANNEL_LCD2, }; -static struct omap_dss_hdmi_data sdp4430_hdmi_data = { - .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, - .ls_oe_gpio = HDMI_GPIO_LS_OE, - .hpd_gpio = HDMI_GPIO_HPD, +static struct platform_device sdp4430_lcd2_device = { + .name = "panel-dsi-cm", + .id = 1, + .dev.platform_data = &dsi2_panel, }; -static struct omap_dss_device sdp4430_hdmi_device = { - .name = "hdmi", - .driver_name = "hdmi_panel", - .type = OMAP_DISPLAY_TYPE_HDMI, - .channel = OMAP_DSS_CHANNEL_DIGIT, - .data = &sdp4430_hdmi_data, +/* HDMI Connector */ +static struct connector_hdmi_platform_data sdp4430_hdmi_connector_pdata = { + .name = "hdmi", + .source = "tpd12s015.0", }; -static struct picodlp_panel_data sdp4430_picodlp_pdata = { - .picodlp_adapter_id = 2, - .emu_done_gpio = 44, - .pwrgood_gpio = 45, +static struct platform_device sdp4430_hdmi_connector_device = { + .name = "connector-hdmi", + .id = 0, + .dev.platform_data = &sdp4430_hdmi_connector_pdata, }; -static struct omap_dss_device sdp4430_picodlp_device = { - .name = "picodlp", - .driver_name = "picodlp_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .channel = OMAP_DSS_CHANNEL_LCD2, - .data = &sdp4430_picodlp_pdata, +/* TPD12S015 HDMI ESD protection & level shifter chip */ +static struct encoder_tpd12s015_platform_data sdp4430_tpd_pdata = { + .name = "tpd12s015.0", + .source = "hdmi.0", + + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, + .ls_oe_gpio = HDMI_GPIO_LS_OE, + .hpd_gpio = HDMI_GPIO_HPD, }; -static struct omap_dss_device *sdp4430_dss_devices[] = { - &sdp4430_lcd_device, - &sdp4430_lcd2_device, - &sdp4430_hdmi_device, - &sdp4430_picodlp_device, +static struct platform_device sdp4430_tpd_device = { + .name = "tpd12s015", + .id = 0, + .dev.platform_data = &sdp4430_tpd_pdata, }; + static struct omap_dss_board_info sdp4430_dss_data = { - .num_devices = ARRAY_SIZE(sdp4430_dss_devices), - .devices = sdp4430_dss_devices, - .default_device = &sdp4430_lcd_device, + .default_display_name = "lcd", }; /* @@ -204,7 +191,7 @@ static struct omap_dss_board_info sdp4430_dss_data = { * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is * selected by default */ -void __init omap_4430sdp_display_init(void) +void __init omap_4430sdp_display_init_of(void) { int r; @@ -219,33 +206,10 @@ void __init omap_4430sdp_display_init(void) pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); omap_display_init(&sdp4430_dss_data); - /* - * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and - * later have external pull up on the HDMI I2C lines - */ - if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2) - omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); - else - omap_hdmi_init(0); - - omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); -} - -void __init omap_4430sdp_display_init_of(void) -{ - int r; - r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, - "display_sel"); - if (r) - pr_err("%s: Could not get display_sel GPIO\n", __func__); - - r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, - "DLP POWER ON"); - if (r) - pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); + platform_device_register(&sdp4430_lcd_device); + platform_device_register(&sdp4430_lcd2_device); - omap_display_init(&sdp4430_dss_data); + platform_device_register(&sdp4430_tpd_device); + platform_device_register(&sdp4430_hdmi_connector_device); } diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h index 915f6fff5106..c28fe3c03588 100644 --- a/arch/arm/mach-omap2/dss-common.h +++ b/arch/arm/mach-omap2/dss-common.h @@ -6,9 +6,7 @@ * This file will be removed when DSS supports DT. */ -void __init omap4_panda_display_init(void); void __init omap4_panda_display_init_of(void); -void __init omap_4430sdp_display_init(void); void __init omap_4430sdp_display_init_of(void); #endif diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f3fdd6afa213..9f4795aff48a 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -149,7 +149,7 @@ struct omap3_gpmc_regs { static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; static struct irq_chip gpmc_irq_chip; -static unsigned gpmc_irq_start; +static int gpmc_irq_start; static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index d940e53dd9f2..b456b4471f35 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -181,7 +181,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, sizeof(struct omap_i2c_bus_platform_data)); WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); - return PTR_RET(pdev); + return PTR_ERR_OR_ZERO(pdev); } static int __init omap_i2c_cmdline(void) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 2dc62a25f2c3..0289adcb6efb 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -61,7 +61,7 @@ int omap_type(void) val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); - } else if (soc_is_omap54xx()) { + } else if (soc_is_omap54xx() || soc_is_dra7xx()) { val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); val &= OMAP5_DEVICETYPE_MASK; val >>= 6; @@ -116,7 +116,7 @@ static u16 tap_prod_id; void omap_get_die_id(struct omap_die_id *odi) { - if (cpu_is_omap44xx() || soc_is_omap54xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4a3f06f02859..3656b8009a1c 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_OMAP5 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) static struct map_desc omap54xx_io_desc[] __initdata = { { .virtual = L3_54XX_VIRT, @@ -333,7 +333,7 @@ void __init omap4_map_io(void) } #endif -#ifdef CONFIG_SOC_OMAP5 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); @@ -653,6 +653,22 @@ void __init omap5_init_early(void) } #endif +#ifdef CONFIG_SOC_DRA7XX +void __init dra7xx_init_early(void) +{ + omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); +} +#endif + + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a086ba15868b..2d35c5709408 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h @@ -30,4 +30,8 @@ #define OMAP54XX_CTRL_BASE 0x4a002800 #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 +#define DRA7XX_CM_CORE_AON_BASE 0x4a005000 +#define DRA7XX_CTRL_BASE 0x4a003400 +#define DRA7XX_TAP_BASE 0x4ae0c000 + #endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 7f4db12b1459..b4ecd2c7db8e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -4113,7 +4113,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; - } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { + } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 3c70f5c1860f..b4d04748576b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -32,7 +32,6 @@ #include "cm1_54xx.h" #include "cm2_54xx.h" #include "prm54xx.h" -#include "prm-regbits-54xx.h" #include "i2c.h" #include "mmc.h" #include "wd_timer.h" diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c index 81f8a7cc26ee..ce1d752af991 100644 --- a/arch/arm/mach-omap2/powerdomains54xx_data.c +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -25,7 +25,6 @@ #include "prcm-common.h" #include "prcm44xx.h" -#include "prm-regbits-54xx.h" #include "prm54xx.h" #include "prcm_mpu54xx.h" diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 91aa5106d637..37fc905c9636 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -16,274 +16,27 @@ #include "prm2xxx.h" -/* Bits shared between registers */ - -/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) -#define OMAP24XX_WKUP2_ST_MASK (1 << 1) -#define OMAP24XX_WKUP1_ST_MASK (1 << 0) - -/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) -#define OMAP24XX_WKUP2_EN_MASK (1 << 1) -#define OMAP24XX_WKUP1_EN_MASK (1 << 0) - -/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ -#define OMAP24XX_EN_MPU_SHIFT 1 -#define OMAP24XX_EN_MPU_MASK (1 << 1) #define OMAP24XX_EN_CORE_SHIFT 0 -#define OMAP24XX_EN_CORE_MASK (1 << 0) - -/* - * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM - * shared bits - */ -#define OMAP24XX_MEMONSTATE_SHIFT 10 -#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEMRETSTATE_MASK (1 << 3) - -/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ #define OMAP24XX_FORCESTATE_MASK (1 << 18) - -/* - * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, - * PM_PWSTST_MDM shared bits - */ -#define OMAP24XX_CLKACTIVITY_MASK (1 << 19) - -/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ -#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 -#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) - -/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ -#define OMAP2430_MEMSTATEST_SHIFT 10 -#define OMAP2430_MEMSTATEST_MASK (0x3 << 10) - -/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ -#define OMAP24XX_POWERSTATEST_SHIFT 0 -#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) - - -/* Bits specific to each register */ - -/* PRCM_REVISION */ -#define OMAP24XX_REV_SHIFT 0 -#define OMAP24XX_REV_MASK (0xff << 0) - -/* PRCM_SYSCONFIG */ #define OMAP24XX_AUTOIDLE_MASK (1 << 0) - -/* PRCM_IRQSTATUS_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) -#define OMAP24XX_TRANSITION_ST_MASK (1 << 5) -#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) -#define OMAP24XX_EVGENON_ST_MASK (1 << 3) - -/* PRCM_IRQENABLE_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) -#define OMAP24XX_TRANSITION_EN_MASK (1 << 5) -#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) -#define OMAP24XX_EVGENON_EN_MASK (1 << 3) - -/* PRCM_VOLTCTRL */ #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) -#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 -#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) #define OMAP24XX_SETRET_LEVEL_SHIFT 6 -#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) #define OMAP24XX_VOLT_LEVEL_SHIFT 0 -#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) - -/* PRCM_VOLTST */ -#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 -#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) - -/* PRCM_CLKSRC_CTRL specific bits */ - -/* PRCM_CLKOUT_CTRL */ #define OMAP2420_CLKOUT2_EN_SHIFT 15 -#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 -#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) #define OMAP2420_CLKOUT2_DIV_WIDTH 3 -#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 -#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 -#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) #define OMAP24XX_CLKOUT_DIV_WIDTH 3 -#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) - -/* PRCM_CLKEMUL_CTRL */ #define OMAP24XX_EMULATION_EN_SHIFT 0 -#define OMAP24XX_EMULATION_EN_MASK (1 << 0) - -/* PRCM_CLKCFG_CTRL */ -#define OMAP24XX_VALID_CONFIG_MASK (1 << 0) - -/* PRCM_CLKCFG_STATUS */ -#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) - -/* PRCM_VOLTSETUP specific bits */ - -/* PRCM_CLKSSETUP specific bits */ - -/* PRCM_POLCTRL */ -#define OMAP2420_CLKOUT2_POL_MASK (1 << 10) -#define OMAP24XX_CLKOUT_POL_MASK (1 << 9) -#define OMAP24XX_CLKREQ_POL_MASK (1 << 8) -#define OMAP2430_USE_POWEROK_MASK (1 << 2) -#define OMAP2430_POWEROK_POL_MASK (1 << 1) -#define OMAP24XX_EXTVOL_POL_MASK (1 << 0) - -/* RM_RSTST_MPU specific bits */ -/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ - -/* PM_WKDEP_MPU specific bits */ #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 -#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5) #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 -#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2) - -/* PM_EVGENCTRL_MPU specific bits */ - -/* PM_EVEGENONTIM_MPU specific bits */ - -/* PM_EVEGENOFFTIM_MPU specific bits */ - -/* PM_PWSTCTRL_MPU specific bits */ -#define OMAP2430_FORCESTATE_MASK (1 << 18) - -/* PM_PWSTST_MPU specific bits */ -/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ - -/* PM_WKEN1_CORE specific bits */ - -/* PM_WKEN2_CORE specific bits */ - -/* PM_WKST1_CORE specific bits*/ - -/* PM_WKST2_CORE specific bits */ - -/* PM_WKDEP_CORE specific bits*/ -#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) -#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) -#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) - -/* PM_PWSTCTRL_CORE specific bits */ -#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) -#define OMAP24XX_MEM3ONSTATE_SHIFT 14 -#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) -#define OMAP24XX_MEM2ONSTATE_SHIFT 12 -#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) -#define OMAP24XX_MEM1ONSTATE_SHIFT 10 -#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) -#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) -#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) - -/* PM_PWSTST_CORE specific bits */ -#define OMAP24XX_MEM3STATEST_SHIFT 14 -#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) -#define OMAP24XX_MEM2STATEST_SHIFT 12 -#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) -#define OMAP24XX_MEM1STATEST_SHIFT 10 -#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) - -/* RM_RSTCTRL_GFX */ -#define OMAP24XX_GFX_RST_MASK (1 << 0) - -/* RM_RSTST_GFX specific bits */ -#define OMAP24XX_GFX_SW_RST_MASK (1 << 4) - -/* PM_PWSTCTRL_GFX specific bits */ - -/* PM_WKDEP_GFX specific bits */ -/* 2430 often calls EN_WAKEUP "EN_WKUP" */ - -/* RM_RSTCTRL_WKUP specific bits */ - -/* RM_RSTTIME_WKUP specific bits */ - -/* RM_RSTST_WKUP specific bits */ -/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ #define OMAP24XX_EXTWMPU_RST_SHIFT 6 -#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) #define OMAP24XX_SECU_WD_RST_SHIFT 5 -#define OMAP24XX_SECU_WD_RST_MASK (1 << 5) #define OMAP24XX_MPU_WD_RST_SHIFT 4 -#define OMAP24XX_MPU_WD_RST_MASK (1 << 4) #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 -#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) - -/* PM_WKEN_WKUP specific bits */ - -/* PM_WKST_WKUP specific bits */ - -/* RM_RSTCTRL_DSP */ -#define OMAP2420_RST_IVA_MASK (1 << 8) -#define OMAP24XX_RST2_DSP_MASK (1 << 1) -#define OMAP24XX_RST1_DSP_MASK (1 << 0) - -/* RM_RSTST_DSP specific bits */ -/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ -#define OMAP2420_IVA_SW_RST_MASK (1 << 8) -#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) -#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) - -/* PM_WKDEP_DSP specific bits */ - -/* PM_PWSTCTRL_DSP specific bits */ -/* 2430 only: MEMONSTATE, MEMRETSTATE */ -#define OMAP2420_MEMIONSTATE_SHIFT 12 -#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) -#define OMAP2420_MEMIRETSTATE_MASK (1 << 4) - -/* PM_PWSTST_DSP specific bits */ -/* MEMSTATEST is 2430 only */ -#define OMAP2420_MEMISTATEST_SHIFT 12 -#define OMAP2420_MEMISTATEST_MASK (0x3 << 12) - -/* PRCM_IRQSTATUS_DSP specific bits */ - -/* PRCM_IRQENABLE_DSP specific bits */ - -/* RM_RSTCTRL_MDM */ -/* 2430 only */ -#define OMAP2430_PWRON1_MDM_MASK (1 << 1) -#define OMAP2430_RST1_MDM_MASK (1 << 0) - -/* RM_RSTST_MDM specific bits */ -/* 2430 only */ -#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) -#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) -#define OMAP2430_MDM_SW_RST1_MASK (1 << 4) - -/* PM_WKEN_MDM */ -/* 2430 only */ -#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) - -/* PM_WKST_MDM specific bits */ -/* 2430 only */ - -/* PM_WKDEP_MDM specific bits */ -/* 2430 only */ - -/* PM_PWSTCTRL_MDM specific bits */ -/* 2430 only */ -#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) - -/* PM_PWSTST_MDM specific bits */ -/* 2430 only */ - -/* PRCM_IRQSTATUS_IVA */ -/* 2420 only */ - -/* PRCM_IRQENABLE_IVA */ -/* 2420 only */ - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h index 0221b5c20e87..84feecee4fe6 100644 --- a/arch/arm/mach-omap2/prm-regbits-33xx.h +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h @@ -18,340 +18,35 @@ #include "prm.h" -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 -#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_AIPOFF_SHIFT 8 -#define AM33XX_AIPOFF_MASK (1 << 8) - -/* Used by PM_WKUP_PWRSTST */ -#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 -#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 -#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 -#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 -#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 -#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 -#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_EMULATION_M3_RST_SHIFT 6 -#define AM33XX_EMULATION_M3_RST_MASK (1 << 6) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_EMULATION_MPU_RST_SHIFT 5 -#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC1_EXPORT_SHIFT 3 -#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC3_EXPORT_SHIFT 5 -#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC4_SHIFT 6 -#define AM33XX_ENFUNC4_MASK (1 << 6) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC5_SHIFT 7 -#define AM33XX_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_RSTST */ -#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 -#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_FORCEWKUP_EN_SHIFT 10 -#define AM33XX_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_FORCEWKUP_ST_SHIFT 10 -#define AM33XX_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) - -/* Used by PM_GFX_PWRSTST */ -#define AM33XX_GFX_MEM_STATEST_SHIFT 4 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) - -/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ -#define AM33XX_GFX_RST_SHIFT 0 -#define AM33XX_GFX_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_COLD_RST_SHIFT 0 -#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 -#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 -#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) - -/* Used by PRM_RSTST */ -#define AM33XX_ICEPICK_RST_SHIFT 9 -#define AM33XX_ICEPICK_RST_MASK (1 << 9) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PRUSS_LRST_SHIFT 1 -#define AM33XX_PRUSS_LRST_MASK (1 << 1) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 +#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ -#define AM33XX_INTRANSITION_SHIFT 20 -#define AM33XX_INTRANSITION_MASK (1 << 20) - -/* Used by PM_CEFUSE_PWRSTST */ #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_SHIFT 2 #define AM33XX_LOGICRETSTATE_MASK (1 << 2) - -/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ #define AM33XX_LOGICSTATEST_SHIFT 2 #define AM33XX_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL - */ #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_ONSTATE_SHIFT 18 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_RETSTATE_SHIFT 22 #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L1_STATEST_SHIFT 6 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_ONSTATE_SHIFT 20 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_RETSTATE_SHIFT 23 #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L2_STATEST_SHIFT 8 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_RAM_STATEST_SHIFT 4 #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ -#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_PCHARGECNT_VALUE_SHIFT 0 -#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PCI_LRST_SHIFT 0 -#define AM33XX_PCI_LRST_MASK (1 << 0) - -/* Renamed from PCI_LRST Used by RM_PER_RSTST */ -#define AM33XX_PCI_LRST_5_5_SHIFT 5 -#define AM33XX_PCI_LRST_5_5_MASK (1 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_ONSTATE_SHIFT 25 #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_RETSTATE_SHIFT 29 #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PER_MEM_STATEST_SHIFT 17 #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL - */ -#define AM33XX_POWERSTATE_SHIFT 0 -#define AM33XX_POWERSTATE_MASK (0x3 << 0) - -/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ -#define AM33XX_POWERSTATEST_SHIFT 0 -#define AM33XX_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_RAM_MEM_STATEST_SHIFT 21 #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_RETMODE_ENABLE_SHIFT 0 -#define AM33XX_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define AM33XX_REV_SHIFT 0 -#define AM33XX_REV_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME1_SHIFT 0 -#define AM33XX_RSTTIME1_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME2_SHIFT 8 -#define AM33XX_RSTTIME2_MASK (0x1f << 8) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 -#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 -#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_SLPCNT_VALUE_SHIFT 16 -#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAMLDO_STATUS_SHIFT 8 -#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 -#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_STARTUP_COUNT_SHIFT 24 -#define AM33XX_STARTUP_COUNT_MASK (0xff << 24) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_TRANSITION_EN_SHIFT 8 -#define AM33XX_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_TRANSITION_ST_SHIFT 8 -#define AM33XX_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_VSETUPCNT_VALUE_SHIFT 8 -#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT0_RST_SHIFT 3 -#define AM33XX_WDT0_RST_MASK (1 << 3) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT1_RST_SHIFT 4 -#define AM33XX_WDT1_RST_MASK (1 << 4) - -/* Used by RM_WKUP_RSTCTRL */ -#define AM33XX_WKUP_M3_LRST_SHIFT 3 -#define AM33XX_WKUP_M3_LRST_MASK (1 << 3) - -/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ -#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 -#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index b0a2142eeb91..cebad565ed37 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -16,115 +16,25 @@ #include "prm3xxx.h" -/* Shared register bits */ - -/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ -#define OMAP3430_ON_SHIFT 24 -#define OMAP3430_ON_MASK (0xff << 24) -#define OMAP3430_ONLP_SHIFT 16 -#define OMAP3430_ONLP_MASK (0xff << 16) -#define OMAP3430_RET_SHIFT 8 -#define OMAP3430_RET_MASK (0xff << 8) -#define OMAP3430_OFF_SHIFT 0 -#define OMAP3430_OFF_MASK (0xff << 0) - -/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ -#define OMAP3430_ERROROFFSET_SHIFT 24 #define OMAP3430_ERROROFFSET_MASK (0xff << 24) -#define OMAP3430_ERRORGAIN_SHIFT 16 #define OMAP3430_ERRORGAIN_MASK (0xff << 16) -#define OMAP3430_INITVOLTAGE_SHIFT 8 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) #define OMAP3430_TIMEOUTEN_MASK (1 << 3) #define OMAP3430_INITVDD_MASK (1 << 2) #define OMAP3430_FORCEUPDATE_MASK (1 << 1) #define OMAP3430_VPENABLE_MASK (1 << 0) - -/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) #define OMAP3430_VSTEPMIN_SHIFT 0 -#define OMAP3430_VSTEPMIN_MASK (0xff << 0) - -/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) #define OMAP3430_VSTEPMAX_SHIFT 0 -#define OMAP3430_VSTEPMAX_MASK (0xff << 0) - -/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ #define OMAP3430_VDDMAX_SHIFT 24 -#define OMAP3430_VDDMAX_MASK (0xff << 24) #define OMAP3430_VDDMIN_SHIFT 16 -#define OMAP3430_VDDMIN_MASK (0xff << 16) #define OMAP3430_TIMEOUT_SHIFT 0 -#define OMAP3430_TIMEOUT_MASK (0xffff << 0) - -/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ -#define OMAP3430_VPVOLTAGE_SHIFT 0 #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) - -/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ -#define OMAP3430_VPINIDLE_MASK (1 << 0) - -/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ #define OMAP3430_EN_PER_SHIFT 7 -#define OMAP3430_EN_PER_MASK (1 << 7) - -/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ -#define OMAP3430_MEMORYCHANGE_MASK (1 << 3) - -/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ #define OMAP3430_LOGICSTATEST_MASK (1 << 2) - -/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) - -/* - * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, - * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, - * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits - */ -#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) - -/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ -#define OMAP3430_WKUP_ST_MASK (1 << 0) - -/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ -#define OMAP3430_WKUP_EN_MASK (1 << 0) - -/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ -#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) -#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) -#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) -#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) -#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) -#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) -#define OMAP3430_GRPSEL_I2C3_SHIFT 17 -#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) -#define OMAP3430_GRPSEL_I2C2_SHIFT 16 -#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) -#define OMAP3430_GRPSEL_I2C1_SHIFT 15 -#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) -#define OMAP3430_GRPSEL_UART2_MASK (1 << 14) -#define OMAP3430_GRPSEL_UART1_MASK (1 << 13) -#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) -#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) -#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) -#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) -#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) -#define OMAP3430_GRPSEL_D2D_MASK (1 << 3) - -/* - * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, - * PM_PWSTCTRL_PER shared bits - */ -#define OMAP3430_MEMONSTATE_SHIFT 16 -#define OMAP3430_MEMONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEMRETSTATE_MASK (1 << 8) - -/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) @@ -132,480 +42,89 @@ #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) -#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) -#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) -#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) -#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) -#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) -#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) -#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) -#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) - -/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ -#define OMAP3430_GRPSEL_IO_MASK (1 << 8) -#define OMAP3430_GRPSEL_SR2_MASK (1 << 7) -#define OMAP3430_GRPSEL_SR1_MASK (1 << 6) #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) - -/* Bits specific to each register */ - -/* RM_RSTCTRL_IVA2 */ #define OMAP3430_RST3_IVA2_MASK (1 << 2) #define OMAP3430_RST2_IVA2_MASK (1 << 1) #define OMAP3430_RST1_IVA2_MASK (1 << 0) - -/* RM_RSTST_IVA2 specific bits */ -#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) -#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) -#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) -#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) -#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) -#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) - -/* PM_WKDEP_IVA2 specific bits */ - -/* PM_PWSTCTRL_IVA2 specific bits */ -#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) -#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) -#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) -#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) - -/* PM_PWSTST_IVA2 specific bits */ -#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) -#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) -#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) -#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) - -/* PM_PREPWSTST_IVA2 specific bits */ -#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) -#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) -#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 -#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 -#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) - -/* PRM_IRQSTATUS_IVA2 specific bits */ -#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) -#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) - -/* PRM_IRQENABLE_IVA2 specific bits */ -#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) -#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) - -/* PRM_REVISION specific bits */ - -/* PRM_SYSCONFIG specific bits */ - -/* PRM_IRQSTATUS_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) -#define OMAP3430_VC_RAERR_ST_MASK (1 << 23) -#define OMAP3430_VC_SAERR_ST_MASK (1 << 22) #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) -#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) -#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) -#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) -#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) -#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) -#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) -#define OMAP3430_IO_ST_MASK (1 << 9) -#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 -#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) #define OMAP3430_MPU_DPLL_ST_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 -#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) #define OMAP3430_CORE_DPLL_ST_SHIFT 5 -#define OMAP3430_TRANSITION_ST_MASK (1 << 4) -#define OMAP3430_EVGENOFF_ST_MASK (1 << 3) -#define OMAP3430_EVGENON_ST_MASK (1 << 2) -#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) - -/* PRM_IRQENABLE_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) -#define OMAP3430_VC_RAERR_EN_MASK (1 << 23) -#define OMAP3430_VC_SAERR_EN_MASK (1 << 22) -#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) -#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) -#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) -#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) -#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) -#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) -#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) -#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) -#define OMAP3430_IO_EN_MASK (1 << 9) -#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 -#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 -#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 -#define OMAP3430_TRANSITION_EN_MASK (1 << 4) -#define OMAP3430_EVGENOFF_EN_MASK (1 << 3) -#define OMAP3430_EVGENON_EN_MASK (1 << 2) -#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) - -/* RM_RSTST_MPU specific bits */ -#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) - -/* PM_WKDEP_MPU specific bits */ #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 -#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 -#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) - -/* PM_EVGENCTRL_MPU */ -#define OMAP3430_OFFLOADMODE_SHIFT 3 -#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) -#define OMAP3430_ONLOADMODE_SHIFT 1 -#define OMAP3430_ONLOADMODE_MASK (0x3 << 1) -#define OMAP3430_ENABLE_MASK (1 << 0) - -/* PM_EVGENONTIM_MPU */ -#define OMAP3430_ONTIMEVAL_SHIFT 0 -#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) - -/* PM_EVGENOFFTIM_MPU */ -#define OMAP3430_OFFTIMEVAL_SHIFT 0 -#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) - -/* PM_PWSTCTRL_MPU specific bits */ -#define OMAP3430_L2CACHEONSTATE_SHIFT 16 -#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) -#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) - -/* PM_PWSTST_MPU specific bits */ -#define OMAP3430_L2CACHESTATEST_SHIFT 6 -#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) -#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) - -/* PM_PREPWSTST_MPU specific bits */ -#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 -#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) - -/* RM_RSTCTRL_CORE */ #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) - -/* RM_RSTST_CORE specific bits */ -#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) - -/* PM_WKEN1_CORE specific bits */ - -/* PM_MPUGRPSEL1_CORE specific bits */ -#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) - -/* PM_IVA2GRPSEL1_CORE specific bits */ - -/* PM_WKST1_CORE specific bits */ - -/* PM_PWSTCTRL_CORE specific bits */ -#define OMAP3430_MEM2ONSTATE_SHIFT 18 -#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) -#define OMAP3430_MEM1ONSTATE_SHIFT 16 -#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEM2RETSTATE_MASK (1 << 9) -#define OMAP3430_MEM1RETSTATE_MASK (1 << 8) - -/* PM_PWSTST_CORE specific bits */ -#define OMAP3430_MEM2STATEST_SHIFT 6 -#define OMAP3430_MEM2STATEST_MASK (0x3 << 6) -#define OMAP3430_MEM1STATEST_SHIFT 4 -#define OMAP3430_MEM1STATEST_MASK (0x3 << 4) - -/* PM_PREPWSTST_CORE specific bits */ -#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) - -/* RM_RSTST_GFX specific bits */ - -/* PM_WKDEP_GFX specific bits */ -#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_GFX specific bits */ - -/* PM_PWSTST_GFX specific bits */ - -/* PM_PREPWSTST_GFX specific bits */ - -/* PM_WKEN_WKUP specific bits */ #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) #define OMAP3430_EN_IO_MASK (1 << 8) #define OMAP3430_EN_GPIO1_MASK (1 << 3) - -/* PM_MPUGRPSEL_WKUP specific bits */ - -/* PM_IVA2GRPSEL_WKUP specific bits */ - -/* PM_WKST_WKUP specific bits */ #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) #define OMAP3430_ST_IO_MASK (1 << 8) - -/* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 -#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 - -/* PRM_CLKOUT_CTRL */ -#define OMAP3430_CLKOUT_EN_MASK (1 << 7) #define OMAP3430_CLKOUT_EN_SHIFT 7 - -/* RM_RSTST_DSS specific bits */ - -/* PM_WKEN_DSS */ #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) - -/* PM_WKDEP_DSS specific bits */ -#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_DSS specific bits */ - -/* PM_PWSTST_DSS specific bits */ - -/* PM_PREPWSTST_DSS specific bits */ - -/* RM_RSTST_CAM specific bits */ - -/* PM_WKDEP_CAM specific bits */ -#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_CAM specific bits */ - -/* PM_PWSTST_CAM specific bits */ - -/* PM_PREPWSTST_CAM specific bits */ - -/* PM_PWSTCTRL_USBHOST specific bits */ #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 - -/* RM_RSTST_PER specific bits */ - -/* PM_WKEN_PER specific bits */ - -/* PM_MPUGRPSEL_PER specific bits */ - -/* PM_IVA2GRPSEL_PER specific bits */ - -/* PM_WKST_PER specific bits */ - -/* PM_WKDEP_PER specific bits */ -#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_PER specific bits */ - -/* PM_PWSTST_PER specific bits */ - -/* PM_PREPWSTST_PER specific bits */ - -/* RM_RSTST_EMU specific bits */ - -/* PM_PWSTST_EMU specific bits */ - -/* PRM_VC_SMPS_SA */ #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) - -/* PRM_VC_SMPS_VOL_RA */ -#define OMAP3430_VOLRA1_SHIFT 16 #define OMAP3430_VOLRA1_MASK (0xff << 16) -#define OMAP3430_VOLRA0_SHIFT 0 #define OMAP3430_VOLRA0_MASK (0xff << 0) - -/* PRM_VC_SMPS_CMD_RA */ -#define OMAP3430_CMDRA1_SHIFT 16 #define OMAP3430_CMDRA1_MASK (0xff << 16) -#define OMAP3430_CMDRA0_SHIFT 0 #define OMAP3430_CMDRA0_MASK (0xff << 0) - -/* PRM_VC_CMD_VAL_0 specific bits */ #define OMAP3430_VC_CMD_ON_SHIFT 24 #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) #define OMAP3430_VC_CMD_ONLP_SHIFT 16 -#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) #define OMAP3430_VC_CMD_RET_SHIFT 8 -#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) #define OMAP3430_VC_CMD_OFF_SHIFT 0 -#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) - -/* PRM_VC_CMD_VAL_1 specific bits */ - -/* PRM_VC_CH_CONF */ -#define OMAP3430_CMD1_MASK (1 << 20) -#define OMAP3430_RACEN1_MASK (1 << 19) -#define OMAP3430_RAC1_MASK (1 << 18) -#define OMAP3430_RAV1_MASK (1 << 17) -#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) -#define OMAP3430_CMD0_MASK (1 << 4) -#define OMAP3430_RACEN0_MASK (1 << 3) -#define OMAP3430_RAC0_MASK (1 << 2) -#define OMAP3430_RAV0_MASK (1 << 1) -#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) - -/* PRM_VC_I2C_CFG */ -#define OMAP3430_HSMASTER_MASK (1 << 5) -#define OMAP3430_SREN_MASK (1 << 4) #define OMAP3430_HSEN_MASK (1 << 3) -#define OMAP3430_MCODE_SHIFT 0 #define OMAP3430_MCODE_MASK (0x7 << 0) - -/* PRM_VC_BYPASS_VAL */ #define OMAP3430_VALID_MASK (1 << 24) #define OMAP3430_DATA_SHIFT 16 -#define OMAP3430_DATA_MASK (0xff << 16) #define OMAP3430_REGADDR_SHIFT 8 -#define OMAP3430_REGADDR_MASK (0xff << 8) #define OMAP3430_SLAVEADDR_SHIFT 0 -#define OMAP3430_SLAVEADDR_MASK (0x7f << 0) - -/* PRM_RSTCTRL */ -#define OMAP3430_RST_DPLL3_MASK (1 << 2) -#define OMAP3430_RST_GS_MASK (1 << 1) - -/* PRM_RSTTIME */ -#define OMAP3430_RSTTIME2_SHIFT 8 -#define OMAP3430_RSTTIME2_MASK (0x1f << 8) -#define OMAP3430_RSTTIME1_SHIFT 0 -#define OMAP3430_RSTTIME1_MASK (0xff << 0) - -/* PRM_RSTST */ #define OMAP3430_ICECRUSHER_RST_SHIFT 10 -#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) #define OMAP3430_ICEPICK_RST_SHIFT 9 -#define OMAP3430_ICEPICK_RST_MASK (1 << 9) #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 -#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 -#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 -#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) #define OMAP3430_SECURE_WD_RST_SHIFT 5 -#define OMAP3430_SECURE_WD_RST_MASK (1 << 5) #define OMAP3430_MPU_WD_RST_SHIFT 4 -#define OMAP3430_MPU_WD_RST_MASK (1 << 4) #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 -#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 -#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) - -/* PRM_VOLTCTRL */ -#define OMAP3430_SEL_VMODE_MASK (1 << 4) #define OMAP3430_SEL_OFF_MASK (1 << 3) #define OMAP3430_AUTO_OFF_MASK (1 << 2) -#define OMAP3430_AUTO_RET_MASK (1 << 1) -#define OMAP3430_AUTO_SLEEP_MASK (1 << 0) - -/* PRM_SRAM_PCHARGE */ -#define OMAP3430_PCHARGE_TIME_SHIFT 0 -#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) - -/* PRM_CLKSRC_CTRL */ -#define OMAP3430_SYSCLKDIV_SHIFT 6 -#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) -#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 -#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) -#define OMAP3430_SYSCLKSEL_SHIFT 0 -#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) - -/* PRM_VOLTSETUP1 */ -#define OMAP3430_SETUP_TIME2_SHIFT 16 #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) -#define OMAP3430_SETUP_TIME1_SHIFT 0 #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) - -/* PRM_VOLTOFFSET */ -#define OMAP3430_OFFSET_TIME_SHIFT 0 -#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) - -/* PRM_CLKSETUP */ -#define OMAP3430_SETUP_TIME_SHIFT 0 -#define OMAP3430_SETUP_TIME_MASK (0xffff << 0) - -/* PRM_POLCTRL */ -#define OMAP3430_OFFMODE_POL_MASK (1 << 3) -#define OMAP3430_CLKOUT_POL_MASK (1 << 2) -#define OMAP3430_CLKREQ_POL_MASK (1 << 1) -#define OMAP3430_EXTVOL_POL_MASK (1 << 0) - -/* PRM_VOLTSETUP2 */ -#define OMAP3430_OFFMODESETUPTIME_SHIFT 0 -#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) - -/* PRM_VP1_CONFIG specific bits */ - -/* PRM_VP1_VSTEPMIN specific bits */ - -/* PRM_VP1_VSTEPMAX specific bits */ - -/* PRM_VP1_VLIMITTO specific bits */ - -/* PRM_VP1_VOLTAGE specific bits */ - -/* PRM_VP1_STATUS specific bits */ - -/* PRM_VP2_CONFIG specific bits */ - -/* PRM_VP2_VSTEPMIN specific bits */ - -/* PRM_VP2_VSTEPMAX specific bits */ - -/* PRM_VP2_VLIMITTO specific bits */ - -/* PRM_VP2_VOLTAGE specific bits */ - -/* PRM_VP2_STATUS specific bits */ - -/* RM_RSTST_NEON specific bits */ - -/* PM_WKDEP_NEON specific bits */ - -/* PM_PWSTCTRL_NEON specific bits */ - -/* PM_PWSTST_NEON specific bits */ - -/* PM_PREPWSTST_NEON specific bits */ - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 3cb247bebdaa..b1c7a33e00e7 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -22,2306 +22,80 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_RA_ERR_SHIFT 25 -#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_SA_ERR_SHIFT 24 -#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 -#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) - -/* Used by PRM_RSTST */ #define OMAP4430_C2C_RST_SHIFT 10 -#define OMAP4430_C2C_RST_MASK (1 << 10) - -/* Used by PM_CAM_PWRSTCTRL */ -#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CAM_PWRSTST */ -#define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_CLKREQCTRL */ -#define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK (0xff << 16) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK (1 << 6) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSS_PWRSTST */ -#define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8 -#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9 -#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) - -/* Used by PM_EMU_PWRSTCTRL */ -#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_EMU_PWRSTST */ -#define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 -#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 -#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK (1 << 6) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERRORGAIN_SHIFT 16 #define OMAP4430_ERRORGAIN_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERROROFFSET_SHIFT 24 #define OMAP4430_ERROROFFSET_MASK (0xff << 24) - -/* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_FORCEUPDATE_SHIFT 1 #define OMAP4430_FORCEUPDATE_MASK (1 << 1) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ -#define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) - -/* Used by PM_GFX_PWRSTCTRL */ -#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_GFX_PWRSTST */ -#define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_GLOBAL_WUEN_SHIFT 16 #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMCODE_SHIFT 0 #define OMAP4430_HSMCODE_MASK (0x7 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMODEEN_SHIFT 3 #define OMAP4430_HSMODEEN_MASK (1 << 3) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK (0xff << 24) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) - -/* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK (1 << 9) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVDD_SHIFT 2 #define OMAP4430_INITVDD_MASK (1 << 2) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVOLTAGE_SHIFT 8 #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) - -/* Used by PRM_IO_COUNT */ -#define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* - * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ #define OMAP4430_LOGICSTATEST_SHIFT 2 #define OMAP4430_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, - * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, - * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, - * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, - * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, - * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, - * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, - * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, - * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, - * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, - * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, - * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, - * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, - * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, - * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, - * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, - * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, - * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, - * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, - * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, - * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, - * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) - -/* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) - -/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) - -/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) - -/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) - -/* Used by RM_L3_2_OCMC_RAM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, - * RM_SDMA_SDMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) - -/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) - -/* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) - -/* Used by RM_GFX_GFX_CONTEXT */ -#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) - -/* - * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, - * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT - */ -#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) - -/* - * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT - */ -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) - -/* - * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, - * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT - */ -#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) - -/* - * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_CRYPTODMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) - -/* Used by RM_IVAHD_SL2_CONTEXT */ -#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) - -/* Used by RM_WKUP_SARRAM_CONTEXT */ -#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK (1 << 1) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK (0xff << 0) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_ON_SHIFT 24 #define OMAP4430_ON_MASK (0xff << 24) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK (0xff << 16) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK (1 << 2) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK (0x3 << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_PHASE1_CNDP */ -#define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2A_CNDP */ -#define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2B_CNDP */ -#define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ -#define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK (0x3 << 0) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PRM_PWRREQCTRL */ -#define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK (0xff << 8) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK (0xff << 8) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ -#define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ -#define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ -#define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ -#define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK (1 << 2) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK (1 << 2) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK (0x1f << 10) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) - -/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) - -/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) - -/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) - -/* Used by REVISION_PRM */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK (0xff << 0) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK (0xff << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 -#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 -#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 -#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 -#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK (1 << 0) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK (1 << 4) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_LDO_BANDGAP_SETUP */ -#define OMAP4430_STARTUP_COUNT_SHIFT 0 -#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK (0xffff << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_TIMEOUTEN_SHIFT 3 #define OMAP4430_TIMEOUTEN_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_VALID_SHIFT 24 #define OMAP4430_VALID_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK (0xff << 24) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK (0xff << 16) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 -#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 -#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 -#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 -#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_VPENABLE_SHIFT 0 #define OMAP4430_VPENABLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_VPVOLTAGE_SHIFT 0 #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK (0xff << 0) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK (0xff << 0) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_DMTIMER10_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER2_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) - -/* Used by PM_L4PER_HECC1_WKDEP */ -#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_HECC2_WKDEP */ -#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_KEYBOARD_WKDEP */ -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_WKUP_RTC_WKDEP */ -#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) - -/* Used by PM_ALWON_SR_MPU_WKDEP */ -#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_TIMER12_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_TIMER1_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_WDT3_WKDEP */ -#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) - -/* Used by PM_L3INIT_XHPI_WKDEP */ -#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_CTRL_SHIFT 8 #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) - -/* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h deleted file mode 100644 index be31b21aa9c6..000000000000 --- a/arch/arm/mach-omap2/prm-regbits-54xx.h +++ /dev/null @@ -1,2701 +0,0 @@ -/* - * OMAP54xx Power Management register bits - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ABBOFF_ACT_SHIFT 1 -#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 -#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 -#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 -#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 -#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 -#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 -#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 -#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 -#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 -#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 -#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP54XX_AESSMEM_STATEST_SHIFT 4 -#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 -#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_AIPOFF_SHIFT 8 -#define OMAP54XX_AIPOFF_WIDTH 0x1 -#define OMAP54XX_AIPOFF_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_RA_ERR_SHIFT 1 -#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_SA_ERR_SHIFT 0 -#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 -#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_C2C_RST_SHIFT 10 -#define OMAP54XX_C2C_RST_WIDTH 0x1 -#define OMAP54XX_C2C_RST_MASK (1 << 10) - -/* Used by PM_CAM_PWRSTCTRL */ -#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CAM_PWRSTST */ -#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 -#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_CLKREQCTRL */ -#define OMAP54XX_CLKREQ_COND_SHIFT 0 -#define OMAP54XX_CLKREQ_COND_WIDTH 0x3 -#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 -#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP54XX_CUSTOM_SHIFT 6 -#define OMAP54XX_CUSTOM_WIDTH 0x2 -#define OMAP54XX_CUSTOM_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_DATA_SHIFT 16 -#define OMAP54XX_DATA_WIDTH 0x8 -#define OMAP54XX_DATA_MASK (0xff << 16) - -/* Used by PRM_DEBUG_CORE_RET_TRANS */ -#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 -#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c -#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa -#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 -#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 -#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc -#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 -#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_DFILTEREN_SHIFT 6 -#define OMAP54XX_DFILTEREN_WIDTH 0x1 -#define OMAP54XX_DFILTEREN_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 -#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 -#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 -#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 -#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 -#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_L1_STATEST_SHIFT 4 -#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 -#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 -#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_L2_STATEST_SHIFT 6 -#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSS_PWRSTST */ -#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 -#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) - -/* Used by PM_EMU_PWRSTCTRL */ -#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_EMU_PWRSTST */ -#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 -#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, - * PRM_SRAM_WKUP_SETUP - */ -#define OMAP54XX_ENABLE_RTA_SHIFT 0 -#define OMAP54XX_ENABLE_RTA_WIDTH 0x1 -#define OMAP54XX_ENABLE_RTA_MASK (1 << 0) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC1_SHIFT 3 -#define OMAP54XX_ENFUNC1_WIDTH 0x1 -#define OMAP54XX_ENFUNC1_MASK (1 << 3) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC2_SHIFT 4 -#define OMAP54XX_ENFUNC2_WIDTH 0x1 -#define OMAP54XX_ENFUNC2_MASK (1 << 4) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC3_SHIFT 5 -#define OMAP54XX_ENFUNC3_WIDTH 0x1 -#define OMAP54XX_ENFUNC3_MASK (1 << 5) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC4_SHIFT 6 -#define OMAP54XX_ENFUNC4_WIDTH 0x1 -#define OMAP54XX_ENFUNC4_MASK (1 << 6) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC5_SHIFT 7 -#define OMAP54XX_ENFUNC5_WIDTH 0x1 -#define OMAP54XX_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_ERRORGAIN_SHIFT 16 -#define OMAP54XX_ERRORGAIN_WIDTH 0x8 -#define OMAP54XX_ERRORGAIN_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_ERROROFFSET_SHIFT 24 -#define OMAP54XX_ERROROFFSET_WIDTH 0x8 -#define OMAP54XX_ERROROFFSET_MASK (0xff << 24) - -/* Used by PRM_RSTST */ -#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 -#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_FORCEUPDATE_SHIFT 1 -#define OMAP54XX_FORCEUPDATE_WIDTH 0x1 -#define OMAP54XX_FORCEUPDATE_MASK (1 << 1) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 -#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ -#define OMAP54XX_FORCEWKUP_EN_SHIFT 10 -#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 -#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ -#define OMAP54XX_FORCEWKUP_ST_SHIFT 10 -#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 -#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP54XX_FUNC_SHIFT 16 -#define OMAP54XX_FUNC_WIDTH 0xc -#define OMAP54XX_FUNC_MASK (0xfff << 16) - -/* Used by PRM_RSTST */ -#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 -#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 -#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_GLOBAL_WUEN_SHIFT 16 -#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 -#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) - -/* Used by PM_GPU_PWRSTCTRL */ -#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_GPU_PWRSTST */ -#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 -#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_HSMCODE_SHIFT 0 -#define OMAP54XX_HSMCODE_WIDTH 0x3 -#define OMAP54XX_HSMCODE_MASK (0x7 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_HSMODEEN_SHIFT 3 -#define OMAP54XX_HSMODEEN_WIDTH 0x1 -#define OMAP54XX_HSMODEEN_MASK (1 << 3) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_HSSCLH_SHIFT 16 -#define OMAP54XX_HSSCLH_WIDTH 0x8 -#define OMAP54XX_HSSCLH_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_HSSCLL_SHIFT 24 -#define OMAP54XX_HSSCLL_WIDTH 0x8 -#define OMAP54XX_HSSCLL_MASK (0xff << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 -#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ -#define OMAP54XX_ICEPICK_RST_SHIFT 9 -#define OMAP54XX_ICEPICK_RST_WIDTH 0x1 -#define OMAP54XX_ICEPICK_RST_MASK (1 << 9) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_INITVDD_SHIFT 2 -#define OMAP54XX_INITVDD_WIDTH 0x1 -#define OMAP54XX_INITVDD_MASK (1 << 2) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_INITVOLTAGE_SHIFT 8 -#define OMAP54XX_INITVOLTAGE_WIDTH 0x8 -#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, - * PRM_VOLTST_MM, PRM_VOLTST_MPU - */ -#define OMAP54XX_INTRANSITION_SHIFT 20 -#define OMAP54XX_INTRANSITION_WIDTH 0x1 -#define OMAP54XX_INTRANSITION_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_IO_EN_SHIFT 9 -#define OMAP54XX_IO_EN_WIDTH 0x1 -#define OMAP54XX_IO_EN_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_IO_ON_STATUS_SHIFT 5 -#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 -#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_IO_ST_SHIFT 9 -#define OMAP54XX_IO_ST_WIDTH 0x1 -#define OMAP54XX_IO_ST_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 -#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 -#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 -#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 -#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 -#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 -#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 -#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 -#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 -#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOCLK_STATUS_SHIFT 1 -#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 -#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 -#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 -#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) - -/* Used by PRM_IO_COUNT */ -#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 -#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 -#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 -#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 -#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 -#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 -#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 -#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 -#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* Used by PRM_RSTST */ -#define OMAP54XX_LLI_RST_SHIFT 14 -#define OMAP54XX_LLI_RST_WIDTH 0x1 -#define OMAP54XX_LLI_RST_MASK (1 << 14) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, - * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_LOGICRETSTATE_SHIFT 2 -#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 -#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_LOGICSTATEST_SHIFT 2 -#define OMAP54XX_LOGICSTATEST_WIDTH 0x1 -#define OMAP54XX_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, - * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, - * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, - * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, - * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, - * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, - * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, - * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, - * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, - * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, - * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, - * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, - * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, - * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, - * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, - * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, - * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, - * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, - * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, - * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, - * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, - * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, - * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, - * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, - * RM_WKUPAON_WD_TIMER2_CONTEXT - */ -#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 -#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) - -/* - * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, - * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, - * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, - * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, - * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, - * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, - * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, - * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, - * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, - * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, - * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT - */ -#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 -#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) - -/* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) - -/* Used by RM_CAM_CAL_CONTEXT */ -#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) - -/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) - -/* Used by RM_EMIF_DMM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) - -/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) - -/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) - -/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 -#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 -#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 -#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) - -/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) - -/* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) - -/* Used by RM_GPU_GPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) - -/* Used by RM_IPU_IPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 -#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) - -/* Used by RM_IPU_IPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) - -/* - * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, - * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, - * RM_L3INIT_USB_OTG_SS_CONTEXT - */ -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) - -/* - * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, - * RM_L4SEC_FPKA_CONTEXT - */ -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) - -/* - * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, - * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT - */ -#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) - -/* - * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, - * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT - */ -#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) - -/* Used by RM_IVA_SL2_CONTEXT */ -#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) - -/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ -#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, - * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 -#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PRM_DEBUG_TRANS_CFG */ -#define OMAP54XX_MODE_SHIFT 0 -#define OMAP54XX_MODE_WIDTH 0x2 -#define OMAP54XX_MODE_MASK (0x3 << 0) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 -#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP54XX_MPU_L2_STATEST_SHIFT 6 -#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 -#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 -#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 -#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 -#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_MPU_WDT_RST_SHIFT 3 -#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 -#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_NOCAP_SHIFT 4 -#define OMAP54XX_NOCAP_WIDTH 0x1 -#define OMAP54XX_NOCAP_MASK (1 << 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_OFF_SHIFT 0 -#define OMAP54XX_OFF_WIDTH 0x8 -#define OMAP54XX_OFF_MASK (0xff << 0) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_ON_SHIFT 24 -#define OMAP54XX_ON_WIDTH 0x8 -#define OMAP54XX_ON_MASK (0xff << 24) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_ONLP_SHIFT 16 -#define OMAP54XX_ONLP_WIDTH 0x8 -#define OMAP54XX_ONLP_MASK (0xff << 16) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_OPP_CHANGE_SHIFT 2 -#define OMAP54XX_OPP_CHANGE_WIDTH 0x1 -#define OMAP54XX_OPP_CHANGE_MASK (1 << 2) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_OPP_SEL_SHIFT 0 -#define OMAP54XX_OPP_SEL_WIDTH 0x2 -#define OMAP54XX_OPP_SEL_MASK (0x3 << 0) - -/* Used by PRM_DEBUG_OUT */ -#define OMAP54XX_OUTPUT_SHIFT 0 -#define OMAP54XX_OUTPUT_WIDTH 0x20 -#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 -#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP54XX_PCHARGE_TIME_SHIFT 0 -#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 -#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 -#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_PHASE1_CNDP */ -#define OMAP54XX_PHASE1_CNDP_SHIFT 0 -#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2A_CNDP */ -#define OMAP54XX_PHASE2A_CNDP_SHIFT 0 -#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2B_CNDP */ -#define OMAP54XX_PHASE2B_CNDP_SHIFT 0 -#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, - * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, - * PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_POWERSTATE_SHIFT 0 -#define OMAP54XX_POWERSTATE_WIDTH 0x2 -#define OMAP54XX_POWERSTATE_MASK (0x3 << 0) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_POWERSTATEST_SHIFT 0 -#define OMAP54XX_POWERSTATEST_WIDTH 0x2 -#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PRM_PWRREQCTRL */ -#define OMAP54XX_PWRREQ_COND_SHIFT 0 -#define OMAP54XX_PWRREQ_COND_WIDTH 0x2 -#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 -#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 -#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 -#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 -#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 -#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_REGADDR_SHIFT 8 -#define OMAP54XX_REGADDR_WIDTH 0x8 -#define OMAP54XX_REGADDR_MASK (0xff << 8) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_RET_SHIFT 8 -#define OMAP54XX_RET_WIDTH 0x8 -#define OMAP54XX_RET_MASK (0xff << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_RETMODE_ENABLE_SHIFT 0 -#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 -#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP54XX_RSTTIME1_SHIFT 0 -#define OMAP54XX_RSTTIME1_WIDTH 0xa -#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP54XX_RSTTIME2_SHIFT 10 -#define OMAP54XX_RSTTIME2_WIDTH 0x5 -#define OMAP54XX_RSTTIME2_MASK (0x1f << 10) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_CPU0_SHIFT 0 -#define OMAP54XX_RST_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_CPU0_MASK (1 << 0) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_CPU1_SHIFT 1 -#define OMAP54XX_RST_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_CPU1_MASK (1 << 1) - -/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_SHIFT 0 -#define OMAP54XX_RST_DSP_WIDTH 0x1 -#define OMAP54XX_RST_DSP_MASK (1 << 0) - -/* Used by RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_EMU_SHIFT 2 -#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 -#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) - -/* Used by RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 -#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 -#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) - -/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 -#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 -#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 -#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 -#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 -#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 -#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) - -/* Used by PRM_RSTCTRL */ -#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 -#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 -#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 -#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 -#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 -#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 -#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 -#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 -#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_LOGIC_SHIFT 2 -#define OMAP54XX_RST_LOGIC_WIDTH 0x1 -#define OMAP54XX_RST_LOGIC_MASK (1 << 2) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_SEQ1_SHIFT 0 -#define OMAP54XX_RST_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_SEQ1_MASK (1 << 0) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_SEQ2_SHIFT 1 -#define OMAP54XX_RST_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_SEQ2_MASK (1 << 1) - -/* Used by REVISION_PRM */ -#define OMAP54XX_R_RTL_SHIFT 11 -#define OMAP54XX_R_RTL_WIDTH 0x5 -#define OMAP54XX_R_RTL_MASK (0x1f << 11) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 -#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_SA_VDD_MM_L_SHIFT 0 -#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 -#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) - -/* Used by REVISION_PRM */ -#define OMAP54XX_SCHEME_SHIFT 30 -#define OMAP54XX_SCHEME_WIDTH 0x2 -#define OMAP54XX_SCHEME_MASK (0x3 << 30) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_SCLH_SHIFT 0 -#define OMAP54XX_SCLH_WIDTH 0x8 -#define OMAP54XX_SCLH_MASK (0xff << 0) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_SCLL_SHIFT 8 -#define OMAP54XX_SCLL_WIDTH 0x8 -#define OMAP54XX_SCLL_MASK (0xff << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_SECURE_WDT_RST_SHIFT 4 -#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 -#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 -#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_SLAVEADDR_SHIFT 0 -#define OMAP54XX_SLAVEADDR_WIDTH 0x7 -#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_SLPCNT_VALUE_SHIFT 16 -#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 -#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 -#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_SR2EN_SHIFT 0 -#define OMAP54XX_SR2EN_WIDTH 0x1 -#define OMAP54XX_SR2EN_MASK (1 << 0) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 -#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_SR2_STATUS_SHIFT 3 -#define OMAP54XX_SR2_STATUS_WIDTH 0x2 -#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 -#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 -#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 -#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_SRMODEEN_SHIFT 4 -#define OMAP54XX_SRMODEEN_WIDTH 0x1 -#define OMAP54XX_SRMODEEN_MASK (1 << 4) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP54XX_STABLE_COUNT_SHIFT 0 -#define OMAP54XX_STABLE_COUNT_WIDTH 0x6 -#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP54XX_STABLE_PRESCAL_SHIFT 8 -#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 -#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_BANDGAP_SETUP */ -#define OMAP54XX_STARTUP_COUNT_SHIFT 0 -#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 -#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 -#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_TIMEOUT_SHIFT 0 -#define OMAP54XX_TIMEOUT_WIDTH 0x10 -#define OMAP54XX_TIMEOUT_MASK (0xffff << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_TIMEOUTEN_SHIFT 3 -#define OMAP54XX_TIMEOUTEN_WIDTH 0x1 -#define OMAP54XX_TIMEOUTEN_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_TRANSITION_EN_SHIFT 8 -#define OMAP54XX_TRANSITION_EN_WIDTH 0x1 -#define OMAP54XX_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_TRANSITION_ST_SHIFT 8 -#define OMAP54XX_TRANSITION_ST_WIDTH 0x1 -#define OMAP54XX_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_DEBUG_TRANS_CFG */ -#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 -#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 -#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 -#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_MM_RST_SHIFT 12 -#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 -#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_VALID_SHIFT 24 -#define OMAP54XX_VALID_WIDTH 0x1 -#define OMAP54XX_VALID_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 -#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 -#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_RAERR_EN_SHIFT 12 -#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_RAERR_ST_SHIFT 12 -#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_SAERR_EN_SHIFT 11 -#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_SAERR_ST_SHIFT 11 -#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_TOERR_EN_SHIFT 13 -#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_TOERR_ST_SHIFT 13 -#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_VDDMAX_SHIFT 24 -#define OMAP54XX_VDDMAX_WIDTH 0x8 -#define OMAP54XX_VDDMAX_MASK (0xff << 24) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_VDDMIN_SHIFT 16 -#define OMAP54XX_VDDMIN_WIDTH 0x8 -#define OMAP54XX_VDDMIN_MASK (0xff << 16) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 -#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 -#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 -#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) - -/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ -#define OMAP54XX_VOLTSTATEST_SHIFT 0 -#define OMAP54XX_VOLTSTATEST_WIDTH 0x2 -#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_VPENABLE_SHIFT 0 -#define OMAP54XX_VPENABLE_WIDTH 0x1 -#define OMAP54XX_VPENABLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP54XX_VPINIDLE_SHIFT 0 -#define OMAP54XX_VPINIDLE_WIDTH 0x1 -#define OMAP54XX_VPINIDLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP54XX_VPVOLTAGE_SHIFT 0 -#define OMAP54XX_VPVOLTAGE_WIDTH 0x8 -#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 -#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 -#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 -#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 -#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 -#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 -#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 -#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 -#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 -#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 -#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP54XX_VSTEPMAX_SHIFT 0 -#define OMAP54XX_VSTEPMAX_WIDTH 0x8 -#define OMAP54XX_VSTEPMAX_MASK (0xff << 0) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP54XX_VSTEPMIN_SHIFT 0 -#define OMAP54XX_VSTEPMIN_WIDTH 0x8 -#define OMAP54XX_VSTEPMIN_MASK (0xff << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO7_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO8_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_KBD_WKDEP */ -#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC4_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC4_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC5_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC5_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) - -/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER10_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER11_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER11_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_TIMER12_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_TIMER1_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER2_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER4_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER4_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER9_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER9_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART5_WKDEP */ -#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART5_WKDEP */ -#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART6_WKDEP */ -#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART6_WKDEP */ -#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_UNIPRO2_WKDEP */ -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_WD_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_WUCLK_CTRL_SHIFT 8 -#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 -#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_WUCLK_STATUS_SHIFT 9 -#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 -#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP54XX_X_MAJOR_SHIFT 8 -#define OMAP54XX_X_MAJOR_WIDTH 0x3 -#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP54XX_Y_MINOR_SHIFT 0 -#define OMAP54XX_Y_MINOR_WIDTH 0x6 -#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) -#endif diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 8c616e436bc7..4588df1447ed 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -8,6 +8,7 @@ * Written by Tony Lindgren <tony.lindgren@nokia.com> * * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,6 +36,7 @@ #ifndef __ASSEMBLY__ #include <linux/bitops.h> +#include <linux/of.h> /* * Test if multicore OMAP support is needed @@ -105,6 +107,15 @@ # endif #endif +#ifdef CONFIG_SOC_DRA7XX +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME DRA7XX +# endif +#endif + /* * Omap device type i.e. EMU/HS/TST/GP/BAD */ @@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437) #define cpu_is_omap447x() 0 #define soc_is_omap54xx() 0 #define soc_is_omap543x() 0 +#define soc_is_dra7xx() 0 #if defined(MULTI_OMAP2) # if defined(CONFIG_ARCH_OMAP2) @@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430) # define soc_is_omap543x() is_omap543x() #endif +#if defined(CONFIG_SOC_DRA7XX) +#undef soc_is_dra7xx +#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) +#endif + /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 #define OMAP2420_REV_ES1_0 OMAP242X_CLASS diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b37e1fcbad56..fa74a0625da1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -537,7 +537,7 @@ static void __init realtime_counter_init(void) reg |= num; __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); - reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); @@ -594,13 +594,14 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 1, "timer_sys_ck", "ti,timer-alwon"); #endif -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 2, "sys_clkin_ck", NULL); #endif #ifdef CONFIG_ARCH_OMAP4 -#ifdef CONFIG_LOCAL_TIMERS +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); void __init omap4_local_timer_init(void) { @@ -619,12 +620,12 @@ void __init omap4_local_timer_init(void) pr_err("twd_local_timer_register failed %d\n", err); } } -#else /* CONFIG_LOCAL_TIMERS */ +#else void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); } -#endif /* CONFIG_LOCAL_TIMERS */ +#endif /* CONFIG_HAVE_ARM_TWD */ #endif /* CONFIG_ARCH_OMAP4 */ #ifdef CONFIG_SOC_OMAP5 diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 2eb19d4d0aa1..e83a6a4b184a 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,7 +28,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/usb/phy.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include "soc.h" #include "omap_device.h" @@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = { /* .init_data filled later */ }; -static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */ +static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */ static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ /** @@ -460,9 +460,9 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) pdevinfo.name = nop_name; pdevinfo.id = phy->port; pdevinfo.data = phy->platform_data; - pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data); - - scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d", + pdevinfo.size_data = + sizeof(struct usb_phy_gen_xceiv_platform_data); + scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", phy->port); pdev = platform_device_register_full(&pdevinfo); if (IS_ERR(pdev)) { diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 8c4de2708cf2..bc897231bd10 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -38,11 +38,8 @@ static struct musb_hdrc_config musb_config = { }; static struct musb_hdrc_platform_data musb_plat = { -#ifdef CONFIG_USB_GADGET_MUSB_HDRC .mode = MUSB_OTG, -#else - .mode = MUSB_HOST, -#endif + /* .clock is set dynamically */ .config = &musb_config, diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index b41599f98a8e..91a5852b44f3 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -174,8 +174,10 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, + ORION_MBUS_SRAM_ATTR, + ORION5X_SRAM_PHYS_BASE, + ORION5X_SRAM_SIZE); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } @@ -222,22 +224,24 @@ void orion5x_setup_wins(void) * The PCIe windows will no longer be statically allocated * here once Orion5x is migrated to the pci-mvebu driver. */ - mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE, + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, + ORION_MBUS_PCIE_IO_ATTR, + ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - ORION5X_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE, - ORION5X_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE, + ORION5X_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, + ORION_MBUS_PCIE_MEM_ATTR, + ORION5X_PCIE_MEM_PHYS_BASE, + ORION5X_PCIE_MEM_SIZE); + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, + ORION_MBUS_PCI_IO_ATTR, + ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - ORION5X_PCI_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE, - ORION5X_PCI_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); + ORION5X_PCI_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, + ORION_MBUS_PCI_MEM_ATTR, + ORION5X_PCI_MEM_PHYS_BASE, + ORION5X_PCI_MEM_SIZE); } int orion5x_tclk; diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index a909afb384fb..f565f9944af2 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -7,6 +7,23 @@ struct dsa_platform_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; +#define ORION_MBUS_PCIE_MEM_TARGET 0x04 +#define ORION_MBUS_PCIE_MEM_ATTR 0x59 +#define ORION_MBUS_PCIE_IO_TARGET 0x04 +#define ORION_MBUS_PCIE_IO_ATTR 0x51 +#define ORION_MBUS_PCIE_WA_TARGET 0x04 +#define ORION_MBUS_PCIE_WA_ATTR 0x79 +#define ORION_MBUS_PCI_MEM_TARGET 0x03 +#define ORION_MBUS_PCI_MEM_ATTR 0x59 +#define ORION_MBUS_PCI_IO_TARGET 0x03 +#define ORION_MBUS_PCI_IO_ATTR 0x51 +#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01 +#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f +#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 +#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) +#define ORION_MBUS_SRAM_TARGET 0x00 +#define ORION_MBUS_SRAM_ATTR 0x00 + /* * Basic Orion init functions used early by machine-setup. */ diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 16c88bbabc98..8f68b745c1d5 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -317,8 +317,10 @@ static void __init d2net_init(void) d2net_sata_power_init(); orion5x_sata_init(&d2net_sata_data); - mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE, - D2NET_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + D2NET_NOR_BOOT_BASE, + D2NET_NOR_BOOT_SIZE); platform_device_register(&d2net_nor_flash); platform_device_register(&d2net_gpio_buttons); diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 4e1263da38bb..4b2aefd1d961 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -340,19 +340,27 @@ static void __init db88f5281_init(void) orion5x_uart0_init(); orion5x_uart1_init(); - mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); platform_device_register(&db88f5281_boot_flash); - mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), + ORION_MBUS_DEVBUS_ATTR(0), + DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE); - mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE, - DB88F5281_NOR_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), + ORION_MBUS_DEVBUS_ATTR(1), + DB88F5281_NOR_BASE, + DB88F5281_NOR_SIZE); platform_device_register(&db88f5281_nor_flash); - mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE, - DB88F5281_NAND_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), + ORION_MBUS_DEVBUS_ATTR(2), + DB88F5281_NAND_BASE, + DB88F5281_NAND_SIZE); platform_device_register(&db88f5281_nand_flash); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 9e6baf581ed3..70974732cbf0 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -611,8 +611,10 @@ static void __init dns323_init(void) /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE, - DNS323_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + DNS323_NOR_BOOT_BASE, + DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); /* Sort out LEDs, Buttons and i2c devices */ diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index 147615510dd0..f66c1b2ee8c1 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -23,8 +23,8 @@ #include <linux/platform_device.h> #include <linux/pci.h> #include <linux/irq.h> +#include <linux/mbus.h> #include <linux/mtd/physmap.h> -#include <linux/mv643xx_eth.h> #include <linux/leds.h> #include <linux/gpio_keys.h> #include <linux/input.h> @@ -96,14 +96,6 @@ static struct platform_device edmini_v2_nor_flash = { }; /***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data edmini_v2_eth_data = { - .phy_addr = 8, -}; - -/***************************************************************************** * RTC 5C372a on I2C bus ****************************************************************************/ @@ -152,10 +144,11 @@ void __init edmini_v2_init(void) * Configure peripherals. */ orion5x_ehci0_init(); - orion5x_eth_init(&edmini_v2_eth_data); - mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE, - EDMINI_V2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + EDMINI_V2_NOR_BOOT_BASE, + EDMINI_V2_NOR_BOOT_SIZE); platform_device_register(&edmini_v2_nor_flash); pr_notice("edmini_v2: USB device port, flash write and power-off " diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S deleted file mode 100644 index f340ed8f8dd0..000000000000 --- a/arch/arm/mach-orion5x/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/debug-macro.S - * - * Debugging macro include header - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/orion5x.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =ORION5X_REGS_PHYS_BASE - ldr \rv, =ORION5X_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index aae10e4a917c..fe6a48a325e8 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void) orion5x_uart1_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); platform_device_register(&kurobox_pro_nor_flash); if (machine_is_kurobox_pro()) { - mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE, - KUROBOX_PRO_NAND_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), + ORION_MBUS_DEVBUS_ATTR(0), + KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE); platform_device_register(&kurobox_pro_nand_flash); } diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 6234977b5aea..028ea038d404 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -294,8 +294,10 @@ static void __init lschl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE, - LSCHL_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LSCHL_NOR_BOOT_BASE, + LSCHL_NOR_BOOT_SIZE); platform_device_register(&lschl_nor_flash); platform_device_register(&lschl_leds); diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index fe04c4b64569..32b7129b767d 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -243,8 +243,10 @@ static void __init ls_hgl_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE, - LS_HGL_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LS_HGL_NOR_BOOT_BASE, + LS_HGL_NOR_BOOT_SIZE); platform_device_register(&ls_hgl_nor_flash); platform_device_register(&ls_hgl_button_device); diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index ca4dbe973daf..a6493e76f96d 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -244,8 +244,10 @@ static void __init lsmini_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE, - LSMINI_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + LSMINI_NOR_BOOT_BASE, + LSMINI_NOR_BOOT_SIZE); platform_device_register(&lsmini_nor_flash); platform_device_register(&lsmini_button_device); diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 827acbafc9dc..e105130ba51c 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -241,8 +241,10 @@ static void __init mss2_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE, - MSS2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + MSS2_NOR_BOOT_BASE, + MSS2_NOR_BOOT_SIZE); platform_device_register(&mss2_nor_flash); platform_device_register(&mss2_button_device); diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 92600ae2b4b6..e032f01da49e 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -204,8 +204,10 @@ static void __init mv2120_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE, - MV2120_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + MV2120_NOR_BOOT_BASE, + MV2120_NOR_BOOT_SIZE); platform_device_register(&mv2120_nor_flash); platform_device_register(&mv2120_button_device); diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index dd0641a0d074..ba73dc7ffb9e 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -397,8 +397,10 @@ static void __init net2big_init(void) net2big_sata_power_init(); orion5x_sata_init(&net2big_sata_data); - mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE, - NET2BIG_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + NET2BIG_NOR_BOOT_BASE, + NET2BIG_NOR_BOOT_SIZE); platform_device_register(&net2big_nor_flash); platform_device_register(&net2big_gpio_buttons); diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 503368023bb1..7fab67053030 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys) if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " "read transaction workaround\n"); - mvebu_mbus_add_window_remap_flags("pcie0.0", - ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_WA); + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET, + ORION_MBUS_PCIE_WA_ATTR, + ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); pcie_ops.read = pcie_rd_conf_wa; } diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 1c4498bf650a..213b3e143c57 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void) orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE, - RD88F5181L_FXO_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5181L_FXO_NOR_BOOT_BASE, + RD88F5181L_FXO_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_fxo_nor_boot_flash); } diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index adabe34c4fc6..594800e1d691 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void) orion5x_i2c_init(); orion5x_uart0_init(); - mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE, - RD88F5181L_GE_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5181L_GE_NOR_BOOT_BASE, + RD88F5181L_GE_NOR_BOOT_SIZE); platform_device_register(&rd88f5181l_ge_nor_boot_flash); i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 66e77ec91532..b1cf68493ffc 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -264,11 +264,14 @@ static void __init rd88f5182_init(void) orion5x_uart0_init(); orion5x_xor_init(); - mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - - mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE, - RD88F5182_NOR_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), + ORION_MBUS_DEVBUS_ATTR(1), + RD88F5182_NOR_BASE, + RD88F5182_NOR_SIZE); platform_device_register(&rd88f5182_nor_flash); platform_device_register(&rd88f5182_gpio_leds); diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index a0bfa53e7556..7e9064844698 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -329,8 +329,10 @@ static void __init tsp2_init(void) /* * Configure peripherals. */ - mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE, - TSP2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + TSP2_NOR_BOOT_BASE, + TSP2_NOR_BOOT_SIZE); platform_device_register(&tsp2_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 80174f0f168e..e90c0618fdad 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void) /* * Configure peripherals. */ - mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); platform_device_register(&qnap_ts209_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 92592790d6da..5c079d312015 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void) /* * Configure peripherals. */ - mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE, - QNAP_TS409_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + QNAP_TS409_NOR_BOOT_BASE, + QNAP_TS409_NOR_BOOT_SIZE); platform_device_register(&qnap_ts409_nor_flash); orion5x_ehci0_init(); diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 6b84863c018d..80a56ee245b3 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -127,8 +127,10 @@ static void __init wnr854t_init(void) orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE, - WNR854T_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + WNR854T_NOR_BOOT_BASE, + WNR854T_NOR_BOOT_SIZE); platform_device_register(&wnr854t_nor_flash); } diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index fae684bc54f2..670e30dc0d1b 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void) orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); orion5x_uart0_init(); - mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE, - WRT350N_V2_NOR_BOOT_SIZE); + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, + ORION_MBUS_DEVBUS_BOOT_ATTR, + WRT350N_V2_NOR_BOOT_BASE, + WRT350N_V2_NOR_BOOT_SIZE); platform_device_register(&wrt350n_v2_nor_flash); platform_device_register(&wrt350n_v2_leds); platform_device_register(&wrt350n_v2_button_device); diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 2c70f74fed5d..e110b6d4ae8c 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -42,7 +42,6 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ - .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_time = sirfsoc_init_time, .init_late = sirfsoc_init_late, @@ -59,7 +58,6 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ - .nr_irqs = 128, .map_io = sirfsoc_map_io, .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index 02cc34388b05..c4525a88e5da 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -34,7 +34,10 @@ static void sirfsoc_set_wakeup_source(void) pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); #define X_ON_KEY_B (1 << 0) - sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B, +#define RTC_ALARM0_B (1 << 2) +#define RTC_ALARM1_B (1 << 3) + sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B | + RTC_ALARM0_B | RTC_ALARM1_B, sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); } @@ -85,12 +88,6 @@ static const struct platform_suspend_ops sirfsoc_pm_ops = { .valid = suspend_valid_only_mem, }; -int __init sirfsoc_pm_init(void) -{ - suspend_set_ops(&sirfsoc_pm_ops); - return 0; -} - static const struct of_device_id pwrc_ids[] = { { .compatible = "sirf,prima2-pwrc" }, {} @@ -118,7 +115,6 @@ static int __init sirfsoc_of_pwrc_init(void) return 0; } -postcore_initcall(sirfsoc_of_pwrc_init); static const struct of_device_id memc_ids[] = { { .compatible = "sirf,prima2-memc" }, @@ -149,4 +145,11 @@ static int __init sirfsoc_memc_init(void) { return platform_driver_register(&sirfsoc_memc_driver); } -postcore_initcall(sirfsoc_memc_init); + +int __init sirfsoc_pm_init(void) +{ + sirfsoc_of_pwrc_init(); + sirfsoc_memc_init(); + suspend_set_ops(&sirfsoc_pm_ops); + return 0; +} diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 8091aac89edf..f9423493ed36 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -29,7 +29,7 @@ #include <linux/pwm_backlight.h> #include <linux/i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/i2c/pxa-i2c.h> #include <linux/mfd/da903x.h> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 3a3362fa793e..8eb4e23c561d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -30,7 +30,7 @@ #include <linux/power_supply.h> #include <linux/apm-emulation.h> #include <linux/i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/i2c/pxa-i2c.h> #include <linux/regulator/userspace-consumer.h> diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index fe31bfcbb8df..c98511c5abd1 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -73,9 +73,6 @@ static struct pxa2xx_spi_chip mcp251x_chip_info4 = { static struct mcp251x_platform_data mcp251x_info = { .oscillator_frequency = 16E6, - .board_specific_setup = NULL, - .power_enable = NULL, - .transceiver_enable = NULL }; static struct spi_board_info mcp251x_board_info[] = { diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 13e5b00eae90..3133ba82c508 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -408,7 +408,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = { .mclk_10khz = 1000, }; -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> static struct pca953x_platform_data pca9536_data = { .gpio_base = PXA_NR_BUILTIN_GPIO, diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c index 3835979a0dd3..f6a2c4b1c1dc 100644 --- a/arch/arm/mach-pxa/pxa-dt.c +++ b/arch/arm/mach-pxa/pxa-dt.c @@ -28,7 +28,7 @@ static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL), OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL), - OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL), + OF_DEV_AUXDATA("intel,pxa3xx-gpio", 0x40e00000, "pxa3xx-gpio", NULL), OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL), OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL), OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL), diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 4c29173026e8..0b11c1af51c4 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -20,7 +20,7 @@ #include <linux/leds.h> #include <linux/i2c.h> #include <linux/i2c/pxa-i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/spi/corgi_lcd.h> diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index f5d436434566..b19d1c361cab 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -26,9 +26,11 @@ #include <linux/mtd/physmap.h> #include <linux/i2c.h> #include <linux/i2c/pxa-i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/apm-emulation.h> #include <linux/can/platform/mcp251x.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> #include <asm/mach-types.h> #include <asm/suspend.h> @@ -391,33 +393,34 @@ static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { }; /* CAN bus on SPI */ -static int zeus_mcp2515_setup(struct spi_device *sdev) -{ - int err; - - err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown"); - if (err) - return err; +static struct regulator_consumer_supply can_regulator_consumer = + REGULATOR_SUPPLY("vdd", "spi3.0"); - err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1); - if (err) { - gpio_free(ZEUS_CAN_SHDN_GPIO); - return err; - } +static struct regulator_init_data can_regulator_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .consumer_supplies = &can_regulator_consumer, + .num_consumer_supplies = 1, +}; - return 0; -} +static struct fixed_voltage_config can_regulator_pdata = { + .supply_name = "CAN_SHDN", + .microvolts = 3300000, + .gpio = ZEUS_CAN_SHDN_GPIO, + .init_data = &can_regulator_init_data, +}; -static int zeus_mcp2515_transceiver_enable(int enable) -{ - gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable); - return 0; -} +static struct platform_device can_regulator_device = { + .name = "reg-fixed-volage", + .id = -1, + .dev = { + .platform_data = &can_regulator_pdata, + }, +}; static struct mcp251x_platform_data zeus_mcp2515_pdata = { .oscillator_frequency = 16*1000*1000, - .board_specific_setup = zeus_mcp2515_setup, - .power_enable = zeus_mcp2515_transceiver_enable, }; static struct spi_board_info zeus_spi_board_info[] = { @@ -516,6 +519,7 @@ static struct platform_device *zeus_devices[] __initdata = { &zeus_leds_device, &zeus_pcmcia_device, &zeus_max6369_device, + &can_regulator_device, }; /* AC'97 */ diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 86e59c043de2..869bce7c3f24 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/i2c.h> #include <linux/i2c/pxa-i2c.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/gpio.h> #include <mach/pxa300.h> diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index d210c0f9c2c4..9db2029aa632 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -13,7 +13,7 @@ config REALVIEW_EB_A9MP depends on MACH_REALVIEW_EB select CPU_V7 select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -26,7 +26,7 @@ config REALVIEW_EB_ARM11MP select ARCH_HAS_BARRIERS if SMP select CPU_V6K select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help @@ -48,7 +48,7 @@ config MACH_REALVIEW_PB11MP select ARM_GIC select CPU_V6K select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -92,7 +92,7 @@ config MACH_REALVIEW_PBX select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ARM_GIC select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_PATA_PLATFORM select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S deleted file mode 100644 index 8cc372dc66a8..000000000000 --- a/arch/arm/mach-realview/include/mach/debug-macro.S +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/mach-realview/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifdef CONFIG_DEBUG_REALVIEW_STD_PORT -#define DEBUG_LL_UART_OFFSET 0x00009000 -#elif defined(CONFIG_DEBUG_REALVIEW_PB1176_PORT) -#define DEBUG_LL_UART_OFFSET 0x0010c000 -#endif - -#ifndef DEBUG_LL_UART_OFFSET -#error "Unknown RealView platform" -#endif - - .macro addruart, rp, rv, tmp - mov \rp, #DEBUG_LL_UART_OFFSET - orr \rv, \rp, #0xfb000000 @ virtual base - orr \rp, \rp, #0x10000000 @ physical base - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S deleted file mode 100644 index 6d28cc99b124..000000000000 --- a/arch/arm/mach-rpc/include/mach/debug-macro.S +++ /dev/null @@ -1,23 +0,0 @@ -/* arch/arm/mach-rpc/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00010000 - orr \rp, \rp, #0x00000fe0 - orr \rv, \rp, #0xe0000000 @ virtual - orr \rp, \rp, #0x03000000 @ physical - .endm - -#define UART_SHIFT 2 -#define FLOW_CONTROL -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 7791ac76f945..dba2173e70f3 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -30,7 +30,6 @@ config CPU_S3C2410 select S3C2410_CLOCK select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ select S3C2410_PM if PM - select SAMSUNG_HRT select SAMSUNG_WDT_RESET help Support for S3C2410 and S3C2410A family from the S3C24XX line @@ -42,7 +41,6 @@ config CPU_S3C2412 select CPU_LLSERIAL_S3C2440 select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM - select SAMSUNG_HRT help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line @@ -54,7 +52,6 @@ config CPU_S3C2416 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2416 SoC from the S3C24XX line @@ -65,7 +62,6 @@ config CPU_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM select S3C2440_DMA if S3C24XX_DMA - select SAMSUNG_HRT help Support for S3C2440 Samsung Mobile CPU based systems. @@ -75,7 +71,6 @@ config CPU_S3C2442 select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2442 Samsung Mobile CPU based systems. @@ -91,7 +86,6 @@ config CPU_S3C2443 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2443 SoC from the S3C24XX line diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c index 564553694b54..d39d3c787580 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2410.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c @@ -281,6 +281,5 @@ int __init s3c2410_baseclk_add(void) (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); - s3c_pwmclk_init(); return 0; } diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c index 2cc017da88fe..d8f253f2b486 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c @@ -757,6 +757,5 @@ int __init s3c2412_baseclk_add(void) } clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup)); - s3c_pwmclk_init(); return 0; } diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index 036056cea57c..d421a72920a5 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c @@ -168,6 +168,4 @@ void __init s3c2416_init_clocks(int xtal) s3c24xx_register_clock(&hsmmc0_clk); clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); - s3c_pwmclk_init(); - } diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index 0a53051b0787..76cd31f7804e 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c @@ -209,6 +209,4 @@ void __init s3c2443_init_clocks(int xtal) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); - - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index c157103ed8eb..457261c98433 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -27,6 +27,7 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> +#include <clocksource/samsung_pwm.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> @@ -49,6 +50,7 @@ #include <plat/clock.h> #include <plat/cpu-freq.h> #include <plat/pll.h> +#include <plat/pwm-core.h> #include "common.h" @@ -216,6 +218,13 @@ static void s3c24xx_default_idle(void) S3C2410_CLKCON); } +static struct samsung_pwm_variant s3c24xx_pwm_variant = { + .bits = 16, + .div_base = 1, + .has_tint_cstat = false, + .tclk_mask = (1 << 4), +}; + void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { arm_pm_idle = s3c24xx_default_idle; @@ -232,6 +241,24 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) s3c24xx_init_cpu(); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s3c24xx_pwm_variant); +} + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s3c24xx_pwm_variant); } /* Serial port registrations */ diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h index 8ba381f2dbe1..444793f0f5f1 100644 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ b/arch/arm/mach-s3c24xx/include/mach/map.h @@ -167,4 +167,6 @@ #define S3C_PA_SPI0 S3C2443_PA_SPI0 #define S3C_PA_SPI1 S3C2443_PA_SPI1 +#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER + #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index af4334d6b4d5..74dd47988b41 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -512,7 +512,7 @@ static struct platform_pwm_backlight_data backlight_data = { static struct platform_device h1940_backlight = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[0].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &backlight_data, }, .id = -1, @@ -632,7 +632,7 @@ static struct platform_device *h1940_devices[] __initdata = { &h1940_device_bluetooth, &s3c_device_sdi, &s3c_device_rtc, - &s3c_device_timer[0], + &samsung_device_pwm, &h1940_backlight, &h1940_lcd_powerdev, &s3c_device_adc, diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 44ca018e1f96..206b1f7546d1 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -530,7 +530,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = { static struct platform_device rx1950_backlight = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[0].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &rx1950_backlight_data, }, }; @@ -717,8 +717,7 @@ static struct platform_device *rx1950_devices[] __initdata = { &s3c_device_sdi, &s3c_device_adc, &s3c_device_ts, - &s3c_device_timer[0], - &s3c_device_timer[1], + &samsung_device_pwm, &rx1950_backlight, &rx1950_device_gpiokeys, &power_supply, diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 20578536aec7..041da5172423 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -17,13 +17,11 @@ config PLAT_S3C64XX # Configuration options for the S3C6410 CPU config CPU_S3C6400 - select SAMSUNG_HRT bool help Enable S3C6400 CPU support config CPU_S3C6410 - select SAMSUNG_HRT bool help Enable S3C6410 CPU support diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 8499415be9cd..c1bcc4a6d3a8 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -1004,6 +1004,4 @@ void __init s3c64xx_register_clocks(unsigned long xtal, for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) s3c_register_clksrc(clksrc_cdev[cnt], 1); clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); - - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 3f62e467b129..73d79cf5e141 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -27,6 +27,7 @@ #include <linux/irq.h> #include <linux/gpio.h> #include <linux/irqchip/arm-vic.h> +#include <clocksource/samsung_pwm.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -42,7 +43,7 @@ #include <plat/pm.h> #include <plat/gpio-cfg.h> #include <plat/irq-uart.h> -#include <plat/irq-vic-timer.h> +#include <plat/pwm-core.h> #include <plat/regs-irqtype.h> #include <plat/regs-serial.h> #include <plat/watchdog-reset.h> @@ -149,6 +150,30 @@ static struct device s3c64xx_dev = { .bus = &s3c64xx_subsys, }; +static struct samsung_pwm_variant s3c64xx_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), +}; + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s3c64xx_pwm_variant); +} + /* read cpu identification code */ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) @@ -161,6 +186,8 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) s3c64xx_init_cpu(); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s3c64xx_pwm_variant); } static __init int s3c64xx_dev_init(void) @@ -195,9 +222,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) /* initialise the pair of VICs */ vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); - - /* add the timer sub-irqs */ - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } #define eint_offset(irq) ((irq) - IRQ_EINT(0)) diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index 96d60e0d9372..67bbd1dd04c2 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h @@ -107,14 +107,6 @@ #define IRQ_TC IRQ_PENDN #define IRQ_ADC S3C64XX_IRQ_VIC1(31) -#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) - -#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) -#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) -#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) -#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) -#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) - /* compatibility for device defines */ #define IRQ_IIC1 IRQ_S3C6410_IIC1 diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 8e2097bb208a..f55ccb1ce893 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -121,5 +121,6 @@ #define SAMSUNG_PA_ADC S3C64XX_PA_ADC #define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON #define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD +#define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c index 0c7e1d960ca4..c3da1b68d03e 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c64xx/irq-pm.c @@ -22,7 +22,6 @@ #include <mach/map.h> #include <plat/regs-serial.h> -#include <plat/regs-timer.h> #include <mach/regs-gpio.h> #include <plat/cpu.h> #include <plat/pm.h> @@ -43,7 +42,6 @@ static struct sleep_save irq_save[] = { SAVE_ITEM(S3C64XX_EINT0FLTCON2), SAVE_ITEM(S3C64XX_EINT0FLTCON3), SAVE_ITEM(S3C64XX_EINT0MASK), - SAVE_ITEM(S3C64XX_TINT_CSTAT), }; static struct irq_grp_save { diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 8ad88ace795a..eb8e5a1aca42 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -30,7 +30,7 @@ #include <linux/basic_mmio_gpio.h> #include <linux/spi/spi.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/platform_data/s3c-hsotg.h> #include <video/platform_lcd.h> @@ -120,7 +120,7 @@ static struct platform_device crag6410_backlight_device = { .name = "pwm-backlight", .id = -1, .dev = { - .parent = &s3c_device_timer[0].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &crag6410_backlight_data, }, }; @@ -375,7 +375,7 @@ static struct platform_device *crag6410_devices[] __initdata = { &s3c_device_fb, &s3c_device_ohci, &s3c_device_usb_hsotg, - &s3c_device_timer[0], + &samsung_device_pwm, &s3c64xx_device_iis0, &s3c64xx_device_iis1, &samsung_device_keypad, diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 5b7f357d8c22..f39569e0f2e6 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -123,7 +123,7 @@ static struct platform_pwm_backlight_data hmt_backlight_data = { static struct platform_device hmt_backlight_device = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[1].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &hmt_backlight_data, }, }; @@ -239,7 +239,7 @@ static struct platform_device *hmt_devices[] __initdata = { &s3c_device_nand, &s3c_device_fb, &s3c_device_ohci, - &s3c_device_timer[1], + &samsung_device_pwm, &hmt_backlight_device, &hmt_leds_device, }; diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 58ac99041274..86d980b448fd 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -157,7 +157,7 @@ static struct platform_pwm_backlight_data smartq_backlight_data = { static struct platform_device smartq_backlight_device = { .name = "pwm-backlight", .dev = { - .parent = &s3c_device_timer[1].dev, + .parent = &samsung_device_pwm.dev, .platform_data = &smartq_backlight_data, }, }; @@ -246,7 +246,7 @@ static struct platform_device *smartq_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_ohci, &s3c_device_rtc, - &s3c_device_timer[1], + &samsung_device_pwm, &s3c_device_ts, &s3c_device_usb_hsotg, &s3c64xx_device_iis0, diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index bd3295a19ad7..d90b450c5645 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -274,6 +274,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_i2c1, &s3c_device_fb, &s3c_device_ohci, + &samsung_device_pwm, &s3c_device_usb_hsotg, &s3c64xx_device_iisv4, &samsung_device_keypad, @@ -691,9 +692,9 @@ static void __init smdk6410_machine_init(void) s3c_ide_set_platdata(&smdk6410_ide_pdata); - samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data); - platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); + + samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data); } MACHINE_START(SMDK6410, "SMDK6410") diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig index 5a707bdb9ea0..bb2111b3751e 100644 --- a/arch/arm/mach-s5p64x0/Kconfig +++ b/arch/arm/mach-s5p64x0/Kconfig @@ -11,14 +11,12 @@ config CPU_S5P6440 bool select S5P_SLEEP if PM select SAMSUNG_DMADEV - select SAMSUNG_HRT select SAMSUNG_WAKEMASK if PM help Enable S5P6440 CPU support config CPU_S5P6450 bool - select SAMSUNG_HRT select S5P_SLEEP if PM select SAMSUNG_DMADEV select SAMSUNG_WAKEMASK if PM diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 3537815247f1..ae34a1d5e10a 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -629,6 +629,4 @@ void __init s5p6440_register_clocks(void) clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup)); s3c24xx_register_clock(&dummy_apb_pclk); - - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index af384ddd2dcf..0b3ca2ed53e9 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -698,6 +698,4 @@ void __init s5p6450_register_clocks(void) clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup)); s3c24xx_register_clock(&dummy_apb_pclk); - - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c index dfdfdc320ce7..42e14f2e7ca7 100644 --- a/arch/arm/mach-s5p64x0/common.c +++ b/arch/arm/mach-s5p64x0/common.c @@ -19,6 +19,7 @@ #include <linux/io.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <clocksource/samsung_pwm.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/dma-mapping.h> @@ -47,6 +48,7 @@ #include <plat/fb-core.h> #include <plat/spi-core.h> #include <plat/gpio-cfg.h> +#include <plat/pwm-core.h> #include <plat/regs-irqtype.h> #include <plat/regs-serial.h> #include <plat/watchdog-reset.h> @@ -157,6 +159,30 @@ static void s5p64x0_idle(void) cpu_do_idle(); } +static struct samsung_pwm_variant s5p64x0_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = 0, +}; + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s5p64x0_pwm_variant); +} + /* * s5p64x0_map_io * @@ -176,6 +202,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size) s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); samsung_wdt_reset_init(S3C_VA_WATCHDOG); + samsung_pwm_set_platdata(&s5p64x0_pwm_variant); } void __init s5p6440_map_io(void) diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 5b845e849b30..53982db9d259 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h @@ -141,8 +141,6 @@ #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) -#define IRQ_TIMER_BASE (11) - /* Set the default NR_IRQS */ #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 0c0175dbfa34..50a6e96d6389 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -76,6 +76,7 @@ #define S5P_PA_TIMER S5P64X0_PA_TIMER #define SAMSUNG_PA_ADC S5P64X0_PA_ADC +#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER /* UART */ diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 73f71a698a34..0b00304c1e91 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -162,6 +162,7 @@ static struct platform_device *smdk6440_devices[] __initdata = { &s3c_device_rtc, &s3c_device_i2c0, &s3c_device_i2c1, + &samsung_device_pwm, &s3c_device_ts, &s3c_device_wdt, &s5p6440_device_iis, @@ -254,8 +255,6 @@ static void __init smdk6440_machine_init(void) i2c_register_board_info(1, smdk6440_i2c_devs1, ARRAY_SIZE(smdk6440_i2c_devs1)); - samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); - s5p6440_set_lcd_interface(); s3c_fb_set_platdata(&smdk6440_lcd_pdata); @@ -264,6 +263,8 @@ static void __init smdk6440_machine_init(void) s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata); platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); + + samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); } MACHINE_START(SMDK6440, "SMDK6440") diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index 18303e12019f..5949296e88fd 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -180,6 +180,7 @@ static struct platform_device *smdk6450_devices[] __initdata = { &s3c_device_rtc, &s3c_device_i2c0, &s3c_device_i2c1, + &samsung_device_pwm, &s3c_device_ts, &s3c_device_wdt, &s5p6450_device_iis0, @@ -273,8 +274,6 @@ static void __init smdk6450_machine_init(void) i2c_register_board_info(1, smdk6450_i2c_devs1, ARRAY_SIZE(smdk6450_i2c_devs1)); - samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); - s5p6450_set_lcd_interface(); s3c_fb_set_platdata(&smdk6450_lcd_pdata); @@ -283,6 +282,8 @@ static void __init smdk6450_machine_init(void) s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata); platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); + + samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); } MACHINE_START(SMDK6450, "SMDK6450") diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c index 97c2a08ad490..861e15cea691 100644 --- a/arch/arm/mach-s5p64x0/pm.c +++ b/arch/arm/mach-s5p64x0/pm.c @@ -18,7 +18,6 @@ #include <plat/cpu.h> #include <plat/pm.h> -#include <plat/regs-timer.h> #include <plat/wakeup-mask.h> #include <mach/regs-clock.h> @@ -48,8 +47,6 @@ static struct sleep_save s5p64x0_misc_save[] = { SAVE_ITEM(S5P64X0_MEM0CONSLP1), SAVE_ITEM(S5P64X0_MEM0DRVCON), SAVE_ITEM(S5P64X0_MEM1DRVCON), - - SAVE_ITEM(S3C64XX_TINT_CSTAT), }; /* DPLL is present only in S5P6450 */ diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 2f456a4533ba..15170be97a74 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -11,7 +11,6 @@ config CPU_S5PC100 bool select S5P_EXT_INT select SAMSUNG_DMADEV - select SAMSUNG_HRT help Enable S5PC100 CPU support diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index a206dc35eff1..d0dc10ee7729 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -1358,6 +1358,4 @@ void __init s5pc100_register_clocks(void) s3c_disable_clocks(clk_cdev[ptr], 1); s3c24xx_register_clock(&dummy_apb_pclk); - - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c index 4bdfecf6d024..c5a8eeacf81c 100644 --- a/arch/arm/mach-s5pc100/common.c +++ b/arch/arm/mach-s5pc100/common.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/device.h> #include <linux/serial_core.h> +#include <clocksource/samsung_pwm.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/reboot.h> @@ -46,6 +47,7 @@ #include <plat/fb-core.h> #include <plat/iic-core.h> #include <plat/onenand-core.h> +#include <plat/pwm-core.h> #include <plat/spi-core.h> #include <plat/regs-serial.h> #include <plat/watchdog-reset.h> @@ -132,6 +134,30 @@ static struct map_desc s5pc100_iodesc[] __initdata = { } }; +static struct samsung_pwm_variant s5pc100_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 5), +}; + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s5pc100_pwm_variant); +} + /* * s5pc100_map_io * @@ -149,6 +175,8 @@ void __init s5pc100_init_io(struct map_desc *mach_desc, int size) s5p_init_cpu(S5P_VA_CHIPID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s5pc100_pwm_variant); } void __init s5pc100_map_io(void) diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 2870f12c7926..d2eb4757381f 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -97,8 +97,6 @@ #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) #define IRQ_VIC_END S5P_IRQ_VIC2(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 54bc4f82e17a..2550b6112b82 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -116,6 +116,7 @@ #define SAMSUNG_PA_ADC S5PC100_PA_TSADC #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD +#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 8c880f76f274..7c57a221785e 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -194,6 +194,7 @@ static struct platform_device *smdkc100_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, + &samsung_device_pwm, &s3c_device_ts, &s3c_device_wdt, &smdkc100_lcd_powerdev, @@ -246,9 +247,9 @@ static void __init smdkc100_machine_init(void) gpio_request(S5PC100_GPH0(6), "GPH0"); smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); - samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data); - platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); + + samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data); } MACHINE_START(SMDKC100, "SMDKC100") diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 0963283a7c5d..caaedafbbf5f 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -15,7 +15,6 @@ config CPU_S5PV210 select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV - select SAMSUNG_HRT help Enable S5PV210 CPU support diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index f051f53e35b7..ca463724a3df 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -1362,5 +1362,4 @@ void __init s5pv210_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) s3c_disable_clocks(clk_cdev[ptr], 1); - s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c index 023f1a796a9c..26027a29b8a1 100644 --- a/arch/arm/mach-s5pv210/common.c +++ b/arch/arm/mach-s5pv210/common.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/device.h> +#include <clocksource/samsung_pwm.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/dma-mapping.h> @@ -42,6 +43,7 @@ #include <plat/fimc-core.h> #include <plat/iic-core.h> #include <plat/keypad-core.h> +#include <plat/pwm-core.h> #include <plat/tv-core.h> #include <plat/spi-core.h> #include <plat/regs-serial.h> @@ -148,6 +150,30 @@ void s5pv210_restart(enum reboot_mode mode, const char *cmd) __raw_writel(0x1, S5P_SWRESET); } +static struct samsung_pwm_variant s5pv210_pwm_variant = { + .bits = 32, + .div_base = 0, + .has_tint_cstat = true, + .tclk_mask = (1 << 5), +}; + +void __init samsung_set_timer_source(unsigned int event, unsigned int source) +{ + s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; + s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); +} + +void __init samsung_timer_init(void) +{ + unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { + IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, + }; + + samsung_pwm_clocksource_init(S3C_VA_TIMER, + timer_irqs, &s5pv210_pwm_variant); +} + /* * s5pv210_map_io * @@ -165,6 +191,8 @@ void __init s5pv210_init_io(struct map_desc *mach_desc, int size) s5p_init_cpu(S5P_VA_CHIPID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + + samsung_pwm_set_platdata(&s5pv210_pwm_variant); } void __init s5pv210_map_io(void) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index e777e010ed2e..5e0de3a31f3d 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -118,8 +118,6 @@ #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) #define IRQ_VIC_END S5P_IRQ_VIC3(31) -#define IRQ_TIMER_BASE (11) - #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index b7c8a1917ffc..763929aca52d 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -139,6 +139,7 @@ #define SAMSUNG_PA_ADC S5PV210_PA_ADC #define SAMSUNG_PA_CFCON S5PV210_PA_CFCON #define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD +#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER /* UART */ diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index d50b6f124465..6d72bb992e38 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -218,6 +218,7 @@ static struct platform_device *smdkv210_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_i2c2, + &samsung_device_pwm, &s3c_device_rtc, &s3c_device_ts, &s3c_device_usb_hsotg, @@ -316,11 +317,11 @@ static void __init smdkv210_machine_init(void) s3c_fb_set_platdata(&smdkv210_lcd0_pdata); - samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data); - s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata); platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); + + samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data); } MACHINE_START(SMDKV210, "SMDKV210") diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 2b68a67b6e95..3cf3f9c8ddd1 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -21,7 +21,6 @@ #include <plat/cpu.h> #include <plat/pm.h> -#include <plat/regs-timer.h> #include <mach/regs-irq.h> #include <mach/regs-clock.h> @@ -77,15 +76,6 @@ static struct sleep_save s5pv210_core_save[] = { /* Clock ETC */ SAVE_ITEM(S5P_CLK_OUT), SAVE_ITEM(S5P_MDNIE_SEL), - - /* PWM Register */ - SAVE_ITEM(S3C2410_TCFG0), - SAVE_ITEM(S3C2410_TCFG1), - SAVE_ITEM(S3C64XX_TINT_CSTAT), - SAVE_ITEM(S3C2410_TCON), - SAVE_ITEM(S3C2410_TCNTB(0)), - SAVE_ITEM(S3C2410_TCMPB(0)), - SAVE_ITEM(S3C2410_TCNTO(0)), }; static int s5pv210_cpu_suspend(unsigned long arg) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index fed06b06056d..1f94c310c477 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -1,3 +1,41 @@ +config ARCH_SHMOBILE_MULTI + bool "SH-Mobile Series" if ARCH_MULTI_V7 + depends on MMU + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP + select ARM_GIC + select MIGHT_HAVE_CACHE_L2X0 + select NO_IOPORT + select PINCTRL + select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP + +if ARCH_SHMOBILE_MULTI + +comment "SH-Mobile System Type" + +config ARCH_EMEV2 + bool "Emma Mobile EV2" + +comment "SH-Mobile Board Type" + +config MACH_KZM9D_REFERENCE + bool "KZM9D board - Reference Device Tree Implementation" + depends on ARCH_EMEV2 + select REGULATOR_FIXED_VOLTAGE if REGULATOR + ---help--- + Use reference implementation of KZM9D board support + which makes a greater use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers + +comment "SH-Mobile System Configuration" +endif + if ARCH_SHMOBILE comment "SH-Mobile System Type" @@ -122,6 +160,7 @@ config MACH_BOCKW depends on ARCH_R8A7778 select ARCH_REQUIRE_GPIOLIB select RENESAS_INTC_IRQPIN + select REGULATOR_FIXED_VOLTAGE if REGULATOR select USE_OF config MACH_BOCKW_REFERENCE @@ -222,6 +261,15 @@ config CPU_HAS_INTEVT bool default y +config SH_CLK_CPG + bool + +source "drivers/sh/Kconfig" + +endif + +if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI + menu "Timer and clock configuration" config SHMOBILE_TIMER_HZ @@ -256,9 +304,4 @@ config EM_TIMER_STI endmenu -config SH_CLK_CPG - bool - -source "drivers/sh/Kconfig" - endif diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index b95b500e3b5a..2705bfa8c113 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -2,18 +2,33 @@ # Makefile for the linux kernel. # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include + # Common objects -obj-y := timer.o console.o clock.o +obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o -obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o -obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o -obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o -obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o -obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o -obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o -obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o +obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o +obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o +obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o +obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o +obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o +obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o +obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o + +# Clock objects +ifndef CONFIG_COMMON_CLK +obj-y += clock.o +obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o +obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o +obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o +obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o +obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o +obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o +obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o +obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o +endif # SMP objects smp-y := platsmp.o headsmp.o diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 57e66eb2fd5a..24b87eea9da3 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -19,8 +19,14 @@ */ #include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> #include <linux/interrupt.h> #include <linux/kernel.h> +#include <linux/mfd/tmio.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/pinctrl/machine.h> #include <linux/platform_device.h> #include <linux/regulator/fixed.h> @@ -33,6 +39,58 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* LEDS */ +static struct gpio_led ape6evm_leds[] = { + { + .name = "gnss-en", + .gpio = 28, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, { + .name = "nfc-nrst", + .gpio = 126, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, { + .name = "gnss-nrst", + .gpio = 132, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, { + .name = "bt-wakeup", + .gpio = 232, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, { + .name = "strobe", + .gpio = 250, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, { + .name = "bbresetout", + .gpio = 288, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, +}; + +static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = { + .leds = ape6evm_leds, + .num_leds = ARRAY_SIZE(ape6evm_leds), +}; + +/* GPIO KEY */ +#define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1 } + +static struct gpio_keys_button gpio_buttons[] = { + GPIO_KEY(KEY_0, 324, "S16"), + GPIO_KEY(KEY_MENU, 325, "S17"), + GPIO_KEY(KEY_HOME, 326, "S18"), + GPIO_KEY(KEY_BACK, 327, "S19"), + GPIO_KEY(KEY_VOLUMEUP, 328, "S20"), + GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"), +}; + +static struct __initdata gpio_keys_platform_data ape6evm_keys_pdata = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + /* Dummy supplies, where voltage doesn't matter */ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vddvario", "smsc911x"), @@ -40,7 +98,7 @@ static struct regulator_consumer_supply dummy_supplies[] = { }; /* SMSC LAN9220 */ -static const struct resource lan9220_res[] = { +static const struct resource lan9220_res[] __initconst = { DEFINE_RES_MEM(0x08000000, 0x1000), { .start = irq_pin(40), /* IRQ40 */ @@ -48,19 +106,83 @@ static const struct resource lan9220_res[] = { }, }; -static const struct smsc911x_platform_config lan9220_data = { +static const struct smsc911x_platform_config lan9220_data __initconst = { .flags = SMSC911X_USE_32BIT, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, }; -static const struct pinctrl_map ape6evm_pinctrl_map[] = { +/* + * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we + * model a VDD supply to MMCIF, using a fixed 3.3V regulator. Also use the + * static power supply for SDHI0 and SDHI1, whereas SDHI0's VccQ is also + * supplied by the same tps80032 regulator and thus can also be adjusted + * dynamically. + */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), +}; + +/* MMCIF */ +static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +}; + +static const struct resource mmcif0_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), + DEFINE_RES_IRQ(gic_spi(169)), +}; + +/* SDHI0 */ +static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, +}; + +static const struct resource sdhi0_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), + DEFINE_RES_IRQ(gic_spi(165)), +}; + +/* SDHI1 */ +static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = { + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, + .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_NEEDS_POLL, +}; + +static const struct resource sdhi1_resources[] __initconst = { + DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), + DEFINE_RES_IRQ(gic_spi(166)), +}; + +static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = { /* SCIFA0 console */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", "scifa0_data", "scifa0"), /* SMSC */ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", "irqc_irq40", "irqc"), + /* MMCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", + "mmc0_data8", "mmc0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", + "mmc0_ctrl", "mmc0"), + /* SDHI0: uSD: no WP */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", + "sdhi0_data4", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", + "sdhi0_ctrl", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", + "sdhi0_cd", "sdhi0"), + /* SDHI1 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", + "sdhi1_data4", "sdhi1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", + "sdhi1_ctrl", "sdhi1"), }; static void __init ape6evm_add_standard_devices(void) @@ -93,6 +215,23 @@ static void __init ape6evm_add_standard_devices(void) platform_device_register_resndata(&platform_bus, "smsc911x", -1, lan9220_res, ARRAY_SIZE(lan9220_res), &lan9220_data, sizeof(lan9220_data)); + regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + platform_device_register_resndata(&platform_bus, "sh_mmcif", 0, + mmcif0_resources, ARRAY_SIZE(mmcif0_resources), + &mmcif0_pdata, sizeof(mmcif0_pdata)); + platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0, + sdhi0_resources, ARRAY_SIZE(sdhi0_resources), + &sdhi0_pdata, sizeof(sdhi0_pdata)); + platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1, + sdhi1_resources, ARRAY_SIZE(sdhi1_resources), + &sdhi1_pdata, sizeof(sdhi1_pdata)); + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &ape6evm_keys_pdata, + sizeof(ape6evm_keys_pdata)); + platform_device_register_data(&platform_bus, "leds-gpio", -1, + &ape6evm_leds_pdata, + sizeof(ape6evm_leds_pdata)); } static const char *ape6evm_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c index 5c8cc3c9e9d0..57d1a78367b6 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c @@ -24,7 +24,6 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <linux/io.h> -#include <linux/pinctrl/machine.h> #include <mach/common.h> #include <mach/r8a7740.h> #include <asm/mach/arch.h> @@ -119,12 +118,6 @@ * usbhsf_power_ctrl() */ -static const struct pinctrl_map eva_pinctrl_map[] = { - /* SCIFA1 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", - "scifa1_data", "scifa1"), -}; - static void __init eva_clock_init(void) { struct clk *system = clk_get(NULL, "system_clk"); @@ -165,35 +158,26 @@ clock_error: */ static void __init eva_init(void) { - r8a7740_clock_init(MD_CK0 | MD_CK2); eva_clock_init(); - pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); - r8a7740_pinmux_init(); - r8a7740_meram_workaround(); - /* - * Touchscreen - * TODO: Move reset GPIO over to .dts when we can reference it - */ - gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ - #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 32K*8way */ l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); #endif r8a7740_add_standard_devices_dt(); + r8a7740_pm_init(); } #define RESCNT2 IOMEM(0xe6188020) -static void eva_restart(char mode, const char *cmd) +static void eva_restart(enum reboot_mode mode, const char *cmd) { /* Do soft power on reset */ - writel((1 << 31), RESCNT2); + writel(1 << 31, RESCNT2); } static const char *eva_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 4d65263aafad..5bd1479d3deb 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -360,7 +360,6 @@ static struct platform_device usbhsf_device = { static struct sh_eth_plat_data sh_eth_platdata = { .phy = 0x00, /* LAN8710A */ .edmac_endian = EDMAC_LITTLE_ENDIAN, - .register_type = SH_ETH_REG_GIGABIT, .phy_interface = PHY_INTERFACE_MODE_MII, }; @@ -824,6 +823,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, + .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, + .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; static struct resource sh_mmcif_resources[] = { diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 255e97e5be83..6b9faf3908f7 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,7 @@ #include <linux/smsc911x.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> +#include <media/soc_camera.h> #include <mach/common.h> #include <mach/irqs.h> #include <mach/r8a7778.h> @@ -102,7 +104,6 @@ static struct resource sdhi0_resources[] __initdata = { static struct sh_eth_plat_data ether_platform_data __initdata = { .phy = 0x01, .edmac_endian = EDMAC_LITTLE_ENDIAN, - .register_type = SH_ETH_REG_FAST_RCAR, .phy_interface = PHY_INTERFACE_MODE_RMII, /* * Although the LINK signal is available on the board, it's connected to @@ -161,6 +162,25 @@ static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { MMC_CAP_NEEDS_POLL, }; +static struct rcar_vin_platform_data vin_platform_data __initdata = { + .flags = RCAR_VIN_BT656, +}; + +/* In the default configuration both decoders reside on I2C bus 0 */ +#define BOCKW_CAMERA(idx) \ +static struct i2c_board_info camera##idx##_info = { \ + I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)), \ +}; \ + \ +static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \ + .bus_id = idx, \ + .i2c_adapter_id = 0, \ + .board_info = &camera##idx##_info, \ +} + +BOCKW_CAMERA(0); +BOCKW_CAMERA(1); + static const struct pinctrl_map bockw_pinctrl_map[] = { /* Ether */ PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", @@ -192,6 +212,16 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { "sdhi0_cd", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", "sdhi0_wp", "sdhi0"), + /* VIN0 */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", + "vin0_clk", "vin0"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", + "vin0_data8", "vin0"), + /* VIN1 */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", + "vin1_clk", "vin1"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", + "vin1_data8", "vin1"), }; #define FPGA 0x18200000 @@ -206,6 +236,16 @@ static void __init bockw_init(void) r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_vin_device(0, &vin_platform_data); + /* VIN1 has a pin conflict with Ether */ + if (!IS_ENABLED(CONFIG_SH_ETH)) + r8a7778_add_vin_device(1, &vin_platform_data); + platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0, + &iclink0_ml86v7667, + sizeof(iclink0_ml86v7667)); + platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1, + &iclink1_ml86v7667, + sizeof(iclink1_ml86v7667)); i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c index a7b28b24ab38..8f8bb2fab076 100644 --- a/arch/arm/mach-shmobile/board-kzm9d-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c @@ -26,7 +26,8 @@ static void __init kzm9d_add_standard_devices(void) { - emev2_clock_init(); + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + emev2_clock_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index 4cf6babc4e02..598e32488410 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -21,66 +21,19 @@ */ #include <linux/delay.h> -#include <linux/gpio.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/input.h> #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf-generic.h> #include <mach/sh73a0.h> #include <mach/common.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -static unsigned long pin_pullup_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), -}; - -static const struct pinctrl_map kzm_pinctrl_map[] = { - PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0", - "i2c3_1", "i2c3"), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", - "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", - "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0", - "mmc0_data8_0", pin_pullup_conf), - /* SCIFA4 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_data", "scifa4"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_ctrl", "scifa4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0", - "sdhi0_wp", "sdhi0"), - /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", - "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0", - "sdhi2_ctrl", "sdhi2"), -}; - static void __init kzm_init(void) { sh73a0_add_standard_devices_dt(); - pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); - sh73a0_pinmux_init(); - - /* enable SD */ - gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ - - gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f89f16650731..4872939cdba2 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -24,10 +24,16 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/leds.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> #include <linux/pinctrl/machine.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/sh_eth.h> #include <mach/common.h> +#include <mach/irqs.h> #include <mach/r8a7790.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -70,6 +76,36 @@ static __initdata struct gpio_keys_platform_data lager_keys_pdata = { .nbuttons = ARRAY_SIZE(gpio_buttons), }; +/* Fixed 3.3V regulator to be used by MMCIF */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"), +}; + +/* MMCIF */ +static struct sh_mmcif_plat_data mmcif1_pdata __initdata = { + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, +}; + +static struct resource mmcif1_resources[] __initdata = { + DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), + DEFINE_RES_IRQ(gic_spi(170)), +}; + +/* Ether */ +static struct sh_eth_plat_data ether_pdata __initdata = { + .phy = 0x1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_RCAR, + .phy_interface = PHY_INTERFACE_MODE_RMII, + .ether_link_active_low = 1, +}; + +static struct resource ether_resources[] __initdata = { + DEFINE_RES_MEM(0xee700000, 0x400), + DEFINE_RES_IRQ(gic_spi(162)), +}; + static const struct pinctrl_map lager_pinctrl_map[] = { /* SCIF0 (CN19: DEBUG SERIAL0) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", @@ -77,6 +113,20 @@ static const struct pinctrl_map lager_pinctrl_map[] = { /* SCIF1 (CN20: DEBUG SERIAL1) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", "scif1_data", "scif1"), + /* MMCIF1 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", + "mmc1_data8", "mmc1"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790", + "mmc1_ctrl", "mmc1"), + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", + "eth_link", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", + "eth_mdio", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", + "eth_rmii", "eth"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790", + "intc_irq0", "intc"), }; static void __init lager_add_standard_devices(void) @@ -94,6 +144,16 @@ static void __init lager_add_standard_devices(void) platform_device_register_data(&platform_bus, "gpio-keys", -1, &lager_keys_pdata, sizeof(lager_keys_pdata)); + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + platform_device_register_resndata(&platform_bus, "sh_mmcif", 1, + mmcif1_resources, ARRAY_SIZE(mmcif1_resources), + &mmcif1_pdata, sizeof(mmcif1_pdata)); + + platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + ðer_pdata, sizeof(ether_pdata)); } static const char *lager_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c index a20b7ee652ea..3f4250a2d4eb 100644 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ b/arch/arm/mach-shmobile/board-marzen-reference.c @@ -19,42 +19,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <linux/pinctrl/machine.h> #include <mach/r8a7779.h> #include <mach/common.h> #include <mach/irqs.h> #include <asm/irq.h> #include <asm/mach/arch.h> -static const struct pinctrl_map marzen_pinctrl_map[] = { - /* SCIF2 (CN18: DEBUG0) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", - "scif2_data_c", "scif2"), - /* SCIF4 (CN19: DEBUG1) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", - "scif4_data", "scif4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_wp", "sdhi0"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "intc_irq1_b", "intc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "lbsc_ex_cs0", "lbsc"), -}; - static void __init marzen_init(void) { - pinctrl_register_mappings(marzen_pinctrl_map, - ARRAY_SIZE(marzen_pinctrl_map)); - r8a7779_pinmux_init(); - r8a7779_add_standard_devices_dt(); } diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 3551b5480b47..3f5044fda4e3 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -1,8 +1,9 @@ /* * marzen board support * - * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011, 2013 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm + * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,7 @@ #include <linux/mmc/host.h> #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> +#include <media/soc_camera.h> #include <mach/r8a7779.h> #include <mach/common.h> #include <mach/irqs.h> @@ -197,6 +199,32 @@ static struct platform_device leds_device = { }, }; +static struct rcar_vin_platform_data vin_platform_data __initdata = { + .flags = RCAR_VIN_BT656, +}; + +#define MARZEN_CAMERA(idx) \ +static struct i2c_board_info camera##idx##_info = { \ + I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ +}; \ + \ +static struct soc_camera_link iclink##idx##_adv7180 = { \ + .bus_id = 1 + 2 * (idx), \ + .i2c_adapter_id = 0, \ + .board_info = &camera##idx##_info, \ +}; \ + \ +static struct platform_device camera##idx##_device = { \ + .name = "soc-camera-pdrv", \ + .id = idx, \ + .dev = { \ + .platform_data = &iclink##idx##_adv7180, \ + }, \ +}; + +MARZEN_CAMERA(0); +MARZEN_CAMERA(1); + static struct platform_device *marzen_devices[] __initdata = { ð_device, &sdhi0_device, @@ -204,6 +232,8 @@ static struct platform_device *marzen_devices[] __initdata = { &hspi_device, &leds_device, &usb_phy, + &camera0_device, + &camera1_device, }; static const struct pinctrl_map marzen_pinctrl_map[] = { @@ -239,6 +269,16 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { /* USB2 */ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", "usb2", "usb2"), + /* VIN1 */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", + "vin1_clk", "vin1"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779", + "vin1_data8", "vin1"), + /* VIN3 */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", + "vin3_clk", "vin3"), + PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779", + "vin3_data8", "vin3"), }; static void __init marzen_init(void) @@ -254,6 +294,8 @@ static void __init marzen_init(void) r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ r8a7779_add_standard_devices(); + r8a7779_add_vin_device(1, &vin_platform_data); + r8a7779_add_vin_device(3, &vin_platform_data); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index de10fd78bf2b..c826bca4024e 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), - CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), + CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), + CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index a0e9eb72e46d..c4bf2d8fb111 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -106,6 +106,7 @@ enum { MSTP331, MSTP323, MSTP322, MSTP321, MSTP114, + MSTP110, MSTP109, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -119,6 +120,8 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ + [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ @@ -146,6 +149,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ + CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 10340f5becbb..bd6ad922eb7e 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -112,7 +112,9 @@ static struct clk *main_clks[] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, + MSTP120, MSTP116, MSTP115, MSTP114, + MSTP110, MSTP109, MSTP108, MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -125,9 +127,13 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */ [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */ + [MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 9, 0), /* VIN1 */ + [MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 8, 0), /* VIN2 */ [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ @@ -162,10 +168,14 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &clkp_clk), /* MSTP32 clocks */ + CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */ CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ + CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ + CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */ CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 50d96f9cf981..fc36d3db0b4d 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -51,6 +51,7 @@ #define SMSTPCR3 0xe615013c #define SMSTPCR5 0xe6150144 #define SMSTPCR7 0xe615014c +#define SMSTPCR8 0xe6150990 #define SDCKCR 0xE6150074 #define SD2CKCR 0xE6150078 @@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { + MSTP813, MSTP721, MSTP720, MSTP717, MSTP716, MSTP522, @@ -190,6 +192,7 @@ enum { }; static struct clk mstp_clks[MSTP_NR] = { + [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ @@ -258,6 +261,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), + CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index bfd920083a3b..f45dde701d7b 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu) lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits ldr r2, [r0, #8] @ SCU Power Status Register mov r3, #3 - bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) + lsl r3, r3, r1 + bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) str r2, [r0, #8] @ write back b shmobile_invalidate_start ENDPROC(shmobile_boot_scu) .text + .align 2 .globl shmobile_scu_base shmobile_scu_base: .space 4 diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 55017f507e96..f93751caf5cb 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -24,12 +24,16 @@ ENDPROC(shmobile_invalidate_start) * This will be mapped at address 0 by SBAR register. * We need _long_ jump to the physical address. */ + .arm .align 12 ENTRY(shmobile_boot_vector) ldr r0, 2f - ldr pc, 1f + ldr r1, 1f + bx r1 + ENDPROC(shmobile_boot_vector) + .align 2 .globl shmobile_boot_fn shmobile_boot_fn: 1: .space 4 diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 41fd6da27574..adfcf51b163d 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -19,10 +19,13 @@ #define __ASM_R8A7778_H__ #include <linux/sh_eth.h> +#include <linux/platform_data/camera-rcar.h> extern void r8a7778_add_standard_devices(void); extern void r8a7778_add_standard_devices_dt(void); extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7778_add_vin_device(int id, + struct rcar_vin_platform_data *pdata); extern void r8a7778_add_dt_devices(void); extern void r8a7778_init_late(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index f08d6ecf5d1d..11c740047e14 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -4,6 +4,7 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> #include <linux/sh_eth.h> +#include <linux/platform_data/camera-rcar.h> struct platform_device; @@ -32,6 +33,8 @@ extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7779_add_vin_device(int idx, + struct rcar_vin_platform_data *pdata); extern void r8a7779_init_late(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index f2d8744c1f14..c3c4669a2d72 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -1,7 +1,6 @@ #ifndef ZBOOT_H #define ZBOOT_H -#include <asm/mach-types.h> #include <mach/zboot_macros.h> /************************************************** @@ -11,7 +10,6 @@ **************************************************/ #ifdef CONFIG_MACH_MACKEREL -#define MACH_TYPE MACH_TYPE_MACKEREL #define MEMORY_START 0x40000000 #include "mach/head-mackerel.txt" #else diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index fed753dbfe42..3ad531caf4f0 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -174,7 +174,8 @@ static struct resource pmu_resources[] = { void __init emev2_add_standard_devices(void) { - emev2_clock_init(); + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + emev2_clock_init(); emev2_register_uart(0); emev2_register_uart(1); diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 604cf36b5616..6a2657ebd197 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -281,6 +281,40 @@ void __init r8a7778_register_hspi(int id) hspi_resources + (2 * id), 2); } +/* VIN */ +#define R8A7778_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5a)), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7778-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ +} + +R8A7778_VIN(0); +R8A7778_VIN(1); + +static struct platform_device_info *vin_info_table[] __initdata = { + &vin0_info, + &vin1_info, +}; + +void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) +{ + BUG_ON(id < 0 || id > 1); + + vin_info_table[id]->data = pdata; + vin_info_table[id]->size_data = sizeof(*pdata); + + platform_device_register_full(vin_info_table[id]); +} + void __init r8a7778_add_dt_devices(void) { int i; diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 6a9933395434..b5b2f787da2e 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -605,6 +605,33 @@ static struct resource ether_resources[] __initdata = { }, }; +#define R8A7779_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7779-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ +} + +R8A7779_VIN(0); +R8A7779_VIN(1); +R8A7779_VIN(2); +R8A7779_VIN(3); + +static struct platform_device_info *vin_info_table[] __initdata = { + &vin0_info, + &vin1_info, + &vin2_info, + &vin3_info, +}; + static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -648,6 +675,16 @@ void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) pdata, sizeof(*pdata)); } +void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) +{ + BUG_ON(id < 0 || id > 3); + + vin_info_table[id]->data = pdata; + vin_info_table[id]->size_data = sizeof(*pdata); + + platform_device_register_full(vin_info_table[id]); +} + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index 53f4840e4949..9782862899e8 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -41,6 +41,7 @@ sh7372_resume_core_standby_sysc: ldr pc, 1f + .align 2 .globl sh7372_cpu_resume sh7372_cpu_resume: 1: .space 4 @@ -96,6 +97,7 @@ sh7372_do_idle_sysc: 1: b 1b + .align 2 kernel_flush: .word v7_flush_dcache_all #endif diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index 442917eedff3..df0d59afeb40 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -23,7 +23,7 @@ config ARCH_SPEAR13XX select CPU_V7 select GPIO_SPEAR_SPICS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL diff --git a/arch/arm/mach-spear/include/mach/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S deleted file mode 100644 index 75b05ad0fbad..000000000000 --- a/arch/arm/mach-spear/include/mach/debug-macro.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/debug-macro.S - * - * Debugging macro include header for spear platform - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar <viresh.linux@gmail.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/amba/serial.h> -#include <mach/spear.h> - - .macro addruart, rp, rv, tmp - mov \rp, #SPEAR_DBG_UART_BASE @ Physical base - mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base - .endm - - .macro senduart, rd, rx - strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER - .endm - - .macro waituart, rd, rx -1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART01x_FR_TXFF @ TX_FULL - bne 1001b - .endm - - .macro busyuart, rd, rx -1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER - tst \rd, #UART011_FR_TXFE @ TX_EMPTY - beq 1002b - .endm diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h index cf3a5369eeca..5cdc53d9b653 100644 --- a/arch/arm/mach-spear/include/mach/spear.h +++ b/arch/arm/mach-spear/include/mach/spear.h @@ -39,7 +39,6 @@ /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR_ICM1_UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_SPEAR_ICM1_UART_BASE /* Sysctl base for spear platform */ #define SPEAR_SYS_CTRL_BASE SPEAR_ICM3_SYS_CTRL_BASE @@ -86,7 +85,6 @@ /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE UART_BASE -#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE #endif /* SPEAR13XX */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 5b045e302b43..3ab2f65f8a50 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -10,3 +10,5 @@ config ARCH_SUNXI select SPARSE_IRQ select SUN4I_TIMER select PINCTRL_SUNXI + select ARM_GIC + select HAVE_SMP diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot deleted file mode 100644 index 46d4cf0841c0..000000000000 --- a/arch/arm/mach-sunxi/Makefile.boot +++ /dev/null @@ -1 +0,0 @@ -zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000 diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 38a3c55527c8..e79fb3469341 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -27,10 +27,19 @@ #include <asm/system_misc.h> #define SUN4I_WATCHDOG_CTRL_REG 0x00 -#define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) +#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) #define SUN4I_WATCHDOG_MODE_REG 0x04 -#define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) -#define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) +#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0) +#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1) + +#define SUN6I_WATCHDOG1_IRQ_REG 0x00 +#define SUN6I_WATCHDOG1_CTRL_REG 0x10 +#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0) +#define SUN6I_WATCHDOG1_CONFIG_REG 0x14 +#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0) +#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1) +#define SUN6I_WATCHDOG1_MODE_REG 0x18 +#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0) static void __iomem *wdt_base; @@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd) } } +static void sun6i_restart(enum reboot_mode mode, const char *cmd) +{ + if (!wdt_base) + return; + + /* Disable interrupts */ + writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG); + + /* We want to disable the IRQ and just reset the whole system */ + writel(SUN6I_WATCHDOG1_CONFIG_RESTART, + wdt_base + SUN6I_WATCHDOG1_CONFIG_REG); + + /* Enable timer. The default and lowest interval value is 0.5s */ + writel(SUN6I_WATCHDOG1_MODE_ENABLE, + wdt_base + SUN6I_WATCHDOG1_MODE_REG); + + /* Restart the watchdog. */ + writel(SUN6I_WATCHDOG1_CTRL_RESTART, + wdt_base + SUN6I_WATCHDOG1_CTRL_REG); + + while (1) { + mdelay(5); + writel(SUN6I_WATCHDOG1_MODE_ENABLE, + wdt_base + SUN6I_WATCHDOG1_MODE_REG); + } +} + static struct of_device_id sunxi_restart_ids[] = { { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, + { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, { /*sentinel*/ } }; @@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", "allwinner,sun5i-a10s", "allwinner,sun5i-a13", + "allwinner,sun6i-a31", + "allwinner,sun7i-a20", NULL, }; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ef3a8da49b2d..67a76f2dfb9f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -2,18 +2,25 @@ config ARCH_TEGRA bool "NVIDIA Tegra" if ARCH_MULTI_V7 select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ARM_GIC select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK + select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PINCTRL select SOC_BUS select SPARSE_IRQ + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY select USE_OF help This enables support for NVIDIA Tegra based systems. @@ -27,15 +34,9 @@ config ARCH_TEGRA_2x_SOC select ARM_ERRATA_720789 select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP - select ARM_GIC - select CPU_V7 - select PINCTRL select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB_PHY - select USB_ULPI_VIEWPORT if USB_PHY help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -44,14 +45,8 @@ config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP - select ARM_GIC - select CPU_V7 - select PINCTRL select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB_PHY - select USB_ULPI_VIEWPORT if USB_PHY help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -59,20 +54,13 @@ config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_114_SOC bool "Enable support for Tegra114 family" select HAVE_ARM_ARCH_TIMER - select ARM_GIC + select ARM_ERRATA_798181 select ARM_L1_CACHE_SHIFT_6 - select CPU_V7 - select PINCTRL select PINCTRL_TEGRA114 help Support for NVIDIA Tegra T114 processor family, based on the ARM CortexA15MP CPU -config TEGRA_PCI - bool "PCI Express support" - depends on ARCH_TEGRA_2x_SOC - select PCI - config TEGRA_AHB bool "Enable AHB driver for NVIDIA Tegra SoCs" default y diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 98b184efc110..e7e5f45c6558 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -17,24 +17,24 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o endif obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o endif obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o - obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c deleted file mode 100644 index 035b240b9e15..000000000000 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/mach-tegra/board-harmony-pcie.c - * - * Copyright (C) 2010 CompuLab, Ltd. - * Mike Rapoport <mike@compulab.co.il> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/gpio.h> -#include <linux/err.h> -#include <linux/of_gpio.h> -#include <linux/regulator/consumer.h> - -#include <asm/mach-types.h> - -#include "board.h" - -#ifdef CONFIG_TEGRA_PCI - -int __init harmony_pcie_init(void) -{ - struct device_node *np; - int en_vdd_1v05; - struct regulator *regulator = NULL; - int err; - - np = of_find_node_by_path("/regulators/regulator@3"); - if (!np) { - pr_err("%s: of_find_node_by_path failed\n", __func__); - return -ENODEV; - } - - en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0); - if (en_vdd_1v05 < 0) { - pr_err("%s: of_get_named_gpio failed: %d\n", __func__, - en_vdd_1v05); - return en_vdd_1v05; - } - - err = gpio_request(en_vdd_1v05, "EN_VDD_1V05"); - if (err) { - pr_err("%s: gpio_request failed: %d\n", __func__, err); - return err; - } - - gpio_direction_output(en_vdd_1v05, 1); - - regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk"); - if (IS_ERR(regulator)) { - err = PTR_ERR(regulator); - pr_err("%s: regulator_get failed: %d\n", __func__, err); - goto err_reg; - } - - err = regulator_enable(regulator); - if (err) { - pr_err("%s: regulator_enable failed: %d\n", __func__, err); - goto err_en; - } - - err = tegra_pcie_init(true, true); - if (err) { - pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err); - goto err_pcie; - } - - return 0; - -err_pcie: - regulator_disable(regulator); -err_en: - regulator_put(regulator); -err_reg: - gpio_free(en_vdd_1v05); - - return err; -} - -#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 9a6659fe2dc2..db6810dc0b3d 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -31,7 +31,6 @@ void __init tegra_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_dt_init_irq(void); -int __init tegra_pcie_init(bool init_port0, bool init_port1); void tegra_init_late(void); @@ -48,13 +47,6 @@ int __init tegra_powergate_debugfs_init(void); static inline int tegra_powergate_debugfs_init(void) { return 0; } #endif -int __init harmony_regulator_init(void); -#ifdef CONFIG_TEGRA_PCI -int __init harmony_pcie_init(void); -#else -static inline int harmony_pcie_init(void) { return 0; } -#endif - void __init tegra_paz00_wifikill_init(void); #endif diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 32f8eb3fe344..5900cc44f780 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops; extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); -extern int tegra_cpu_disable(unsigned int cpu); diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index 1d1c6023f4a2..e0b87300243d 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -17,15 +17,64 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/clockchips.h> #include <asm/cpuidle.h> +#include <asm/suspend.h> +#include <asm/smp_plat.h> + +#include "pm.h" +#include "sleep.h" + +#ifdef CONFIG_PM_SLEEP +#define TEGRA114_MAX_STATES 2 +#else +#define TEGRA114_MAX_STATES 1 +#endif + +#ifdef CONFIG_PM_SLEEP +static int tegra114_idle_power_down(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + local_fiq_disable(); + + tegra_set_cpu_in_lp2(); + cpu_pm_enter(); + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); + + cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); + + cpu_pm_exit(); + tegra_clear_cpu_in_lp2(); + + local_fiq_enable(); + + return index; +} +#endif static struct cpuidle_driver tegra_idle_driver = { .name = "tegra_idle", .owner = THIS_MODULE, - .state_count = 1, + .state_count = TEGRA114_MAX_STATES, .states = { [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), +#ifdef CONFIG_PM_SLEEP + [1] = { + .enter = tegra114_idle_power_down, + .exit_latency = 500, + .target_residency = 1000, + .power_usage = 0, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "powered-down", + .desc = "CPU power gated", + }, +#endif }, }; diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 706aa4215c36..b82dcaee2ef4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -211,6 +211,18 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, } #endif +/* + * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether + * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around + * this, simply disable LP2 if the PCI driver and DT node are both enabled. + */ +void tegra20_cpuidle_pcie_irqs_in_use(void) +{ + pr_info_once( + "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); + tegra_idle_driver.states[1].disabled = true; +} + int __init tegra20_cpuidle_init(void) { return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index e85973cef037..0961dfcf83a4 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -44,3 +44,13 @@ void __init tegra_cpuidle_init(void) break; } } + +void tegra_cpuidle_pcie_irqs_in_use(void) +{ + switch (tegra_chip_id) { + case TEGRA20: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_cpuidle_pcie_irqs_in_use(); + break; + } +} diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 9ec2c1ab0fa4..c017dab60ffa 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -19,6 +19,7 @@ #ifdef CONFIG_CPU_IDLE int tegra20_cpuidle_init(void); +void tegra20_cpuidle_pcie_irqs_in_use(void); int tegra30_cpuidle_init(void); int tegra114_cpuidle_init(void); void tegra_cpuidle_init(void); diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index b477ef310dcd..5348543382bf 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -86,6 +86,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; break; case TEGRA30: + case TEGRA114: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ @@ -123,6 +124,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; break; case TEGRA30: + case TEGRA114: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 7a29bae799a7..c89aac60a143 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -28,9 +28,18 @@ #define FLOW_CTRL_SCLK_RESUME (1 << 27) #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) +#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) +#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) +#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) #define FLOW_CTRL_CPU0_CSR 0x8 #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) +#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) +#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ + FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ + FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) #define FLOW_CTRL_CSR_ENABLE (1 << 0) #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 #define FLOW_CTRL_CPU1_CSR 0x18 diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 045c16f2dd51..2072e7322c39 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -6,6 +6,7 @@ .section ".text.head", "ax" ENTRY(tegra_secondary_startup) - bl v7_invalidate_l1 + check_cpu_part_num 0xc09, r8, r9 + bleq v7_invalidate_l1 b secondary_startup ENDPROC(tegra_secondary_startup) diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index a52c10e0a857..04de2e860923 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu) void __ref tegra_cpu_die(unsigned int cpu) { /* Clean L1 data cache */ - tegra_disable_clean_inv_dcache(); + tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); /* Shut down the current CPU. */ tegra_hotplug_shutdown(); @@ -46,17 +46,6 @@ void __ref tegra_cpu_die(unsigned int cpu) BUG(); } -int tegra_cpu_disable(unsigned int cpu) -{ - switch (tegra_chip_id) { - case TEGRA20: - case TEGRA30: - return cpu == 0 ? -EPERM : 0; - default: - return 0; - } -} - void __init tegra_hotplug_init(void) { if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 399fbca27102..3f5fa0749bde 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -24,6 +24,8 @@ #define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_SIZE SZ_256K +#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) + #define TEGRA_HOST1X_BASE 0x50000000 #define TEGRA_HOST1X_SIZE 0x24000 @@ -237,6 +239,12 @@ #define TEGRA_KFUSE_BASE 0x7000FC00 #define TEGRA_KFUSE_SIZE SZ_1K +#define TEGRA_EMC0_BASE 0x7001A000 +#define TEGRA_EMC0_SIZE SZ_2K + +#define TEGRA_EMC1_BASE 0x7001A800 +#define TEGRA_EMC1_SIZE SZ_2K + #define TEGRA_CSITE_BASE 0x70040000 #define TEGRA_CSITE_SIZE SZ_256K @@ -278,9 +286,6 @@ #define IO_APB_VIRT IOMEM(0xFE300000) #define IO_APB_SIZE SZ_1M -#define TEGRA_PCIE_BASE 0x80000000 -#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) - #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 0de4eed1493d..1a74d562dca1 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -18,10 +18,12 @@ */ #include <linux/kernel.h> +#include <linux/cpu_pm.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/irqchip/arm-gic.h> #include <linux/syscore_ops.h> @@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS]; static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; +static void __iomem *tegra_gic_cpu_base; #endif bool tegra_pending_sgi(void) @@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void) return 0; } + +static int tegra_gic_notifier(struct notifier_block *self, + unsigned long cmd, void *v) +{ + switch (cmd) { + case CPU_PM_ENTER: + writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block tegra_gic_notifier_block = { + .notifier_call = tegra_gic_notifier, +}; + +static const struct of_device_id tegra114_dt_gic_match[] __initconst = { + { .compatible = "arm,cortex-a15-gic" }, + { } +}; + +static void tegra114_gic_cpu_pm_registration(void) +{ + struct device_node *dn; + + dn = of_find_matching_node(NULL, tegra114_dt_gic_match); + if (!dn) + return; + + tegra_gic_cpu_base = of_iomap(dn, 1); + + cpu_pm_register_notifier(&tegra_gic_notifier_block); +} #else #define tegra_set_wake NULL +static void tegra114_gic_cpu_pm_registration(void) { } #endif void __init tegra_init_irq(void) @@ -252,4 +290,6 @@ void __init tegra_init_irq(void) if (!of_have_populated_dt()) gic_init(0, 29, distbase, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); + + tegra114_gic_cpu_pm_registration(); } diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c deleted file mode 100644 index 46144a19a7e7..000000000000 --- a/arch/arm/mach-tegra/pcie.c +++ /dev/null @@ -1,886 +0,0 @@ -/* - * arch/arm/mach-tegra/pci.c - * - * PCIe host controller driver for TEGRA(2) SOCs - * - * Copyright (c) 2010, CompuLab, Ltd. - * Author: Mike Rapoport <mike@compulab.co.il> - * - * Based on NVIDIA PCIe driver - * Copyright (c) 2008-2009, NVIDIA Corporation. - * - * Bits taken from arch/arm/mach-dove/pcie.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/export.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-powergate.h> - -#include <asm/sizes.h> -#include <asm/mach/pci.h> - -#include "board.h" -#include "iomap.h" - -/* Hack - need to parse this from DT */ -#define INT_PCIE_INTR 130 - -/* register definitions */ -#define AFI_OFFSET 0x3800 -#define PADS_OFFSET 0x3000 -#define RP0_OFFSET 0x0000 -#define RP1_OFFSET 0x1000 - -#define AFI_AXI_BAR0_SZ 0x00 -#define AFI_AXI_BAR1_SZ 0x04 -#define AFI_AXI_BAR2_SZ 0x08 -#define AFI_AXI_BAR3_SZ 0x0c -#define AFI_AXI_BAR4_SZ 0x10 -#define AFI_AXI_BAR5_SZ 0x14 - -#define AFI_AXI_BAR0_START 0x18 -#define AFI_AXI_BAR1_START 0x1c -#define AFI_AXI_BAR2_START 0x20 -#define AFI_AXI_BAR3_START 0x24 -#define AFI_AXI_BAR4_START 0x28 -#define AFI_AXI_BAR5_START 0x2c - -#define AFI_FPCI_BAR0 0x30 -#define AFI_FPCI_BAR1 0x34 -#define AFI_FPCI_BAR2 0x38 -#define AFI_FPCI_BAR3 0x3c -#define AFI_FPCI_BAR4 0x40 -#define AFI_FPCI_BAR5 0x44 - -#define AFI_CACHE_BAR0_SZ 0x48 -#define AFI_CACHE_BAR0_ST 0x4c -#define AFI_CACHE_BAR1_SZ 0x50 -#define AFI_CACHE_BAR1_ST 0x54 - -#define AFI_MSI_BAR_SZ 0x60 -#define AFI_MSI_FPCI_BAR_ST 0x64 -#define AFI_MSI_AXI_BAR_ST 0x68 - -#define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) - -#define AFI_FPCI_ERROR_MASKS 0xb0 - -#define AFI_INTR_MASK 0xb4 -#define AFI_INTR_MASK_INT_MASK (1 << 0) -#define AFI_INTR_MASK_MSI_MASK (1 << 8) - -#define AFI_INTR_CODE 0xb8 -#define AFI_INTR_CODE_MASK 0xf -#define AFI_INTR_MASTER_ABORT 4 -#define AFI_INTR_LEGACY 6 - -#define AFI_INTR_SIGNATURE 0xbc -#define AFI_SM_INTR_ENABLE 0xc4 - -#define AFI_AFI_INTR_ENABLE 0xc8 -#define AFI_INTR_EN_INI_SLVERR (1 << 0) -#define AFI_INTR_EN_INI_DECERR (1 << 1) -#define AFI_INTR_EN_TGT_SLVERR (1 << 2) -#define AFI_INTR_EN_TGT_DECERR (1 << 3) -#define AFI_INTR_EN_TGT_WRERR (1 << 4) -#define AFI_INTR_EN_DFPCI_DECERR (1 << 5) -#define AFI_INTR_EN_AXI_DECERR (1 << 6) -#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) - -#define AFI_PCIE_CONFIG 0x0f8 -#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1) -#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2) -#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) -#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) -#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) - -#define AFI_FUSE 0x104 -#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) - -#define AFI_PEX0_CTRL 0x110 -#define AFI_PEX1_CTRL 0x118 -#define AFI_PEX_CTRL_RST (1 << 0) -#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) - -#define RP_VEND_XP 0x00000F00 -#define RP_VEND_XP_DL_UP (1 << 30) - -#define RP_LINK_CONTROL_STATUS 0x00000090 -#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 - -#define PADS_CTL_SEL 0x0000009C - -#define PADS_CTL 0x000000A0 -#define PADS_CTL_IDDQ_1L (1 << 0) -#define PADS_CTL_TX_DATA_EN_1L (1 << 6) -#define PADS_CTL_RX_DATA_EN_1L (1 << 10) - -#define PADS_PLL_CTL 0x000000B8 -#define PADS_PLL_CTL_RST_B4SM (1 << 1) -#define PADS_PLL_CTL_LOCKDET (1 << 8) -#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) -#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) -#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) -#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) -#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) -#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) -#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) - -/* PMC access is required for PCIE xclk (un)clamping */ -#define PMC_SCRATCH42 0x144 -#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) - -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); - -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) - -/* - * Tegra2 defines 1GB in the AXI address map for PCIe. - * - * That address space is split into different regions, with sizes and - * offsets as follows: - * - * 0x80000000 - 0x80003fff - PCI controller registers - * 0x80004000 - 0x80103fff - PCI configuration space - * 0x80104000 - 0x80203fff - PCI extended configuration space - * 0x80203fff - 0x803fffff - unused - * 0x80400000 - 0x8040ffff - downstream IO - * 0x80410000 - 0x8fffffff - unused - * 0x90000000 - 0x9fffffff - non-prefetchable memory - * 0xa0000000 - 0xbfffffff - prefetchable memory - */ -#define PCIE_REGS_SZ SZ_16K -#define PCIE_CFG_OFF PCIE_REGS_SZ -#define PCIE_CFG_SZ SZ_1M -#define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF) -#define PCIE_EXT_CFG_SZ SZ_1M -#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) - -#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) -#define MEM_SIZE_0 SZ_128M -#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) -#define MEM_SIZE_1 SZ_128M -#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1) -#define PREFETCH_MEM_SIZE_0 SZ_128M -#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0) -#define PREFETCH_MEM_SIZE_1 SZ_128M - -#define PCIE_CONF_BUS(b) ((b) << 16) -#define PCIE_CONF_DEV(d) ((d) << 11) -#define PCIE_CONF_FUNC(f) ((f) << 8) -#define PCIE_CONF_REG(r) \ - (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) - -struct tegra_pcie_port { - int index; - u8 root_bus_nr; - void __iomem *base; - - bool link_up; - - char mem_space_name[16]; - char prefetch_space_name[20]; - struct resource res[2]; -}; - -struct tegra_pcie_info { - struct tegra_pcie_port port[2]; - int num_ports; - - void __iomem *regs; - struct resource res_mmio; - - struct clk *pex_clk; - struct clk *afi_clk; - struct clk *pcie_xclk; - struct clk *pll_e; -}; - -static struct tegra_pcie_info tegra_pcie; - -static inline void afi_writel(u32 value, unsigned long offset) -{ - writel(value, offset + AFI_OFFSET + tegra_pcie.regs); -} - -static inline u32 afi_readl(unsigned long offset) -{ - return readl(offset + AFI_OFFSET + tegra_pcie.regs); -} - -static inline void pads_writel(u32 value, unsigned long offset) -{ - writel(value, offset + PADS_OFFSET + tegra_pcie.regs); -} - -static inline u32 pads_readl(unsigned long offset) -{ - return readl(offset + PADS_OFFSET + tegra_pcie.regs); -} - -static struct tegra_pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = tegra_pcie.num_ports - 1; i >= 0; i--) { - int rbus = tegra_pcie.port[i].root_bus_nr; - if (rbus != -1 && rbus == bus) - break; - } - - return i >= 0 ? tegra_pcie.port + i : NULL; -} - -static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - struct tegra_pcie_port *pp = bus_to_port(bus->number); - void __iomem *addr; - - if (pp) { - if (devfn != 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - addr = pp->base + (where & ~0x3); - } else { - addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + - PCIE_CONF_DEV(PCI_SLOT(devfn)) + - PCIE_CONF_FUNC(PCI_FUNC(devfn)) + - PCIE_CONF_REG(where)); - } - - *val = readl(addr); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xff; - else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xffff; - - return PCIBIOS_SUCCESSFUL; -} - -static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct tegra_pcie_port *pp = bus_to_port(bus->number); - void __iomem *addr; - - u32 mask; - u32 tmp; - - if (pp) { - if (devfn != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - addr = pp->base + (where & ~0x3); - } else { - addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) + - PCIE_CONF_DEV(PCI_SLOT(devfn)) + - PCIE_CONF_FUNC(PCI_FUNC(devfn)) + - PCIE_CONF_REG(where)); - } - - if (size == 4) { - writel(val, addr); - return PCIBIOS_SUCCESSFUL; - } - - if (size == 2) - mask = ~(0xffff << ((where & 0x3) * 8)); - else if (size == 1) - mask = ~(0xff << ((where & 0x3) * 8)); - else - return PCIBIOS_BAD_REGISTER_NUMBER; - - tmp = readl(addr) & mask; - tmp |= val << ((where & 0x3) * 8); - writel(tmp, addr); - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops tegra_pcie_ops = { - .read = tegra_pcie_read_conf, - .write = tegra_pcie_write_conf, -}; - -static void tegra_pcie_fixup_bridge(struct pci_dev *dev) -{ - u16 reg; - - if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { - pci_read_config_word(dev, PCI_COMMAND, ®); - reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - pci_write_config_word(dev, PCI_COMMAND, reg); - } -} -DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); - -/* Tegra PCIE root complex wrongly reports device class */ -static void tegra_pcie_fixup_class(struct pci_dev *dev) -{ - dev->class = PCI_CLASS_BRIDGE_PCI << 8; -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); - -/* Tegra PCIE requires relaxed ordering */ -static void tegra_pcie_relax_enable(struct pci_dev *dev) -{ - pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); -} -DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); - -static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct tegra_pcie_port *pp; - - if (nr >= tegra_pcie.num_ports) - return 0; - - pp = tegra_pcie.port + nr; - pp->root_bus_nr = sys->busnr; - - pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE); - - /* - * IORESOURCE_MEM - */ - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), - "PCIe %d MEM", pp->index); - pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[0].name = pp->mem_space_name; - if (pp->index == 0) { - pp->res[0].start = MEM_BASE_0; - pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1; - } else { - pp->res[0].start = MEM_BASE_1; - pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1; - } - pp->res[0].flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res[0])) - panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset); - - /* - * IORESOURCE_MEM | IORESOURCE_PREFETCH - */ - snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), - "PCIe %d PREFETCH MEM", pp->index); - pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; - pp->res[1].name = pp->prefetch_space_name; - if (pp->index == 0) { - pp->res[1].start = PREFETCH_MEM_BASE_0; - pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1; - } else { - pp->res[1].start = PREFETCH_MEM_BASE_1; - pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1; - } - pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (request_resource(&iomem_resource, &pp->res[1])) - panic("Request PCIe Prefetch Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); - - return 1; -} - -static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return INT_PCIE_INTR; -} - -static struct pci_bus __init *tegra_pcie_scan_bus(int nr, - struct pci_sys_data *sys) -{ - struct tegra_pcie_port *pp; - - if (nr >= tegra_pcie.num_ports) - return NULL; - - pp = tegra_pcie.port + nr; - pp->root_bus_nr = sys->busnr; - - return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys, - &sys->resources); -} - -static struct hw_pci tegra_pcie_hw __initdata = { - .nr_controllers = 2, - .setup = tegra_pcie_setup, - .scan = tegra_pcie_scan_bus, - .map_irq = tegra_pcie_map_irq, -}; - - -static irqreturn_t tegra_pcie_isr(int irq, void *arg) -{ - const char *err_msg[] = { - "Unknown", - "AXI slave error", - "AXI decode error", - "Target abort", - "Master abort", - "Invalid write", - "Response decoding error", - "AXI response decoding error", - "Transcation timeout", - }; - - u32 code, signature; - - code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK; - signature = afi_readl(AFI_INTR_SIGNATURE); - afi_writel(0, AFI_INTR_CODE); - - if (code == AFI_INTR_LEGACY) - return IRQ_NONE; - - if (code >= ARRAY_SIZE(err_msg)) - code = 0; - - /* - * do not pollute kernel log with master abort reports since they - * happen a lot during enumeration - */ - if (code == AFI_INTR_MASTER_ABORT) - pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature); - else - pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature); - - return IRQ_HANDLED; -} - -static void tegra_pcie_setup_translations(void) -{ - u32 fpci_bar; - u32 size; - u32 axi_address; - - /* Bar 0: config Bar */ - fpci_bar = ((u32)0xfdff << 16); - size = PCIE_CFG_SZ; - axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF; - afi_writel(axi_address, AFI_AXI_BAR0_START); - afi_writel(size >> 12, AFI_AXI_BAR0_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR0); - - /* Bar 1: extended config Bar */ - fpci_bar = ((u32)0xfe1 << 20); - size = PCIE_EXT_CFG_SZ; - axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF; - afi_writel(axi_address, AFI_AXI_BAR1_START); - afi_writel(size >> 12, AFI_AXI_BAR1_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR1); - - /* Bar 2: downstream IO bar */ - fpci_bar = ((__u32)0xfdfc << 16); - size = SZ_128K; - axi_address = TEGRA_PCIE_IO_BASE; - afi_writel(axi_address, AFI_AXI_BAR2_START); - afi_writel(size >> 12, AFI_AXI_BAR2_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR2); - - /* Bar 3: prefetchable memory BAR */ - fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1; - size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1; - axi_address = PREFETCH_MEM_BASE_0; - afi_writel(axi_address, AFI_AXI_BAR3_START); - afi_writel(size >> 12, AFI_AXI_BAR3_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR3); - - /* Bar 4: non prefetchable memory BAR */ - fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1; - size = MEM_SIZE_0 + MEM_SIZE_1; - axi_address = MEM_BASE_0; - afi_writel(axi_address, AFI_AXI_BAR4_START); - afi_writel(size >> 12, AFI_AXI_BAR4_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR4); - - /* Bar 5: NULL out the remaining BAR as it is not used */ - fpci_bar = 0; - size = 0; - axi_address = 0; - afi_writel(axi_address, AFI_AXI_BAR5_START); - afi_writel(size >> 12, AFI_AXI_BAR5_SZ); - afi_writel(fpci_bar, AFI_FPCI_BAR5); - - /* map all upstream transactions as uncached */ - afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST); - afi_writel(0, AFI_CACHE_BAR0_SZ); - afi_writel(0, AFI_CACHE_BAR1_ST); - afi_writel(0, AFI_CACHE_BAR1_SZ); - - /* No MSI */ - afi_writel(0, AFI_MSI_FPCI_BAR_ST); - afi_writel(0, AFI_MSI_BAR_SZ); - afi_writel(0, AFI_MSI_AXI_BAR_ST); - afi_writel(0, AFI_MSI_BAR_SZ); -} - -static int tegra_pcie_enable_controller(void) -{ - u32 val, reg; - int i, timeout; - - /* Enable slot clock and pulse the reset signals */ - for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { - val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN; - afi_writel(val, reg); - val &= ~AFI_PEX_CTRL_RST; - afi_writel(val, reg); - - val = afi_readl(reg) | AFI_PEX_CTRL_RST; - afi_writel(val, reg); - } - - /* Enable dual controller and both ports */ - val = afi_readl(AFI_PCIE_CONFIG); - val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | - AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | - AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK); - val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; - afi_writel(val, AFI_PCIE_CONFIG); - - val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; - afi_writel(val, AFI_FUSE); - - /* Initialze internal PHY, enable up to 16 PCIE lanes */ - pads_writel(0x0, PADS_CTL_SEL); - - /* override IDDQ to 1 on all 4 lanes */ - val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L; - pads_writel(val, PADS_CTL); - - /* - * set up PHY PLL inputs select PLLE output as refclock, - * set TX ref sel to div10 (not div5) - */ - val = pads_readl(PADS_PLL_CTL); - val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); - val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); - pads_writel(val, PADS_PLL_CTL); - - /* take PLL out of reset */ - val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM; - pads_writel(val, PADS_PLL_CTL); - - /* - * Hack, set the clock voltage to the DEFAULT provided by hw folks. - * This doesn't exist in the documentation - */ - pads_writel(0xfa5cfa5c, 0xc8); - - /* Wait for the PLL to lock */ - timeout = 300; - do { - val = pads_readl(PADS_PLL_CTL); - usleep_range(1000, 1000); - if (--timeout == 0) { - pr_err("Tegra PCIe error: timeout waiting for PLL\n"); - return -EBUSY; - } - } while (!(val & PADS_PLL_CTL_LOCKDET)); - - /* turn off IDDQ override */ - val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L; - pads_writel(val, PADS_CTL); - - /* enable TX/RX data */ - val = pads_readl(PADS_CTL); - val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); - pads_writel(val, PADS_CTL); - - /* Take the PCIe interface module out of reset */ - tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); - - /* Finally enable PCIe */ - val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI; - afi_writel(val, AFI_CONFIGURATION); - - val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | - AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | - AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR); - afi_writel(val, AFI_AFI_INTR_ENABLE); - afi_writel(0xffffffff, AFI_SM_INTR_ENABLE); - - /* FIXME: No MSI for now, only INT */ - afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); - - /* Disable all execptions */ - afi_writel(0, AFI_FPCI_ERROR_MASKS); - - return 0; -} - -static void tegra_pcie_xclk_clamp(bool clamp) -{ - u32 reg; - - reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; - - if (clamp) - reg |= PMC_SCRATCH42_PCX_CLAMP; - - pmc_writel(reg, PMC_SCRATCH42); -} - -static void tegra_pcie_power_off(void) -{ - tegra_periph_reset_assert(tegra_pcie.pcie_xclk); - tegra_periph_reset_assert(tegra_pcie.afi_clk); - tegra_periph_reset_assert(tegra_pcie.pex_clk); - - tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); - tegra_pcie_xclk_clamp(true); -} - -static int tegra_pcie_power_regate(void) -{ - int err; - - tegra_pcie_power_off(); - - tegra_pcie_xclk_clamp(true); - - tegra_periph_reset_assert(tegra_pcie.pcie_xclk); - tegra_periph_reset_assert(tegra_pcie.afi_clk); - - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, - tegra_pcie.pex_clk); - if (err) { - pr_err("PCIE: powerup sequence failed: %d\n", err); - return err; - } - - tegra_periph_reset_deassert(tegra_pcie.afi_clk); - - tegra_pcie_xclk_clamp(false); - - clk_prepare_enable(tegra_pcie.afi_clk); - clk_prepare_enable(tegra_pcie.pex_clk); - return clk_prepare_enable(tegra_pcie.pll_e); -} - -static int tegra_pcie_clocks_get(void) -{ - int err; - - tegra_pcie.pex_clk = clk_get(NULL, "pex"); - if (IS_ERR(tegra_pcie.pex_clk)) - return PTR_ERR(tegra_pcie.pex_clk); - - tegra_pcie.afi_clk = clk_get(NULL, "afi"); - if (IS_ERR(tegra_pcie.afi_clk)) { - err = PTR_ERR(tegra_pcie.afi_clk); - goto err_afi_clk; - } - - tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk"); - if (IS_ERR(tegra_pcie.pcie_xclk)) { - err = PTR_ERR(tegra_pcie.pcie_xclk); - goto err_pcie_xclk; - } - - tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e"); - if (IS_ERR(tegra_pcie.pll_e)) { - err = PTR_ERR(tegra_pcie.pll_e); - goto err_pll_e; - } - - return 0; - -err_pll_e: - clk_put(tegra_pcie.pcie_xclk); -err_pcie_xclk: - clk_put(tegra_pcie.afi_clk); -err_afi_clk: - clk_put(tegra_pcie.pex_clk); - - return err; -} - -static void tegra_pcie_clocks_put(void) -{ - clk_put(tegra_pcie.pll_e); - clk_put(tegra_pcie.pcie_xclk); - clk_put(tegra_pcie.afi_clk); - clk_put(tegra_pcie.pex_clk); -} - -static int __init tegra_pcie_get_resources(void) -{ - int err; - - err = tegra_pcie_clocks_get(); - if (err) { - pr_err("PCIE: failed to get clocks: %d\n", err); - return err; - } - - err = tegra_pcie_power_regate(); - if (err) { - pr_err("PCIE: failed to power up: %d\n", err); - goto err_pwr_on; - } - - tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); - if (tegra_pcie.regs == NULL) { - pr_err("PCIE: Failed to map PCI/AFI registers\n"); - err = -ENOMEM; - goto err_map_reg; - } - - err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, - IRQF_SHARED, "PCIE", &tegra_pcie); - if (err) { - pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_req_io; - } - set_irq_flags(INT_PCIE_INTR, IRQF_VALID); - - return 0; - -err_req_io: - iounmap(tegra_pcie.regs); -err_map_reg: - tegra_pcie_power_off(); -err_pwr_on: - tegra_pcie_clocks_put(); - - return err; -} - -/* - * FIXME: If there are no PCIe cards attached, then calling this function - * can result in the increase of the bootup time as there are big timeout - * loops. - */ -#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ -static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, - u32 reset_reg) -{ - u32 reg; - int retries = 3; - int timeout; - - do { - timeout = TEGRA_PCIE_LINKUP_TIMEOUT; - while (timeout) { - reg = readl(pp->base + RP_VEND_XP); - - if (reg & RP_VEND_XP_DL_UP) - break; - - mdelay(1); - timeout--; - } - - if (!timeout) { - pr_err("PCIE: port %d: link down, retrying\n", idx); - goto retry; - } - - timeout = TEGRA_PCIE_LINKUP_TIMEOUT; - while (timeout) { - reg = readl(pp->base + RP_LINK_CONTROL_STATUS); - - if (reg & 0x20000000) - return true; - - mdelay(1); - timeout--; - } - -retry: - /* Pulse the PEX reset */ - reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - mdelay(1); - reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - - retries--; - } while (retries); - - return false; -} - -static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) -{ - struct tegra_pcie_port *pp; - - pp = tegra_pcie.port + tegra_pcie.num_ports; - - pp->index = -1; - pp->base = tegra_pcie.regs + offset; - pp->link_up = tegra_pcie_check_link(pp, index, reset_reg); - - if (!pp->link_up) { - pp->base = NULL; - printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); - return; - } - - tegra_pcie.num_ports++; - pp->index = index; - pp->root_bus_nr = -1; - memset(pp->res, 0, sizeof(pp->res)); -} - -int __init tegra_pcie_init(bool init_port0, bool init_port1) -{ - int err; - - if (!(init_port0 || init_port1)) - return -ENODEV; - - pcibios_min_mem = 0; - - err = tegra_pcie_get_resources(); - if (err) - return err; - - err = tegra_pcie_enable_controller(); - if (err) - return err; - - /* setup the AFI address translations */ - tegra_pcie_setup_translations(); - - if (init_port0) - tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL); - - if (init_port1) - tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL); - - pci_common_init(&tegra_pcie_hw); - - return 0; -} diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 97b33a2a2d75..2d0203627fbb 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -196,6 +196,5 @@ struct smp_operations tegra_smp_ops __initdata = { #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, - .cpu_disable = tegra_cpu_disable, #endif }; diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c new file mode 100644 index 000000000000..d65e1d786400 --- /dev/null +++ b/arch/arm/mach-tegra/pm-tegra20.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/kernel.h> + +#include "pm.h" + +#ifdef CONFIG_PM_SLEEP +extern u32 tegra20_iram_start, tegra20_iram_end; +extern void tegra20_sleep_core_finish(unsigned long); + +void tegra20_lp1_iram_hook(void) +{ + tegra_lp1_iram.start_addr = &tegra20_iram_start; + tegra_lp1_iram.end_addr = &tegra20_iram_end; +} + +void tegra20_sleep_core_init(void) +{ + tegra_sleep_core_finish = tegra20_sleep_core_finish; +} +#endif diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c new file mode 100644 index 000000000000..8fa326d6ff1a --- /dev/null +++ b/arch/arm/mach-tegra/pm-tegra30.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/kernel.h> + +#include "pm.h" + +#ifdef CONFIG_PM_SLEEP +extern u32 tegra30_iram_start, tegra30_iram_end; +extern void tegra30_sleep_core_finish(unsigned long); + +void tegra30_lp1_iram_hook(void) +{ + tegra_lp1_iram.start_addr = &tegra30_iram_start; + tegra_lp1_iram.end_addr = &tegra30_iram_end; +} + +void tegra30_sleep_core_init(void) +{ + tegra_sleep_core_finish = tegra30_sleep_core_finish; +} +#endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 261fec140c06..ed294a04e1d3 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -37,12 +37,18 @@ #include "reset.h" #include "flowctrl.h" #include "fuse.h" +#include "pm.h" #include "pmc.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP static DEFINE_SPINLOCK(tegra_lp2_lock); +static u32 iram_save_size; +static void *iram_save_addr; +struct tegra_lp1_iram tegra_lp1_iram; void (*tegra_tear_down_cpu)(void); +void (*tegra_sleep_core_finish)(unsigned long v2p); +static int (*tegra_sleep_func)(unsigned long v2p); static void tegra_tear_down_cpu_init(void) { @@ -52,7 +58,9 @@ static void tegra_tear_down_cpu_init(void) tegra_tear_down_cpu = tegra20_tear_down_cpu; break; case TEGRA30: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + case TEGRA114: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) tegra_tear_down_cpu = tegra30_tear_down_cpu; break; } @@ -171,19 +179,109 @@ void tegra_idle_lp2_last(void) enum tegra_suspend_mode tegra_pm_validate_suspend_mode( enum tegra_suspend_mode mode) { - /* Tegra114 didn't support any suspending mode yet. */ - if (tegra_chip_id == TEGRA114) - return TEGRA_SUSPEND_NONE; - /* - * The Tegra devices only support suspending to LP2 currently. + * The Tegra devices support suspending to LP1 or lower currently. */ - if (mode > TEGRA_SUSPEND_LP2) - return TEGRA_SUSPEND_LP2; + if (mode > TEGRA_SUSPEND_LP1) + return TEGRA_SUSPEND_LP1; return mode; } +static int tegra_sleep_core(unsigned long v2p) +{ + setup_mm_for_reboot(); + tegra_sleep_core_finish(v2p); + + /* should never here */ + BUG(); + + return 0; +} + +/* + * tegra_lp1_iram_hook + * + * Hooking the address of LP1 reset vector and SDRAM self-refresh code in + * SDRAM. These codes not be copied to IRAM in this fuction. We need to + * copy these code to IRAM before LP0/LP1 suspend and restore the content + * of IRAM after resume. + */ +static bool tegra_lp1_iram_hook(void) +{ + switch (tegra_chip_id) { + case TEGRA20: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_lp1_iram_hook(); + break; + case TEGRA30: + case TEGRA114: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) + tegra30_lp1_iram_hook(); + break; + default: + break; + } + + if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) + return false; + + iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; + iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); + if (!iram_save_addr) + return false; + + return true; +} + +static bool tegra_sleep_core_init(void) +{ + switch (tegra_chip_id) { + case TEGRA20: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_sleep_core_init(); + break; + case TEGRA30: + case TEGRA114: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) + tegra30_sleep_core_init(); + break; + default: + break; + } + + if (!tegra_sleep_core_finish) + return false; + + return true; +} + +static void tegra_suspend_enter_lp1(void) +{ + tegra_pmc_suspend(); + + /* copy the reset vector & SDRAM shutdown code into IRAM */ + memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), + iram_save_size); + memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr, + iram_save_size); + + *((u32 *)tegra_cpu_lp1_mask) = 1; +} + +static void tegra_suspend_exit_lp1(void) +{ + tegra_pmc_resume(); + + /* restore IRAM */ + memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, + iram_save_size); + + *(u32 *)tegra_cpu_lp1_mask = 0; +} + static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { [TEGRA_SUSPEND_NONE] = "none", [TEGRA_SUSPEND_LP2] = "LP2", @@ -207,6 +305,9 @@ static int tegra_suspend_enter(suspend_state_t state) suspend_cpu_complex(); switch (mode) { + case TEGRA_SUSPEND_LP1: + tegra_suspend_enter_lp1(); + break; case TEGRA_SUSPEND_LP2: tegra_set_cpu_in_lp2(); break; @@ -214,9 +315,12 @@ static int tegra_suspend_enter(suspend_state_t state) break; } - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); switch (mode) { + case TEGRA_SUSPEND_LP1: + tegra_suspend_exit_lp1(); + break; case TEGRA_SUSPEND_LP2: tegra_clear_cpu_in_lp2(); break; @@ -237,12 +341,36 @@ static const struct platform_suspend_ops tegra_suspend_ops = { void __init tegra_init_suspend(void) { - if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) + enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); + + if (mode == TEGRA_SUSPEND_NONE) return; tegra_tear_down_cpu_init(); tegra_pmc_suspend_init(); + if (mode >= TEGRA_SUSPEND_LP1) { + if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { + pr_err("%s: unable to allocate memory for SDRAM" + "self-refresh -- LP0/LP1 unavailable\n", + __func__); + tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); + mode = TEGRA_SUSPEND_LP2; + } + } + + /* set up sleep function for cpu_suspend */ + switch (mode) { + case TEGRA_SUSPEND_LP1: + tegra_sleep_func = tegra_sleep_core; + break; + case TEGRA_SUSPEND_LP2: + tegra_sleep_func = tegra_sleep_cpu; + break; + default: + break; + } + suspend_set_ops(&tegra_suspend_ops); } #endif diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 94c4b9d9077c..fe204e5256e7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,6 +23,18 @@ #include "pmc.h" +struct tegra_lp1_iram { + void *start_addr; + void *end_addr; +}; +extern struct tegra_lp1_iram tegra_lp1_iram; +extern void (*tegra_sleep_core_finish)(unsigned long v2p); + +void tegra20_lp1_iram_hook(void); +void tegra20_sleep_core_init(void); +void tegra30_lp1_iram_hook(void); +void tegra30_sleep_core_init(void); + extern unsigned long l2x0_saved_regs_addr; void save_cpu_arch_register(void); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index eb3fa4aee0e4..8acb881f7cfe 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -21,11 +21,14 @@ #include <linux/of.h> #include <linux/of_address.h> +#include "flowctrl.h" #include "fuse.h" #include "pm.h" #include "pmc.h" #include "sleep.h" +#define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ +#define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */ #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ @@ -193,16 +196,50 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) return pmc_pm_data.suspend_mode; } +void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) +{ + if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) + return; + + pmc_pm_data.suspend_mode = mode; +} + +void tegra_pmc_suspend(void) +{ + tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); +} + +void tegra_pmc_resume(void) +{ + tegra_pmc_writel(0x0, PMC_SCRATCH41); +} + void tegra_pmc_pm_set(enum tegra_suspend_mode mode) { - u32 reg; + u32 reg, csr_reg; unsigned long rate = 0; reg = tegra_pmc_readl(PMC_CTRL); reg |= TEGRA_POWER_CPU_PWRREQ_OE; reg &= ~TEGRA_POWER_EFFECT_LP0; + switch (tegra_chip_id) { + case TEGRA20: + case TEGRA30: + break; + default: + /* Turn off CRAIL */ + csr_reg = flowctrl_read_cpu_csr(0); + csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; + csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; + flowctrl_write_cpu_csr(0, csr_reg); + break; + } + switch (mode) { + case TEGRA_SUSPEND_LP1: + rate = 32768; + break; case TEGRA_SUSPEND_LP2: rate = clk_get_rate(tegra_pclk); break; @@ -224,6 +261,20 @@ void tegra_pmc_suspend_init(void) reg = tegra_pmc_readl(PMC_CTRL); reg |= TEGRA_POWER_CPU_PWRREQ_OE; tegra_pmc_writel(reg, PMC_CTRL); + + reg = tegra_pmc_readl(PMC_CTRL); + + if (!pmc_pm_data.sysclkreq_high) + reg |= TEGRA_POWER_SYSCLK_POLARITY; + else + reg &= ~TEGRA_POWER_SYSCLK_POLARITY; + + /* configure the output polarity while the request is tristated */ + tegra_pmc_writel(reg, PMC_CTRL); + + /* now enable the request */ + reg |= TEGRA_POWER_SYSCLK_OE; + tegra_pmc_writel(reg, PMC_CTRL); } #endif diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index e1c2df272f7d..549f8c7b762c 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -28,6 +28,9 @@ enum tegra_suspend_mode { #ifdef CONFIG_PM_SLEEP enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); +void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); +void tegra_pmc_suspend(void); +void tegra_pmc_resume(void); void tegra_pmc_pm_set(enum tegra_suspend_mode mode); void tegra_pmc_suspend_init(void); #endif diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 39dc9e7834f3..f527b2c2dea7 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -40,9 +40,12 @@ * re-enabling sdram. * * r6: SoC ID + * r8: CPU part number */ ENTRY(tegra_resume) - bl v7_invalidate_l1 + check_cpu_part_num 0xc09, r8, r9 + bleq v7_invalidate_l1 + blne tegra_init_l2_for_a15 cpu_id r0 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 @@ -70,7 +73,8 @@ no_cpu0_chk: str r1, [r2] 1: - check_cpu_part_num 0xc09, r8, r9 + mov32 r9, 0xc09 + cmp r8, r9 bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ @@ -178,6 +182,19 @@ after_errata: 1: #endif + /* Waking up from LP1? */ + ldr r8, [r12, #RESET_DATA(MASK_LP1)] + tst r8, r11 @ if in_lp1 + beq __is_not_lp1 + cmp r10, #0 + bne __die @ only CPU0 can be here + ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] + cmp lr, #0 + bleq __die @ no LP1 startup handler + THUMB( add lr, lr, #1 ) @ switch to Thumb mode + bx lr +__is_not_lp1: + /* Waking up from LP2? */ ldr r9, [r12, #RESET_DATA(MASK_LP2)] tst r9, r11 @ if in_lp2 diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e0068f..fd0bbf8a6c94 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void) #endif #ifdef CONFIG_PM_SLEEP + __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = + TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index c90d8e9c4ad2..76a93434c6ee 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -39,6 +39,10 @@ void __tegra_cpu_reset_handler_end(void); void tegra_secondary_startup(void); #ifdef CONFIG_PM_SLEEP +#define tegra_cpu_lp1_mask \ + (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ + ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ + (u32)__tegra_cpu_reset_handler_start))) #define tegra_cpu_lp2_mask \ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index e3f2417c420e..5c3bd11c9838 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -23,10 +23,49 @@ #include <asm/assembler.h> #include <asm/proc-fns.h> #include <asm/cp15.h> +#include <asm/cache.h> #include "sleep.h" #include "flowctrl.h" +#define EMC_CFG 0xc +#define EMC_ADR_CFG 0x10 +#define EMC_REFRESH 0x70 +#define EMC_NOP 0xdc +#define EMC_SELF_REF 0xe0 +#define EMC_REQ_CTRL 0x2b0 +#define EMC_EMC_STATUS 0x2b4 + +#define CLK_RESET_CCLK_BURST 0x20 +#define CLK_RESET_CCLK_DIVIDER 0x24 +#define CLK_RESET_SCLK_BURST 0x28 +#define CLK_RESET_SCLK_DIVIDER 0x2c +#define CLK_RESET_PLLC_BASE 0x80 +#define CLK_RESET_PLLM_BASE 0x90 +#define CLK_RESET_PLLP_BASE 0xa0 + +#define APB_MISC_XM2CFGCPADCTRL 0x8c8 +#define APB_MISC_XM2CFGDPADCTRL 0x8cc +#define APB_MISC_XM2CLKCFGPADCTRL 0x8d0 +#define APB_MISC_XM2COMPPADCTRL 0x8d4 +#define APB_MISC_XM2VTTGENPADCTRL 0x8d8 +#define APB_MISC_XM2CFGCPADCTRL2 0x8e4 +#define APB_MISC_XM2CFGDPADCTRL2 0x8e8 + +.macro pll_enable, rd, r_car_base, pll_base + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + orreq \rd, \rd, #(1 << 30) + streq \rd, [\r_car_base, #\pll_base] +.endm + +.macro emc_device_mask, rd, base + ldr \rd, [\base, #EMC_ADR_CFG] + tst \rd, #(0x3 << 24) + moveq \rd, #(0x1 << 8) @ just 1 device + movne \rd, #(0x3 << 8) @ 2 devices +.endm + #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) /* * tegra20_hotplug_shutdown(void) @@ -181,6 +220,28 @@ ENTRY(tegra20_cpu_is_resettable_soon) ENDPROC(tegra20_cpu_is_resettable_soon) /* + * tegra20_sleep_core_finish(unsigned long v2p) + * + * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to + * tegra20_tear_down_core in IRAM + */ +ENTRY(tegra20_sleep_core_finish) + /* Flush, disable the L1 data cache and exit SMP */ + bl tegra_disable_clean_inv_dcache + + mov32 r3, tegra_shut_off_mmu + add r3, r3, r0 + + mov32 r0, tegra20_tear_down_core + mov32 r1, tegra20_iram_start + sub r0, r0, r1 + mov32 r1, TEGRA_IRAM_CODE_AREA + add r0, r0, r1 + + mov pc, r3 +ENDPROC(tegra20_sleep_core_finish) + +/* * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) * * Enters WFI on secondary CPU by exiting coherency. @@ -191,6 +252,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency /* Flush and disable the L1 data cache */ + mov r0, #TEGRA_FLUSH_CACHE_LOUIS bl tegra_disable_clean_inv_dcache mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 @@ -250,6 +312,150 @@ ENTRY(tegra20_tear_down_cpu) b tegra20_enter_sleep ENDPROC(tegra20_tear_down_cpu) +/* START OF ROUTINES COPIED TO IRAM */ + .align L1_CACHE_SHIFT + .globl tegra20_iram_start +tegra20_iram_start: + +/* + * tegra20_lp1_reset + * + * reset vector for LP1 restore; copied into IRAM during suspend. + * Brings the system back up to a safe staring point (SDRAM out of + * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP, + * system clock running on the same PLL that it suspended at), and + * jumps to tegra_resume to restore virtual addressing and PLLX. + * The physical address of tegra_resume expected to be stored in + * PMC_SCRATCH41. + * + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. + */ +ENTRY(tegra20_lp1_reset) + /* + * The CPU and system bus are running at 32KHz and executing from + * IRAM when this code is executed; immediately switch to CLKM and + * enable PLLM, PLLP, PLLC. + */ + mov32 r0, TEGRA_CLK_RESET_BASE + + mov r1, #(1 << 28) + str r1, [r0, #CLK_RESET_SCLK_BURST] + str r1, [r0, #CLK_RESET_CCLK_BURST] + mov r1, #0 + str r1, [r0, #CLK_RESET_CCLK_DIVIDER] + str r1, [r0, #CLK_RESET_SCLK_DIVIDER] + + pll_enable r1, r0, CLK_RESET_PLLM_BASE + pll_enable r1, r0, CLK_RESET_PLLP_BASE + pll_enable r1, r0, CLK_RESET_PLLC_BASE + + adr r2, tegra20_sdram_pad_address + adr r4, tegra20_sdram_pad_save + mov r5, #0 + + ldr r6, tegra20_sdram_pad_size +padload: + ldr r7, [r2, r5] @ r7 is the addr in the pad_address + + ldr r1, [r4, r5] + str r1, [r7] @ restore the value in pad_save + + add r5, r5, #4 + cmp r6, r5 + bne padload + +padload_done: + /* 255uS delay for PLL stabilization */ + mov32 r7, TEGRA_TMRUS_BASE + ldr r1, [r7] + add r1, r1, #0xff + wait_until r1, r7, r9 + + adr r4, tegra20_sclk_save + ldr r4, [r4] + str r4, [r0, #CLK_RESET_SCLK_BURST] + mov32 r4, ((1 << 28) | (4)) @ burst policy is PLLP + str r4, [r0, #CLK_RESET_CCLK_BURST] + + mov32 r0, TEGRA_EMC_BASE + ldr r1, [r0, #EMC_CFG] + bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP + str r1, [r0, #EMC_CFG] + + mov r1, #0 + str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh + mov r1, #1 + str r1, [r0, #EMC_NOP] + str r1, [r0, #EMC_NOP] + str r1, [r0, #EMC_REFRESH] + + emc_device_mask r1, r0 + +exit_selfrefresh_loop: + ldr r2, [r0, #EMC_EMC_STATUS] + ands r2, r2, r1 + bne exit_selfrefresh_loop + + mov r1, #0 @ unstall all transactions + str r1, [r0, #EMC_REQ_CTRL] + + mov32 r0, TEGRA_PMC_BASE + ldr r0, [r0, #PMC_SCRATCH41] + mov pc, r0 @ jump to tegra_resume +ENDPROC(tegra20_lp1_reset) + +/* + * tegra20_tear_down_core + * + * copied into and executed from IRAM + * puts memory in self-refresh for LP0 and LP1 + */ +tegra20_tear_down_core: + bl tegra20_sdram_self_refresh + bl tegra20_switch_cpu_to_clk32k + b tegra20_enter_sleep + +/* + * tegra20_switch_cpu_to_clk32k + * + * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock + * to the 32KHz clock. + */ +tegra20_switch_cpu_to_clk32k: + /* + * start by switching to CLKM to safely disable PLLs, then switch to + * CLKS. + */ + mov r0, #(1 << 28) + str r0, [r5, #CLK_RESET_SCLK_BURST] + str r0, [r5, #CLK_RESET_CCLK_BURST] + mov r0, #0 + str r0, [r5, #CLK_RESET_CCLK_DIVIDER] + str r0, [r5, #CLK_RESET_SCLK_DIVIDER] + + /* 2uS delay delay between changing SCLK and disabling PLLs */ + mov32 r7, TEGRA_TMRUS_BASE + ldr r1, [r7] + add r1, r1, #2 + wait_until r1, r7, r9 + + /* disable PLLM, PLLP and PLLC */ + ldr r0, [r5, #CLK_RESET_PLLM_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLM_BASE] + ldr r0, [r5, #CLK_RESET_PLLP_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLP_BASE] + ldr r0, [r5, #CLK_RESET_PLLC_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLC_BASE] + + /* switch to CLKS */ + mov r0, #0 /* brust policy = 32KHz */ + str r0, [r5, #CLK_RESET_SCLK_BURST] + + mov pc, lr + /* * tegra20_enter_sleep * @@ -274,4 +480,95 @@ halted: isb b halted +/* + * tegra20_sdram_self_refresh + * + * called with MMU off and caches disabled + * puts sdram in self refresh + * must be executed from IRAM + */ +tegra20_sdram_self_refresh: + mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr + + mov r2, #3 + str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests + +emcidle: + ldr r2, [r1, #EMC_EMC_STATUS] + tst r2, #4 + beq emcidle + + mov r2, #1 + str r2, [r1, #EMC_SELF_REF] + + emc_device_mask r2, r1 + +emcself: + ldr r3, [r1, #EMC_EMC_STATUS] + and r3, r3, r2 + cmp r3, r2 + bne emcself @ loop until DDR in self-refresh + + adr r2, tegra20_sdram_pad_address + adr r3, tegra20_sdram_pad_safe + adr r4, tegra20_sdram_pad_save + mov r5, #0 + + ldr r6, tegra20_sdram_pad_size +padsave: + ldr r0, [r2, r5] @ r0 is the addr in the pad_address + + ldr r1, [r0] + str r1, [r4, r5] @ save the content of the addr + + ldr r1, [r3, r5] + str r1, [r0] @ set the save val to the addr + + add r5, r5, #4 + cmp r6, r5 + bne padsave +padsave_done: + + mov32 r5, TEGRA_CLK_RESET_BASE + ldr r0, [r5, #CLK_RESET_SCLK_BURST] + adr r2, tegra20_sclk_save + str r0, [r2] + dsb + mov pc, lr + +tegra20_sdram_pad_address: + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CLKCFGPADCTRL + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2COMPPADCTRL + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2VTTGENPADCTRL + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL2 + .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL2 + +tegra20_sdram_pad_size: + .word tegra20_sdram_pad_size - tegra20_sdram_pad_address + +tegra20_sdram_pad_safe: + .word 0x8 + .word 0x8 + .word 0x0 + .word 0x8 + .word 0x5500 + .word 0x08080040 + .word 0x0 + +tegra20_sclk_save: + .word 0x0 + +tegra20_sdram_pad_save: + .rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4 + .long 0 + .endr + + .ltorg +/* dummy symbol for end of IRAM */ + .align L1_CACHE_SHIFT + .globl tegra20_iram_end +tegra20_iram_end: + b . #endif diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index ada8821b48be..63fa91b5fafb 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -18,13 +18,118 @@ #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include <asm/cache.h> #include "fuse.h" #include "sleep.h" #include "flowctrl.h" +#define EMC_CFG 0xc +#define EMC_ADR_CFG 0x10 +#define EMC_TIMING_CONTROL 0x28 +#define EMC_REFRESH 0x70 +#define EMC_NOP 0xdc +#define EMC_SELF_REF 0xe0 +#define EMC_MRW 0xe8 +#define EMC_FBIO_CFG5 0x104 +#define EMC_AUTO_CAL_CONFIG 0x2a4 +#define EMC_AUTO_CAL_INTERVAL 0x2a8 +#define EMC_AUTO_CAL_STATUS 0x2ac +#define EMC_REQ_CTRL 0x2b0 +#define EMC_CFG_DIG_DLL 0x2bc +#define EMC_EMC_STATUS 0x2b4 +#define EMC_ZCAL_INTERVAL 0x2e0 +#define EMC_ZQ_CAL 0x2ec +#define EMC_XM2VTTGENPADCTRL 0x310 +#define EMC_XM2VTTGENPADCTRL2 0x314 + +#define PMC_CTRL 0x0 +#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */ + +#define PMC_PLLP_WB0_OVERRIDE 0xf8 +#define PMC_IO_DPD_REQ 0x1b8 +#define PMC_IO_DPD_STATUS 0x1bc + +#define CLK_RESET_CCLK_BURST 0x20 +#define CLK_RESET_CCLK_DIVIDER 0x24 +#define CLK_RESET_SCLK_BURST 0x28 +#define CLK_RESET_SCLK_DIVIDER 0x2c + +#define CLK_RESET_PLLC_BASE 0x80 +#define CLK_RESET_PLLC_MISC 0x8c +#define CLK_RESET_PLLM_BASE 0x90 +#define CLK_RESET_PLLM_MISC 0x9c +#define CLK_RESET_PLLP_BASE 0xa0 +#define CLK_RESET_PLLP_MISC 0xac +#define CLK_RESET_PLLA_BASE 0xb0 +#define CLK_RESET_PLLA_MISC 0xbc +#define CLK_RESET_PLLX_BASE 0xe0 +#define CLK_RESET_PLLX_MISC 0xe4 +#define CLK_RESET_PLLX_MISC3 0x518 +#define CLK_RESET_PLLX_MISC3_IDDQ 3 +#define CLK_RESET_PLLM_MISC_IDDQ 5 +#define CLK_RESET_PLLC_MISC_IDDQ 26 + +#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 + +#define MSELECT_CLKM (0x3 << 30) + +#define LOCK_DELAY 50 /* safety delay after lock is detected */ + #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ +.macro emc_device_mask, rd, base + ldr \rd, [\base, #EMC_ADR_CFG] + tst \rd, #0x1 + moveq \rd, #(0x1 << 8) @ just 1 device + movne \rd, #(0x3 << 8) @ 2 devices +.endm + +.macro emc_timing_update, rd, base + mov \rd, #1 + str \rd, [\base, #EMC_TIMING_CONTROL] +1001: + ldr \rd, [\base, #EMC_EMC_STATUS] + tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear + bne 1001b +.endm + +.macro pll_enable, rd, r_car_base, pll_base, pll_misc + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + orreq \rd, \rd, #(1 << 30) + streq \rd, [\r_car_base, #\pll_base] + /* Enable lock detector */ + .if \pll_misc + ldr \rd, [\r_car_base, #\pll_misc] + bic \rd, \rd, #(1 << 18) + str \rd, [\r_car_base, #\pll_misc] + ldr \rd, [\r_car_base, #\pll_misc] + ldr \rd, [\r_car_base, #\pll_misc] + orr \rd, \rd, #(1 << 18) + str \rd, [\r_car_base, #\pll_misc] + .endif +.endm + +.macro pll_locked, rd, r_car_base, pll_base +1: + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 27) + beq 1b +.endm + +.macro pll_iddq_exit, rd, car, iddq, iddq_bit + ldr \rd, [\car, #\iddq] + bic \rd, \rd, #(1<<\iddq_bit) + str \rd, [\car, #\iddq] +.endm + +.macro pll_iddq_entry, rd, car, iddq, iddq_bit + ldr \rd, [\car, #\iddq] + orr \rd, \rd, #(1<<\iddq_bit) + str \rd, [\car, #\iddq] +.endm + #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) /* * tegra30_hotplug_shutdown(void) @@ -99,6 +204,8 @@ flow_ctrl_setting_for_lp2: cmp r10, #TEGRA30 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 movne r3, #FLOW_CTRL_WAITEVENT + orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ + orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ flow_ctrl_done: cmp r10, #TEGRA30 str r3, [r2] @@ -127,6 +234,41 @@ ENDPROC(tegra30_cpu_shutdown) #ifdef CONFIG_PM_SLEEP /* + * tegra30_sleep_core_finish(unsigned long v2p) + * + * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to + * tegra30_tear_down_core in IRAM + */ +ENTRY(tegra30_sleep_core_finish) + /* Flush, disable the L1 data cache and exit SMP */ + bl tegra_disable_clean_inv_dcache + + /* + * Preload all the address literals that are needed for the + * CPU power-gating process, to avoid loading from SDRAM which + * are not supported once SDRAM is put into self-refresh. + * LP0 / LP1 use physical address, since the MMU needs to be + * disabled before putting SDRAM into self-refresh to avoid + * memory access due to page table walks. + */ + mov32 r4, TEGRA_PMC_BASE + mov32 r5, TEGRA_CLK_RESET_BASE + mov32 r6, TEGRA_FLOW_CTRL_BASE + mov32 r7, TEGRA_TMRUS_BASE + + mov32 r3, tegra_shut_off_mmu + add r3, r3, r0 + + mov32 r0, tegra30_tear_down_core + mov32 r1, tegra30_iram_start + sub r0, r0, r1 + mov32 r1, TEGRA_IRAM_CODE_AREA + add r0, r0, r1 + + mov pc, r3 +ENDPROC(tegra30_sleep_core_finish) + +/* * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) * * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. @@ -135,6 +277,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish) mov r7, lr /* Flush and disable the L1 data cache */ + mov r0, #TEGRA_FLUSH_CACHE_LOUIS bl tegra_disable_clean_inv_dcache /* Powergate this CPU. */ @@ -155,6 +298,351 @@ ENTRY(tegra30_tear_down_cpu) b tegra30_enter_sleep ENDPROC(tegra30_tear_down_cpu) +/* START OF ROUTINES COPIED TO IRAM */ + .align L1_CACHE_SHIFT + .globl tegra30_iram_start +tegra30_iram_start: + +/* + * tegra30_lp1_reset + * + * reset vector for LP1 restore; copied into IRAM during suspend. + * Brings the system back up to a safe staring point (SDRAM out of + * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX, + * system clock running on the same PLL that it suspended at), and + * jumps to tegra_resume to restore virtual addressing. + * The physical address of tegra_resume expected to be stored in + * PMC_SCRATCH41. + * + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. + */ +ENTRY(tegra30_lp1_reset) + /* + * The CPU and system bus are running at 32KHz and executing from + * IRAM when this code is executed; immediately switch to CLKM and + * enable PLLP, PLLM, PLLC, PLLA and PLLX. + */ + mov32 r0, TEGRA_CLK_RESET_BASE + + mov r1, #(1 << 28) + str r1, [r0, #CLK_RESET_SCLK_BURST] + str r1, [r0, #CLK_RESET_CCLK_BURST] + mov r1, #0 + str r1, [r0, #CLK_RESET_CCLK_DIVIDER] + str r1, [r0, #CLK_RESET_SCLK_DIVIDER] + + tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 + cmp r10, #TEGRA30 + beq _no_pll_iddq_exit + + pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ + pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ + pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ + + mov32 r7, TEGRA_TMRUS_BASE + ldr r1, [r7] + add r1, r1, #2 + wait_until r1, r7, r3 + + /* enable PLLM via PMC */ + mov32 r2, TEGRA_PMC_BASE + ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + orr r1, r1, #(1 << 12) + str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + + pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 + pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 + pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 + + b _pll_m_c_x_done + +_no_pll_iddq_exit: + /* enable PLLM via PMC */ + mov32 r2, TEGRA_PMC_BASE + ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + orr r1, r1, #(1 << 12) + str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + + pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC + pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC + pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC + +_pll_m_c_x_done: + pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC + pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC + + pll_locked r1, r0, CLK_RESET_PLLM_BASE + pll_locked r1, r0, CLK_RESET_PLLP_BASE + pll_locked r1, r0, CLK_RESET_PLLA_BASE + pll_locked r1, r0, CLK_RESET_PLLC_BASE + pll_locked r1, r0, CLK_RESET_PLLX_BASE + + mov32 r7, TEGRA_TMRUS_BASE + ldr r1, [r7] + add r1, r1, #LOCK_DELAY + wait_until r1, r7, r3 + + adr r5, tegra30_sdram_pad_save + + ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT + str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] + + ldr r4, [r5, #0x1C] @ restore SCLK_BURST + str r4, [r0, #CLK_RESET_SCLK_BURST] + + cmp r10, #TEGRA30 + movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX + movteq r4, #:upper16:((1 << 28) | (0x8)) + movwne r4, #:lower16:((1 << 28) | (0xe)) + movtne r4, #:upper16:((1 << 28) | (0xe)) + str r4, [r0, #CLK_RESET_CCLK_BURST] + + /* Restore pad power state to normal */ + ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS + mvn r1, r1 + bic r1, r1, #(1 << 31) + orr r1, r1, #(1 << 30) + str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF + + cmp r10, #TEGRA30 + movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base + movteq r0, #:upper16:TEGRA_EMC_BASE + movwne r0, #:lower16:TEGRA_EMC0_BASE + movtne r0, #:upper16:TEGRA_EMC0_BASE + +exit_self_refresh: + ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL + str r1, [r0, #EMC_XM2VTTGENPADCTRL] + ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2 + str r1, [r0, #EMC_XM2VTTGENPADCTRL2] + ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL + str r1, [r0, #EMC_AUTO_CAL_INTERVAL] + + /* Relock DLL */ + ldr r1, [r0, #EMC_CFG_DIG_DLL] + orr r1, r1, #(1 << 30) @ set DLL_RESET + str r1, [r0, #EMC_CFG_DIG_DLL] + + emc_timing_update r1, r0 + + cmp r10, #TEGRA114 + movweq r1, #:lower16:TEGRA_EMC1_BASE + movteq r1, #:upper16:TEGRA_EMC1_BASE + cmpeq r0, r1 + + ldr r1, [r0, #EMC_AUTO_CAL_CONFIG] + orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE + orreq r1, r1, #(1 << 27) @ set slave mode for channel 1 + str r1, [r0, #EMC_AUTO_CAL_CONFIG] + +emc_wait_auto_cal_onetime: + ldr r1, [r0, #EMC_AUTO_CAL_STATUS] + tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared + bne emc_wait_auto_cal_onetime + + ldr r1, [r0, #EMC_CFG] + bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD + str r1, [r0, #EMC_CFG] + + mov r1, #0 + str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh + mov r1, #1 + cmp r10, #TEGRA30 + streq r1, [r0, #EMC_NOP] + streq r1, [r0, #EMC_NOP] + streq r1, [r0, #EMC_REFRESH] + + emc_device_mask r1, r0 + +exit_selfrefresh_loop: + ldr r2, [r0, #EMC_EMC_STATUS] + ands r2, r2, r1 + bne exit_selfrefresh_loop + + lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1 + + mov32 r7, TEGRA_TMRUS_BASE + ldr r2, [r0, #EMC_FBIO_CFG5] + + and r2, r2, #3 @ check DRAM_TYPE + cmp r2, #2 + beq emc_lpddr2 + + /* Issue a ZQ_CAL for dev0 - DDR3 */ + mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1 + str r2, [r0, #EMC_ZQ_CAL] + ldr r2, [r7] + add r2, r2, #10 + wait_until r2, r7, r3 + + tst r1, #2 + beq zcal_done + + /* Issue a ZQ_CAL for dev1 - DDR3 */ + mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1 + str r2, [r0, #EMC_ZQ_CAL] + ldr r2, [r7] + add r2, r2, #10 + wait_until r2, r7, r3 + b zcal_done + +emc_lpddr2: + /* Issue a ZQ_CAL for dev0 - LPDDR2 */ + mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB + str r2, [r0, #EMC_MRW] + ldr r2, [r7] + add r2, r2, #1 + wait_until r2, r7, r3 + + tst r1, #2 + beq zcal_done + + /* Issue a ZQ_CAL for dev0 - LPDDR2 */ + mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB + str r2, [r0, #EMC_MRW] + ldr r2, [r7] + add r2, r2, #1 + wait_until r2, r7, r3 + +zcal_done: + mov r1, #0 @ unstall all transactions + str r1, [r0, #EMC_REQ_CTRL] + ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL + str r1, [r0, #EMC_ZCAL_INTERVAL] + ldr r1, [r5, #0x0] @ restore EMC_CFG + str r1, [r0, #EMC_CFG] + + /* Tegra114 had dual EMC channel, now config the other one */ + cmp r10, #TEGRA114 + bne __no_dual_emc_chanl + mov32 r1, TEGRA_EMC1_BASE + cmp r0, r1 + movne r0, r1 + addne r5, r5, #0x20 + bne exit_self_refresh +__no_dual_emc_chanl: + + mov32 r0, TEGRA_PMC_BASE + ldr r0, [r0, #PMC_SCRATCH41] + mov pc, r0 @ jump to tegra_resume +ENDPROC(tegra30_lp1_reset) + + .align L1_CACHE_SHIFT +tegra30_sdram_pad_address: + .word TEGRA_EMC_BASE + EMC_CFG @0x0 + .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 + .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 + .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc + .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c + +tegra114_sdram_pad_address: + .word TEGRA_EMC0_BASE + EMC_CFG @0x0 + .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4 + .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 + .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc + .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c + .word TEGRA_EMC1_BASE + EMC_CFG @0x20 + .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 + .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 + +tegra30_sdram_pad_size: + .word tegra114_sdram_pad_address - tegra30_sdram_pad_address + +tegra114_sdram_pad_size: + .word tegra30_sdram_pad_size - tegra114_sdram_pad_address + + .type tegra30_sdram_pad_save, %object +tegra30_sdram_pad_save: + .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4 + .long 0 + .endr + +/* + * tegra30_tear_down_core + * + * copied into and executed from IRAM + * puts memory in self-refresh for LP0 and LP1 + */ +tegra30_tear_down_core: + bl tegra30_sdram_self_refresh + bl tegra30_switch_cpu_to_clk32k + b tegra30_enter_sleep + +/* + * tegra30_switch_cpu_to_clk32k + * + * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK + * to the 32KHz clock. + * r4 = TEGRA_PMC_BASE + * r5 = TEGRA_CLK_RESET_BASE + * r6 = TEGRA_FLOW_CTRL_BASE + * r7 = TEGRA_TMRUS_BASE + * r10= SoC ID + */ +tegra30_switch_cpu_to_clk32k: + /* + * start by jumping to CLKM to safely disable PLLs, then jump to + * CLKS. + */ + mov r0, #(1 << 28) + str r0, [r5, #CLK_RESET_SCLK_BURST] + /* 2uS delay delay between changing SCLK and CCLK */ + ldr r1, [r7] + add r1, r1, #2 + wait_until r1, r7, r9 + str r0, [r5, #CLK_RESET_CCLK_BURST] + mov r0, #0 + str r0, [r5, #CLK_RESET_CCLK_DIVIDER] + str r0, [r5, #CLK_RESET_SCLK_DIVIDER] + + /* switch the clock source of mselect to be CLK_M */ + ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] + orr r0, r0, #MSELECT_CLKM + str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] + + /* 2uS delay delay between changing SCLK and disabling PLLs */ + ldr r1, [r7] + add r1, r1, #2 + wait_until r1, r7, r9 + + /* disable PLLM via PMC in LP1 */ + ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + bic r0, r0, #(1 << 12) + str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + + /* disable PLLP, PLLA, PLLC and PLLX */ + ldr r0, [r5, #CLK_RESET_PLLP_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLP_BASE] + ldr r0, [r5, #CLK_RESET_PLLA_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLA_BASE] + ldr r0, [r5, #CLK_RESET_PLLC_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLC_BASE] + ldr r0, [r5, #CLK_RESET_PLLX_BASE] + bic r0, r0, #(1 << 30) + str r0, [r5, #CLK_RESET_PLLX_BASE] + + cmp r10, #TEGRA30 + beq _no_pll_in_iddq + pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ +_no_pll_in_iddq: + + /* switch to CLKS */ + mov r0, #0 /* brust policy = 32KHz */ + str r0, [r5, #CLK_RESET_SCLK_BURST] + + mov pc, lr + /* * tegra30_enter_sleep * @@ -172,8 +660,12 @@ tegra30_enter_sleep: orr r0, r0, #FLOW_CTRL_CSR_ENABLE str r0, [r6, r2] + tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 + cmp r10, #TEGRA30 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT - orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ + orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ + orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ + cpu_to_halt_reg r2, r1 str r0, [r6, r2] dsb @@ -187,4 +679,126 @@ halted: /* !!!FIXME!!! Implement halt failure handler */ b halted +/* + * tegra30_sdram_self_refresh + * + * called with MMU off and caches disabled + * must be executed from IRAM + * r4 = TEGRA_PMC_BASE + * r5 = TEGRA_CLK_RESET_BASE + * r6 = TEGRA_FLOW_CTRL_BASE + * r7 = TEGRA_TMRUS_BASE + * r10= SoC ID + */ +tegra30_sdram_self_refresh: + + adr r8, tegra30_sdram_pad_save + tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 + cmp r10, #TEGRA30 + adreq r2, tegra30_sdram_pad_address + ldreq r3, tegra30_sdram_pad_size + adrne r2, tegra114_sdram_pad_address + ldrne r3, tegra114_sdram_pad_size + mov r9, #0 + +padsave: + ldr r0, [r2, r9] @ r0 is the addr in the pad_address + + ldr r1, [r0] + str r1, [r8, r9] @ save the content of the addr + + add r9, r9, #4 + cmp r3, r9 + bne padsave +padsave_done: + + dsb + + cmp r10, #TEGRA30 + ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr + ldrne r0, =TEGRA_EMC0_BASE + +enter_self_refresh: + cmp r10, #TEGRA30 + mov r1, #0 + str r1, [r0, #EMC_ZCAL_INTERVAL] + str r1, [r0, #EMC_AUTO_CAL_INTERVAL] + ldr r1, [r0, #EMC_CFG] + bic r1, r1, #(1 << 28) + bicne r1, r1, #(1 << 29) + str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF + + emc_timing_update r1, r0 + + ldr r1, [r7] + add r1, r1, #5 + wait_until r1, r7, r2 + +emc_wait_auto_cal: + ldr r1, [r0, #EMC_AUTO_CAL_STATUS] + tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared + bne emc_wait_auto_cal + + mov r1, #3 + str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests + +emcidle: + ldr r1, [r0, #EMC_EMC_STATUS] + tst r1, #4 + beq emcidle + + mov r1, #1 + str r1, [r0, #EMC_SELF_REF] + + emc_device_mask r1, r0 + +emcself: + ldr r2, [r0, #EMC_EMC_STATUS] + and r2, r2, r1 + cmp r2, r1 + bne emcself @ loop until DDR in self-refresh + + /* Put VTTGEN in the lowest power mode */ + ldr r1, [r0, #EMC_XM2VTTGENPADCTRL] + mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN + and r1, r1, r2 + str r1, [r0, #EMC_XM2VTTGENPADCTRL] + ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2] + cmp r10, #TEGRA30 + orreq r1, r1, #7 @ set E_NO_VTTGEN + orrne r1, r1, #0x3f + str r1, [r0, #EMC_XM2VTTGENPADCTRL2] + + emc_timing_update r1, r0 + + /* Tegra114 had dual EMC channel, now config the other one */ + cmp r10, #TEGRA114 + bne no_dual_emc_chanl + mov32 r1, TEGRA_EMC1_BASE + cmp r0, r1 + movne r0, r1 + bne enter_self_refresh +no_dual_emc_chanl: + + ldr r1, [r4, #PMC_CTRL] + tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 + bne pmc_io_dpd_skip + /* + * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK + * and COMP in the lowest power mode when LP1. + */ + mov32 r1, 0x8EC00000 + str r1, [r4, #PMC_IO_DPD_REQ] +pmc_io_dpd_skip: + + dsb + + mov pc, lr + + .ltorg +/* dummy symbol for end of IRAM */ + .align L1_CACHE_SHIFT + .global tegra30_iram_end +tegra30_iram_end: + b . #endif diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 9daaef26b0f6..8d06213fbc47 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache) isb /* Flush the D-cache */ - bl v7_flush_dcache_louis + cmp r0, #TEGRA_FLUSH_CACHE_ALL + blne v7_flush_dcache_louis + bleq v7_flush_dcache_all /* Trun off coherency */ exit_smp r4, r5 @@ -67,15 +69,40 @@ ENDPROC(tegra_disable_clean_inv_dcache) #ifdef CONFIG_PM_SLEEP /* + * tegra_init_l2_for_a15 + * + * set up the correct L2 cache data RAM latency + */ +ENTRY(tegra_init_l2_for_a15) + mrc p15, 0, r0, c0, c0, 5 + ubfx r0, r0, #8, #4 + tst r0, #1 @ only need for cluster 0 + bne _exit_init_l2_a15 + + mrc p15, 0x1, r0, c9, c0, 2 + and r0, r0, #7 + cmp r0, #2 + bicne r0, r0, #7 + orrne r0, r0, #2 + mcrne p15, 0x1, r0, c9, c0, 2 +_exit_init_l2_a15: + + mov pc, lr +ENDPROC(tegra_init_l2_for_a15) + +/* * tegra_sleep_cpu_finish(unsigned long v2p) * * enters suspend in LP2 by turning off the mmu and jumping to * tegra?_tear_down_cpu */ ENTRY(tegra_sleep_cpu_finish) + mov r4, r0 /* Flush and disable the L1 data cache */ + mov r0, #TEGRA_FLUSH_CACHE_ALL bl tegra_disable_clean_inv_dcache + mov r0, r4 mov32 r6, tegra_tear_down_cpu ldr r1, [r6] add r1, r1, r0 @@ -107,10 +134,10 @@ ENTRY(tegra_shut_off_mmu) #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ check_cpu_part_num 0xc09, r9, r10 - movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) - movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) - moveq r5, #0 - streq r5, [r4, #L2X0_CTRL] + movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) + movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) + moveq r3, #0 + streq r3, [r2, #L2X0_CTRL] #endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 98b7da698f2b..a4edbb3abd3d 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -41,7 +41,19 @@ #define CPU_NOT_RESETTABLE 0 #endif +/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */ +#define TEGRA_FLUSH_CACHE_LOUIS 0 +#define TEGRA_FLUSH_CACHE_ALL 1 + #ifdef __ASSEMBLY__ +/* waits until the microsecond counter (base) is > rn */ +.macro wait_until, rn, base, tmp + add \rn, \rn, #1 +1001: ldr \tmp, [\base] + cmp \tmp, \rn + bmi 1001b +.endm + /* returns the offset of the flow controller halt register for a cpu */ .macro cpu_to_halt_reg rd, rcpu cmp \rcpu, #0 @@ -144,7 +156,7 @@ void tegra_pen_lock(void); void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); -void tegra_disable_clean_inv_dcache(void); +void tegra_disable_clean_inv_dcache(u32 flag); #ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_shutdown(void); diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 0d1e4128d460..5b8605547a09 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -29,7 +29,6 @@ #include <linux/of_fdt.h> #include <linux/of_platform.h> #include <linux/pda_power.h> -#include <linux/platform_data/tegra_usb.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/sys_soc.h> @@ -46,40 +45,6 @@ #include "fuse.h" #include "iomap.h" -static struct tegra_ehci_platform_data tegra_ehci1_pdata = { - .operating_mode = TEGRA_USB_OTG, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { - .reset_gpio = -1, - .clk = "cdev2", -}; - -static struct tegra_ehci_platform_data tegra_ehci2_pdata = { - .phy_config = &tegra_ehci2_ulpi_phy_config, - .operating_mode = TEGRA_USB_HOST, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -static struct tegra_ehci_platform_data tegra_ehci3_pdata = { - .operating_mode = TEGRA_USB_HOST, - .power_down_on_bus_suspend = 1, - .vbus_gpio = -1, -}; - -static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0", - &tegra_ehci1_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1", - &tegra_ehci2_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2", - &tegra_ehci3_pdata), - {} -}; - static void __init tegra_dt_init(void) { struct soc_device_attribute *soc_dev_attr; @@ -112,30 +77,7 @@ static void __init tegra_dt_init(void) * devices */ out: - of_platform_populate(NULL, of_default_bus_match_table, - tegra20_auxdata_lookup, parent); -} - -static void __init trimslice_init(void) -{ -#ifdef CONFIG_TEGRA_PCI - int ret; - - ret = tegra_pcie_init(true, true); - if (ret) - pr_err("tegra_pci_init() failed: %d\n", ret); -#endif -} - -static void __init harmony_init(void) -{ -#ifdef CONFIG_TEGRA_PCI - int ret; - - ret = harmony_pcie_init(); - if (ret) - pr_err("harmony_pcie_init() failed: %d\n", ret); -#endif + of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); } static void __init paz00_init(void) @@ -148,8 +90,6 @@ static struct { char *machine; void (*init)(void); } board_init_funcs[] = { - { "compulab,trimslice", trimslice_init }, - { "nvidia,harmony", harmony_init }, { "compal,paz00", paz00_init }, }; diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index b19b07204aaf..99a28d628297 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -8,7 +8,7 @@ config ARCH_U8500 select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 help diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index bf9b6be5b180..fe1f3e26b88b 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -4,7 +4,6 @@ obj-y := cpu.o devices.o devices-common.o \ id.o usb.o timer.o pm.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index df5d27a532e9..4e7ab3a0dd60 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -42,7 +42,6 @@ #include <linux/platform_data/dma-ste-dma40.h> #include <asm/mach-types.h> -#include <asm/mach/arch.h> #include "setup.h" #include "devices.h" @@ -686,6 +685,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform") .init_time = ux500_timer_init, .init_machine = mop500_init_machine, .init_late = ux500_init_late, + .restart = ux500_restart, MACHINE_END MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") @@ -695,6 +695,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") .init_time = ux500_timer_init, .init_machine = mop500_init_machine, .init_late = ux500_init_late, + .restart = ux500_restart, MACHINE_END MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") @@ -705,6 +706,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") .init_time = ux500_timer_init, .init_machine = hrefv60_init_machine, .init_late = ux500_init_late, + .restart = ux500_restart, MACHINE_END MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") @@ -716,4 +718,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .init_time = ux500_timer_init, .init_machine = snowball_init_machine, .init_late = NULL, + .restart = ux500_restart, MACHINE_END diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 12eee8167525..bfaf95d22cbb 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -26,7 +26,6 @@ #include <asm/pmu.h> #include <asm/mach/map.h> -#include <asm/mach/arch.h> #include "setup.h" #include "devices.h" @@ -223,10 +222,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), - OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL), /* Requires clock name bindings. */ OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), @@ -325,6 +324,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") .init_machine = u8500_init_machine, .init_late = NULL, .dt_compat = stericsson_dt_platform_compat, + .restart = ux500_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index e6fb0239151b..5d7eebcabc63 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -31,6 +31,14 @@ #include "db8500-regs.h" #include "id.h" +void ux500_restart(enum reboot_mode mode, const char *cmd) +{ + local_irq_disable(); + local_fiq_disable(); + + prcmu_system_reset(0); +} + /* * FIXME: Should we set up the GPIO domain here? * diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c deleted file mode 100644 index a45dd09daed9..000000000000 --- a/arch/arm/mach-ux500/cpuidle.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2012 Linaro : Daniel Lezcano <daniel.lezcano@linaro.org> (IBM) - * - * Based on the work of Rickard Andersson <rickard.andersson@stericsson.com> - * and Jonas Aaberg <jonas.aberg@stericsson.com>. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/cpuidle.h> -#include <linux/spinlock.h> -#include <linux/atomic.h> -#include <linux/smp.h> -#include <linux/mfd/dbx500-prcmu.h> -#include <linux/platform_data/arm-ux500-pm.h> - -#include <asm/cpuidle.h> -#include <asm/proc-fns.h> - -#include "db8500-regs.h" -#include "id.h" - -static atomic_t master = ATOMIC_INIT(0); -static DEFINE_SPINLOCK(master_lock); - -static inline int ux500_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) -{ - int this_cpu = smp_processor_id(); - bool recouple = false; - - if (atomic_inc_return(&master) == num_online_cpus()) { - - /* With this lock, we prevent the other cpu to exit and enter - * this function again and become the master */ - if (!spin_trylock(&master_lock)) - goto wfi; - - /* decouple the gic from the A9 cores */ - if (prcmu_gic_decouple()) { - spin_unlock(&master_lock); - goto out; - } - - /* If an error occur, we will have to recouple the gic - * manually */ - recouple = true; - - /* At this state, as the gic is decoupled, if the other - * cpu is in WFI, we have the guarantee it won't be wake - * up, so we can safely go to retention */ - if (!prcmu_is_cpu_in_wfi(this_cpu ? 0 : 1)) - goto out; - - /* The prcmu will be in charge of watching the interrupts - * and wake up the cpus */ - if (prcmu_copy_gic_settings()) - goto out; - - /* Check in the meantime an interrupt did - * not occur on the gic ... */ - if (prcmu_gic_pending_irq()) - goto out; - - /* ... and the prcmu */ - if (prcmu_pending_irq()) - goto out; - - /* Go to the retention state, the prcmu will wait for the - * cpu to go WFI and this is what happens after exiting this - * 'master' critical section */ - if (prcmu_set_power_state(PRCMU_AP_IDLE, true, true)) - goto out; - - /* When we switch to retention, the prcmu is in charge - * of recoupling the gic automatically */ - recouple = false; - - spin_unlock(&master_lock); - } -wfi: - cpu_do_idle(); -out: - atomic_dec(&master); - - if (recouple) { - prcmu_gic_recouple(); - spin_unlock(&master_lock); - } - - return index; -} - -static struct cpuidle_driver ux500_idle_driver = { - .name = "ux500_idle", - .owner = THIS_MODULE, - .states = { - ARM_CPUIDLE_WFI_STATE, - { - .enter = ux500_enter_idle, - .exit_latency = 70, - .target_residency = 260, - .flags = CPUIDLE_FLAG_TIME_VALID | - CPUIDLE_FLAG_TIMER_STOP, - .name = "ApIdle", - .desc = "ARM Retention", - }, - }, - .safe_state_index = 0, - .state_count = 2, -}; - -int __init ux500_idle_init(void) -{ - if (!(cpu_is_u8500_family() || cpu_is_ux540_family())) - return -ENODEV; - - /* Configure wake up reasons */ - prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | - PRCMU_WAKEUP(ABB)); - - return cpuidle_register(&ux500_idle_driver, NULL); -} - -device_initcall(ux500_idle_init); diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 516a6f57d159..bc316062e0c2 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -49,6 +49,7 @@ struct stedma40_platform_data dma40_plat_data = { struct platform_device u8500_dma40_device = { .dev = { .platform_data = &dma40_plat_data, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .name = "dma40", .id = 0, diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S index 08da5589bcd8..9cdea049485d 100644 --- a/arch/arm/mach-ux500/headsmp.S +++ b/arch/arm/mach-ux500/headsmp.S @@ -11,8 +11,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __INIT - /* * U8500 specific entry point for secondary CPUs. */ diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index cad3ca86c540..656324aad18e 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -11,10 +11,13 @@ #ifndef __ASM_ARCH_SETUP_H #define __ASM_ARCH_SETUP_H +#include <asm/mach/arch.h> #include <asm/mach/time.h> #include <linux/init.h> #include <linux/mfd/abx500/ab8500.h> +void ux500_restart(enum reboot_mode mode, const char *cmd); + void __init ux500_map_io(void); extern void __init u8500_map_io(void); diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S deleted file mode 100644 index d0fbd7f1cb00..000000000000 --- a/arch/arm/mach-versatile/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-versatile/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x001F0000 - orr \rp, \rp, #0x00001000 - orr \rv, \rp, #0xf1000000 @ virtual base - orr \rp, \rp, #0x10000000 @ physical base - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index b8bbabec6310..365795447804 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -10,7 +10,7 @@ config ARCH_VEXPRESS select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_CLK select HAVE_PATA_PLATFORM select HAVE_SMP @@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB This is needed to provide CPU and cluster power management on RTSM implementing big.LITTLE. +config ARCH_VEXPRESS_TC2_PM + bool "Versatile Express TC2 power management" + depends on MCPM + select ARM_CCI + help + Support for CPU and cluster power management on Versatile Express + with a TC2 (A15x2 A7x3) big.LITTLE core tile. + endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 48ba89a8149f..36ea8247123a 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o +obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 16d57a8a9d5a..3a6384c6c435 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -136,14 +136,35 @@ static void dcscb_power_down(void) /* * Flush all cache levels for this cluster. * - * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need - * a preliminary flush here for those CPUs. At least, that's - * the theory -- without the extra flush, Linux explodes on - * RTSM (to be investigated). + * To do so we do: + * - Clear the SCTLR.C bit to prevent further cache allocations + * - Flush the whole cache + * - Clear the ACTLR "SMP" bit to disable local coherency + * + * Let's do it in the safest possible way i.e. with + * no memory access within the following sequence + * including to the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. */ - flush_cache_all(); - set_cr(get_cr() & ~CR_C); - flush_cache_all(); + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_all \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); /* * This is a harmless no-op. On platforms with a real @@ -152,9 +173,6 @@ static void dcscb_power_down(void) */ outer_flush_all(); - /* Disable local coherency by clearing the ACTLR "SMP" bit: */ - set_auxcr(get_auxcr() & ~(1 << 6)); - /* * Disable cluster-level coherency by masking * incoming snoops and DVM messages: @@ -167,18 +185,24 @@ static void dcscb_power_down(void) /* * Flush the local CPU cache. - * - * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need - * a preliminary flush here for those CPUs. At least, that's - * the theory -- without the extra flush, Linux explodes on - * RTSM (to be investigated). + * Let's do it in the safest possible way as above. */ - flush_cache_louis(); - set_cr(get_cr() & ~CR_C); - flush_cache_louis(); - - /* Disable local coherency by clearing the ACTLR "SMP" bit: */ - set_auxcr(get_auxcr() & ~(1 << 6)); + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_louis \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); } __mcpm_cpu_down(cpu, cluster); diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c new file mode 100644 index 000000000000..eefb029197ca --- /dev/null +++ b/arch/arm/mach-vexpress/spc.c @@ -0,0 +1,180 @@ +/* + * Versatile Express Serial Power Controller (SPC) support + * + * Copyright (C) 2013 ARM Ltd. + * + * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> + * Achin Gupta <achin.gupta@arm.com> + * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> + +#include <asm/cacheflush.h> + +#define SPCLOG "vexpress-spc: " + +/* SPC wake-up IRQs status and mask */ +#define WAKE_INT_MASK 0x24 +#define WAKE_INT_RAW 0x28 +#define WAKE_INT_STAT 0x2c +/* SPC power down registers */ +#define A15_PWRDN_EN 0x30 +#define A7_PWRDN_EN 0x34 +/* SPC per-CPU mailboxes */ +#define A15_BX_ADDR0 0x68 +#define A7_BX_ADDR0 0x78 + +/* wake-up interrupt masks */ +#define GBL_WAKEUP_INT_MSK (0x3 << 10) + +/* TC2 static dual-cluster configuration */ +#define MAX_CLUSTERS 2 + +struct ve_spc_drvdata { + void __iomem *baseaddr; + /* + * A15s cluster identifier + * It corresponds to A15 processors MPIDR[15:8] bitfield + */ + u32 a15_clusid; +}; + +static struct ve_spc_drvdata *info; + +static inline bool cluster_is_a15(u32 cluster) +{ + return cluster == info->a15_clusid; +} + +/** + * ve_spc_global_wakeup_irq() + * + * Function to set/clear global wakeup IRQs. Not protected by locking since + * it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @set: if true, global wake-up IRQs are set, if false they are cleared + */ +void ve_spc_global_wakeup_irq(bool set) +{ + u32 reg; + + reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); + + if (set) + reg |= GBL_WAKEUP_INT_MSK; + else + reg &= ~GBL_WAKEUP_INT_MSK; + + writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); +} + +/** + * ve_spc_cpu_wakeup_irq() + * + * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since + * it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @cpu: mpidr[7:0] bitfield describing cpu affinity level + * @set: if true, wake-up IRQs are set, if false they are cleared + */ +void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set) +{ + u32 mask, reg; + + if (cluster >= MAX_CLUSTERS) + return; + + mask = 1 << cpu; + + if (!cluster_is_a15(cluster)) + mask <<= 4; + + reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); + + if (set) + reg |= mask; + else + reg &= ~mask; + + writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); +} + +/** + * ve_spc_set_resume_addr() - set the jump address used for warm boot + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @cpu: mpidr[7:0] bitfield describing cpu affinity level + * @addr: physical resume address + */ +void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr) +{ + void __iomem *baseaddr; + + if (cluster >= MAX_CLUSTERS) + return; + + if (cluster_is_a15(cluster)) + baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2); + else + baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2); + + writel_relaxed(addr, baseaddr); +} + +/** + * ve_spc_powerdown() + * + * Function to enable/disable cluster powerdown. Not protected by locking + * since it might be used in code paths where normal cacheable locks are not + * working. Locking must be provided by the caller to ensure atomicity. + * + * @cluster: mpidr[15:8] bitfield describing cluster affinity level + * @enable: if true enables powerdown, if false disables it + */ +void ve_spc_powerdown(u32 cluster, bool enable) +{ + u32 pwdrn_reg; + + if (cluster >= MAX_CLUSTERS) + return; + + pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN; + writel_relaxed(enable, info->baseaddr + pwdrn_reg); +} + +int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid) +{ + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + pr_err(SPCLOG "unable to allocate mem\n"); + return -ENOMEM; + } + + info->baseaddr = baseaddr; + info->a15_clusid = a15_clusid; + + /* + * Multi-cluster systems may need this data when non-coherent, during + * cluster power-up/power-down. Make sure driver info reaches main + * memory. + */ + sync_cache_w(info); + sync_cache_w(&info); + + return 0; +} diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h new file mode 100644 index 000000000000..5f7e4a446a17 --- /dev/null +++ b/arch/arm/mach-vexpress/spc.h @@ -0,0 +1,24 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + */ + + +#ifndef __SPC_H_ +#define __SPC_H_ + +int __init ve_spc_init(void __iomem *base, u32 a15_clusid); +void ve_spc_global_wakeup_irq(bool set); +void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); +void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); +void ve_spc_powerdown(u32 cluster, bool enable); + +#endif diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c new file mode 100644 index 000000000000..7aeb5d60e484 --- /dev/null +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -0,0 +1,354 @@ +/* + * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support + * + * Created by: Nicolas Pitre, October 2012 + * Copyright: (C) 2012-2013 Linaro Limited + * + * Some portions of this file were originally written by Achin Gupta + * Copyright: (C) 2012 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of_address.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/irqchip/arm-gic.h> + +#include <asm/mcpm.h> +#include <asm/proc-fns.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <asm/cp15.h> + +#include <linux/arm-cci.h> + +#include "spc.h" + +/* SCC conf registers */ +#define A15_CONF 0x400 +#define A7_CONF 0x500 +#define SYS_INFO 0x700 +#define SPC_BASE 0xb00 + +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() after its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED; + +#define TC2_CLUSTERS 2 +#define TC2_MAX_CPUS_PER_CLUSTER 3 + +static unsigned int tc2_nr_cpus[TC2_CLUSTERS]; + +/* Keep per-cpu usage count to cope with unordered up/down requests */ +static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS]; + +#define tc2_cluster_unused(cluster) \ + (!tc2_pm_use_count[0][cluster] && \ + !tc2_pm_use_count[1][cluster] && \ + !tc2_pm_use_count[2][cluster]) + +static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster) +{ + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) + return -EINVAL; + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&tc2_pm_lock); + + if (tc2_cluster_unused(cluster)) + ve_spc_powerdown(cluster, false); + + tc2_pm_use_count[cpu][cluster]++; + if (tc2_pm_use_count[cpu][cluster] == 1) { + ve_spc_set_resume_addr(cluster, cpu, + virt_to_phys(mcpm_entry_point)); + ve_spc_cpu_wakeup_irq(cluster, cpu, true); + } else if (tc2_pm_use_count[cpu][cluster] != 2) { + /* + * The only possible values are: + * 0 = CPU down + * 1 = CPU (still) up + * 2 = CPU requested to be up before it had a chance + * to actually make itself down. + * Any other value is a bug. + */ + BUG(); + } + + arch_spin_unlock(&tc2_pm_lock); + local_irq_enable(); + + return 0; +} + +static void tc2_pm_down(u64 residency) +{ + unsigned int mpidr, cpu, cluster; + bool last_man = false, skip_wfi = false; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); + + __mcpm_cpu_going_down(cpu, cluster); + + arch_spin_lock(&tc2_pm_lock); + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); + tc2_pm_use_count[cpu][cluster]--; + if (tc2_pm_use_count[cpu][cluster] == 0) { + ve_spc_cpu_wakeup_irq(cluster, cpu, true); + if (tc2_cluster_unused(cluster)) { + ve_spc_powerdown(cluster, true); + ve_spc_global_wakeup_irq(true); + last_man = true; + } + } else if (tc2_pm_use_count[cpu][cluster] == 1) { + /* + * A power_up request went ahead of us. + * Even if we do not want to shut this CPU down, + * the caller expects a certain state as if the WFI + * was aborted. So let's continue with cache cleaning. + */ + skip_wfi = true; + } else + BUG(); + + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { + arch_spin_unlock(&tc2_pm_lock); + + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + /* + * On the Cortex-A15 we need to disable + * L2 prefetching before flushing the cache. + */ + asm volatile( + "mcr p15, 1, %0, c15, c0, 3 \n\t" + "isb \n\t" + "dsb " + : : "r" (0x400) ); + } + + /* + * We need to disable and flush the whole (L1 and L2) cache. + * Let's do it in the safest possible way i.e. with + * no memory access within the following sequence + * including the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_all \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); + + cci_disable_port_by_cpu(mpidr); + + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); + } else { + /* + * If last man then undo any setup done previously. + */ + if (last_man) { + ve_spc_powerdown(cluster, false); + ve_spc_global_wakeup_irq(false); + } + + arch_spin_unlock(&tc2_pm_lock); + + /* + * We need to disable and flush only the L1 cache. + * Let's do it in the safest possible way as above. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_louis \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); + } + + __mcpm_cpu_down(cpu, cluster); + + /* Now we are prepared for power-down, do it: */ + if (!skip_wfi) + wfi(); + + /* Not dead at this point? Let our caller cope. */ +} + +static void tc2_pm_power_down(void) +{ + tc2_pm_down(0); +} + +static void tc2_pm_suspend(u64 residency) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point)); + gic_cpu_if_down(); + tc2_pm_down(residency); +} + +static void tc2_pm_powered_up(void) +{ + unsigned int mpidr, cpu, cluster; + unsigned long flags; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); + + local_irq_save(flags); + arch_spin_lock(&tc2_pm_lock); + + if (tc2_cluster_unused(cluster)) { + ve_spc_powerdown(cluster, false); + ve_spc_global_wakeup_irq(false); + } + + if (!tc2_pm_use_count[cpu][cluster]) + tc2_pm_use_count[cpu][cluster] = 1; + + ve_spc_cpu_wakeup_irq(cluster, cpu, false); + ve_spc_set_resume_addr(cluster, cpu, 0); + + arch_spin_unlock(&tc2_pm_lock); + local_irq_restore(flags); +} + +static const struct mcpm_platform_ops tc2_pm_power_ops = { + .power_up = tc2_pm_power_up, + .power_down = tc2_pm_power_down, + .suspend = tc2_pm_suspend, + .powered_up = tc2_pm_powered_up, +}; + +static bool __init tc2_pm_usage_count_init(void) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) { + pr_err("%s: boot CPU is out of bound!\n", __func__); + return false; + } + tc2_pm_use_count[cpu][cluster] = 1; + return true; +} + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + */ +static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) +{ + asm volatile (" \n" +" cmp r0, #1 \n" +" bxne lr \n" +" b cci_enable_port_for_self "); +} + +static int __init tc2_pm_init(void) +{ + int ret; + void __iomem *scc; + u32 a15_cluster_id, a7_cluster_id, sys_info; + struct device_node *np; + + /* + * The power management-related features are hidden behind + * SCC registers. We need to extract runtime information like + * cluster ids and number of CPUs really available in clusters. + */ + np = of_find_compatible_node(NULL, NULL, + "arm,vexpress-scc,v2p-ca15_a7"); + scc = of_iomap(np, 0); + if (!scc) + return -ENODEV; + + a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; + a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; + if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS) + return -EINVAL; + + sys_info = readl_relaxed(scc + SYS_INFO); + tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf; + tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf; + + /* + * A subset of the SCC registers is also used to communicate + * with the SPC (power controller). We need to be able to + * drive it very early in the boot process to power up + * processors, so we initialize the SPC driver here. + */ + ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id); + if (ret) + return ret; + + if (!cci_probed()) + return -ENODEV; + + if (!tc2_pm_usage_count_init()) + return -EINVAL; + + ret = mcpm_platform_register(&tc2_pm_power_ops); + if (!ret) { + mcpm_sync_init(tc2_pm_power_up_setup); + pr_info("TC2 power management initialized\n"); + } + return ret; +} + +early_initcall(tc2_pm_init); diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index c1d61f281e68..04f8a4a6e755 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -6,7 +6,7 @@ config ARCH_ZYNQ select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select ICST select MIGHT_HAVE_CACHE_L2X0 select USE_OF diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c index c89672bd1de2..5052c70326e4 100644 --- a/arch/arm/mach-zynq/hotplug.c +++ b/arch/arm/mach-zynq/hotplug.c @@ -40,44 +40,6 @@ static inline void zynq_cpu_enter_lowpower(void) : "cc"); } -static inline void zynq_cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x40\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - dsb(); - wfi(); - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - /* * platform-specific code to shutdown a CPU * @@ -85,20 +47,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious) */ void zynq_platform_cpu_die(unsigned int cpu) { - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ zynq_cpu_enter_lowpower(); - zynq_platform_do_lowpower(cpu, &spurious); /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts */ - zynq_cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); + for (;;) + cpu_do_idle(); } diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 50d008d8f87f..1836d5a34606 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -14,32 +14,21 @@ * 02139, USA. */ -#include <linux/export.h> #include <linux/io.h> -#include <linux/fs.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> #include <linux/of_address.h> -#include <linux/uaccess.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/string.h> #include <linux/clk/zynq.h> #include "common.h" -#define SLCR_UNLOCK_MAGIC 0xDF0D -#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ - +/* register offsets */ +#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ +#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ +#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 #define SLCR_A9_CPU_RST 0x1 -#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ -#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ - void __iomem *zynq_slcr_base; /** @@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void) * Note that this seems to require raw i/o * functions or there's a lockup? */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); /* * Clear 0x0F000000 bits of reboot status register to workaround * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ - reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); - writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); + reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); + writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); } @@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void) */ void zynq_slcr_cpu_start(int cpu) { - /* enable CPUn */ - writel(SLCR_A9_CPU_CLKSTOP << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); - /* enable CLK for CPUn */ - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_RST << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) */ void zynq_slcr_cpu_stop(int cpu) { - /* stop CLK and reset CPUn */ - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -113,7 +102,7 @@ int __init zynq_slcr_init(void) } /* unlock the SLCR so that registers can be changed */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index db5c2cab8fda..cd2c88e7a8f7 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -809,15 +809,18 @@ config KUSER_HELPERS the CPU type fitted to the system. This permits binaries to be run on ARMv4 through to ARMv7 without modification. + See Documentation/arm/kernel_user_helpers.txt for details. + However, the fixed address nature of these helpers can be used by ROP (return orientated programming) authors when creating exploits. If all of the binaries and libraries which run on your platform are built specifically for your platform, and make no use of - these helpers, then you can turn this option off. However, - when such an binary or library is run, it will receive a SIGILL - signal, which will terminate the program. + these helpers, then you can turn this option off to hinder + such exploits. However, in that case, if a binary or library + relying on those helpers is run, it will receive a SIGILL signal, + which will terminate the program. Say N here only if you are absolutely certain that you do not need these helpers; otherwise, the safe option is to say Y. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index d70e0aba0c9d..447da6ffadd5 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -290,7 +290,7 @@ static void l2x0_disable(void) raw_spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); writel_relaxed(0, l2x0_base + L2X0_CTRL); - dsb(); + dsb(st); raw_spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -417,9 +417,9 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.disable = l2x0_disable; } - printk(KERN_INFO "%s cache controller enabled\n", type); - printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", - ways, cache_id, aux, l2x0_size); + pr_info("%s cache controller enabled\n", type); + pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n", + ways, cache_id, aux, l2x0_size >> 10); } #ifdef CONFIG_OF @@ -929,7 +929,9 @@ static const struct of_device_id l2x0_ids[] __initconst = { .data = (void *)&aurora_no_outer_data}, { .compatible = "marvell,aurora-outer-cache", .data = (void *)&aurora_with_outer_data}, - { .compatible = "bcm,bcm11351-a2-pl310-cache", + { .compatible = "brcm,bcm11351-a2-pl310-cache", + .data = (void *)&bcm_l2x0_data}, + { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */ .data = (void *)&bcm_l2x0_data}, {} }; diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 515b00064da8..b5c467a65c27 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -282,7 +282,7 @@ ENTRY(v7_coherent_user_range) add r12, r12, r2 cmp r12, r1 blo 1b - dsb + dsb ishst icache_line_size r2, r3 sub r3, r2, #1 bic r12, r0, r3 @@ -294,7 +294,7 @@ ENTRY(v7_coherent_user_range) mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB - dsb + dsb ishst isb mov pc, lr diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 4a0544492f10..84e6f772e204 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -162,10 +162,7 @@ static void flush_context(unsigned int cpu) } /* Queue a TLB invalidate and flush the I-cache if necessary. */ - if (!tlb_ops_need_broadcast()) - cpumask_set_cpu(cpu, &tlb_flush_pending); - else - cpumask_setall(&tlb_flush_pending); + cpumask_setall(&tlb_flush_pending); if (icache_is_vivt_asid_tagged()) __flush_icache_all(); @@ -245,8 +242,6 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { local_flush_bp_all(); local_flush_tlb_all(); - if (erratum_a15_798181()) - dummy_flush_tlb_a15_erratum(); } atomic64_set(&per_cpu(active_asids, cpu), asid); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 7f9b1798c6cf..f5e1a8471714 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -358,7 +358,7 @@ static int __init atomic_pool_init(void) if (!pages) goto no_pages; - if (IS_ENABLED(CONFIG_CMA)) + if (IS_ENABLED(CONFIG_DMA_CMA)) ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page, atomic_pool_init); else @@ -455,7 +455,6 @@ static void __dma_remap(struct page *page, size_t size, pgprot_t prot) unsigned end = start + size; apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); - dsb(); flush_tlb_kernel_range(start, end); } @@ -670,7 +669,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, addr = __alloc_simple_buffer(dev, size, gfp, &page); else if (!(gfp & __GFP_WAIT)) addr = __alloc_from_pool(size, &page); - else if (!IS_ENABLED(CONFIG_CMA)) + else if (!IS_ENABLED(CONFIG_DMA_CMA)) addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); else addr = __alloc_from_contiguous(dev, size, prot, &page, caller); @@ -759,7 +758,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, __dma_free_buffer(page, size); } else if (__free_from_pool(cpu_addr, size)) { return; - } else if (!IS_ENABLED(CONFIG_CMA)) { + } else if (!IS_ENABLED(CONFIG_DMA_CMA)) { __dma_free_remap(cpu_addr, size); __dma_free_buffer(page, size); } else { diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c index 3d1e4a205b0b..66781bf34077 100644 --- a/arch/arm/mm/hugetlbpage.c +++ b/arch/arm/mm/hugetlbpage.c @@ -36,22 +36,6 @@ * of type casting from pmd_t * to pte_t *. */ -pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd = NULL; - - pgd = pgd_offset(mm, addr); - if (pgd_present(*pgd)) { - pud = pud_offset(pgd, addr); - if (pud_present(*pud)) - pmd = pmd_offset(pud, addr); - } - - return (pte_t *)pmd; -} - struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address, int write) { @@ -68,33 +52,6 @@ int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep) return 0; } -pte_t *huge_pte_alloc(struct mm_struct *mm, - unsigned long addr, unsigned long sz) -{ - pgd_t *pgd; - pud_t *pud; - pte_t *pte = NULL; - - pgd = pgd_offset(mm, addr); - pud = pud_alloc(mm, pgd, addr); - if (pud) - pte = (pte_t *)pmd_alloc(mm, pud, addr); - - return pte; -} - -struct page * -follow_huge_pmd(struct mm_struct *mm, unsigned long address, - pmd_t *pmd, int write) -{ - struct page *page; - - page = pte_page(*(pte_t *)pmd); - if (page) - page += ((address & ~PMD_MASK) >> PAGE_SHIFT); - return page; -} - int pmd_huge(pmd_t pmd) { return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 15225d829d71..7b0cb3b524f1 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -17,6 +17,7 @@ #include <linux/nodemask.h> #include <linux/initrd.h> #include <linux/of_fdt.h> +#include <linux/of_reserved_mem.h> #include <linux/highmem.h> #include <linux/gfp.h> #include <linux/memblock.h> @@ -231,7 +232,7 @@ static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, } #endif -void __init setup_dma_zone(struct machine_desc *mdesc) +void __init setup_dma_zone(const struct machine_desc *mdesc) { #ifdef CONFIG_ZONE_DMA if (mdesc->dma_zone_size) { @@ -335,7 +336,8 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align) return phys; } -void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) +void __init arm_memblock_init(struct meminfo *mi, + const struct machine_desc *mdesc) { int i; @@ -377,6 +379,8 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc) if (mdesc->reserve) mdesc->reserve(); + early_init_dt_scan_reserved_mem(); + /* * reserve memory for DMA contigouos allocations, * must come from DMA area inside low memory diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 53cdbd39ec8e..b1d17eeb59b8 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -1186,7 +1186,7 @@ void __init arm_mm_memblock_reserve(void) * called function. This means you can't use any function or debugging * method which may touch any device, otherwise the kernel _will_ crash. */ -static void __init devicemaps_init(struct machine_desc *mdesc) +static void __init devicemaps_init(const struct machine_desc *mdesc) { struct map_desc map; unsigned long addr; @@ -1319,7 +1319,7 @@ static void __init map_lowmem(void) * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ -void __init paging_init(struct machine_desc *mdesc) +void __init paging_init(const struct machine_desc *mdesc) { void *zero_page; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 1fa50100ab6a..34d4ab217bab 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -299,7 +299,7 @@ void __init sanity_check_meminfo(void) * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ -void __init paging_init(struct machine_desc *mdesc) +void __init paging_init(const struct machine_desc *mdesc) { early_trap_init((void *)CONFIG_VECTORS_BASE); mpu_setup(); diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index d5146b98c8d1..db79b62c92fb 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -514,6 +514,32 @@ ENTRY(cpu_feroceon_set_pte_ext) #endif mov pc, lr +/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */ +.globl cpu_feroceon_suspend_size +.equ cpu_feroceon_suspend_size, 4 * 3 +#ifdef CONFIG_ARM_CPU_SUSPEND +ENTRY(cpu_feroceon_do_suspend) + stmfd sp!, {r4 - r6, lr} + mrc p15, 0, r4, c13, c0, 0 @ PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c1, c0, 0 @ Control register + stmia r0, {r4 - r6} + ldmfd sp!, {r4 - r6, pc} +ENDPROC(cpu_feroceon_do_suspend) + +ENTRY(cpu_feroceon_do_resume) + mov ip, #0 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs + mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches + ldmia r0, {r4 - r6} + mcr p15, 0, r4, c13, c0, 0 @ PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r1, c2, c0, 0 @ TTB address + mov r0, r6 @ control register + b cpu_resume_mmu +ENDPROC(cpu_feroceon_do_resume) +#endif + .type __feroceon_setup, #function __feroceon_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 73398bcf9bd8..c63d9bdee51e 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -83,7 +83,7 @@ ENTRY(cpu_v7_dcache_clean_area) add r0, r0, r2 subs r1, r1, r2 bhi 2b - dsb + dsb ishst mov pc, lr ENDPROC(cpu_v7_dcache_clean_area) @@ -330,7 +330,19 @@ __v7_setup: 1: #endif -3: mov r10, #0 + /* Cortex-A15 Errata */ +3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number + teq r0, r10 + bne 4f + +#ifdef CONFIG_ARM_ERRATA_773022 + cmp r6, #0x4 @ only present up to r0p4 + mrcle p15, 0, r10, c1, c0, 1 @ read aux control register + orrle r10, r10, #1 << 1 @ disable loop buffer + mcrle p15, 0, r10, c1, c0, 1 @ write aux control register +#endif + +4: mov r10, #0 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate dsb #ifdef CONFIG_MMU diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index ea94765acf9a..355308767bae 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -35,7 +35,7 @@ ENTRY(v7wbi_flush_user_tlb_range) vma_vm_mm r3, r2 @ get vma->vm_mm mmid r3, r3 @ get vm_mm->context.id - dsb + dsb ish mov r0, r0, lsr #PAGE_SHIFT @ align address mov r1, r1, lsr #PAGE_SHIFT asid r3, r3 @ mask ASID @@ -56,7 +56,7 @@ ENTRY(v7wbi_flush_user_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - dsb + dsb ish mov pc, lr ENDPROC(v7wbi_flush_user_tlb_range) @@ -69,7 +69,7 @@ ENDPROC(v7wbi_flush_user_tlb_range) * - end - end address (exclusive, may not be aligned) */ ENTRY(v7wbi_flush_kern_tlb_range) - dsb + dsb ish mov r0, r0, lsr #PAGE_SHIFT @ align address mov r1, r1, lsr #PAGE_SHIFT mov r0, r0, lsl #PAGE_SHIFT @@ -84,7 +84,7 @@ ENTRY(v7wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b - dsb + dsb ish isb mov pc, lr ENDPROC(v7wbi_flush_kern_tlb_range) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index f82bae2171eb..436ea97074cd 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -106,7 +106,7 @@ config OMAP_32K_TIMER This timer saves power compared to the OMAP_MPU_TIMER, and has support for no tick during idle. The 32KHz timer provides less intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is - currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5. + currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX. On OMAP2PLUS this value is only used for CONFIG_HZ and CLOCK_TICK_RATE compile time calculation. diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 4d463ca6821f..037660633fa4 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -2083,6 +2083,7 @@ static int omap_system_dma_probe(struct platform_device *pdev) dma_irq = platform_get_irq_byname(pdev, irq_name); if (dma_irq < 0) { dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); + ret = dma_irq; goto exit_dma_lch_fail; } ret = setup_irq(dma_irq, &omap24xx_dma_irq); diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 8db0b981ca64..c492e1b3dfdb 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -47,7 +47,7 @@ static int __init orion_add_irq_domain(struct device_node *np, do { base = of_iomap(np, i); if (base) { - orion_irq_init(i * 32, base); + orion_irq_init(i * 32, base + 0x04); i++; } } while (base); diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c index 8e11e96eab5e..c83f27b6bdda 100644 --- a/arch/arm/plat-pxa/ssp.c +++ b/arch/arm/plat-pxa/ssp.c @@ -30,6 +30,8 @@ #include <linux/platform_device.h> #include <linux/spi/pxa2xx_spi.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> #include <asm/irq.h> #include <mach/hardware.h> @@ -60,6 +62,30 @@ struct ssp_device *pxa_ssp_request(int port, const char *label) } EXPORT_SYMBOL(pxa_ssp_request); +struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node, + const char *label) +{ + struct ssp_device *ssp = NULL; + + mutex_lock(&ssp_lock); + + list_for_each_entry(ssp, &ssp_list, node) { + if (ssp->of_node == of_node && ssp->use_count == 0) { + ssp->use_count++; + ssp->label = label; + break; + } + } + + mutex_unlock(&ssp_lock); + + if (&ssp->node == &ssp_list) + return NULL; + + return ssp; +} +EXPORT_SYMBOL(pxa_ssp_request_of); + void pxa_ssp_free(struct ssp_device *ssp) { mutex_lock(&ssp_lock); @@ -72,96 +98,126 @@ void pxa_ssp_free(struct ssp_device *ssp) } EXPORT_SYMBOL(pxa_ssp_free); +#ifdef CONFIG_OF +static const struct of_device_id pxa_ssp_of_ids[] = { + { .compatible = "mrvl,pxa25x-ssp", .data = (void *) PXA25x_SSP }, + { .compatible = "mvrl,pxa25x-nssp", .data = (void *) PXA25x_NSSP }, + { .compatible = "mrvl,pxa27x-ssp", .data = (void *) PXA27x_SSP }, + { .compatible = "mrvl,pxa3xx-ssp", .data = (void *) PXA3xx_SSP }, + { .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP }, + { .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP }, + { .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP }, + { .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP }, + { }, +}; +MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids); +#endif + static int pxa_ssp_probe(struct platform_device *pdev) { - const struct platform_device_id *id = platform_get_device_id(pdev); struct resource *res; struct ssp_device *ssp; - int ret = 0; + struct device *dev = &pdev->dev; - ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL); - if (ssp == NULL) { - dev_err(&pdev->dev, "failed to allocate memory"); + ssp = devm_kzalloc(dev, sizeof(struct ssp_device), GFP_KERNEL); + if (ssp == NULL) return -ENOMEM; - } - ssp->pdev = pdev; - ssp->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(ssp->clk)) { - ret = PTR_ERR(ssp->clk); - goto err_free; - } + ssp->pdev = pdev; - res = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no SSP RX DRCMR defined\n"); - ret = -ENODEV; - goto err_free_clk; - } - ssp->drcmr_rx = res->start; + ssp->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ssp->clk)) + return PTR_ERR(ssp->clk); + + if (dev->of_node) { + struct of_phandle_args dma_spec; + struct device_node *np = dev->of_node; + + /* + * FIXME: we should allocate the DMA channel from this + * context and pass the channel down to the ssp users. + * For now, we lookup the rx and tx indices manually + */ + + /* rx */ + of_parse_phandle_with_args(np, "dmas", "#dma-cells", + 0, &dma_spec); + ssp->drcmr_rx = dma_spec.args[0]; + of_node_put(dma_spec.np); + + /* tx */ + of_parse_phandle_with_args(np, "dmas", "#dma-cells", + 1, &dma_spec); + ssp->drcmr_tx = dma_spec.args[0]; + of_node_put(dma_spec.np); + } else { + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (res == NULL) { + dev_err(dev, "no SSP RX DRCMR defined\n"); + return -ENODEV; + } + ssp->drcmr_rx = res->start; - res = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (res == NULL) { - dev_err(&pdev->dev, "no SSP TX DRCMR defined\n"); - ret = -ENODEV; - goto err_free_clk; + res = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (res == NULL) { + dev_err(dev, "no SSP TX DRCMR defined\n"); + return -ENODEV; + } + ssp->drcmr_tx = res->start; } - ssp->drcmr_tx = res->start; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - ret = -ENODEV; - goto err_free_clk; + dev_err(dev, "no memory resource defined\n"); + return -ENODEV; } - res = request_mem_region(res->start, resource_size(res), - pdev->name); + res = devm_request_mem_region(dev, res->start, resource_size(res), + pdev->name); if (res == NULL) { - dev_err(&pdev->dev, "failed to request memory resource\n"); - ret = -EBUSY; - goto err_free_clk; + dev_err(dev, "failed to request memory resource\n"); + return -EBUSY; } ssp->phys_base = res->start; - ssp->mmio_base = ioremap(res->start, resource_size(res)); + ssp->mmio_base = devm_ioremap(dev, res->start, resource_size(res)); if (ssp->mmio_base == NULL) { - dev_err(&pdev->dev, "failed to ioremap() registers\n"); - ret = -ENODEV; - goto err_free_mem; + dev_err(dev, "failed to ioremap() registers\n"); + return -ENODEV; } ssp->irq = platform_get_irq(pdev, 0); if (ssp->irq < 0) { - dev_err(&pdev->dev, "no IRQ resource defined\n"); - ret = -ENODEV; - goto err_free_io; + dev_err(dev, "no IRQ resource defined\n"); + return -ENODEV; + } + + if (dev->of_node) { + const struct of_device_id *id = + of_match_device(of_match_ptr(pxa_ssp_of_ids), dev); + ssp->type = (int) id->data; + } else { + const struct platform_device_id *id = + platform_get_device_id(pdev); + ssp->type = (int) id->driver_data; + + /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id + * starts from 0, do a translation here + */ + ssp->port_id = pdev->id + 1; } - /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id - * starts from 0, do a translation here - */ - ssp->port_id = pdev->id + 1; ssp->use_count = 0; - ssp->type = (int)id->driver_data; + ssp->of_node = dev->of_node; mutex_lock(&ssp_lock); list_add(&ssp->node, &ssp_list); mutex_unlock(&ssp_lock); platform_set_drvdata(pdev, ssp); - return 0; -err_free_io: - iounmap(ssp->mmio_base); -err_free_mem: - release_mem_region(res->start, resource_size(res)); -err_free_clk: - clk_put(ssp->clk); -err_free: - kfree(ssp); - return ret; + return 0; } static int pxa_ssp_remove(struct platform_device *pdev) @@ -201,8 +257,9 @@ static struct platform_driver pxa_ssp_driver = { .probe = pxa_ssp_probe, .remove = pxa_ssp_remove, .driver = { - .owner = THIS_MODULE, - .name = "pxa2xx-ssp", + .owner = THIS_MODULE, + .name = "pxa2xx-ssp", + .of_match_table = of_match_ptr(pxa_ssp_of_ids), }, .id_table = ssp_id_table, }; diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a5b5ff6e68d2..7dfba937d8fc 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -25,7 +25,6 @@ config PLAT_S5P select S5P_GPIO_DRVSTR select SAMSUNG_CLKSRC if !COMMON_CLK select SAMSUNG_GPIOLIB_4BIT - select SAMSUNG_IRQ_VIC_TIMER help Base platform code for Samsung's S5P series SoC. @@ -79,14 +78,6 @@ config SAMSUNG_ATAGS if SAMSUNG_ATAGS -# timer options - -config SAMSUNG_HRT - bool - select SAMSUNG_DEV_PWM - help - Use the High Resolution timer support - # clock options config SAMSUNG_CLOCK @@ -106,11 +97,6 @@ config S5P_CLOCK # options for IRQ support -config SAMSUNG_IRQ_VIC_TIMER - bool - help - Internal configuration to build the VIC timer interrupt code. - config S5P_IRQ def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 199bbe304d02..498c7c23e9f4 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -12,15 +12,12 @@ obj- := # Objects we always build independent of SoC choice obj-y += init.o cpu.o -obj-$(CONFIG_SAMSUNG_HRT) += samsung-time.o obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o -obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o -obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o obj-$(CONFIG_S5P_IRQ) += s5p-irq.o obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c index 5f197dcaf10c..d51f9565567c 100644 --- a/arch/arm/plat-samsung/dev-backlight.c +++ b/arch/arm/plat-samsung/dev-backlight.c @@ -20,13 +20,18 @@ #include <plat/gpio-cfg.h> #include <plat/backlight.h> +struct samsung_bl_drvdata { + struct platform_pwm_backlight_data plat_data; + struct samsung_bl_gpio_info *gpio_info; +}; + static int samsung_bl_init(struct device *dev) { int ret = 0; - struct platform_device *timer_dev = - container_of(dev->parent, struct platform_device, dev); - struct samsung_bl_gpio_info *bl_gpio_info = - timer_dev->dev.platform_data; + struct platform_pwm_backlight_data *pdata = dev->platform_data; + struct samsung_bl_drvdata *drvdata = container_of(pdata, + struct samsung_bl_drvdata, plat_data); + struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info; ret = gpio_request(bl_gpio_info->no, "Backlight"); if (ret) { @@ -42,10 +47,10 @@ static int samsung_bl_init(struct device *dev) static void samsung_bl_exit(struct device *dev) { - struct platform_device *timer_dev = - container_of(dev->parent, struct platform_device, dev); - struct samsung_bl_gpio_info *bl_gpio_info = - timer_dev->dev.platform_data; + struct platform_pwm_backlight_data *pdata = dev->platform_data; + struct samsung_bl_drvdata *drvdata = container_of(pdata, + struct samsung_bl_drvdata, plat_data); + struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info; s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT); gpio_free(bl_gpio_info->no); @@ -60,12 +65,14 @@ static void samsung_bl_exit(struct device *dev) * for their specific boards */ -static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = { - .max_brightness = 255, - .dft_brightness = 255, - .pwm_period_ns = 78770, - .init = samsung_bl_init, - .exit = samsung_bl_exit, +static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = { + .plat_data = { + .max_brightness = 255, + .dft_brightness = 255, + .pwm_period_ns = 78770, + .init = samsung_bl_init, + .exit = samsung_bl_exit, + }, }; static struct platform_device samsung_dfl_bl_device __initdata = { @@ -82,6 +89,7 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, { int ret = 0; struct platform_device *samsung_bl_device; + struct samsung_bl_drvdata *samsung_bl_drvdata; struct platform_pwm_backlight_data *samsung_bl_data; samsung_bl_device = kmemdup(&samsung_dfl_bl_device, @@ -91,17 +99,19 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, return; } - samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data, - sizeof(struct platform_pwm_backlight_data), samsung_bl_device); - if (!samsung_bl_data) { + samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data, + sizeof(samsung_dfl_bl_data), GFP_KERNEL); + if (!samsung_bl_drvdata) { printk(KERN_ERR "%s: no memory for platform dev\n", __func__); goto err_data; } + samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data; + samsung_bl_drvdata->gpio_info = gpio_info; + samsung_bl_data = &samsung_bl_drvdata->plat_data; /* Copy board specific data provided by user */ samsung_bl_data->pwm_id = bl_data->pwm_id; - samsung_bl_device->dev.parent = - &s3c_device_timer[samsung_bl_data->pwm_id].dev; + samsung_bl_device->dev.parent = &samsung_device_pwm.dev; if (bl_data->max_brightness) samsung_bl_data->max_brightness = bl_data->max_brightness; @@ -122,17 +132,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, if (bl_data->check_fb) samsung_bl_data->check_fb = bl_data->check_fb; - /* Keep the GPIO info for future use */ - s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info; - - /* Register the specific PWM timer dev for Backlight control */ - ret = platform_device_register( - &s3c_device_timer[samsung_bl_data->pwm_id]); - if (ret) { - printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret); - goto err_plat_reg1; - } - /* Register the Backlight dev */ ret = platform_device_register(samsung_bl_device); if (ret) { @@ -143,8 +142,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, return; err_plat_reg2: - platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]); -err_plat_reg1: kfree(samsung_bl_data); err_data: kfree(samsung_bl_device); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 0f9c3f431a5f..8ce0ac007eb9 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -58,6 +58,7 @@ #include <plat/keypad.h> #include <linux/platform_data/mmc-s3cmci.h> #include <linux/platform_data/mtd-nand-s3c2410.h> +#include <plat/pwm-core.h> #include <plat/sdhci.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> @@ -1097,36 +1098,21 @@ arch_initcall(s5p_pmu_init); /* PWM Timer */ #ifdef CONFIG_SAMSUNG_DEV_PWM +static struct resource samsung_pwm_resource[] = { + DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), +}; -#define TIMER_RESOURCE_SIZE (1) - -#define TIMER_RESOURCE(_tmr, _irq) \ - (struct resource [TIMER_RESOURCE_SIZE]) { \ - [0] = { \ - .start = _irq, \ - .end = _irq, \ - .flags = IORESOURCE_IRQ \ - } \ - } - -#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ - .name = "s3c24xx-pwm", \ - .id = _tmr_no, \ - .num_resources = TIMER_RESOURCE_SIZE, \ - .resource = TIMER_RESOURCE(_tmr_no, _irq), \ - -/* - * since we already have an static mapping for the timer, - * we do not bother setting any IO resource for the base. - */ - -struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, +struct platform_device samsung_device_pwm = { + .name = "samsung-pwm", + .id = -1, + .num_resources = ARRAY_SIZE(samsung_pwm_resource), + .resource = samsung_pwm_resource, }; + +void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) +{ + samsung_device_pwm.dev.platform_data = pd; +} #endif /* CONFIG_SAMSUNG_DEV_PWM */ /* RTC */ diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index df45d6edc98d..63239f409807 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -145,10 +145,6 @@ extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable); extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); -/* Init for pwm clock code */ - -extern void s3c_pwmclk_init(void); - /* Global watchdog clock used by arch_wtd_reset() callback */ extern struct clk *s3c2410_wdtclk; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 87d501ff3328..0dc4ac4909b0 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -134,6 +134,7 @@ extern struct platform_device exynos4_device_spdif; extern struct platform_device samsung_asoc_idma; extern struct platform_device samsung_device_keypad; +extern struct platform_device samsung_device_pwm; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h deleted file mode 100644 index 5b9c42fd32d7..000000000000 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ /dev/null @@ -1,13 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h - * - * Copyright (c) 2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Header file for Samsung SoC IRQ VIC timer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index df46b776976a..039001c0ef05 100644 --- a/arch/arm/plat-samsung/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -44,15 +44,6 @@ #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) -#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x)) - -#define IRQ_TIMER0 S5P_TIMER_IRQ(0) -#define IRQ_TIMER1 S5P_TIMER_IRQ(1) -#define IRQ_TIMER2 S5P_TIMER_IRQ(2) -#define IRQ_TIMER3 S5P_TIMER_IRQ(3) -#define IRQ_TIMER4 S5P_TIMER_IRQ(4) -#define IRQ_TIMER_COUNT (5) - #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ : ((x) - 16 + S5P_EINT_BASE2)) diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h deleted file mode 100644 index bf6a60eb6237..000000000000 --- a/arch/arm/plat-samsung/include/plat/pwm-clock.h +++ /dev/null @@ -1,81 +0,0 @@ -/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * SAMSUNG - pwm clock and timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_PWM_CLOCK_H -#define __ASM_PLAT_PWM_CLOCK_H __FILE__ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - if (soc_is_s3c24xx()) - return tcfg == S3C2410_TCFG1_MUX_TCLK; - else if (soc_is_s3c64xx() || soc_is_s5pc100()) - return tcfg >= S3C64XX_TCFG1_MUX_TCLK; - else if (soc_is_s5p6440() || soc_is_s5p6450()) - return 0; - else - return tcfg == S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - if (soc_is_s3c24xx()) - return 1 << (tcfg1 + 1); - else - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - if (soc_is_s3c24xx()) - return 0; - else - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - if (soc_is_s3c24xx()) - return ilog2(div) - 1; - else - return ilog2(div); -} -#endif /* __ASM_PLAT_PWM_CLOCK_H */ diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/plat-samsung/include/plat/pwm-core.h new file mode 100644 index 000000000000..5bff1facb672 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pwm-core.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Tomasz Figa <tomasz.figa@gmail.com> + * + * Samsung PWM controller platform data helpers. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PWM_CORE_H +#define __ASM_ARCH_PWM_CORE_H __FILE__ + +#include <clocksource/samsung_pwm.h> + +#ifdef CONFIG_SAMSUNG_DEV_PWM +extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd); +#else +static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { } +#endif + +#endif /* __ASM_ARCH_PWM_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h deleted file mode 100644 index d097d92f8cc7..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-timer.h +++ /dev/null @@ -1,124 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-timer.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Timer configuration -*/ - -#ifndef __ASM_ARCH_REGS_TIMER_H -#define __ASM_ARCH_REGS_TIMER_H - -#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) -#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) - -#define S3C2410_TCFG0 S3C_TIMERREG(0x00) -#define S3C2410_TCFG1 S3C_TIMERREG(0x04) -#define S3C2410_TCON S3C_TIMERREG(0x08) - -#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) - -#define S3C2410_TCFG_PRESCALER0_MASK (255<<0) -#define S3C2410_TCFG_PRESCALER1_MASK (255<<8) -#define S3C2410_TCFG_PRESCALER1_SHIFT (8) -#define S3C2410_TCFG_DEADZONE_MASK (255<<16) -#define S3C2410_TCFG_DEADZONE_SHIFT (16) - -#define S3C2410_TCFG1_MUX4_DIV2 (0<<16) -#define S3C2410_TCFG1_MUX4_DIV4 (1<<16) -#define S3C2410_TCFG1_MUX4_DIV8 (2<<16) -#define S3C2410_TCFG1_MUX4_DIV16 (3<<16) -#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) -#define S3C2410_TCFG1_MUX4_MASK (15<<16) -#define S3C2410_TCFG1_MUX4_SHIFT (16) - -#define S3C2410_TCFG1_MUX3_DIV2 (0<<12) -#define S3C2410_TCFG1_MUX3_DIV4 (1<<12) -#define S3C2410_TCFG1_MUX3_DIV8 (2<<12) -#define S3C2410_TCFG1_MUX3_DIV16 (3<<12) -#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) -#define S3C2410_TCFG1_MUX3_MASK (15<<12) - - -#define S3C2410_TCFG1_MUX2_DIV2 (0<<8) -#define S3C2410_TCFG1_MUX2_DIV4 (1<<8) -#define S3C2410_TCFG1_MUX2_DIV8 (2<<8) -#define S3C2410_TCFG1_MUX2_DIV16 (3<<8) -#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) -#define S3C2410_TCFG1_MUX2_MASK (15<<8) - - -#define S3C2410_TCFG1_MUX1_DIV2 (0<<4) -#define S3C2410_TCFG1_MUX1_DIV4 (1<<4) -#define S3C2410_TCFG1_MUX1_DIV8 (2<<4) -#define S3C2410_TCFG1_MUX1_DIV16 (3<<4) -#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) -#define S3C2410_TCFG1_MUX1_MASK (15<<4) - -#define S3C2410_TCFG1_MUX0_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX0_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX0_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX0_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) -#define S3C2410_TCFG1_MUX0_MASK (15<<0) - -#define S3C2410_TCFG1_MUX_DIV2 (0<<0) -#define S3C2410_TCFG1_MUX_DIV4 (1<<0) -#define S3C2410_TCFG1_MUX_DIV8 (2<<0) -#define S3C2410_TCFG1_MUX_DIV16 (3<<0) -#define S3C2410_TCFG1_MUX_TCLK (4<<0) -#define S3C2410_TCFG1_MUX_MASK (15<<0) - -#define S3C64XX_TCFG1_MUX_DIV1 (0<<0) -#define S3C64XX_TCFG1_MUX_DIV2 (1<<0) -#define S3C64XX_TCFG1_MUX_DIV4 (2<<0) -#define S3C64XX_TCFG1_MUX_DIV8 (3<<0) -#define S3C64XX_TCFG1_MUX_DIV16 (4<<0) -#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ -#define S3C64XX_TCFG1_MUX_MASK (15<<0) - -#define S3C2410_TCFG1_SHIFT(x) ((x) * 4) - -/* for each timer, we have an count buffer, an compare buffer and - * an observation buffer -*/ - -/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ - -#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) -#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) -#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) - -#define S3C2410_TCON_T4RELOAD (1<<22) -#define S3C2410_TCON_T4MANUALUPD (1<<21) -#define S3C2410_TCON_T4START (1<<20) - -#define S3C2410_TCON_T3RELOAD (1<<19) -#define S3C2410_TCON_T3INVERT (1<<18) -#define S3C2410_TCON_T3MANUALUPD (1<<17) -#define S3C2410_TCON_T3START (1<<16) - -#define S3C2410_TCON_T2RELOAD (1<<15) -#define S3C2410_TCON_T2INVERT (1<<14) -#define S3C2410_TCON_T2MANUALUPD (1<<13) -#define S3C2410_TCON_T2START (1<<12) - -#define S3C2410_TCON_T1RELOAD (1<<11) -#define S3C2410_TCON_T1INVERT (1<<10) -#define S3C2410_TCON_T1MANUALUPD (1<<9) -#define S3C2410_TCON_T1START (1<<8) - -#define S3C2410_TCON_T0DEADZONE (1<<4) -#define S3C2410_TCON_T0RELOAD (1<<3) -#define S3C2410_TCON_T0INVERT (1<<2) -#define S3C2410_TCON_T0MANUALUPD (1<<1) -#define S3C2410_TCON_T0START (1<<0) - -#endif /* __ASM_ARCH_REGS_TIMER_H */ - - - diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h index 4cc99bb1f176..209464adef97 100644 --- a/arch/arm/plat-samsung/include/plat/samsung-time.h +++ b/arch/arm/plat-samsung/include/plat/samsung-time.h @@ -22,29 +22,6 @@ enum samsung_timer_mode { SAMSUNG_PWM4, }; -struct samsung_timer_source { - unsigned int event_id; - unsigned int source_id; -}; - -/* Be able to sleep for atleast 4 seconds (usually more) */ -#define SAMSUNG_TIMER_MIN_RANGE 4 - -#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100) -#define TCNT_MAX 0xffff -#define TSCALER_DIV 25 -#define TDIV 50 -#define TSIZE 16 -#else -#define TCNT_MAX 0xffffffff -#define TSCALER_DIV 2 -#define TDIV 2 -#define TSIZE 32 -#endif - -#define NON_PERIODIC 0 -#define PERIODIC 1 - extern void __init samsung_set_timer_source(enum samsung_timer_mode event, enum samsung_timer_mode source); diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index ce1d0f785efd..bf650218b40e 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -260,44 +260,6 @@ static inline void s5pv210_default_sdhci3(void) { } #endif /* CONFIG_S5PV210_SETUP_SDHCI */ -/* EXYNOS4 SDHCI setup */ -#ifdef CONFIG_EXYNOS4_SETUP_SDHCI -static inline void exynos4_default_sdhci0(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci1(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci2(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; -#endif -} - -static inline void exynos4_default_sdhci3(void) -{ -#ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; -#endif -} - -#else -static inline void exynos4_default_sdhci0(void) { } -static inline void exynos4_default_sdhci1(void) { } -static inline void exynos4_default_sdhci2(void) { } -static inline void exynos4_default_sdhci3(void) { } - -#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ - static inline void s3c_sdhci_setname(int id, char *name) { switch (id) { diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 3e5c4619caa5..50a3ea0037db 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -55,12 +55,13 @@ void __init s3c_init_cpu(unsigned long idcode, printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); - if (cpu->map_io == NULL || cpu->init == NULL) { + if (cpu->init == NULL) { printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); panic("Unsupported Samsung CPU"); } - cpu->map_io(); + if (cpu->map_io) + cpu->map_io(); } /* s3c24xx_init_clocks diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c deleted file mode 100644 index 0fceb4273824..000000000000 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ /dev/null @@ -1,98 +0,0 @@ -/* arch/arm/plat-samsung/irq-vic-timer.c - * originally part of arch/arm/plat-s3c64xx/irq.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - Interrupt handling - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqchip/chained_irq.h> -#include <linux/io.h> - -#include <mach/map.h> -#include <mach/irqs.h> -#include <plat/cpu.h> -#include <plat/irq-vic-timer.h> -#include <plat/regs-timer.h> - -static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - chained_irq_enter(chip, desc); - generic_handle_irq((int)desc->irq_data.handler_data); - chained_irq_exit(chip, desc); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ -static void s3c_irq_timer_ack(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = (1 << 5) << (d->irq - gc->irq_base); - - irq_reg_writel(mask | gc->mask_cache, gc->reg_base); -} - -/** - * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @num: Number of timers to initialize - * @timer_irq: Base IRQ number to be used for the timers. - * - * Register the necessary IRQ chaining and support for the timer IRQs - * chained of the VIC. - */ -void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) -{ - unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, - IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; - struct irq_chip_generic *s3c_tgc; - struct irq_chip_type *ct; - unsigned int i; - -#ifdef CONFIG_ARCH_EXYNOS - if (soc_is_exynos5250()) { - pirq[0] = EXYNOS5_IRQ_TIMER0_VIC; - pirq[1] = EXYNOS5_IRQ_TIMER1_VIC; - pirq[2] = EXYNOS5_IRQ_TIMER2_VIC; - pirq[3] = EXYNOS5_IRQ_TIMER3_VIC; - pirq[4] = EXYNOS5_IRQ_TIMER4_VIC; - } else { - pirq[0] = EXYNOS4_IRQ_TIMER0_VIC; - pirq[1] = EXYNOS4_IRQ_TIMER1_VIC; - pirq[2] = EXYNOS4_IRQ_TIMER2_VIC; - pirq[3] = EXYNOS4_IRQ_TIMER3_VIC; - pirq[4] = EXYNOS4_IRQ_TIMER4_VIC; - } -#endif - s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, - S3C64XX_TINT_CSTAT, handle_level_irq); - - if (!s3c_tgc) { - pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n", - __func__, timer_irq); - return; - } - - ct = s3c_tgc->chip_types; - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->chip.irq_ack = s3c_irq_timer_ack; - irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, - IRQ_NOREQUEST | IRQ_NOPROBE, 0); - /* Clear the upper bits of the mask_cache*/ - s3c_tgc->mask_cache &= 0x1f; - - for (i = 0; i < num; i++, timer_irq++) { - irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); - irq_set_handler_data(pirq[i], (void *)timer_irq); - } -} diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c deleted file mode 100644 index a35ff3bcffe4..000000000000 --- a/arch/arm/plat-samsung/pwm-clock.c +++ /dev/null @@ -1,474 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/pwm-clock.c - * - * Copyright (c) 2007 Simtec Electronics - * Copyright (c) 2007, 2008 Ben Dooks - * Ben Dooks <ben-linux@fluff.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/log2.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/map.h> -#include <asm/irq.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -#include <plat/regs-timer.h> -#include <plat/pwm-clock.h> - -/* Each of the timers 0 through 5 go through the following - * clock tree, with the inputs depending on the timers. - * - * pclk ---- [ prescaler 0 ] -+---> timer 0 - * +---> timer 1 - * - * pclk ---- [ prescaler 1 ] -+---> timer 2 - * +---> timer 3 - * \---> timer 4 - * - * Which are fed into the timers as so: - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 0 - * tclk 0 ------------------------------/ - * - * prescaled 0 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 1 - * tclk 0 ------------------------------/ - * - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 2 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8,16 ] ---\ - * [mux] -> timer 3 - * tclk 1 ------------------------------/ - * - * prescaled 1 ---- [ div 2,4,8, 16 ] --\ - * [mux] -> timer 4 - * tclk 1 ------------------------------/ - * - * Since the mux and the divider are tied together in the - * same register space, it is impossible to set the parent - * and the rate at the same time. To avoid this, we add an - * intermediate 'prescaled-and-divided' clock to select - * as the parent for the timer input clock called tdiv. - * - * prescaled clk --> pwm-tdiv ---\ - * [ mux ] --> timer X - * tclk -------------------------/ -*/ - -static struct clk clk_timer_scaler[]; - -static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) -{ - unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK; - } - - return clk_get_rate(clk->parent) / (tcfg0 + 1); -} - -static unsigned long clk_pwm_scaler_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor = parent_rate / rate; - - if (divisor > 256) - divisor = 256; - else if (divisor < 2) - divisor = 2; - - return parent_rate / divisor; -} - -static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long round = clk_pwm_scaler_round_rate(clk, rate); - unsigned long tcfg0; - unsigned long divisor; - unsigned long flags; - - divisor = clk_get_rate(clk->parent) / round; - divisor--; - - local_irq_save(flags); - tcfg0 = __raw_readl(S3C2410_TCFG0); - - if (clk == &clk_timer_scaler[1]) { - tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; - } else { - tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK; - tcfg0 |= divisor; - } - - __raw_writel(tcfg0, S3C2410_TCFG0); - local_irq_restore(flags); - - return 0; -} - -static struct clk_ops clk_pwm_scaler_ops = { - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, -}; - -static struct clk clk_timer_scaler[] = { - [0] = { - .name = "pwm-scaler0", - .id = -1, - .ops = &clk_pwm_scaler_ops, - }, - [1] = { - .name = "pwm-scaler1", - .id = -1, - .ops = &clk_pwm_scaler_ops, - }, -}; - -static struct clk clk_timer_tclk[] = { - [0] = { - .name = "pwm-tclk0", - .id = -1, - }, - [1] = { - .name = "pwm-tclk1", - .id = -1, - }, -}; - -struct pwm_tdiv_clk { - struct clk clk; - unsigned int divisor; -}; - -static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) -{ - return container_of(clk, struct pwm_tdiv_clk, clk); -} - -static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - divisor = to_tdiv(clk)->divisor; - else - divisor = tcfg_to_divisor(tcfg1); - - return clk_get_rate(clk->parent) / divisor; -} - -static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate; - unsigned long divisor; - - parent_rate = clk_get_rate(clk->parent); - divisor = parent_rate / rate; - - if (divisor <= 1 && pwm_tdiv_has_div1()) - divisor = 1; - else if (divisor <= 2) - divisor = 2; - else if (divisor <= 4) - divisor = 4; - else if (divisor <= 8) - divisor = 8; - else - divisor = 16; - - return parent_rate / divisor; -} - -static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) -{ - return pwm_tdiv_div_bits(divclk->divisor); -} - -static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long bits = clk_pwm_tdiv_bits(divclk); - unsigned long flags; - unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id); - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - tcfg1 |= bits << shift; - __raw_writel(tcfg1, S3C2410_TCFG1); - - local_irq_restore(flags); -} - -static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) -{ - struct pwm_tdiv_clk *divclk = to_tdiv(clk); - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long divisor; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - rate = clk_round_rate(clk, rate); - divisor = parent_rate / rate; - - if (divisor > 16) - return -EINVAL; - - divclk->divisor = divisor; - - /* Update the current MUX settings if we are currently - * selected as the clock source for this clock. */ - - if (!pwm_cfg_src_is_tclk(tcfg1)) - clk_pwm_tdiv_update(divclk); - - return 0; -} - -static struct clk_ops clk_tdiv_ops = { - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, -}; - -static struct pwm_tdiv_clk clk_timer_tdiv[] = { - [0] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.0", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[0], - }, - }, - [1] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.1", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[0], - } - }, - [2] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.2", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, - [3] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.3", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, - [4] = { - .clk = { - .name = "pwm-tdiv", - .devname = "s3c24xx-pwm.4", - .ops = &clk_tdiv_ops, - .parent = &clk_timer_scaler[1], - }, - }, -}; - -static int __init clk_pwm_tdiv_register(unsigned int id) -{ - struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id]; - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - divclk->clk.id = id; - divclk->divisor = tcfg_to_divisor(tcfg1); - - return s3c24xx_register_clock(&divclk->clk); -} - -static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id) -{ - return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0]; -} - -static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id) -{ - return &clk_timer_tdiv[id].clk; -} - -static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned int id = clk->id; - unsigned long tcfg1; - unsigned long flags; - unsigned long bits; - unsigned long shift = S3C2410_TCFG1_SHIFT(id); - - unsigned long mux_tclk; - - if (soc_is_s3c24xx()) - mux_tclk = S3C2410_TCFG1_MUX_TCLK; - else if (soc_is_s5p6440() || soc_is_s5p6450()) - mux_tclk = 0; - else - mux_tclk = S3C64XX_TCFG1_MUX_TCLK; - - if (parent == s3c24xx_pwmclk_tclk(id)) - bits = mux_tclk << shift; - else if (parent == s3c24xx_pwmclk_tdiv(id)) - bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; - else - return -EINVAL; - - clk->parent = parent; - - local_irq_save(flags); - - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); - __raw_writel(tcfg1 | bits, S3C2410_TCFG1); - - local_irq_restore(flags); - - return 0; -} - -static struct clk_ops clk_tin_ops = { - .set_parent = clk_pwm_tin_set_parent, -}; - -static struct clk clk_tin[] = { - [0] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.0", - .id = 0, - .ops = &clk_tin_ops, - }, - [1] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.1", - .id = 1, - .ops = &clk_tin_ops, - }, - [2] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.2", - .id = 2, - .ops = &clk_tin_ops, - }, - [3] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.3", - .id = 3, - .ops = &clk_tin_ops, - }, - [4] = { - .name = "pwm-tin", - .devname = "s3c24xx-pwm.4", - .id = 4, - .ops = &clk_tin_ops, - }, -}; - -static __init int clk_pwm_tin_register(struct clk *pwm) -{ - unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); - unsigned int id = pwm->id; - - struct clk *parent; - int ret; - - ret = s3c24xx_register_clock(pwm); - if (ret < 0) - return ret; - - tcfg1 >>= S3C2410_TCFG1_SHIFT(id); - tcfg1 &= S3C2410_TCFG1_MUX_MASK; - - if (pwm_cfg_src_is_tclk(tcfg1)) - parent = s3c24xx_pwmclk_tclk(id); - else - parent = s3c24xx_pwmclk_tdiv(id); - - return clk_set_parent(pwm, parent); -} - -/** - * s3c_pwmclk_init() - initialise pwm clocks - * - * Initialise and register the clocks which provide the inputs for the - * pwm timer blocks. - * - * Note, this call is required by the time core, so must be called after - * the base clocks are added and before any of the initcalls are run. - */ -__init void s3c_pwmclk_init(void) -{ - struct clk *clk_timers; - unsigned int clk; - int ret; - - clk_timers = clk_get(NULL, "timers"); - if (IS_ERR(clk_timers)) { - printk(KERN_ERR "%s: no parent clock\n", __func__); - return; - } - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) - clk_timer_scaler[clk].parent = clk_timers; - - s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler)); - s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk)); - - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { - ret = clk_pwm_tdiv_register(clk); - - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); - return; - } - } - - for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) { - ret = clk_pwm_tin_register(&clk_tin[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm%d tin clock\n", clk); - return; - } - } -} diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c index 0cc40aea3f5a..98b10ba67dc7 100644 --- a/arch/arm/plat-samsung/s3c-dma-ops.c +++ b/arch/arm/plat-samsung/s3c-dma-ops.c @@ -82,7 +82,8 @@ static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param) static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) { struct cb_data *data; - int len = (param->cap == DMA_CYCLIC) ? param->period : param->len; + dma_addr_t pos = param->buf; + dma_addr_t end = param->buf + param->len; list_for_each_entry(data, &dma_list, node) if (data->ch == ch) @@ -94,7 +95,15 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) data->fp_param = param->fp_param; } - s3c2410_dma_enqueue(ch, (void *)data, param->buf, len); + if (param->cap != DMA_CYCLIC) { + s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len); + return 0; + } + + while (pos < end) { + s3c2410_dma_enqueue(ch, (void *)data, pos, param->period); + pos += param->period; + } return 0; } diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index ff1a76011b1e..ddfaca9c79d8 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -17,9 +17,7 @@ #include <mach/irqs.h> #include <mach/map.h> -#include <plat/regs-timer.h> #include <plat/cpu.h> -#include <plat/irq-vic-timer.h> void __init s5p_init_irq(u32 *vic, u32 num_vic) { @@ -30,6 +28,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - - s3c_init_vic_timer_irq(5, IRQ_TIMER0); } diff --git a/arch/arm/plat-samsung/samsung-time.c b/arch/arm/plat-samsung/samsung-time.c deleted file mode 100644 index 2957075ca836..000000000000 --- a/arch/arm/plat-samsung/samsung-time.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * samsung - Common hr-timer support (s3c and s5p) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/clockchips.h> -#include <linux/platform_device.h> -#include <linux/sched_clock.h> - -#include <asm/smp_twd.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/map.h> -#include <plat/devs.h> -#include <plat/regs-timer.h> -#include <plat/samsung-time.h> - -static struct clk *tin_event; -static struct clk *tin_source; -static struct clk *tdiv_event; -static struct clk *tdiv_source; -static struct clk *timerclk; -static struct samsung_timer_source timer_source; -static unsigned long clock_count_per_tick; -static void samsung_timer_resume(void); - -static void samsung_time_stop(enum samsung_timer_mode mode) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - switch (mode) { - case SAMSUNG_PWM0: - tcon &= ~S3C2410_TCON_T0START; - break; - - case SAMSUNG_PWM1: - tcon &= ~S3C2410_TCON_T1START; - break; - - case SAMSUNG_PWM2: - tcon &= ~S3C2410_TCON_T2START; - break; - - case SAMSUNG_PWM3: - tcon &= ~S3C2410_TCON_T3START; - break; - - case SAMSUNG_PWM4: - tcon &= ~S3C2410_TCON_T4START; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - __raw_writel(tcon, S3C2410_TCON); -} - -static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - tcnt--; - - switch (mode) { - case SAMSUNG_PWM0: - tcon &= ~(0x0f << 0); - tcon |= S3C2410_TCON_T0MANUALUPD; - break; - - case SAMSUNG_PWM1: - tcon &= ~(0x0f << 8); - tcon |= S3C2410_TCON_T1MANUALUPD; - break; - - case SAMSUNG_PWM2: - tcon &= ~(0x0f << 12); - tcon |= S3C2410_TCON_T2MANUALUPD; - break; - - case SAMSUNG_PWM3: - tcon &= ~(0x0f << 16); - tcon |= S3C2410_TCON_T3MANUALUPD; - break; - - case SAMSUNG_PWM4: - tcon &= ~(0x07 << 20); - tcon |= S3C2410_TCON_T4MANUALUPD; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - - __raw_writel(tcnt, S3C2410_TCNTB(mode)); - __raw_writel(tcnt, S3C2410_TCMPB(mode)); - __raw_writel(tcon, S3C2410_TCON); -} - -static void samsung_time_start(enum samsung_timer_mode mode, bool periodic) -{ - unsigned long tcon; - - tcon = __raw_readl(S3C2410_TCON); - - switch (mode) { - case SAMSUNG_PWM0: - tcon |= S3C2410_TCON_T0START; - tcon &= ~S3C2410_TCON_T0MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T0RELOAD; - else - tcon &= ~S3C2410_TCON_T0RELOAD; - break; - - case SAMSUNG_PWM1: - tcon |= S3C2410_TCON_T1START; - tcon &= ~S3C2410_TCON_T1MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T1RELOAD; - else - tcon &= ~S3C2410_TCON_T1RELOAD; - break; - - case SAMSUNG_PWM2: - tcon |= S3C2410_TCON_T2START; - tcon &= ~S3C2410_TCON_T2MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T2RELOAD; - else - tcon &= ~S3C2410_TCON_T2RELOAD; - break; - - case SAMSUNG_PWM3: - tcon |= S3C2410_TCON_T3START; - tcon &= ~S3C2410_TCON_T3MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T3RELOAD; - else - tcon &= ~S3C2410_TCON_T3RELOAD; - break; - - case SAMSUNG_PWM4: - tcon |= S3C2410_TCON_T4START; - tcon &= ~S3C2410_TCON_T4MANUALUPD; - - if (periodic) - tcon |= S3C2410_TCON_T4RELOAD; - else - tcon &= ~S3C2410_TCON_T4RELOAD; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", mode); - break; - } - __raw_writel(tcon, S3C2410_TCON); -} - -static int samsung_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - samsung_time_setup(timer_source.event_id, cycles); - samsung_time_start(timer_source.event_id, NON_PERIODIC); - - return 0; -} - -static void samsung_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - samsung_time_stop(timer_source.event_id); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - samsung_time_setup(timer_source.event_id, clock_count_per_tick); - samsung_time_start(timer_source.event_id, PERIODIC); - break; - - case CLOCK_EVT_MODE_ONESHOT: - break; - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - break; - - case CLOCK_EVT_MODE_RESUME: - samsung_timer_resume(); - break; - } -} - -static void samsung_timer_resume(void) -{ - /* event timer restart */ - samsung_time_setup(timer_source.event_id, clock_count_per_tick); - samsung_time_start(timer_source.event_id, PERIODIC); - - /* source timer restart */ - samsung_time_setup(timer_source.source_id, TCNT_MAX); - samsung_time_start(timer_source.source_id, PERIODIC); -} - -void __init samsung_set_timer_source(enum samsung_timer_mode event, - enum samsung_timer_mode source) -{ - s3c_device_timer[event].dev.bus = &platform_bus_type; - s3c_device_timer[source].dev.bus = &platform_bus_type; - - timer_source.event_id = event; - timer_source.source_id = source; -} - -static struct clock_event_device time_event_device = { - .name = "samsung_event_timer", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = samsung_set_next_event, - .set_mode = samsung_set_mode, -}; - -static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction samsung_clock_event_irq = { - .name = "samsung_time_irq", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = samsung_clock_event_isr, - .dev_id = &time_event_device, -}; - -static void __init samsung_clockevent_init(void) -{ - unsigned long pclk; - unsigned long clock_rate; - unsigned int irq_number; - struct clk *tscaler; - - pclk = clk_get_rate(timerclk); - - tscaler = clk_get_parent(tdiv_event); - - clk_set_rate(tscaler, pclk / TSCALER_DIV); - clk_set_rate(tdiv_event, pclk / TDIV); - clk_set_parent(tin_event, tdiv_event); - - clock_rate = clk_get_rate(tin_event); - clock_count_per_tick = clock_rate / HZ; - - time_event_device.cpumask = cpumask_of(0); - clockevents_config_and_register(&time_event_device, clock_rate, 1, -1); - - irq_number = timer_source.event_id + IRQ_TIMER0; - setup_irq(irq_number, &samsung_clock_event_irq); -} - -static void __iomem *samsung_timer_reg(void) -{ - unsigned long offset = 0; - - switch (timer_source.source_id) { - case SAMSUNG_PWM0: - case SAMSUNG_PWM1: - case SAMSUNG_PWM2: - case SAMSUNG_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case SAMSUNG_PWM4: - offset = 0x40; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - return NULL; - } - - return S3C_TIMERREG(offset); -} - -/* - * Override the global weak sched_clock symbol with this - * local implementation which uses the clocksource to get some - * better resolution when scheduling the kernel. We accept that - * this wraps around for now, since it is just a relative time - * stamp. (Inspired by U300 implementation.) - */ -static u32 notrace samsung_read_sched_clock(void) -{ - void __iomem *reg = samsung_timer_reg(); - - if (!reg) - return 0; - - return ~__raw_readl(reg); -} - -static void __init samsung_clocksource_init(void) -{ - unsigned long pclk; - unsigned long clock_rate; - - pclk = clk_get_rate(timerclk); - - clk_set_rate(tdiv_source, pclk / TDIV); - clk_set_parent(tin_source, tdiv_source); - - clock_rate = clk_get_rate(tin_source); - - samsung_time_setup(timer_source.source_id, TCNT_MAX); - samsung_time_start(timer_source.source_id, PERIODIC); - - setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate); - - if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer", - clock_rate, 250, TSIZE, clocksource_mmio_readl_down)) - panic("samsung_clocksource_timer: can't register clocksource\n"); -} - -static void __init samsung_timer_resources(void) -{ - - unsigned long event_id = timer_source.event_id; - unsigned long source_id = timer_source.source_id; - char devname[15]; - - timerclk = clk_get(NULL, "timers"); - if (IS_ERR(timerclk)) - panic("failed to get timers clock for timer"); - - clk_enable(timerclk); - - sprintf(devname, "s3c24xx-pwm.%lu", event_id); - s3c_device_timer[event_id].id = event_id; - s3c_device_timer[event_id].dev.init_name = devname; - - tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); - if (IS_ERR(tin_event)) - panic("failed to get pwm-tin clock for event timer"); - - tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv"); - if (IS_ERR(tdiv_event)) - panic("failed to get pwm-tdiv clock for event timer"); - - clk_enable(tin_event); - - sprintf(devname, "s3c24xx-pwm.%lu", source_id); - s3c_device_timer[source_id].id = source_id; - s3c_device_timer[source_id].dev.init_name = devname; - - tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); - if (IS_ERR(tin_source)) - panic("failed to get pwm-tin clock for source timer"); - - tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv"); - if (IS_ERR(tdiv_source)) - panic("failed to get pwm-tdiv clock for source timer"); - - clk_enable(tin_source); -} - -void __init samsung_timer_init(void) -{ - samsung_timer_resources(); - samsung_clockevent_init(); - samsung_clocksource_init(); -} diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 8d10dc8a1e17..3e5d3115a2a6 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -78,6 +78,11 @@ ENTRY(vfp_support_entry) DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 + ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions + and r3, r3, #MODE_MASK @ are supported in kernel mode + teq r3, #USR_MODE + bne vfp_kmode_exception @ Returns through lr + VFPFMRX r1, FPEXC @ Is the VFP enabled? DBGSTR1 "fpexc %08x", r1 tst r1, #FPEXC_EN diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 5dfbb0b8e7f4..52b8f40b1c73 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -20,6 +20,7 @@ #include <linux/init.h> #include <linux/uaccess.h> #include <linux/user.h> +#include <linux/export.h> #include <asm/cp15.h> #include <asm/cputype.h> @@ -648,6 +649,72 @@ static int vfp_hotplug(struct notifier_block *b, unsigned long action, return NOTIFY_OK; } +void vfp_kmode_exception(void) +{ + /* + * If we reach this point, a floating point exception has been raised + * while running in kernel mode. If the NEON/VFP unit was enabled at the + * time, it means a VFP instruction has been issued that requires + * software assistance to complete, something which is not currently + * supported in kernel mode. + * If the NEON/VFP unit was disabled, and the location pointed to below + * is properly preceded by a call to kernel_neon_begin(), something has + * caused the task to be scheduled out and back in again. In this case, + * rebuilding and running with CONFIG_DEBUG_ATOMIC_SLEEP enabled should + * be helpful in localizing the problem. + */ + if (fmrx(FPEXC) & FPEXC_EN) + pr_crit("BUG: unsupported FP instruction in kernel mode\n"); + else + pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n"); +} + +#ifdef CONFIG_KERNEL_MODE_NEON + +/* + * Kernel-side NEON support functions + */ +void kernel_neon_begin(void) +{ + struct thread_info *thread = current_thread_info(); + unsigned int cpu; + u32 fpexc; + + /* + * Kernel mode NEON is only allowed outside of interrupt context + * with preemption disabled. This will make sure that the kernel + * mode NEON register contents never need to be preserved. + */ + BUG_ON(in_interrupt()); + cpu = get_cpu(); + + fpexc = fmrx(FPEXC) | FPEXC_EN; + fmxr(FPEXC, fpexc); + + /* + * Save the userland NEON/VFP state. Under UP, + * the owner could be a task other than 'current' + */ + if (vfp_state_in_hw(cpu, thread)) + vfp_save_state(&thread->vfpstate, fpexc); +#ifndef CONFIG_SMP + else if (vfp_current_hw_state[cpu] != NULL) + vfp_save_state(vfp_current_hw_state[cpu], fpexc); +#endif + vfp_current_hw_state[cpu] = NULL; +} +EXPORT_SYMBOL(kernel_neon_begin); + +void kernel_neon_end(void) +{ + /* Disable the NEON/VFP unit. */ + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + put_cpu(); +} +EXPORT_SYMBOL(kernel_neon_end); + +#endif /* CONFIG_KERNEL_MODE_NEON */ + /* * VFP support code initialisation. */ @@ -731,4 +798,4 @@ static int __init vfp_init(void) return 0; } -late_initcall(vfp_init); +core_initcall(vfp_init); diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index c9770ba5c7df..8a6295c86209 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -170,6 +170,7 @@ static void __init xen_percpu_init(void *unused) per_cpu(xen_vcpu, cpu) = vcpup; enable_percpu_irq(xen_events_irq, 0); + put_cpu(); } static void xen_restart(enum reboot_mode reboot_mode, const char *cmd) |