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-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi66
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi50
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi20
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi22
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts6
-rw-r--r--arch/arm/boot/dts/exynos5422-odroid-core.dtsi10
6 files changed, 97 insertions, 77 deletions
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index c17870a54acf..5659c4a10729 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -126,39 +126,6 @@
};
};
- gpu: gpu@13000000 {
- compatible = "samsung,exynos4210-mali", "arm,mali-400";
- reg = <0x13000000 0x10000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp",
- "gpmmu",
- "pp0",
- "ppmmu0",
- "pp1",
- "ppmmu1",
- "pp2",
- "ppmmu2",
- "pp3",
- "ppmmu3",
- "pmu";
- clocks = <&cmu CLK_G3D>,
- <&cmu CLK_SCLK_G3D>;
- clock-names = "bus", "core";
- power-domains = <&pd_g3d>;
- status = "disabled";
- /* TODO: operating points for DVFS, assigned clock as 134 MHz */
- };
-
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -495,6 +462,39 @@
status = "disabled";
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3",
+ "pmu";
+ clocks = <&cmu CLK_G3D>,
+ <&cmu CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ /* TODO: operating points for DVFS, assigned clock as 134 MHz */
+ };
+
mfc: codec@13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 6005cfbbed89..1264cc431ff6 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -51,42 +51,6 @@
serial3 = &serial_3;
};
- gpu: gpu@13000000 {
- compatible = "samsung,exynos4210-mali", "arm,mali-400";
- reg = <0x13000000 0x10000>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp",
- "gpmmu",
- "pp0",
- "ppmmu0",
- "pp1",
- "ppmmu1",
- "pp2",
- "ppmmu2",
- "pp3",
- "ppmmu3",
- "pmu";
- /*
- * CLK_G3D is not actually bus clock but a IP-level clock.
- * The bus clock is not described in hardware manual.
- */
- clocks = <&clock CLK_G3D>,
- <&clock CLK_SCLK_G3D>;
- clock-names = "bus", "core";
- power-domains = <&pd_g3d>;
- status = "disabled";
- };
-
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
@@ -451,6 +415,20 @@
};
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ /*
+ * CLK_G3D is not actually bus clock but a IP-level clock.
+ * The bus clock is not described in hardware manual.
+ */
+ clocks = <&clock CLK_G3D>,
+ <&clock CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ };
+
i2s1: i2s@13960000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13960000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 6122da368092..f220716239db 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -450,6 +450,26 @@
};
&gpu {
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
operating-points-v2 = <&gpu_opp_table>;
gpu_opp_table: opp_table {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 7bed6842575a..d20db2dfe8e2 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -717,6 +717,28 @@
};
&gpu {
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3",
+ "pmu";
operating-points-v2 = <&gpu_opp_table>;
gpu_opp_table: opp_table {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index ac7f2fa0ba22..592d7b45ecc8 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -723,15 +723,15 @@
buck7_reg: BUCK7 {
regulator-name = "VIN_LLDO_1V4";
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
buck8_reg: BUCK8 {
regulator-name = "VIN_MLDO_2V0";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
regulator-always-on;
};
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 9843d21d6924..829147e320e0 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -551,17 +551,17 @@
};
buck7_reg: BUCK7 {
- regulator-name = "vdd_1.0v_ldo";
- regulator-min-microvolt = <800000>;
+ regulator-name = "vdd_1.35v_ldo";
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
buck8_reg: BUCK8 {
- regulator-name = "vdd_1.8v_ldo";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2000000>;
+ regulator-name = "vdd_2.0v_ldo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
regulator-always-on;
regulator-boot-on;
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 11:35:35 +0100