diff options
Diffstat (limited to 'arch/m68k/coldfire/m527x.c')
| -rw-r--r-- | arch/m68k/coldfire/m527x.c | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/arch/m68k/coldfire/m527x.c b/arch/m68k/coldfire/m527x.c new file mode 100644 index 000000000000..62d81ef016f1 --- /dev/null +++ b/arch/m68k/coldfire/m527x.c @@ -0,0 +1,126 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/527x/config.c + * + * Sub-architcture dependent initialization code for the Freescale + * 5270/5271 CPUs. + * + * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/init.h> +#include <linux/io.h> +#include <asm/machdep.h> +#include <asm/coldfire.h> +#include <asm/mcfsim.h> +#include <asm/mcfuart.h> +#include <asm/mcfclk.h> + +/***************************************************************************/ + +DEFINE_CLK(pll, "pll.0", MCF_CLK); +DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); +DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); +DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); +DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); +DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); +DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); +DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); +DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); +DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); +DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); +DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); + +struct clk *mcf_clks[] = { + &clk_pll, + &clk_sys, + &clk_mcfpit0, + &clk_mcfpit1, + &clk_mcfpit2, + &clk_mcfpit3, + &clk_mcfuart0, + &clk_mcfuart1, + &clk_mcfuart2, + &clk_mcfqspi0, + &clk_fec0, + &clk_fec1, + NULL +}; + +/***************************************************************************/ + +static void __init m527x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) +#if defined(CONFIG_M5271) + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +#elif defined(CONFIG_M5275) + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x003e, MCFGPIO_PAR_QSPI); +#endif +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +static void __init m527x_uarts_init(void) +{ + u16 sepmask; + + /* + * External Pin Mask Setting & Enable External Pin for Interface + */ + sepmask = readw(MCFGPIO_PAR_UART); + sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; + writew(sepmask, MCFGPIO_PAR_UART); +} + +/***************************************************************************/ + +static void __init m527x_fec_init(void) +{ + u16 par; + u8 v; + + /* Set multi-function pins to ethernet mode for fec0 */ +#if defined(CONFIG_M5271) + v = readb(MCFGPIO_PAR_FECI2C); + writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); +#else + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xf00, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC0HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); + + /* Set multi-function pins to ethernet mode for fec1 */ + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xa0, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC1HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); +#endif +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m527x_uarts_init(); + m527x_fec_init(); + m527x_qspi_init(); +} + +/***************************************************************************/ |