diff options
Diffstat (limited to 'arch/mips/include/asm/ip32')
| -rw-r--r-- | arch/mips/include/asm/ip32/crime.h | 8 | ||||
| -rw-r--r-- | arch/mips/include/asm/ip32/ip32_ints.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/ip32/mace.h | 12 |
3 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/include/asm/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h index 7c36b0e5b1c6..16c94a27beba 100644 --- a/arch/mips/include/asm/ip32/crime.h +++ b/arch/mips/include/asm/ip32/crime.h @@ -74,7 +74,7 @@ struct sgi_crime { #define CRIME_RE_IDLE_E_INT BIT(24) #define CRIME_RE_EMPTY_L_INT BIT(25) #define CRIME_RE_FULL_L_INT BIT(26) -#define CRIME_RE_IDLE_L_INT BIT(27) +#define CRIME_RE_IDLE_L_INT BIT(27) #define CRIME_SOFT0_INT BIT(28) #define CRIME_SOFT1_INT BIT(29) #define CRIME_SOFT2_INT BIT(30) @@ -118,7 +118,7 @@ struct sgi_crime { #define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ volatile unsigned long mem_error_stat; -#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ +#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ #define CRIME_MEM_ERROR_MACE_ID 0x0000007f #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 #define CRIME_MEM_ERROR_RE_ID 0x00007f00 @@ -134,8 +134,8 @@ struct sgi_crime { #define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 #define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 #define CRIME_MEM_ERROR_INV 0x0e000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 -#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 +#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 +#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 volatile unsigned long mem_error_addr; diff --git a/arch/mips/include/asm/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h index 85bc5302bce0..72e3368de111 100644 --- a/arch/mips/include/asm/ip32/ip32_ints.h +++ b/arch/mips/include/asm/ip32/ip32_ints.h @@ -13,7 +13,7 @@ /* * This list reflects the assignment of interrupt numbers to - * interrupting events. Order is fairly irrelevant to handling + * interrupting events. Order is fairly irrelevant to handling * priority. This differs from irix. */ diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h index c523123df380..253ed7ea80be 100644 --- a/arch/mips/include/asm/ip32/mace.h +++ b/arch/mips/include/asm/ip32/mace.h @@ -250,12 +250,12 @@ struct mace_ps2 { * -> drivers/i2c/algos/i2c-algo-sgi.c */ struct mace_i2c { volatile unsigned long config; -#define MACEI2C_RESET BIT(0) -#define MACEI2C_FAST BIT(1) -#define MACEI2C_DATA_OVERRIDE BIT(2) -#define MACEI2C_CLOCK_OVERRIDE BIT(3) -#define MACEI2C_DATA_STATUS BIT(4) -#define MACEI2C_CLOCK_STATUS BIT(5) +#define MACEI2C_RESET BIT(0) +#define MACEI2C_FAST BIT(1) +#define MACEI2C_DATA_OVERRIDE BIT(2) +#define MACEI2C_CLOCK_OVERRIDE BIT(3) +#define MACEI2C_DATA_STATUS BIT(4) +#define MACEI2C_CLOCK_STATUS BIT(5) volatile unsigned long control; volatile unsigned long data; }; |