diff options
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/apm.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/entry.S | 6 | ||||
-rw-r--r-- | arch/mips/kernel/gdb-low.S | 4 | ||||
-rw-r--r-- | arch/mips/kernel/genex.S | 2 | ||||
-rw-r--r-- | arch/mips/kernel/head.S | 2 | ||||
-rw-r--r-- | arch/mips/kernel/r4k_switch.S | 6 | ||||
-rw-r--r-- | arch/mips/kernel/scall32-o32.S | 1 | ||||
-rw-r--r-- | arch/mips/kernel/scall64-64.S | 1 | ||||
-rw-r--r-- | arch/mips/kernel/scall64-n32.S | 1 | ||||
-rw-r--r-- | arch/mips/kernel/scall64-o32.S | 1 | ||||
-rw-r--r-- | arch/mips/kernel/setup.c | 3 | ||||
-rw-r--r-- | arch/mips/kernel/smtc-asm.S | 10 | ||||
-rw-r--r-- | arch/mips/kernel/syscall.c | 8 | ||||
-rw-r--r-- | arch/mips/kernel/traps.c | 15 |
15 files changed, 36 insertions, 28 deletions
diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c index 15f46b4471fd..7bdbcd811b57 100644 --- a/arch/mips/kernel/apm.c +++ b/arch/mips/kernel/apm.c @@ -260,7 +260,7 @@ static unsigned int apm_poll(struct file *fp, poll_table * wait) * has acknowledge does the actual suspend happen. */ static int -apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) +apm_ioctl(struct inode * inode, struct file *filp, unsigned int cmd, unsigned long arg) { struct apm_user *as = filp->private_data; unsigned long flags; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8c2c359a05f4..e045aba4ebda 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - /* Probe for L2 cache */ - c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; case PRID_IMP_34K: c->cputype = CPU_34K; diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index a9c6de1b9542..457565162dd5 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame ori v1, v0, TCSTATUS_IXMT mtc0 v1, CP0_TCSTATUS andi v0, TCSTATUS_IXMT - ehb + _ehb mfc0 t0, CP0_TCCONTEXT DMT 9 # dmt t1 jal mips_ihb @@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame andi t3, t0, 0xff00 or t2, t2, t3 mtc0 t2, CP0_STATUS - ehb + _ehb andi t1, t1, VPECONTROL_TE beqz t1, 1f EMT @@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame xori v1, v1, TCSTATUS_IXMT or v1, v0, v1 mtc0 v1, CP0_TCSTATUS - ehb + _ehb xor t0, t0, t3 mtc0 t0, CP0_TCCONTEXT #endif /* CONFIG_MIPS_MT_SMTC */ diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index 5fd7a8af0c62..8760131f89d9 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -291,7 +291,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 9 # dmt t1 jal mips_ihb nop @@ -310,7 +310,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ LONG_L v0, GDB_FR_STATUS(sp) LONG_L v1, GDB_FR_EPC(sp) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index ff7af369f286..6888cde560af 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp) mtc0 t0, CP0_TCCONTEXT xor t1, t1, t0 mtc0 t1, CP0_STATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ CLI move a0, sp diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index bdf6f6eff721..c018098c9a56 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -96,7 +96,7 @@ /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS - ehb + _ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index db94e556fc97..e1b85e6c486a 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -94,7 +94,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 8 # dmt t0 move t1,ra jal mips_ihb @@ -109,7 +109,7 @@ or a2, t1 mtc0 a2, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC - ehb + _ehb andi t0, t0, VPECONTROL_TE beqz t0, 1f emt @@ -118,7 +118,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ move v0, a0 jr ra diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 2d2fdf77e308..6344be46ca8c 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -647,6 +647,7 @@ einval: li v0, -EINVAL sys sys_unshare 1 sys sys_splice 4 sys sys_sync_file_range 7 /* 4305 */ + sys sys_tee 4 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 9ba750887377..12d96c7d0bb2 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -462,3 +462,4 @@ sys_call_table: PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee /* 5265 */ diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 942aca26f9c4..685698554a8a 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -388,3 +388,4 @@ EXPORT(sysn32_call_table) PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 8efb23a84131..0e632934cb76 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -510,4 +510,5 @@ sys_call_table: PTR sys_unshare PTR sys_splice PTR sys32_sync_file_range /* 4305 */ + PTR sys_tee .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index bfcec8d9bfe4..d3e087115023 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -488,6 +488,9 @@ static inline void resource_init(void) { int i; + if (UNCAC_BASE != IO_BASE) + return; + code_resource.start = virt_to_phys(&_text); code_resource.end = virt_to_phys(&_etext) - 1; data_resource.start = virt_to_phys(&_etext); diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index c9d65196d917..72c6d98f8854 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector) .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 - ehb + _ehb /* Set EXL */ mfc0 k0,CP0_STATUS ori k0,k0,ST0_EXL mtc0 k0,CP0_STATUS - ehb + _ehb /* Thread scheduling now inhibited by EXL. Restore TE state. */ andi k1,k1,VPECONTROL_TE beqz k1,1f @@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector) li k1,ST0_CU0 or k1,k1,k0 mtc0 k1,CP0_STATUS - ehb + _ehb get_saved_sp /* Interrupting TC will have pre-set values in slots in the new frame */ 2: subu k1,k1,PT_SIZE @@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector) lw k0,PT_TCSTATUS(k1) /* Write it to TCStatus to restore CU/KSU/IXMT state */ mtc0 k0,$2,1 - ehb + _ehb lw k0,PT_EPC(k1) mtc0 k0,CP0_EPC /* Save all will redundantly recompute the SP, but use it for now */ @@ -116,7 +116,7 @@ LEAF(self_ipi) mfc0 t0,CP0_TCSTATUS ori t1,t0,TCSTATUS_IXMT mtc0 t1,CP0_TCSTATUS - ehb + _ehb /* We know we're in kernel mode, so prepare stack frame */ subu t1,sp,PT_SIZE sw ra,PT_EPC(t1) diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 5e8a18a8e2bd..6da8c68e89db 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -301,7 +301,7 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) * * This is really horribly ugly. */ -asmlinkage int sys_ipc (uint call, int first, int second, +asmlinkage int sys_ipc (unsigned int call, int first, int second, unsigned long third, void __user *ptr, long fifth) { int version, ret; @@ -359,18 +359,18 @@ asmlinkage int sys_ipc (uint call, int first, int second, case SHMAT: switch (version) { default: { - ulong raddr; + unsigned long raddr; ret = do_shmat (first, (char __user *) ptr, second, &raddr); if (ret) return ret; - return put_user (raddr, (ulong __user *) third); + return put_user (raddr, (unsigned long __user *) third); } case 1: /* iBCS2 emulator entry point */ if (!segment_eq(get_fs(), get_ds())) return -EINVAL; return do_shmat (first, (char __user *) ptr, second, - (ulong *) third); + (unsigned long *) third); } case SHMDT: return sys_shmdt ((char __user *)ptr); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad16eceb24dd..67971938a2cb 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr) return (void *)old_handler; } -#ifdef CONFIG_CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2_SRS /* * MIPSR2 shadow register set allocation * FIXME: SMP... @@ -1069,11 +1069,9 @@ static struct shadow_registers { static void mips_srs_init(void) { -#ifdef CONFIG_CPU_MIPSR2_SRS shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; printk(KERN_INFO "%d MIPSR2 register sets available\n", shadow_registers.sr_supported); -#endif shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ } @@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr) { return set_vi_srs_handler(n, addr, 0); } -#endif + +#else + +static inline void mips_srs_init(void) +{ +} + +#endif /* CONFIG_CPU_MIPSR2_SRS */ /* * This is used by native signal handling @@ -1388,9 +1393,7 @@ void __init trap_init(void) else ebase = CAC_BASE; -#ifdef CONFIG_CPU_MIPSR2 mips_srs_init(); -#endif per_cpu_trap_init(); |